arm-cpu-cdata.h revision 1.1.1.2
1 /* This file is automatically generated. DO NOT EDIT! */ 2 /* Generated from: NetBSD: mknative-gcc,v 1.108 2020/09/05 10:58:08 mrg Exp */ 3 /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */ 4 5 /* -*- buffer-read-only: t -*- 6 Generated automatically by parsecpu.awk from arm-cpus.in. 7 Do not edit. 8 9 Copyright (C) 2011-2019 Free Software Foundation, Inc. 10 11 This file is part of GCC. 12 13 GCC is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as 15 published by the Free Software Foundation; either version 3, 16 or (at your option) any later version. 17 18 GCC is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public 24 License along with GCC; see the file COPYING3. If not see 25 <http://www.gnu.org/licenses/>. */ 26 27 static const cpu_alias cpu_aliastab_strongarm[] = { 28 { "strongarm110", true}, 29 { "strongarm1100", false}, 30 { "strongarm1110", false}, 31 { NULL, false} 32 }; 33 34 static const cpu_alias cpu_aliastab_arm7tdmi[] = { 35 { "arm7tdmi-s", true}, 36 { NULL, false} 37 }; 38 39 static const cpu_alias cpu_aliastab_arm710t[] = { 40 { "arm720t", true}, 41 { "arm740t", true}, 42 { NULL, false} 43 }; 44 45 static const cpu_alias cpu_aliastab_arm920t[] = { 46 { "arm920", true}, 47 { "arm922t", true}, 48 { "arm940t", true}, 49 { "ep9312", true}, 50 { NULL, false} 51 }; 52 53 static const cpu_alias cpu_aliastab_arm10tdmi[] = { 54 { "arm1020t", true}, 55 { NULL, false} 56 }; 57 58 static const cpu_arch_extension cpu_opttab_arm9e[] = { 59 { 60 "nofp", true, false, 61 { 62 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 63 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 64 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 65 } 66 }, 67 { NULL, false, false, {isa_nobit}} 68 }; 69 70 static const cpu_alias cpu_aliastab_arm9e[] = { 71 { "arm946e-s", true}, 72 { "arm966e-s", true}, 73 { "arm968e-s", true}, 74 { NULL, false} 75 }; 76 77 static const cpu_arch_extension cpu_opttab_arm10e[] = { 78 { 79 "nofp", true, false, 80 { 81 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 82 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 83 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 84 } 85 }, 86 { NULL, false, false, {isa_nobit}} 87 }; 88 89 static const cpu_alias cpu_aliastab_arm10e[] = { 90 { "arm1020e", true}, 91 { "arm1022e", true}, 92 { NULL, false} 93 }; 94 95 static const cpu_arch_extension cpu_opttab_arm926ejs[] = { 96 { 97 "nofp", true, false, 98 { 99 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 100 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 101 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 102 } 103 }, 104 { NULL, false, false, {isa_nobit}} 105 }; 106 107 static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { 108 { 109 "nofp", true, false, 110 { 111 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 112 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 113 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 114 } 115 }, 116 { NULL, false, false, {isa_nobit}} 117 }; 118 119 static const cpu_arch_extension cpu_opttab_genericv7a[] = { 120 { 121 "mp", false, false, 122 { 123 isa_bit_mp, isa_nobit 124 } 125 }, 126 { 127 "sec", false, false, 128 { 129 isa_bit_sec, isa_nobit 130 } 131 }, 132 { 133 "vfpv3-d16", false, false, 134 { 135 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 136 } 137 }, 138 { 139 "vfpv3", false, false, 140 { 141 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 142 isa_nobit 143 } 144 }, 145 { 146 "vfpv3-d16-fp16", false, false, 147 { 148 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 149 isa_nobit 150 } 151 }, 152 { 153 "vfpv3-fp16", false, false, 154 { 155 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 156 isa_bit_fp_dbl, isa_nobit 157 } 158 }, 159 { 160 "vfpv4-d16", false, false, 161 { 162 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 163 isa_bit_fp_dbl, isa_nobit 164 } 165 }, 166 { 167 "vfpv4", false, false, 168 { 169 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 170 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 171 } 172 }, 173 { 174 "simd", false, false, 175 { 176 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 177 isa_bit_fp_dbl, isa_nobit 178 } 179 }, 180 { 181 "neon-fp16", false, false, 182 { 183 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 184 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 185 } 186 }, 187 { 188 "neon-vfpv4", false, false, 189 { 190 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 191 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 192 } 193 }, 194 { 195 "nosimd", true, false, 196 { 197 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 198 isa_bit_crypto, isa_nobit 199 } 200 }, 201 { 202 "nofp", true, false, 203 { 204 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 205 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 206 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 207 } 208 }, 209 { 210 "neon", false, true, 211 { 212 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 213 isa_bit_fp_dbl, isa_nobit 214 } 215 }, 216 { 217 "neon-vfpv3", false, true, 218 { 219 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 220 isa_bit_fp_dbl, isa_nobit 221 } 222 }, 223 { NULL, false, false, {isa_nobit}} 224 }; 225 226 static const cpu_arch_extension cpu_opttab_cortexa5[] = { 227 { 228 "nosimd", true, false, 229 { 230 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 231 isa_bit_crypto, isa_nobit 232 } 233 }, 234 { 235 "nofp", true, false, 236 { 237 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 238 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 239 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 240 } 241 }, 242 { NULL, false, false, {isa_nobit}} 243 }; 244 245 static const cpu_arch_extension cpu_opttab_cortexa7[] = { 246 { 247 "nosimd", true, false, 248 { 249 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 250 isa_bit_crypto, isa_nobit 251 } 252 }, 253 { 254 "nofp", true, false, 255 { 256 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 257 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 258 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 259 } 260 }, 261 { NULL, false, false, {isa_nobit}} 262 }; 263 264 static const cpu_arch_extension cpu_opttab_cortexa8[] = { 265 { 266 "nofp", true, false, 267 { 268 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 269 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 270 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 271 } 272 }, 273 { NULL, false, false, {isa_nobit}} 274 }; 275 276 static const cpu_arch_extension cpu_opttab_cortexa9[] = { 277 { 278 "nosimd", true, false, 279 { 280 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 281 isa_bit_crypto, isa_nobit 282 } 283 }, 284 { 285 "nofp", true, false, 286 { 287 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 288 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 289 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 290 } 291 }, 292 { NULL, false, false, {isa_nobit}} 293 }; 294 295 static const cpu_arch_extension cpu_opttab_cortexa12[] = { 296 { 297 "nofp", true, false, 298 { 299 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 300 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 301 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 302 } 303 }, 304 { NULL, false, false, {isa_nobit}} 305 }; 306 307 static const cpu_arch_extension cpu_opttab_cortexa15[] = { 308 { 309 "nofp", true, false, 310 { 311 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 312 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 313 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 314 } 315 }, 316 { NULL, false, false, {isa_nobit}} 317 }; 318 319 static const cpu_arch_extension cpu_opttab_cortexa17[] = { 320 { 321 "nofp", true, false, 322 { 323 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 324 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 325 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 326 } 327 }, 328 { NULL, false, false, {isa_nobit}} 329 }; 330 331 static const cpu_arch_extension cpu_opttab_cortexr5[] = { 332 { 333 "nofp.dp", true, false, 334 { 335 isa_bit_fp_dbl, isa_nobit 336 } 337 }, 338 { 339 "nofp", true, false, 340 { 341 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 342 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 343 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 344 } 345 }, 346 { NULL, false, false, {isa_nobit}} 347 }; 348 349 static const cpu_arch_extension cpu_opttab_cortexr7[] = { 350 { 351 "nofp.dp", true, false, 352 { 353 isa_bit_fp_dbl, isa_nobit 354 } 355 }, 356 { 357 "nofp", true, false, 358 { 359 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 360 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 361 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 362 } 363 }, 364 { NULL, false, false, {isa_nobit}} 365 }; 366 367 static const cpu_arch_extension cpu_opttab_cortexr8[] = { 368 { 369 "nofp.dp", true, false, 370 { 371 isa_bit_fp_dbl, isa_nobit 372 } 373 }, 374 { 375 "nofp", true, false, 376 { 377 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 378 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 379 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 380 } 381 }, 382 { NULL, false, false, {isa_nobit}} 383 }; 384 385 static const cpu_arch_extension cpu_opttab_cortexm7[] = { 386 { 387 "nofp.dp", true, false, 388 { 389 isa_bit_fp_dbl, isa_nobit 390 } 391 }, 392 { 393 "nofp", true, false, 394 { 395 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 396 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 397 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 398 } 399 }, 400 { NULL, false, false, {isa_nobit}} 401 }; 402 403 static const cpu_arch_extension cpu_opttab_cortexm4[] = { 404 { 405 "nofp", true, false, 406 { 407 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 408 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 409 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 410 } 411 }, 412 { NULL, false, false, {isa_nobit}} 413 }; 414 415 static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { 416 { 417 "nofp", true, false, 418 { 419 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 420 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 421 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 422 } 423 }, 424 { NULL, false, false, {isa_nobit}} 425 }; 426 427 static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { 428 { 429 "nofp", true, false, 430 { 431 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 432 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 433 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 434 } 435 }, 436 { NULL, false, false, {isa_nobit}} 437 }; 438 439 static const cpu_arch_extension cpu_opttab_cortexa32[] = { 440 { 441 "crypto", false, false, 442 { 443 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 444 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 445 isa_bit_fp_dbl, isa_nobit 446 } 447 }, 448 { 449 "nofp", true, false, 450 { 451 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 452 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 453 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 454 } 455 }, 456 { NULL, false, false, {isa_nobit}} 457 }; 458 459 static const cpu_arch_extension cpu_opttab_cortexa35[] = { 460 { 461 "crypto", false, false, 462 { 463 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 464 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 465 isa_bit_fp_dbl, isa_nobit 466 } 467 }, 468 { 469 "nofp", true, false, 470 { 471 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 472 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 473 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 474 } 475 }, 476 { NULL, false, false, {isa_nobit}} 477 }; 478 479 static const cpu_arch_extension cpu_opttab_cortexa53[] = { 480 { 481 "crypto", false, false, 482 { 483 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 484 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 485 isa_bit_fp_dbl, isa_nobit 486 } 487 }, 488 { 489 "nofp", true, false, 490 { 491 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 492 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 493 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 494 } 495 }, 496 { NULL, false, false, {isa_nobit}} 497 }; 498 499 static const cpu_arch_extension cpu_opttab_cortexa57[] = { 500 { 501 "crypto", false, false, 502 { 503 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 504 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 505 isa_bit_fp_dbl, isa_nobit 506 } 507 }, 508 { NULL, false, false, {isa_nobit}} 509 }; 510 511 static const cpu_arch_extension cpu_opttab_cortexa72[] = { 512 { 513 "crypto", false, false, 514 { 515 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 516 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 517 isa_bit_fp_dbl, isa_nobit 518 } 519 }, 520 { NULL, false, false, {isa_nobit}} 521 }; 522 523 static const cpu_arch_extension cpu_opttab_cortexa73[] = { 524 { 525 "crypto", false, false, 526 { 527 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 528 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 529 isa_bit_fp_dbl, isa_nobit 530 } 531 }, 532 { NULL, false, false, {isa_nobit}} 533 }; 534 535 static const cpu_arch_extension cpu_opttab_exynosm1[] = { 536 { 537 "crypto", false, false, 538 { 539 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 540 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 541 isa_bit_fp_dbl, isa_nobit 542 } 543 }, 544 { NULL, false, false, {isa_nobit}} 545 }; 546 547 static const cpu_arch_extension cpu_opttab_xgene1[] = { 548 { 549 "crypto", false, false, 550 { 551 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 552 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 553 isa_bit_fp_dbl, isa_nobit 554 } 555 }, 556 { NULL, false, false, {isa_nobit}} 557 }; 558 559 static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { 560 { 561 "crypto", false, false, 562 { 563 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 564 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 565 isa_bit_fp_dbl, isa_nobit 566 } 567 }, 568 { NULL, false, false, {isa_nobit}} 569 }; 570 571 static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { 572 { 573 "crypto", false, false, 574 { 575 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 576 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 577 isa_bit_fp_dbl, isa_nobit 578 } 579 }, 580 { NULL, false, false, {isa_nobit}} 581 }; 582 583 static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { 584 { 585 "crypto", false, false, 586 { 587 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 588 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 589 isa_bit_fp_dbl, isa_nobit 590 } 591 }, 592 { NULL, false, false, {isa_nobit}} 593 }; 594 595 static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { 596 { 597 "crypto", false, false, 598 { 599 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 600 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 601 isa_bit_fp_dbl, isa_nobit 602 } 603 }, 604 { NULL, false, false, {isa_nobit}} 605 }; 606 607 static const cpu_arch_extension cpu_opttab_cortexa55[] = { 608 { 609 "crypto", false, false, 610 { 611 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 612 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 613 isa_bit_fp_dbl, isa_nobit 614 } 615 }, 616 { 617 "nofp", true, false, 618 { 619 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 620 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 621 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 622 } 623 }, 624 { NULL, false, false, {isa_nobit}} 625 }; 626 627 static const cpu_arch_extension cpu_opttab_cortexa75[] = { 628 { 629 "crypto", false, false, 630 { 631 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 632 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 633 isa_bit_fp_dbl, isa_nobit 634 } 635 }, 636 { NULL, false, false, {isa_nobit}} 637 }; 638 639 static const cpu_arch_extension cpu_opttab_cortexa76[] = { 640 { 641 "crypto", false, false, 642 { 643 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 644 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 645 isa_bit_fp_dbl, isa_nobit 646 } 647 }, 648 { NULL, false, false, {isa_nobit}} 649 }; 650 651 static const cpu_arch_extension cpu_opttab_neoversen1[] = { 652 { 653 "crypto", false, false, 654 { 655 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 656 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 657 isa_bit_fp_dbl, isa_nobit 658 } 659 }, 660 { NULL, false, false, {isa_nobit}} 661 }; 662 663 static const cpu_alias cpu_aliastab_neoversen1[] = { 664 { "ares", false}, 665 { NULL, false} 666 }; 667 668 static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = { 669 { 670 "crypto", false, false, 671 { 672 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 673 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 674 isa_bit_fp_dbl, isa_nobit 675 } 676 }, 677 { NULL, false, false, {isa_nobit}} 678 }; 679 680 static const cpu_arch_extension cpu_opttab_cortexa76cortexa55[] = { 681 { 682 "crypto", false, false, 683 { 684 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 685 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 686 isa_bit_fp_dbl, isa_nobit 687 } 688 }, 689 { NULL, false, false, {isa_nobit}} 690 }; 691 692 static const cpu_arch_extension cpu_opttab_cortexm33[] = { 693 { 694 "nofp", true, false, 695 { 696 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 697 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 698 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 699 } 700 }, 701 { 702 "nodsp", true, false, 703 { 704 isa_bit_armv7em, isa_nobit 705 } 706 }, 707 { NULL, false, false, {isa_nobit}} 708 }; 709 710 static const cpu_arch_extension cpu_opttab_cortexr52[] = { 711 { 712 "nofp.dp", true, false, 713 { 714 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 715 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 716 } 717 }, 718 { NULL, false, false, {isa_nobit}} 719 }; 720 721 const cpu_option all_cores[] = 722 { 723 { 724 { 725 "arm8", 726 NULL, 727 { 728 isa_bit_armv4, isa_bit_notm, isa_nobit 729 } 730 }, 731 NULL, 732 TARGET_ARCH_armv4 733 }, 734 { 735 { 736 "arm810", 737 NULL, 738 { 739 isa_bit_armv4, isa_bit_notm, isa_nobit 740 } 741 }, 742 NULL, 743 TARGET_ARCH_armv4 744 }, 745 { 746 { 747 "strongarm", 748 NULL, 749 { 750 isa_bit_armv4, isa_bit_notm, isa_nobit 751 } 752 }, 753 cpu_aliastab_strongarm, 754 TARGET_ARCH_armv4 755 }, 756 { 757 { 758 "fa526", 759 NULL, 760 { 761 isa_bit_armv4, isa_bit_notm, isa_nobit 762 } 763 }, 764 NULL, 765 TARGET_ARCH_armv4 766 }, 767 { 768 { 769 "fa626", 770 NULL, 771 { 772 isa_bit_armv4, isa_bit_notm, isa_nobit 773 } 774 }, 775 NULL, 776 TARGET_ARCH_armv4 777 }, 778 { 779 { 780 "arm7tdmi", 781 NULL, 782 { 783 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 784 } 785 }, 786 cpu_aliastab_arm7tdmi, 787 TARGET_ARCH_armv4t 788 }, 789 { 790 { 791 "arm710t", 792 NULL, 793 { 794 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 795 } 796 }, 797 cpu_aliastab_arm710t, 798 TARGET_ARCH_armv4t 799 }, 800 { 801 { 802 "arm9", 803 NULL, 804 { 805 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 806 } 807 }, 808 NULL, 809 TARGET_ARCH_armv4t 810 }, 811 { 812 { 813 "arm9tdmi", 814 NULL, 815 { 816 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 817 } 818 }, 819 NULL, 820 TARGET_ARCH_armv4t 821 }, 822 { 823 { 824 "arm920t", 825 NULL, 826 { 827 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 828 } 829 }, 830 cpu_aliastab_arm920t, 831 TARGET_ARCH_armv4t 832 }, 833 { 834 { 835 "arm10tdmi", 836 NULL, 837 { 838 isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 839 isa_nobit 840 } 841 }, 842 cpu_aliastab_arm10tdmi, 843 TARGET_ARCH_armv5t 844 }, 845 { 846 { 847 "arm9e", 848 cpu_opttab_arm9e, 849 { 850 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 851 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 852 } 853 }, 854 cpu_aliastab_arm9e, 855 TARGET_ARCH_armv5te 856 }, 857 { 858 { 859 "arm10e", 860 cpu_opttab_arm10e, 861 { 862 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 863 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 864 } 865 }, 866 cpu_aliastab_arm10e, 867 TARGET_ARCH_armv5te 868 }, 869 { 870 { 871 "xscale", 872 NULL, 873 { 874 isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, isa_bit_armv5t, 875 isa_bit_armv4, isa_bit_notm, isa_nobit 876 } 877 }, 878 NULL, 879 TARGET_ARCH_armv5te 880 }, 881 { 882 { 883 "iwmmxt", 884 NULL, 885 { 886 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 887 isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 888 } 889 }, 890 NULL, 891 TARGET_ARCH_iwmmxt 892 }, 893 { 894 { 895 "iwmmxt2", 896 NULL, 897 { 898 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 899 isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 900 isa_nobit 901 } 902 }, 903 NULL, 904 TARGET_ARCH_iwmmxt2 905 }, 906 { 907 { 908 "fa606te", 909 NULL, 910 { 911 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 912 isa_bit_notm, isa_nobit 913 } 914 }, 915 NULL, 916 TARGET_ARCH_armv5te 917 }, 918 { 919 { 920 "fa626te", 921 NULL, 922 { 923 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 924 isa_bit_notm, isa_nobit 925 } 926 }, 927 NULL, 928 TARGET_ARCH_armv5te 929 }, 930 { 931 { 932 "fmp626", 933 NULL, 934 { 935 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 936 isa_bit_notm, isa_nobit 937 } 938 }, 939 NULL, 940 TARGET_ARCH_armv5te 941 }, 942 { 943 { 944 "fa726te", 945 NULL, 946 { 947 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 948 isa_bit_notm, isa_nobit 949 } 950 }, 951 NULL, 952 TARGET_ARCH_armv5te 953 }, 954 { 955 { 956 "arm926ej-s", 957 cpu_opttab_arm926ejs, 958 { 959 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 960 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 961 } 962 }, 963 NULL, 964 TARGET_ARCH_armv5tej 965 }, 966 { 967 { 968 "arm1026ej-s", 969 cpu_opttab_arm1026ejs, 970 { 971 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 972 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 973 } 974 }, 975 NULL, 976 TARGET_ARCH_armv5tej 977 }, 978 { 979 { 980 "arm1136j-s", 981 NULL, 982 { 983 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 984 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 985 } 986 }, 987 NULL, 988 TARGET_ARCH_armv6j 989 }, 990 { 991 { 992 "arm1136jf-s", 993 NULL, 994 { 995 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 996 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 997 isa_bit_fp_dbl, isa_nobit 998 } 999 }, 1000 NULL, 1001 TARGET_ARCH_armv6j 1002 }, 1003 { 1004 { 1005 "arm1176jz-s", 1006 NULL, 1007 { 1008 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1009 isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 1010 isa_bit_armv6k, isa_nobit 1011 } 1012 }, 1013 NULL, 1014 TARGET_ARCH_armv6kz 1015 }, 1016 { 1017 { 1018 "arm1176jzf-s", 1019 NULL, 1020 { 1021 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1022 isa_bit_armv5t, isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, 1023 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1024 } 1025 }, 1026 NULL, 1027 TARGET_ARCH_armv6kz 1028 }, 1029 { 1030 { 1031 "mpcorenovfp", 1032 NULL, 1033 { 1034 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1035 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 1036 isa_nobit 1037 } 1038 }, 1039 NULL, 1040 TARGET_ARCH_armv6k 1041 }, 1042 { 1043 { 1044 "mpcore", 1045 NULL, 1046 { 1047 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1048 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 1049 isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1050 } 1051 }, 1052 NULL, 1053 TARGET_ARCH_armv6k 1054 }, 1055 { 1056 { 1057 "arm1156t2-s", 1058 NULL, 1059 { 1060 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1061 isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 1062 isa_nobit 1063 } 1064 }, 1065 NULL, 1066 TARGET_ARCH_armv6t2 1067 }, 1068 { 1069 { 1070 "arm1156t2f-s", 1071 NULL, 1072 { 1073 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1074 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, 1075 isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1076 } 1077 }, 1078 NULL, 1079 TARGET_ARCH_armv6t2 1080 }, 1081 { 1082 { 1083 "cortex-m1", 1084 NULL, 1085 { 1086 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1087 isa_bit_armv4, isa_bit_armv6, isa_nobit 1088 } 1089 }, 1090 NULL, 1091 TARGET_ARCH_armv6s_m 1092 }, 1093 { 1094 { 1095 "cortex-m0", 1096 NULL, 1097 { 1098 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1099 isa_bit_armv4, isa_bit_armv6, isa_nobit 1100 } 1101 }, 1102 NULL, 1103 TARGET_ARCH_armv6s_m 1104 }, 1105 { 1106 { 1107 "cortex-m0plus", 1108 NULL, 1109 { 1110 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1111 isa_bit_armv4, isa_bit_armv6, isa_nobit 1112 } 1113 }, 1114 NULL, 1115 TARGET_ARCH_armv6s_m 1116 }, 1117 { 1118 { 1119 "cortex-m1.small-multiply", 1120 NULL, 1121 { 1122 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1123 isa_bit_armv4, isa_bit_armv6, isa_nobit 1124 } 1125 }, 1126 NULL, 1127 TARGET_ARCH_armv6s_m 1128 }, 1129 { 1130 { 1131 "cortex-m0.small-multiply", 1132 NULL, 1133 { 1134 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1135 isa_bit_armv4, isa_bit_armv6, isa_nobit 1136 } 1137 }, 1138 NULL, 1139 TARGET_ARCH_armv6s_m 1140 }, 1141 { 1142 { 1143 "cortex-m0plus.small-multiply", 1144 NULL, 1145 { 1146 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1147 isa_bit_armv4, isa_bit_armv6, isa_nobit 1148 } 1149 }, 1150 NULL, 1151 TARGET_ARCH_armv6s_m 1152 }, 1153 { 1154 { 1155 "generic-armv7-a", 1156 cpu_opttab_genericv7a, 1157 { 1158 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1159 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1160 isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 1161 isa_bit_fp_dbl, isa_nobit 1162 } 1163 }, 1164 NULL, 1165 TARGET_ARCH_armv7_a 1166 }, 1167 { 1168 { 1169 "cortex-a5", 1170 cpu_opttab_cortexa5, 1171 { 1172 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1173 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1174 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1175 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1176 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1177 } 1178 }, 1179 NULL, 1180 TARGET_ARCH_armv7_a 1181 }, 1182 { 1183 { 1184 "cortex-a7", 1185 cpu_opttab_cortexa7, 1186 { 1187 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1188 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1189 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1190 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1191 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1192 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1193 } 1194 }, 1195 NULL, 1196 TARGET_ARCH_armv7ve 1197 }, 1198 { 1199 { 1200 "cortex-a8", 1201 cpu_opttab_cortexa8, 1202 { 1203 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1204 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1205 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1206 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_sec, 1207 isa_nobit 1208 } 1209 }, 1210 NULL, 1211 TARGET_ARCH_armv7_a 1212 }, 1213 { 1214 { 1215 "cortex-a9", 1216 cpu_opttab_cortexa9, 1217 { 1218 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1219 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1220 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1221 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1222 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1223 } 1224 }, 1225 NULL, 1226 TARGET_ARCH_armv7_a 1227 }, 1228 { 1229 { 1230 "cortex-a12", 1231 cpu_opttab_cortexa12, 1232 { 1233 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1234 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1235 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1236 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1237 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1238 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1239 } 1240 }, 1241 NULL, 1242 TARGET_ARCH_armv7ve 1243 }, 1244 { 1245 { 1246 "cortex-a15", 1247 cpu_opttab_cortexa15, 1248 { 1249 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1250 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1251 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1252 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1253 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1254 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1255 } 1256 }, 1257 NULL, 1258 TARGET_ARCH_armv7ve 1259 }, 1260 { 1261 { 1262 "cortex-a17", 1263 cpu_opttab_cortexa17, 1264 { 1265 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1266 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1267 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1268 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1269 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1270 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1271 } 1272 }, 1273 NULL, 1274 TARGET_ARCH_armv7ve 1275 }, 1276 { 1277 { 1278 "cortex-r4", 1279 NULL, 1280 { 1281 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1282 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 1283 isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 1284 } 1285 }, 1286 NULL, 1287 TARGET_ARCH_armv7_r 1288 }, 1289 { 1290 { 1291 "cortex-r4f", 1292 NULL, 1293 { 1294 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1295 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1296 isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 1297 isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1298 } 1299 }, 1300 NULL, 1301 TARGET_ARCH_armv7_r 1302 }, 1303 { 1304 { 1305 "cortex-r5", 1306 cpu_opttab_cortexr5, 1307 { 1308 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1309 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1310 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1311 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1312 } 1313 }, 1314 NULL, 1315 TARGET_ARCH_armv7_r 1316 }, 1317 { 1318 { 1319 "cortex-r7", 1320 cpu_opttab_cortexr7, 1321 { 1322 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1323 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1324 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1325 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1326 isa_nobit 1327 } 1328 }, 1329 NULL, 1330 TARGET_ARCH_armv7_r 1331 }, 1332 { 1333 { 1334 "cortex-r8", 1335 cpu_opttab_cortexr8, 1336 { 1337 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1338 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1339 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1340 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1341 isa_nobit 1342 } 1343 }, 1344 NULL, 1345 TARGET_ARCH_armv7_r 1346 }, 1347 { 1348 { 1349 "cortex-m7", 1350 cpu_opttab_cortexm7, 1351 { 1352 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1353 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1354 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5, 1355 isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_thumb2, isa_bit_fp16conv, 1356 isa_bit_fp_dbl, isa_nobit 1357 } 1358 }, 1359 NULL, 1360 TARGET_ARCH_armv7e_m 1361 }, 1362 { 1363 { 1364 "cortex-m4", 1365 cpu_opttab_cortexm4, 1366 { 1367 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1368 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1369 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv, 1370 isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 1371 } 1372 }, 1373 NULL, 1374 TARGET_ARCH_armv7e_m 1375 }, 1376 { 1377 { 1378 "cortex-m3", 1379 NULL, 1380 { 1381 isa_bit_armv5te, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8, 1382 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, 1383 isa_bit_tdiv, isa_bit_thumb2, isa_nobit 1384 } 1385 }, 1386 NULL, 1387 TARGET_ARCH_armv7_m 1388 }, 1389 { 1390 { 1391 "marvell-pj4", 1392 NULL, 1393 { 1394 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1395 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 1396 isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 1397 isa_nobit 1398 } 1399 }, 1400 NULL, 1401 TARGET_ARCH_armv7_a 1402 }, 1403 { 1404 { 1405 "cortex-a15.cortex-a7", 1406 cpu_opttab_cortexa15cortexa7, 1407 { 1408 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1409 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1410 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1411 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1412 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1413 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1414 } 1415 }, 1416 NULL, 1417 TARGET_ARCH_armv7ve 1418 }, 1419 { 1420 { 1421 "cortex-a17.cortex-a7", 1422 cpu_opttab_cortexa17cortexa7, 1423 { 1424 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1425 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1426 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1427 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1428 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1429 isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1430 } 1431 }, 1432 NULL, 1433 TARGET_ARCH_armv7ve 1434 }, 1435 { 1436 { 1437 "cortex-a32", 1438 cpu_opttab_cortexa32, 1439 { 1440 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1441 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1442 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1443 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1444 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1445 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1446 isa_bit_sec, isa_nobit 1447 } 1448 }, 1449 NULL, 1450 TARGET_ARCH_armv8_a 1451 }, 1452 { 1453 { 1454 "cortex-a35", 1455 cpu_opttab_cortexa35, 1456 { 1457 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1458 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1459 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1460 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1461 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1462 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1463 isa_bit_sec, isa_nobit 1464 } 1465 }, 1466 NULL, 1467 TARGET_ARCH_armv8_a 1468 }, 1469 { 1470 { 1471 "cortex-a53", 1472 cpu_opttab_cortexa53, 1473 { 1474 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1475 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1476 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1477 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1478 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1479 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1480 isa_bit_sec, isa_nobit 1481 } 1482 }, 1483 NULL, 1484 TARGET_ARCH_armv8_a 1485 }, 1486 { 1487 { 1488 "cortex-a57", 1489 cpu_opttab_cortexa57, 1490 { 1491 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1492 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1493 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1494 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1495 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1496 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1497 isa_bit_sec, isa_nobit 1498 } 1499 }, 1500 NULL, 1501 TARGET_ARCH_armv8_a 1502 }, 1503 { 1504 { 1505 "cortex-a72", 1506 cpu_opttab_cortexa72, 1507 { 1508 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1509 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1510 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1511 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1512 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1513 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1514 isa_bit_sec, isa_nobit 1515 } 1516 }, 1517 NULL, 1518 TARGET_ARCH_armv8_a 1519 }, 1520 { 1521 { 1522 "cortex-a73", 1523 cpu_opttab_cortexa73, 1524 { 1525 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1526 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1527 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1528 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1529 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1530 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1531 isa_bit_sec, isa_nobit 1532 } 1533 }, 1534 NULL, 1535 TARGET_ARCH_armv8_a 1536 }, 1537 { 1538 { 1539 "exynos-m1", 1540 cpu_opttab_exynosm1, 1541 { 1542 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1543 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1544 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1545 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1546 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1547 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1548 isa_bit_sec, isa_nobit 1549 } 1550 }, 1551 NULL, 1552 TARGET_ARCH_armv8_a 1553 }, 1554 { 1555 { 1556 "xgene1", 1557 cpu_opttab_xgene1, 1558 { 1559 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1560 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1561 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1562 isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, 1563 isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, 1564 isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, 1565 isa_nobit 1566 } 1567 }, 1568 NULL, 1569 TARGET_ARCH_armv8_a 1570 }, 1571 { 1572 { 1573 "cortex-a57.cortex-a53", 1574 cpu_opttab_cortexa57cortexa53, 1575 { 1576 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1577 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1578 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1579 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1580 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1581 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1582 isa_bit_sec, isa_nobit 1583 } 1584 }, 1585 NULL, 1586 TARGET_ARCH_armv8_a 1587 }, 1588 { 1589 { 1590 "cortex-a72.cortex-a53", 1591 cpu_opttab_cortexa72cortexa53, 1592 { 1593 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1594 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1595 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1596 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1597 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1598 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1599 isa_bit_sec, isa_nobit 1600 } 1601 }, 1602 NULL, 1603 TARGET_ARCH_armv8_a 1604 }, 1605 { 1606 { 1607 "cortex-a73.cortex-a35", 1608 cpu_opttab_cortexa73cortexa35, 1609 { 1610 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1611 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1612 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1613 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1614 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1615 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1616 isa_bit_sec, isa_nobit 1617 } 1618 }, 1619 NULL, 1620 TARGET_ARCH_armv8_a 1621 }, 1622 { 1623 { 1624 "cortex-a73.cortex-a53", 1625 cpu_opttab_cortexa73cortexa53, 1626 { 1627 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1628 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1629 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1630 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1631 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1632 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1633 isa_bit_sec, isa_nobit 1634 } 1635 }, 1636 NULL, 1637 TARGET_ARCH_armv8_a 1638 }, 1639 { 1640 { 1641 "cortex-a55", 1642 cpu_opttab_cortexa55, 1643 { 1644 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1645 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1646 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1647 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1648 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1649 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1650 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1651 isa_bit_sec, isa_nobit 1652 } 1653 }, 1654 NULL, 1655 TARGET_ARCH_armv8_2_a 1656 }, 1657 { 1658 { 1659 "cortex-a75", 1660 cpu_opttab_cortexa75, 1661 { 1662 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1663 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1664 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1665 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1666 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1667 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1668 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1669 isa_bit_sec, isa_nobit 1670 } 1671 }, 1672 NULL, 1673 TARGET_ARCH_armv8_2_a 1674 }, 1675 { 1676 { 1677 "cortex-a76", 1678 cpu_opttab_cortexa76, 1679 { 1680 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1681 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1682 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1683 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1684 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1685 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1686 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1687 isa_bit_sec, isa_nobit 1688 } 1689 }, 1690 NULL, 1691 TARGET_ARCH_armv8_2_a 1692 }, 1693 { 1694 { 1695 "neoverse-n1", 1696 cpu_opttab_neoversen1, 1697 { 1698 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1699 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1700 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1701 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1702 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1703 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1704 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1705 isa_bit_sec, isa_nobit 1706 } 1707 }, 1708 cpu_aliastab_neoversen1, 1709 TARGET_ARCH_armv8_2_a 1710 }, 1711 { 1712 { 1713 "cortex-a75.cortex-a55", 1714 cpu_opttab_cortexa75cortexa55, 1715 { 1716 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1717 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1718 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1719 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1720 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1721 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1722 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1723 isa_bit_sec, isa_nobit 1724 } 1725 }, 1726 NULL, 1727 TARGET_ARCH_armv8_2_a 1728 }, 1729 { 1730 { 1731 "cortex-a76.cortex-a55", 1732 cpu_opttab_cortexa76cortexa55, 1733 { 1734 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1735 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1736 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1737 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1738 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1739 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1740 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1741 isa_bit_sec, isa_nobit 1742 } 1743 }, 1744 NULL, 1745 TARGET_ARCH_armv8_2_a 1746 }, 1747 { 1748 { 1749 "cortex-m23", 1750 NULL, 1751 { 1752 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1753 isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 1754 isa_bit_tdiv, isa_nobit 1755 } 1756 }, 1757 NULL, 1758 TARGET_ARCH_armv8_m_base 1759 }, 1760 { 1761 { 1762 "cortex-m33", 1763 cpu_opttab_cortexm33, 1764 { 1765 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1766 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1767 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_cmse, 1768 isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, isa_bit_thumb2, 1769 isa_bit_fp16conv, isa_nobit 1770 } 1771 }, 1772 NULL, 1773 TARGET_ARCH_armv8_m_main 1774 }, 1775 { 1776 { 1777 "cortex-r52", 1778 cpu_opttab_cortexr52, 1779 { 1780 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1781 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1782 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1783 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1784 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1785 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1786 isa_bit_sec, isa_nobit 1787 } 1788 }, 1789 NULL, 1790 TARGET_ARCH_armv8_r 1791 }, 1792 {{NULL, NULL, {isa_nobit}}, NULL, TARGET_ARCH_arm_none} 1793 }; 1794 static const struct cpu_arch_extension arch_opttab_armv5te[] = { 1795 { 1796 "fp", false, false, 1797 { 1798 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1799 } 1800 }, 1801 { 1802 "nofp", true, false, 1803 { 1804 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1805 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1806 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1807 } 1808 }, 1809 { 1810 "vfpv2", false, true, 1811 { 1812 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1813 } 1814 }, 1815 { NULL, false, false, {isa_nobit}} 1816 }; 1817 1818 static const struct cpu_arch_extension arch_opttab_armv5tej[] = { 1819 { 1820 "fp", false, false, 1821 { 1822 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1823 } 1824 }, 1825 { 1826 "nofp", true, false, 1827 { 1828 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1829 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1830 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1831 } 1832 }, 1833 { 1834 "vfpv2", false, true, 1835 { 1836 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1837 } 1838 }, 1839 { NULL, false, false, {isa_nobit}} 1840 }; 1841 1842 static const struct cpu_arch_extension arch_opttab_armv6[] = { 1843 { 1844 "fp", false, false, 1845 { 1846 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1847 } 1848 }, 1849 { 1850 "nofp", true, false, 1851 { 1852 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1853 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1854 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1855 } 1856 }, 1857 { 1858 "vfpv2", false, true, 1859 { 1860 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1861 } 1862 }, 1863 { NULL, false, false, {isa_nobit}} 1864 }; 1865 1866 static const struct cpu_arch_extension arch_opttab_armv6j[] = { 1867 { 1868 "fp", false, false, 1869 { 1870 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1871 } 1872 }, 1873 { 1874 "nofp", true, false, 1875 { 1876 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1877 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1878 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1879 } 1880 }, 1881 { 1882 "vfpv2", false, true, 1883 { 1884 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1885 } 1886 }, 1887 { NULL, false, false, {isa_nobit}} 1888 }; 1889 1890 static const struct cpu_arch_extension arch_opttab_armv6k[] = { 1891 { 1892 "fp", false, false, 1893 { 1894 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1895 } 1896 }, 1897 { 1898 "nofp", true, false, 1899 { 1900 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1901 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1902 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1903 } 1904 }, 1905 { 1906 "vfpv2", false, true, 1907 { 1908 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1909 } 1910 }, 1911 { NULL, false, false, {isa_nobit}} 1912 }; 1913 1914 static const struct cpu_arch_extension arch_opttab_armv6z[] = { 1915 { 1916 "fp", false, false, 1917 { 1918 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1919 } 1920 }, 1921 { 1922 "nofp", true, false, 1923 { 1924 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1925 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1926 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1927 } 1928 }, 1929 { 1930 "vfpv2", false, true, 1931 { 1932 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1933 } 1934 }, 1935 { NULL, false, false, {isa_nobit}} 1936 }; 1937 1938 static const struct cpu_arch_extension arch_opttab_armv6kz[] = { 1939 { 1940 "fp", false, false, 1941 { 1942 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1943 } 1944 }, 1945 { 1946 "nofp", true, false, 1947 { 1948 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1949 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1950 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1951 } 1952 }, 1953 { 1954 "vfpv2", false, true, 1955 { 1956 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1957 } 1958 }, 1959 { NULL, false, false, {isa_nobit}} 1960 }; 1961 1962 static const struct cpu_arch_extension arch_opttab_armv6zk[] = { 1963 { 1964 "fp", false, false, 1965 { 1966 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1967 } 1968 }, 1969 { 1970 "nofp", true, false, 1971 { 1972 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1973 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1974 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1975 } 1976 }, 1977 { 1978 "vfpv2", false, true, 1979 { 1980 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1981 } 1982 }, 1983 { NULL, false, false, {isa_nobit}} 1984 }; 1985 1986 static const struct cpu_arch_extension arch_opttab_armv6t2[] = { 1987 { 1988 "fp", false, false, 1989 { 1990 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1991 } 1992 }, 1993 { 1994 "nofp", true, false, 1995 { 1996 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1997 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1998 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1999 } 2000 }, 2001 { 2002 "vfpv2", false, true, 2003 { 2004 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2005 } 2006 }, 2007 { NULL, false, false, {isa_nobit}} 2008 }; 2009 2010 static const struct cpu_arch_extension arch_opttab_armv7[] = { 2011 { 2012 "fp", false, false, 2013 { 2014 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2015 } 2016 }, 2017 { 2018 "nofp", true, false, 2019 { 2020 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2021 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2022 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2023 } 2024 }, 2025 { 2026 "vfpv3-d16", false, true, 2027 { 2028 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2029 } 2030 }, 2031 { NULL, false, false, {isa_nobit}} 2032 }; 2033 2034 static const struct cpu_arch_extension arch_opttab_armv7_a[] = { 2035 { 2036 "mp", false, false, 2037 { 2038 isa_bit_mp, isa_nobit 2039 } 2040 }, 2041 { 2042 "sec", false, false, 2043 { 2044 isa_bit_sec, isa_nobit 2045 } 2046 }, 2047 { 2048 "fp", false, false, 2049 { 2050 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2051 } 2052 }, 2053 { 2054 "vfpv3", false, false, 2055 { 2056 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2057 isa_nobit 2058 } 2059 }, 2060 { 2061 "vfpv3-d16-fp16", false, false, 2062 { 2063 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2064 isa_nobit 2065 } 2066 }, 2067 { 2068 "vfpv3-fp16", false, false, 2069 { 2070 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2071 isa_bit_fp_dbl, isa_nobit 2072 } 2073 }, 2074 { 2075 "vfpv4-d16", false, false, 2076 { 2077 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2078 isa_bit_fp_dbl, isa_nobit 2079 } 2080 }, 2081 { 2082 "vfpv4", false, false, 2083 { 2084 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2085 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2086 } 2087 }, 2088 { 2089 "simd", false, false, 2090 { 2091 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2092 isa_bit_fp_dbl, isa_nobit 2093 } 2094 }, 2095 { 2096 "neon-fp16", false, false, 2097 { 2098 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2099 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2100 } 2101 }, 2102 { 2103 "neon-vfpv4", false, false, 2104 { 2105 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2106 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2107 } 2108 }, 2109 { 2110 "nosimd", true, false, 2111 { 2112 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2113 isa_bit_crypto, isa_nobit 2114 } 2115 }, 2116 { 2117 "nofp", true, false, 2118 { 2119 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2120 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2121 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2122 } 2123 }, 2124 { 2125 "vfpv3-d16", false, true, 2126 { 2127 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2128 } 2129 }, 2130 { 2131 "neon", false, true, 2132 { 2133 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2134 isa_bit_fp_dbl, isa_nobit 2135 } 2136 }, 2137 { 2138 "neon-vfpv3", false, true, 2139 { 2140 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2141 isa_bit_fp_dbl, isa_nobit 2142 } 2143 }, 2144 { NULL, false, false, {isa_nobit}} 2145 }; 2146 2147 static const struct cpu_arch_extension arch_opttab_armv7ve[] = { 2148 { 2149 "vfpv3-d16", false, false, 2150 { 2151 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2152 } 2153 }, 2154 { 2155 "vfpv3", false, false, 2156 { 2157 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2158 isa_nobit 2159 } 2160 }, 2161 { 2162 "vfpv3-d16-fp16", false, false, 2163 { 2164 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2165 isa_nobit 2166 } 2167 }, 2168 { 2169 "vfpv3-fp16", false, false, 2170 { 2171 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2172 isa_bit_fp_dbl, isa_nobit 2173 } 2174 }, 2175 { 2176 "fp", false, false, 2177 { 2178 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2179 isa_bit_fp_dbl, isa_nobit 2180 } 2181 }, 2182 { 2183 "vfpv4", false, false, 2184 { 2185 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2186 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2187 } 2188 }, 2189 { 2190 "neon", false, false, 2191 { 2192 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2193 isa_bit_fp_dbl, isa_nobit 2194 } 2195 }, 2196 { 2197 "neon-fp16", false, false, 2198 { 2199 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2200 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2201 } 2202 }, 2203 { 2204 "simd", false, false, 2205 { 2206 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2207 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2208 } 2209 }, 2210 { 2211 "nosimd", true, false, 2212 { 2213 isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2214 isa_bit_crypto, isa_nobit 2215 } 2216 }, 2217 { 2218 "nofp", true, false, 2219 { 2220 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2221 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2222 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2223 } 2224 }, 2225 { 2226 "vfpv4-d16", false, true, 2227 { 2228 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2229 isa_bit_fp_dbl, isa_nobit 2230 } 2231 }, 2232 { 2233 "neon-vfpv3", false, true, 2234 { 2235 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2236 isa_bit_fp_dbl, isa_nobit 2237 } 2238 }, 2239 { 2240 "neon-vfpv4", false, true, 2241 { 2242 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2243 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2244 } 2245 }, 2246 { NULL, false, false, {isa_nobit}} 2247 }; 2248 2249 static const struct cpu_arch_extension arch_opttab_armv7_r[] = { 2250 { 2251 "fp.sp", false, false, 2252 { 2253 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2254 } 2255 }, 2256 { 2257 "fp", false, false, 2258 { 2259 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2260 } 2261 }, 2262 { 2263 "vfpv3xd-fp16", false, false, 2264 { 2265 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 2266 } 2267 }, 2268 { 2269 "vfpv3-d16-fp16", false, false, 2270 { 2271 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2272 isa_nobit 2273 } 2274 }, 2275 { 2276 "idiv", false, false, 2277 { 2278 isa_bit_adiv, isa_nobit 2279 } 2280 }, 2281 { 2282 "nofp", true, false, 2283 { 2284 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2285 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2286 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2287 } 2288 }, 2289 { 2290 "noidiv", true, false, 2291 { 2292 isa_bit_adiv, isa_nobit 2293 } 2294 }, 2295 { 2296 "vfpv3xd", false, true, 2297 { 2298 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2299 } 2300 }, 2301 { 2302 "vfpv3-d16", false, true, 2303 { 2304 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2305 } 2306 }, 2307 { NULL, false, false, {isa_nobit}} 2308 }; 2309 2310 static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { 2311 { 2312 "fp", false, false, 2313 { 2314 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2315 isa_nobit 2316 } 2317 }, 2318 { 2319 "fpv5", false, false, 2320 { 2321 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2322 isa_bit_fp16conv, isa_nobit 2323 } 2324 }, 2325 { 2326 "fp.dp", false, false, 2327 { 2328 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2329 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2330 } 2331 }, 2332 { 2333 "nofp", true, false, 2334 { 2335 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2336 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2337 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2338 } 2339 }, 2340 { 2341 "vfpv4-sp-d16", false, true, 2342 { 2343 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2344 isa_nobit 2345 } 2346 }, 2347 { 2348 "fpv5-d16", false, true, 2349 { 2350 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2351 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2352 } 2353 }, 2354 { NULL, false, false, {isa_nobit}} 2355 }; 2356 2357 static const struct cpu_arch_extension arch_opttab_armv8_a[] = { 2358 { 2359 "crc", false, false, 2360 { 2361 isa_bit_crc32, isa_nobit 2362 } 2363 }, 2364 { 2365 "simd", false, false, 2366 { 2367 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2368 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2369 isa_nobit 2370 } 2371 }, 2372 { 2373 "crypto", false, false, 2374 { 2375 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2376 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2377 isa_bit_fp_dbl, isa_nobit 2378 } 2379 }, 2380 { 2381 "nocrypto", true, false, 2382 { 2383 isa_bit_crypto, isa_nobit 2384 } 2385 }, 2386 { 2387 "nofp", true, false, 2388 { 2389 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2390 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2391 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2392 } 2393 }, 2394 { 2395 "sb", false, false, 2396 { 2397 isa_bit_sb, isa_nobit 2398 } 2399 }, 2400 { 2401 "predres", false, false, 2402 { 2403 isa_bit_predres, isa_nobit 2404 } 2405 }, 2406 { NULL, false, false, {isa_nobit}} 2407 }; 2408 2409 static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { 2410 { 2411 "simd", false, false, 2412 { 2413 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2414 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2415 isa_nobit 2416 } 2417 }, 2418 { 2419 "crypto", false, false, 2420 { 2421 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2422 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2423 isa_bit_fp_dbl, isa_nobit 2424 } 2425 }, 2426 { 2427 "nocrypto", true, false, 2428 { 2429 isa_bit_crypto, isa_nobit 2430 } 2431 }, 2432 { 2433 "nofp", true, false, 2434 { 2435 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2436 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2437 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2438 } 2439 }, 2440 { 2441 "sb", false, false, 2442 { 2443 isa_bit_sb, isa_nobit 2444 } 2445 }, 2446 { 2447 "predres", false, false, 2448 { 2449 isa_bit_predres, isa_nobit 2450 } 2451 }, 2452 { NULL, false, false, {isa_nobit}} 2453 }; 2454 2455 static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { 2456 { 2457 "simd", false, false, 2458 { 2459 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2460 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2461 isa_nobit 2462 } 2463 }, 2464 { 2465 "fp16", false, false, 2466 { 2467 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2468 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2469 isa_bit_fp_dbl, isa_nobit 2470 } 2471 }, 2472 { 2473 "fp16fml", false, false, 2474 { 2475 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2476 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2477 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2478 } 2479 }, 2480 { 2481 "crypto", false, false, 2482 { 2483 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2484 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2485 isa_bit_fp_dbl, isa_nobit 2486 } 2487 }, 2488 { 2489 "nocrypto", true, false, 2490 { 2491 isa_bit_crypto, isa_nobit 2492 } 2493 }, 2494 { 2495 "nofp", true, false, 2496 { 2497 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2498 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2499 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2500 } 2501 }, 2502 { 2503 "dotprod", false, false, 2504 { 2505 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2506 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2507 isa_bit_fp_dbl, isa_nobit 2508 } 2509 }, 2510 { 2511 "sb", false, false, 2512 { 2513 isa_bit_sb, isa_nobit 2514 } 2515 }, 2516 { 2517 "predres", false, false, 2518 { 2519 isa_bit_predres, isa_nobit 2520 } 2521 }, 2522 { NULL, false, false, {isa_nobit}} 2523 }; 2524 2525 static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = { 2526 { 2527 "simd", false, false, 2528 { 2529 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2530 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2531 isa_nobit 2532 } 2533 }, 2534 { 2535 "fp16", false, false, 2536 { 2537 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2538 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2539 isa_bit_fp_dbl, isa_nobit 2540 } 2541 }, 2542 { 2543 "fp16fml", false, false, 2544 { 2545 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2546 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2547 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2548 } 2549 }, 2550 { 2551 "crypto", false, false, 2552 { 2553 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2554 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2555 isa_bit_fp_dbl, isa_nobit 2556 } 2557 }, 2558 { 2559 "nocrypto", true, false, 2560 { 2561 isa_bit_crypto, isa_nobit 2562 } 2563 }, 2564 { 2565 "nofp", true, false, 2566 { 2567 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2568 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2569 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2570 } 2571 }, 2572 { 2573 "dotprod", false, false, 2574 { 2575 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2576 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2577 isa_bit_fp_dbl, isa_nobit 2578 } 2579 }, 2580 { 2581 "sb", false, false, 2582 { 2583 isa_bit_sb, isa_nobit 2584 } 2585 }, 2586 { 2587 "predres", false, false, 2588 { 2589 isa_bit_predres, isa_nobit 2590 } 2591 }, 2592 { NULL, false, false, {isa_nobit}} 2593 }; 2594 2595 static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = { 2596 { 2597 "simd", false, false, 2598 { 2599 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2600 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2601 isa_bit_fp_dbl, isa_nobit 2602 } 2603 }, 2604 { 2605 "fp16", false, false, 2606 { 2607 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2608 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2609 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2610 } 2611 }, 2612 { 2613 "crypto", false, false, 2614 { 2615 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2616 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2617 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2618 } 2619 }, 2620 { 2621 "nocrypto", true, false, 2622 { 2623 isa_bit_crypto, isa_nobit 2624 } 2625 }, 2626 { 2627 "nofp", true, false, 2628 { 2629 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2630 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2631 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2632 } 2633 }, 2634 { 2635 "sb", false, false, 2636 { 2637 isa_bit_sb, isa_nobit 2638 } 2639 }, 2640 { 2641 "predres", false, false, 2642 { 2643 isa_bit_predres, isa_nobit 2644 } 2645 }, 2646 { NULL, false, false, {isa_nobit}} 2647 }; 2648 2649 static const struct cpu_arch_extension arch_opttab_armv8_5_a[] = { 2650 { 2651 "simd", false, false, 2652 { 2653 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2654 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2655 isa_bit_fp_dbl, isa_nobit 2656 } 2657 }, 2658 { 2659 "fp16", false, false, 2660 { 2661 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2662 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2663 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2664 } 2665 }, 2666 { 2667 "crypto", false, false, 2668 { 2669 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2670 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2671 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2672 } 2673 }, 2674 { 2675 "nocrypto", true, false, 2676 { 2677 isa_bit_crypto, isa_nobit 2678 } 2679 }, 2680 { 2681 "nofp", true, false, 2682 { 2683 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2684 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2685 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2686 } 2687 }, 2688 { NULL, false, false, {isa_nobit}} 2689 }; 2690 2691 static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { 2692 { 2693 "dsp", false, false, 2694 { 2695 isa_bit_armv7em, isa_nobit 2696 } 2697 }, 2698 { 2699 "fp", false, false, 2700 { 2701 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2702 isa_bit_fp16conv, isa_nobit 2703 } 2704 }, 2705 { 2706 "fp.dp", false, false, 2707 { 2708 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2709 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2710 } 2711 }, 2712 { 2713 "nofp", true, false, 2714 { 2715 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2716 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2717 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2718 } 2719 }, 2720 { 2721 "nodsp", true, false, 2722 { 2723 isa_bit_armv7em, isa_nobit 2724 } 2725 }, 2726 { NULL, false, false, {isa_nobit}} 2727 }; 2728 2729 static const struct cpu_arch_extension arch_opttab_armv8_r[] = { 2730 { 2731 "crc", false, false, 2732 { 2733 isa_bit_crc32, isa_nobit 2734 } 2735 }, 2736 { 2737 "fp.sp", false, false, 2738 { 2739 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2740 isa_bit_fp16conv, isa_nobit 2741 } 2742 }, 2743 { 2744 "simd", false, false, 2745 { 2746 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2747 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2748 isa_nobit 2749 } 2750 }, 2751 { 2752 "crypto", false, false, 2753 { 2754 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2755 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2756 isa_bit_fp_dbl, isa_nobit 2757 } 2758 }, 2759 { 2760 "nocrypto", true, false, 2761 { 2762 isa_bit_crypto, isa_nobit 2763 } 2764 }, 2765 { 2766 "nofp", true, false, 2767 { 2768 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2769 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2770 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2771 } 2772 }, 2773 { NULL, false, false, {isa_nobit}} 2774 }; 2775 2776 const arch_option all_architectures[] = 2777 { 2778 { 2779 "armv4", 2780 NULL, 2781 { 2782 isa_bit_armv4, isa_bit_notm, isa_nobit 2783 }, 2784 "4", BASE_ARCH_4, 2785 0, 2786 TARGET_CPU_arm7tdmi, 2787 }, 2788 { 2789 "armv4t", 2790 NULL, 2791 { 2792 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 2793 }, 2794 "4T", BASE_ARCH_4T, 2795 0, 2796 TARGET_CPU_arm7tdmi, 2797 }, 2798 { 2799 "armv5t", 2800 NULL, 2801 { 2802 isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 2803 isa_nobit 2804 }, 2805 "5T", BASE_ARCH_5T, 2806 0, 2807 TARGET_CPU_arm10tdmi, 2808 }, 2809 { 2810 "armv5te", 2811 arch_opttab_armv5te, 2812 { 2813 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2814 isa_bit_notm, isa_nobit 2815 }, 2816 "5TE", BASE_ARCH_5TE, 2817 0, 2818 TARGET_CPU_arm1026ejs, 2819 }, 2820 { 2821 "armv5tej", 2822 arch_opttab_armv5tej, 2823 { 2824 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2825 isa_bit_notm, isa_nobit 2826 }, 2827 "5TEJ", BASE_ARCH_5TEJ, 2828 0, 2829 TARGET_CPU_arm1026ejs, 2830 }, 2831 { 2832 "armv6", 2833 arch_opttab_armv6, 2834 { 2835 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2836 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2837 }, 2838 "6", BASE_ARCH_6, 2839 0, 2840 TARGET_CPU_arm1136js, 2841 }, 2842 { 2843 "armv6j", 2844 arch_opttab_armv6j, 2845 { 2846 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2847 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2848 }, 2849 "6J", BASE_ARCH_6J, 2850 0, 2851 TARGET_CPU_arm1136js, 2852 }, 2853 { 2854 "armv6k", 2855 arch_opttab_armv6k, 2856 { 2857 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2858 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 2859 isa_nobit 2860 }, 2861 "6K", BASE_ARCH_6K, 2862 0, 2863 TARGET_CPU_mpcore, 2864 }, 2865 { 2866 "armv6z", 2867 arch_opttab_armv6z, 2868 { 2869 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2870 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2871 }, 2872 "6Z", BASE_ARCH_6Z, 2873 0, 2874 TARGET_CPU_arm1176jzs, 2875 }, 2876 { 2877 "armv6kz", 2878 arch_opttab_armv6kz, 2879 { 2880 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2881 isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2882 isa_bit_armv6k, isa_nobit 2883 }, 2884 "6KZ", BASE_ARCH_6KZ, 2885 0, 2886 TARGET_CPU_arm1176jzs, 2887 }, 2888 { 2889 "armv6zk", 2890 arch_opttab_armv6zk, 2891 { 2892 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2893 isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2894 isa_bit_armv6k, isa_nobit 2895 }, 2896 "6KZ", BASE_ARCH_6KZ, 2897 0, 2898 TARGET_CPU_arm1176jzs, 2899 }, 2900 { 2901 "armv6t2", 2902 arch_opttab_armv6t2, 2903 { 2904 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2905 isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 2906 isa_nobit 2907 }, 2908 "6T2", BASE_ARCH_6T2, 2909 0, 2910 TARGET_CPU_arm1156t2s, 2911 }, 2912 { 2913 "armv6-m", 2914 NULL, 2915 { 2916 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2917 isa_bit_armv4, isa_bit_armv6, isa_nobit 2918 }, 2919 "6M", BASE_ARCH_6M, 2920 'M', 2921 TARGET_CPU_cortexm1, 2922 }, 2923 { 2924 "armv6s-m", 2925 NULL, 2926 { 2927 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2928 isa_bit_armv4, isa_bit_armv6, isa_nobit 2929 }, 2930 "6M", BASE_ARCH_6M, 2931 'M', 2932 TARGET_CPU_cortexm1, 2933 }, 2934 { 2935 "armv7", 2936 arch_opttab_armv7, 2937 { 2938 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2939 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2940 isa_nobit 2941 }, 2942 "7", BASE_ARCH_7, 2943 0, 2944 TARGET_CPU_cortexa8, 2945 }, 2946 { 2947 "armv7-a", 2948 arch_opttab_armv7_a, 2949 { 2950 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2951 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2952 isa_bit_notm, isa_bit_armv6k, isa_nobit 2953 }, 2954 "7A", BASE_ARCH_7A, 2955 'A', 2956 TARGET_CPU_cortexa8, 2957 }, 2958 { 2959 "armv7ve", 2960 arch_opttab_armv7ve, 2961 { 2962 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 2963 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 2964 isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 2965 isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 2966 }, 2967 "7A", BASE_ARCH_7A, 2968 'A', 2969 TARGET_CPU_cortexa8, 2970 }, 2971 { 2972 "armv7-r", 2973 arch_opttab_armv7_r, 2974 { 2975 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2976 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2977 isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 2978 }, 2979 "7R", BASE_ARCH_7R, 2980 'R', 2981 TARGET_CPU_cortexr4, 2982 }, 2983 { 2984 "armv7-m", 2985 NULL, 2986 { 2987 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2988 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2989 isa_bit_thumb2, isa_nobit 2990 }, 2991 "7M", BASE_ARCH_7M, 2992 'M', 2993 TARGET_CPU_cortexm3, 2994 }, 2995 { 2996 "armv7e-m", 2997 arch_opttab_armv7e_m, 2998 { 2999 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3000 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, 3001 isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3002 }, 3003 "7EM", BASE_ARCH_7EM, 3004 'M', 3005 TARGET_CPU_cortexm4, 3006 }, 3007 { 3008 "armv8-a", 3009 arch_opttab_armv8_a, 3010 { 3011 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3012 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3013 isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3014 isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3015 isa_nobit 3016 }, 3017 "8A", BASE_ARCH_8A, 3018 'A', 3019 TARGET_CPU_cortexa53, 3020 }, 3021 { 3022 "armv8.1-a", 3023 arch_opttab_armv8_1_a, 3024 { 3025 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3026 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3027 isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3028 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3029 isa_bit_mp, isa_bit_sec, isa_nobit 3030 }, 3031 "8A", BASE_ARCH_8A, 3032 'A', 3033 TARGET_CPU_cortexa53, 3034 }, 3035 { 3036 "armv8.2-a", 3037 arch_opttab_armv8_2_a, 3038 { 3039 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3040 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3041 isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3042 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3043 isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 3044 }, 3045 "8A", BASE_ARCH_8A, 3046 'A', 3047 TARGET_CPU_cortexa53, 3048 }, 3049 { 3050 "armv8.3-a", 3051 arch_opttab_armv8_3_a, 3052 { 3053 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3054 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3055 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3056 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3057 isa_bit_armv8_2, isa_bit_armv8_3, isa_bit_mp, isa_bit_sec, 3058 isa_nobit 3059 }, 3060 "8A", BASE_ARCH_8A, 3061 'A', 3062 TARGET_CPU_cortexa53, 3063 }, 3064 { 3065 "armv8.4-a", 3066 arch_opttab_armv8_4_a, 3067 { 3068 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3069 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3070 isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3071 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3072 isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp, 3073 isa_bit_sec, isa_nobit 3074 }, 3075 "8A", BASE_ARCH_8A, 3076 'A', 3077 TARGET_CPU_cortexa53, 3078 }, 3079 { 3080 "armv8.5-a", 3081 arch_opttab_armv8_5_a, 3082 { 3083 isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3084 isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3085 isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 3086 isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3087 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 3088 isa_bit_mp, isa_bit_armv8_5, isa_bit_sec, isa_bit_predres, 3089 isa_nobit 3090 }, 3091 "8A", BASE_ARCH_8A, 3092 'A', 3093 TARGET_CPU_cortexa53, 3094 }, 3095 { 3096 "armv8-m.base", 3097 NULL, 3098 { 3099 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3100 isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 3101 isa_bit_tdiv, isa_nobit 3102 }, 3103 "8M_BASE", BASE_ARCH_8M_BASE, 3104 'M', 3105 TARGET_CPU_cortexm23, 3106 }, 3107 { 3108 "armv8-m.main", 3109 arch_opttab_armv8_m_main, 3110 { 3111 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3112 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_cmse, 3113 isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3114 }, 3115 "8M_MAIN", BASE_ARCH_8M_MAIN, 3116 'M', 3117 TARGET_CPU_cortexm7, 3118 }, 3119 { 3120 "armv8-r", 3121 arch_opttab_armv8_r, 3122 { 3123 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3124 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3125 isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3126 isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3127 isa_nobit 3128 }, 3129 "8R", BASE_ARCH_8R, 3130 'R', 3131 TARGET_CPU_cortexr52, 3132 }, 3133 { 3134 "iwmmxt", 3135 NULL, 3136 { 3137 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3138 isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 3139 }, 3140 "5TE", BASE_ARCH_5TE, 3141 0, 3142 TARGET_CPU_iwmmxt, 3143 }, 3144 { 3145 "iwmmxt2", 3146 NULL, 3147 { 3148 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3149 isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 3150 isa_nobit 3151 }, 3152 "5TE", BASE_ARCH_5TE, 3153 0, 3154 TARGET_CPU_iwmmxt2, 3155 }, 3156 {{NULL, NULL, {isa_nobit}}, 3157 NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none} 3158 }; 3159 3160 const arm_fpu_desc all_fpus[] = 3161 { 3162 { 3163 "vfp", 3164 { 3165 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3166 } 3167 }, 3168 { 3169 "vfpv2", 3170 { 3171 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3172 } 3173 }, 3174 { 3175 "vfpv3", 3176 { 3177 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3178 isa_nobit 3179 } 3180 }, 3181 { 3182 "vfpv3-fp16", 3183 { 3184 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 3185 isa_bit_fp_dbl, isa_nobit 3186 } 3187 }, 3188 { 3189 "vfpv3-d16", 3190 { 3191 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 3192 } 3193 }, 3194 { 3195 "vfpv3-d16-fp16", 3196 { 3197 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 3198 isa_nobit 3199 } 3200 }, 3201 { 3202 "vfpv3xd", 3203 { 3204 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 3205 } 3206 }, 3207 { 3208 "vfpv3xd-fp16", 3209 { 3210 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 3211 } 3212 }, 3213 { 3214 "neon", 3215 { 3216 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3217 isa_bit_fp_dbl, isa_nobit 3218 } 3219 }, 3220 { 3221 "neon-vfpv3", 3222 { 3223 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3224 isa_bit_fp_dbl, isa_nobit 3225 } 3226 }, 3227 { 3228 "neon-fp16", 3229 { 3230 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3231 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3232 } 3233 }, 3234 { 3235 "vfpv4", 3236 { 3237 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 3238 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3239 } 3240 }, 3241 { 3242 "neon-vfpv4", 3243 { 3244 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3245 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3246 } 3247 }, 3248 { 3249 "vfpv4-d16", 3250 { 3251 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3252 isa_bit_fp_dbl, isa_nobit 3253 } 3254 }, 3255 { 3256 "fpv4-sp-d16", 3257 { 3258 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3259 isa_nobit 3260 } 3261 }, 3262 { 3263 "fpv5-sp-d16", 3264 { 3265 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3266 isa_bit_fp16conv, isa_nobit 3267 } 3268 }, 3269 { 3270 "fpv5-d16", 3271 { 3272 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3273 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3274 } 3275 }, 3276 { 3277 "fp-armv8", 3278 { 3279 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3280 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3281 } 3282 }, 3283 { 3284 "neon-fp-armv8", 3285 { 3286 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3287 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 3288 isa_nobit 3289 } 3290 }, 3291 { 3292 "crypto-neon-fp-armv8", 3293 { 3294 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3295 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 3296 isa_bit_fp_dbl, isa_nobit 3297 } 3298 }, 3299 { 3300 "vfp3", 3301 { 3302 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3303 isa_nobit 3304 } 3305 }, 3306 }; 3307
Indexes created Mon Apr 06 00:22:49 UTC 2026