1 1.1 mrg /* This file is automatically generated. DO NOT EDIT! */ 2 1.1.1.4 mrg /* Generated from: NetBSD: mknative-gcc,v 1.117 2023/07/31 01:48:37 mrg Exp */ 3 1.1 mrg /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */ 4 1.1 mrg 5 1.1 mrg /* -*- buffer-read-only: t -*- 6 1.1 mrg Generated automatically by parsecpu.awk from arm-cpus.in. 7 1.1 mrg Do not edit. 8 1.1 mrg 9 1.1.1.4 mrg Copyright (C) 2011-2022 Free Software Foundation, Inc. 10 1.1 mrg 11 1.1 mrg This file is part of GCC. 12 1.1 mrg 13 1.1 mrg GCC is free software; you can redistribute it and/or modify 14 1.1 mrg it under the terms of the GNU General Public License as 15 1.1 mrg published by the Free Software Foundation; either version 3, 16 1.1 mrg or (at your option) any later version. 17 1.1 mrg 18 1.1 mrg GCC is distributed in the hope that it will be useful, 19 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 20 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 1.1 mrg GNU General Public License for more details. 22 1.1 mrg 23 1.1 mrg You should have received a copy of the GNU General Public 24 1.1 mrg License along with GCC; see the file COPYING3. If not see 25 1.1 mrg <http://www.gnu.org/licenses/>. */ 26 1.1 mrg 27 1.1.1.2 mrg static const cpu_alias cpu_aliastab_strongarm[] = { 28 1.1.1.2 mrg { "strongarm110", true}, 29 1.1.1.2 mrg { "strongarm1100", false}, 30 1.1.1.2 mrg { "strongarm1110", false}, 31 1.1.1.2 mrg { NULL, false} 32 1.1 mrg }; 33 1.1 mrg 34 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm7tdmi[] = { 35 1.1.1.2 mrg { "arm7tdmi-s", true}, 36 1.1.1.2 mrg { NULL, false} 37 1.1 mrg }; 38 1.1 mrg 39 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm710t[] = { 40 1.1.1.2 mrg { "arm720t", true}, 41 1.1.1.2 mrg { "arm740t", true}, 42 1.1.1.2 mrg { NULL, false} 43 1.1 mrg }; 44 1.1 mrg 45 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm920t[] = { 46 1.1.1.2 mrg { "arm920", true}, 47 1.1.1.2 mrg { "arm922t", true}, 48 1.1.1.2 mrg { "arm940t", true}, 49 1.1.1.2 mrg { "ep9312", true}, 50 1.1.1.2 mrg { NULL, false} 51 1.1 mrg }; 52 1.1 mrg 53 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm10tdmi[] = { 54 1.1.1.2 mrg { "arm1020t", true}, 55 1.1.1.2 mrg { NULL, false} 56 1.1 mrg }; 57 1.1 mrg 58 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_arm9e[] = { 59 1.1 mrg { 60 1.1 mrg "nofp", true, false, 61 1.1 mrg { 62 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 63 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 64 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 65 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 66 1.1 mrg } 67 1.1 mrg }, 68 1.1 mrg { NULL, false, false, {isa_nobit}} 69 1.1 mrg }; 70 1.1 mrg 71 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm9e[] = { 72 1.1.1.2 mrg { "arm946e-s", true}, 73 1.1.1.2 mrg { "arm966e-s", true}, 74 1.1.1.2 mrg { "arm968e-s", true}, 75 1.1.1.2 mrg { NULL, false} 76 1.1.1.2 mrg }; 77 1.1.1.2 mrg 78 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_arm10e[] = { 79 1.1 mrg { 80 1.1 mrg "nofp", true, false, 81 1.1 mrg { 82 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 83 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 84 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 85 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 86 1.1 mrg } 87 1.1 mrg }, 88 1.1 mrg { NULL, false, false, {isa_nobit}} 89 1.1 mrg }; 90 1.1 mrg 91 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm10e[] = { 92 1.1.1.2 mrg { "arm1020e", true}, 93 1.1.1.2 mrg { "arm1022e", true}, 94 1.1.1.2 mrg { NULL, false} 95 1.1.1.2 mrg }; 96 1.1.1.2 mrg 97 1.1 mrg static const cpu_arch_extension cpu_opttab_arm926ejs[] = { 98 1.1 mrg { 99 1.1 mrg "nofp", true, false, 100 1.1 mrg { 101 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 102 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 103 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 104 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 105 1.1 mrg } 106 1.1 mrg }, 107 1.1 mrg { NULL, false, false, {isa_nobit}} 108 1.1 mrg }; 109 1.1 mrg 110 1.1 mrg static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { 111 1.1 mrg { 112 1.1 mrg "nofp", true, false, 113 1.1 mrg { 114 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 115 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 116 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 117 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 118 1.1 mrg } 119 1.1 mrg }, 120 1.1 mrg { NULL, false, false, {isa_nobit}} 121 1.1 mrg }; 122 1.1 mrg 123 1.1 mrg static const cpu_arch_extension cpu_opttab_genericv7a[] = { 124 1.1 mrg { 125 1.1 mrg "mp", false, false, 126 1.1 mrg { 127 1.1 mrg isa_bit_mp, isa_nobit 128 1.1 mrg } 129 1.1 mrg }, 130 1.1 mrg { 131 1.1 mrg "sec", false, false, 132 1.1 mrg { 133 1.1 mrg isa_bit_sec, isa_nobit 134 1.1 mrg } 135 1.1 mrg }, 136 1.1 mrg { 137 1.1 mrg "vfpv3-d16", false, false, 138 1.1 mrg { 139 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 140 1.1 mrg } 141 1.1 mrg }, 142 1.1 mrg { 143 1.1 mrg "vfpv3", false, false, 144 1.1 mrg { 145 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 146 1.1 mrg isa_nobit 147 1.1 mrg } 148 1.1 mrg }, 149 1.1 mrg { 150 1.1 mrg "vfpv3-d16-fp16", false, false, 151 1.1 mrg { 152 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 153 1.1 mrg isa_nobit 154 1.1 mrg } 155 1.1 mrg }, 156 1.1 mrg { 157 1.1 mrg "vfpv3-fp16", false, false, 158 1.1 mrg { 159 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 160 1.1 mrg isa_bit_fp_dbl, isa_nobit 161 1.1 mrg } 162 1.1 mrg }, 163 1.1 mrg { 164 1.1 mrg "vfpv4-d16", false, false, 165 1.1 mrg { 166 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 167 1.1 mrg isa_bit_fp_dbl, isa_nobit 168 1.1 mrg } 169 1.1 mrg }, 170 1.1 mrg { 171 1.1 mrg "vfpv4", false, false, 172 1.1 mrg { 173 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 174 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 175 1.1 mrg } 176 1.1 mrg }, 177 1.1 mrg { 178 1.1 mrg "simd", false, false, 179 1.1 mrg { 180 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 181 1.1 mrg isa_bit_fp_dbl, isa_nobit 182 1.1 mrg } 183 1.1 mrg }, 184 1.1 mrg { 185 1.1 mrg "neon-fp16", false, false, 186 1.1 mrg { 187 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 188 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 189 1.1 mrg } 190 1.1 mrg }, 191 1.1 mrg { 192 1.1 mrg "neon-vfpv4", false, false, 193 1.1 mrg { 194 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 195 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 196 1.1 mrg } 197 1.1 mrg }, 198 1.1 mrg { 199 1.1 mrg "nosimd", true, false, 200 1.1 mrg { 201 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 202 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 203 1.1 mrg } 204 1.1 mrg }, 205 1.1 mrg { 206 1.1 mrg "nofp", true, false, 207 1.1 mrg { 208 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 209 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 210 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 211 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 212 1.1 mrg } 213 1.1 mrg }, 214 1.1 mrg { 215 1.1 mrg "neon", false, true, 216 1.1 mrg { 217 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 218 1.1 mrg isa_bit_fp_dbl, isa_nobit 219 1.1 mrg } 220 1.1 mrg }, 221 1.1 mrg { 222 1.1 mrg "neon-vfpv3", false, true, 223 1.1 mrg { 224 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 225 1.1 mrg isa_bit_fp_dbl, isa_nobit 226 1.1 mrg } 227 1.1 mrg }, 228 1.1 mrg { NULL, false, false, {isa_nobit}} 229 1.1 mrg }; 230 1.1 mrg 231 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa5[] = { 232 1.1 mrg { 233 1.1 mrg "nosimd", true, false, 234 1.1 mrg { 235 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 236 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 237 1.1 mrg } 238 1.1 mrg }, 239 1.1 mrg { 240 1.1 mrg "nofp", true, false, 241 1.1 mrg { 242 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 243 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 244 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 245 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 246 1.1 mrg } 247 1.1 mrg }, 248 1.1 mrg { NULL, false, false, {isa_nobit}} 249 1.1 mrg }; 250 1.1 mrg 251 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa7[] = { 252 1.1 mrg { 253 1.1 mrg "nosimd", true, false, 254 1.1 mrg { 255 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 256 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 257 1.1 mrg } 258 1.1 mrg }, 259 1.1 mrg { 260 1.1 mrg "nofp", true, false, 261 1.1 mrg { 262 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 263 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 264 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 265 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 266 1.1 mrg } 267 1.1 mrg }, 268 1.1 mrg { NULL, false, false, {isa_nobit}} 269 1.1 mrg }; 270 1.1 mrg 271 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa8[] = { 272 1.1 mrg { 273 1.1 mrg "nofp", true, false, 274 1.1 mrg { 275 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 276 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 277 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 278 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 279 1.1 mrg } 280 1.1 mrg }, 281 1.1 mrg { NULL, false, false, {isa_nobit}} 282 1.1 mrg }; 283 1.1 mrg 284 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa9[] = { 285 1.1 mrg { 286 1.1 mrg "nosimd", true, false, 287 1.1 mrg { 288 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 289 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 290 1.1 mrg } 291 1.1 mrg }, 292 1.1 mrg { 293 1.1 mrg "nofp", true, false, 294 1.1 mrg { 295 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 296 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 297 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 298 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 299 1.1 mrg } 300 1.1 mrg }, 301 1.1 mrg { NULL, false, false, {isa_nobit}} 302 1.1 mrg }; 303 1.1 mrg 304 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa12[] = { 305 1.1 mrg { 306 1.1 mrg "nofp", true, false, 307 1.1 mrg { 308 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 309 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 310 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 311 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 312 1.1 mrg } 313 1.1 mrg }, 314 1.1 mrg { NULL, false, false, {isa_nobit}} 315 1.1 mrg }; 316 1.1 mrg 317 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15[] = { 318 1.1 mrg { 319 1.1 mrg "nofp", true, false, 320 1.1 mrg { 321 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 322 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 323 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 324 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 325 1.1 mrg } 326 1.1 mrg }, 327 1.1 mrg { NULL, false, false, {isa_nobit}} 328 1.1 mrg }; 329 1.1 mrg 330 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17[] = { 331 1.1 mrg { 332 1.1 mrg "nofp", true, false, 333 1.1 mrg { 334 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 335 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 336 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 337 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 338 1.1 mrg } 339 1.1 mrg }, 340 1.1 mrg { NULL, false, false, {isa_nobit}} 341 1.1 mrg }; 342 1.1 mrg 343 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr5[] = { 344 1.1 mrg { 345 1.1 mrg "nofp.dp", true, false, 346 1.1 mrg { 347 1.1 mrg isa_bit_fp_dbl, isa_nobit 348 1.1 mrg } 349 1.1 mrg }, 350 1.1 mrg { 351 1.1 mrg "nofp", true, false, 352 1.1 mrg { 353 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 354 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 355 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 356 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 357 1.1 mrg } 358 1.1 mrg }, 359 1.1 mrg { NULL, false, false, {isa_nobit}} 360 1.1 mrg }; 361 1.1 mrg 362 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr7[] = { 363 1.1 mrg { 364 1.1 mrg "nofp.dp", true, false, 365 1.1 mrg { 366 1.1 mrg isa_bit_fp_dbl, isa_nobit 367 1.1 mrg } 368 1.1 mrg }, 369 1.1 mrg { 370 1.1 mrg "nofp", true, false, 371 1.1 mrg { 372 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 373 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 374 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 375 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 376 1.1 mrg } 377 1.1 mrg }, 378 1.1 mrg { NULL, false, false, {isa_nobit}} 379 1.1 mrg }; 380 1.1 mrg 381 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr8[] = { 382 1.1 mrg { 383 1.1 mrg "nofp.dp", true, false, 384 1.1 mrg { 385 1.1 mrg isa_bit_fp_dbl, isa_nobit 386 1.1 mrg } 387 1.1 mrg }, 388 1.1 mrg { 389 1.1 mrg "nofp", true, false, 390 1.1 mrg { 391 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 392 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 393 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 394 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 395 1.1 mrg } 396 1.1 mrg }, 397 1.1 mrg { NULL, false, false, {isa_nobit}} 398 1.1 mrg }; 399 1.1 mrg 400 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm7[] = { 401 1.1 mrg { 402 1.1 mrg "nofp.dp", true, false, 403 1.1 mrg { 404 1.1 mrg isa_bit_fp_dbl, isa_nobit 405 1.1 mrg } 406 1.1 mrg }, 407 1.1 mrg { 408 1.1 mrg "nofp", true, false, 409 1.1 mrg { 410 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 411 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 412 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 413 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 414 1.1 mrg } 415 1.1 mrg }, 416 1.1 mrg { NULL, false, false, {isa_nobit}} 417 1.1 mrg }; 418 1.1 mrg 419 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm4[] = { 420 1.1 mrg { 421 1.1 mrg "nofp", true, false, 422 1.1 mrg { 423 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 424 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 425 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 426 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 427 1.1 mrg } 428 1.1 mrg }, 429 1.1 mrg { NULL, false, false, {isa_nobit}} 430 1.1 mrg }; 431 1.1 mrg 432 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { 433 1.1 mrg { 434 1.1 mrg "nofp", true, false, 435 1.1 mrg { 436 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 437 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 438 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 439 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 440 1.1 mrg } 441 1.1 mrg }, 442 1.1 mrg { NULL, false, false, {isa_nobit}} 443 1.1 mrg }; 444 1.1 mrg 445 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { 446 1.1 mrg { 447 1.1 mrg "nofp", true, false, 448 1.1 mrg { 449 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 450 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 451 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 452 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 453 1.1 mrg } 454 1.1 mrg }, 455 1.1 mrg { NULL, false, false, {isa_nobit}} 456 1.1 mrg }; 457 1.1 mrg 458 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa32[] = { 459 1.1 mrg { 460 1.1 mrg "crypto", false, false, 461 1.1 mrg { 462 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 463 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 464 1.1 mrg isa_bit_fp_dbl, isa_nobit 465 1.1 mrg } 466 1.1 mrg }, 467 1.1 mrg { 468 1.1 mrg "nofp", true, false, 469 1.1 mrg { 470 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 471 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 472 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 473 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 474 1.1 mrg } 475 1.1 mrg }, 476 1.1 mrg { NULL, false, false, {isa_nobit}} 477 1.1 mrg }; 478 1.1 mrg 479 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa35[] = { 480 1.1 mrg { 481 1.1 mrg "crypto", false, false, 482 1.1 mrg { 483 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 484 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 485 1.1 mrg isa_bit_fp_dbl, isa_nobit 486 1.1 mrg } 487 1.1 mrg }, 488 1.1 mrg { 489 1.1 mrg "nofp", true, false, 490 1.1 mrg { 491 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 492 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 493 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 494 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 495 1.1 mrg } 496 1.1 mrg }, 497 1.1 mrg { NULL, false, false, {isa_nobit}} 498 1.1 mrg }; 499 1.1 mrg 500 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa53[] = { 501 1.1 mrg { 502 1.1 mrg "crypto", false, false, 503 1.1 mrg { 504 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 505 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 506 1.1 mrg isa_bit_fp_dbl, isa_nobit 507 1.1 mrg } 508 1.1 mrg }, 509 1.1 mrg { 510 1.1 mrg "nofp", true, false, 511 1.1 mrg { 512 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 513 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 514 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 515 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 516 1.1 mrg } 517 1.1 mrg }, 518 1.1 mrg { NULL, false, false, {isa_nobit}} 519 1.1 mrg }; 520 1.1 mrg 521 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57[] = { 522 1.1 mrg { 523 1.1 mrg "crypto", false, false, 524 1.1 mrg { 525 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 526 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 527 1.1 mrg isa_bit_fp_dbl, isa_nobit 528 1.1 mrg } 529 1.1 mrg }, 530 1.1 mrg { NULL, false, false, {isa_nobit}} 531 1.1 mrg }; 532 1.1 mrg 533 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72[] = { 534 1.1 mrg { 535 1.1 mrg "crypto", false, false, 536 1.1 mrg { 537 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 538 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 539 1.1 mrg isa_bit_fp_dbl, isa_nobit 540 1.1 mrg } 541 1.1 mrg }, 542 1.1 mrg { NULL, false, false, {isa_nobit}} 543 1.1 mrg }; 544 1.1 mrg 545 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73[] = { 546 1.1 mrg { 547 1.1 mrg "crypto", false, false, 548 1.1 mrg { 549 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 550 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 551 1.1 mrg isa_bit_fp_dbl, isa_nobit 552 1.1 mrg } 553 1.1 mrg }, 554 1.1 mrg { NULL, false, false, {isa_nobit}} 555 1.1 mrg }; 556 1.1 mrg 557 1.1 mrg static const cpu_arch_extension cpu_opttab_exynosm1[] = { 558 1.1 mrg { 559 1.1 mrg "crypto", false, false, 560 1.1 mrg { 561 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 562 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 563 1.1 mrg isa_bit_fp_dbl, isa_nobit 564 1.1 mrg } 565 1.1 mrg }, 566 1.1 mrg { NULL, false, false, {isa_nobit}} 567 1.1 mrg }; 568 1.1 mrg 569 1.1 mrg static const cpu_arch_extension cpu_opttab_xgene1[] = { 570 1.1 mrg { 571 1.1 mrg "crypto", false, false, 572 1.1 mrg { 573 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 574 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 575 1.1 mrg isa_bit_fp_dbl, isa_nobit 576 1.1 mrg } 577 1.1 mrg }, 578 1.1 mrg { NULL, false, false, {isa_nobit}} 579 1.1 mrg }; 580 1.1 mrg 581 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { 582 1.1 mrg { 583 1.1 mrg "crypto", false, false, 584 1.1 mrg { 585 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 586 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 587 1.1 mrg isa_bit_fp_dbl, isa_nobit 588 1.1 mrg } 589 1.1 mrg }, 590 1.1 mrg { NULL, false, false, {isa_nobit}} 591 1.1 mrg }; 592 1.1 mrg 593 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { 594 1.1 mrg { 595 1.1 mrg "crypto", false, false, 596 1.1 mrg { 597 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 598 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 599 1.1 mrg isa_bit_fp_dbl, isa_nobit 600 1.1 mrg } 601 1.1 mrg }, 602 1.1 mrg { NULL, false, false, {isa_nobit}} 603 1.1 mrg }; 604 1.1 mrg 605 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { 606 1.1 mrg { 607 1.1 mrg "crypto", false, false, 608 1.1 mrg { 609 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 610 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 611 1.1 mrg isa_bit_fp_dbl, isa_nobit 612 1.1 mrg } 613 1.1 mrg }, 614 1.1 mrg { NULL, false, false, {isa_nobit}} 615 1.1 mrg }; 616 1.1 mrg 617 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { 618 1.1 mrg { 619 1.1 mrg "crypto", false, false, 620 1.1 mrg { 621 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 622 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 623 1.1 mrg isa_bit_fp_dbl, isa_nobit 624 1.1 mrg } 625 1.1 mrg }, 626 1.1 mrg { NULL, false, false, {isa_nobit}} 627 1.1 mrg }; 628 1.1 mrg 629 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa55[] = { 630 1.1 mrg { 631 1.1 mrg "crypto", false, false, 632 1.1 mrg { 633 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 634 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 635 1.1 mrg isa_bit_fp_dbl, isa_nobit 636 1.1 mrg } 637 1.1 mrg }, 638 1.1 mrg { 639 1.1 mrg "nofp", true, false, 640 1.1 mrg { 641 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 642 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 643 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 644 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 645 1.1 mrg } 646 1.1 mrg }, 647 1.1 mrg { NULL, false, false, {isa_nobit}} 648 1.1 mrg }; 649 1.1 mrg 650 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75[] = { 651 1.1 mrg { 652 1.1 mrg "crypto", false, false, 653 1.1 mrg { 654 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 655 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 656 1.1 mrg isa_bit_fp_dbl, isa_nobit 657 1.1 mrg } 658 1.1 mrg }, 659 1.1 mrg { NULL, false, false, {isa_nobit}} 660 1.1 mrg }; 661 1.1 mrg 662 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_cortexa76[] = { 663 1.1.1.2 mrg { 664 1.1.1.2 mrg "crypto", false, false, 665 1.1.1.2 mrg { 666 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 667 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 668 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 669 1.1.1.2 mrg } 670 1.1.1.2 mrg }, 671 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 672 1.1.1.2 mrg }; 673 1.1.1.2 mrg 674 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_cortexa76ae[] = { 675 1.1.1.3 mrg { 676 1.1.1.3 mrg "crypto", false, false, 677 1.1.1.3 mrg { 678 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 679 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 680 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 681 1.1.1.3 mrg } 682 1.1.1.3 mrg }, 683 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 684 1.1.1.3 mrg }; 685 1.1.1.3 mrg 686 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_cortexa77[] = { 687 1.1.1.3 mrg { 688 1.1.1.3 mrg "crypto", false, false, 689 1.1.1.3 mrg { 690 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 691 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 692 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 693 1.1.1.3 mrg } 694 1.1.1.3 mrg }, 695 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 696 1.1.1.3 mrg }; 697 1.1.1.3 mrg 698 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexa78[] = { 699 1.1.1.4 mrg { 700 1.1.1.4 mrg "crypto", false, false, 701 1.1.1.4 mrg { 702 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 703 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 704 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 705 1.1.1.4 mrg } 706 1.1.1.4 mrg }, 707 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 708 1.1.1.4 mrg }; 709 1.1.1.4 mrg 710 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexa78ae[] = { 711 1.1.1.4 mrg { 712 1.1.1.4 mrg "crypto", false, false, 713 1.1.1.4 mrg { 714 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 715 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 716 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 717 1.1.1.4 mrg } 718 1.1.1.4 mrg }, 719 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 720 1.1.1.4 mrg }; 721 1.1.1.4 mrg 722 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexa78c[] = { 723 1.1.1.4 mrg { 724 1.1.1.4 mrg "crypto", false, false, 725 1.1.1.4 mrg { 726 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 727 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 728 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 729 1.1.1.4 mrg } 730 1.1.1.4 mrg }, 731 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 732 1.1.1.4 mrg }; 733 1.1.1.4 mrg 734 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexa710[] = { 735 1.1.1.4 mrg { 736 1.1.1.4 mrg "crypto", false, false, 737 1.1.1.4 mrg { 738 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 739 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 740 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 741 1.1.1.4 mrg } 742 1.1.1.4 mrg }, 743 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 744 1.1.1.4 mrg }; 745 1.1.1.4 mrg 746 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexx1[] = { 747 1.1.1.4 mrg { 748 1.1.1.4 mrg "crypto", false, false, 749 1.1.1.4 mrg { 750 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 751 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 752 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 753 1.1.1.4 mrg } 754 1.1.1.4 mrg }, 755 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 756 1.1.1.4 mrg }; 757 1.1.1.4 mrg 758 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_neoversen1[] = { 759 1.1.1.2 mrg { 760 1.1.1.2 mrg "crypto", false, false, 761 1.1.1.2 mrg { 762 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 763 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 764 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 765 1.1.1.2 mrg } 766 1.1.1.2 mrg }, 767 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 768 1.1.1.2 mrg }; 769 1.1.1.2 mrg 770 1.1.1.2 mrg static const cpu_alias cpu_aliastab_neoversen1[] = { 771 1.1.1.2 mrg { "ares", false}, 772 1.1.1.2 mrg { NULL, false} 773 1.1.1.2 mrg }; 774 1.1.1.2 mrg 775 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = { 776 1.1 mrg { 777 1.1 mrg "crypto", false, false, 778 1.1 mrg { 779 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 780 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 781 1.1 mrg isa_bit_fp_dbl, isa_nobit 782 1.1 mrg } 783 1.1 mrg }, 784 1.1 mrg { NULL, false, false, {isa_nobit}} 785 1.1 mrg }; 786 1.1 mrg 787 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_cortexa76cortexa55[] = { 788 1.1.1.2 mrg { 789 1.1.1.2 mrg "crypto", false, false, 790 1.1.1.2 mrg { 791 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 792 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 793 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 794 1.1.1.2 mrg } 795 1.1.1.2 mrg }, 796 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 797 1.1.1.2 mrg }; 798 1.1.1.2 mrg 799 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_neoversev1[] = { 800 1.1.1.3 mrg { 801 1.1.1.3 mrg "crypto", false, false, 802 1.1.1.3 mrg { 803 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 804 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 805 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 806 1.1.1.3 mrg } 807 1.1.1.3 mrg }, 808 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 809 1.1.1.3 mrg }; 810 1.1.1.3 mrg 811 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_neoversen2[] = { 812 1.1.1.3 mrg { 813 1.1.1.3 mrg "crypto", false, false, 814 1.1.1.3 mrg { 815 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 816 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 817 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 818 1.1.1.3 mrg } 819 1.1.1.3 mrg }, 820 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 821 1.1.1.3 mrg }; 822 1.1.1.3 mrg 823 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm33[] = { 824 1.1 mrg { 825 1.1 mrg "nofp", true, false, 826 1.1 mrg { 827 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 828 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 829 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 830 1.1.1.3 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 831 1.1.1.3 mrg } 832 1.1.1.3 mrg }, 833 1.1.1.3 mrg { 834 1.1.1.3 mrg "nodsp", true, false, 835 1.1.1.3 mrg { 836 1.1.1.3 mrg isa_bit_armv7em, isa_nobit 837 1.1.1.3 mrg } 838 1.1.1.3 mrg }, 839 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 840 1.1.1.3 mrg }; 841 1.1.1.3 mrg 842 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_cortexm35p[] = { 843 1.1.1.3 mrg { 844 1.1.1.3 mrg "nofp", true, false, 845 1.1.1.3 mrg { 846 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 847 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 848 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 849 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 850 1.1 mrg } 851 1.1 mrg }, 852 1.1 mrg { 853 1.1 mrg "nodsp", true, false, 854 1.1 mrg { 855 1.1 mrg isa_bit_armv7em, isa_nobit 856 1.1 mrg } 857 1.1 mrg }, 858 1.1 mrg { NULL, false, false, {isa_nobit}} 859 1.1 mrg }; 860 1.1 mrg 861 1.1.1.3 mrg static const cpu_arch_extension cpu_opttab_cortexm55[] = { 862 1.1.1.3 mrg { 863 1.1.1.3 mrg "nomve.fp", true, false, 864 1.1.1.3 mrg { 865 1.1.1.3 mrg isa_bit_mve_float, isa_nobit 866 1.1.1.3 mrg } 867 1.1.1.3 mrg }, 868 1.1.1.3 mrg { 869 1.1.1.3 mrg "nomve", true, false, 870 1.1.1.3 mrg { 871 1.1.1.3 mrg isa_bit_mve, isa_bit_mve_float, isa_nobit 872 1.1.1.3 mrg } 873 1.1.1.3 mrg }, 874 1.1.1.3 mrg { 875 1.1.1.3 mrg "nofp", true, false, 876 1.1.1.3 mrg { 877 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 878 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 879 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 880 1.1.1.3 mrg isa_bit_crypto, isa_bit_mve_float, isa_bit_fp_dbl, isa_nobit 881 1.1.1.3 mrg } 882 1.1.1.3 mrg }, 883 1.1.1.3 mrg { 884 1.1.1.3 mrg "nodsp", true, false, 885 1.1.1.3 mrg { 886 1.1.1.3 mrg isa_bit_mve, isa_bit_armv7em, isa_bit_mve_float, isa_nobit 887 1.1.1.3 mrg } 888 1.1.1.3 mrg }, 889 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 890 1.1.1.3 mrg }; 891 1.1.1.3 mrg 892 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr52[] = { 893 1.1 mrg { 894 1.1 mrg "nofp.dp", true, false, 895 1.1 mrg { 896 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 897 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 898 1.1 mrg } 899 1.1 mrg }, 900 1.1 mrg { NULL, false, false, {isa_nobit}} 901 1.1 mrg }; 902 1.1 mrg 903 1.1.1.4 mrg static const cpu_arch_extension cpu_opttab_cortexr52plus[] = { 904 1.1.1.4 mrg { 905 1.1.1.4 mrg "nofp.dp", true, false, 906 1.1.1.4 mrg { 907 1.1.1.4 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 908 1.1.1.4 mrg isa_bit_fp_d32, isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 909 1.1.1.4 mrg } 910 1.1.1.4 mrg }, 911 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 912 1.1.1.4 mrg }; 913 1.1.1.4 mrg 914 1.1 mrg const cpu_option all_cores[] = 915 1.1 mrg { 916 1.1 mrg { 917 1.1 mrg { 918 1.1 mrg "arm8", 919 1.1 mrg NULL, 920 1.1 mrg { 921 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 922 1.1 mrg } 923 1.1 mrg }, 924 1.1.1.2 mrg NULL, 925 1.1 mrg TARGET_ARCH_armv4 926 1.1 mrg }, 927 1.1 mrg { 928 1.1 mrg { 929 1.1 mrg "arm810", 930 1.1 mrg NULL, 931 1.1 mrg { 932 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 933 1.1 mrg } 934 1.1 mrg }, 935 1.1.1.2 mrg NULL, 936 1.1 mrg TARGET_ARCH_armv4 937 1.1 mrg }, 938 1.1 mrg { 939 1.1 mrg { 940 1.1 mrg "strongarm", 941 1.1 mrg NULL, 942 1.1 mrg { 943 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 944 1.1 mrg } 945 1.1 mrg }, 946 1.1.1.2 mrg cpu_aliastab_strongarm, 947 1.1 mrg TARGET_ARCH_armv4 948 1.1 mrg }, 949 1.1 mrg { 950 1.1 mrg { 951 1.1 mrg "fa526", 952 1.1 mrg NULL, 953 1.1 mrg { 954 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 955 1.1 mrg } 956 1.1 mrg }, 957 1.1.1.2 mrg NULL, 958 1.1 mrg TARGET_ARCH_armv4 959 1.1 mrg }, 960 1.1 mrg { 961 1.1 mrg { 962 1.1 mrg "fa626", 963 1.1 mrg NULL, 964 1.1 mrg { 965 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 966 1.1 mrg } 967 1.1 mrg }, 968 1.1.1.2 mrg NULL, 969 1.1 mrg TARGET_ARCH_armv4 970 1.1 mrg }, 971 1.1 mrg { 972 1.1 mrg { 973 1.1 mrg "arm7tdmi", 974 1.1 mrg NULL, 975 1.1 mrg { 976 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 977 1.1 mrg } 978 1.1 mrg }, 979 1.1.1.2 mrg cpu_aliastab_arm7tdmi, 980 1.1 mrg TARGET_ARCH_armv4t 981 1.1 mrg }, 982 1.1 mrg { 983 1.1 mrg { 984 1.1 mrg "arm710t", 985 1.1 mrg NULL, 986 1.1 mrg { 987 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 988 1.1 mrg } 989 1.1 mrg }, 990 1.1.1.2 mrg cpu_aliastab_arm710t, 991 1.1 mrg TARGET_ARCH_armv4t 992 1.1 mrg }, 993 1.1 mrg { 994 1.1 mrg { 995 1.1 mrg "arm9", 996 1.1 mrg NULL, 997 1.1 mrg { 998 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 999 1.1 mrg } 1000 1.1 mrg }, 1001 1.1.1.2 mrg NULL, 1002 1.1 mrg TARGET_ARCH_armv4t 1003 1.1 mrg }, 1004 1.1 mrg { 1005 1.1 mrg { 1006 1.1 mrg "arm9tdmi", 1007 1.1 mrg NULL, 1008 1.1 mrg { 1009 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 1010 1.1 mrg } 1011 1.1 mrg }, 1012 1.1.1.2 mrg NULL, 1013 1.1 mrg TARGET_ARCH_armv4t 1014 1.1 mrg }, 1015 1.1 mrg { 1016 1.1 mrg { 1017 1.1 mrg "arm920t", 1018 1.1 mrg NULL, 1019 1.1 mrg { 1020 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 1021 1.1 mrg } 1022 1.1 mrg }, 1023 1.1.1.2 mrg cpu_aliastab_arm920t, 1024 1.1 mrg TARGET_ARCH_armv4t 1025 1.1 mrg }, 1026 1.1 mrg { 1027 1.1 mrg { 1028 1.1 mrg "arm10tdmi", 1029 1.1 mrg NULL, 1030 1.1 mrg { 1031 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 1032 1.1.1.2 mrg isa_nobit 1033 1.1 mrg } 1034 1.1 mrg }, 1035 1.1.1.2 mrg cpu_aliastab_arm10tdmi, 1036 1.1 mrg TARGET_ARCH_armv5t 1037 1.1 mrg }, 1038 1.1 mrg { 1039 1.1 mrg { 1040 1.1 mrg "arm9e", 1041 1.1 mrg cpu_opttab_arm9e, 1042 1.1 mrg { 1043 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 1044 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1045 1.1 mrg } 1046 1.1 mrg }, 1047 1.1.1.2 mrg cpu_aliastab_arm9e, 1048 1.1 mrg TARGET_ARCH_armv5te 1049 1.1 mrg }, 1050 1.1 mrg { 1051 1.1 mrg { 1052 1.1 mrg "arm10e", 1053 1.1 mrg cpu_opttab_arm10e, 1054 1.1 mrg { 1055 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 1056 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1057 1.1 mrg } 1058 1.1 mrg }, 1059 1.1.1.2 mrg cpu_aliastab_arm10e, 1060 1.1 mrg TARGET_ARCH_armv5te 1061 1.1 mrg }, 1062 1.1 mrg { 1063 1.1 mrg { 1064 1.1 mrg "xscale", 1065 1.1 mrg NULL, 1066 1.1 mrg { 1067 1.1.1.2 mrg isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, isa_bit_armv5t, 1068 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 1069 1.1 mrg } 1070 1.1 mrg }, 1071 1.1.1.2 mrg NULL, 1072 1.1 mrg TARGET_ARCH_armv5te 1073 1.1 mrg }, 1074 1.1 mrg { 1075 1.1 mrg { 1076 1.1 mrg "iwmmxt", 1077 1.1 mrg NULL, 1078 1.1 mrg { 1079 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 1080 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 1081 1.1 mrg } 1082 1.1 mrg }, 1083 1.1.1.2 mrg NULL, 1084 1.1 mrg TARGET_ARCH_iwmmxt 1085 1.1 mrg }, 1086 1.1 mrg { 1087 1.1 mrg { 1088 1.1 mrg "iwmmxt2", 1089 1.1 mrg NULL, 1090 1.1 mrg { 1091 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 1092 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 1093 1.1.1.2 mrg isa_nobit 1094 1.1 mrg } 1095 1.1 mrg }, 1096 1.1.1.2 mrg NULL, 1097 1.1 mrg TARGET_ARCH_iwmmxt2 1098 1.1 mrg }, 1099 1.1 mrg { 1100 1.1 mrg { 1101 1.1 mrg "fa606te", 1102 1.1 mrg NULL, 1103 1.1 mrg { 1104 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 1105 1.1.1.2 mrg isa_bit_notm, isa_nobit 1106 1.1 mrg } 1107 1.1 mrg }, 1108 1.1.1.2 mrg NULL, 1109 1.1 mrg TARGET_ARCH_armv5te 1110 1.1 mrg }, 1111 1.1 mrg { 1112 1.1 mrg { 1113 1.1 mrg "fa626te", 1114 1.1 mrg NULL, 1115 1.1 mrg { 1116 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 1117 1.1.1.2 mrg isa_bit_notm, isa_nobit 1118 1.1 mrg } 1119 1.1 mrg }, 1120 1.1.1.2 mrg NULL, 1121 1.1 mrg TARGET_ARCH_armv5te 1122 1.1 mrg }, 1123 1.1 mrg { 1124 1.1 mrg { 1125 1.1 mrg "fmp626", 1126 1.1 mrg NULL, 1127 1.1 mrg { 1128 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 1129 1.1.1.2 mrg isa_bit_notm, isa_nobit 1130 1.1 mrg } 1131 1.1 mrg }, 1132 1.1.1.2 mrg NULL, 1133 1.1 mrg TARGET_ARCH_armv5te 1134 1.1 mrg }, 1135 1.1 mrg { 1136 1.1 mrg { 1137 1.1 mrg "fa726te", 1138 1.1 mrg NULL, 1139 1.1 mrg { 1140 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 1141 1.1.1.2 mrg isa_bit_notm, isa_nobit 1142 1.1 mrg } 1143 1.1 mrg }, 1144 1.1.1.2 mrg NULL, 1145 1.1 mrg TARGET_ARCH_armv5te 1146 1.1 mrg }, 1147 1.1 mrg { 1148 1.1 mrg { 1149 1.1 mrg "arm926ej-s", 1150 1.1 mrg cpu_opttab_arm926ejs, 1151 1.1 mrg { 1152 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 1153 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1154 1.1 mrg } 1155 1.1 mrg }, 1156 1.1.1.2 mrg NULL, 1157 1.1 mrg TARGET_ARCH_armv5tej 1158 1.1 mrg }, 1159 1.1 mrg { 1160 1.1 mrg { 1161 1.1 mrg "arm1026ej-s", 1162 1.1 mrg cpu_opttab_arm1026ejs, 1163 1.1 mrg { 1164 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 1165 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1166 1.1 mrg } 1167 1.1 mrg }, 1168 1.1.1.2 mrg NULL, 1169 1.1 mrg TARGET_ARCH_armv5tej 1170 1.1 mrg }, 1171 1.1 mrg { 1172 1.1 mrg { 1173 1.1 mrg "arm1136j-s", 1174 1.1 mrg NULL, 1175 1.1 mrg { 1176 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1177 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 1178 1.1 mrg } 1179 1.1 mrg }, 1180 1.1.1.2 mrg NULL, 1181 1.1 mrg TARGET_ARCH_armv6j 1182 1.1 mrg }, 1183 1.1 mrg { 1184 1.1 mrg { 1185 1.1 mrg "arm1136jf-s", 1186 1.1 mrg NULL, 1187 1.1 mrg { 1188 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1189 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 1190 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 1191 1.1 mrg } 1192 1.1 mrg }, 1193 1.1.1.2 mrg NULL, 1194 1.1 mrg TARGET_ARCH_armv6j 1195 1.1 mrg }, 1196 1.1 mrg { 1197 1.1 mrg { 1198 1.1 mrg "arm1176jz-s", 1199 1.1 mrg NULL, 1200 1.1 mrg { 1201 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1202 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm, 1203 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 1204 1.1 mrg } 1205 1.1 mrg }, 1206 1.1.1.2 mrg NULL, 1207 1.1 mrg TARGET_ARCH_armv6kz 1208 1.1 mrg }, 1209 1.1 mrg { 1210 1.1 mrg { 1211 1.1 mrg "arm1176jzf-s", 1212 1.1 mrg NULL, 1213 1.1 mrg { 1214 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1215 1.1.1.3 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, 1216 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1217 1.1 mrg } 1218 1.1 mrg }, 1219 1.1.1.2 mrg NULL, 1220 1.1 mrg TARGET_ARCH_armv6kz 1221 1.1 mrg }, 1222 1.1 mrg { 1223 1.1 mrg { 1224 1.1 mrg "mpcorenovfp", 1225 1.1 mrg NULL, 1226 1.1 mrg { 1227 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1228 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 1229 1.1.1.2 mrg isa_nobit 1230 1.1 mrg } 1231 1.1 mrg }, 1232 1.1.1.2 mrg NULL, 1233 1.1 mrg TARGET_ARCH_armv6k 1234 1.1 mrg }, 1235 1.1 mrg { 1236 1.1 mrg { 1237 1.1 mrg "mpcore", 1238 1.1 mrg NULL, 1239 1.1 mrg { 1240 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1241 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 1242 1.1.1.2 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1243 1.1 mrg } 1244 1.1 mrg }, 1245 1.1.1.2 mrg NULL, 1246 1.1 mrg TARGET_ARCH_armv6k 1247 1.1 mrg }, 1248 1.1 mrg { 1249 1.1 mrg { 1250 1.1 mrg "arm1156t2-s", 1251 1.1 mrg NULL, 1252 1.1 mrg { 1253 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1254 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 1255 1.1.1.2 mrg isa_nobit 1256 1.1 mrg } 1257 1.1 mrg }, 1258 1.1.1.2 mrg NULL, 1259 1.1 mrg TARGET_ARCH_armv6t2 1260 1.1 mrg }, 1261 1.1 mrg { 1262 1.1 mrg { 1263 1.1 mrg "arm1156t2f-s", 1264 1.1 mrg NULL, 1265 1.1 mrg { 1266 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1267 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, 1268 1.1.1.2 mrg isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1269 1.1 mrg } 1270 1.1 mrg }, 1271 1.1.1.2 mrg NULL, 1272 1.1 mrg TARGET_ARCH_armv6t2 1273 1.1 mrg }, 1274 1.1 mrg { 1275 1.1 mrg { 1276 1.1 mrg "cortex-m1", 1277 1.1 mrg NULL, 1278 1.1 mrg { 1279 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1280 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1281 1.1 mrg } 1282 1.1 mrg }, 1283 1.1.1.2 mrg NULL, 1284 1.1 mrg TARGET_ARCH_armv6s_m 1285 1.1 mrg }, 1286 1.1 mrg { 1287 1.1 mrg { 1288 1.1 mrg "cortex-m0", 1289 1.1 mrg NULL, 1290 1.1 mrg { 1291 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1292 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1293 1.1 mrg } 1294 1.1 mrg }, 1295 1.1.1.2 mrg NULL, 1296 1.1 mrg TARGET_ARCH_armv6s_m 1297 1.1 mrg }, 1298 1.1 mrg { 1299 1.1 mrg { 1300 1.1 mrg "cortex-m0plus", 1301 1.1 mrg NULL, 1302 1.1 mrg { 1303 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1304 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1305 1.1 mrg } 1306 1.1 mrg }, 1307 1.1.1.2 mrg NULL, 1308 1.1 mrg TARGET_ARCH_armv6s_m 1309 1.1 mrg }, 1310 1.1 mrg { 1311 1.1 mrg { 1312 1.1 mrg "cortex-m1.small-multiply", 1313 1.1 mrg NULL, 1314 1.1 mrg { 1315 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1316 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1317 1.1 mrg } 1318 1.1 mrg }, 1319 1.1.1.2 mrg NULL, 1320 1.1 mrg TARGET_ARCH_armv6s_m 1321 1.1 mrg }, 1322 1.1 mrg { 1323 1.1 mrg { 1324 1.1 mrg "cortex-m0.small-multiply", 1325 1.1 mrg NULL, 1326 1.1 mrg { 1327 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1328 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1329 1.1 mrg } 1330 1.1 mrg }, 1331 1.1.1.2 mrg NULL, 1332 1.1 mrg TARGET_ARCH_armv6s_m 1333 1.1 mrg }, 1334 1.1 mrg { 1335 1.1 mrg { 1336 1.1 mrg "cortex-m0plus.small-multiply", 1337 1.1 mrg NULL, 1338 1.1 mrg { 1339 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1340 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1341 1.1 mrg } 1342 1.1 mrg }, 1343 1.1.1.2 mrg NULL, 1344 1.1 mrg TARGET_ARCH_armv6s_m 1345 1.1 mrg }, 1346 1.1 mrg { 1347 1.1 mrg { 1348 1.1 mrg "generic-armv7-a", 1349 1.1 mrg cpu_opttab_genericv7a, 1350 1.1 mrg { 1351 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_quirk_no_asmcpu, 1352 1.1.1.3 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1353 1.1.1.3 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, 1354 1.1.1.3 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1355 1.1 mrg } 1356 1.1 mrg }, 1357 1.1.1.2 mrg NULL, 1358 1.1 mrg TARGET_ARCH_armv7_a 1359 1.1 mrg }, 1360 1.1 mrg { 1361 1.1 mrg { 1362 1.1 mrg "cortex-a5", 1363 1.1 mrg cpu_opttab_cortexa5, 1364 1.1 mrg { 1365 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1366 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1367 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1368 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1369 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1370 1.1 mrg } 1371 1.1 mrg }, 1372 1.1.1.2 mrg NULL, 1373 1.1 mrg TARGET_ARCH_armv7_a 1374 1.1 mrg }, 1375 1.1 mrg { 1376 1.1 mrg { 1377 1.1 mrg "cortex-a7", 1378 1.1 mrg cpu_opttab_cortexa7, 1379 1.1 mrg { 1380 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1381 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1382 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1383 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1384 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1385 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1386 1.1 mrg } 1387 1.1 mrg }, 1388 1.1.1.2 mrg NULL, 1389 1.1 mrg TARGET_ARCH_armv7ve 1390 1.1 mrg }, 1391 1.1 mrg { 1392 1.1 mrg { 1393 1.1 mrg "cortex-a8", 1394 1.1 mrg cpu_opttab_cortexa8, 1395 1.1 mrg { 1396 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1397 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1398 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1399 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_sec, 1400 1.1.1.2 mrg isa_nobit 1401 1.1 mrg } 1402 1.1 mrg }, 1403 1.1.1.2 mrg NULL, 1404 1.1 mrg TARGET_ARCH_armv7_a 1405 1.1 mrg }, 1406 1.1 mrg { 1407 1.1 mrg { 1408 1.1 mrg "cortex-a9", 1409 1.1 mrg cpu_opttab_cortexa9, 1410 1.1 mrg { 1411 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1412 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1413 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1414 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1415 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1416 1.1 mrg } 1417 1.1 mrg }, 1418 1.1.1.2 mrg NULL, 1419 1.1 mrg TARGET_ARCH_armv7_a 1420 1.1 mrg }, 1421 1.1 mrg { 1422 1.1 mrg { 1423 1.1 mrg "cortex-a12", 1424 1.1 mrg cpu_opttab_cortexa12, 1425 1.1 mrg { 1426 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1427 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1428 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1429 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1430 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1431 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1432 1.1 mrg } 1433 1.1 mrg }, 1434 1.1.1.2 mrg NULL, 1435 1.1 mrg TARGET_ARCH_armv7ve 1436 1.1 mrg }, 1437 1.1 mrg { 1438 1.1 mrg { 1439 1.1 mrg "cortex-a15", 1440 1.1 mrg cpu_opttab_cortexa15, 1441 1.1 mrg { 1442 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1443 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1444 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1445 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1446 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1447 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1448 1.1 mrg } 1449 1.1 mrg }, 1450 1.1.1.2 mrg NULL, 1451 1.1 mrg TARGET_ARCH_armv7ve 1452 1.1 mrg }, 1453 1.1 mrg { 1454 1.1 mrg { 1455 1.1 mrg "cortex-a17", 1456 1.1 mrg cpu_opttab_cortexa17, 1457 1.1 mrg { 1458 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1459 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1460 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1461 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1462 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1463 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1464 1.1 mrg } 1465 1.1 mrg }, 1466 1.1.1.2 mrg NULL, 1467 1.1 mrg TARGET_ARCH_armv7ve 1468 1.1 mrg }, 1469 1.1 mrg { 1470 1.1 mrg { 1471 1.1 mrg "cortex-r4", 1472 1.1 mrg NULL, 1473 1.1 mrg { 1474 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1475 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 1476 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 1477 1.1 mrg } 1478 1.1 mrg }, 1479 1.1.1.2 mrg NULL, 1480 1.1 mrg TARGET_ARCH_armv7_r 1481 1.1 mrg }, 1482 1.1 mrg { 1483 1.1 mrg { 1484 1.1 mrg "cortex-r4f", 1485 1.1 mrg NULL, 1486 1.1 mrg { 1487 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1488 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1489 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 1490 1.1.1.2 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1491 1.1 mrg } 1492 1.1 mrg }, 1493 1.1.1.2 mrg NULL, 1494 1.1 mrg TARGET_ARCH_armv7_r 1495 1.1 mrg }, 1496 1.1 mrg { 1497 1.1 mrg { 1498 1.1 mrg "cortex-r5", 1499 1.1 mrg cpu_opttab_cortexr5, 1500 1.1 mrg { 1501 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1502 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1503 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1504 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1505 1.1 mrg } 1506 1.1 mrg }, 1507 1.1.1.2 mrg NULL, 1508 1.1 mrg TARGET_ARCH_armv7_r 1509 1.1 mrg }, 1510 1.1 mrg { 1511 1.1 mrg { 1512 1.1 mrg "cortex-r7", 1513 1.1 mrg cpu_opttab_cortexr7, 1514 1.1 mrg { 1515 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1516 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1517 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1518 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1519 1.1.1.2 mrg isa_nobit 1520 1.1 mrg } 1521 1.1 mrg }, 1522 1.1.1.2 mrg NULL, 1523 1.1 mrg TARGET_ARCH_armv7_r 1524 1.1 mrg }, 1525 1.1 mrg { 1526 1.1 mrg { 1527 1.1 mrg "cortex-r8", 1528 1.1 mrg cpu_opttab_cortexr8, 1529 1.1 mrg { 1530 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1531 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1532 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1533 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1534 1.1.1.2 mrg isa_nobit 1535 1.1 mrg } 1536 1.1 mrg }, 1537 1.1.1.2 mrg NULL, 1538 1.1 mrg TARGET_ARCH_armv7_r 1539 1.1 mrg }, 1540 1.1 mrg { 1541 1.1 mrg { 1542 1.1 mrg "cortex-m7", 1543 1.1 mrg cpu_opttab_cortexm7, 1544 1.1 mrg { 1545 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1546 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1547 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5, 1548 1.1.1.2 mrg isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_thumb2, isa_bit_fp16conv, 1549 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 1550 1.1 mrg } 1551 1.1 mrg }, 1552 1.1.1.2 mrg NULL, 1553 1.1 mrg TARGET_ARCH_armv7e_m 1554 1.1 mrg }, 1555 1.1 mrg { 1556 1.1 mrg { 1557 1.1 mrg "cortex-m4", 1558 1.1 mrg cpu_opttab_cortexm4, 1559 1.1 mrg { 1560 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1561 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1562 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv, 1563 1.1.1.2 mrg isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 1564 1.1 mrg } 1565 1.1 mrg }, 1566 1.1.1.2 mrg NULL, 1567 1.1 mrg TARGET_ARCH_armv7e_m 1568 1.1 mrg }, 1569 1.1 mrg { 1570 1.1 mrg { 1571 1.1 mrg "cortex-m3", 1572 1.1 mrg NULL, 1573 1.1 mrg { 1574 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8, 1575 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, 1576 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 1577 1.1 mrg } 1578 1.1 mrg }, 1579 1.1.1.2 mrg NULL, 1580 1.1 mrg TARGET_ARCH_armv7_m 1581 1.1 mrg }, 1582 1.1 mrg { 1583 1.1 mrg { 1584 1.1 mrg "marvell-pj4", 1585 1.1 mrg NULL, 1586 1.1 mrg { 1587 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1588 1.1.1.3 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1589 1.1.1.3 mrg isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 1590 1.1.1.3 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1591 1.1 mrg } 1592 1.1 mrg }, 1593 1.1.1.2 mrg NULL, 1594 1.1 mrg TARGET_ARCH_armv7_a 1595 1.1 mrg }, 1596 1.1 mrg { 1597 1.1 mrg { 1598 1.1 mrg "cortex-a15.cortex-a7", 1599 1.1 mrg cpu_opttab_cortexa15cortexa7, 1600 1.1 mrg { 1601 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1602 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1603 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1604 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1605 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1606 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1607 1.1 mrg } 1608 1.1 mrg }, 1609 1.1.1.2 mrg NULL, 1610 1.1 mrg TARGET_ARCH_armv7ve 1611 1.1 mrg }, 1612 1.1 mrg { 1613 1.1 mrg { 1614 1.1 mrg "cortex-a17.cortex-a7", 1615 1.1 mrg cpu_opttab_cortexa17cortexa7, 1616 1.1 mrg { 1617 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1618 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1619 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1620 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1621 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1622 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1623 1.1 mrg } 1624 1.1 mrg }, 1625 1.1.1.2 mrg NULL, 1626 1.1 mrg TARGET_ARCH_armv7ve 1627 1.1 mrg }, 1628 1.1 mrg { 1629 1.1 mrg { 1630 1.1 mrg "cortex-a32", 1631 1.1 mrg cpu_opttab_cortexa32, 1632 1.1 mrg { 1633 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1634 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1635 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1636 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1637 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1638 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1639 1.1.1.2 mrg isa_bit_sec, isa_nobit 1640 1.1 mrg } 1641 1.1 mrg }, 1642 1.1.1.2 mrg NULL, 1643 1.1 mrg TARGET_ARCH_armv8_a 1644 1.1 mrg }, 1645 1.1 mrg { 1646 1.1 mrg { 1647 1.1 mrg "cortex-a35", 1648 1.1 mrg cpu_opttab_cortexa35, 1649 1.1 mrg { 1650 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1651 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1652 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1653 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1654 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1655 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1656 1.1.1.2 mrg isa_bit_sec, isa_nobit 1657 1.1 mrg } 1658 1.1 mrg }, 1659 1.1.1.2 mrg NULL, 1660 1.1 mrg TARGET_ARCH_armv8_a 1661 1.1 mrg }, 1662 1.1 mrg { 1663 1.1 mrg { 1664 1.1 mrg "cortex-a53", 1665 1.1 mrg cpu_opttab_cortexa53, 1666 1.1 mrg { 1667 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1668 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1669 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1670 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1671 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1672 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1673 1.1.1.2 mrg isa_bit_sec, isa_nobit 1674 1.1 mrg } 1675 1.1 mrg }, 1676 1.1.1.2 mrg NULL, 1677 1.1 mrg TARGET_ARCH_armv8_a 1678 1.1 mrg }, 1679 1.1 mrg { 1680 1.1 mrg { 1681 1.1 mrg "cortex-a57", 1682 1.1 mrg cpu_opttab_cortexa57, 1683 1.1 mrg { 1684 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1685 1.1.1.4 mrg isa_bit_quirk_aes_1742098, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1686 1.1.1.4 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1687 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1688 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1689 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1690 1.1.1.4 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1691 1.1 mrg } 1692 1.1 mrg }, 1693 1.1.1.2 mrg NULL, 1694 1.1 mrg TARGET_ARCH_armv8_a 1695 1.1 mrg }, 1696 1.1 mrg { 1697 1.1 mrg { 1698 1.1 mrg "cortex-a72", 1699 1.1 mrg cpu_opttab_cortexa72, 1700 1.1 mrg { 1701 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1702 1.1.1.4 mrg isa_bit_quirk_aes_1742098, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1703 1.1.1.4 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1704 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1705 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1706 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1707 1.1.1.4 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1708 1.1 mrg } 1709 1.1 mrg }, 1710 1.1.1.2 mrg NULL, 1711 1.1 mrg TARGET_ARCH_armv8_a 1712 1.1 mrg }, 1713 1.1 mrg { 1714 1.1 mrg { 1715 1.1 mrg "cortex-a73", 1716 1.1 mrg cpu_opttab_cortexa73, 1717 1.1 mrg { 1718 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1719 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1720 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1721 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1722 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1723 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1724 1.1.1.2 mrg isa_bit_sec, isa_nobit 1725 1.1 mrg } 1726 1.1 mrg }, 1727 1.1.1.2 mrg NULL, 1728 1.1 mrg TARGET_ARCH_armv8_a 1729 1.1 mrg }, 1730 1.1 mrg { 1731 1.1 mrg { 1732 1.1 mrg "exynos-m1", 1733 1.1 mrg cpu_opttab_exynosm1, 1734 1.1 mrg { 1735 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1736 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1737 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1738 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1739 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1740 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1741 1.1.1.2 mrg isa_bit_sec, isa_nobit 1742 1.1 mrg } 1743 1.1 mrg }, 1744 1.1.1.2 mrg NULL, 1745 1.1 mrg TARGET_ARCH_armv8_a 1746 1.1 mrg }, 1747 1.1 mrg { 1748 1.1 mrg { 1749 1.1 mrg "xgene1", 1750 1.1 mrg cpu_opttab_xgene1, 1751 1.1 mrg { 1752 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1753 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1754 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1755 1.1 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, 1756 1.1.1.2 mrg isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, 1757 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, 1758 1.1.1.2 mrg isa_nobit 1759 1.1 mrg } 1760 1.1 mrg }, 1761 1.1.1.2 mrg NULL, 1762 1.1 mrg TARGET_ARCH_armv8_a 1763 1.1 mrg }, 1764 1.1 mrg { 1765 1.1 mrg { 1766 1.1 mrg "cortex-a57.cortex-a53", 1767 1.1 mrg cpu_opttab_cortexa57cortexa53, 1768 1.1 mrg { 1769 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1770 1.1.1.4 mrg isa_bit_quirk_aes_1742098, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1771 1.1.1.4 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1772 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1773 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1774 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1775 1.1.1.4 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1776 1.1 mrg } 1777 1.1 mrg }, 1778 1.1.1.2 mrg NULL, 1779 1.1 mrg TARGET_ARCH_armv8_a 1780 1.1 mrg }, 1781 1.1 mrg { 1782 1.1 mrg { 1783 1.1 mrg "cortex-a72.cortex-a53", 1784 1.1 mrg cpu_opttab_cortexa72cortexa53, 1785 1.1 mrg { 1786 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1787 1.1.1.4 mrg isa_bit_quirk_aes_1742098, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1788 1.1.1.4 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1789 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1790 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1791 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1792 1.1.1.4 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1793 1.1 mrg } 1794 1.1 mrg }, 1795 1.1.1.2 mrg NULL, 1796 1.1 mrg TARGET_ARCH_armv8_a 1797 1.1 mrg }, 1798 1.1 mrg { 1799 1.1 mrg { 1800 1.1 mrg "cortex-a73.cortex-a35", 1801 1.1 mrg cpu_opttab_cortexa73cortexa35, 1802 1.1 mrg { 1803 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1804 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1805 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1806 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1807 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1808 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1809 1.1.1.2 mrg isa_bit_sec, isa_nobit 1810 1.1 mrg } 1811 1.1 mrg }, 1812 1.1.1.2 mrg NULL, 1813 1.1 mrg TARGET_ARCH_armv8_a 1814 1.1 mrg }, 1815 1.1 mrg { 1816 1.1 mrg { 1817 1.1 mrg "cortex-a73.cortex-a53", 1818 1.1 mrg cpu_opttab_cortexa73cortexa53, 1819 1.1 mrg { 1820 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1821 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1822 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1823 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1824 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1825 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1826 1.1.1.2 mrg isa_bit_sec, isa_nobit 1827 1.1 mrg } 1828 1.1 mrg }, 1829 1.1.1.2 mrg NULL, 1830 1.1 mrg TARGET_ARCH_armv8_a 1831 1.1 mrg }, 1832 1.1 mrg { 1833 1.1 mrg { 1834 1.1 mrg "cortex-a55", 1835 1.1 mrg cpu_opttab_cortexa55, 1836 1.1 mrg { 1837 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1838 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1839 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1840 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1841 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1842 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1843 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1844 1.1.1.2 mrg isa_bit_sec, isa_nobit 1845 1.1 mrg } 1846 1.1 mrg }, 1847 1.1.1.2 mrg NULL, 1848 1.1 mrg TARGET_ARCH_armv8_2_a 1849 1.1 mrg }, 1850 1.1 mrg { 1851 1.1 mrg { 1852 1.1 mrg "cortex-a75", 1853 1.1 mrg cpu_opttab_cortexa75, 1854 1.1 mrg { 1855 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1856 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1857 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1858 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1859 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1860 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1861 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1862 1.1.1.2 mrg isa_bit_sec, isa_nobit 1863 1.1.1.2 mrg } 1864 1.1.1.2 mrg }, 1865 1.1.1.2 mrg NULL, 1866 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 1867 1.1.1.2 mrg }, 1868 1.1.1.2 mrg { 1869 1.1.1.2 mrg { 1870 1.1.1.2 mrg "cortex-a76", 1871 1.1.1.2 mrg cpu_opttab_cortexa76, 1872 1.1.1.2 mrg { 1873 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1874 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1875 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1876 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1877 1.1.1.3 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1878 1.1.1.3 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1879 1.1.1.3 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1880 1.1.1.3 mrg isa_bit_sec, isa_nobit 1881 1.1.1.3 mrg } 1882 1.1.1.3 mrg }, 1883 1.1.1.3 mrg NULL, 1884 1.1.1.3 mrg TARGET_ARCH_armv8_2_a 1885 1.1.1.3 mrg }, 1886 1.1.1.3 mrg { 1887 1.1.1.3 mrg { 1888 1.1.1.3 mrg "cortex-a76ae", 1889 1.1.1.3 mrg cpu_opttab_cortexa76ae, 1890 1.1.1.3 mrg { 1891 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1892 1.1.1.3 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1893 1.1.1.3 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1894 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1895 1.1.1.3 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1896 1.1.1.3 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1897 1.1.1.3 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1898 1.1.1.3 mrg isa_bit_sec, isa_nobit 1899 1.1.1.3 mrg } 1900 1.1.1.3 mrg }, 1901 1.1.1.3 mrg NULL, 1902 1.1.1.3 mrg TARGET_ARCH_armv8_2_a 1903 1.1.1.3 mrg }, 1904 1.1.1.3 mrg { 1905 1.1.1.3 mrg { 1906 1.1.1.3 mrg "cortex-a77", 1907 1.1.1.3 mrg cpu_opttab_cortexa77, 1908 1.1.1.3 mrg { 1909 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1910 1.1.1.3 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1911 1.1.1.3 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1912 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1913 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1914 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1915 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1916 1.1.1.2 mrg isa_bit_sec, isa_nobit 1917 1.1.1.2 mrg } 1918 1.1.1.2 mrg }, 1919 1.1.1.2 mrg NULL, 1920 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 1921 1.1.1.2 mrg }, 1922 1.1.1.2 mrg { 1923 1.1.1.2 mrg { 1924 1.1.1.4 mrg "cortex-a78", 1925 1.1.1.4 mrg cpu_opttab_cortexa78, 1926 1.1.1.4 mrg { 1927 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1928 1.1.1.4 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1929 1.1.1.4 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1930 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1931 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1932 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1933 1.1.1.4 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1934 1.1.1.4 mrg isa_bit_sec, isa_nobit 1935 1.1.1.4 mrg } 1936 1.1.1.4 mrg }, 1937 1.1.1.4 mrg NULL, 1938 1.1.1.4 mrg TARGET_ARCH_armv8_2_a 1939 1.1.1.4 mrg }, 1940 1.1.1.4 mrg { 1941 1.1.1.4 mrg { 1942 1.1.1.4 mrg "cortex-a78ae", 1943 1.1.1.4 mrg cpu_opttab_cortexa78ae, 1944 1.1.1.4 mrg { 1945 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1946 1.1.1.4 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1947 1.1.1.4 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1948 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1949 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1950 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1951 1.1.1.4 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1952 1.1.1.4 mrg isa_bit_sec, isa_nobit 1953 1.1.1.4 mrg } 1954 1.1.1.4 mrg }, 1955 1.1.1.4 mrg NULL, 1956 1.1.1.4 mrg TARGET_ARCH_armv8_2_a 1957 1.1.1.4 mrg }, 1958 1.1.1.4 mrg { 1959 1.1.1.4 mrg { 1960 1.1.1.4 mrg "cortex-a78c", 1961 1.1.1.4 mrg cpu_opttab_cortexa78c, 1962 1.1.1.4 mrg { 1963 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1964 1.1.1.4 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1965 1.1.1.4 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1966 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1967 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1968 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1969 1.1.1.4 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1970 1.1.1.4 mrg isa_bit_sec, isa_nobit 1971 1.1.1.4 mrg } 1972 1.1.1.4 mrg }, 1973 1.1.1.4 mrg NULL, 1974 1.1.1.4 mrg TARGET_ARCH_armv8_2_a 1975 1.1.1.4 mrg }, 1976 1.1.1.4 mrg { 1977 1.1.1.4 mrg { 1978 1.1.1.4 mrg "cortex-a710", 1979 1.1.1.4 mrg cpu_opttab_cortexa710, 1980 1.1.1.4 mrg { 1981 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1982 1.1.1.4 mrg isa_bit_armv5te, isa_bit_i8mm, isa_bit_fp16fml, isa_bit_bf16, 1983 1.1.1.4 mrg isa_bit_sb, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1984 1.1.1.4 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1985 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 1986 1.1.1.4 mrg isa_bit_fpv5, isa_bit_armv9, isa_bit_tdiv, isa_bit_fp_d32, 1987 1.1.1.4 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, 1988 1.1.1.4 mrg isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, 1989 1.1.1.4 mrg isa_bit_mp, isa_bit_armv8_4, isa_bit_armv8_5, isa_bit_fp_dbl, 1990 1.1.1.4 mrg isa_bit_sec, isa_bit_predres, isa_nobit 1991 1.1.1.4 mrg } 1992 1.1.1.4 mrg }, 1993 1.1.1.4 mrg NULL, 1994 1.1.1.4 mrg TARGET_ARCH_armv9_a 1995 1.1.1.4 mrg }, 1996 1.1.1.4 mrg { 1997 1.1.1.4 mrg { 1998 1.1.1.4 mrg "cortex-x1", 1999 1.1.1.4 mrg cpu_opttab_cortexx1, 2000 1.1.1.4 mrg { 2001 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2002 1.1.1.4 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2003 1.1.1.4 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 2004 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2005 1.1.1.4 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 2006 1.1.1.4 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 2007 1.1.1.4 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2008 1.1.1.4 mrg isa_bit_sec, isa_nobit 2009 1.1.1.4 mrg } 2010 1.1.1.4 mrg }, 2011 1.1.1.4 mrg NULL, 2012 1.1.1.4 mrg TARGET_ARCH_armv8_2_a 2013 1.1.1.4 mrg }, 2014 1.1.1.4 mrg { 2015 1.1.1.4 mrg { 2016 1.1.1.2 mrg "neoverse-n1", 2017 1.1.1.2 mrg cpu_opttab_neoversen1, 2018 1.1.1.2 mrg { 2019 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2020 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2021 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 2022 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2023 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 2024 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 2025 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2026 1.1.1.2 mrg isa_bit_sec, isa_nobit 2027 1.1 mrg } 2028 1.1 mrg }, 2029 1.1.1.2 mrg cpu_aliastab_neoversen1, 2030 1.1 mrg TARGET_ARCH_armv8_2_a 2031 1.1 mrg }, 2032 1.1 mrg { 2033 1.1 mrg { 2034 1.1 mrg "cortex-a75.cortex-a55", 2035 1.1 mrg cpu_opttab_cortexa75cortexa55, 2036 1.1 mrg { 2037 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2038 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2039 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 2040 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2041 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 2042 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 2043 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2044 1.1.1.2 mrg isa_bit_sec, isa_nobit 2045 1.1.1.2 mrg } 2046 1.1.1.2 mrg }, 2047 1.1.1.2 mrg NULL, 2048 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 2049 1.1.1.2 mrg }, 2050 1.1.1.2 mrg { 2051 1.1.1.2 mrg { 2052 1.1.1.2 mrg "cortex-a76.cortex-a55", 2053 1.1.1.2 mrg cpu_opttab_cortexa76cortexa55, 2054 1.1.1.2 mrg { 2055 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2056 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2057 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 2058 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2059 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 2060 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 2061 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2062 1.1.1.2 mrg isa_bit_sec, isa_nobit 2063 1.1 mrg } 2064 1.1 mrg }, 2065 1.1.1.2 mrg NULL, 2066 1.1 mrg TARGET_ARCH_armv8_2_a 2067 1.1 mrg }, 2068 1.1 mrg { 2069 1.1 mrg { 2070 1.1.1.3 mrg "neoverse-v1", 2071 1.1.1.3 mrg cpu_opttab_neoversev1, 2072 1.1.1.3 mrg { 2073 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2074 1.1.1.3 mrg isa_bit_armv5te, isa_bit_i8mm, isa_bit_fp16fml, isa_bit_bf16, 2075 1.1.1.3 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_dotprod, 2076 1.1.1.3 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 2077 1.1.1.3 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 2078 1.1.1.3 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 2079 1.1.1.3 mrg isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, isa_bit_armv8_2, 2080 1.1.1.3 mrg isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp, 2081 1.1.1.3 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 2082 1.1.1.3 mrg } 2083 1.1.1.3 mrg }, 2084 1.1.1.3 mrg NULL, 2085 1.1.1.3 mrg TARGET_ARCH_armv8_4_a 2086 1.1.1.3 mrg }, 2087 1.1.1.3 mrg { 2088 1.1.1.3 mrg { 2089 1.1.1.3 mrg "neoverse-n2", 2090 1.1.1.3 mrg cpu_opttab_neoversen2, 2091 1.1.1.3 mrg { 2092 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2093 1.1.1.3 mrg isa_bit_armv5te, isa_bit_i8mm, isa_bit_fp16fml, isa_bit_bf16, 2094 1.1.1.3 mrg isa_bit_sb, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2095 1.1.1.3 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 2096 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2097 1.1.1.3 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 2098 1.1.1.3 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 2099 1.1.1.3 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 2100 1.1.1.3 mrg isa_bit_mp, isa_bit_armv8_5, isa_bit_fp_dbl, isa_bit_sec, 2101 1.1.1.3 mrg isa_bit_predres, isa_nobit 2102 1.1.1.3 mrg } 2103 1.1.1.3 mrg }, 2104 1.1.1.3 mrg NULL, 2105 1.1.1.3 mrg TARGET_ARCH_armv8_5_a 2106 1.1.1.3 mrg }, 2107 1.1.1.3 mrg { 2108 1.1.1.3 mrg { 2109 1.1 mrg "cortex-m23", 2110 1.1 mrg NULL, 2111 1.1 mrg { 2112 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2113 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse, 2114 1.1.1.2 mrg isa_bit_tdiv, isa_nobit 2115 1.1 mrg } 2116 1.1 mrg }, 2117 1.1.1.2 mrg NULL, 2118 1.1 mrg TARGET_ARCH_armv8_m_base 2119 1.1 mrg }, 2120 1.1 mrg { 2121 1.1 mrg { 2122 1.1 mrg "cortex-m33", 2123 1.1 mrg cpu_opttab_cortexm33, 2124 1.1 mrg { 2125 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 2126 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 2127 1.1.1.3 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8, 2128 1.1.1.3 mrg isa_bit_cmse, isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv, 2129 1.1.1.3 mrg isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 2130 1.1.1.3 mrg } 2131 1.1.1.3 mrg }, 2132 1.1.1.3 mrg NULL, 2133 1.1.1.3 mrg TARGET_ARCH_armv8_m_main 2134 1.1.1.3 mrg }, 2135 1.1.1.3 mrg { 2136 1.1.1.3 mrg { 2137 1.1.1.3 mrg "cortex-m35p", 2138 1.1.1.3 mrg cpu_opttab_cortexm35p, 2139 1.1.1.3 mrg { 2140 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 2141 1.1.1.3 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 2142 1.1.1.3 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8, 2143 1.1.1.3 mrg isa_bit_cmse, isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv, 2144 1.1.1.3 mrg isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 2145 1.1 mrg } 2146 1.1 mrg }, 2147 1.1.1.2 mrg NULL, 2148 1.1 mrg TARGET_ARCH_armv8_m_main 2149 1.1 mrg }, 2150 1.1 mrg { 2151 1.1 mrg { 2152 1.1.1.3 mrg "cortex-m55", 2153 1.1.1.3 mrg cpu_opttab_cortexm55, 2154 1.1.1.3 mrg { 2155 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_mve, 2156 1.1.1.3 mrg isa_bit_armv5te, isa_bit_quirk_no_asmcpu, isa_bit_thumb, isa_bit_be8, 2157 1.1.1.3 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv8_1m_main, isa_bit_armv6, 2158 1.1.1.3 mrg isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8, isa_bit_cmse, 2159 1.1.1.3 mrg isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv, isa_bit_thumb2, 2160 1.1.1.3 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_bit_mve_float, 2161 1.1.1.3 mrg isa_nobit 2162 1.1.1.3 mrg } 2163 1.1.1.3 mrg }, 2164 1.1.1.3 mrg NULL, 2165 1.1.1.3 mrg TARGET_ARCH_armv8_1_m_main 2166 1.1.1.3 mrg }, 2167 1.1.1.3 mrg { 2168 1.1.1.3 mrg { 2169 1.1 mrg "cortex-r52", 2170 1.1 mrg cpu_opttab_cortexr52, 2171 1.1 mrg { 2172 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2173 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2174 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 2175 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 2176 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 2177 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2178 1.1.1.2 mrg isa_bit_sec, isa_nobit 2179 1.1 mrg } 2180 1.1 mrg }, 2181 1.1.1.2 mrg NULL, 2182 1.1 mrg TARGET_ARCH_armv8_r 2183 1.1 mrg }, 2184 1.1.1.4 mrg { 2185 1.1.1.4 mrg { 2186 1.1.1.4 mrg "cortex-r52plus", 2187 1.1.1.4 mrg cpu_opttab_cortexr52plus, 2188 1.1.1.4 mrg { 2189 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2190 1.1.1.4 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2191 1.1.1.4 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 2192 1.1.1.4 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 2193 1.1.1.4 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 2194 1.1.1.4 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 2195 1.1.1.4 mrg isa_bit_sec, isa_nobit 2196 1.1.1.4 mrg } 2197 1.1.1.4 mrg }, 2198 1.1.1.4 mrg NULL, 2199 1.1.1.4 mrg TARGET_ARCH_armv8_r 2200 1.1.1.4 mrg }, 2201 1.1.1.2 mrg {{NULL, NULL, {isa_nobit}}, NULL, TARGET_ARCH_arm_none} 2202 1.1 mrg }; 2203 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5te[] = { 2204 1.1 mrg { 2205 1.1 mrg "fp", false, false, 2206 1.1 mrg { 2207 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2208 1.1 mrg } 2209 1.1 mrg }, 2210 1.1 mrg { 2211 1.1 mrg "nofp", true, false, 2212 1.1 mrg { 2213 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2214 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2215 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2216 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2217 1.1 mrg } 2218 1.1 mrg }, 2219 1.1 mrg { 2220 1.1 mrg "vfpv2", false, true, 2221 1.1 mrg { 2222 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2223 1.1 mrg } 2224 1.1 mrg }, 2225 1.1 mrg { NULL, false, false, {isa_nobit}} 2226 1.1 mrg }; 2227 1.1 mrg 2228 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5tej[] = { 2229 1.1 mrg { 2230 1.1 mrg "fp", false, false, 2231 1.1 mrg { 2232 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2233 1.1 mrg } 2234 1.1 mrg }, 2235 1.1 mrg { 2236 1.1 mrg "nofp", true, false, 2237 1.1 mrg { 2238 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2239 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2240 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2241 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2242 1.1 mrg } 2243 1.1 mrg }, 2244 1.1 mrg { 2245 1.1 mrg "vfpv2", false, true, 2246 1.1 mrg { 2247 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2248 1.1 mrg } 2249 1.1 mrg }, 2250 1.1 mrg { NULL, false, false, {isa_nobit}} 2251 1.1 mrg }; 2252 1.1 mrg 2253 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6[] = { 2254 1.1 mrg { 2255 1.1 mrg "fp", false, false, 2256 1.1 mrg { 2257 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2258 1.1 mrg } 2259 1.1 mrg }, 2260 1.1 mrg { 2261 1.1 mrg "nofp", true, false, 2262 1.1 mrg { 2263 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2264 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2265 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2266 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2267 1.1 mrg } 2268 1.1 mrg }, 2269 1.1 mrg { 2270 1.1 mrg "vfpv2", false, true, 2271 1.1 mrg { 2272 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2273 1.1 mrg } 2274 1.1 mrg }, 2275 1.1 mrg { NULL, false, false, {isa_nobit}} 2276 1.1 mrg }; 2277 1.1 mrg 2278 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6j[] = { 2279 1.1 mrg { 2280 1.1 mrg "fp", false, false, 2281 1.1 mrg { 2282 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2283 1.1 mrg } 2284 1.1 mrg }, 2285 1.1 mrg { 2286 1.1 mrg "nofp", true, false, 2287 1.1 mrg { 2288 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2289 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2290 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2291 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2292 1.1 mrg } 2293 1.1 mrg }, 2294 1.1 mrg { 2295 1.1 mrg "vfpv2", false, true, 2296 1.1 mrg { 2297 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2298 1.1 mrg } 2299 1.1 mrg }, 2300 1.1 mrg { NULL, false, false, {isa_nobit}} 2301 1.1 mrg }; 2302 1.1 mrg 2303 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6k[] = { 2304 1.1 mrg { 2305 1.1 mrg "fp", false, false, 2306 1.1 mrg { 2307 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2308 1.1 mrg } 2309 1.1 mrg }, 2310 1.1 mrg { 2311 1.1 mrg "nofp", true, false, 2312 1.1 mrg { 2313 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2314 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2315 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2316 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2317 1.1 mrg } 2318 1.1 mrg }, 2319 1.1 mrg { 2320 1.1 mrg "vfpv2", false, true, 2321 1.1 mrg { 2322 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2323 1.1 mrg } 2324 1.1 mrg }, 2325 1.1 mrg { NULL, false, false, {isa_nobit}} 2326 1.1 mrg }; 2327 1.1 mrg 2328 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6z[] = { 2329 1.1 mrg { 2330 1.1 mrg "fp", false, false, 2331 1.1 mrg { 2332 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2333 1.1 mrg } 2334 1.1 mrg }, 2335 1.1 mrg { 2336 1.1 mrg "nofp", true, false, 2337 1.1 mrg { 2338 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2339 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2340 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2341 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2342 1.1 mrg } 2343 1.1 mrg }, 2344 1.1 mrg { 2345 1.1 mrg "vfpv2", false, true, 2346 1.1 mrg { 2347 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2348 1.1 mrg } 2349 1.1 mrg }, 2350 1.1 mrg { NULL, false, false, {isa_nobit}} 2351 1.1 mrg }; 2352 1.1 mrg 2353 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6kz[] = { 2354 1.1 mrg { 2355 1.1 mrg "fp", false, false, 2356 1.1 mrg { 2357 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2358 1.1 mrg } 2359 1.1 mrg }, 2360 1.1 mrg { 2361 1.1 mrg "nofp", true, false, 2362 1.1 mrg { 2363 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2364 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2365 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2366 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2367 1.1 mrg } 2368 1.1 mrg }, 2369 1.1 mrg { 2370 1.1 mrg "vfpv2", false, true, 2371 1.1 mrg { 2372 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2373 1.1 mrg } 2374 1.1 mrg }, 2375 1.1 mrg { NULL, false, false, {isa_nobit}} 2376 1.1 mrg }; 2377 1.1 mrg 2378 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6zk[] = { 2379 1.1 mrg { 2380 1.1 mrg "fp", false, false, 2381 1.1 mrg { 2382 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2383 1.1 mrg } 2384 1.1 mrg }, 2385 1.1 mrg { 2386 1.1 mrg "nofp", true, false, 2387 1.1 mrg { 2388 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2389 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2390 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2391 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2392 1.1 mrg } 2393 1.1 mrg }, 2394 1.1 mrg { 2395 1.1 mrg "vfpv2", false, true, 2396 1.1 mrg { 2397 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2398 1.1 mrg } 2399 1.1 mrg }, 2400 1.1 mrg { NULL, false, false, {isa_nobit}} 2401 1.1 mrg }; 2402 1.1 mrg 2403 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6t2[] = { 2404 1.1 mrg { 2405 1.1 mrg "fp", false, false, 2406 1.1 mrg { 2407 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2408 1.1 mrg } 2409 1.1 mrg }, 2410 1.1 mrg { 2411 1.1 mrg "nofp", true, false, 2412 1.1 mrg { 2413 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2414 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2415 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2416 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2417 1.1 mrg } 2418 1.1 mrg }, 2419 1.1 mrg { 2420 1.1 mrg "vfpv2", false, true, 2421 1.1 mrg { 2422 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2423 1.1 mrg } 2424 1.1 mrg }, 2425 1.1 mrg { NULL, false, false, {isa_nobit}} 2426 1.1 mrg }; 2427 1.1 mrg 2428 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7[] = { 2429 1.1 mrg { 2430 1.1 mrg "fp", false, false, 2431 1.1 mrg { 2432 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2433 1.1 mrg } 2434 1.1 mrg }, 2435 1.1 mrg { 2436 1.1 mrg "nofp", true, false, 2437 1.1 mrg { 2438 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2439 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2440 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2441 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2442 1.1 mrg } 2443 1.1 mrg }, 2444 1.1 mrg { 2445 1.1 mrg "vfpv3-d16", false, true, 2446 1.1 mrg { 2447 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2448 1.1 mrg } 2449 1.1 mrg }, 2450 1.1 mrg { NULL, false, false, {isa_nobit}} 2451 1.1 mrg }; 2452 1.1 mrg 2453 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_a[] = { 2454 1.1 mrg { 2455 1.1 mrg "mp", false, false, 2456 1.1 mrg { 2457 1.1 mrg isa_bit_mp, isa_nobit 2458 1.1 mrg } 2459 1.1 mrg }, 2460 1.1 mrg { 2461 1.1 mrg "sec", false, false, 2462 1.1 mrg { 2463 1.1 mrg isa_bit_sec, isa_nobit 2464 1.1 mrg } 2465 1.1 mrg }, 2466 1.1 mrg { 2467 1.1 mrg "fp", false, false, 2468 1.1 mrg { 2469 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2470 1.1 mrg } 2471 1.1 mrg }, 2472 1.1 mrg { 2473 1.1 mrg "vfpv3", false, false, 2474 1.1 mrg { 2475 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2476 1.1 mrg isa_nobit 2477 1.1 mrg } 2478 1.1 mrg }, 2479 1.1 mrg { 2480 1.1 mrg "vfpv3-d16-fp16", false, false, 2481 1.1 mrg { 2482 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2483 1.1 mrg isa_nobit 2484 1.1 mrg } 2485 1.1 mrg }, 2486 1.1 mrg { 2487 1.1 mrg "vfpv3-fp16", false, false, 2488 1.1 mrg { 2489 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2490 1.1 mrg isa_bit_fp_dbl, isa_nobit 2491 1.1 mrg } 2492 1.1 mrg }, 2493 1.1 mrg { 2494 1.1 mrg "vfpv4-d16", false, false, 2495 1.1 mrg { 2496 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2497 1.1 mrg isa_bit_fp_dbl, isa_nobit 2498 1.1 mrg } 2499 1.1 mrg }, 2500 1.1 mrg { 2501 1.1 mrg "vfpv4", false, false, 2502 1.1 mrg { 2503 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2504 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2505 1.1 mrg } 2506 1.1 mrg }, 2507 1.1 mrg { 2508 1.1 mrg "simd", false, false, 2509 1.1 mrg { 2510 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2511 1.1 mrg isa_bit_fp_dbl, isa_nobit 2512 1.1 mrg } 2513 1.1 mrg }, 2514 1.1 mrg { 2515 1.1 mrg "neon-fp16", false, false, 2516 1.1 mrg { 2517 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2518 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2519 1.1 mrg } 2520 1.1 mrg }, 2521 1.1 mrg { 2522 1.1 mrg "neon-vfpv4", false, false, 2523 1.1 mrg { 2524 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2525 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2526 1.1 mrg } 2527 1.1 mrg }, 2528 1.1 mrg { 2529 1.1 mrg "nosimd", true, false, 2530 1.1 mrg { 2531 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 2532 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 2533 1.1 mrg } 2534 1.1 mrg }, 2535 1.1 mrg { 2536 1.1 mrg "nofp", true, false, 2537 1.1 mrg { 2538 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2539 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2540 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2541 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2542 1.1 mrg } 2543 1.1 mrg }, 2544 1.1 mrg { 2545 1.1 mrg "vfpv3-d16", false, true, 2546 1.1 mrg { 2547 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2548 1.1 mrg } 2549 1.1 mrg }, 2550 1.1 mrg { 2551 1.1 mrg "neon", false, true, 2552 1.1 mrg { 2553 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2554 1.1 mrg isa_bit_fp_dbl, isa_nobit 2555 1.1 mrg } 2556 1.1 mrg }, 2557 1.1 mrg { 2558 1.1 mrg "neon-vfpv3", false, true, 2559 1.1 mrg { 2560 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2561 1.1 mrg isa_bit_fp_dbl, isa_nobit 2562 1.1 mrg } 2563 1.1 mrg }, 2564 1.1 mrg { NULL, false, false, {isa_nobit}} 2565 1.1 mrg }; 2566 1.1 mrg 2567 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7ve[] = { 2568 1.1 mrg { 2569 1.1 mrg "vfpv3-d16", false, false, 2570 1.1 mrg { 2571 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2572 1.1 mrg } 2573 1.1 mrg }, 2574 1.1 mrg { 2575 1.1 mrg "vfpv3", false, false, 2576 1.1 mrg { 2577 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2578 1.1 mrg isa_nobit 2579 1.1 mrg } 2580 1.1 mrg }, 2581 1.1 mrg { 2582 1.1 mrg "vfpv3-d16-fp16", false, false, 2583 1.1 mrg { 2584 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2585 1.1 mrg isa_nobit 2586 1.1 mrg } 2587 1.1 mrg }, 2588 1.1 mrg { 2589 1.1 mrg "vfpv3-fp16", false, false, 2590 1.1 mrg { 2591 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2592 1.1 mrg isa_bit_fp_dbl, isa_nobit 2593 1.1 mrg } 2594 1.1 mrg }, 2595 1.1 mrg { 2596 1.1 mrg "fp", false, false, 2597 1.1 mrg { 2598 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2599 1.1 mrg isa_bit_fp_dbl, isa_nobit 2600 1.1 mrg } 2601 1.1 mrg }, 2602 1.1 mrg { 2603 1.1 mrg "vfpv4", false, false, 2604 1.1 mrg { 2605 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2606 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2607 1.1 mrg } 2608 1.1 mrg }, 2609 1.1 mrg { 2610 1.1 mrg "neon", false, false, 2611 1.1 mrg { 2612 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2613 1.1 mrg isa_bit_fp_dbl, isa_nobit 2614 1.1 mrg } 2615 1.1 mrg }, 2616 1.1 mrg { 2617 1.1 mrg "neon-fp16", false, false, 2618 1.1 mrg { 2619 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2620 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2621 1.1 mrg } 2622 1.1 mrg }, 2623 1.1 mrg { 2624 1.1 mrg "simd", false, false, 2625 1.1 mrg { 2626 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2627 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2628 1.1 mrg } 2629 1.1 mrg }, 2630 1.1 mrg { 2631 1.1 mrg "nosimd", true, false, 2632 1.1 mrg { 2633 1.1.1.3 mrg isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, 2634 1.1.1.3 mrg isa_bit_fp_d32, isa_bit_crypto, isa_nobit 2635 1.1 mrg } 2636 1.1 mrg }, 2637 1.1 mrg { 2638 1.1 mrg "nofp", true, false, 2639 1.1 mrg { 2640 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2641 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2642 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2643 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2644 1.1 mrg } 2645 1.1 mrg }, 2646 1.1 mrg { 2647 1.1 mrg "vfpv4-d16", false, true, 2648 1.1 mrg { 2649 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2650 1.1 mrg isa_bit_fp_dbl, isa_nobit 2651 1.1 mrg } 2652 1.1 mrg }, 2653 1.1 mrg { 2654 1.1 mrg "neon-vfpv3", false, true, 2655 1.1 mrg { 2656 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2657 1.1 mrg isa_bit_fp_dbl, isa_nobit 2658 1.1 mrg } 2659 1.1 mrg }, 2660 1.1 mrg { 2661 1.1 mrg "neon-vfpv4", false, true, 2662 1.1 mrg { 2663 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2664 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2665 1.1 mrg } 2666 1.1 mrg }, 2667 1.1 mrg { NULL, false, false, {isa_nobit}} 2668 1.1 mrg }; 2669 1.1 mrg 2670 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_r[] = { 2671 1.1 mrg { 2672 1.1 mrg "fp.sp", false, false, 2673 1.1 mrg { 2674 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2675 1.1 mrg } 2676 1.1 mrg }, 2677 1.1 mrg { 2678 1.1 mrg "fp", false, false, 2679 1.1 mrg { 2680 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2681 1.1 mrg } 2682 1.1 mrg }, 2683 1.1 mrg { 2684 1.1 mrg "vfpv3xd-fp16", false, false, 2685 1.1 mrg { 2686 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 2687 1.1 mrg } 2688 1.1 mrg }, 2689 1.1 mrg { 2690 1.1 mrg "vfpv3-d16-fp16", false, false, 2691 1.1 mrg { 2692 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2693 1.1 mrg isa_nobit 2694 1.1 mrg } 2695 1.1 mrg }, 2696 1.1 mrg { 2697 1.1 mrg "idiv", false, false, 2698 1.1 mrg { 2699 1.1 mrg isa_bit_adiv, isa_nobit 2700 1.1 mrg } 2701 1.1 mrg }, 2702 1.1 mrg { 2703 1.1 mrg "nofp", true, false, 2704 1.1 mrg { 2705 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2706 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2707 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2708 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2709 1.1 mrg } 2710 1.1 mrg }, 2711 1.1 mrg { 2712 1.1 mrg "noidiv", true, false, 2713 1.1 mrg { 2714 1.1 mrg isa_bit_adiv, isa_nobit 2715 1.1 mrg } 2716 1.1 mrg }, 2717 1.1 mrg { 2718 1.1 mrg "vfpv3xd", false, true, 2719 1.1 mrg { 2720 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2721 1.1 mrg } 2722 1.1 mrg }, 2723 1.1 mrg { 2724 1.1 mrg "vfpv3-d16", false, true, 2725 1.1 mrg { 2726 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2727 1.1 mrg } 2728 1.1 mrg }, 2729 1.1 mrg { NULL, false, false, {isa_nobit}} 2730 1.1 mrg }; 2731 1.1 mrg 2732 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { 2733 1.1 mrg { 2734 1.1 mrg "fp", false, false, 2735 1.1 mrg { 2736 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2737 1.1 mrg isa_nobit 2738 1.1 mrg } 2739 1.1 mrg }, 2740 1.1 mrg { 2741 1.1 mrg "fpv5", false, false, 2742 1.1 mrg { 2743 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2744 1.1 mrg isa_bit_fp16conv, isa_nobit 2745 1.1 mrg } 2746 1.1 mrg }, 2747 1.1 mrg { 2748 1.1 mrg "fp.dp", false, false, 2749 1.1 mrg { 2750 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2751 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2752 1.1 mrg } 2753 1.1 mrg }, 2754 1.1 mrg { 2755 1.1 mrg "nofp", true, false, 2756 1.1 mrg { 2757 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2758 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2759 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2760 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2761 1.1 mrg } 2762 1.1 mrg }, 2763 1.1 mrg { 2764 1.1 mrg "vfpv4-sp-d16", false, true, 2765 1.1 mrg { 2766 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2767 1.1 mrg isa_nobit 2768 1.1 mrg } 2769 1.1 mrg }, 2770 1.1 mrg { 2771 1.1 mrg "fpv5-d16", false, true, 2772 1.1 mrg { 2773 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2774 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2775 1.1 mrg } 2776 1.1 mrg }, 2777 1.1 mrg { NULL, false, false, {isa_nobit}} 2778 1.1 mrg }; 2779 1.1 mrg 2780 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_a[] = { 2781 1.1 mrg { 2782 1.1 mrg "crc", false, false, 2783 1.1 mrg { 2784 1.1 mrg isa_bit_crc32, isa_nobit 2785 1.1 mrg } 2786 1.1 mrg }, 2787 1.1 mrg { 2788 1.1 mrg "simd", false, false, 2789 1.1 mrg { 2790 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2791 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2792 1.1 mrg isa_nobit 2793 1.1 mrg } 2794 1.1 mrg }, 2795 1.1 mrg { 2796 1.1 mrg "crypto", false, false, 2797 1.1 mrg { 2798 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2799 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2800 1.1 mrg isa_bit_fp_dbl, isa_nobit 2801 1.1 mrg } 2802 1.1 mrg }, 2803 1.1 mrg { 2804 1.1 mrg "nocrypto", true, false, 2805 1.1 mrg { 2806 1.1 mrg isa_bit_crypto, isa_nobit 2807 1.1 mrg } 2808 1.1 mrg }, 2809 1.1 mrg { 2810 1.1 mrg "nofp", true, false, 2811 1.1 mrg { 2812 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2813 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2814 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2815 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2816 1.1 mrg } 2817 1.1 mrg }, 2818 1.1.1.2 mrg { 2819 1.1.1.2 mrg "sb", false, false, 2820 1.1.1.2 mrg { 2821 1.1.1.2 mrg isa_bit_sb, isa_nobit 2822 1.1.1.2 mrg } 2823 1.1.1.2 mrg }, 2824 1.1.1.2 mrg { 2825 1.1.1.2 mrg "predres", false, false, 2826 1.1.1.2 mrg { 2827 1.1.1.2 mrg isa_bit_predres, isa_nobit 2828 1.1.1.2 mrg } 2829 1.1.1.2 mrg }, 2830 1.1 mrg { NULL, false, false, {isa_nobit}} 2831 1.1 mrg }; 2832 1.1 mrg 2833 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { 2834 1.1 mrg { 2835 1.1 mrg "simd", false, false, 2836 1.1 mrg { 2837 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2838 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2839 1.1 mrg isa_nobit 2840 1.1 mrg } 2841 1.1 mrg }, 2842 1.1 mrg { 2843 1.1 mrg "crypto", false, false, 2844 1.1 mrg { 2845 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2846 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2847 1.1 mrg isa_bit_fp_dbl, isa_nobit 2848 1.1 mrg } 2849 1.1 mrg }, 2850 1.1 mrg { 2851 1.1 mrg "nocrypto", true, false, 2852 1.1 mrg { 2853 1.1 mrg isa_bit_crypto, isa_nobit 2854 1.1 mrg } 2855 1.1 mrg }, 2856 1.1 mrg { 2857 1.1 mrg "nofp", true, false, 2858 1.1 mrg { 2859 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2860 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2861 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2862 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2863 1.1 mrg } 2864 1.1 mrg }, 2865 1.1.1.2 mrg { 2866 1.1.1.2 mrg "sb", false, false, 2867 1.1.1.2 mrg { 2868 1.1.1.2 mrg isa_bit_sb, isa_nobit 2869 1.1.1.2 mrg } 2870 1.1.1.2 mrg }, 2871 1.1.1.2 mrg { 2872 1.1.1.2 mrg "predres", false, false, 2873 1.1.1.2 mrg { 2874 1.1.1.2 mrg isa_bit_predres, isa_nobit 2875 1.1.1.2 mrg } 2876 1.1.1.2 mrg }, 2877 1.1 mrg { NULL, false, false, {isa_nobit}} 2878 1.1 mrg }; 2879 1.1 mrg 2880 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { 2881 1.1 mrg { 2882 1.1 mrg "simd", false, false, 2883 1.1 mrg { 2884 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2885 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2886 1.1 mrg isa_nobit 2887 1.1 mrg } 2888 1.1 mrg }, 2889 1.1 mrg { 2890 1.1 mrg "fp16", false, false, 2891 1.1 mrg { 2892 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2893 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2894 1.1 mrg isa_bit_fp_dbl, isa_nobit 2895 1.1 mrg } 2896 1.1 mrg }, 2897 1.1 mrg { 2898 1.1 mrg "fp16fml", false, false, 2899 1.1 mrg { 2900 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2901 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2902 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2903 1.1 mrg } 2904 1.1 mrg }, 2905 1.1 mrg { 2906 1.1 mrg "crypto", false, false, 2907 1.1 mrg { 2908 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2909 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2910 1.1 mrg isa_bit_fp_dbl, isa_nobit 2911 1.1 mrg } 2912 1.1 mrg }, 2913 1.1 mrg { 2914 1.1 mrg "nocrypto", true, false, 2915 1.1 mrg { 2916 1.1 mrg isa_bit_crypto, isa_nobit 2917 1.1 mrg } 2918 1.1 mrg }, 2919 1.1 mrg { 2920 1.1 mrg "nofp", true, false, 2921 1.1 mrg { 2922 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2923 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 2924 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2925 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2926 1.1 mrg } 2927 1.1 mrg }, 2928 1.1 mrg { 2929 1.1 mrg "dotprod", false, false, 2930 1.1 mrg { 2931 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2932 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2933 1.1 mrg isa_bit_fp_dbl, isa_nobit 2934 1.1 mrg } 2935 1.1 mrg }, 2936 1.1.1.2 mrg { 2937 1.1.1.2 mrg "sb", false, false, 2938 1.1.1.2 mrg { 2939 1.1.1.2 mrg isa_bit_sb, isa_nobit 2940 1.1.1.2 mrg } 2941 1.1.1.2 mrg }, 2942 1.1.1.2 mrg { 2943 1.1.1.2 mrg "predres", false, false, 2944 1.1.1.2 mrg { 2945 1.1.1.2 mrg isa_bit_predres, isa_nobit 2946 1.1.1.2 mrg } 2947 1.1.1.2 mrg }, 2948 1.1.1.3 mrg { 2949 1.1.1.3 mrg "i8mm", false, false, 2950 1.1.1.3 mrg { 2951 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 2952 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2953 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 2954 1.1.1.3 mrg } 2955 1.1.1.3 mrg }, 2956 1.1.1.3 mrg { 2957 1.1.1.3 mrg "bf16", false, false, 2958 1.1.1.3 mrg { 2959 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 2960 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2961 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 2962 1.1.1.3 mrg } 2963 1.1.1.3 mrg }, 2964 1.1 mrg { NULL, false, false, {isa_nobit}} 2965 1.1 mrg }; 2966 1.1 mrg 2967 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = { 2968 1.1 mrg { 2969 1.1 mrg "simd", false, false, 2970 1.1 mrg { 2971 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2972 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2973 1.1 mrg isa_nobit 2974 1.1 mrg } 2975 1.1 mrg }, 2976 1.1 mrg { 2977 1.1 mrg "fp16", false, false, 2978 1.1 mrg { 2979 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2980 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2981 1.1 mrg isa_bit_fp_dbl, isa_nobit 2982 1.1 mrg } 2983 1.1 mrg }, 2984 1.1 mrg { 2985 1.1 mrg "fp16fml", false, false, 2986 1.1 mrg { 2987 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2988 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2989 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2990 1.1 mrg } 2991 1.1 mrg }, 2992 1.1 mrg { 2993 1.1 mrg "crypto", false, false, 2994 1.1 mrg { 2995 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2996 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2997 1.1 mrg isa_bit_fp_dbl, isa_nobit 2998 1.1 mrg } 2999 1.1 mrg }, 3000 1.1 mrg { 3001 1.1 mrg "nocrypto", true, false, 3002 1.1 mrg { 3003 1.1 mrg isa_bit_crypto, isa_nobit 3004 1.1 mrg } 3005 1.1 mrg }, 3006 1.1 mrg { 3007 1.1 mrg "nofp", true, false, 3008 1.1 mrg { 3009 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3010 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3011 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3012 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3013 1.1 mrg } 3014 1.1 mrg }, 3015 1.1 mrg { 3016 1.1 mrg "dotprod", false, false, 3017 1.1 mrg { 3018 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3019 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3020 1.1 mrg isa_bit_fp_dbl, isa_nobit 3021 1.1 mrg } 3022 1.1 mrg }, 3023 1.1.1.2 mrg { 3024 1.1.1.2 mrg "sb", false, false, 3025 1.1.1.2 mrg { 3026 1.1.1.2 mrg isa_bit_sb, isa_nobit 3027 1.1.1.2 mrg } 3028 1.1.1.2 mrg }, 3029 1.1.1.2 mrg { 3030 1.1.1.2 mrg "predres", false, false, 3031 1.1.1.2 mrg { 3032 1.1.1.2 mrg isa_bit_predres, isa_nobit 3033 1.1.1.2 mrg } 3034 1.1.1.2 mrg }, 3035 1.1.1.3 mrg { 3036 1.1.1.3 mrg "i8mm", false, false, 3037 1.1.1.3 mrg { 3038 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3039 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3040 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 3041 1.1.1.3 mrg } 3042 1.1.1.3 mrg }, 3043 1.1.1.3 mrg { 3044 1.1.1.3 mrg "bf16", false, false, 3045 1.1.1.3 mrg { 3046 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 3047 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3048 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 3049 1.1.1.3 mrg } 3050 1.1.1.3 mrg }, 3051 1.1 mrg { NULL, false, false, {isa_nobit}} 3052 1.1 mrg }; 3053 1.1 mrg 3054 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = { 3055 1.1 mrg { 3056 1.1 mrg "simd", false, false, 3057 1.1 mrg { 3058 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3059 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3060 1.1 mrg isa_bit_fp_dbl, isa_nobit 3061 1.1 mrg } 3062 1.1 mrg }, 3063 1.1 mrg { 3064 1.1 mrg "fp16", false, false, 3065 1.1 mrg { 3066 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 3067 1.1 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3068 1.1 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3069 1.1 mrg } 3070 1.1 mrg }, 3071 1.1 mrg { 3072 1.1 mrg "crypto", false, false, 3073 1.1 mrg { 3074 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3075 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3076 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3077 1.1 mrg } 3078 1.1 mrg }, 3079 1.1 mrg { 3080 1.1 mrg "nocrypto", true, false, 3081 1.1 mrg { 3082 1.1 mrg isa_bit_crypto, isa_nobit 3083 1.1 mrg } 3084 1.1 mrg }, 3085 1.1 mrg { 3086 1.1 mrg "nofp", true, false, 3087 1.1 mrg { 3088 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3089 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3090 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3091 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3092 1.1 mrg } 3093 1.1 mrg }, 3094 1.1.1.2 mrg { 3095 1.1.1.2 mrg "sb", false, false, 3096 1.1.1.2 mrg { 3097 1.1.1.2 mrg isa_bit_sb, isa_nobit 3098 1.1.1.2 mrg } 3099 1.1.1.2 mrg }, 3100 1.1.1.2 mrg { 3101 1.1.1.2 mrg "predres", false, false, 3102 1.1.1.2 mrg { 3103 1.1.1.2 mrg isa_bit_predres, isa_nobit 3104 1.1.1.2 mrg } 3105 1.1.1.2 mrg }, 3106 1.1.1.3 mrg { 3107 1.1.1.3 mrg "i8mm", false, false, 3108 1.1.1.3 mrg { 3109 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3110 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3111 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3112 1.1.1.3 mrg } 3113 1.1.1.3 mrg }, 3114 1.1.1.3 mrg { 3115 1.1.1.3 mrg "bf16", false, false, 3116 1.1.1.3 mrg { 3117 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 3118 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3119 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3120 1.1.1.3 mrg } 3121 1.1.1.3 mrg }, 3122 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 3123 1.1.1.2 mrg }; 3124 1.1.1.2 mrg 3125 1.1.1.2 mrg static const struct cpu_arch_extension arch_opttab_armv8_5_a[] = { 3126 1.1.1.2 mrg { 3127 1.1.1.2 mrg "simd", false, false, 3128 1.1.1.2 mrg { 3129 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3130 1.1.1.2 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3131 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 3132 1.1.1.2 mrg } 3133 1.1.1.2 mrg }, 3134 1.1.1.2 mrg { 3135 1.1.1.2 mrg "fp16", false, false, 3136 1.1.1.2 mrg { 3137 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 3138 1.1.1.2 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3139 1.1.1.2 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3140 1.1.1.2 mrg } 3141 1.1.1.2 mrg }, 3142 1.1.1.2 mrg { 3143 1.1.1.2 mrg "crypto", false, false, 3144 1.1.1.2 mrg { 3145 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3146 1.1.1.2 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3147 1.1.1.2 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3148 1.1.1.2 mrg } 3149 1.1.1.2 mrg }, 3150 1.1.1.2 mrg { 3151 1.1.1.2 mrg "nocrypto", true, false, 3152 1.1.1.2 mrg { 3153 1.1.1.2 mrg isa_bit_crypto, isa_nobit 3154 1.1.1.2 mrg } 3155 1.1.1.2 mrg }, 3156 1.1.1.2 mrg { 3157 1.1.1.2 mrg "nofp", true, false, 3158 1.1.1.2 mrg { 3159 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3160 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3161 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3162 1.1.1.3 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3163 1.1.1.3 mrg } 3164 1.1.1.3 mrg }, 3165 1.1.1.3 mrg { 3166 1.1.1.3 mrg "i8mm", false, false, 3167 1.1.1.3 mrg { 3168 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3169 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3170 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3171 1.1.1.3 mrg } 3172 1.1.1.3 mrg }, 3173 1.1.1.3 mrg { 3174 1.1.1.3 mrg "bf16", false, false, 3175 1.1.1.3 mrg { 3176 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 3177 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3178 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3179 1.1.1.3 mrg } 3180 1.1.1.3 mrg }, 3181 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 3182 1.1.1.3 mrg }; 3183 1.1.1.3 mrg 3184 1.1.1.3 mrg static const struct cpu_arch_extension arch_opttab_armv8_6_a[] = { 3185 1.1.1.3 mrg { 3186 1.1.1.3 mrg "simd", false, false, 3187 1.1.1.3 mrg { 3188 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3189 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3190 1.1.1.3 mrg isa_bit_fp_dbl, isa_nobit 3191 1.1.1.3 mrg } 3192 1.1.1.3 mrg }, 3193 1.1.1.3 mrg { 3194 1.1.1.3 mrg "fp16", false, false, 3195 1.1.1.3 mrg { 3196 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 3197 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3198 1.1.1.3 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3199 1.1.1.3 mrg } 3200 1.1.1.3 mrg }, 3201 1.1.1.3 mrg { 3202 1.1.1.3 mrg "crypto", false, false, 3203 1.1.1.3 mrg { 3204 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3205 1.1.1.3 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3206 1.1.1.3 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3207 1.1.1.3 mrg } 3208 1.1.1.3 mrg }, 3209 1.1.1.3 mrg { 3210 1.1.1.3 mrg "nocrypto", true, false, 3211 1.1.1.3 mrg { 3212 1.1.1.3 mrg isa_bit_crypto, isa_nobit 3213 1.1.1.3 mrg } 3214 1.1.1.3 mrg }, 3215 1.1.1.3 mrg { 3216 1.1.1.3 mrg "nofp", true, false, 3217 1.1.1.3 mrg { 3218 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3219 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3220 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3221 1.1.1.2 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3222 1.1.1.2 mrg } 3223 1.1.1.2 mrg }, 3224 1.1.1.3 mrg { 3225 1.1.1.3 mrg "i8mm", false, false, 3226 1.1.1.3 mrg { 3227 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3228 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3229 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3230 1.1.1.3 mrg } 3231 1.1.1.3 mrg }, 3232 1.1.1.3 mrg { 3233 1.1.1.3 mrg "bf16", false, false, 3234 1.1.1.3 mrg { 3235 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 3236 1.1.1.3 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3237 1.1.1.3 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3238 1.1.1.3 mrg } 3239 1.1.1.3 mrg }, 3240 1.1 mrg { NULL, false, false, {isa_nobit}} 3241 1.1 mrg }; 3242 1.1 mrg 3243 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { 3244 1.1 mrg { 3245 1.1 mrg "dsp", false, false, 3246 1.1 mrg { 3247 1.1 mrg isa_bit_armv7em, isa_nobit 3248 1.1 mrg } 3249 1.1 mrg }, 3250 1.1 mrg { 3251 1.1 mrg "fp", false, false, 3252 1.1 mrg { 3253 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3254 1.1 mrg isa_bit_fp16conv, isa_nobit 3255 1.1 mrg } 3256 1.1 mrg }, 3257 1.1 mrg { 3258 1.1 mrg "fp.dp", false, false, 3259 1.1 mrg { 3260 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3261 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3262 1.1 mrg } 3263 1.1 mrg }, 3264 1.1 mrg { 3265 1.1 mrg "nofp", true, false, 3266 1.1 mrg { 3267 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3268 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3269 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3270 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3271 1.1 mrg } 3272 1.1 mrg }, 3273 1.1 mrg { 3274 1.1 mrg "nodsp", true, false, 3275 1.1 mrg { 3276 1.1 mrg isa_bit_armv7em, isa_nobit 3277 1.1 mrg } 3278 1.1 mrg }, 3279 1.1.1.3 mrg { 3280 1.1.1.3 mrg "cdecp0", false, false, 3281 1.1.1.3 mrg { 3282 1.1.1.3 mrg isa_bit_cdecp0, isa_nobit 3283 1.1.1.3 mrg } 3284 1.1.1.3 mrg }, 3285 1.1.1.3 mrg { 3286 1.1.1.3 mrg "cdecp1", false, false, 3287 1.1.1.3 mrg { 3288 1.1.1.3 mrg isa_bit_cdecp1, isa_nobit 3289 1.1.1.3 mrg } 3290 1.1.1.3 mrg }, 3291 1.1.1.3 mrg { 3292 1.1.1.3 mrg "cdecp2", false, false, 3293 1.1.1.3 mrg { 3294 1.1.1.3 mrg isa_bit_cdecp2, isa_nobit 3295 1.1.1.3 mrg } 3296 1.1.1.3 mrg }, 3297 1.1.1.3 mrg { 3298 1.1.1.3 mrg "cdecp3", false, false, 3299 1.1.1.3 mrg { 3300 1.1.1.3 mrg isa_bit_cdecp3, isa_nobit 3301 1.1.1.3 mrg } 3302 1.1.1.3 mrg }, 3303 1.1.1.3 mrg { 3304 1.1.1.3 mrg "cdecp4", false, false, 3305 1.1.1.3 mrg { 3306 1.1.1.3 mrg isa_bit_cdecp4, isa_nobit 3307 1.1.1.3 mrg } 3308 1.1.1.3 mrg }, 3309 1.1.1.3 mrg { 3310 1.1.1.3 mrg "cdecp5", false, false, 3311 1.1.1.3 mrg { 3312 1.1.1.3 mrg isa_bit_cdecp5, isa_nobit 3313 1.1.1.3 mrg } 3314 1.1.1.3 mrg }, 3315 1.1.1.3 mrg { 3316 1.1.1.3 mrg "cdecp6", false, false, 3317 1.1.1.3 mrg { 3318 1.1.1.3 mrg isa_bit_cdecp6, isa_nobit 3319 1.1.1.3 mrg } 3320 1.1.1.3 mrg }, 3321 1.1.1.3 mrg { 3322 1.1.1.3 mrg "cdecp7", false, false, 3323 1.1.1.3 mrg { 3324 1.1.1.3 mrg isa_bit_cdecp7, isa_nobit 3325 1.1.1.3 mrg } 3326 1.1.1.3 mrg }, 3327 1.1 mrg { NULL, false, false, {isa_nobit}} 3328 1.1 mrg }; 3329 1.1 mrg 3330 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_r[] = { 3331 1.1 mrg { 3332 1.1 mrg "crc", false, false, 3333 1.1 mrg { 3334 1.1 mrg isa_bit_crc32, isa_nobit 3335 1.1 mrg } 3336 1.1 mrg }, 3337 1.1 mrg { 3338 1.1 mrg "fp.sp", false, false, 3339 1.1 mrg { 3340 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3341 1.1 mrg isa_bit_fp16conv, isa_nobit 3342 1.1 mrg } 3343 1.1 mrg }, 3344 1.1 mrg { 3345 1.1 mrg "simd", false, false, 3346 1.1 mrg { 3347 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3348 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 3349 1.1 mrg isa_nobit 3350 1.1 mrg } 3351 1.1 mrg }, 3352 1.1 mrg { 3353 1.1 mrg "crypto", false, false, 3354 1.1 mrg { 3355 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3356 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 3357 1.1 mrg isa_bit_fp_dbl, isa_nobit 3358 1.1 mrg } 3359 1.1 mrg }, 3360 1.1 mrg { 3361 1.1 mrg "nocrypto", true, false, 3362 1.1 mrg { 3363 1.1 mrg isa_bit_crypto, isa_nobit 3364 1.1 mrg } 3365 1.1 mrg }, 3366 1.1 mrg { 3367 1.1 mrg "nofp", true, false, 3368 1.1 mrg { 3369 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3370 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3371 1.1.1.3 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3372 1.1.1.3 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3373 1.1.1.3 mrg } 3374 1.1.1.3 mrg }, 3375 1.1.1.3 mrg { NULL, false, false, {isa_nobit}} 3376 1.1.1.3 mrg }; 3377 1.1.1.3 mrg 3378 1.1.1.3 mrg static const struct cpu_arch_extension arch_opttab_armv8_1_m_main[] = { 3379 1.1.1.3 mrg { 3380 1.1.1.3 mrg "dsp", false, false, 3381 1.1.1.3 mrg { 3382 1.1.1.3 mrg isa_bit_armv7em, isa_nobit 3383 1.1.1.3 mrg } 3384 1.1.1.3 mrg }, 3385 1.1.1.3 mrg { 3386 1.1.1.3 mrg "fp", false, false, 3387 1.1.1.3 mrg { 3388 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3389 1.1.1.3 mrg isa_bit_fp16, isa_bit_fp16conv, isa_nobit 3390 1.1.1.3 mrg } 3391 1.1.1.3 mrg }, 3392 1.1.1.3 mrg { 3393 1.1.1.3 mrg "fp.dp", false, false, 3394 1.1.1.3 mrg { 3395 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3396 1.1.1.3 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3397 1.1.1.3 mrg } 3398 1.1.1.3 mrg }, 3399 1.1.1.3 mrg { 3400 1.1.1.3 mrg "nofp", true, false, 3401 1.1.1.3 mrg { 3402 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3403 1.1.1.3 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3404 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3405 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3406 1.1 mrg } 3407 1.1 mrg }, 3408 1.1.1.3 mrg { 3409 1.1.1.3 mrg "mve", false, false, 3410 1.1.1.3 mrg { 3411 1.1.1.3 mrg isa_bit_mve, isa_bit_armv7em, isa_nobit 3412 1.1.1.3 mrg } 3413 1.1.1.3 mrg }, 3414 1.1.1.3 mrg { 3415 1.1.1.3 mrg "mve.fp", false, false, 3416 1.1.1.3 mrg { 3417 1.1.1.3 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_mve, 3418 1.1.1.3 mrg isa_bit_armv7em, isa_bit_fpv5, isa_bit_fp16, isa_bit_fp16conv, 3419 1.1.1.3 mrg isa_bit_mve_float, isa_nobit 3420 1.1.1.3 mrg } 3421 1.1.1.3 mrg }, 3422 1.1.1.3 mrg { 3423 1.1.1.3 mrg "cdecp0", false, false, 3424 1.1.1.3 mrg { 3425 1.1.1.3 mrg isa_bit_cdecp0, isa_nobit 3426 1.1.1.3 mrg } 3427 1.1.1.3 mrg }, 3428 1.1.1.3 mrg { 3429 1.1.1.3 mrg "cdecp1", false, false, 3430 1.1.1.3 mrg { 3431 1.1.1.3 mrg isa_bit_cdecp1, isa_nobit 3432 1.1.1.3 mrg } 3433 1.1.1.3 mrg }, 3434 1.1.1.3 mrg { 3435 1.1.1.3 mrg "cdecp2", false, false, 3436 1.1.1.3 mrg { 3437 1.1.1.3 mrg isa_bit_cdecp2, isa_nobit 3438 1.1.1.3 mrg } 3439 1.1.1.3 mrg }, 3440 1.1.1.3 mrg { 3441 1.1.1.3 mrg "cdecp3", false, false, 3442 1.1.1.3 mrg { 3443 1.1.1.3 mrg isa_bit_cdecp3, isa_nobit 3444 1.1.1.3 mrg } 3445 1.1.1.3 mrg }, 3446 1.1.1.3 mrg { 3447 1.1.1.3 mrg "cdecp4", false, false, 3448 1.1.1.3 mrg { 3449 1.1.1.3 mrg isa_bit_cdecp4, isa_nobit 3450 1.1.1.3 mrg } 3451 1.1.1.3 mrg }, 3452 1.1.1.3 mrg { 3453 1.1.1.3 mrg "cdecp5", false, false, 3454 1.1.1.3 mrg { 3455 1.1.1.3 mrg isa_bit_cdecp5, isa_nobit 3456 1.1.1.3 mrg } 3457 1.1.1.3 mrg }, 3458 1.1.1.3 mrg { 3459 1.1.1.3 mrg "cdecp6", false, false, 3460 1.1.1.3 mrg { 3461 1.1.1.3 mrg isa_bit_cdecp6, isa_nobit 3462 1.1.1.3 mrg } 3463 1.1.1.3 mrg }, 3464 1.1.1.3 mrg { 3465 1.1.1.3 mrg "cdecp7", false, false, 3466 1.1.1.3 mrg { 3467 1.1.1.3 mrg isa_bit_cdecp7, isa_nobit 3468 1.1.1.3 mrg } 3469 1.1.1.3 mrg }, 3470 1.1 mrg { NULL, false, false, {isa_nobit}} 3471 1.1 mrg }; 3472 1.1 mrg 3473 1.1.1.4 mrg static const struct cpu_arch_extension arch_opttab_armv9_a[] = { 3474 1.1.1.4 mrg { 3475 1.1.1.4 mrg "simd", false, false, 3476 1.1.1.4 mrg { 3477 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3478 1.1.1.4 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3479 1.1.1.4 mrg isa_bit_fp_dbl, isa_nobit 3480 1.1.1.4 mrg } 3481 1.1.1.4 mrg }, 3482 1.1.1.4 mrg { 3483 1.1.1.4 mrg "fp16", false, false, 3484 1.1.1.4 mrg { 3485 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 3486 1.1.1.4 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3487 1.1.1.4 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3488 1.1.1.4 mrg } 3489 1.1.1.4 mrg }, 3490 1.1.1.4 mrg { 3491 1.1.1.4 mrg "crypto", false, false, 3492 1.1.1.4 mrg { 3493 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 3494 1.1.1.4 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 3495 1.1.1.4 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3496 1.1.1.4 mrg } 3497 1.1.1.4 mrg }, 3498 1.1.1.4 mrg { 3499 1.1.1.4 mrg "nocrypto", true, false, 3500 1.1.1.4 mrg { 3501 1.1.1.4 mrg isa_bit_crypto, isa_nobit 3502 1.1.1.4 mrg } 3503 1.1.1.4 mrg }, 3504 1.1.1.4 mrg { 3505 1.1.1.4 mrg "nofp", true, false, 3506 1.1.1.4 mrg { 3507 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3508 1.1.1.4 mrg isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon, 3509 1.1.1.4 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 3510 1.1.1.4 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 3511 1.1.1.4 mrg } 3512 1.1.1.4 mrg }, 3513 1.1.1.4 mrg { 3514 1.1.1.4 mrg "i8mm", false, false, 3515 1.1.1.4 mrg { 3516 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm, 3517 1.1.1.4 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3518 1.1.1.4 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3519 1.1.1.4 mrg } 3520 1.1.1.4 mrg }, 3521 1.1.1.4 mrg { 3522 1.1.1.4 mrg "bf16", false, false, 3523 1.1.1.4 mrg { 3524 1.1.1.4 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16, 3525 1.1.1.4 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 3526 1.1.1.4 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3527 1.1.1.4 mrg } 3528 1.1.1.4 mrg }, 3529 1.1.1.4 mrg { NULL, false, false, {isa_nobit}} 3530 1.1.1.4 mrg }; 3531 1.1.1.4 mrg 3532 1.1 mrg const arch_option all_architectures[] = 3533 1.1 mrg { 3534 1.1 mrg { 3535 1.1 mrg "armv4", 3536 1.1 mrg NULL, 3537 1.1 mrg { 3538 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 3539 1.1 mrg }, 3540 1.1 mrg "4", BASE_ARCH_4, 3541 1.1 mrg 0, 3542 1.1 mrg TARGET_CPU_arm7tdmi, 3543 1.1 mrg }, 3544 1.1 mrg { 3545 1.1 mrg "armv4t", 3546 1.1 mrg NULL, 3547 1.1 mrg { 3548 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 3549 1.1 mrg }, 3550 1.1 mrg "4T", BASE_ARCH_4T, 3551 1.1 mrg 0, 3552 1.1 mrg TARGET_CPU_arm7tdmi, 3553 1.1 mrg }, 3554 1.1 mrg { 3555 1.1 mrg "armv5t", 3556 1.1 mrg NULL, 3557 1.1 mrg { 3558 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 3559 1.1.1.2 mrg isa_nobit 3560 1.1 mrg }, 3561 1.1 mrg "5T", BASE_ARCH_5T, 3562 1.1 mrg 0, 3563 1.1 mrg TARGET_CPU_arm10tdmi, 3564 1.1 mrg }, 3565 1.1 mrg { 3566 1.1 mrg "armv5te", 3567 1.1 mrg arch_opttab_armv5te, 3568 1.1 mrg { 3569 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 3570 1.1.1.2 mrg isa_bit_notm, isa_nobit 3571 1.1 mrg }, 3572 1.1 mrg "5TE", BASE_ARCH_5TE, 3573 1.1 mrg 0, 3574 1.1 mrg TARGET_CPU_arm1026ejs, 3575 1.1 mrg }, 3576 1.1 mrg { 3577 1.1 mrg "armv5tej", 3578 1.1 mrg arch_opttab_armv5tej, 3579 1.1 mrg { 3580 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 3581 1.1.1.2 mrg isa_bit_notm, isa_nobit 3582 1.1 mrg }, 3583 1.1 mrg "5TEJ", BASE_ARCH_5TEJ, 3584 1.1 mrg 0, 3585 1.1 mrg TARGET_CPU_arm1026ejs, 3586 1.1 mrg }, 3587 1.1 mrg { 3588 1.1 mrg "armv6", 3589 1.1 mrg arch_opttab_armv6, 3590 1.1 mrg { 3591 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3592 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 3593 1.1 mrg }, 3594 1.1 mrg "6", BASE_ARCH_6, 3595 1.1 mrg 0, 3596 1.1 mrg TARGET_CPU_arm1136js, 3597 1.1 mrg }, 3598 1.1 mrg { 3599 1.1 mrg "armv6j", 3600 1.1 mrg arch_opttab_armv6j, 3601 1.1 mrg { 3602 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3603 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 3604 1.1 mrg }, 3605 1.1 mrg "6J", BASE_ARCH_6J, 3606 1.1 mrg 0, 3607 1.1 mrg TARGET_CPU_arm1136js, 3608 1.1 mrg }, 3609 1.1 mrg { 3610 1.1 mrg "armv6k", 3611 1.1 mrg arch_opttab_armv6k, 3612 1.1 mrg { 3613 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3614 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 3615 1.1.1.2 mrg isa_nobit 3616 1.1 mrg }, 3617 1.1 mrg "6K", BASE_ARCH_6K, 3618 1.1 mrg 0, 3619 1.1 mrg TARGET_CPU_mpcore, 3620 1.1 mrg }, 3621 1.1 mrg { 3622 1.1 mrg "armv6z", 3623 1.1 mrg arch_opttab_armv6z, 3624 1.1 mrg { 3625 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3626 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 3627 1.1 mrg }, 3628 1.1 mrg "6Z", BASE_ARCH_6Z, 3629 1.1 mrg 0, 3630 1.1 mrg TARGET_CPU_arm1176jzs, 3631 1.1 mrg }, 3632 1.1 mrg { 3633 1.1 mrg "armv6kz", 3634 1.1 mrg arch_opttab_armv6kz, 3635 1.1 mrg { 3636 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3637 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm, 3638 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 3639 1.1 mrg }, 3640 1.1 mrg "6KZ", BASE_ARCH_6KZ, 3641 1.1 mrg 0, 3642 1.1 mrg TARGET_CPU_arm1176jzs, 3643 1.1 mrg }, 3644 1.1 mrg { 3645 1.1 mrg "armv6zk", 3646 1.1 mrg arch_opttab_armv6zk, 3647 1.1 mrg { 3648 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3649 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm, 3650 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 3651 1.1 mrg }, 3652 1.1 mrg "6KZ", BASE_ARCH_6KZ, 3653 1.1 mrg 0, 3654 1.1 mrg TARGET_CPU_arm1176jzs, 3655 1.1 mrg }, 3656 1.1 mrg { 3657 1.1 mrg "armv6t2", 3658 1.1 mrg arch_opttab_armv6t2, 3659 1.1 mrg { 3660 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3661 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 3662 1.1.1.2 mrg isa_nobit 3663 1.1 mrg }, 3664 1.1 mrg "6T2", BASE_ARCH_6T2, 3665 1.1 mrg 0, 3666 1.1 mrg TARGET_CPU_arm1156t2s, 3667 1.1 mrg }, 3668 1.1 mrg { 3669 1.1 mrg "armv6-m", 3670 1.1 mrg NULL, 3671 1.1 mrg { 3672 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3673 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 3674 1.1 mrg }, 3675 1.1 mrg "6M", BASE_ARCH_6M, 3676 1.1 mrg 'M', 3677 1.1 mrg TARGET_CPU_cortexm1, 3678 1.1 mrg }, 3679 1.1 mrg { 3680 1.1 mrg "armv6s-m", 3681 1.1 mrg NULL, 3682 1.1 mrg { 3683 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3684 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 3685 1.1 mrg }, 3686 1.1 mrg "6M", BASE_ARCH_6M, 3687 1.1 mrg 'M', 3688 1.1 mrg TARGET_CPU_cortexm1, 3689 1.1 mrg }, 3690 1.1 mrg { 3691 1.1 mrg "armv7", 3692 1.1 mrg arch_opttab_armv7, 3693 1.1 mrg { 3694 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3695 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 3696 1.1.1.2 mrg isa_nobit 3697 1.1 mrg }, 3698 1.1 mrg "7", BASE_ARCH_7, 3699 1.1 mrg 0, 3700 1.1.1.3 mrg TARGET_CPU_cortexa53, 3701 1.1 mrg }, 3702 1.1 mrg { 3703 1.1 mrg "armv7-a", 3704 1.1 mrg arch_opttab_armv7_a, 3705 1.1 mrg { 3706 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3707 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 3708 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_nobit 3709 1.1 mrg }, 3710 1.1 mrg "7A", BASE_ARCH_7A, 3711 1.1 mrg 'A', 3712 1.1.1.3 mrg TARGET_CPU_cortexa53, 3713 1.1 mrg }, 3714 1.1 mrg { 3715 1.1 mrg "armv7ve", 3716 1.1 mrg arch_opttab_armv7ve, 3717 1.1 mrg { 3718 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3719 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3720 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 3721 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 3722 1.1 mrg }, 3723 1.1 mrg "7A", BASE_ARCH_7A, 3724 1.1 mrg 'A', 3725 1.1.1.3 mrg TARGET_CPU_cortexa53, 3726 1.1 mrg }, 3727 1.1 mrg { 3728 1.1 mrg "armv7-r", 3729 1.1 mrg arch_opttab_armv7_r, 3730 1.1 mrg { 3731 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3732 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 3733 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 3734 1.1 mrg }, 3735 1.1 mrg "7R", BASE_ARCH_7R, 3736 1.1 mrg 'R', 3737 1.1 mrg TARGET_CPU_cortexr4, 3738 1.1 mrg }, 3739 1.1 mrg { 3740 1.1 mrg "armv7-m", 3741 1.1 mrg NULL, 3742 1.1 mrg { 3743 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3744 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 3745 1.1.1.2 mrg isa_bit_thumb2, isa_nobit 3746 1.1 mrg }, 3747 1.1 mrg "7M", BASE_ARCH_7M, 3748 1.1 mrg 'M', 3749 1.1 mrg TARGET_CPU_cortexm3, 3750 1.1 mrg }, 3751 1.1 mrg { 3752 1.1 mrg "armv7e-m", 3753 1.1 mrg arch_opttab_armv7e_m, 3754 1.1 mrg { 3755 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3756 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, 3757 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3758 1.1 mrg }, 3759 1.1 mrg "7EM", BASE_ARCH_7EM, 3760 1.1 mrg 'M', 3761 1.1 mrg TARGET_CPU_cortexm4, 3762 1.1 mrg }, 3763 1.1 mrg { 3764 1.1 mrg "armv8-a", 3765 1.1 mrg arch_opttab_armv8_a, 3766 1.1 mrg { 3767 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3768 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3769 1.1.1.2 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3770 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3771 1.1.1.2 mrg isa_nobit 3772 1.1 mrg }, 3773 1.1 mrg "8A", BASE_ARCH_8A, 3774 1.1 mrg 'A', 3775 1.1 mrg TARGET_CPU_cortexa53, 3776 1.1 mrg }, 3777 1.1 mrg { 3778 1.1 mrg "armv8.1-a", 3779 1.1 mrg arch_opttab_armv8_1_a, 3780 1.1 mrg { 3781 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3782 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3783 1.1 mrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3784 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3785 1.1.1.2 mrg isa_bit_mp, isa_bit_sec, isa_nobit 3786 1.1 mrg }, 3787 1.1 mrg "8A", BASE_ARCH_8A, 3788 1.1 mrg 'A', 3789 1.1 mrg TARGET_CPU_cortexa53, 3790 1.1 mrg }, 3791 1.1 mrg { 3792 1.1 mrg "armv8.2-a", 3793 1.1 mrg arch_opttab_armv8_2_a, 3794 1.1 mrg { 3795 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3796 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3797 1.1.1.3 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3798 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3799 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 3800 1.1 mrg }, 3801 1.1 mrg "8A", BASE_ARCH_8A, 3802 1.1 mrg 'A', 3803 1.1 mrg TARGET_CPU_cortexa53, 3804 1.1 mrg }, 3805 1.1 mrg { 3806 1.1 mrg "armv8.3-a", 3807 1.1 mrg arch_opttab_armv8_3_a, 3808 1.1 mrg { 3809 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3810 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3811 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3812 1.1.1.3 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3813 1.1.1.3 mrg isa_bit_armv6k, isa_bit_armv8_3, isa_bit_mp, isa_bit_sec, 3814 1.1.1.2 mrg isa_nobit 3815 1.1 mrg }, 3816 1.1 mrg "8A", BASE_ARCH_8A, 3817 1.1 mrg 'A', 3818 1.1 mrg TARGET_CPU_cortexa53, 3819 1.1 mrg }, 3820 1.1 mrg { 3821 1.1 mrg "armv8.4-a", 3822 1.1 mrg arch_opttab_armv8_4_a, 3823 1.1 mrg { 3824 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3825 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3826 1.1.1.3 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3827 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3828 1.1.1.2 mrg isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp, 3829 1.1.1.2 mrg isa_bit_sec, isa_nobit 3830 1.1.1.2 mrg }, 3831 1.1.1.2 mrg "8A", BASE_ARCH_8A, 3832 1.1.1.2 mrg 'A', 3833 1.1.1.2 mrg TARGET_CPU_cortexa53, 3834 1.1.1.2 mrg }, 3835 1.1.1.2 mrg { 3836 1.1.1.2 mrg "armv8.5-a", 3837 1.1.1.2 mrg arch_opttab_armv8_5_a, 3838 1.1.1.2 mrg { 3839 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3840 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3841 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 3842 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3843 1.1 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 3844 1.1.1.2 mrg isa_bit_mp, isa_bit_armv8_5, isa_bit_sec, isa_bit_predres, 3845 1.1.1.2 mrg isa_nobit 3846 1.1 mrg }, 3847 1.1 mrg "8A", BASE_ARCH_8A, 3848 1.1 mrg 'A', 3849 1.1 mrg TARGET_CPU_cortexa53, 3850 1.1 mrg }, 3851 1.1 mrg { 3852 1.1.1.3 mrg "armv8.6-a", 3853 1.1.1.3 mrg arch_opttab_armv8_6_a, 3854 1.1.1.3 mrg { 3855 1.1.1.3 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3856 1.1.1.3 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3857 1.1.1.3 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 3858 1.1.1.3 mrg isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3859 1.1.1.3 mrg isa_bit_armv6k, isa_bit_armv8_2, isa_bit_armv8_3, isa_bit_mp, 3860 1.1.1.3 mrg isa_bit_armv8_4, isa_bit_armv8_5, isa_bit_armv8_6, isa_bit_sec, 3861 1.1.1.3 mrg isa_bit_predres, isa_nobit 3862 1.1.1.3 mrg }, 3863 1.1.1.3 mrg "8A", BASE_ARCH_8A, 3864 1.1.1.3 mrg 'A', 3865 1.1.1.3 mrg TARGET_CPU_cortexa53, 3866 1.1.1.3 mrg }, 3867 1.1.1.3 mrg { 3868 1.1 mrg "armv8-m.base", 3869 1.1 mrg NULL, 3870 1.1 mrg { 3871 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3872 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse, 3873 1.1.1.2 mrg isa_bit_tdiv, isa_nobit 3874 1.1 mrg }, 3875 1.1 mrg "8M_BASE", BASE_ARCH_8M_BASE, 3876 1.1 mrg 'M', 3877 1.1 mrg TARGET_CPU_cortexm23, 3878 1.1 mrg }, 3879 1.1 mrg { 3880 1.1 mrg "armv8-m.main", 3881 1.1 mrg arch_opttab_armv8_m_main, 3882 1.1 mrg { 3883 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3884 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_armv8, 3885 1.1.1.3 mrg isa_bit_cmse, isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3886 1.1 mrg }, 3887 1.1 mrg "8M_MAIN", BASE_ARCH_8M_MAIN, 3888 1.1 mrg 'M', 3889 1.1 mrg TARGET_CPU_cortexm7, 3890 1.1 mrg }, 3891 1.1 mrg { 3892 1.1 mrg "armv8-r", 3893 1.1 mrg arch_opttab_armv8_r, 3894 1.1 mrg { 3895 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3896 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3897 1.1.1.2 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3898 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3899 1.1.1.2 mrg isa_nobit 3900 1.1 mrg }, 3901 1.1 mrg "8R", BASE_ARCH_8R, 3902 1.1 mrg 'R', 3903 1.1 mrg TARGET_CPU_cortexr52, 3904 1.1 mrg }, 3905 1.1 mrg { 3906 1.1.1.3 mrg "armv8.1-m.main", 3907 1.1.1.3 mrg arch_opttab_armv8_1_m_main, 3908 1.1.1.3 mrg { 3909 1.1.1.3 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3910 1.1.1.3 mrg isa_bit_armv4, isa_bit_armv8_1m_main, isa_bit_armv6, isa_bit_armv7, 3911 1.1.1.3 mrg isa_bit_armv8, isa_bit_cmse, isa_bit_tdiv, isa_bit_thumb2, 3912 1.1.1.3 mrg isa_nobit 3913 1.1.1.3 mrg }, 3914 1.1.1.3 mrg "8M_MAIN", BASE_ARCH_8M_MAIN, 3915 1.1.1.3 mrg 'M', 3916 1.1.1.4 mrg TARGET_CPU_cortexm55, 3917 1.1.1.4 mrg }, 3918 1.1.1.4 mrg { 3919 1.1.1.4 mrg "armv9-a", 3920 1.1.1.4 mrg arch_opttab_armv9_a, 3921 1.1.1.4 mrg { 3922 1.1.1.4 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3923 1.1.1.4 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3924 1.1.1.4 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 3925 1.1.1.4 mrg isa_bit_armv9, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 3926 1.1.1.4 mrg isa_bit_armv8_1, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, 3927 1.1.1.4 mrg isa_bit_mp, isa_bit_armv8_4, isa_bit_armv8_5, isa_bit_sec, 3928 1.1.1.4 mrg isa_bit_predres, isa_nobit 3929 1.1.1.4 mrg }, 3930 1.1.1.4 mrg "9A", BASE_ARCH_9A, 3931 1.1.1.4 mrg 'A', 3932 1.1.1.4 mrg TARGET_CPU_cortexa53, 3933 1.1.1.3 mrg }, 3934 1.1.1.3 mrg { 3935 1.1 mrg "iwmmxt", 3936 1.1 mrg NULL, 3937 1.1 mrg { 3938 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3939 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 3940 1.1 mrg }, 3941 1.1 mrg "5TE", BASE_ARCH_5TE, 3942 1.1 mrg 0, 3943 1.1 mrg TARGET_CPU_iwmmxt, 3944 1.1 mrg }, 3945 1.1 mrg { 3946 1.1 mrg "iwmmxt2", 3947 1.1 mrg NULL, 3948 1.1 mrg { 3949 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3950 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 3951 1.1.1.2 mrg isa_nobit 3952 1.1 mrg }, 3953 1.1 mrg "5TE", BASE_ARCH_5TE, 3954 1.1 mrg 0, 3955 1.1 mrg TARGET_CPU_iwmmxt2, 3956 1.1 mrg }, 3957 1.1 mrg {{NULL, NULL, {isa_nobit}}, 3958 1.1 mrg NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none} 3959 1.1 mrg }; 3960 1.1 mrg 3961 1.1 mrg const arm_fpu_desc all_fpus[] = 3962 1.1 mrg { 3963 1.1 mrg { 3964 1.1 mrg "vfp", 3965 1.1 mrg { 3966 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3967 1.1 mrg } 3968 1.1 mrg }, 3969 1.1 mrg { 3970 1.1 mrg "vfpv2", 3971 1.1 mrg { 3972 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3973 1.1 mrg } 3974 1.1 mrg }, 3975 1.1 mrg { 3976 1.1 mrg "vfpv3", 3977 1.1 mrg { 3978 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3979 1.1 mrg isa_nobit 3980 1.1 mrg } 3981 1.1 mrg }, 3982 1.1 mrg { 3983 1.1 mrg "vfpv3-fp16", 3984 1.1 mrg { 3985 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 3986 1.1 mrg isa_bit_fp_dbl, isa_nobit 3987 1.1 mrg } 3988 1.1 mrg }, 3989 1.1 mrg { 3990 1.1 mrg "vfpv3-d16", 3991 1.1 mrg { 3992 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 3993 1.1 mrg } 3994 1.1 mrg }, 3995 1.1 mrg { 3996 1.1 mrg "vfpv3-d16-fp16", 3997 1.1 mrg { 3998 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 3999 1.1 mrg isa_nobit 4000 1.1 mrg } 4001 1.1 mrg }, 4002 1.1 mrg { 4003 1.1 mrg "vfpv3xd", 4004 1.1 mrg { 4005 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 4006 1.1 mrg } 4007 1.1 mrg }, 4008 1.1 mrg { 4009 1.1 mrg "vfpv3xd-fp16", 4010 1.1 mrg { 4011 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 4012 1.1 mrg } 4013 1.1 mrg }, 4014 1.1 mrg { 4015 1.1 mrg "neon", 4016 1.1 mrg { 4017 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 4018 1.1 mrg isa_bit_fp_dbl, isa_nobit 4019 1.1 mrg } 4020 1.1 mrg }, 4021 1.1 mrg { 4022 1.1 mrg "neon-vfpv3", 4023 1.1 mrg { 4024 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 4025 1.1 mrg isa_bit_fp_dbl, isa_nobit 4026 1.1 mrg } 4027 1.1 mrg }, 4028 1.1 mrg { 4029 1.1 mrg "neon-fp16", 4030 1.1 mrg { 4031 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 4032 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 4033 1.1 mrg } 4034 1.1 mrg }, 4035 1.1 mrg { 4036 1.1 mrg "vfpv4", 4037 1.1 mrg { 4038 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 4039 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 4040 1.1 mrg } 4041 1.1 mrg }, 4042 1.1 mrg { 4043 1.1 mrg "neon-vfpv4", 4044 1.1 mrg { 4045 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 4046 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 4047 1.1 mrg } 4048 1.1 mrg }, 4049 1.1 mrg { 4050 1.1 mrg "vfpv4-d16", 4051 1.1 mrg { 4052 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 4053 1.1 mrg isa_bit_fp_dbl, isa_nobit 4054 1.1 mrg } 4055 1.1 mrg }, 4056 1.1 mrg { 4057 1.1 mrg "fpv4-sp-d16", 4058 1.1 mrg { 4059 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 4060 1.1 mrg isa_nobit 4061 1.1 mrg } 4062 1.1 mrg }, 4063 1.1 mrg { 4064 1.1 mrg "fpv5-sp-d16", 4065 1.1 mrg { 4066 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 4067 1.1 mrg isa_bit_fp16conv, isa_nobit 4068 1.1 mrg } 4069 1.1 mrg }, 4070 1.1 mrg { 4071 1.1 mrg "fpv5-d16", 4072 1.1 mrg { 4073 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 4074 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 4075 1.1 mrg } 4076 1.1 mrg }, 4077 1.1 mrg { 4078 1.1 mrg "fp-armv8", 4079 1.1 mrg { 4080 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 4081 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 4082 1.1 mrg } 4083 1.1 mrg }, 4084 1.1 mrg { 4085 1.1 mrg "neon-fp-armv8", 4086 1.1 mrg { 4087 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 4088 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 4089 1.1 mrg isa_nobit 4090 1.1 mrg } 4091 1.1 mrg }, 4092 1.1 mrg { 4093 1.1 mrg "crypto-neon-fp-armv8", 4094 1.1 mrg { 4095 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 4096 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 4097 1.1 mrg isa_bit_fp_dbl, isa_nobit 4098 1.1 mrg } 4099 1.1 mrg }, 4100 1.1 mrg { 4101 1.1 mrg "vfp3", 4102 1.1 mrg { 4103 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 4104 1.1 mrg isa_nobit 4105 1.1 mrg } 4106 1.1 mrg }, 4107 1.1 mrg }; 4108