arm-cpu-cdata.h revision 1.1.1.3 1 /* This file is automatically generated. DO NOT EDIT! */
2 /* Generated from: NetBSD: mknative-gcc,v 1.116 2022/07/22 06:50:26 mrg Exp */
3 /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */
4
5 /* -*- buffer-read-only: t -*-
6 Generated automatically by parsecpu.awk from arm-cpus.in.
7 Do not edit.
8
9 Copyright (C) 2011-2020 Free Software Foundation, Inc.
10
11 This file is part of GCC.
12
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 3,
16 or (at your option) any later version.
17
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public
24 License along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
26
27 static const cpu_alias cpu_aliastab_strongarm[] = {
28 { "strongarm110", true},
29 { "strongarm1100", false},
30 { "strongarm1110", false},
31 { NULL, false}
32 };
33
34 static const cpu_alias cpu_aliastab_arm7tdmi[] = {
35 { "arm7tdmi-s", true},
36 { NULL, false}
37 };
38
39 static const cpu_alias cpu_aliastab_arm710t[] = {
40 { "arm720t", true},
41 { "arm740t", true},
42 { NULL, false}
43 };
44
45 static const cpu_alias cpu_aliastab_arm920t[] = {
46 { "arm920", true},
47 { "arm922t", true},
48 { "arm940t", true},
49 { "ep9312", true},
50 { NULL, false}
51 };
52
53 static const cpu_alias cpu_aliastab_arm10tdmi[] = {
54 { "arm1020t", true},
55 { NULL, false}
56 };
57
58 static const cpu_arch_extension cpu_opttab_arm9e[] = {
59 {
60 "nofp", true, false,
61 {
62 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
63 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
64 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
65 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
66 }
67 },
68 { NULL, false, false, {isa_nobit}}
69 };
70
71 static const cpu_alias cpu_aliastab_arm9e[] = {
72 { "arm946e-s", true},
73 { "arm966e-s", true},
74 { "arm968e-s", true},
75 { NULL, false}
76 };
77
78 static const cpu_arch_extension cpu_opttab_arm10e[] = {
79 {
80 "nofp", true, false,
81 {
82 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
83 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
84 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
85 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
86 }
87 },
88 { NULL, false, false, {isa_nobit}}
89 };
90
91 static const cpu_alias cpu_aliastab_arm10e[] = {
92 { "arm1020e", true},
93 { "arm1022e", true},
94 { NULL, false}
95 };
96
97 static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
98 {
99 "nofp", true, false,
100 {
101 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
102 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
103 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
104 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
105 }
106 },
107 { NULL, false, false, {isa_nobit}}
108 };
109
110 static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
111 {
112 "nofp", true, false,
113 {
114 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
115 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
116 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
117 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
118 }
119 },
120 { NULL, false, false, {isa_nobit}}
121 };
122
123 static const cpu_arch_extension cpu_opttab_genericv7a[] = {
124 {
125 "mp", false, false,
126 {
127 isa_bit_mp, isa_nobit
128 }
129 },
130 {
131 "sec", false, false,
132 {
133 isa_bit_sec, isa_nobit
134 }
135 },
136 {
137 "vfpv3-d16", false, false,
138 {
139 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
140 }
141 },
142 {
143 "vfpv3", false, false,
144 {
145 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
146 isa_nobit
147 }
148 },
149 {
150 "vfpv3-d16-fp16", false, false,
151 {
152 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
153 isa_nobit
154 }
155 },
156 {
157 "vfpv3-fp16", false, false,
158 {
159 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
160 isa_bit_fp_dbl, isa_nobit
161 }
162 },
163 {
164 "vfpv4-d16", false, false,
165 {
166 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
167 isa_bit_fp_dbl, isa_nobit
168 }
169 },
170 {
171 "vfpv4", false, false,
172 {
173 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
174 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
175 }
176 },
177 {
178 "simd", false, false,
179 {
180 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
181 isa_bit_fp_dbl, isa_nobit
182 }
183 },
184 {
185 "neon-fp16", false, false,
186 {
187 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
188 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
189 }
190 },
191 {
192 "neon-vfpv4", false, false,
193 {
194 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
195 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
196 }
197 },
198 {
199 "nosimd", true, false,
200 {
201 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
202 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
203 }
204 },
205 {
206 "nofp", true, false,
207 {
208 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
209 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
210 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
211 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
212 }
213 },
214 {
215 "neon", false, true,
216 {
217 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
218 isa_bit_fp_dbl, isa_nobit
219 }
220 },
221 {
222 "neon-vfpv3", false, true,
223 {
224 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
225 isa_bit_fp_dbl, isa_nobit
226 }
227 },
228 { NULL, false, false, {isa_nobit}}
229 };
230
231 static const cpu_arch_extension cpu_opttab_cortexa5[] = {
232 {
233 "nosimd", true, false,
234 {
235 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
236 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
237 }
238 },
239 {
240 "nofp", true, false,
241 {
242 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
243 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
244 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
245 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
246 }
247 },
248 { NULL, false, false, {isa_nobit}}
249 };
250
251 static const cpu_arch_extension cpu_opttab_cortexa7[] = {
252 {
253 "nosimd", true, false,
254 {
255 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
256 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
257 }
258 },
259 {
260 "nofp", true, false,
261 {
262 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
263 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
264 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
265 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
266 }
267 },
268 { NULL, false, false, {isa_nobit}}
269 };
270
271 static const cpu_arch_extension cpu_opttab_cortexa8[] = {
272 {
273 "nofp", true, false,
274 {
275 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
276 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
277 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
278 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
279 }
280 },
281 { NULL, false, false, {isa_nobit}}
282 };
283
284 static const cpu_arch_extension cpu_opttab_cortexa9[] = {
285 {
286 "nosimd", true, false,
287 {
288 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
289 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
290 }
291 },
292 {
293 "nofp", true, false,
294 {
295 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
296 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
297 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
298 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
299 }
300 },
301 { NULL, false, false, {isa_nobit}}
302 };
303
304 static const cpu_arch_extension cpu_opttab_cortexa12[] = {
305 {
306 "nofp", true, false,
307 {
308 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
309 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
310 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
311 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
312 }
313 },
314 { NULL, false, false, {isa_nobit}}
315 };
316
317 static const cpu_arch_extension cpu_opttab_cortexa15[] = {
318 {
319 "nofp", true, false,
320 {
321 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
322 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
323 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
324 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
325 }
326 },
327 { NULL, false, false, {isa_nobit}}
328 };
329
330 static const cpu_arch_extension cpu_opttab_cortexa17[] = {
331 {
332 "nofp", true, false,
333 {
334 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
335 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
336 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
337 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
338 }
339 },
340 { NULL, false, false, {isa_nobit}}
341 };
342
343 static const cpu_arch_extension cpu_opttab_cortexr5[] = {
344 {
345 "nofp.dp", true, false,
346 {
347 isa_bit_fp_dbl, isa_nobit
348 }
349 },
350 {
351 "nofp", true, false,
352 {
353 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
354 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
355 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
356 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
357 }
358 },
359 { NULL, false, false, {isa_nobit}}
360 };
361
362 static const cpu_arch_extension cpu_opttab_cortexr7[] = {
363 {
364 "nofp.dp", true, false,
365 {
366 isa_bit_fp_dbl, isa_nobit
367 }
368 },
369 {
370 "nofp", true, false,
371 {
372 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
373 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
374 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
375 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
376 }
377 },
378 { NULL, false, false, {isa_nobit}}
379 };
380
381 static const cpu_arch_extension cpu_opttab_cortexr8[] = {
382 {
383 "nofp.dp", true, false,
384 {
385 isa_bit_fp_dbl, isa_nobit
386 }
387 },
388 {
389 "nofp", true, false,
390 {
391 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
392 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
393 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
394 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
395 }
396 },
397 { NULL, false, false, {isa_nobit}}
398 };
399
400 static const cpu_arch_extension cpu_opttab_cortexm7[] = {
401 {
402 "nofp.dp", true, false,
403 {
404 isa_bit_fp_dbl, isa_nobit
405 }
406 },
407 {
408 "nofp", true, false,
409 {
410 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
411 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
412 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
413 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
414 }
415 },
416 { NULL, false, false, {isa_nobit}}
417 };
418
419 static const cpu_arch_extension cpu_opttab_cortexm4[] = {
420 {
421 "nofp", true, false,
422 {
423 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
424 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
425 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
426 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
427 }
428 },
429 { NULL, false, false, {isa_nobit}}
430 };
431
432 static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
433 {
434 "nofp", true, false,
435 {
436 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
437 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
438 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
439 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
440 }
441 },
442 { NULL, false, false, {isa_nobit}}
443 };
444
445 static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
446 {
447 "nofp", true, false,
448 {
449 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
450 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
451 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
452 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
453 }
454 },
455 { NULL, false, false, {isa_nobit}}
456 };
457
458 static const cpu_arch_extension cpu_opttab_cortexa32[] = {
459 {
460 "crypto", false, false,
461 {
462 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
463 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
464 isa_bit_fp_dbl, isa_nobit
465 }
466 },
467 {
468 "nofp", true, false,
469 {
470 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
471 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
472 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
473 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
474 }
475 },
476 { NULL, false, false, {isa_nobit}}
477 };
478
479 static const cpu_arch_extension cpu_opttab_cortexa35[] = {
480 {
481 "crypto", false, false,
482 {
483 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
484 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
485 isa_bit_fp_dbl, isa_nobit
486 }
487 },
488 {
489 "nofp", true, false,
490 {
491 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
492 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
493 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
494 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
495 }
496 },
497 { NULL, false, false, {isa_nobit}}
498 };
499
500 static const cpu_arch_extension cpu_opttab_cortexa53[] = {
501 {
502 "crypto", false, false,
503 {
504 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
505 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
506 isa_bit_fp_dbl, isa_nobit
507 }
508 },
509 {
510 "nofp", true, false,
511 {
512 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
513 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
514 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
515 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
516 }
517 },
518 { NULL, false, false, {isa_nobit}}
519 };
520
521 static const cpu_arch_extension cpu_opttab_cortexa57[] = {
522 {
523 "crypto", false, false,
524 {
525 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
526 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
527 isa_bit_fp_dbl, isa_nobit
528 }
529 },
530 { NULL, false, false, {isa_nobit}}
531 };
532
533 static const cpu_arch_extension cpu_opttab_cortexa72[] = {
534 {
535 "crypto", false, false,
536 {
537 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
538 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
539 isa_bit_fp_dbl, isa_nobit
540 }
541 },
542 { NULL, false, false, {isa_nobit}}
543 };
544
545 static const cpu_arch_extension cpu_opttab_cortexa73[] = {
546 {
547 "crypto", false, false,
548 {
549 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
550 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
551 isa_bit_fp_dbl, isa_nobit
552 }
553 },
554 { NULL, false, false, {isa_nobit}}
555 };
556
557 static const cpu_arch_extension cpu_opttab_exynosm1[] = {
558 {
559 "crypto", false, false,
560 {
561 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
562 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
563 isa_bit_fp_dbl, isa_nobit
564 }
565 },
566 { NULL, false, false, {isa_nobit}}
567 };
568
569 static const cpu_arch_extension cpu_opttab_xgene1[] = {
570 {
571 "crypto", false, false,
572 {
573 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
574 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
575 isa_bit_fp_dbl, isa_nobit
576 }
577 },
578 { NULL, false, false, {isa_nobit}}
579 };
580
581 static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
582 {
583 "crypto", false, false,
584 {
585 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
586 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
587 isa_bit_fp_dbl, isa_nobit
588 }
589 },
590 { NULL, false, false, {isa_nobit}}
591 };
592
593 static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
594 {
595 "crypto", false, false,
596 {
597 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
598 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
599 isa_bit_fp_dbl, isa_nobit
600 }
601 },
602 { NULL, false, false, {isa_nobit}}
603 };
604
605 static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
606 {
607 "crypto", false, false,
608 {
609 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
610 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
611 isa_bit_fp_dbl, isa_nobit
612 }
613 },
614 { NULL, false, false, {isa_nobit}}
615 };
616
617 static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
618 {
619 "crypto", false, false,
620 {
621 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
622 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
623 isa_bit_fp_dbl, isa_nobit
624 }
625 },
626 { NULL, false, false, {isa_nobit}}
627 };
628
629 static const cpu_arch_extension cpu_opttab_cortexa55[] = {
630 {
631 "crypto", false, false,
632 {
633 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
634 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
635 isa_bit_fp_dbl, isa_nobit
636 }
637 },
638 {
639 "nofp", true, false,
640 {
641 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
642 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
643 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
644 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
645 }
646 },
647 { NULL, false, false, {isa_nobit}}
648 };
649
650 static const cpu_arch_extension cpu_opttab_cortexa75[] = {
651 {
652 "crypto", false, false,
653 {
654 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
655 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
656 isa_bit_fp_dbl, isa_nobit
657 }
658 },
659 { NULL, false, false, {isa_nobit}}
660 };
661
662 static const cpu_arch_extension cpu_opttab_cortexa76[] = {
663 {
664 "crypto", false, false,
665 {
666 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
667 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
668 isa_bit_fp_dbl, isa_nobit
669 }
670 },
671 { NULL, false, false, {isa_nobit}}
672 };
673
674 static const cpu_arch_extension cpu_opttab_cortexa76ae[] = {
675 {
676 "crypto", false, false,
677 {
678 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
679 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
680 isa_bit_fp_dbl, isa_nobit
681 }
682 },
683 { NULL, false, false, {isa_nobit}}
684 };
685
686 static const cpu_arch_extension cpu_opttab_cortexa77[] = {
687 {
688 "crypto", false, false,
689 {
690 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
691 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
692 isa_bit_fp_dbl, isa_nobit
693 }
694 },
695 { NULL, false, false, {isa_nobit}}
696 };
697
698 static const cpu_arch_extension cpu_opttab_neoversen1[] = {
699 {
700 "crypto", false, false,
701 {
702 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
703 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
704 isa_bit_fp_dbl, isa_nobit
705 }
706 },
707 { NULL, false, false, {isa_nobit}}
708 };
709
710 static const cpu_alias cpu_aliastab_neoversen1[] = {
711 { "ares", false},
712 { NULL, false}
713 };
714
715 static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = {
716 {
717 "crypto", false, false,
718 {
719 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
720 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
721 isa_bit_fp_dbl, isa_nobit
722 }
723 },
724 { NULL, false, false, {isa_nobit}}
725 };
726
727 static const cpu_arch_extension cpu_opttab_cortexa76cortexa55[] = {
728 {
729 "crypto", false, false,
730 {
731 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
732 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
733 isa_bit_fp_dbl, isa_nobit
734 }
735 },
736 { NULL, false, false, {isa_nobit}}
737 };
738
739 static const cpu_arch_extension cpu_opttab_neoversev1[] = {
740 {
741 "crypto", false, false,
742 {
743 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
744 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
745 isa_bit_fp_dbl, isa_nobit
746 }
747 },
748 { NULL, false, false, {isa_nobit}}
749 };
750
751 static const cpu_arch_extension cpu_opttab_neoversen2[] = {
752 {
753 "crypto", false, false,
754 {
755 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
756 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
757 isa_bit_fp_dbl, isa_nobit
758 }
759 },
760 { NULL, false, false, {isa_nobit}}
761 };
762
763 static const cpu_arch_extension cpu_opttab_cortexm33[] = {
764 {
765 "nofp", true, false,
766 {
767 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
768 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
769 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
770 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
771 }
772 },
773 {
774 "nodsp", true, false,
775 {
776 isa_bit_armv7em, isa_nobit
777 }
778 },
779 { NULL, false, false, {isa_nobit}}
780 };
781
782 static const cpu_arch_extension cpu_opttab_cortexm35p[] = {
783 {
784 "nofp", true, false,
785 {
786 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
787 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
788 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
789 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
790 }
791 },
792 {
793 "nodsp", true, false,
794 {
795 isa_bit_armv7em, isa_nobit
796 }
797 },
798 { NULL, false, false, {isa_nobit}}
799 };
800
801 static const cpu_arch_extension cpu_opttab_cortexm55[] = {
802 {
803 "nomve.fp", true, false,
804 {
805 isa_bit_mve_float, isa_nobit
806 }
807 },
808 {
809 "nomve", true, false,
810 {
811 isa_bit_mve, isa_bit_mve_float, isa_nobit
812 }
813 },
814 {
815 "nofp", true, false,
816 {
817 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
818 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
819 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
820 isa_bit_crypto, isa_bit_mve_float, isa_bit_fp_dbl, isa_nobit
821 }
822 },
823 {
824 "nodsp", true, false,
825 {
826 isa_bit_mve, isa_bit_armv7em, isa_bit_mve_float, isa_nobit
827 }
828 },
829 { NULL, false, false, {isa_nobit}}
830 };
831
832 static const cpu_arch_extension cpu_opttab_cortexr52[] = {
833 {
834 "nofp.dp", true, false,
835 {
836 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
837 isa_bit_fp_d32, isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
838 }
839 },
840 { NULL, false, false, {isa_nobit}}
841 };
842
843 const cpu_option all_cores[] =
844 {
845 {
846 {
847 "arm8",
848 NULL,
849 {
850 isa_bit_armv4, isa_bit_notm, isa_nobit
851 }
852 },
853 NULL,
854 TARGET_ARCH_armv4
855 },
856 {
857 {
858 "arm810",
859 NULL,
860 {
861 isa_bit_armv4, isa_bit_notm, isa_nobit
862 }
863 },
864 NULL,
865 TARGET_ARCH_armv4
866 },
867 {
868 {
869 "strongarm",
870 NULL,
871 {
872 isa_bit_armv4, isa_bit_notm, isa_nobit
873 }
874 },
875 cpu_aliastab_strongarm,
876 TARGET_ARCH_armv4
877 },
878 {
879 {
880 "fa526",
881 NULL,
882 {
883 isa_bit_armv4, isa_bit_notm, isa_nobit
884 }
885 },
886 NULL,
887 TARGET_ARCH_armv4
888 },
889 {
890 {
891 "fa626",
892 NULL,
893 {
894 isa_bit_armv4, isa_bit_notm, isa_nobit
895 }
896 },
897 NULL,
898 TARGET_ARCH_armv4
899 },
900 {
901 {
902 "arm7tdmi",
903 NULL,
904 {
905 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
906 }
907 },
908 cpu_aliastab_arm7tdmi,
909 TARGET_ARCH_armv4t
910 },
911 {
912 {
913 "arm710t",
914 NULL,
915 {
916 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
917 }
918 },
919 cpu_aliastab_arm710t,
920 TARGET_ARCH_armv4t
921 },
922 {
923 {
924 "arm9",
925 NULL,
926 {
927 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
928 }
929 },
930 NULL,
931 TARGET_ARCH_armv4t
932 },
933 {
934 {
935 "arm9tdmi",
936 NULL,
937 {
938 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
939 }
940 },
941 NULL,
942 TARGET_ARCH_armv4t
943 },
944 {
945 {
946 "arm920t",
947 NULL,
948 {
949 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
950 }
951 },
952 cpu_aliastab_arm920t,
953 TARGET_ARCH_armv4t
954 },
955 {
956 {
957 "arm10tdmi",
958 NULL,
959 {
960 isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm,
961 isa_nobit
962 }
963 },
964 cpu_aliastab_arm10tdmi,
965 TARGET_ARCH_armv5t
966 },
967 {
968 {
969 "arm9e",
970 cpu_opttab_arm9e,
971 {
972 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t,
973 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit
974 }
975 },
976 cpu_aliastab_arm9e,
977 TARGET_ARCH_armv5te
978 },
979 {
980 {
981 "arm10e",
982 cpu_opttab_arm10e,
983 {
984 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t,
985 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit
986 }
987 },
988 cpu_aliastab_arm10e,
989 TARGET_ARCH_armv5te
990 },
991 {
992 {
993 "xscale",
994 NULL,
995 {
996 isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, isa_bit_armv5t,
997 isa_bit_armv4, isa_bit_notm, isa_nobit
998 }
999 },
1000 NULL,
1001 TARGET_ARCH_armv5te
1002 },
1003 {
1004 {
1005 "iwmmxt",
1006 NULL,
1007 {
1008 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb,
1009 isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit
1010 }
1011 },
1012 NULL,
1013 TARGET_ARCH_iwmmxt
1014 },
1015 {
1016 {
1017 "iwmmxt2",
1018 NULL,
1019 {
1020 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb,
1021 isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm,
1022 isa_nobit
1023 }
1024 },
1025 NULL,
1026 TARGET_ARCH_iwmmxt2
1027 },
1028 {
1029 {
1030 "fa606te",
1031 NULL,
1032 {
1033 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
1034 isa_bit_notm, isa_nobit
1035 }
1036 },
1037 NULL,
1038 TARGET_ARCH_armv5te
1039 },
1040 {
1041 {
1042 "fa626te",
1043 NULL,
1044 {
1045 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
1046 isa_bit_notm, isa_nobit
1047 }
1048 },
1049 NULL,
1050 TARGET_ARCH_armv5te
1051 },
1052 {
1053 {
1054 "fmp626",
1055 NULL,
1056 {
1057 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
1058 isa_bit_notm, isa_nobit
1059 }
1060 },
1061 NULL,
1062 TARGET_ARCH_armv5te
1063 },
1064 {
1065 {
1066 "fa726te",
1067 NULL,
1068 {
1069 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
1070 isa_bit_notm, isa_nobit
1071 }
1072 },
1073 NULL,
1074 TARGET_ARCH_armv5te
1075 },
1076 {
1077 {
1078 "arm926ej-s",
1079 cpu_opttab_arm926ejs,
1080 {
1081 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t,
1082 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit
1083 }
1084 },
1085 NULL,
1086 TARGET_ARCH_armv5tej
1087 },
1088 {
1089 {
1090 "arm1026ej-s",
1091 cpu_opttab_arm1026ejs,
1092 {
1093 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t,
1094 isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit
1095 }
1096 },
1097 NULL,
1098 TARGET_ARCH_armv5tej
1099 },
1100 {
1101 {
1102 "arm1136j-s",
1103 NULL,
1104 {
1105 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1106 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit
1107 }
1108 },
1109 NULL,
1110 TARGET_ARCH_armv6j
1111 },
1112 {
1113 {
1114 "arm1136jf-s",
1115 NULL,
1116 {
1117 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
1118 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm,
1119 isa_bit_fp_dbl, isa_nobit
1120 }
1121 },
1122 NULL,
1123 TARGET_ARCH_armv6j
1124 },
1125 {
1126 {
1127 "arm1176jz-s",
1128 NULL,
1129 {
1130 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1131 isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm,
1132 isa_bit_armv6k, isa_nobit
1133 }
1134 },
1135 NULL,
1136 TARGET_ARCH_armv6kz
1137 },
1138 {
1139 {
1140 "arm1176jzf-s",
1141 NULL,
1142 {
1143 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
1144 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz,
1145 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit
1146 }
1147 },
1148 NULL,
1149 TARGET_ARCH_armv6kz
1150 },
1151 {
1152 {
1153 "mpcorenovfp",
1154 NULL,
1155 {
1156 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1157 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k,
1158 isa_nobit
1159 }
1160 },
1161 NULL,
1162 TARGET_ARCH_armv6k
1163 },
1164 {
1165 {
1166 "mpcore",
1167 NULL,
1168 {
1169 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
1170 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm,
1171 isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit
1172 }
1173 },
1174 NULL,
1175 TARGET_ARCH_armv6k
1176 },
1177 {
1178 {
1179 "arm1156t2-s",
1180 NULL,
1181 {
1182 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1183 isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm,
1184 isa_nobit
1185 }
1186 },
1187 NULL,
1188 TARGET_ARCH_armv6t2
1189 },
1190 {
1191 {
1192 "arm1156t2f-s",
1193 NULL,
1194 {
1195 isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
1196 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2,
1197 isa_bit_notm, isa_bit_fp_dbl, isa_nobit
1198 }
1199 },
1200 NULL,
1201 TARGET_ARCH_armv6t2
1202 },
1203 {
1204 {
1205 "cortex-m1",
1206 NULL,
1207 {
1208 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1209 isa_bit_armv4, isa_bit_armv6, isa_nobit
1210 }
1211 },
1212 NULL,
1213 TARGET_ARCH_armv6s_m
1214 },
1215 {
1216 {
1217 "cortex-m0",
1218 NULL,
1219 {
1220 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1221 isa_bit_armv4, isa_bit_armv6, isa_nobit
1222 }
1223 },
1224 NULL,
1225 TARGET_ARCH_armv6s_m
1226 },
1227 {
1228 {
1229 "cortex-m0plus",
1230 NULL,
1231 {
1232 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1233 isa_bit_armv4, isa_bit_armv6, isa_nobit
1234 }
1235 },
1236 NULL,
1237 TARGET_ARCH_armv6s_m
1238 },
1239 {
1240 {
1241 "cortex-m1.small-multiply",
1242 NULL,
1243 {
1244 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1245 isa_bit_armv4, isa_bit_armv6, isa_nobit
1246 }
1247 },
1248 NULL,
1249 TARGET_ARCH_armv6s_m
1250 },
1251 {
1252 {
1253 "cortex-m0.small-multiply",
1254 NULL,
1255 {
1256 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1257 isa_bit_armv4, isa_bit_armv6, isa_nobit
1258 }
1259 },
1260 NULL,
1261 TARGET_ARCH_armv6s_m
1262 },
1263 {
1264 {
1265 "cortex-m0plus.small-multiply",
1266 NULL,
1267 {
1268 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1269 isa_bit_armv4, isa_bit_armv6, isa_nobit
1270 }
1271 },
1272 NULL,
1273 TARGET_ARCH_armv6s_m
1274 },
1275 {
1276 {
1277 "generic-armv7-a",
1278 cpu_opttab_genericv7a,
1279 {
1280 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_quirk_no_asmcpu,
1281 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1282 isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, isa_bit_notm,
1283 isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit
1284 }
1285 },
1286 NULL,
1287 TARGET_ARCH_armv7_a
1288 },
1289 {
1290 {
1291 "cortex-a5",
1292 cpu_opttab_cortexa5,
1293 {
1294 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb,
1295 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon,
1296 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2,
1297 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1298 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1299 }
1300 },
1301 NULL,
1302 TARGET_ARCH_armv7_a
1303 },
1304 {
1305 {
1306 "cortex-a7",
1307 cpu_opttab_cortexa7,
1308 {
1309 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1310 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1311 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1312 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1313 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1314 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1315 }
1316 },
1317 NULL,
1318 TARGET_ARCH_armv7ve
1319 },
1320 {
1321 {
1322 "cortex-a8",
1323 cpu_opttab_cortexa8,
1324 {
1325 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb,
1326 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon,
1327 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2,
1328 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_sec,
1329 isa_nobit
1330 }
1331 },
1332 NULL,
1333 TARGET_ARCH_armv7_a
1334 },
1335 {
1336 {
1337 "cortex-a9",
1338 cpu_opttab_cortexa9,
1339 {
1340 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb,
1341 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon,
1342 isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2,
1343 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1344 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1345 }
1346 },
1347 NULL,
1348 TARGET_ARCH_armv7_a
1349 },
1350 {
1351 {
1352 "cortex-a12",
1353 cpu_opttab_cortexa12,
1354 {
1355 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1356 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1357 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1358 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1359 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1360 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1361 }
1362 },
1363 NULL,
1364 TARGET_ARCH_armv7ve
1365 },
1366 {
1367 {
1368 "cortex-a15",
1369 cpu_opttab_cortexa15,
1370 {
1371 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1372 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1373 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1374 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1375 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1376 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1377 }
1378 },
1379 NULL,
1380 TARGET_ARCH_armv7ve
1381 },
1382 {
1383 {
1384 "cortex-a17",
1385 cpu_opttab_cortexa17,
1386 {
1387 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1388 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1389 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1390 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1391 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1392 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1393 }
1394 },
1395 NULL,
1396 TARGET_ARCH_armv7ve
1397 },
1398 {
1399 {
1400 "cortex-r4",
1401 NULL,
1402 {
1403 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1404 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
1405 isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit
1406 }
1407 },
1408 NULL,
1409 TARGET_ARCH_armv7_r
1410 },
1411 {
1412 {
1413 "cortex-r4f",
1414 NULL,
1415 {
1416 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb,
1417 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6,
1418 isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm,
1419 isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit
1420 }
1421 },
1422 NULL,
1423 TARGET_ARCH_armv7_r
1424 },
1425 {
1426 {
1427 "cortex-r5",
1428 cpu_opttab_cortexr5,
1429 {
1430 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te,
1431 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1432 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2,
1433 isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit
1434 }
1435 },
1436 NULL,
1437 TARGET_ARCH_armv7_r
1438 },
1439 {
1440 {
1441 "cortex-r7",
1442 cpu_opttab_cortexr7,
1443 {
1444 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te,
1445 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1446 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2,
1447 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl,
1448 isa_nobit
1449 }
1450 },
1451 NULL,
1452 TARGET_ARCH_armv7_r
1453 },
1454 {
1455 {
1456 "cortex-r8",
1457 cpu_opttab_cortexr8,
1458 {
1459 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te,
1460 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1461 isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2,
1462 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl,
1463 isa_nobit
1464 }
1465 },
1466 NULL,
1467 TARGET_ARCH_armv7_r
1468 },
1469 {
1470 {
1471 "cortex-m7",
1472 cpu_opttab_cortexm7,
1473 {
1474 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te,
1475 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1476 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5,
1477 isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_thumb2, isa_bit_fp16conv,
1478 isa_bit_fp_dbl, isa_nobit
1479 }
1480 },
1481 NULL,
1482 TARGET_ARCH_armv7e_m
1483 },
1484 {
1485 {
1486 "cortex-m4",
1487 cpu_opttab_cortexm4,
1488 {
1489 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te,
1490 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1491 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv,
1492 isa_bit_thumb2, isa_bit_fp16conv, isa_nobit
1493 }
1494 },
1495 NULL,
1496 TARGET_ARCH_armv7e_m
1497 },
1498 {
1499 {
1500 "cortex-m3",
1501 NULL,
1502 {
1503 isa_bit_armv5te, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8,
1504 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_armv7,
1505 isa_bit_tdiv, isa_bit_thumb2, isa_nobit
1506 }
1507 },
1508 NULL,
1509 TARGET_ARCH_armv7_m
1510 },
1511 {
1512 {
1513 "marvell-pj4",
1514 NULL,
1515 {
1516 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb,
1517 isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6,
1518 isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k,
1519 isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1520 }
1521 },
1522 NULL,
1523 TARGET_ARCH_armv7_a
1524 },
1525 {
1526 {
1527 "cortex-a15.cortex-a7",
1528 cpu_opttab_cortexa15cortexa7,
1529 {
1530 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1531 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1532 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1533 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1534 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1535 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1536 }
1537 },
1538 NULL,
1539 TARGET_ARCH_armv7ve
1540 },
1541 {
1542 {
1543 "cortex-a17.cortex-a7",
1544 cpu_opttab_cortexa17cortexa7,
1545 {
1546 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1547 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1548 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1549 isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1550 isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1551 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1552 }
1553 },
1554 NULL,
1555 TARGET_ARCH_armv7ve
1556 },
1557 {
1558 {
1559 "cortex-a32",
1560 cpu_opttab_cortexa32,
1561 {
1562 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1563 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1564 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1565 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1566 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1567 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1568 isa_bit_sec, isa_nobit
1569 }
1570 },
1571 NULL,
1572 TARGET_ARCH_armv8_a
1573 },
1574 {
1575 {
1576 "cortex-a35",
1577 cpu_opttab_cortexa35,
1578 {
1579 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1580 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1581 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1582 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1583 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1584 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1585 isa_bit_sec, isa_nobit
1586 }
1587 },
1588 NULL,
1589 TARGET_ARCH_armv8_a
1590 },
1591 {
1592 {
1593 "cortex-a53",
1594 cpu_opttab_cortexa53,
1595 {
1596 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1597 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1598 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1599 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1600 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1601 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1602 isa_bit_sec, isa_nobit
1603 }
1604 },
1605 NULL,
1606 TARGET_ARCH_armv8_a
1607 },
1608 {
1609 {
1610 "cortex-a57",
1611 cpu_opttab_cortexa57,
1612 {
1613 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1614 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1615 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1616 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1617 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1618 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1619 isa_bit_sec, isa_nobit
1620 }
1621 },
1622 NULL,
1623 TARGET_ARCH_armv8_a
1624 },
1625 {
1626 {
1627 "cortex-a72",
1628 cpu_opttab_cortexa72,
1629 {
1630 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1631 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1632 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1633 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1634 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1635 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1636 isa_bit_sec, isa_nobit
1637 }
1638 },
1639 NULL,
1640 TARGET_ARCH_armv8_a
1641 },
1642 {
1643 {
1644 "cortex-a73",
1645 cpu_opttab_cortexa73,
1646 {
1647 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1648 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1649 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1650 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1651 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1652 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1653 isa_bit_sec, isa_nobit
1654 }
1655 },
1656 NULL,
1657 TARGET_ARCH_armv8_a
1658 },
1659 {
1660 {
1661 "exynos-m1",
1662 cpu_opttab_exynosm1,
1663 {
1664 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1665 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1666 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1667 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1668 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1669 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1670 isa_bit_sec, isa_nobit
1671 }
1672 },
1673 NULL,
1674 TARGET_ARCH_armv8_a
1675 },
1676 {
1677 {
1678 "xgene1",
1679 cpu_opttab_xgene1,
1680 {
1681 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1682 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1683 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1684 isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv,
1685 isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv,
1686 isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec,
1687 isa_nobit
1688 }
1689 },
1690 NULL,
1691 TARGET_ARCH_armv8_a
1692 },
1693 {
1694 {
1695 "cortex-a57.cortex-a53",
1696 cpu_opttab_cortexa57cortexa53,
1697 {
1698 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1699 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1700 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1701 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1702 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1703 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1704 isa_bit_sec, isa_nobit
1705 }
1706 },
1707 NULL,
1708 TARGET_ARCH_armv8_a
1709 },
1710 {
1711 {
1712 "cortex-a72.cortex-a53",
1713 cpu_opttab_cortexa72cortexa53,
1714 {
1715 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1716 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1717 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1718 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1719 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1720 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1721 isa_bit_sec, isa_nobit
1722 }
1723 },
1724 NULL,
1725 TARGET_ARCH_armv8_a
1726 },
1727 {
1728 {
1729 "cortex-a73.cortex-a35",
1730 cpu_opttab_cortexa73cortexa35,
1731 {
1732 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1733 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1734 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1735 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1736 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1737 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1738 isa_bit_sec, isa_nobit
1739 }
1740 },
1741 NULL,
1742 TARGET_ARCH_armv8_a
1743 },
1744 {
1745 {
1746 "cortex-a73.cortex-a53",
1747 cpu_opttab_cortexa73cortexa53,
1748 {
1749 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1750 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1751 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1752 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1753 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1754 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1755 isa_bit_sec, isa_nobit
1756 }
1757 },
1758 NULL,
1759 TARGET_ARCH_armv8_a
1760 },
1761 {
1762 {
1763 "cortex-a55",
1764 cpu_opttab_cortexa55,
1765 {
1766 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1767 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1768 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1769 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1770 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1771 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1772 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1773 isa_bit_sec, isa_nobit
1774 }
1775 },
1776 NULL,
1777 TARGET_ARCH_armv8_2_a
1778 },
1779 {
1780 {
1781 "cortex-a75",
1782 cpu_opttab_cortexa75,
1783 {
1784 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1785 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1786 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1787 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1788 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1789 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1790 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1791 isa_bit_sec, isa_nobit
1792 }
1793 },
1794 NULL,
1795 TARGET_ARCH_armv8_2_a
1796 },
1797 {
1798 {
1799 "cortex-a76",
1800 cpu_opttab_cortexa76,
1801 {
1802 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1803 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1804 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1805 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1806 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1807 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1808 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1809 isa_bit_sec, isa_nobit
1810 }
1811 },
1812 NULL,
1813 TARGET_ARCH_armv8_2_a
1814 },
1815 {
1816 {
1817 "cortex-a76ae",
1818 cpu_opttab_cortexa76ae,
1819 {
1820 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1821 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1822 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1823 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1824 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1825 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1826 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1827 isa_bit_sec, isa_nobit
1828 }
1829 },
1830 NULL,
1831 TARGET_ARCH_armv8_2_a
1832 },
1833 {
1834 {
1835 "cortex-a77",
1836 cpu_opttab_cortexa77,
1837 {
1838 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1839 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1840 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1841 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1842 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1843 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1844 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1845 isa_bit_sec, isa_nobit
1846 }
1847 },
1848 NULL,
1849 TARGET_ARCH_armv8_2_a
1850 },
1851 {
1852 {
1853 "neoverse-n1",
1854 cpu_opttab_neoversen1,
1855 {
1856 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1857 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1858 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1859 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1860 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1861 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1862 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1863 isa_bit_sec, isa_nobit
1864 }
1865 },
1866 cpu_aliastab_neoversen1,
1867 TARGET_ARCH_armv8_2_a
1868 },
1869 {
1870 {
1871 "cortex-a75.cortex-a55",
1872 cpu_opttab_cortexa75cortexa55,
1873 {
1874 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1875 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1876 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1877 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1878 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1879 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1880 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1881 isa_bit_sec, isa_nobit
1882 }
1883 },
1884 NULL,
1885 TARGET_ARCH_armv8_2_a
1886 },
1887 {
1888 {
1889 "cortex-a76.cortex-a55",
1890 cpu_opttab_cortexa76cortexa55,
1891 {
1892 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1893 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1894 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1895 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1896 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1897 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1898 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1899 isa_bit_sec, isa_nobit
1900 }
1901 },
1902 NULL,
1903 TARGET_ARCH_armv8_2_a
1904 },
1905 {
1906 {
1907 "neoverse-v1",
1908 cpu_opttab_neoversev1,
1909 {
1910 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1911 isa_bit_armv5te, isa_bit_i8mm, isa_bit_fp16fml, isa_bit_bf16,
1912 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_dotprod,
1913 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
1914 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1915 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
1916 isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, isa_bit_armv8_2,
1917 isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp,
1918 isa_bit_fp_dbl, isa_bit_sec, isa_nobit
1919 }
1920 },
1921 NULL,
1922 TARGET_ARCH_armv8_4_a
1923 },
1924 {
1925 {
1926 "neoverse-n2",
1927 cpu_opttab_neoversen2,
1928 {
1929 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1930 isa_bit_armv5te, isa_bit_i8mm, isa_bit_fp16fml, isa_bit_bf16,
1931 isa_bit_sb, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1932 isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon,
1933 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
1934 isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2,
1935 isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv,
1936 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4,
1937 isa_bit_mp, isa_bit_armv8_5, isa_bit_fp_dbl, isa_bit_sec,
1938 isa_bit_predres, isa_nobit
1939 }
1940 },
1941 NULL,
1942 TARGET_ARCH_armv8_5_a
1943 },
1944 {
1945 {
1946 "cortex-m23",
1947 NULL,
1948 {
1949 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
1950 isa_bit_armv4, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
1951 isa_bit_tdiv, isa_nobit
1952 }
1953 },
1954 NULL,
1955 TARGET_ARCH_armv8_m_base
1956 },
1957 {
1958 {
1959 "cortex-m33",
1960 cpu_opttab_cortexm33,
1961 {
1962 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te,
1963 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1964 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8,
1965 isa_bit_cmse, isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv,
1966 isa_bit_thumb2, isa_bit_fp16conv, isa_nobit
1967 }
1968 },
1969 NULL,
1970 TARGET_ARCH_armv8_m_main
1971 },
1972 {
1973 {
1974 "cortex-m35p",
1975 cpu_opttab_cortexm35p,
1976 {
1977 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te,
1978 isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4,
1979 isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8,
1980 isa_bit_cmse, isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv,
1981 isa_bit_thumb2, isa_bit_fp16conv, isa_nobit
1982 }
1983 },
1984 NULL,
1985 TARGET_ARCH_armv8_m_main
1986 },
1987 {
1988 {
1989 "cortex-m55",
1990 cpu_opttab_cortexm55,
1991 {
1992 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_mve,
1993 isa_bit_armv5te, isa_bit_quirk_no_asmcpu, isa_bit_thumb, isa_bit_be8,
1994 isa_bit_armv5t, isa_bit_armv4, isa_bit_armv8_1m_main, isa_bit_armv6,
1995 isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8, isa_bit_cmse,
1996 isa_bit_fpv5, isa_bit_quirk_vlldm, isa_bit_tdiv, isa_bit_thumb2,
1997 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_bit_mve_float,
1998 isa_nobit
1999 }
2000 },
2001 NULL,
2002 TARGET_ARCH_armv8_1_m_main
2003 },
2004 {
2005 {
2006 "cortex-r52",
2007 cpu_opttab_cortexr52,
2008 {
2009 isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2010 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
2011 isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6,
2012 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
2013 isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm,
2014 isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
2015 isa_bit_sec, isa_nobit
2016 }
2017 },
2018 NULL,
2019 TARGET_ARCH_armv8_r
2020 },
2021 {{NULL, NULL, {isa_nobit}}, NULL, TARGET_ARCH_arm_none}
2022 };
2023 static const struct cpu_arch_extension arch_opttab_armv5te[] = {
2024 {
2025 "fp", false, false,
2026 {
2027 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2028 }
2029 },
2030 {
2031 "nofp", true, false,
2032 {
2033 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2034 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2035 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2036 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2037 }
2038 },
2039 {
2040 "vfpv2", false, true,
2041 {
2042 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2043 }
2044 },
2045 { NULL, false, false, {isa_nobit}}
2046 };
2047
2048 static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
2049 {
2050 "fp", false, false,
2051 {
2052 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2053 }
2054 },
2055 {
2056 "nofp", true, false,
2057 {
2058 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2059 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2060 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2061 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2062 }
2063 },
2064 {
2065 "vfpv2", false, true,
2066 {
2067 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2068 }
2069 },
2070 { NULL, false, false, {isa_nobit}}
2071 };
2072
2073 static const struct cpu_arch_extension arch_opttab_armv6[] = {
2074 {
2075 "fp", false, false,
2076 {
2077 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2078 }
2079 },
2080 {
2081 "nofp", true, false,
2082 {
2083 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2084 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2085 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2086 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2087 }
2088 },
2089 {
2090 "vfpv2", false, true,
2091 {
2092 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2093 }
2094 },
2095 { NULL, false, false, {isa_nobit}}
2096 };
2097
2098 static const struct cpu_arch_extension arch_opttab_armv6j[] = {
2099 {
2100 "fp", false, false,
2101 {
2102 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2103 }
2104 },
2105 {
2106 "nofp", true, false,
2107 {
2108 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2109 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2110 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2111 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2112 }
2113 },
2114 {
2115 "vfpv2", false, true,
2116 {
2117 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2118 }
2119 },
2120 { NULL, false, false, {isa_nobit}}
2121 };
2122
2123 static const struct cpu_arch_extension arch_opttab_armv6k[] = {
2124 {
2125 "fp", false, false,
2126 {
2127 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2128 }
2129 },
2130 {
2131 "nofp", true, false,
2132 {
2133 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2134 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2135 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2136 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2137 }
2138 },
2139 {
2140 "vfpv2", false, true,
2141 {
2142 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2143 }
2144 },
2145 { NULL, false, false, {isa_nobit}}
2146 };
2147
2148 static const struct cpu_arch_extension arch_opttab_armv6z[] = {
2149 {
2150 "fp", false, false,
2151 {
2152 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2153 }
2154 },
2155 {
2156 "nofp", true, false,
2157 {
2158 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2159 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2160 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2161 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2162 }
2163 },
2164 {
2165 "vfpv2", false, true,
2166 {
2167 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2168 }
2169 },
2170 { NULL, false, false, {isa_nobit}}
2171 };
2172
2173 static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
2174 {
2175 "fp", false, false,
2176 {
2177 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2178 }
2179 },
2180 {
2181 "nofp", true, false,
2182 {
2183 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2184 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2185 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2186 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2187 }
2188 },
2189 {
2190 "vfpv2", false, true,
2191 {
2192 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2193 }
2194 },
2195 { NULL, false, false, {isa_nobit}}
2196 };
2197
2198 static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
2199 {
2200 "fp", false, false,
2201 {
2202 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2203 }
2204 },
2205 {
2206 "nofp", true, false,
2207 {
2208 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2209 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2210 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2211 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2212 }
2213 },
2214 {
2215 "vfpv2", false, true,
2216 {
2217 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2218 }
2219 },
2220 { NULL, false, false, {isa_nobit}}
2221 };
2222
2223 static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
2224 {
2225 "fp", false, false,
2226 {
2227 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2228 }
2229 },
2230 {
2231 "nofp", true, false,
2232 {
2233 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2234 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2235 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2236 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2237 }
2238 },
2239 {
2240 "vfpv2", false, true,
2241 {
2242 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2243 }
2244 },
2245 { NULL, false, false, {isa_nobit}}
2246 };
2247
2248 static const struct cpu_arch_extension arch_opttab_armv7[] = {
2249 {
2250 "fp", false, false,
2251 {
2252 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2253 }
2254 },
2255 {
2256 "nofp", true, false,
2257 {
2258 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2259 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2260 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2261 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2262 }
2263 },
2264 {
2265 "vfpv3-d16", false, true,
2266 {
2267 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2268 }
2269 },
2270 { NULL, false, false, {isa_nobit}}
2271 };
2272
2273 static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
2274 {
2275 "mp", false, false,
2276 {
2277 isa_bit_mp, isa_nobit
2278 }
2279 },
2280 {
2281 "sec", false, false,
2282 {
2283 isa_bit_sec, isa_nobit
2284 }
2285 },
2286 {
2287 "fp", false, false,
2288 {
2289 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2290 }
2291 },
2292 {
2293 "vfpv3", false, false,
2294 {
2295 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2296 isa_nobit
2297 }
2298 },
2299 {
2300 "vfpv3-d16-fp16", false, false,
2301 {
2302 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2303 isa_nobit
2304 }
2305 },
2306 {
2307 "vfpv3-fp16", false, false,
2308 {
2309 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2310 isa_bit_fp_dbl, isa_nobit
2311 }
2312 },
2313 {
2314 "vfpv4-d16", false, false,
2315 {
2316 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2317 isa_bit_fp_dbl, isa_nobit
2318 }
2319 },
2320 {
2321 "vfpv4", false, false,
2322 {
2323 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2324 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2325 }
2326 },
2327 {
2328 "simd", false, false,
2329 {
2330 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2331 isa_bit_fp_dbl, isa_nobit
2332 }
2333 },
2334 {
2335 "neon-fp16", false, false,
2336 {
2337 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2338 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2339 }
2340 },
2341 {
2342 "neon-vfpv4", false, false,
2343 {
2344 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2345 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2346 }
2347 },
2348 {
2349 "nosimd", true, false,
2350 {
2351 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
2352 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
2353 }
2354 },
2355 {
2356 "nofp", true, false,
2357 {
2358 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2359 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2360 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2361 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2362 }
2363 },
2364 {
2365 "vfpv3-d16", false, true,
2366 {
2367 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2368 }
2369 },
2370 {
2371 "neon", false, true,
2372 {
2373 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2374 isa_bit_fp_dbl, isa_nobit
2375 }
2376 },
2377 {
2378 "neon-vfpv3", false, true,
2379 {
2380 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2381 isa_bit_fp_dbl, isa_nobit
2382 }
2383 },
2384 { NULL, false, false, {isa_nobit}}
2385 };
2386
2387 static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
2388 {
2389 "vfpv3-d16", false, false,
2390 {
2391 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2392 }
2393 },
2394 {
2395 "vfpv3", false, false,
2396 {
2397 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2398 isa_nobit
2399 }
2400 },
2401 {
2402 "vfpv3-d16-fp16", false, false,
2403 {
2404 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2405 isa_nobit
2406 }
2407 },
2408 {
2409 "vfpv3-fp16", false, false,
2410 {
2411 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2412 isa_bit_fp_dbl, isa_nobit
2413 }
2414 },
2415 {
2416 "fp", false, false,
2417 {
2418 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2419 isa_bit_fp_dbl, isa_nobit
2420 }
2421 },
2422 {
2423 "vfpv4", false, false,
2424 {
2425 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2426 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2427 }
2428 },
2429 {
2430 "neon", false, false,
2431 {
2432 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2433 isa_bit_fp_dbl, isa_nobit
2434 }
2435 },
2436 {
2437 "neon-fp16", false, false,
2438 {
2439 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2440 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2441 }
2442 },
2443 {
2444 "simd", false, false,
2445 {
2446 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2447 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2448 }
2449 },
2450 {
2451 "nosimd", true, false,
2452 {
2453 isa_bit_i8mm, isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon,
2454 isa_bit_fp_d32, isa_bit_crypto, isa_nobit
2455 }
2456 },
2457 {
2458 "nofp", true, false,
2459 {
2460 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2461 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2462 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2463 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2464 }
2465 },
2466 {
2467 "vfpv4-d16", false, true,
2468 {
2469 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2470 isa_bit_fp_dbl, isa_nobit
2471 }
2472 },
2473 {
2474 "neon-vfpv3", false, true,
2475 {
2476 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2477 isa_bit_fp_dbl, isa_nobit
2478 }
2479 },
2480 {
2481 "neon-vfpv4", false, true,
2482 {
2483 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2484 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2485 }
2486 },
2487 { NULL, false, false, {isa_nobit}}
2488 };
2489
2490 static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
2491 {
2492 "fp.sp", false, false,
2493 {
2494 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2495 }
2496 },
2497 {
2498 "fp", false, false,
2499 {
2500 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2501 }
2502 },
2503 {
2504 "vfpv3xd-fp16", false, false,
2505 {
2506 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
2507 }
2508 },
2509 {
2510 "vfpv3-d16-fp16", false, false,
2511 {
2512 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2513 isa_nobit
2514 }
2515 },
2516 {
2517 "idiv", false, false,
2518 {
2519 isa_bit_adiv, isa_nobit
2520 }
2521 },
2522 {
2523 "nofp", true, false,
2524 {
2525 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2526 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2527 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2528 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2529 }
2530 },
2531 {
2532 "noidiv", true, false,
2533 {
2534 isa_bit_adiv, isa_nobit
2535 }
2536 },
2537 {
2538 "vfpv3xd", false, true,
2539 {
2540 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2541 }
2542 },
2543 {
2544 "vfpv3-d16", false, true,
2545 {
2546 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2547 }
2548 },
2549 { NULL, false, false, {isa_nobit}}
2550 };
2551
2552 static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
2553 {
2554 "fp", false, false,
2555 {
2556 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2557 isa_nobit
2558 }
2559 },
2560 {
2561 "fpv5", false, false,
2562 {
2563 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2564 isa_bit_fp16conv, isa_nobit
2565 }
2566 },
2567 {
2568 "fp.dp", false, false,
2569 {
2570 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2571 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2572 }
2573 },
2574 {
2575 "nofp", true, false,
2576 {
2577 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2578 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2579 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2580 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2581 }
2582 },
2583 {
2584 "vfpv4-sp-d16", false, true,
2585 {
2586 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2587 isa_nobit
2588 }
2589 },
2590 {
2591 "fpv5-d16", false, true,
2592 {
2593 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2594 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2595 }
2596 },
2597 { NULL, false, false, {isa_nobit}}
2598 };
2599
2600 static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
2601 {
2602 "crc", false, false,
2603 {
2604 isa_bit_crc32, isa_nobit
2605 }
2606 },
2607 {
2608 "simd", false, false,
2609 {
2610 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2611 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2612 isa_nobit
2613 }
2614 },
2615 {
2616 "crypto", false, false,
2617 {
2618 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2619 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2620 isa_bit_fp_dbl, isa_nobit
2621 }
2622 },
2623 {
2624 "nocrypto", true, false,
2625 {
2626 isa_bit_crypto, isa_nobit
2627 }
2628 },
2629 {
2630 "nofp", true, false,
2631 {
2632 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2633 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2634 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2635 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2636 }
2637 },
2638 {
2639 "sb", false, false,
2640 {
2641 isa_bit_sb, isa_nobit
2642 }
2643 },
2644 {
2645 "predres", false, false,
2646 {
2647 isa_bit_predres, isa_nobit
2648 }
2649 },
2650 { NULL, false, false, {isa_nobit}}
2651 };
2652
2653 static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
2654 {
2655 "simd", false, false,
2656 {
2657 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2658 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2659 isa_nobit
2660 }
2661 },
2662 {
2663 "crypto", false, false,
2664 {
2665 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2666 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2667 isa_bit_fp_dbl, isa_nobit
2668 }
2669 },
2670 {
2671 "nocrypto", true, false,
2672 {
2673 isa_bit_crypto, isa_nobit
2674 }
2675 },
2676 {
2677 "nofp", true, false,
2678 {
2679 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2680 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2681 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2682 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2683 }
2684 },
2685 {
2686 "sb", false, false,
2687 {
2688 isa_bit_sb, isa_nobit
2689 }
2690 },
2691 {
2692 "predres", false, false,
2693 {
2694 isa_bit_predres, isa_nobit
2695 }
2696 },
2697 { NULL, false, false, {isa_nobit}}
2698 };
2699
2700 static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
2701 {
2702 "simd", false, false,
2703 {
2704 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2705 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2706 isa_nobit
2707 }
2708 },
2709 {
2710 "fp16", false, false,
2711 {
2712 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2713 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2714 isa_bit_fp_dbl, isa_nobit
2715 }
2716 },
2717 {
2718 "fp16fml", false, false,
2719 {
2720 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2721 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2722 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2723 }
2724 },
2725 {
2726 "crypto", false, false,
2727 {
2728 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2729 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2730 isa_bit_fp_dbl, isa_nobit
2731 }
2732 },
2733 {
2734 "nocrypto", true, false,
2735 {
2736 isa_bit_crypto, isa_nobit
2737 }
2738 },
2739 {
2740 "nofp", true, false,
2741 {
2742 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2743 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2744 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2745 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2746 }
2747 },
2748 {
2749 "dotprod", false, false,
2750 {
2751 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2752 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2753 isa_bit_fp_dbl, isa_nobit
2754 }
2755 },
2756 {
2757 "sb", false, false,
2758 {
2759 isa_bit_sb, isa_nobit
2760 }
2761 },
2762 {
2763 "predres", false, false,
2764 {
2765 isa_bit_predres, isa_nobit
2766 }
2767 },
2768 {
2769 "i8mm", false, false,
2770 {
2771 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2772 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2773 isa_bit_fp_dbl, isa_nobit
2774 }
2775 },
2776 {
2777 "bf16", false, false,
2778 {
2779 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16,
2780 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2781 isa_bit_fp_dbl, isa_nobit
2782 }
2783 },
2784 { NULL, false, false, {isa_nobit}}
2785 };
2786
2787 static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = {
2788 {
2789 "simd", false, false,
2790 {
2791 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2792 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2793 isa_nobit
2794 }
2795 },
2796 {
2797 "fp16", false, false,
2798 {
2799 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2800 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2801 isa_bit_fp_dbl, isa_nobit
2802 }
2803 },
2804 {
2805 "fp16fml", false, false,
2806 {
2807 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2808 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2809 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2810 }
2811 },
2812 {
2813 "crypto", false, false,
2814 {
2815 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2816 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2817 isa_bit_fp_dbl, isa_nobit
2818 }
2819 },
2820 {
2821 "nocrypto", true, false,
2822 {
2823 isa_bit_crypto, isa_nobit
2824 }
2825 },
2826 {
2827 "nofp", true, false,
2828 {
2829 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2830 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2831 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2832 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2833 }
2834 },
2835 {
2836 "dotprod", false, false,
2837 {
2838 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2839 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2840 isa_bit_fp_dbl, isa_nobit
2841 }
2842 },
2843 {
2844 "sb", false, false,
2845 {
2846 isa_bit_sb, isa_nobit
2847 }
2848 },
2849 {
2850 "predres", false, false,
2851 {
2852 isa_bit_predres, isa_nobit
2853 }
2854 },
2855 {
2856 "i8mm", false, false,
2857 {
2858 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2859 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2860 isa_bit_fp_dbl, isa_nobit
2861 }
2862 },
2863 {
2864 "bf16", false, false,
2865 {
2866 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16,
2867 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2868 isa_bit_fp_dbl, isa_nobit
2869 }
2870 },
2871 { NULL, false, false, {isa_nobit}}
2872 };
2873
2874 static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = {
2875 {
2876 "simd", false, false,
2877 {
2878 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2879 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2880 isa_bit_fp_dbl, isa_nobit
2881 }
2882 },
2883 {
2884 "fp16", false, false,
2885 {
2886 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2887 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2888 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2889 }
2890 },
2891 {
2892 "crypto", false, false,
2893 {
2894 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2895 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2896 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2897 }
2898 },
2899 {
2900 "nocrypto", true, false,
2901 {
2902 isa_bit_crypto, isa_nobit
2903 }
2904 },
2905 {
2906 "nofp", true, false,
2907 {
2908 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2909 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2910 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2911 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2912 }
2913 },
2914 {
2915 "sb", false, false,
2916 {
2917 isa_bit_sb, isa_nobit
2918 }
2919 },
2920 {
2921 "predres", false, false,
2922 {
2923 isa_bit_predres, isa_nobit
2924 }
2925 },
2926 {
2927 "i8mm", false, false,
2928 {
2929 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2930 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2931 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2932 }
2933 },
2934 {
2935 "bf16", false, false,
2936 {
2937 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16,
2938 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2939 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2940 }
2941 },
2942 { NULL, false, false, {isa_nobit}}
2943 };
2944
2945 static const struct cpu_arch_extension arch_opttab_armv8_5_a[] = {
2946 {
2947 "simd", false, false,
2948 {
2949 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2950 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2951 isa_bit_fp_dbl, isa_nobit
2952 }
2953 },
2954 {
2955 "fp16", false, false,
2956 {
2957 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2958 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2959 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2960 }
2961 },
2962 {
2963 "crypto", false, false,
2964 {
2965 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2966 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2967 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2968 }
2969 },
2970 {
2971 "nocrypto", true, false,
2972 {
2973 isa_bit_crypto, isa_nobit
2974 }
2975 },
2976 {
2977 "nofp", true, false,
2978 {
2979 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2980 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
2981 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2982 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2983 }
2984 },
2985 {
2986 "i8mm", false, false,
2987 {
2988 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
2989 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2990 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2991 }
2992 },
2993 {
2994 "bf16", false, false,
2995 {
2996 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16,
2997 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2998 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2999 }
3000 },
3001 { NULL, false, false, {isa_nobit}}
3002 };
3003
3004 static const struct cpu_arch_extension arch_opttab_armv8_6_a[] = {
3005 {
3006 "simd", false, false,
3007 {
3008 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
3009 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
3010 isa_bit_fp_dbl, isa_nobit
3011 }
3012 },
3013 {
3014 "fp16", false, false,
3015 {
3016 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
3017 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
3018 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3019 }
3020 },
3021 {
3022 "crypto", false, false,
3023 {
3024 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
3025 isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
3026 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
3027 }
3028 },
3029 {
3030 "nocrypto", true, false,
3031 {
3032 isa_bit_crypto, isa_nobit
3033 }
3034 },
3035 {
3036 "nofp", true, false,
3037 {
3038 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
3039 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
3040 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
3041 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
3042 }
3043 },
3044 {
3045 "i8mm", false, false,
3046 {
3047 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
3048 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
3049 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3050 }
3051 },
3052 {
3053 "bf16", false, false,
3054 {
3055 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_bf16,
3056 isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
3057 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3058 }
3059 },
3060 { NULL, false, false, {isa_nobit}}
3061 };
3062
3063 static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
3064 {
3065 "dsp", false, false,
3066 {
3067 isa_bit_armv7em, isa_nobit
3068 }
3069 },
3070 {
3071 "fp", false, false,
3072 {
3073 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3074 isa_bit_fp16conv, isa_nobit
3075 }
3076 },
3077 {
3078 "fp.dp", false, false,
3079 {
3080 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3081 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3082 }
3083 },
3084 {
3085 "nofp", true, false,
3086 {
3087 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
3088 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
3089 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
3090 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
3091 }
3092 },
3093 {
3094 "nodsp", true, false,
3095 {
3096 isa_bit_armv7em, isa_nobit
3097 }
3098 },
3099 {
3100 "cdecp0", false, false,
3101 {
3102 isa_bit_cdecp0, isa_nobit
3103 }
3104 },
3105 {
3106 "cdecp1", false, false,
3107 {
3108 isa_bit_cdecp1, isa_nobit
3109 }
3110 },
3111 {
3112 "cdecp2", false, false,
3113 {
3114 isa_bit_cdecp2, isa_nobit
3115 }
3116 },
3117 {
3118 "cdecp3", false, false,
3119 {
3120 isa_bit_cdecp3, isa_nobit
3121 }
3122 },
3123 {
3124 "cdecp4", false, false,
3125 {
3126 isa_bit_cdecp4, isa_nobit
3127 }
3128 },
3129 {
3130 "cdecp5", false, false,
3131 {
3132 isa_bit_cdecp5, isa_nobit
3133 }
3134 },
3135 {
3136 "cdecp6", false, false,
3137 {
3138 isa_bit_cdecp6, isa_nobit
3139 }
3140 },
3141 {
3142 "cdecp7", false, false,
3143 {
3144 isa_bit_cdecp7, isa_nobit
3145 }
3146 },
3147 { NULL, false, false, {isa_nobit}}
3148 };
3149
3150 static const struct cpu_arch_extension arch_opttab_armv8_r[] = {
3151 {
3152 "crc", false, false,
3153 {
3154 isa_bit_crc32, isa_nobit
3155 }
3156 },
3157 {
3158 "fp.sp", false, false,
3159 {
3160 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3161 isa_bit_fp16conv, isa_nobit
3162 }
3163 },
3164 {
3165 "simd", false, false,
3166 {
3167 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3168 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
3169 isa_nobit
3170 }
3171 },
3172 {
3173 "crypto", false, false,
3174 {
3175 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3176 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
3177 isa_bit_fp_dbl, isa_nobit
3178 }
3179 },
3180 {
3181 "nocrypto", true, false,
3182 {
3183 isa_bit_crypto, isa_nobit
3184 }
3185 },
3186 {
3187 "nofp", true, false,
3188 {
3189 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
3190 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
3191 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
3192 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
3193 }
3194 },
3195 { NULL, false, false, {isa_nobit}}
3196 };
3197
3198 static const struct cpu_arch_extension arch_opttab_armv8_1_m_main[] = {
3199 {
3200 "dsp", false, false,
3201 {
3202 isa_bit_armv7em, isa_nobit
3203 }
3204 },
3205 {
3206 "fp", false, false,
3207 {
3208 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3209 isa_bit_fp16, isa_bit_fp16conv, isa_nobit
3210 }
3211 },
3212 {
3213 "fp.dp", false, false,
3214 {
3215 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3216 isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3217 }
3218 },
3219 {
3220 "nofp", true, false,
3221 {
3222 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_i8mm,
3223 isa_bit_fp16fml, isa_bit_bf16, isa_bit_dotprod, isa_bit_neon,
3224 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
3225 isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
3226 }
3227 },
3228 {
3229 "mve", false, false,
3230 {
3231 isa_bit_mve, isa_bit_armv7em, isa_nobit
3232 }
3233 },
3234 {
3235 "mve.fp", false, false,
3236 {
3237 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_mve,
3238 isa_bit_armv7em, isa_bit_fpv5, isa_bit_fp16, isa_bit_fp16conv,
3239 isa_bit_mve_float, isa_nobit
3240 }
3241 },
3242 {
3243 "cdecp0", false, false,
3244 {
3245 isa_bit_cdecp0, isa_nobit
3246 }
3247 },
3248 {
3249 "cdecp1", false, false,
3250 {
3251 isa_bit_cdecp1, isa_nobit
3252 }
3253 },
3254 {
3255 "cdecp2", false, false,
3256 {
3257 isa_bit_cdecp2, isa_nobit
3258 }
3259 },
3260 {
3261 "cdecp3", false, false,
3262 {
3263 isa_bit_cdecp3, isa_nobit
3264 }
3265 },
3266 {
3267 "cdecp4", false, false,
3268 {
3269 isa_bit_cdecp4, isa_nobit
3270 }
3271 },
3272 {
3273 "cdecp5", false, false,
3274 {
3275 isa_bit_cdecp5, isa_nobit
3276 }
3277 },
3278 {
3279 "cdecp6", false, false,
3280 {
3281 isa_bit_cdecp6, isa_nobit
3282 }
3283 },
3284 {
3285 "cdecp7", false, false,
3286 {
3287 isa_bit_cdecp7, isa_nobit
3288 }
3289 },
3290 { NULL, false, false, {isa_nobit}}
3291 };
3292
3293 const arch_option all_architectures[] =
3294 {
3295 {
3296 "armv4",
3297 NULL,
3298 {
3299 isa_bit_armv4, isa_bit_notm, isa_nobit
3300 },
3301 "4", BASE_ARCH_4,
3302 0,
3303 TARGET_CPU_arm7tdmi,
3304 },
3305 {
3306 "armv4t",
3307 NULL,
3308 {
3309 isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit
3310 },
3311 "4T", BASE_ARCH_4T,
3312 0,
3313 TARGET_CPU_arm7tdmi,
3314 },
3315 {
3316 "armv5t",
3317 NULL,
3318 {
3319 isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm,
3320 isa_nobit
3321 },
3322 "5T", BASE_ARCH_5T,
3323 0,
3324 TARGET_CPU_arm10tdmi,
3325 },
3326 {
3327 "armv5te",
3328 arch_opttab_armv5te,
3329 {
3330 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
3331 isa_bit_notm, isa_nobit
3332 },
3333 "5TE", BASE_ARCH_5TE,
3334 0,
3335 TARGET_CPU_arm1026ejs,
3336 },
3337 {
3338 "armv5tej",
3339 arch_opttab_armv5tej,
3340 {
3341 isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4,
3342 isa_bit_notm, isa_nobit
3343 },
3344 "5TEJ", BASE_ARCH_5TEJ,
3345 0,
3346 TARGET_CPU_arm1026ejs,
3347 },
3348 {
3349 "armv6",
3350 arch_opttab_armv6,
3351 {
3352 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3353 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit
3354 },
3355 "6", BASE_ARCH_6,
3356 0,
3357 TARGET_CPU_arm1136js,
3358 },
3359 {
3360 "armv6j",
3361 arch_opttab_armv6j,
3362 {
3363 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3364 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit
3365 },
3366 "6J", BASE_ARCH_6J,
3367 0,
3368 TARGET_CPU_arm1136js,
3369 },
3370 {
3371 "armv6k",
3372 arch_opttab_armv6k,
3373 {
3374 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3375 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k,
3376 isa_nobit
3377 },
3378 "6K", BASE_ARCH_6K,
3379 0,
3380 TARGET_CPU_mpcore,
3381 },
3382 {
3383 "armv6z",
3384 arch_opttab_armv6z,
3385 {
3386 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3387 isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit
3388 },
3389 "6Z", BASE_ARCH_6Z,
3390 0,
3391 TARGET_CPU_arm1176jzs,
3392 },
3393 {
3394 "armv6kz",
3395 arch_opttab_armv6kz,
3396 {
3397 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3398 isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm,
3399 isa_bit_armv6k, isa_nobit
3400 },
3401 "6KZ", BASE_ARCH_6KZ,
3402 0,
3403 TARGET_CPU_arm1176jzs,
3404 },
3405 {
3406 "armv6zk",
3407 arch_opttab_armv6zk,
3408 {
3409 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3410 isa_bit_armv4, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_notm,
3411 isa_bit_armv6k, isa_nobit
3412 },
3413 "6KZ", BASE_ARCH_6KZ,
3414 0,
3415 TARGET_CPU_arm1176jzs,
3416 },
3417 {
3418 "armv6t2",
3419 arch_opttab_armv6t2,
3420 {
3421 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3422 isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm,
3423 isa_nobit
3424 },
3425 "6T2", BASE_ARCH_6T2,
3426 0,
3427 TARGET_CPU_arm1156t2s,
3428 },
3429 {
3430 "armv6-m",
3431 NULL,
3432 {
3433 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3434 isa_bit_armv4, isa_bit_armv6, isa_nobit
3435 },
3436 "6M", BASE_ARCH_6M,
3437 'M',
3438 TARGET_CPU_cortexm1,
3439 },
3440 {
3441 "armv6s-m",
3442 NULL,
3443 {
3444 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3445 isa_bit_armv4, isa_bit_armv6, isa_nobit
3446 },
3447 "6M", BASE_ARCH_6M,
3448 'M',
3449 TARGET_CPU_cortexm1,
3450 },
3451 {
3452 "armv7",
3453 arch_opttab_armv7,
3454 {
3455 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3456 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2,
3457 isa_nobit
3458 },
3459 "7", BASE_ARCH_7,
3460 0,
3461 TARGET_CPU_cortexa53,
3462 },
3463 {
3464 "armv7-a",
3465 arch_opttab_armv7_a,
3466 {
3467 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3468 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2,
3469 isa_bit_notm, isa_bit_armv6k, isa_nobit
3470 },
3471 "7A", BASE_ARCH_7A,
3472 'A',
3473 TARGET_CPU_cortexa53,
3474 },
3475 {
3476 "armv7ve",
3477 arch_opttab_armv7ve,
3478 {
3479 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3480 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3481 isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm,
3482 isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit
3483 },
3484 "7A", BASE_ARCH_7A,
3485 'A',
3486 TARGET_CPU_cortexa53,
3487 },
3488 {
3489 "armv7-r",
3490 arch_opttab_armv7_r,
3491 {
3492 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3493 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3494 isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit
3495 },
3496 "7R", BASE_ARCH_7R,
3497 'R',
3498 TARGET_CPU_cortexr4,
3499 },
3500 {
3501 "armv7-m",
3502 NULL,
3503 {
3504 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3505 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3506 isa_bit_thumb2, isa_nobit
3507 },
3508 "7M", BASE_ARCH_7M,
3509 'M',
3510 TARGET_CPU_cortexm3,
3511 },
3512 {
3513 "armv7e-m",
3514 arch_opttab_armv7e_m,
3515 {
3516 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3517 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7,
3518 isa_bit_tdiv, isa_bit_thumb2, isa_nobit
3519 },
3520 "7EM", BASE_ARCH_7EM,
3521 'M',
3522 TARGET_CPU_cortexm4,
3523 },
3524 {
3525 "armv8-a",
3526 arch_opttab_armv8_a,
3527 {
3528 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3529 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3530 isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2,
3531 isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3532 isa_nobit
3533 },
3534 "8A", BASE_ARCH_8A,
3535 'A',
3536 TARGET_CPU_cortexa53,
3537 },
3538 {
3539 "armv8.1-a",
3540 arch_opttab_armv8_1_a,
3541 {
3542 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3543 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3544 isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv,
3545 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k,
3546 isa_bit_mp, isa_bit_sec, isa_nobit
3547 },
3548 "8A", BASE_ARCH_8A,
3549 'A',
3550 TARGET_CPU_cortexa53,
3551 },
3552 {
3553 "armv8.2-a",
3554 arch_opttab_armv8_2_a,
3555 {
3556 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3557 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3558 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3559 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2,
3560 isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit
3561 },
3562 "8A", BASE_ARCH_8A,
3563 'A',
3564 TARGET_CPU_cortexa53,
3565 },
3566 {
3567 "armv8.3-a",
3568 arch_opttab_armv8_3_a,
3569 {
3570 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3571 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3572 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3573 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2,
3574 isa_bit_armv6k, isa_bit_armv8_3, isa_bit_mp, isa_bit_sec,
3575 isa_nobit
3576 },
3577 "8A", BASE_ARCH_8A,
3578 'A',
3579 TARGET_CPU_cortexa53,
3580 },
3581 {
3582 "armv8.4-a",
3583 arch_opttab_armv8_4_a,
3584 {
3585 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3586 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3587 isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3588 isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2,
3589 isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp,
3590 isa_bit_sec, isa_nobit
3591 },
3592 "8A", BASE_ARCH_8A,
3593 'A',
3594 TARGET_CPU_cortexa53,
3595 },
3596 {
3597 "armv8.5-a",
3598 arch_opttab_armv8_5_a,
3599 {
3600 isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb,
3601 isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4,
3602 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
3603 isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3604 isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4,
3605 isa_bit_mp, isa_bit_armv8_5, isa_bit_sec, isa_bit_predres,
3606 isa_nobit
3607 },
3608 "8A", BASE_ARCH_8A,
3609 'A',
3610 TARGET_CPU_cortexa53,
3611 },
3612 {
3613 "armv8.6-a",
3614 arch_opttab_armv8_6_a,
3615 {
3616 isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb,
3617 isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4,
3618 isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
3619 isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3620 isa_bit_armv6k, isa_bit_armv8_2, isa_bit_armv8_3, isa_bit_mp,
3621 isa_bit_armv8_4, isa_bit_armv8_5, isa_bit_armv8_6, isa_bit_sec,
3622 isa_bit_predres, isa_nobit
3623 },
3624 "8A", BASE_ARCH_8A,
3625 'A',
3626 TARGET_CPU_cortexa53,
3627 },
3628 {
3629 "armv8-m.base",
3630 NULL,
3631 {
3632 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3633 isa_bit_armv4, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
3634 isa_bit_tdiv, isa_nobit
3635 },
3636 "8M_BASE", BASE_ARCH_8M_BASE,
3637 'M',
3638 TARGET_CPU_cortexm23,
3639 },
3640 {
3641 "armv8-m.main",
3642 arch_opttab_armv8_m_main,
3643 {
3644 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3645 isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_armv8,
3646 isa_bit_cmse, isa_bit_tdiv, isa_bit_thumb2, isa_nobit
3647 },
3648 "8M_MAIN", BASE_ARCH_8M_MAIN,
3649 'M',
3650 TARGET_CPU_cortexm7,
3651 },
3652 {
3653 "armv8-r",
3654 arch_opttab_armv8_r,
3655 {
3656 isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8,
3657 isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6,
3658 isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2,
3659 isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3660 isa_nobit
3661 },
3662 "8R", BASE_ARCH_8R,
3663 'R',
3664 TARGET_CPU_cortexr52,
3665 },
3666 {
3667 "armv8.1-m.main",
3668 arch_opttab_armv8_1_m_main,
3669 {
3670 isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t,
3671 isa_bit_armv4, isa_bit_armv8_1m_main, isa_bit_armv6, isa_bit_armv7,
3672 isa_bit_armv8, isa_bit_cmse, isa_bit_tdiv, isa_bit_thumb2,
3673 isa_nobit
3674 },
3675 "8M_MAIN", BASE_ARCH_8M_MAIN,
3676 'M',
3677 TARGET_CPU_cortexm7,
3678 },
3679 {
3680 "iwmmxt",
3681 NULL,
3682 {
3683 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb,
3684 isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit
3685 },
3686 "5TE", BASE_ARCH_5TE,
3687 0,
3688 TARGET_CPU_iwmmxt,
3689 },
3690 {
3691 "iwmmxt2",
3692 NULL,
3693 {
3694 isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb,
3695 isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm,
3696 isa_nobit
3697 },
3698 "5TE", BASE_ARCH_5TE,
3699 0,
3700 TARGET_CPU_iwmmxt2,
3701 },
3702 {{NULL, NULL, {isa_nobit}},
3703 NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none}
3704 };
3705
3706 const arm_fpu_desc all_fpus[] =
3707 {
3708 {
3709 "vfp",
3710 {
3711 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3712 }
3713 },
3714 {
3715 "vfpv2",
3716 {
3717 isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3718 }
3719 },
3720 {
3721 "vfpv3",
3722 {
3723 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3724 isa_nobit
3725 }
3726 },
3727 {
3728 "vfpv3-fp16",
3729 {
3730 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
3731 isa_bit_fp_dbl, isa_nobit
3732 }
3733 },
3734 {
3735 "vfpv3-d16",
3736 {
3737 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
3738 }
3739 },
3740 {
3741 "vfpv3-d16-fp16",
3742 {
3743 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
3744 isa_nobit
3745 }
3746 },
3747 {
3748 "vfpv3xd",
3749 {
3750 isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
3751 }
3752 },
3753 {
3754 "vfpv3xd-fp16",
3755 {
3756 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
3757 }
3758 },
3759 {
3760 "neon",
3761 {
3762 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3763 isa_bit_fp_dbl, isa_nobit
3764 }
3765 },
3766 {
3767 "neon-vfpv3",
3768 {
3769 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3770 isa_bit_fp_dbl, isa_nobit
3771 }
3772 },
3773 {
3774 "neon-fp16",
3775 {
3776 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3777 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3778 }
3779 },
3780 {
3781 "vfpv4",
3782 {
3783 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
3784 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3785 }
3786 },
3787 {
3788 "neon-vfpv4",
3789 {
3790 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3791 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3792 }
3793 },
3794 {
3795 "vfpv4-d16",
3796 {
3797 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3798 isa_bit_fp_dbl, isa_nobit
3799 }
3800 },
3801 {
3802 "fpv4-sp-d16",
3803 {
3804 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3805 isa_nobit
3806 }
3807 },
3808 {
3809 "fpv5-sp-d16",
3810 {
3811 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3812 isa_bit_fp16conv, isa_nobit
3813 }
3814 },
3815 {
3816 "fpv5-d16",
3817 {
3818 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3819 isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3820 }
3821 },
3822 {
3823 "fp-armv8",
3824 {
3825 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3826 isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3827 }
3828 },
3829 {
3830 "neon-fp-armv8",
3831 {
3832 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3833 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
3834 isa_nobit
3835 }
3836 },
3837 {
3838 "crypto-neon-fp-armv8",
3839 {
3840 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3841 isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
3842 isa_bit_fp_dbl, isa_nobit
3843 }
3844 },
3845 {
3846 "vfp3",
3847 {
3848 isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3849 isa_nobit
3850 }
3851 },
3852 };
3853