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t-elf revision 1.1 
      1  1.1  mrg # For most CPUs we have an assembly soft-float implementations.
      2  1.1  mrg # However this is not true for ARMv6M.  Here we want to use the soft-fp C
      3  1.1  mrg # implementation.  The soft-fp code is only build for ARMv6M.  This pulls
      4  1.1  mrg # in the asm implementation for other CPUs.
      5  1.1  mrg LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \
      6  1.1  mrg 	_call_via_rX _interwork_call_via_rX \
      7  1.1  mrg 	_lshrdi3 _ashrdi3 _ashldi3 \
      8  1.1  mrg 	_arm_negdf2 _arm_addsubdf3 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
      9  1.1  mrg 	_arm_fixdfsi _arm_fixunsdfsi \
     10  1.1  mrg 	_arm_truncdfsf2 _arm_negsf2 _arm_addsubsf3 _arm_muldivsf3 \
     11  1.1  mrg 	_arm_cmpsf2 _arm_unordsf2 _arm_fixsfsi _arm_fixunssfsi \
     12  1.1  mrg 	_arm_floatdidf _arm_floatdisf _arm_floatundidf _arm_floatundisf \
     13  1.1  mrg 	_clzsi2 _clzdi2 _ctzsi2
     14  1.1  mrg 
     15  1.1  mrg # Currently there is a bug somewhere in GCC's alias analysis
     16  1.1  mrg # or scheduling code that is breaking _fpmul_parts in fp-bit.c.
     17  1.1  mrg # Disabling function inlining is a workaround for this problem.
     18  1.1  mrg HOST_LIBGCC2_CFLAGS += -fno-inline
     19