1 1.1 mrg /* Unsigned 32 bit division optimized for Epiphany. 2 1.1.1.11 mrg Copyright (C) 2009-2024 Free Software Foundation, Inc. 3 1.1 mrg Contributed by Embecosm on behalf of Adapteva, Inc. 4 1.1 mrg 5 1.1 mrg This file is part of GCC. 6 1.1 mrg 7 1.1 mrg This file is free software; you can redistribute it and/or modify it 8 1.1 mrg under the terms of the GNU General Public License as published by the 9 1.1 mrg Free Software Foundation; either version 3, or (at your option) any 10 1.1 mrg later version. 11 1.1 mrg 12 1.1 mrg This file is distributed in the hope that it will be useful, but 13 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of 14 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 1.1 mrg General Public License for more details. 16 1.1 mrg 17 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 18 1.1 mrg permissions described in the GCC Runtime Library Exception, version 19 1.1 mrg 3.1, as published by the Free Software Foundation. 20 1.1 mrg 21 1.1 mrg You should have received a copy of the GNU General Public License and 22 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 23 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 1.1 mrg <http://www.gnu.org/licenses/>. */ 25 1.1 mrg 26 1.1 mrg #include "epiphany-asm.h" 27 1.1 mrg 28 1.1 mrg FSTAB (__udivsi3,T_UINT) 29 1.1 mrg .global SYM(__udivsi3) 30 1.1 mrg .balign 4 31 1.1 mrg HIDDEN_FUNC(__udivsi3) 32 1.1 mrg SYM(__udivsi3): 33 1.1 mrg sub r3,r0,r1 34 1.1 mrg bltu .Lret0 35 1.1 mrg mov r3,0x95 36 1.1 mrg lsl r12,r3,23 ; 0x4a800000 37 1.1 mrg lsl r3,r3,30 ; 0x40000000 38 1.1 mrg orr r16,r0,r3 39 1.1 mrg orr r2,r1,r3 40 1.1 mrg fsub r16,r16,r3 41 1.1 mrg fsub r2,r2,r3 42 1.1 mrg lsr r3,r1,21 43 1.1 mrg lsr r17,r0,21 44 1.1 mrg movt r17,0x4a80 45 1.1 mrg fsub r17,r17,r12 46 1.1 mrg movt r3,0x4a80 47 1.1 mrg fsub r3,r3,r12 48 1.1 mrg mov r12,%low(.L0step) 49 1.1 mrg movt r12,%high(.L0step) 50 1.1 mrg mov r21,1 51 1.1 mrg movne r16,r17 52 1.1 mrg lsr r17,r1,21 53 1.1 mrg movne r2,r3 54 1.1 mrg lsr r3,r16,23 ; must mask lower bits of r2 in case op0 was .. 55 1.1 mrg lsr r2,r2,23 ; .. shifted and op1 was not. 56 1.1 mrg sub r3,r3,r2 ; calculate bit number difference. 57 1.1 mrg lsl r1,r1,r3 58 1.1 mrg lsr r16,r1,1 59 1.1 mrg lsl r2,r21,r3 60 1.1 mrg lsl r3,r3,3 61 1.1 mrg sub r12,r12,r3 62 1.1 mrg sub r3,r0,r1 63 1.1 mrg movltu r3,r0 64 1.1 mrg mov r0,0 65 1.1 mrg movgteu r0,r2 66 1.1 mrg lsr r2,r2,1 67 1.1 mrg add r17,r2,r0 68 1.1 mrg sub r1,r3,r16 69 1.1 mrg movgteu r3,r1 70 1.1 mrg movgteu r0,r17 71 1.1 mrg sub r16,r16,1 72 1.1 mrg jr r12 73 1.1 mrg .rep 30 74 1.1 mrg lsl r3,r3,1 75 1.1 mrg sub r1,r3,r16 76 1.1 mrg movgteu r3,r1 77 1.1 mrg .endr 78 1.1 mrg sub r2,r2,1 ; mask result bits from steps ... 79 1.1 mrg and r3,r3,r2 80 1.1 mrg orr r0,r0,r3 ; ... and combine with first bits. 81 1.1 mrg nop 82 1.1 mrg .L0step:rts 83 1.1 mrg .Lret0: mov r0,0 84 1.1 mrg rts 85 1.1 mrg ENDFUNC(__udivsi3) 86
Indexes created Sat Feb 28 05:31:39 UTC 2026