1 1.1 mrg /* Copyright (C) 2012-2024 Free Software Foundation, Inc. 2 1.1 mrg Contributed by Altera and Mentor Graphics, Inc. 3 1.1 mrg 4 1.1 mrg This file is free software; you can redistribute it and/or modify it 5 1.1 mrg under the terms of the GNU General Public License as published by the 6 1.1 mrg Free Software Foundation; either version 3, or (at your option) any 7 1.1 mrg later version. 8 1.1 mrg 9 1.1 mrg This file is distributed in the hope that it will be useful, but 10 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of 11 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 1.1 mrg General Public License for more details. 13 1.1 mrg 14 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 15 1.1 mrg permissions described in the GCC Runtime Library Exception, version 16 1.1 mrg 3.1, as published by the Free Software Foundation. 17 1.1 mrg 18 1.1 mrg You should have received a copy of the GNU General Public License and 19 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 20 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 21 1.1 mrg <http://www.gnu.org/licenses/>. */ 22 1.1 mrg 23 1.1 mrg #include "lib2-gcn.h" 24 1.1 mrg 25 1.1 mrg /* 16-bit V64HI divide and modulo as used in gcn. 26 1.1 mrg This is a simple conversion from lib2-divmod.c. */ 27 1.1 mrg 28 1.1 mrg #define MASKMODE v64hi 29 1.1 mrg #include "amdgcn_veclib.h" 30 1.1 mrg 31 1.1 mrg static v64udi 32 1.1 mrg __udivmodv64hi4_aux (v64uhi num, v64uhi den, v64hi __mask) 33 1.1 mrg { 34 1.1 mrg v64uhi bit = VECTOR_INIT ((unsigned short)1U); 35 1.1 mrg v64uhi res = VECTOR_INIT ((unsigned short)0U); 36 1.1 mrg 37 1.1 mrg VECTOR_WHILE ((den < num) & (bit != 0) & ((den & (1L<<15)) == 0), 38 1.1 mrg cond, NO_COND) 39 1.1 mrg VECTOR_COND_MOVE (den, den << 1, cond); 40 1.1 mrg VECTOR_COND_MOVE (bit, bit << 1, cond); 41 1.1 mrg VECTOR_ENDWHILE 42 1.1 mrg VECTOR_WHILE (bit != 0, loopcond, NO_COND) 43 1.1 mrg VECTOR_IF2 (num >= den, ifcond, loopcond) 44 1.1 mrg VECTOR_COND_MOVE (num, num - den, ifcond); 45 1.1 mrg VECTOR_COND_MOVE (res, res | bit, ifcond); 46 1.1 mrg VECTOR_ENDIF 47 1.1 mrg VECTOR_COND_MOVE (bit, bit >> 1, loopcond); 48 1.1 mrg VECTOR_COND_MOVE (den, den >> 1, loopcond); 49 1.1 mrg VECTOR_ENDWHILE 50 1.1 mrg 51 1.1 mrg return PACK_SI_PAIR (res, num); 52 1.1 mrg } 53 1.1 mrg 54 1.1 mrg static v64udi 55 1.1 mrg __divmodv64hi4_aux (v64hi a, v64hi b, v64hi __mask) 56 1.1 mrg { 57 1.1 mrg v64hi nega = VECTOR_INIT ((short)0); 58 1.1 mrg v64hi negb = VECTOR_INIT ((short)0); 59 1.1 mrg 60 1.1 mrg VECTOR_IF (a < 0, cond) 61 1.1 mrg VECTOR_COND_MOVE (a, -a, cond); 62 1.1 mrg nega = cond; 63 1.1 mrg VECTOR_ENDIF 64 1.1 mrg 65 1.1 mrg VECTOR_IF (b < 0, cond) 66 1.1 mrg VECTOR_COND_MOVE (b, -b, cond); 67 1.1 mrg negb = cond; 68 1.1 mrg VECTOR_ENDIF 69 1.1 mrg 70 1.1 mrg v64uhi ua = __builtin_convertvector (a, v64uhi); 71 1.1 mrg v64uhi ub = __builtin_convertvector (b, v64uhi); 72 1.1 mrg v64udi pair = __udivmodv64hi4_aux (ua, ub, __mask); 73 1.1 mrg 74 1.1 mrg v64hi quot = UNPACK_SI_LOW (v64hi, pair); 75 1.1 mrg v64hi rem = UNPACK_SI_HIGH (v64hi, pair); 76 1.1 mrg VECTOR_COND_MOVE (quot, -quot, nega ^ negb); 77 1.1 mrg VECTOR_COND_MOVE (rem, -rem, nega); 78 1.1 mrg pair = PACK_SI_PAIR (quot, rem); 79 1.1 mrg 80 1.1 mrg return pair; 81 1.1 mrg } 82 1.1 mrg 83 1.1 mrg 84 1.1 mrg static inline v64hi 85 1.1 mrg __divv64hi3_aux (v64hi a, v64hi b, v64hi __mask) 86 1.1 mrg { 87 1.1 mrg v64udi pair = __divmodv64hi4_aux (a, b, __mask); 88 1.1 mrg return UNPACK_SI_LOW (v64hi, pair); 89 1.1 mrg } 90 1.1 mrg 91 1.1 mrg static inline v64hi 92 1.1 mrg __modv64hi3_aux (v64hi a, v64hi b, v64hi __mask) 93 1.1 mrg { 94 1.1 mrg v64udi pair = __divmodv64hi4_aux (a, b, __mask); 95 1.1 mrg return UNPACK_SI_HIGH (v64hi, pair); 96 1.1 mrg } 97 1.1 mrg 98 1.1 mrg 99 1.1 mrg static inline v64uhi 100 1.1 mrg __udivv64hi3_aux (v64uhi a, v64uhi b, v64hi __mask) 101 1.1 mrg { 102 1.1 mrg v64udi pair = __udivmodv64hi4_aux (a, b, __mask); 103 1.1 mrg return UNPACK_SI_LOW (v64uhi, pair); 104 1.1 mrg } 105 1.1 mrg 106 1.1 mrg static inline v64uhi 107 1.1 mrg __umodv64hi3_aux (v64uhi a, v64uhi b, v64hi __mask) 108 1.1 mrg { 109 1.1 mrg v64udi pair = __udivmodv64hi4_aux (a, b, __mask); 110 1.1 mrg return UNPACK_SI_HIGH (v64uhi, pair); 111 1.1 mrg } 112 1.1 mrg 113 1.1 mrg DEF_VARIANTS (__div, hi3, hi) 114 1.1 mrg DEF_VARIANTS (__mod, hi3, hi) 115 1.1 mrg DEF_VARIANTS_B (__divmod, hi4, udi, hi) 116 1.1 mrg DEF_VARIANTS (__udiv, hi3, uhi) 117 1.1 mrg DEF_VARIANTS (__umod, hi3, uhi) 118 1.1 mrg DEF_VARIANTS_B (__udivmod, hi4, udi, uhi) 119
Indexes created Sat Feb 28 05:31:39 UTC 2026