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powerpc-plxv-nonrel.exp revision 1.1 
      1 # Copyright 2021-2023 Free Software Foundation, Inc.
      2 
      3 # This program is free software; you can redistribute it and/or modify
      4 # it under the terms of the GNU General Public License as published by
      5 # the Free Software Foundation; either version 3 of the License, or
      6 # (at your option) any later version.
      7 #
      8 # This program is distributed in the hope that it will be useful,
      9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
     10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     11 # GNU General Public License for more details.
     12 #
     13 # You should have received a copy of the GNU General Public License
     14 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
     15 
     16 # Test to see if gdb is properly single stepping over the
     17 # displaced plxv instruction.
     18 
     19 if { ![istarget powerpc*-*] || [skip_power_isa_3_1_tests] } {
     20     verbose "Skipping powerpc ISA 3.1 plxv test."
     21     return
     22 }
     23 
     24 set retval 0
     25 
     26 standard_testfile .s
     27 
     28 if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
     29       {debug quiet}] } {
     30     return -1
     31 }
     32 
     33 gdb_test "set radix 0b10000"
     34 gdb_test "set debug displaced"
     35 
     36 if {![runto_main]} {
     37       return
     38 }
     39 
     40 gdb_test "set debug displaced on"
     41 
     42 # Proc to extract the uint128 hex value from the output of
     43 # a print vector statement.
     44 proc get_vector_hexadecimal_valueof { exp default {test ""} } {
     45 	set val "0x0000"
     46 	global gdb_prompt
     47 	if {$test == ""} {
     48 		set test "get vector_hexadecimal valueof \"${exp}\""
     49 	}
     50 	gdb_test_multiple "print $${exp}.uint128" $test {
     51 		-re -wrap "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" {
     52 			set val $expect_out(1,string)
     53 				pass "$test"
     54 		}
     55 		-re -wrap ".*Illegal instruction.* $" {
     56 			fail "Illegal instruction on print."
     57 			set val 0xffff
     58 		}
     59 	}
     60 	return ${val}
     61 }
     62 
     63 # Proc to do a single-step, and ensure we gently handle
     64 # an illegal instruction situation.
     65 proc stepi_over_instruction { xyz } {
     66 	global gdb_prompt
     67 	gdb_test_multiple "stepi" "${xyz} " {
     68 		-re -wrap ".*Illegal instruction.*" {
     69 			fail "Illegal instruction on single step."
     70 		return
     71 		}
     72 		-re -wrap ".*" {
     73 		 pass "stepi ${xyz}"
     74 		}
     75 	}
     76 }
     77 
     78 set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
     79 
     80 # set some breakpoints on the instructions below main().
     81 gdb_test "disas /r main"
     82 set bp1 *$check_pc+4
     83 set bp2 *$check_pc+0d12
     84 set bp3 *$check_pc+0d20
     85 set bp4 *$check_pc+0d28
     86 gdb_breakpoint $bp1
     87 gdb_breakpoint $bp2
     88 gdb_breakpoint $bp3
     89 gdb_breakpoint $bp4
     90 
     91 # single-step through the plxv instructions, and retrieve the
     92 # register values as we proceed.
     93 
     94 stepi_over_instruction  "stepi over NOP"
     95 stepi_over_instruction  "stepi over lnia"
     96 stepi_over_instruction  "stepi over addi"
     97 
     98 stepi_over_instruction  "stepi over vs4 assignment"
     99 set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
    100 
    101 stepi_over_instruction  "stepi over vs5 assignment"
    102 set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
    103 
    104 stepi_over_instruction  "stepi over vs6 assignment"
    105 set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
    106 
    107 stepi_over_instruction  "stepi over vs7 assignment"
    108 set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
    109 
    110 set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
    111 set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
    112 set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
    113 set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
    114 
    115 if [expr  $check_vs4 != $vs4_expected] {
    116     fail "unexpected value vs4;  actual:$check_vs4 expected:$vs4_expected"
    117 }
    118 if [expr $check_vs5 != $vs5_expected ] {
    119     fail "unexpected value vs5;   actual:$check_vs5 expected:$vs5_expected"
    120 }
    121 if [expr $check_vs6 != $vs6_expected ] {
    122     fail "unexpected value vs6;   actual:$check_vs6 expected:$vs6_expected"
    123 }
    124 if [expr $check_vs7 != $vs7_expected ] {
    125     fail "unexpected value vs7;   actual:$check_vs7 expected:$vs7_expected"
    126 }
    127 
    128 gdb_test "info break"
    129 gdb_test "info register vs4 vs5 vs6 vs7 "
    130 gdb_test "disas main #2"
    131 
    132