epiphany-ibld.c revision 1.1.1.1
1 /* Instruction building/extraction support for epiphany. -*- C -*- 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 4 - the resultant file is machine generated, cgen-ibld.in isn't 5 6 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, 7 2008, 2010 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "epiphany-desc.h" 35 #include "epiphany-opc.h" 36 #include "cgen/basic-modes.h" 37 #include "opintl.h" 38 #include "safe-ctype.h" 39 40 #undef min 41 #define min(a,b) ((a) < (b) ? (a) : (b)) 42 #undef max 43 #define max(a,b) ((a) > (b) ? (a) : (b)) 44 45 /* Used by the ifield rtx function. */ 46 #define FLD(f) (fields->f) 47 48 static const char * insert_normal 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 51 static const char * insert_insn_normal 52 (CGEN_CPU_DESC, const CGEN_INSN *, 53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 54 static int extract_normal 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 56 unsigned int, unsigned int, unsigned int, unsigned int, 57 unsigned int, unsigned int, bfd_vma, long *); 58 static int extract_insn_normal 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 61 #if CGEN_INT_INSN_P 62 static void put_insn_int_value 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 64 #endif 65 #if ! CGEN_INT_INSN_P 66 static CGEN_INLINE void insert_1 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 68 static CGEN_INLINE int fill_cache 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 70 static CGEN_INLINE long extract_1 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 72 #endif 73 74 /* Operand insertion. */ 76 77 #if ! CGEN_INT_INSN_P 78 79 /* Subroutine of insert_normal. */ 80 81 static CGEN_INLINE void 82 insert_1 (CGEN_CPU_DESC cd, 83 unsigned long value, 84 int start, 85 int length, 86 int word_length, 87 unsigned char *bufp) 88 { 89 unsigned long x,mask; 90 int shift; 91 92 x = cgen_get_insn_value (cd, bufp, word_length); 93 94 /* Written this way to avoid undefined behaviour. */ 95 mask = (((1L << (length - 1)) - 1) << 1) | 1; 96 if (CGEN_INSN_LSB0_P) 97 shift = (start + 1) - length; 98 else 99 shift = (word_length - (start + length)); 100 x = (x & ~(mask << shift)) | ((value & mask) << shift); 101 102 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 103 } 104 105 #endif /* ! CGEN_INT_INSN_P */ 106 107 /* Default insertion routine. 108 109 ATTRS is a mask of the boolean attributes. 110 WORD_OFFSET is the offset in bits from the start of the insn of the value. 111 WORD_LENGTH is the length of the word in bits in which the value resides. 112 START is the starting bit number in the word, architecture origin. 113 LENGTH is the length of VALUE in bits. 114 TOTAL_LENGTH is the total length of the insn in bits. 115 116 The result is an error message or NULL if success. */ 117 118 /* ??? This duplicates functionality with bfd's howto table and 119 bfd_install_relocation. */ 120 /* ??? This doesn't handle bfd_vma's. Create another function when 121 necessary. */ 122 123 static const char * 124 insert_normal (CGEN_CPU_DESC cd, 125 long value, 126 unsigned int attrs, 127 unsigned int word_offset, 128 unsigned int start, 129 unsigned int length, 130 unsigned int word_length, 131 unsigned int total_length, 132 CGEN_INSN_BYTES_PTR buffer) 133 { 134 static char errbuf[100]; 135 /* Written this way to avoid undefined behaviour. */ 136 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 137 138 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 139 if (length == 0) 140 return NULL; 141 142 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 143 abort (); 144 145 /* For architectures with insns smaller than the base-insn-bitsize, 146 word_length may be too big. */ 147 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 148 { 149 if (word_offset == 0 150 && word_length > total_length) 151 word_length = total_length; 152 } 153 154 /* Ensure VALUE will fit. */ 155 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 156 { 157 long minval = - (1L << (length - 1)); 158 unsigned long maxval = mask; 159 160 if ((value > 0 && (unsigned long) value > maxval) 161 || value < minval) 162 { 163 /* xgettext:c-format */ 164 sprintf (errbuf, 165 _("operand out of range (%ld not between %ld and %lu)"), 166 value, minval, maxval); 167 return errbuf; 168 } 169 } 170 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 171 { 172 unsigned long maxval = mask; 173 unsigned long val = (unsigned long) value; 174 175 /* For hosts with a word size > 32 check to see if value has been sign 176 extended beyond 32 bits. If so then ignore these higher sign bits 177 as the user is attempting to store a 32-bit signed value into an 178 unsigned 32-bit field which is allowed. */ 179 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 180 val &= 0xFFFFFFFF; 181 182 if (val > maxval) 183 { 184 /* xgettext:c-format */ 185 sprintf (errbuf, 186 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 187 val, maxval); 188 return errbuf; 189 } 190 } 191 else 192 { 193 if (! cgen_signed_overflow_ok_p (cd)) 194 { 195 long minval = - (1L << (length - 1)); 196 long maxval = (1L << (length - 1)) - 1; 197 198 if (value < minval || value > maxval) 199 { 200 sprintf 201 /* xgettext:c-format */ 202 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 203 value, minval, maxval); 204 return errbuf; 205 } 206 } 207 } 208 209 #if CGEN_INT_INSN_P 210 211 { 212 int shift; 213 214 if (CGEN_INSN_LSB0_P) 215 shift = (word_offset + start + 1) - length; 216 else 217 shift = total_length - (word_offset + start + length); 218 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 219 } 220 221 #else /* ! CGEN_INT_INSN_P */ 222 223 { 224 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 225 226 insert_1 (cd, value, start, length, word_length, bufp); 227 } 228 229 #endif /* ! CGEN_INT_INSN_P */ 230 231 return NULL; 232 } 233 234 /* Default insn builder (insert handler). 235 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 236 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 237 recorded in host byte order, otherwise BUFFER is an array of bytes 238 and the value is recorded in target byte order). 239 The result is an error message or NULL if success. */ 240 241 static const char * 242 insert_insn_normal (CGEN_CPU_DESC cd, 243 const CGEN_INSN * insn, 244 CGEN_FIELDS * fields, 245 CGEN_INSN_BYTES_PTR buffer, 246 bfd_vma pc) 247 { 248 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 249 unsigned long value; 250 const CGEN_SYNTAX_CHAR_TYPE * syn; 251 252 CGEN_INIT_INSERT (cd); 253 value = CGEN_INSN_BASE_VALUE (insn); 254 255 /* If we're recording insns as numbers (rather than a string of bytes), 256 target byte order handling is deferred until later. */ 257 258 #if CGEN_INT_INSN_P 259 260 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 261 CGEN_FIELDS_BITSIZE (fields), value); 262 263 #else 264 265 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 266 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 267 value); 268 269 #endif /* ! CGEN_INT_INSN_P */ 270 271 /* ??? It would be better to scan the format's fields. 272 Still need to be able to insert a value based on the operand though; 273 e.g. storing a branch displacement that got resolved later. 274 Needs more thought first. */ 275 276 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 277 { 278 const char *errmsg; 279 280 if (CGEN_SYNTAX_CHAR_P (* syn)) 281 continue; 282 283 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 284 fields, buffer, pc); 285 if (errmsg) 286 return errmsg; 287 } 288 289 return NULL; 290 } 291 292 #if CGEN_INT_INSN_P 293 /* Cover function to store an insn value into an integral insn. Must go here 294 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 295 296 static void 297 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 298 CGEN_INSN_BYTES_PTR buf, 299 int length, 300 int insn_length, 301 CGEN_INSN_INT value) 302 { 303 /* For architectures with insns smaller than the base-insn-bitsize, 304 length may be too big. */ 305 if (length > insn_length) 306 *buf = value; 307 else 308 { 309 int shift = insn_length - length; 310 /* Written this way to avoid undefined behaviour. */ 311 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 312 313 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 314 } 315 } 316 #endif 317 318 /* Operand extraction. */ 320 321 #if ! CGEN_INT_INSN_P 322 323 /* Subroutine of extract_normal. 324 Ensure sufficient bytes are cached in EX_INFO. 325 OFFSET is the offset in bytes from the start of the insn of the value. 326 BYTES is the length of the needed value. 327 Returns 1 for success, 0 for failure. */ 328 329 static CGEN_INLINE int 330 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 331 CGEN_EXTRACT_INFO *ex_info, 332 int offset, 333 int bytes, 334 bfd_vma pc) 335 { 336 /* It's doubtful that the middle part has already been fetched so 337 we don't optimize that case. kiss. */ 338 unsigned int mask; 339 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 340 341 /* First do a quick check. */ 342 mask = (1 << bytes) - 1; 343 if (((ex_info->valid >> offset) & mask) == mask) 344 return 1; 345 346 /* Search for the first byte we need to read. */ 347 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 348 if (! (mask & ex_info->valid)) 349 break; 350 351 if (bytes) 352 { 353 int status; 354 355 pc += offset; 356 status = (*info->read_memory_func) 357 (pc, ex_info->insn_bytes + offset, bytes, info); 358 359 if (status != 0) 360 { 361 (*info->memory_error_func) (status, pc, info); 362 return 0; 363 } 364 365 ex_info->valid |= ((1 << bytes) - 1) << offset; 366 } 367 368 return 1; 369 } 370 371 /* Subroutine of extract_normal. */ 372 373 static CGEN_INLINE long 374 extract_1 (CGEN_CPU_DESC cd, 375 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 376 int start, 377 int length, 378 int word_length, 379 unsigned char *bufp, 380 bfd_vma pc ATTRIBUTE_UNUSED) 381 { 382 unsigned long x; 383 int shift; 384 385 x = cgen_get_insn_value (cd, bufp, word_length); 386 387 if (CGEN_INSN_LSB0_P) 388 shift = (start + 1) - length; 389 else 390 shift = (word_length - (start + length)); 391 return x >> shift; 392 } 393 394 #endif /* ! CGEN_INT_INSN_P */ 395 396 /* Default extraction routine. 397 398 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 399 or sometimes less for cases like the m32r where the base insn size is 32 400 but some insns are 16 bits. 401 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 402 but for generality we take a bitmask of all of them. 403 WORD_OFFSET is the offset in bits from the start of the insn of the value. 404 WORD_LENGTH is the length of the word in bits in which the value resides. 405 START is the starting bit number in the word, architecture origin. 406 LENGTH is the length of VALUE in bits. 407 TOTAL_LENGTH is the total length of the insn in bits. 408 409 Returns 1 for success, 0 for failure. */ 410 411 /* ??? The return code isn't properly used. wip. */ 412 413 /* ??? This doesn't handle bfd_vma's. Create another function when 414 necessary. */ 415 416 static int 417 extract_normal (CGEN_CPU_DESC cd, 418 #if ! CGEN_INT_INSN_P 419 CGEN_EXTRACT_INFO *ex_info, 420 #else 421 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 422 #endif 423 CGEN_INSN_INT insn_value, 424 unsigned int attrs, 425 unsigned int word_offset, 426 unsigned int start, 427 unsigned int length, 428 unsigned int word_length, 429 unsigned int total_length, 430 #if ! CGEN_INT_INSN_P 431 bfd_vma pc, 432 #else 433 bfd_vma pc ATTRIBUTE_UNUSED, 434 #endif 435 long *valuep) 436 { 437 long value, mask; 438 439 /* If LENGTH is zero, this operand doesn't contribute to the value 440 so give it a standard value of zero. */ 441 if (length == 0) 442 { 443 *valuep = 0; 444 return 1; 445 } 446 447 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 448 abort (); 449 450 /* For architectures with insns smaller than the insn-base-bitsize, 451 word_length may be too big. */ 452 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 453 { 454 if (word_offset + word_length > total_length) 455 word_length = total_length - word_offset; 456 } 457 458 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 459 460 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 461 { 462 if (CGEN_INSN_LSB0_P) 463 value = insn_value >> ((word_offset + start + 1) - length); 464 else 465 value = insn_value >> (total_length - ( word_offset + start + length)); 466 } 467 468 #if ! CGEN_INT_INSN_P 469 470 else 471 { 472 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 473 474 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 475 abort (); 476 477 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 478 return 0; 479 480 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 481 } 482 483 #endif /* ! CGEN_INT_INSN_P */ 484 485 /* Written this way to avoid undefined behaviour. */ 486 mask = (((1L << (length - 1)) - 1) << 1) | 1; 487 488 value &= mask; 489 /* sign extend? */ 490 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 491 && (value & (1L << (length - 1)))) 492 value |= ~mask; 493 494 *valuep = value; 495 496 return 1; 497 } 498 499 /* Default insn extractor. 500 501 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 502 The extracted fields are stored in FIELDS. 503 EX_INFO is used to handle reading variable length insns. 504 Return the length of the insn in bits, or 0 if no match, 505 or -1 if an error occurs fetching data (memory_error_func will have 506 been called). */ 507 508 static int 509 extract_insn_normal (CGEN_CPU_DESC cd, 510 const CGEN_INSN *insn, 511 CGEN_EXTRACT_INFO *ex_info, 512 CGEN_INSN_INT insn_value, 513 CGEN_FIELDS *fields, 514 bfd_vma pc) 515 { 516 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 517 const CGEN_SYNTAX_CHAR_TYPE *syn; 518 519 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 520 521 CGEN_INIT_EXTRACT (cd); 522 523 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 524 { 525 int length; 526 527 if (CGEN_SYNTAX_CHAR_P (*syn)) 528 continue; 529 530 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 531 ex_info, insn_value, fields, pc); 532 if (length <= 0) 533 return length; 534 } 535 536 /* We recognized and successfully extracted this insn. */ 537 return CGEN_INSN_BITSIZE (insn); 538 } 539 540 /* Machine generated code added here. */ 542 543 const char * epiphany_cgen_insert_operand 544 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 545 546 /* Main entry point for operand insertion. 547 548 This function is basically just a big switch statement. Earlier versions 549 used tables to look up the function to use, but 550 - if the table contains both assembler and disassembler functions then 551 the disassembler contains much of the assembler and vice-versa, 552 - there's a lot of inlining possibilities as things grow, 553 - using a switch statement avoids the function call overhead. 554 555 This function could be moved into `parse_insn_normal', but keeping it 556 separate makes clear the interface between `parse_insn_normal' and each of 557 the handlers. It's also needed by GAS to insert operands that couldn't be 558 resolved during parsing. */ 559 560 const char * 561 epiphany_cgen_insert_operand (CGEN_CPU_DESC cd, 562 int opindex, 563 CGEN_FIELDS * fields, 564 CGEN_INSN_BYTES_PTR buffer, 565 bfd_vma pc ATTRIBUTE_UNUSED) 566 { 567 const char * errmsg = NULL; 568 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 569 570 switch (opindex) 571 { 572 case EPIPHANY_OPERAND_DIRECTION : 573 errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer); 574 break; 575 case EPIPHANY_OPERAND_DISP11 : 576 { 577 { 578 FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255)); 579 FLD (f_disp3) = ((FLD (f_disp11)) & (7)); 580 } 581 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 582 if (errmsg) 583 break; 584 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 585 if (errmsg) 586 break; 587 } 588 break; 589 case EPIPHANY_OPERAND_DISP3 : 590 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 591 break; 592 case EPIPHANY_OPERAND_DPMI : 593 errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer); 594 break; 595 case EPIPHANY_OPERAND_FRD : 596 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 597 break; 598 case EPIPHANY_OPERAND_FRD6 : 599 { 600 { 601 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 602 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 603 } 604 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 605 if (errmsg) 606 break; 607 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 608 if (errmsg) 609 break; 610 } 611 break; 612 case EPIPHANY_OPERAND_FRM : 613 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 614 break; 615 case EPIPHANY_OPERAND_FRM6 : 616 { 617 { 618 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 619 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 620 } 621 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 622 if (errmsg) 623 break; 624 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 625 if (errmsg) 626 break; 627 } 628 break; 629 case EPIPHANY_OPERAND_FRN : 630 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 631 break; 632 case EPIPHANY_OPERAND_FRN6 : 633 { 634 { 635 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 636 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 637 } 638 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 639 if (errmsg) 640 break; 641 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 642 if (errmsg) 643 break; 644 } 645 break; 646 case EPIPHANY_OPERAND_IMM16 : 647 { 648 { 649 FLD (f_imm8) = ((FLD (f_imm16)) & (255)); 650 FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8)); 651 } 652 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 653 if (errmsg) 654 break; 655 errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer); 656 if (errmsg) 657 break; 658 } 659 break; 660 case EPIPHANY_OPERAND_IMM8 : 661 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 662 break; 663 case EPIPHANY_OPERAND_RD : 664 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 665 break; 666 case EPIPHANY_OPERAND_RD6 : 667 { 668 { 669 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 670 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 671 } 672 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 673 if (errmsg) 674 break; 675 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 676 if (errmsg) 677 break; 678 } 679 break; 680 case EPIPHANY_OPERAND_RM : 681 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 682 break; 683 case EPIPHANY_OPERAND_RM6 : 684 { 685 { 686 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 687 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 688 } 689 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 690 if (errmsg) 691 break; 692 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 693 if (errmsg) 694 break; 695 } 696 break; 697 case EPIPHANY_OPERAND_RN : 698 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 699 break; 700 case EPIPHANY_OPERAND_RN6 : 701 { 702 { 703 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 704 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 705 } 706 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 707 if (errmsg) 708 break; 709 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 710 if (errmsg) 711 break; 712 } 713 break; 714 case EPIPHANY_OPERAND_SD : 715 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 716 break; 717 case EPIPHANY_OPERAND_SD6 : 718 { 719 { 720 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 721 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 722 } 723 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 724 if (errmsg) 725 break; 726 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 727 if (errmsg) 728 break; 729 } 730 break; 731 case EPIPHANY_OPERAND_SDDMA : 732 { 733 { 734 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 735 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 736 } 737 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 738 if (errmsg) 739 break; 740 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 741 if (errmsg) 742 break; 743 } 744 break; 745 case EPIPHANY_OPERAND_SDMEM : 746 { 747 { 748 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 749 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 750 } 751 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 752 if (errmsg) 753 break; 754 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 755 if (errmsg) 756 break; 757 } 758 break; 759 case EPIPHANY_OPERAND_SDMESH : 760 { 761 { 762 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 763 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 764 } 765 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 766 if (errmsg) 767 break; 768 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 769 if (errmsg) 770 break; 771 } 772 break; 773 case EPIPHANY_OPERAND_SHIFT : 774 errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer); 775 break; 776 case EPIPHANY_OPERAND_SIMM11 : 777 { 778 { 779 FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3)))); 780 FLD (f_disp3) = ((FLD (f_sdisp11)) & (7)); 781 } 782 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 783 if (errmsg) 784 break; 785 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 786 if (errmsg) 787 break; 788 } 789 break; 790 case EPIPHANY_OPERAND_SIMM24 : 791 { 792 long value = fields->f_simm24; 793 value = ((SI) (((value) - (pc))) >> (1)); 794 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer); 795 } 796 break; 797 case EPIPHANY_OPERAND_SIMM3 : 798 errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer); 799 break; 800 case EPIPHANY_OPERAND_SIMM8 : 801 { 802 long value = fields->f_simm8; 803 value = ((SI) (((value) - (pc))) >> (1)); 804 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer); 805 } 806 break; 807 case EPIPHANY_OPERAND_SN : 808 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 809 break; 810 case EPIPHANY_OPERAND_SN6 : 811 { 812 { 813 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 814 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 815 } 816 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 817 if (errmsg) 818 break; 819 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 820 if (errmsg) 821 break; 822 } 823 break; 824 case EPIPHANY_OPERAND_SNDMA : 825 { 826 { 827 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 828 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 829 } 830 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 831 if (errmsg) 832 break; 833 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 834 if (errmsg) 835 break; 836 } 837 break; 838 case EPIPHANY_OPERAND_SNMEM : 839 { 840 { 841 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 842 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 843 } 844 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 845 if (errmsg) 846 break; 847 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 848 if (errmsg) 849 break; 850 } 851 break; 852 case EPIPHANY_OPERAND_SNMESH : 853 { 854 { 855 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 856 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 857 } 858 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 859 if (errmsg) 860 break; 861 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 862 if (errmsg) 863 break; 864 } 865 break; 866 case EPIPHANY_OPERAND_SWI_NUM : 867 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 868 break; 869 case EPIPHANY_OPERAND_TRAPNUM6 : 870 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 871 break; 872 873 default : 874 /* xgettext:c-format */ 875 fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 876 opindex); 877 abort (); 878 } 879 880 return errmsg; 881 } 882 883 int epiphany_cgen_extract_operand 884 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 885 886 /* Main entry point for operand extraction. 887 The result is <= 0 for error, >0 for success. 888 ??? Actual values aren't well defined right now. 889 890 This function is basically just a big switch statement. Earlier versions 891 used tables to look up the function to use, but 892 - if the table contains both assembler and disassembler functions then 893 the disassembler contains much of the assembler and vice-versa, 894 - there's a lot of inlining possibilities as things grow, 895 - using a switch statement avoids the function call overhead. 896 897 This function could be moved into `print_insn_normal', but keeping it 898 separate makes clear the interface between `print_insn_normal' and each of 899 the handlers. */ 900 901 int 902 epiphany_cgen_extract_operand (CGEN_CPU_DESC cd, 903 int opindex, 904 CGEN_EXTRACT_INFO *ex_info, 905 CGEN_INSN_INT insn_value, 906 CGEN_FIELDS * fields, 907 bfd_vma pc) 908 { 909 /* Assume success (for those operands that are nops). */ 910 int length = 1; 911 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 912 913 switch (opindex) 914 { 915 case EPIPHANY_OPERAND_DIRECTION : 916 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx); 917 break; 918 case EPIPHANY_OPERAND_DISP11 : 919 { 920 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 921 if (length <= 0) break; 922 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 923 if (length <= 0) break; 924 { 925 FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3))); 926 } 927 } 928 break; 929 case EPIPHANY_OPERAND_DISP3 : 930 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 931 break; 932 case EPIPHANY_OPERAND_DPMI : 933 length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd); 934 break; 935 case EPIPHANY_OPERAND_FRD : 936 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 937 break; 938 case EPIPHANY_OPERAND_FRD6 : 939 { 940 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 941 if (length <= 0) break; 942 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 943 if (length <= 0) break; 944 { 945 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 946 } 947 } 948 break; 949 case EPIPHANY_OPERAND_FRM : 950 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 951 break; 952 case EPIPHANY_OPERAND_FRM6 : 953 { 954 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 955 if (length <= 0) break; 956 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 957 if (length <= 0) break; 958 { 959 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 960 } 961 } 962 break; 963 case EPIPHANY_OPERAND_FRN : 964 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 965 break; 966 case EPIPHANY_OPERAND_FRN6 : 967 { 968 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 969 if (length <= 0) break; 970 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 971 if (length <= 0) break; 972 { 973 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 974 } 975 } 976 break; 977 case EPIPHANY_OPERAND_IMM16 : 978 { 979 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 980 if (length <= 0) break; 981 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8); 982 if (length <= 0) break; 983 { 984 FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8))); 985 } 986 } 987 break; 988 case EPIPHANY_OPERAND_IMM8 : 989 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 990 break; 991 case EPIPHANY_OPERAND_RD : 992 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 993 break; 994 case EPIPHANY_OPERAND_RD6 : 995 { 996 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 997 if (length <= 0) break; 998 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 999 if (length <= 0) break; 1000 { 1001 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 1002 } 1003 } 1004 break; 1005 case EPIPHANY_OPERAND_RM : 1006 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1007 break; 1008 case EPIPHANY_OPERAND_RM6 : 1009 { 1010 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 1011 if (length <= 0) break; 1012 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1013 if (length <= 0) break; 1014 { 1015 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 1016 } 1017 } 1018 break; 1019 case EPIPHANY_OPERAND_RN : 1020 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1021 break; 1022 case EPIPHANY_OPERAND_RN6 : 1023 { 1024 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 1025 if (length <= 0) break; 1026 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1027 if (length <= 0) break; 1028 { 1029 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 1030 } 1031 } 1032 break; 1033 case EPIPHANY_OPERAND_SD : 1034 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1035 break; 1036 case EPIPHANY_OPERAND_SD6 : 1037 { 1038 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1039 if (length <= 0) break; 1040 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1041 if (length <= 0) break; 1042 { 1043 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1044 } 1045 } 1046 break; 1047 case EPIPHANY_OPERAND_SDDMA : 1048 { 1049 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1050 if (length <= 0) break; 1051 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1052 if (length <= 0) break; 1053 { 1054 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1055 } 1056 } 1057 break; 1058 case EPIPHANY_OPERAND_SDMEM : 1059 { 1060 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1061 if (length <= 0) break; 1062 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1063 if (length <= 0) break; 1064 { 1065 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1066 } 1067 } 1068 break; 1069 case EPIPHANY_OPERAND_SDMESH : 1070 { 1071 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1072 if (length <= 0) break; 1073 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1074 if (length <= 0) break; 1075 { 1076 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1077 } 1078 } 1079 break; 1080 case EPIPHANY_OPERAND_SHIFT : 1081 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift); 1082 break; 1083 case EPIPHANY_OPERAND_SIMM11 : 1084 { 1085 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 1086 if (length <= 0) break; 1087 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 1088 if (length <= 0) break; 1089 { 1090 FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21)); 1091 } 1092 } 1093 break; 1094 case EPIPHANY_OPERAND_SIMM24 : 1095 { 1096 long value; 1097 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value); 1098 value = ((((value) << (1))) + (pc)); 1099 fields->f_simm24 = value; 1100 } 1101 break; 1102 case EPIPHANY_OPERAND_SIMM3 : 1103 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3); 1104 break; 1105 case EPIPHANY_OPERAND_SIMM8 : 1106 { 1107 long value; 1108 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value); 1109 value = ((((value) << (1))) + (pc)); 1110 fields->f_simm8 = value; 1111 } 1112 break; 1113 case EPIPHANY_OPERAND_SN : 1114 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1115 break; 1116 case EPIPHANY_OPERAND_SN6 : 1117 { 1118 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1119 if (length <= 0) break; 1120 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1121 if (length <= 0) break; 1122 { 1123 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1124 } 1125 } 1126 break; 1127 case EPIPHANY_OPERAND_SNDMA : 1128 { 1129 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1130 if (length <= 0) break; 1131 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1132 if (length <= 0) break; 1133 { 1134 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1135 } 1136 } 1137 break; 1138 case EPIPHANY_OPERAND_SNMEM : 1139 { 1140 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1141 if (length <= 0) break; 1142 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1143 if (length <= 0) break; 1144 { 1145 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1146 } 1147 } 1148 break; 1149 case EPIPHANY_OPERAND_SNMESH : 1150 { 1151 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1152 if (length <= 0) break; 1153 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1154 if (length <= 0) break; 1155 { 1156 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1157 } 1158 } 1159 break; 1160 case EPIPHANY_OPERAND_SWI_NUM : 1161 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1162 break; 1163 case EPIPHANY_OPERAND_TRAPNUM6 : 1164 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1165 break; 1166 1167 default : 1168 /* xgettext:c-format */ 1169 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 1170 opindex); 1171 abort (); 1172 } 1173 1174 return length; 1175 } 1176 1177 cgen_insert_fn * const epiphany_cgen_insert_handlers[] = 1178 { 1179 insert_insn_normal, 1180 }; 1181 1182 cgen_extract_fn * const epiphany_cgen_extract_handlers[] = 1183 { 1184 extract_insn_normal, 1185 }; 1186 1187 int epiphany_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1188 bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1189 1190 /* Getting values from cgen_fields is handled by a collection of functions. 1191 They are distinguished by the type of the VALUE argument they return. 1192 TODO: floating point, inlining support, remove cases where result type 1193 not appropriate. */ 1194 1195 int 1196 epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1197 int opindex, 1198 const CGEN_FIELDS * fields) 1199 { 1200 int value; 1201 1202 switch (opindex) 1203 { 1204 case EPIPHANY_OPERAND_DIRECTION : 1205 value = fields->f_addsubx; 1206 break; 1207 case EPIPHANY_OPERAND_DISP11 : 1208 value = fields->f_disp11; 1209 break; 1210 case EPIPHANY_OPERAND_DISP3 : 1211 value = fields->f_disp3; 1212 break; 1213 case EPIPHANY_OPERAND_DPMI : 1214 value = fields->f_subd; 1215 break; 1216 case EPIPHANY_OPERAND_FRD : 1217 value = fields->f_rd; 1218 break; 1219 case EPIPHANY_OPERAND_FRD6 : 1220 value = fields->f_rd6; 1221 break; 1222 case EPIPHANY_OPERAND_FRM : 1223 value = fields->f_rm; 1224 break; 1225 case EPIPHANY_OPERAND_FRM6 : 1226 value = fields->f_rm6; 1227 break; 1228 case EPIPHANY_OPERAND_FRN : 1229 value = fields->f_rn; 1230 break; 1231 case EPIPHANY_OPERAND_FRN6 : 1232 value = fields->f_rn6; 1233 break; 1234 case EPIPHANY_OPERAND_IMM16 : 1235 value = fields->f_imm16; 1236 break; 1237 case EPIPHANY_OPERAND_IMM8 : 1238 value = fields->f_imm8; 1239 break; 1240 case EPIPHANY_OPERAND_RD : 1241 value = fields->f_rd; 1242 break; 1243 case EPIPHANY_OPERAND_RD6 : 1244 value = fields->f_rd6; 1245 break; 1246 case EPIPHANY_OPERAND_RM : 1247 value = fields->f_rm; 1248 break; 1249 case EPIPHANY_OPERAND_RM6 : 1250 value = fields->f_rm6; 1251 break; 1252 case EPIPHANY_OPERAND_RN : 1253 value = fields->f_rn; 1254 break; 1255 case EPIPHANY_OPERAND_RN6 : 1256 value = fields->f_rn6; 1257 break; 1258 case EPIPHANY_OPERAND_SD : 1259 value = fields->f_sd; 1260 break; 1261 case EPIPHANY_OPERAND_SD6 : 1262 value = fields->f_sd6; 1263 break; 1264 case EPIPHANY_OPERAND_SDDMA : 1265 value = fields->f_sd6; 1266 break; 1267 case EPIPHANY_OPERAND_SDMEM : 1268 value = fields->f_sd6; 1269 break; 1270 case EPIPHANY_OPERAND_SDMESH : 1271 value = fields->f_sd6; 1272 break; 1273 case EPIPHANY_OPERAND_SHIFT : 1274 value = fields->f_shift; 1275 break; 1276 case EPIPHANY_OPERAND_SIMM11 : 1277 value = fields->f_sdisp11; 1278 break; 1279 case EPIPHANY_OPERAND_SIMM24 : 1280 value = fields->f_simm24; 1281 break; 1282 case EPIPHANY_OPERAND_SIMM3 : 1283 value = fields->f_sdisp3; 1284 break; 1285 case EPIPHANY_OPERAND_SIMM8 : 1286 value = fields->f_simm8; 1287 break; 1288 case EPIPHANY_OPERAND_SN : 1289 value = fields->f_sn; 1290 break; 1291 case EPIPHANY_OPERAND_SN6 : 1292 value = fields->f_sn6; 1293 break; 1294 case EPIPHANY_OPERAND_SNDMA : 1295 value = fields->f_sn6; 1296 break; 1297 case EPIPHANY_OPERAND_SNMEM : 1298 value = fields->f_sn6; 1299 break; 1300 case EPIPHANY_OPERAND_SNMESH : 1301 value = fields->f_sn6; 1302 break; 1303 case EPIPHANY_OPERAND_SWI_NUM : 1304 value = fields->f_trap_num; 1305 break; 1306 case EPIPHANY_OPERAND_TRAPNUM6 : 1307 value = fields->f_trap_num; 1308 break; 1309 1310 default : 1311 /* xgettext:c-format */ 1312 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 1313 opindex); 1314 abort (); 1315 } 1316 1317 return value; 1318 } 1319 1320 bfd_vma 1321 epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1322 int opindex, 1323 const CGEN_FIELDS * fields) 1324 { 1325 bfd_vma value; 1326 1327 switch (opindex) 1328 { 1329 case EPIPHANY_OPERAND_DIRECTION : 1330 value = fields->f_addsubx; 1331 break; 1332 case EPIPHANY_OPERAND_DISP11 : 1333 value = fields->f_disp11; 1334 break; 1335 case EPIPHANY_OPERAND_DISP3 : 1336 value = fields->f_disp3; 1337 break; 1338 case EPIPHANY_OPERAND_DPMI : 1339 value = fields->f_subd; 1340 break; 1341 case EPIPHANY_OPERAND_FRD : 1342 value = fields->f_rd; 1343 break; 1344 case EPIPHANY_OPERAND_FRD6 : 1345 value = fields->f_rd6; 1346 break; 1347 case EPIPHANY_OPERAND_FRM : 1348 value = fields->f_rm; 1349 break; 1350 case EPIPHANY_OPERAND_FRM6 : 1351 value = fields->f_rm6; 1352 break; 1353 case EPIPHANY_OPERAND_FRN : 1354 value = fields->f_rn; 1355 break; 1356 case EPIPHANY_OPERAND_FRN6 : 1357 value = fields->f_rn6; 1358 break; 1359 case EPIPHANY_OPERAND_IMM16 : 1360 value = fields->f_imm16; 1361 break; 1362 case EPIPHANY_OPERAND_IMM8 : 1363 value = fields->f_imm8; 1364 break; 1365 case EPIPHANY_OPERAND_RD : 1366 value = fields->f_rd; 1367 break; 1368 case EPIPHANY_OPERAND_RD6 : 1369 value = fields->f_rd6; 1370 break; 1371 case EPIPHANY_OPERAND_RM : 1372 value = fields->f_rm; 1373 break; 1374 case EPIPHANY_OPERAND_RM6 : 1375 value = fields->f_rm6; 1376 break; 1377 case EPIPHANY_OPERAND_RN : 1378 value = fields->f_rn; 1379 break; 1380 case EPIPHANY_OPERAND_RN6 : 1381 value = fields->f_rn6; 1382 break; 1383 case EPIPHANY_OPERAND_SD : 1384 value = fields->f_sd; 1385 break; 1386 case EPIPHANY_OPERAND_SD6 : 1387 value = fields->f_sd6; 1388 break; 1389 case EPIPHANY_OPERAND_SDDMA : 1390 value = fields->f_sd6; 1391 break; 1392 case EPIPHANY_OPERAND_SDMEM : 1393 value = fields->f_sd6; 1394 break; 1395 case EPIPHANY_OPERAND_SDMESH : 1396 value = fields->f_sd6; 1397 break; 1398 case EPIPHANY_OPERAND_SHIFT : 1399 value = fields->f_shift; 1400 break; 1401 case EPIPHANY_OPERAND_SIMM11 : 1402 value = fields->f_sdisp11; 1403 break; 1404 case EPIPHANY_OPERAND_SIMM24 : 1405 value = fields->f_simm24; 1406 break; 1407 case EPIPHANY_OPERAND_SIMM3 : 1408 value = fields->f_sdisp3; 1409 break; 1410 case EPIPHANY_OPERAND_SIMM8 : 1411 value = fields->f_simm8; 1412 break; 1413 case EPIPHANY_OPERAND_SN : 1414 value = fields->f_sn; 1415 break; 1416 case EPIPHANY_OPERAND_SN6 : 1417 value = fields->f_sn6; 1418 break; 1419 case EPIPHANY_OPERAND_SNDMA : 1420 value = fields->f_sn6; 1421 break; 1422 case EPIPHANY_OPERAND_SNMEM : 1423 value = fields->f_sn6; 1424 break; 1425 case EPIPHANY_OPERAND_SNMESH : 1426 value = fields->f_sn6; 1427 break; 1428 case EPIPHANY_OPERAND_SWI_NUM : 1429 value = fields->f_trap_num; 1430 break; 1431 case EPIPHANY_OPERAND_TRAPNUM6 : 1432 value = fields->f_trap_num; 1433 break; 1434 1435 default : 1436 /* xgettext:c-format */ 1437 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 1438 opindex); 1439 abort (); 1440 } 1441 1442 return value; 1443 } 1444 1445 void epiphany_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1446 void epiphany_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1447 1448 /* Stuffing values in cgen_fields is handled by a collection of functions. 1449 They are distinguished by the type of the VALUE argument they accept. 1450 TODO: floating point, inlining support, remove cases where argument type 1451 not appropriate. */ 1452 1453 void 1454 epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1455 int opindex, 1456 CGEN_FIELDS * fields, 1457 int value) 1458 { 1459 switch (opindex) 1460 { 1461 case EPIPHANY_OPERAND_DIRECTION : 1462 fields->f_addsubx = value; 1463 break; 1464 case EPIPHANY_OPERAND_DISP11 : 1465 fields->f_disp11 = value; 1466 break; 1467 case EPIPHANY_OPERAND_DISP3 : 1468 fields->f_disp3 = value; 1469 break; 1470 case EPIPHANY_OPERAND_DPMI : 1471 fields->f_subd = value; 1472 break; 1473 case EPIPHANY_OPERAND_FRD : 1474 fields->f_rd = value; 1475 break; 1476 case EPIPHANY_OPERAND_FRD6 : 1477 fields->f_rd6 = value; 1478 break; 1479 case EPIPHANY_OPERAND_FRM : 1480 fields->f_rm = value; 1481 break; 1482 case EPIPHANY_OPERAND_FRM6 : 1483 fields->f_rm6 = value; 1484 break; 1485 case EPIPHANY_OPERAND_FRN : 1486 fields->f_rn = value; 1487 break; 1488 case EPIPHANY_OPERAND_FRN6 : 1489 fields->f_rn6 = value; 1490 break; 1491 case EPIPHANY_OPERAND_IMM16 : 1492 fields->f_imm16 = value; 1493 break; 1494 case EPIPHANY_OPERAND_IMM8 : 1495 fields->f_imm8 = value; 1496 break; 1497 case EPIPHANY_OPERAND_RD : 1498 fields->f_rd = value; 1499 break; 1500 case EPIPHANY_OPERAND_RD6 : 1501 fields->f_rd6 = value; 1502 break; 1503 case EPIPHANY_OPERAND_RM : 1504 fields->f_rm = value; 1505 break; 1506 case EPIPHANY_OPERAND_RM6 : 1507 fields->f_rm6 = value; 1508 break; 1509 case EPIPHANY_OPERAND_RN : 1510 fields->f_rn = value; 1511 break; 1512 case EPIPHANY_OPERAND_RN6 : 1513 fields->f_rn6 = value; 1514 break; 1515 case EPIPHANY_OPERAND_SD : 1516 fields->f_sd = value; 1517 break; 1518 case EPIPHANY_OPERAND_SD6 : 1519 fields->f_sd6 = value; 1520 break; 1521 case EPIPHANY_OPERAND_SDDMA : 1522 fields->f_sd6 = value; 1523 break; 1524 case EPIPHANY_OPERAND_SDMEM : 1525 fields->f_sd6 = value; 1526 break; 1527 case EPIPHANY_OPERAND_SDMESH : 1528 fields->f_sd6 = value; 1529 break; 1530 case EPIPHANY_OPERAND_SHIFT : 1531 fields->f_shift = value; 1532 break; 1533 case EPIPHANY_OPERAND_SIMM11 : 1534 fields->f_sdisp11 = value; 1535 break; 1536 case EPIPHANY_OPERAND_SIMM24 : 1537 fields->f_simm24 = value; 1538 break; 1539 case EPIPHANY_OPERAND_SIMM3 : 1540 fields->f_sdisp3 = value; 1541 break; 1542 case EPIPHANY_OPERAND_SIMM8 : 1543 fields->f_simm8 = value; 1544 break; 1545 case EPIPHANY_OPERAND_SN : 1546 fields->f_sn = value; 1547 break; 1548 case EPIPHANY_OPERAND_SN6 : 1549 fields->f_sn6 = value; 1550 break; 1551 case EPIPHANY_OPERAND_SNDMA : 1552 fields->f_sn6 = value; 1553 break; 1554 case EPIPHANY_OPERAND_SNMEM : 1555 fields->f_sn6 = value; 1556 break; 1557 case EPIPHANY_OPERAND_SNMESH : 1558 fields->f_sn6 = value; 1559 break; 1560 case EPIPHANY_OPERAND_SWI_NUM : 1561 fields->f_trap_num = value; 1562 break; 1563 case EPIPHANY_OPERAND_TRAPNUM6 : 1564 fields->f_trap_num = value; 1565 break; 1566 1567 default : 1568 /* xgettext:c-format */ 1569 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 1570 opindex); 1571 abort (); 1572 } 1573 } 1574 1575 void 1576 epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1577 int opindex, 1578 CGEN_FIELDS * fields, 1579 bfd_vma value) 1580 { 1581 switch (opindex) 1582 { 1583 case EPIPHANY_OPERAND_DIRECTION : 1584 fields->f_addsubx = value; 1585 break; 1586 case EPIPHANY_OPERAND_DISP11 : 1587 fields->f_disp11 = value; 1588 break; 1589 case EPIPHANY_OPERAND_DISP3 : 1590 fields->f_disp3 = value; 1591 break; 1592 case EPIPHANY_OPERAND_DPMI : 1593 fields->f_subd = value; 1594 break; 1595 case EPIPHANY_OPERAND_FRD : 1596 fields->f_rd = value; 1597 break; 1598 case EPIPHANY_OPERAND_FRD6 : 1599 fields->f_rd6 = value; 1600 break; 1601 case EPIPHANY_OPERAND_FRM : 1602 fields->f_rm = value; 1603 break; 1604 case EPIPHANY_OPERAND_FRM6 : 1605 fields->f_rm6 = value; 1606 break; 1607 case EPIPHANY_OPERAND_FRN : 1608 fields->f_rn = value; 1609 break; 1610 case EPIPHANY_OPERAND_FRN6 : 1611 fields->f_rn6 = value; 1612 break; 1613 case EPIPHANY_OPERAND_IMM16 : 1614 fields->f_imm16 = value; 1615 break; 1616 case EPIPHANY_OPERAND_IMM8 : 1617 fields->f_imm8 = value; 1618 break; 1619 case EPIPHANY_OPERAND_RD : 1620 fields->f_rd = value; 1621 break; 1622 case EPIPHANY_OPERAND_RD6 : 1623 fields->f_rd6 = value; 1624 break; 1625 case EPIPHANY_OPERAND_RM : 1626 fields->f_rm = value; 1627 break; 1628 case EPIPHANY_OPERAND_RM6 : 1629 fields->f_rm6 = value; 1630 break; 1631 case EPIPHANY_OPERAND_RN : 1632 fields->f_rn = value; 1633 break; 1634 case EPIPHANY_OPERAND_RN6 : 1635 fields->f_rn6 = value; 1636 break; 1637 case EPIPHANY_OPERAND_SD : 1638 fields->f_sd = value; 1639 break; 1640 case EPIPHANY_OPERAND_SD6 : 1641 fields->f_sd6 = value; 1642 break; 1643 case EPIPHANY_OPERAND_SDDMA : 1644 fields->f_sd6 = value; 1645 break; 1646 case EPIPHANY_OPERAND_SDMEM : 1647 fields->f_sd6 = value; 1648 break; 1649 case EPIPHANY_OPERAND_SDMESH : 1650 fields->f_sd6 = value; 1651 break; 1652 case EPIPHANY_OPERAND_SHIFT : 1653 fields->f_shift = value; 1654 break; 1655 case EPIPHANY_OPERAND_SIMM11 : 1656 fields->f_sdisp11 = value; 1657 break; 1658 case EPIPHANY_OPERAND_SIMM24 : 1659 fields->f_simm24 = value; 1660 break; 1661 case EPIPHANY_OPERAND_SIMM3 : 1662 fields->f_sdisp3 = value; 1663 break; 1664 case EPIPHANY_OPERAND_SIMM8 : 1665 fields->f_simm8 = value; 1666 break; 1667 case EPIPHANY_OPERAND_SN : 1668 fields->f_sn = value; 1669 break; 1670 case EPIPHANY_OPERAND_SN6 : 1671 fields->f_sn6 = value; 1672 break; 1673 case EPIPHANY_OPERAND_SNDMA : 1674 fields->f_sn6 = value; 1675 break; 1676 case EPIPHANY_OPERAND_SNMEM : 1677 fields->f_sn6 = value; 1678 break; 1679 case EPIPHANY_OPERAND_SNMESH : 1680 fields->f_sn6 = value; 1681 break; 1682 case EPIPHANY_OPERAND_SWI_NUM : 1683 fields->f_trap_num = value; 1684 break; 1685 case EPIPHANY_OPERAND_TRAPNUM6 : 1686 fields->f_trap_num = value; 1687 break; 1688 1689 default : 1690 /* xgettext:c-format */ 1691 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 1692 opindex); 1693 abort (); 1694 } 1695 } 1696 1697 /* Function to call before using the instruction builder tables. */ 1698 1699 void 1700 epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1701 { 1702 cd->insert_handlers = & epiphany_cgen_insert_handlers[0]; 1703 cd->extract_handlers = & epiphany_cgen_extract_handlers[0]; 1704 1705 cd->insert_operand = epiphany_cgen_insert_operand; 1706 cd->extract_operand = epiphany_cgen_extract_operand; 1707 1708 cd->get_int_operand = epiphany_cgen_get_int_operand; 1709 cd->set_int_operand = epiphany_cgen_set_int_operand; 1710 cd->get_vma_operand = epiphany_cgen_get_vma_operand; 1711 cd->set_vma_operand = epiphany_cgen_set_vma_operand; 1712 } 1713
Indexes created Mon Jun 29 00:24:49 UTC 2026