epiphany-ibld.c revision 1.1.1.2
1 /* Instruction building/extraction support for epiphany. -*- C -*- 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 4 - the resultant file is machine generated, cgen-ibld.in isn't 5 6 Copyright (C) 1996-2015 Free Software Foundation, Inc. 7 8 This file is part of libopcodes. 9 10 This library is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 25 Keep that in mind. */ 26 27 #include "sysdep.h" 28 #include <stdio.h> 29 #include "ansidecl.h" 30 #include "dis-asm.h" 31 #include "bfd.h" 32 #include "symcat.h" 33 #include "epiphany-desc.h" 34 #include "epiphany-opc.h" 35 #include "cgen/basic-modes.h" 36 #include "opintl.h" 37 #include "safe-ctype.h" 38 39 #undef min 40 #define min(a,b) ((a) < (b) ? (a) : (b)) 41 #undef max 42 #define max(a,b) ((a) > (b) ? (a) : (b)) 43 44 /* Used by the ifield rtx function. */ 45 #define FLD(f) (fields->f) 46 47 static const char * insert_normal 48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 50 static const char * insert_insn_normal 51 (CGEN_CPU_DESC, const CGEN_INSN *, 52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 53 static int extract_normal 54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 55 unsigned int, unsigned int, unsigned int, unsigned int, 56 unsigned int, unsigned int, bfd_vma, long *); 57 static int extract_insn_normal 58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 60 #if CGEN_INT_INSN_P 61 static void put_insn_int_value 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 63 #endif 64 #if ! CGEN_INT_INSN_P 65 static CGEN_INLINE void insert_1 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 67 static CGEN_INLINE int fill_cache 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 69 static CGEN_INLINE long extract_1 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 71 #endif 72 73 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift; 212 213 if (CGEN_INSN_LSB0_P) 214 shift = (word_offset + start + 1) - length; 215 else 216 shift = total_length - (word_offset + start + length); 217 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 218 } 219 220 #else /* ! CGEN_INT_INSN_P */ 221 222 { 223 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 224 225 insert_1 (cd, value, start, length, word_length, bufp); 226 } 227 228 #endif /* ! CGEN_INT_INSN_P */ 229 230 return NULL; 231 } 232 233 /* Default insn builder (insert handler). 234 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 235 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 236 recorded in host byte order, otherwise BUFFER is an array of bytes 237 and the value is recorded in target byte order). 238 The result is an error message or NULL if success. */ 239 240 static const char * 241 insert_insn_normal (CGEN_CPU_DESC cd, 242 const CGEN_INSN * insn, 243 CGEN_FIELDS * fields, 244 CGEN_INSN_BYTES_PTR buffer, 245 bfd_vma pc) 246 { 247 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 248 unsigned long value; 249 const CGEN_SYNTAX_CHAR_TYPE * syn; 250 251 CGEN_INIT_INSERT (cd); 252 value = CGEN_INSN_BASE_VALUE (insn); 253 254 /* If we're recording insns as numbers (rather than a string of bytes), 255 target byte order handling is deferred until later. */ 256 257 #if CGEN_INT_INSN_P 258 259 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 260 CGEN_FIELDS_BITSIZE (fields), value); 261 262 #else 263 264 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 265 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 266 value); 267 268 #endif /* ! CGEN_INT_INSN_P */ 269 270 /* ??? It would be better to scan the format's fields. 271 Still need to be able to insert a value based on the operand though; 272 e.g. storing a branch displacement that got resolved later. 273 Needs more thought first. */ 274 275 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 276 { 277 const char *errmsg; 278 279 if (CGEN_SYNTAX_CHAR_P (* syn)) 280 continue; 281 282 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 283 fields, buffer, pc); 284 if (errmsg) 285 return errmsg; 286 } 287 288 return NULL; 289 } 290 291 #if CGEN_INT_INSN_P 292 /* Cover function to store an insn value into an integral insn. Must go here 293 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 294 295 static void 296 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 297 CGEN_INSN_BYTES_PTR buf, 298 int length, 299 int insn_length, 300 CGEN_INSN_INT value) 301 { 302 /* For architectures with insns smaller than the base-insn-bitsize, 303 length may be too big. */ 304 if (length > insn_length) 305 *buf = value; 306 else 307 { 308 int shift = insn_length - length; 309 /* Written this way to avoid undefined behaviour. */ 310 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 311 312 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 313 } 314 } 315 #endif 316 317 /* Operand extraction. */ 319 320 #if ! CGEN_INT_INSN_P 321 322 /* Subroutine of extract_normal. 323 Ensure sufficient bytes are cached in EX_INFO. 324 OFFSET is the offset in bytes from the start of the insn of the value. 325 BYTES is the length of the needed value. 326 Returns 1 for success, 0 for failure. */ 327 328 static CGEN_INLINE int 329 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 330 CGEN_EXTRACT_INFO *ex_info, 331 int offset, 332 int bytes, 333 bfd_vma pc) 334 { 335 /* It's doubtful that the middle part has already been fetched so 336 we don't optimize that case. kiss. */ 337 unsigned int mask; 338 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 339 340 /* First do a quick check. */ 341 mask = (1 << bytes) - 1; 342 if (((ex_info->valid >> offset) & mask) == mask) 343 return 1; 344 345 /* Search for the first byte we need to read. */ 346 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 347 if (! (mask & ex_info->valid)) 348 break; 349 350 if (bytes) 351 { 352 int status; 353 354 pc += offset; 355 status = (*info->read_memory_func) 356 (pc, ex_info->insn_bytes + offset, bytes, info); 357 358 if (status != 0) 359 { 360 (*info->memory_error_func) (status, pc, info); 361 return 0; 362 } 363 364 ex_info->valid |= ((1 << bytes) - 1) << offset; 365 } 366 367 return 1; 368 } 369 370 /* Subroutine of extract_normal. */ 371 372 static CGEN_INLINE long 373 extract_1 (CGEN_CPU_DESC cd, 374 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 375 int start, 376 int length, 377 int word_length, 378 unsigned char *bufp, 379 bfd_vma pc ATTRIBUTE_UNUSED) 380 { 381 unsigned long x; 382 int shift; 383 384 x = cgen_get_insn_value (cd, bufp, word_length); 385 386 if (CGEN_INSN_LSB0_P) 387 shift = (start + 1) - length; 388 else 389 shift = (word_length - (start + length)); 390 return x >> shift; 391 } 392 393 #endif /* ! CGEN_INT_INSN_P */ 394 395 /* Default extraction routine. 396 397 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 398 or sometimes less for cases like the m32r where the base insn size is 32 399 but some insns are 16 bits. 400 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 401 but for generality we take a bitmask of all of them. 402 WORD_OFFSET is the offset in bits from the start of the insn of the value. 403 WORD_LENGTH is the length of the word in bits in which the value resides. 404 START is the starting bit number in the word, architecture origin. 405 LENGTH is the length of VALUE in bits. 406 TOTAL_LENGTH is the total length of the insn in bits. 407 408 Returns 1 for success, 0 for failure. */ 409 410 /* ??? The return code isn't properly used. wip. */ 411 412 /* ??? This doesn't handle bfd_vma's. Create another function when 413 necessary. */ 414 415 static int 416 extract_normal (CGEN_CPU_DESC cd, 417 #if ! CGEN_INT_INSN_P 418 CGEN_EXTRACT_INFO *ex_info, 419 #else 420 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 421 #endif 422 CGEN_INSN_INT insn_value, 423 unsigned int attrs, 424 unsigned int word_offset, 425 unsigned int start, 426 unsigned int length, 427 unsigned int word_length, 428 unsigned int total_length, 429 #if ! CGEN_INT_INSN_P 430 bfd_vma pc, 431 #else 432 bfd_vma pc ATTRIBUTE_UNUSED, 433 #endif 434 long *valuep) 435 { 436 long value, mask; 437 438 /* If LENGTH is zero, this operand doesn't contribute to the value 439 so give it a standard value of zero. */ 440 if (length == 0) 441 { 442 *valuep = 0; 443 return 1; 444 } 445 446 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 447 abort (); 448 449 /* For architectures with insns smaller than the insn-base-bitsize, 450 word_length may be too big. */ 451 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 452 { 453 if (word_offset + word_length > total_length) 454 word_length = total_length - word_offset; 455 } 456 457 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 458 459 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 460 { 461 if (CGEN_INSN_LSB0_P) 462 value = insn_value >> ((word_offset + start + 1) - length); 463 else 464 value = insn_value >> (total_length - ( word_offset + start + length)); 465 } 466 467 #if ! CGEN_INT_INSN_P 468 469 else 470 { 471 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 472 473 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 474 abort (); 475 476 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 477 return 0; 478 479 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 480 } 481 482 #endif /* ! CGEN_INT_INSN_P */ 483 484 /* Written this way to avoid undefined behaviour. */ 485 mask = (((1L << (length - 1)) - 1) << 1) | 1; 486 487 value &= mask; 488 /* sign extend? */ 489 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 490 && (value & (1L << (length - 1)))) 491 value |= ~mask; 492 493 *valuep = value; 494 495 return 1; 496 } 497 498 /* Default insn extractor. 499 500 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 501 The extracted fields are stored in FIELDS. 502 EX_INFO is used to handle reading variable length insns. 503 Return the length of the insn in bits, or 0 if no match, 504 or -1 if an error occurs fetching data (memory_error_func will have 505 been called). */ 506 507 static int 508 extract_insn_normal (CGEN_CPU_DESC cd, 509 const CGEN_INSN *insn, 510 CGEN_EXTRACT_INFO *ex_info, 511 CGEN_INSN_INT insn_value, 512 CGEN_FIELDS *fields, 513 bfd_vma pc) 514 { 515 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 516 const CGEN_SYNTAX_CHAR_TYPE *syn; 517 518 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 519 520 CGEN_INIT_EXTRACT (cd); 521 522 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 523 { 524 int length; 525 526 if (CGEN_SYNTAX_CHAR_P (*syn)) 527 continue; 528 529 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 530 ex_info, insn_value, fields, pc); 531 if (length <= 0) 532 return length; 533 } 534 535 /* We recognized and successfully extracted this insn. */ 536 return CGEN_INSN_BITSIZE (insn); 537 } 538 539 /* Machine generated code added here. */ 541 542 const char * epiphany_cgen_insert_operand 543 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 544 545 /* Main entry point for operand insertion. 546 547 This function is basically just a big switch statement. Earlier versions 548 used tables to look up the function to use, but 549 - if the table contains both assembler and disassembler functions then 550 the disassembler contains much of the assembler and vice-versa, 551 - there's a lot of inlining possibilities as things grow, 552 - using a switch statement avoids the function call overhead. 553 554 This function could be moved into `parse_insn_normal', but keeping it 555 separate makes clear the interface between `parse_insn_normal' and each of 556 the handlers. It's also needed by GAS to insert operands that couldn't be 557 resolved during parsing. */ 558 559 const char * 560 epiphany_cgen_insert_operand (CGEN_CPU_DESC cd, 561 int opindex, 562 CGEN_FIELDS * fields, 563 CGEN_INSN_BYTES_PTR buffer, 564 bfd_vma pc ATTRIBUTE_UNUSED) 565 { 566 const char * errmsg = NULL; 567 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 568 569 switch (opindex) 570 { 571 case EPIPHANY_OPERAND_DIRECTION : 572 errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer); 573 break; 574 case EPIPHANY_OPERAND_DISP11 : 575 { 576 { 577 FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255)); 578 FLD (f_disp3) = ((FLD (f_disp11)) & (7)); 579 } 580 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 581 if (errmsg) 582 break; 583 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 584 if (errmsg) 585 break; 586 } 587 break; 588 case EPIPHANY_OPERAND_DISP3 : 589 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 590 break; 591 case EPIPHANY_OPERAND_DPMI : 592 errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer); 593 break; 594 case EPIPHANY_OPERAND_FRD : 595 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 596 break; 597 case EPIPHANY_OPERAND_FRD6 : 598 { 599 { 600 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 601 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 602 } 603 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 604 if (errmsg) 605 break; 606 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 607 if (errmsg) 608 break; 609 } 610 break; 611 case EPIPHANY_OPERAND_FRM : 612 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 613 break; 614 case EPIPHANY_OPERAND_FRM6 : 615 { 616 { 617 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 618 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 619 } 620 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 621 if (errmsg) 622 break; 623 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 624 if (errmsg) 625 break; 626 } 627 break; 628 case EPIPHANY_OPERAND_FRN : 629 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 630 break; 631 case EPIPHANY_OPERAND_FRN6 : 632 { 633 { 634 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 635 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 636 } 637 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 638 if (errmsg) 639 break; 640 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 641 if (errmsg) 642 break; 643 } 644 break; 645 case EPIPHANY_OPERAND_IMM16 : 646 { 647 { 648 FLD (f_imm8) = ((FLD (f_imm16)) & (255)); 649 FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8)); 650 } 651 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 652 if (errmsg) 653 break; 654 errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer); 655 if (errmsg) 656 break; 657 } 658 break; 659 case EPIPHANY_OPERAND_IMM8 : 660 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 661 break; 662 case EPIPHANY_OPERAND_RD : 663 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 664 break; 665 case EPIPHANY_OPERAND_RD6 : 666 { 667 { 668 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 669 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 670 } 671 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 672 if (errmsg) 673 break; 674 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 675 if (errmsg) 676 break; 677 } 678 break; 679 case EPIPHANY_OPERAND_RM : 680 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 681 break; 682 case EPIPHANY_OPERAND_RM6 : 683 { 684 { 685 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 686 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 687 } 688 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 689 if (errmsg) 690 break; 691 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 692 if (errmsg) 693 break; 694 } 695 break; 696 case EPIPHANY_OPERAND_RN : 697 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 698 break; 699 case EPIPHANY_OPERAND_RN6 : 700 { 701 { 702 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 703 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 704 } 705 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 706 if (errmsg) 707 break; 708 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 709 if (errmsg) 710 break; 711 } 712 break; 713 case EPIPHANY_OPERAND_SD : 714 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 715 break; 716 case EPIPHANY_OPERAND_SD6 : 717 { 718 { 719 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 720 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 721 } 722 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 723 if (errmsg) 724 break; 725 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 726 if (errmsg) 727 break; 728 } 729 break; 730 case EPIPHANY_OPERAND_SDDMA : 731 { 732 { 733 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 734 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 735 } 736 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 737 if (errmsg) 738 break; 739 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 740 if (errmsg) 741 break; 742 } 743 break; 744 case EPIPHANY_OPERAND_SDMEM : 745 { 746 { 747 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 748 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 749 } 750 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 751 if (errmsg) 752 break; 753 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 754 if (errmsg) 755 break; 756 } 757 break; 758 case EPIPHANY_OPERAND_SDMESH : 759 { 760 { 761 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 762 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 763 } 764 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 765 if (errmsg) 766 break; 767 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 768 if (errmsg) 769 break; 770 } 771 break; 772 case EPIPHANY_OPERAND_SHIFT : 773 errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer); 774 break; 775 case EPIPHANY_OPERAND_SIMM11 : 776 { 777 { 778 FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3)))); 779 FLD (f_disp3) = ((FLD (f_sdisp11)) & (7)); 780 } 781 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 782 if (errmsg) 783 break; 784 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 785 if (errmsg) 786 break; 787 } 788 break; 789 case EPIPHANY_OPERAND_SIMM24 : 790 { 791 long value = fields->f_simm24; 792 value = ((SI) (((value) - (pc))) >> (1)); 793 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer); 794 } 795 break; 796 case EPIPHANY_OPERAND_SIMM3 : 797 errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer); 798 break; 799 case EPIPHANY_OPERAND_SIMM8 : 800 { 801 long value = fields->f_simm8; 802 value = ((SI) (((value) - (pc))) >> (1)); 803 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer); 804 } 805 break; 806 case EPIPHANY_OPERAND_SN : 807 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 808 break; 809 case EPIPHANY_OPERAND_SN6 : 810 { 811 { 812 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 813 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 814 } 815 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 816 if (errmsg) 817 break; 818 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 819 if (errmsg) 820 break; 821 } 822 break; 823 case EPIPHANY_OPERAND_SNDMA : 824 { 825 { 826 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 827 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 828 } 829 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 830 if (errmsg) 831 break; 832 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 833 if (errmsg) 834 break; 835 } 836 break; 837 case EPIPHANY_OPERAND_SNMEM : 838 { 839 { 840 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 841 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 842 } 843 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 844 if (errmsg) 845 break; 846 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 847 if (errmsg) 848 break; 849 } 850 break; 851 case EPIPHANY_OPERAND_SNMESH : 852 { 853 { 854 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 855 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 856 } 857 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 858 if (errmsg) 859 break; 860 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 861 if (errmsg) 862 break; 863 } 864 break; 865 case EPIPHANY_OPERAND_SWI_NUM : 866 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 867 break; 868 case EPIPHANY_OPERAND_TRAPNUM6 : 869 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 870 break; 871 872 default : 873 /* xgettext:c-format */ 874 fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 875 opindex); 876 abort (); 877 } 878 879 return errmsg; 880 } 881 882 int epiphany_cgen_extract_operand 883 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 884 885 /* Main entry point for operand extraction. 886 The result is <= 0 for error, >0 for success. 887 ??? Actual values aren't well defined right now. 888 889 This function is basically just a big switch statement. Earlier versions 890 used tables to look up the function to use, but 891 - if the table contains both assembler and disassembler functions then 892 the disassembler contains much of the assembler and vice-versa, 893 - there's a lot of inlining possibilities as things grow, 894 - using a switch statement avoids the function call overhead. 895 896 This function could be moved into `print_insn_normal', but keeping it 897 separate makes clear the interface between `print_insn_normal' and each of 898 the handlers. */ 899 900 int 901 epiphany_cgen_extract_operand (CGEN_CPU_DESC cd, 902 int opindex, 903 CGEN_EXTRACT_INFO *ex_info, 904 CGEN_INSN_INT insn_value, 905 CGEN_FIELDS * fields, 906 bfd_vma pc) 907 { 908 /* Assume success (for those operands that are nops). */ 909 int length = 1; 910 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 911 912 switch (opindex) 913 { 914 case EPIPHANY_OPERAND_DIRECTION : 915 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx); 916 break; 917 case EPIPHANY_OPERAND_DISP11 : 918 { 919 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 920 if (length <= 0) break; 921 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 922 if (length <= 0) break; 923 { 924 FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3))); 925 } 926 } 927 break; 928 case EPIPHANY_OPERAND_DISP3 : 929 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 930 break; 931 case EPIPHANY_OPERAND_DPMI : 932 length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd); 933 break; 934 case EPIPHANY_OPERAND_FRD : 935 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 936 break; 937 case EPIPHANY_OPERAND_FRD6 : 938 { 939 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 940 if (length <= 0) break; 941 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 942 if (length <= 0) break; 943 { 944 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 945 } 946 } 947 break; 948 case EPIPHANY_OPERAND_FRM : 949 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 950 break; 951 case EPIPHANY_OPERAND_FRM6 : 952 { 953 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 954 if (length <= 0) break; 955 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 956 if (length <= 0) break; 957 { 958 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 959 } 960 } 961 break; 962 case EPIPHANY_OPERAND_FRN : 963 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 964 break; 965 case EPIPHANY_OPERAND_FRN6 : 966 { 967 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 968 if (length <= 0) break; 969 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 970 if (length <= 0) break; 971 { 972 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 973 } 974 } 975 break; 976 case EPIPHANY_OPERAND_IMM16 : 977 { 978 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 979 if (length <= 0) break; 980 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8); 981 if (length <= 0) break; 982 { 983 FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8))); 984 } 985 } 986 break; 987 case EPIPHANY_OPERAND_IMM8 : 988 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 989 break; 990 case EPIPHANY_OPERAND_RD : 991 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 992 break; 993 case EPIPHANY_OPERAND_RD6 : 994 { 995 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 996 if (length <= 0) break; 997 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 998 if (length <= 0) break; 999 { 1000 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 1001 } 1002 } 1003 break; 1004 case EPIPHANY_OPERAND_RM : 1005 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1006 break; 1007 case EPIPHANY_OPERAND_RM6 : 1008 { 1009 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 1010 if (length <= 0) break; 1011 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1012 if (length <= 0) break; 1013 { 1014 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 1015 } 1016 } 1017 break; 1018 case EPIPHANY_OPERAND_RN : 1019 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1020 break; 1021 case EPIPHANY_OPERAND_RN6 : 1022 { 1023 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 1024 if (length <= 0) break; 1025 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1026 if (length <= 0) break; 1027 { 1028 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 1029 } 1030 } 1031 break; 1032 case EPIPHANY_OPERAND_SD : 1033 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1034 break; 1035 case EPIPHANY_OPERAND_SD6 : 1036 { 1037 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1038 if (length <= 0) break; 1039 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1040 if (length <= 0) break; 1041 { 1042 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1043 } 1044 } 1045 break; 1046 case EPIPHANY_OPERAND_SDDMA : 1047 { 1048 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1049 if (length <= 0) break; 1050 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1051 if (length <= 0) break; 1052 { 1053 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1054 } 1055 } 1056 break; 1057 case EPIPHANY_OPERAND_SDMEM : 1058 { 1059 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1060 if (length <= 0) break; 1061 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1062 if (length <= 0) break; 1063 { 1064 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1065 } 1066 } 1067 break; 1068 case EPIPHANY_OPERAND_SDMESH : 1069 { 1070 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1071 if (length <= 0) break; 1072 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1073 if (length <= 0) break; 1074 { 1075 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1076 } 1077 } 1078 break; 1079 case EPIPHANY_OPERAND_SHIFT : 1080 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift); 1081 break; 1082 case EPIPHANY_OPERAND_SIMM11 : 1083 { 1084 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 1085 if (length <= 0) break; 1086 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 1087 if (length <= 0) break; 1088 { 1089 FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21)); 1090 } 1091 } 1092 break; 1093 case EPIPHANY_OPERAND_SIMM24 : 1094 { 1095 long value; 1096 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value); 1097 value = ((((value) << (1))) + (pc)); 1098 fields->f_simm24 = value; 1099 } 1100 break; 1101 case EPIPHANY_OPERAND_SIMM3 : 1102 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3); 1103 break; 1104 case EPIPHANY_OPERAND_SIMM8 : 1105 { 1106 long value; 1107 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value); 1108 value = ((((value) << (1))) + (pc)); 1109 fields->f_simm8 = value; 1110 } 1111 break; 1112 case EPIPHANY_OPERAND_SN : 1113 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1114 break; 1115 case EPIPHANY_OPERAND_SN6 : 1116 { 1117 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1118 if (length <= 0) break; 1119 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1120 if (length <= 0) break; 1121 { 1122 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1123 } 1124 } 1125 break; 1126 case EPIPHANY_OPERAND_SNDMA : 1127 { 1128 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1129 if (length <= 0) break; 1130 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1131 if (length <= 0) break; 1132 { 1133 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1134 } 1135 } 1136 break; 1137 case EPIPHANY_OPERAND_SNMEM : 1138 { 1139 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1140 if (length <= 0) break; 1141 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1142 if (length <= 0) break; 1143 { 1144 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1145 } 1146 } 1147 break; 1148 case EPIPHANY_OPERAND_SNMESH : 1149 { 1150 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1151 if (length <= 0) break; 1152 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1153 if (length <= 0) break; 1154 { 1155 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1156 } 1157 } 1158 break; 1159 case EPIPHANY_OPERAND_SWI_NUM : 1160 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1161 break; 1162 case EPIPHANY_OPERAND_TRAPNUM6 : 1163 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1164 break; 1165 1166 default : 1167 /* xgettext:c-format */ 1168 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 1169 opindex); 1170 abort (); 1171 } 1172 1173 return length; 1174 } 1175 1176 cgen_insert_fn * const epiphany_cgen_insert_handlers[] = 1177 { 1178 insert_insn_normal, 1179 }; 1180 1181 cgen_extract_fn * const epiphany_cgen_extract_handlers[] = 1182 { 1183 extract_insn_normal, 1184 }; 1185 1186 int epiphany_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1187 bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1188 1189 /* Getting values from cgen_fields is handled by a collection of functions. 1190 They are distinguished by the type of the VALUE argument they return. 1191 TODO: floating point, inlining support, remove cases where result type 1192 not appropriate. */ 1193 1194 int 1195 epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1196 int opindex, 1197 const CGEN_FIELDS * fields) 1198 { 1199 int value; 1200 1201 switch (opindex) 1202 { 1203 case EPIPHANY_OPERAND_DIRECTION : 1204 value = fields->f_addsubx; 1205 break; 1206 case EPIPHANY_OPERAND_DISP11 : 1207 value = fields->f_disp11; 1208 break; 1209 case EPIPHANY_OPERAND_DISP3 : 1210 value = fields->f_disp3; 1211 break; 1212 case EPIPHANY_OPERAND_DPMI : 1213 value = fields->f_subd; 1214 break; 1215 case EPIPHANY_OPERAND_FRD : 1216 value = fields->f_rd; 1217 break; 1218 case EPIPHANY_OPERAND_FRD6 : 1219 value = fields->f_rd6; 1220 break; 1221 case EPIPHANY_OPERAND_FRM : 1222 value = fields->f_rm; 1223 break; 1224 case EPIPHANY_OPERAND_FRM6 : 1225 value = fields->f_rm6; 1226 break; 1227 case EPIPHANY_OPERAND_FRN : 1228 value = fields->f_rn; 1229 break; 1230 case EPIPHANY_OPERAND_FRN6 : 1231 value = fields->f_rn6; 1232 break; 1233 case EPIPHANY_OPERAND_IMM16 : 1234 value = fields->f_imm16; 1235 break; 1236 case EPIPHANY_OPERAND_IMM8 : 1237 value = fields->f_imm8; 1238 break; 1239 case EPIPHANY_OPERAND_RD : 1240 value = fields->f_rd; 1241 break; 1242 case EPIPHANY_OPERAND_RD6 : 1243 value = fields->f_rd6; 1244 break; 1245 case EPIPHANY_OPERAND_RM : 1246 value = fields->f_rm; 1247 break; 1248 case EPIPHANY_OPERAND_RM6 : 1249 value = fields->f_rm6; 1250 break; 1251 case EPIPHANY_OPERAND_RN : 1252 value = fields->f_rn; 1253 break; 1254 case EPIPHANY_OPERAND_RN6 : 1255 value = fields->f_rn6; 1256 break; 1257 case EPIPHANY_OPERAND_SD : 1258 value = fields->f_sd; 1259 break; 1260 case EPIPHANY_OPERAND_SD6 : 1261 value = fields->f_sd6; 1262 break; 1263 case EPIPHANY_OPERAND_SDDMA : 1264 value = fields->f_sd6; 1265 break; 1266 case EPIPHANY_OPERAND_SDMEM : 1267 value = fields->f_sd6; 1268 break; 1269 case EPIPHANY_OPERAND_SDMESH : 1270 value = fields->f_sd6; 1271 break; 1272 case EPIPHANY_OPERAND_SHIFT : 1273 value = fields->f_shift; 1274 break; 1275 case EPIPHANY_OPERAND_SIMM11 : 1276 value = fields->f_sdisp11; 1277 break; 1278 case EPIPHANY_OPERAND_SIMM24 : 1279 value = fields->f_simm24; 1280 break; 1281 case EPIPHANY_OPERAND_SIMM3 : 1282 value = fields->f_sdisp3; 1283 break; 1284 case EPIPHANY_OPERAND_SIMM8 : 1285 value = fields->f_simm8; 1286 break; 1287 case EPIPHANY_OPERAND_SN : 1288 value = fields->f_sn; 1289 break; 1290 case EPIPHANY_OPERAND_SN6 : 1291 value = fields->f_sn6; 1292 break; 1293 case EPIPHANY_OPERAND_SNDMA : 1294 value = fields->f_sn6; 1295 break; 1296 case EPIPHANY_OPERAND_SNMEM : 1297 value = fields->f_sn6; 1298 break; 1299 case EPIPHANY_OPERAND_SNMESH : 1300 value = fields->f_sn6; 1301 break; 1302 case EPIPHANY_OPERAND_SWI_NUM : 1303 value = fields->f_trap_num; 1304 break; 1305 case EPIPHANY_OPERAND_TRAPNUM6 : 1306 value = fields->f_trap_num; 1307 break; 1308 1309 default : 1310 /* xgettext:c-format */ 1311 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 1312 opindex); 1313 abort (); 1314 } 1315 1316 return value; 1317 } 1318 1319 bfd_vma 1320 epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1321 int opindex, 1322 const CGEN_FIELDS * fields) 1323 { 1324 bfd_vma value; 1325 1326 switch (opindex) 1327 { 1328 case EPIPHANY_OPERAND_DIRECTION : 1329 value = fields->f_addsubx; 1330 break; 1331 case EPIPHANY_OPERAND_DISP11 : 1332 value = fields->f_disp11; 1333 break; 1334 case EPIPHANY_OPERAND_DISP3 : 1335 value = fields->f_disp3; 1336 break; 1337 case EPIPHANY_OPERAND_DPMI : 1338 value = fields->f_subd; 1339 break; 1340 case EPIPHANY_OPERAND_FRD : 1341 value = fields->f_rd; 1342 break; 1343 case EPIPHANY_OPERAND_FRD6 : 1344 value = fields->f_rd6; 1345 break; 1346 case EPIPHANY_OPERAND_FRM : 1347 value = fields->f_rm; 1348 break; 1349 case EPIPHANY_OPERAND_FRM6 : 1350 value = fields->f_rm6; 1351 break; 1352 case EPIPHANY_OPERAND_FRN : 1353 value = fields->f_rn; 1354 break; 1355 case EPIPHANY_OPERAND_FRN6 : 1356 value = fields->f_rn6; 1357 break; 1358 case EPIPHANY_OPERAND_IMM16 : 1359 value = fields->f_imm16; 1360 break; 1361 case EPIPHANY_OPERAND_IMM8 : 1362 value = fields->f_imm8; 1363 break; 1364 case EPIPHANY_OPERAND_RD : 1365 value = fields->f_rd; 1366 break; 1367 case EPIPHANY_OPERAND_RD6 : 1368 value = fields->f_rd6; 1369 break; 1370 case EPIPHANY_OPERAND_RM : 1371 value = fields->f_rm; 1372 break; 1373 case EPIPHANY_OPERAND_RM6 : 1374 value = fields->f_rm6; 1375 break; 1376 case EPIPHANY_OPERAND_RN : 1377 value = fields->f_rn; 1378 break; 1379 case EPIPHANY_OPERAND_RN6 : 1380 value = fields->f_rn6; 1381 break; 1382 case EPIPHANY_OPERAND_SD : 1383 value = fields->f_sd; 1384 break; 1385 case EPIPHANY_OPERAND_SD6 : 1386 value = fields->f_sd6; 1387 break; 1388 case EPIPHANY_OPERAND_SDDMA : 1389 value = fields->f_sd6; 1390 break; 1391 case EPIPHANY_OPERAND_SDMEM : 1392 value = fields->f_sd6; 1393 break; 1394 case EPIPHANY_OPERAND_SDMESH : 1395 value = fields->f_sd6; 1396 break; 1397 case EPIPHANY_OPERAND_SHIFT : 1398 value = fields->f_shift; 1399 break; 1400 case EPIPHANY_OPERAND_SIMM11 : 1401 value = fields->f_sdisp11; 1402 break; 1403 case EPIPHANY_OPERAND_SIMM24 : 1404 value = fields->f_simm24; 1405 break; 1406 case EPIPHANY_OPERAND_SIMM3 : 1407 value = fields->f_sdisp3; 1408 break; 1409 case EPIPHANY_OPERAND_SIMM8 : 1410 value = fields->f_simm8; 1411 break; 1412 case EPIPHANY_OPERAND_SN : 1413 value = fields->f_sn; 1414 break; 1415 case EPIPHANY_OPERAND_SN6 : 1416 value = fields->f_sn6; 1417 break; 1418 case EPIPHANY_OPERAND_SNDMA : 1419 value = fields->f_sn6; 1420 break; 1421 case EPIPHANY_OPERAND_SNMEM : 1422 value = fields->f_sn6; 1423 break; 1424 case EPIPHANY_OPERAND_SNMESH : 1425 value = fields->f_sn6; 1426 break; 1427 case EPIPHANY_OPERAND_SWI_NUM : 1428 value = fields->f_trap_num; 1429 break; 1430 case EPIPHANY_OPERAND_TRAPNUM6 : 1431 value = fields->f_trap_num; 1432 break; 1433 1434 default : 1435 /* xgettext:c-format */ 1436 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 1437 opindex); 1438 abort (); 1439 } 1440 1441 return value; 1442 } 1443 1444 void epiphany_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1445 void epiphany_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1446 1447 /* Stuffing values in cgen_fields is handled by a collection of functions. 1448 They are distinguished by the type of the VALUE argument they accept. 1449 TODO: floating point, inlining support, remove cases where argument type 1450 not appropriate. */ 1451 1452 void 1453 epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1454 int opindex, 1455 CGEN_FIELDS * fields, 1456 int value) 1457 { 1458 switch (opindex) 1459 { 1460 case EPIPHANY_OPERAND_DIRECTION : 1461 fields->f_addsubx = value; 1462 break; 1463 case EPIPHANY_OPERAND_DISP11 : 1464 fields->f_disp11 = value; 1465 break; 1466 case EPIPHANY_OPERAND_DISP3 : 1467 fields->f_disp3 = value; 1468 break; 1469 case EPIPHANY_OPERAND_DPMI : 1470 fields->f_subd = value; 1471 break; 1472 case EPIPHANY_OPERAND_FRD : 1473 fields->f_rd = value; 1474 break; 1475 case EPIPHANY_OPERAND_FRD6 : 1476 fields->f_rd6 = value; 1477 break; 1478 case EPIPHANY_OPERAND_FRM : 1479 fields->f_rm = value; 1480 break; 1481 case EPIPHANY_OPERAND_FRM6 : 1482 fields->f_rm6 = value; 1483 break; 1484 case EPIPHANY_OPERAND_FRN : 1485 fields->f_rn = value; 1486 break; 1487 case EPIPHANY_OPERAND_FRN6 : 1488 fields->f_rn6 = value; 1489 break; 1490 case EPIPHANY_OPERAND_IMM16 : 1491 fields->f_imm16 = value; 1492 break; 1493 case EPIPHANY_OPERAND_IMM8 : 1494 fields->f_imm8 = value; 1495 break; 1496 case EPIPHANY_OPERAND_RD : 1497 fields->f_rd = value; 1498 break; 1499 case EPIPHANY_OPERAND_RD6 : 1500 fields->f_rd6 = value; 1501 break; 1502 case EPIPHANY_OPERAND_RM : 1503 fields->f_rm = value; 1504 break; 1505 case EPIPHANY_OPERAND_RM6 : 1506 fields->f_rm6 = value; 1507 break; 1508 case EPIPHANY_OPERAND_RN : 1509 fields->f_rn = value; 1510 break; 1511 case EPIPHANY_OPERAND_RN6 : 1512 fields->f_rn6 = value; 1513 break; 1514 case EPIPHANY_OPERAND_SD : 1515 fields->f_sd = value; 1516 break; 1517 case EPIPHANY_OPERAND_SD6 : 1518 fields->f_sd6 = value; 1519 break; 1520 case EPIPHANY_OPERAND_SDDMA : 1521 fields->f_sd6 = value; 1522 break; 1523 case EPIPHANY_OPERAND_SDMEM : 1524 fields->f_sd6 = value; 1525 break; 1526 case EPIPHANY_OPERAND_SDMESH : 1527 fields->f_sd6 = value; 1528 break; 1529 case EPIPHANY_OPERAND_SHIFT : 1530 fields->f_shift = value; 1531 break; 1532 case EPIPHANY_OPERAND_SIMM11 : 1533 fields->f_sdisp11 = value; 1534 break; 1535 case EPIPHANY_OPERAND_SIMM24 : 1536 fields->f_simm24 = value; 1537 break; 1538 case EPIPHANY_OPERAND_SIMM3 : 1539 fields->f_sdisp3 = value; 1540 break; 1541 case EPIPHANY_OPERAND_SIMM8 : 1542 fields->f_simm8 = value; 1543 break; 1544 case EPIPHANY_OPERAND_SN : 1545 fields->f_sn = value; 1546 break; 1547 case EPIPHANY_OPERAND_SN6 : 1548 fields->f_sn6 = value; 1549 break; 1550 case EPIPHANY_OPERAND_SNDMA : 1551 fields->f_sn6 = value; 1552 break; 1553 case EPIPHANY_OPERAND_SNMEM : 1554 fields->f_sn6 = value; 1555 break; 1556 case EPIPHANY_OPERAND_SNMESH : 1557 fields->f_sn6 = value; 1558 break; 1559 case EPIPHANY_OPERAND_SWI_NUM : 1560 fields->f_trap_num = value; 1561 break; 1562 case EPIPHANY_OPERAND_TRAPNUM6 : 1563 fields->f_trap_num = value; 1564 break; 1565 1566 default : 1567 /* xgettext:c-format */ 1568 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 1569 opindex); 1570 abort (); 1571 } 1572 } 1573 1574 void 1575 epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1576 int opindex, 1577 CGEN_FIELDS * fields, 1578 bfd_vma value) 1579 { 1580 switch (opindex) 1581 { 1582 case EPIPHANY_OPERAND_DIRECTION : 1583 fields->f_addsubx = value; 1584 break; 1585 case EPIPHANY_OPERAND_DISP11 : 1586 fields->f_disp11 = value; 1587 break; 1588 case EPIPHANY_OPERAND_DISP3 : 1589 fields->f_disp3 = value; 1590 break; 1591 case EPIPHANY_OPERAND_DPMI : 1592 fields->f_subd = value; 1593 break; 1594 case EPIPHANY_OPERAND_FRD : 1595 fields->f_rd = value; 1596 break; 1597 case EPIPHANY_OPERAND_FRD6 : 1598 fields->f_rd6 = value; 1599 break; 1600 case EPIPHANY_OPERAND_FRM : 1601 fields->f_rm = value; 1602 break; 1603 case EPIPHANY_OPERAND_FRM6 : 1604 fields->f_rm6 = value; 1605 break; 1606 case EPIPHANY_OPERAND_FRN : 1607 fields->f_rn = value; 1608 break; 1609 case EPIPHANY_OPERAND_FRN6 : 1610 fields->f_rn6 = value; 1611 break; 1612 case EPIPHANY_OPERAND_IMM16 : 1613 fields->f_imm16 = value; 1614 break; 1615 case EPIPHANY_OPERAND_IMM8 : 1616 fields->f_imm8 = value; 1617 break; 1618 case EPIPHANY_OPERAND_RD : 1619 fields->f_rd = value; 1620 break; 1621 case EPIPHANY_OPERAND_RD6 : 1622 fields->f_rd6 = value; 1623 break; 1624 case EPIPHANY_OPERAND_RM : 1625 fields->f_rm = value; 1626 break; 1627 case EPIPHANY_OPERAND_RM6 : 1628 fields->f_rm6 = value; 1629 break; 1630 case EPIPHANY_OPERAND_RN : 1631 fields->f_rn = value; 1632 break; 1633 case EPIPHANY_OPERAND_RN6 : 1634 fields->f_rn6 = value; 1635 break; 1636 case EPIPHANY_OPERAND_SD : 1637 fields->f_sd = value; 1638 break; 1639 case EPIPHANY_OPERAND_SD6 : 1640 fields->f_sd6 = value; 1641 break; 1642 case EPIPHANY_OPERAND_SDDMA : 1643 fields->f_sd6 = value; 1644 break; 1645 case EPIPHANY_OPERAND_SDMEM : 1646 fields->f_sd6 = value; 1647 break; 1648 case EPIPHANY_OPERAND_SDMESH : 1649 fields->f_sd6 = value; 1650 break; 1651 case EPIPHANY_OPERAND_SHIFT : 1652 fields->f_shift = value; 1653 break; 1654 case EPIPHANY_OPERAND_SIMM11 : 1655 fields->f_sdisp11 = value; 1656 break; 1657 case EPIPHANY_OPERAND_SIMM24 : 1658 fields->f_simm24 = value; 1659 break; 1660 case EPIPHANY_OPERAND_SIMM3 : 1661 fields->f_sdisp3 = value; 1662 break; 1663 case EPIPHANY_OPERAND_SIMM8 : 1664 fields->f_simm8 = value; 1665 break; 1666 case EPIPHANY_OPERAND_SN : 1667 fields->f_sn = value; 1668 break; 1669 case EPIPHANY_OPERAND_SN6 : 1670 fields->f_sn6 = value; 1671 break; 1672 case EPIPHANY_OPERAND_SNDMA : 1673 fields->f_sn6 = value; 1674 break; 1675 case EPIPHANY_OPERAND_SNMEM : 1676 fields->f_sn6 = value; 1677 break; 1678 case EPIPHANY_OPERAND_SNMESH : 1679 fields->f_sn6 = value; 1680 break; 1681 case EPIPHANY_OPERAND_SWI_NUM : 1682 fields->f_trap_num = value; 1683 break; 1684 case EPIPHANY_OPERAND_TRAPNUM6 : 1685 fields->f_trap_num = value; 1686 break; 1687 1688 default : 1689 /* xgettext:c-format */ 1690 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 1691 opindex); 1692 abort (); 1693 } 1694 } 1695 1696 /* Function to call before using the instruction builder tables. */ 1697 1698 void 1699 epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1700 { 1701 cd->insert_handlers = & epiphany_cgen_insert_handlers[0]; 1702 cd->extract_handlers = & epiphany_cgen_extract_handlers[0]; 1703 1704 cd->insert_operand = epiphany_cgen_insert_operand; 1705 cd->extract_operand = epiphany_cgen_extract_operand; 1706 1707 cd->get_int_operand = epiphany_cgen_get_int_operand; 1708 cd->set_int_operand = epiphany_cgen_set_int_operand; 1709 cd->get_vma_operand = epiphany_cgen_get_vma_operand; 1710 cd->set_vma_operand = epiphany_cgen_set_vma_operand; 1711 } 1712
Indexes created Mon Jun 29 00:24:49 UTC 2026