epiphany-ibld.c revision 1.1.1.3
1 /* Instruction building/extraction support for epiphany. -*- C -*- 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 4 - the resultant file is machine generated, cgen-ibld.in isn't 5 6 Copyright (C) 1996-2016 Free Software Foundation, Inc. 7 8 This file is part of libopcodes. 9 10 This library is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 25 Keep that in mind. */ 26 27 #include "sysdep.h" 28 #include <stdio.h> 29 #include "ansidecl.h" 30 #include "dis-asm.h" 31 #include "bfd.h" 32 #include "symcat.h" 33 #include "epiphany-desc.h" 34 #include "epiphany-opc.h" 35 #include "cgen/basic-modes.h" 36 #include "opintl.h" 37 #include "safe-ctype.h" 38 39 #undef min 40 #define min(a,b) ((a) < (b) ? (a) : (b)) 41 #undef max 42 #define max(a,b) ((a) > (b) ? (a) : (b)) 43 44 /* Used by the ifield rtx function. */ 45 #define FLD(f) (fields->f) 46 47 static const char * insert_normal 48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 50 static const char * insert_insn_normal 51 (CGEN_CPU_DESC, const CGEN_INSN *, 52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 53 static int extract_normal 54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 55 unsigned int, unsigned int, unsigned int, unsigned int, 56 unsigned int, unsigned int, bfd_vma, long *); 57 static int extract_insn_normal 58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 60 #if CGEN_INT_INSN_P 61 static void put_insn_int_value 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 63 #endif 64 #if ! CGEN_INT_INSN_P 65 static CGEN_INLINE void insert_1 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 67 static CGEN_INLINE int fill_cache 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 69 static CGEN_INLINE long extract_1 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 71 #endif 72 73 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift_within_word, shift_to_word, shift; 212 213 /* How to shift the value to BIT0 of the word. */ 214 shift_to_word = total_length - (word_offset + word_length); 215 216 /* How to shift the value to the field within the word. */ 217 if (CGEN_INSN_LSB0_P) 218 shift_within_word = start + 1 - length; 219 else 220 shift_within_word = word_length - start - length; 221 222 /* The total SHIFT, then mask in the value. */ 223 shift = shift_to_word + shift_within_word; 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 225 } 226 227 #else /* ! CGEN_INT_INSN_P */ 228 229 { 230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 231 232 insert_1 (cd, value, start, length, word_length, bufp); 233 } 234 235 #endif /* ! CGEN_INT_INSN_P */ 236 237 return NULL; 238 } 239 240 /* Default insn builder (insert handler). 241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 243 recorded in host byte order, otherwise BUFFER is an array of bytes 244 and the value is recorded in target byte order). 245 The result is an error message or NULL if success. */ 246 247 static const char * 248 insert_insn_normal (CGEN_CPU_DESC cd, 249 const CGEN_INSN * insn, 250 CGEN_FIELDS * fields, 251 CGEN_INSN_BYTES_PTR buffer, 252 bfd_vma pc) 253 { 254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 255 unsigned long value; 256 const CGEN_SYNTAX_CHAR_TYPE * syn; 257 258 CGEN_INIT_INSERT (cd); 259 value = CGEN_INSN_BASE_VALUE (insn); 260 261 /* If we're recording insns as numbers (rather than a string of bytes), 262 target byte order handling is deferred until later. */ 263 264 #if CGEN_INT_INSN_P 265 266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 267 CGEN_FIELDS_BITSIZE (fields), value); 268 269 #else 270 271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 272 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 273 value); 274 275 #endif /* ! CGEN_INT_INSN_P */ 276 277 /* ??? It would be better to scan the format's fields. 278 Still need to be able to insert a value based on the operand though; 279 e.g. storing a branch displacement that got resolved later. 280 Needs more thought first. */ 281 282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 283 { 284 const char *errmsg; 285 286 if (CGEN_SYNTAX_CHAR_P (* syn)) 287 continue; 288 289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 290 fields, buffer, pc); 291 if (errmsg) 292 return errmsg; 293 } 294 295 return NULL; 296 } 297 298 #if CGEN_INT_INSN_P 299 /* Cover function to store an insn value into an integral insn. Must go here 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 301 302 static void 303 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 304 CGEN_INSN_BYTES_PTR buf, 305 int length, 306 int insn_length, 307 CGEN_INSN_INT value) 308 { 309 /* For architectures with insns smaller than the base-insn-bitsize, 310 length may be too big. */ 311 if (length > insn_length) 312 *buf = value; 313 else 314 { 315 int shift = insn_length - length; 316 /* Written this way to avoid undefined behaviour. */ 317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 318 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 320 } 321 } 322 #endif 323 324 /* Operand extraction. */ 326 327 #if ! CGEN_INT_INSN_P 328 329 /* Subroutine of extract_normal. 330 Ensure sufficient bytes are cached in EX_INFO. 331 OFFSET is the offset in bytes from the start of the insn of the value. 332 BYTES is the length of the needed value. 333 Returns 1 for success, 0 for failure. */ 334 335 static CGEN_INLINE int 336 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 337 CGEN_EXTRACT_INFO *ex_info, 338 int offset, 339 int bytes, 340 bfd_vma pc) 341 { 342 /* It's doubtful that the middle part has already been fetched so 343 we don't optimize that case. kiss. */ 344 unsigned int mask; 345 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 346 347 /* First do a quick check. */ 348 mask = (1 << bytes) - 1; 349 if (((ex_info->valid >> offset) & mask) == mask) 350 return 1; 351 352 /* Search for the first byte we need to read. */ 353 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 354 if (! (mask & ex_info->valid)) 355 break; 356 357 if (bytes) 358 { 359 int status; 360 361 pc += offset; 362 status = (*info->read_memory_func) 363 (pc, ex_info->insn_bytes + offset, bytes, info); 364 365 if (status != 0) 366 { 367 (*info->memory_error_func) (status, pc, info); 368 return 0; 369 } 370 371 ex_info->valid |= ((1 << bytes) - 1) << offset; 372 } 373 374 return 1; 375 } 376 377 /* Subroutine of extract_normal. */ 378 379 static CGEN_INLINE long 380 extract_1 (CGEN_CPU_DESC cd, 381 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 382 int start, 383 int length, 384 int word_length, 385 unsigned char *bufp, 386 bfd_vma pc ATTRIBUTE_UNUSED) 387 { 388 unsigned long x; 389 int shift; 390 391 x = cgen_get_insn_value (cd, bufp, word_length); 392 393 if (CGEN_INSN_LSB0_P) 394 shift = (start + 1) - length; 395 else 396 shift = (word_length - (start + length)); 397 return x >> shift; 398 } 399 400 #endif /* ! CGEN_INT_INSN_P */ 401 402 /* Default extraction routine. 403 404 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 405 or sometimes less for cases like the m32r where the base insn size is 32 406 but some insns are 16 bits. 407 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 408 but for generality we take a bitmask of all of them. 409 WORD_OFFSET is the offset in bits from the start of the insn of the value. 410 WORD_LENGTH is the length of the word in bits in which the value resides. 411 START is the starting bit number in the word, architecture origin. 412 LENGTH is the length of VALUE in bits. 413 TOTAL_LENGTH is the total length of the insn in bits. 414 415 Returns 1 for success, 0 for failure. */ 416 417 /* ??? The return code isn't properly used. wip. */ 418 419 /* ??? This doesn't handle bfd_vma's. Create another function when 420 necessary. */ 421 422 static int 423 extract_normal (CGEN_CPU_DESC cd, 424 #if ! CGEN_INT_INSN_P 425 CGEN_EXTRACT_INFO *ex_info, 426 #else 427 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 428 #endif 429 CGEN_INSN_INT insn_value, 430 unsigned int attrs, 431 unsigned int word_offset, 432 unsigned int start, 433 unsigned int length, 434 unsigned int word_length, 435 unsigned int total_length, 436 #if ! CGEN_INT_INSN_P 437 bfd_vma pc, 438 #else 439 bfd_vma pc ATTRIBUTE_UNUSED, 440 #endif 441 long *valuep) 442 { 443 long value, mask; 444 445 /* If LENGTH is zero, this operand doesn't contribute to the value 446 so give it a standard value of zero. */ 447 if (length == 0) 448 { 449 *valuep = 0; 450 return 1; 451 } 452 453 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 454 abort (); 455 456 /* For architectures with insns smaller than the insn-base-bitsize, 457 word_length may be too big. */ 458 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 459 { 460 if (word_offset + word_length > total_length) 461 word_length = total_length - word_offset; 462 } 463 464 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 465 466 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 467 { 468 if (CGEN_INSN_LSB0_P) 469 value = insn_value >> ((word_offset + start + 1) - length); 470 else 471 value = insn_value >> (total_length - ( word_offset + start + length)); 472 } 473 474 #if ! CGEN_INT_INSN_P 475 476 else 477 { 478 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 479 480 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 481 abort (); 482 483 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 484 return 0; 485 486 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 487 } 488 489 #endif /* ! CGEN_INT_INSN_P */ 490 491 /* Written this way to avoid undefined behaviour. */ 492 mask = (((1L << (length - 1)) - 1) << 1) | 1; 493 494 value &= mask; 495 /* sign extend? */ 496 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 497 && (value & (1L << (length - 1)))) 498 value |= ~mask; 499 500 *valuep = value; 501 502 return 1; 503 } 504 505 /* Default insn extractor. 506 507 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 508 The extracted fields are stored in FIELDS. 509 EX_INFO is used to handle reading variable length insns. 510 Return the length of the insn in bits, or 0 if no match, 511 or -1 if an error occurs fetching data (memory_error_func will have 512 been called). */ 513 514 static int 515 extract_insn_normal (CGEN_CPU_DESC cd, 516 const CGEN_INSN *insn, 517 CGEN_EXTRACT_INFO *ex_info, 518 CGEN_INSN_INT insn_value, 519 CGEN_FIELDS *fields, 520 bfd_vma pc) 521 { 522 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 523 const CGEN_SYNTAX_CHAR_TYPE *syn; 524 525 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 526 527 CGEN_INIT_EXTRACT (cd); 528 529 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 530 { 531 int length; 532 533 if (CGEN_SYNTAX_CHAR_P (*syn)) 534 continue; 535 536 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 537 ex_info, insn_value, fields, pc); 538 if (length <= 0) 539 return length; 540 } 541 542 /* We recognized and successfully extracted this insn. */ 543 return CGEN_INSN_BITSIZE (insn); 544 } 545 546 /* Machine generated code added here. */ 548 549 const char * epiphany_cgen_insert_operand 550 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 551 552 /* Main entry point for operand insertion. 553 554 This function is basically just a big switch statement. Earlier versions 555 used tables to look up the function to use, but 556 - if the table contains both assembler and disassembler functions then 557 the disassembler contains much of the assembler and vice-versa, 558 - there's a lot of inlining possibilities as things grow, 559 - using a switch statement avoids the function call overhead. 560 561 This function could be moved into `parse_insn_normal', but keeping it 562 separate makes clear the interface between `parse_insn_normal' and each of 563 the handlers. It's also needed by GAS to insert operands that couldn't be 564 resolved during parsing. */ 565 566 const char * 567 epiphany_cgen_insert_operand (CGEN_CPU_DESC cd, 568 int opindex, 569 CGEN_FIELDS * fields, 570 CGEN_INSN_BYTES_PTR buffer, 571 bfd_vma pc ATTRIBUTE_UNUSED) 572 { 573 const char * errmsg = NULL; 574 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 575 576 switch (opindex) 577 { 578 case EPIPHANY_OPERAND_DIRECTION : 579 errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer); 580 break; 581 case EPIPHANY_OPERAND_DISP11 : 582 { 583 { 584 FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255)); 585 FLD (f_disp3) = ((FLD (f_disp11)) & (7)); 586 } 587 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 588 if (errmsg) 589 break; 590 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 591 if (errmsg) 592 break; 593 } 594 break; 595 case EPIPHANY_OPERAND_DISP3 : 596 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 597 break; 598 case EPIPHANY_OPERAND_DPMI : 599 errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer); 600 break; 601 case EPIPHANY_OPERAND_FRD : 602 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 603 break; 604 case EPIPHANY_OPERAND_FRD6 : 605 { 606 { 607 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 608 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 609 } 610 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 611 if (errmsg) 612 break; 613 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 614 if (errmsg) 615 break; 616 } 617 break; 618 case EPIPHANY_OPERAND_FRM : 619 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 620 break; 621 case EPIPHANY_OPERAND_FRM6 : 622 { 623 { 624 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 625 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 626 } 627 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 628 if (errmsg) 629 break; 630 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 631 if (errmsg) 632 break; 633 } 634 break; 635 case EPIPHANY_OPERAND_FRN : 636 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 637 break; 638 case EPIPHANY_OPERAND_FRN6 : 639 { 640 { 641 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 642 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 643 } 644 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 645 if (errmsg) 646 break; 647 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 648 if (errmsg) 649 break; 650 } 651 break; 652 case EPIPHANY_OPERAND_IMM16 : 653 { 654 { 655 FLD (f_imm8) = ((FLD (f_imm16)) & (255)); 656 FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8)); 657 } 658 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 659 if (errmsg) 660 break; 661 errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer); 662 if (errmsg) 663 break; 664 } 665 break; 666 case EPIPHANY_OPERAND_IMM8 : 667 errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); 668 break; 669 case EPIPHANY_OPERAND_RD : 670 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 671 break; 672 case EPIPHANY_OPERAND_RD6 : 673 { 674 { 675 FLD (f_rd) = ((FLD (f_rd6)) & (7)); 676 FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); 677 } 678 errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); 679 if (errmsg) 680 break; 681 errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); 682 if (errmsg) 683 break; 684 } 685 break; 686 case EPIPHANY_OPERAND_RM : 687 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 688 break; 689 case EPIPHANY_OPERAND_RM6 : 690 { 691 { 692 FLD (f_rm) = ((FLD (f_rm6)) & (7)); 693 FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); 694 } 695 errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); 696 if (errmsg) 697 break; 698 errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); 699 if (errmsg) 700 break; 701 } 702 break; 703 case EPIPHANY_OPERAND_RN : 704 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 705 break; 706 case EPIPHANY_OPERAND_RN6 : 707 { 708 { 709 FLD (f_rn) = ((FLD (f_rn6)) & (7)); 710 FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); 711 } 712 errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); 713 if (errmsg) 714 break; 715 errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); 716 if (errmsg) 717 break; 718 } 719 break; 720 case EPIPHANY_OPERAND_SD : 721 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 722 break; 723 case EPIPHANY_OPERAND_SD6 : 724 { 725 { 726 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 727 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 728 } 729 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 730 if (errmsg) 731 break; 732 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 733 if (errmsg) 734 break; 735 } 736 break; 737 case EPIPHANY_OPERAND_SDDMA : 738 { 739 { 740 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 741 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 742 } 743 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 744 if (errmsg) 745 break; 746 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 747 if (errmsg) 748 break; 749 } 750 break; 751 case EPIPHANY_OPERAND_SDMEM : 752 { 753 { 754 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 755 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 756 } 757 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 758 if (errmsg) 759 break; 760 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 761 if (errmsg) 762 break; 763 } 764 break; 765 case EPIPHANY_OPERAND_SDMESH : 766 { 767 { 768 FLD (f_sd) = ((FLD (f_sd6)) & (7)); 769 FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); 770 } 771 errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); 772 if (errmsg) 773 break; 774 errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); 775 if (errmsg) 776 break; 777 } 778 break; 779 case EPIPHANY_OPERAND_SHIFT : 780 errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer); 781 break; 782 case EPIPHANY_OPERAND_SIMM11 : 783 { 784 { 785 FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3)))); 786 FLD (f_disp3) = ((FLD (f_sdisp11)) & (7)); 787 } 788 errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); 789 if (errmsg) 790 break; 791 errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); 792 if (errmsg) 793 break; 794 } 795 break; 796 case EPIPHANY_OPERAND_SIMM24 : 797 { 798 long value = fields->f_simm24; 799 value = ((SI) (((value) - (pc))) >> (1)); 800 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer); 801 } 802 break; 803 case EPIPHANY_OPERAND_SIMM3 : 804 errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer); 805 break; 806 case EPIPHANY_OPERAND_SIMM8 : 807 { 808 long value = fields->f_simm8; 809 value = ((SI) (((value) - (pc))) >> (1)); 810 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer); 811 } 812 break; 813 case EPIPHANY_OPERAND_SN : 814 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 815 break; 816 case EPIPHANY_OPERAND_SN6 : 817 { 818 { 819 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 820 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 821 } 822 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 823 if (errmsg) 824 break; 825 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 826 if (errmsg) 827 break; 828 } 829 break; 830 case EPIPHANY_OPERAND_SNDMA : 831 { 832 { 833 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 834 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 835 } 836 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 837 if (errmsg) 838 break; 839 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 840 if (errmsg) 841 break; 842 } 843 break; 844 case EPIPHANY_OPERAND_SNMEM : 845 { 846 { 847 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 848 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 849 } 850 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 851 if (errmsg) 852 break; 853 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 854 if (errmsg) 855 break; 856 } 857 break; 858 case EPIPHANY_OPERAND_SNMESH : 859 { 860 { 861 FLD (f_sn) = ((FLD (f_sn6)) & (7)); 862 FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); 863 } 864 errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); 865 if (errmsg) 866 break; 867 errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); 868 if (errmsg) 869 break; 870 } 871 break; 872 case EPIPHANY_OPERAND_SWI_NUM : 873 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 874 break; 875 case EPIPHANY_OPERAND_TRAPNUM6 : 876 errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); 877 break; 878 879 default : 880 /* xgettext:c-format */ 881 fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 882 opindex); 883 abort (); 884 } 885 886 return errmsg; 887 } 888 889 int epiphany_cgen_extract_operand 890 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 891 892 /* Main entry point for operand extraction. 893 The result is <= 0 for error, >0 for success. 894 ??? Actual values aren't well defined right now. 895 896 This function is basically just a big switch statement. Earlier versions 897 used tables to look up the function to use, but 898 - if the table contains both assembler and disassembler functions then 899 the disassembler contains much of the assembler and vice-versa, 900 - there's a lot of inlining possibilities as things grow, 901 - using a switch statement avoids the function call overhead. 902 903 This function could be moved into `print_insn_normal', but keeping it 904 separate makes clear the interface between `print_insn_normal' and each of 905 the handlers. */ 906 907 int 908 epiphany_cgen_extract_operand (CGEN_CPU_DESC cd, 909 int opindex, 910 CGEN_EXTRACT_INFO *ex_info, 911 CGEN_INSN_INT insn_value, 912 CGEN_FIELDS * fields, 913 bfd_vma pc) 914 { 915 /* Assume success (for those operands that are nops). */ 916 int length = 1; 917 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 918 919 switch (opindex) 920 { 921 case EPIPHANY_OPERAND_DIRECTION : 922 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx); 923 break; 924 case EPIPHANY_OPERAND_DISP11 : 925 { 926 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 927 if (length <= 0) break; 928 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 929 if (length <= 0) break; 930 { 931 FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3))); 932 } 933 } 934 break; 935 case EPIPHANY_OPERAND_DISP3 : 936 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 937 break; 938 case EPIPHANY_OPERAND_DPMI : 939 length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd); 940 break; 941 case EPIPHANY_OPERAND_FRD : 942 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 943 break; 944 case EPIPHANY_OPERAND_FRD6 : 945 { 946 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 947 if (length <= 0) break; 948 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 949 if (length <= 0) break; 950 { 951 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 952 } 953 } 954 break; 955 case EPIPHANY_OPERAND_FRM : 956 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 957 break; 958 case EPIPHANY_OPERAND_FRM6 : 959 { 960 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 961 if (length <= 0) break; 962 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 963 if (length <= 0) break; 964 { 965 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 966 } 967 } 968 break; 969 case EPIPHANY_OPERAND_FRN : 970 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 971 break; 972 case EPIPHANY_OPERAND_FRN6 : 973 { 974 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 975 if (length <= 0) break; 976 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 977 if (length <= 0) break; 978 { 979 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 980 } 981 } 982 break; 983 case EPIPHANY_OPERAND_IMM16 : 984 { 985 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 986 if (length <= 0) break; 987 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8); 988 if (length <= 0) break; 989 { 990 FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8))); 991 } 992 } 993 break; 994 case EPIPHANY_OPERAND_IMM8 : 995 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); 996 break; 997 case EPIPHANY_OPERAND_RD : 998 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 999 break; 1000 case EPIPHANY_OPERAND_RD6 : 1001 { 1002 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); 1003 if (length <= 0) break; 1004 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); 1005 if (length <= 0) break; 1006 { 1007 FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); 1008 } 1009 } 1010 break; 1011 case EPIPHANY_OPERAND_RM : 1012 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1013 break; 1014 case EPIPHANY_OPERAND_RM6 : 1015 { 1016 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); 1017 if (length <= 0) break; 1018 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); 1019 if (length <= 0) break; 1020 { 1021 FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); 1022 } 1023 } 1024 break; 1025 case EPIPHANY_OPERAND_RN : 1026 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1027 break; 1028 case EPIPHANY_OPERAND_RN6 : 1029 { 1030 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); 1031 if (length <= 0) break; 1032 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); 1033 if (length <= 0) break; 1034 { 1035 FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); 1036 } 1037 } 1038 break; 1039 case EPIPHANY_OPERAND_SD : 1040 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1041 break; 1042 case EPIPHANY_OPERAND_SD6 : 1043 { 1044 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1045 if (length <= 0) break; 1046 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1047 if (length <= 0) break; 1048 { 1049 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1050 } 1051 } 1052 break; 1053 case EPIPHANY_OPERAND_SDDMA : 1054 { 1055 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1056 if (length <= 0) break; 1057 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1058 if (length <= 0) break; 1059 { 1060 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1061 } 1062 } 1063 break; 1064 case EPIPHANY_OPERAND_SDMEM : 1065 { 1066 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1067 if (length <= 0) break; 1068 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1069 if (length <= 0) break; 1070 { 1071 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1072 } 1073 } 1074 break; 1075 case EPIPHANY_OPERAND_SDMESH : 1076 { 1077 length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); 1078 if (length <= 0) break; 1079 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); 1080 if (length <= 0) break; 1081 { 1082 FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); 1083 } 1084 } 1085 break; 1086 case EPIPHANY_OPERAND_SHIFT : 1087 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift); 1088 break; 1089 case EPIPHANY_OPERAND_SIMM11 : 1090 { 1091 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); 1092 if (length <= 0) break; 1093 length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); 1094 if (length <= 0) break; 1095 { 1096 FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21)); 1097 } 1098 } 1099 break; 1100 case EPIPHANY_OPERAND_SIMM24 : 1101 { 1102 long value; 1103 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value); 1104 value = ((((value) << (1))) + (pc)); 1105 fields->f_simm24 = value; 1106 } 1107 break; 1108 case EPIPHANY_OPERAND_SIMM3 : 1109 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3); 1110 break; 1111 case EPIPHANY_OPERAND_SIMM8 : 1112 { 1113 long value; 1114 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value); 1115 value = ((((value) << (1))) + (pc)); 1116 fields->f_simm8 = value; 1117 } 1118 break; 1119 case EPIPHANY_OPERAND_SN : 1120 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1121 break; 1122 case EPIPHANY_OPERAND_SN6 : 1123 { 1124 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1125 if (length <= 0) break; 1126 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1127 if (length <= 0) break; 1128 { 1129 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1130 } 1131 } 1132 break; 1133 case EPIPHANY_OPERAND_SNDMA : 1134 { 1135 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1136 if (length <= 0) break; 1137 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1138 if (length <= 0) break; 1139 { 1140 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1141 } 1142 } 1143 break; 1144 case EPIPHANY_OPERAND_SNMEM : 1145 { 1146 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1147 if (length <= 0) break; 1148 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1149 if (length <= 0) break; 1150 { 1151 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1152 } 1153 } 1154 break; 1155 case EPIPHANY_OPERAND_SNMESH : 1156 { 1157 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); 1158 if (length <= 0) break; 1159 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); 1160 if (length <= 0) break; 1161 { 1162 FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); 1163 } 1164 } 1165 break; 1166 case EPIPHANY_OPERAND_SWI_NUM : 1167 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1168 break; 1169 case EPIPHANY_OPERAND_TRAPNUM6 : 1170 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); 1171 break; 1172 1173 default : 1174 /* xgettext:c-format */ 1175 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 1176 opindex); 1177 abort (); 1178 } 1179 1180 return length; 1181 } 1182 1183 cgen_insert_fn * const epiphany_cgen_insert_handlers[] = 1184 { 1185 insert_insn_normal, 1186 }; 1187 1188 cgen_extract_fn * const epiphany_cgen_extract_handlers[] = 1189 { 1190 extract_insn_normal, 1191 }; 1192 1193 int epiphany_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1194 bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 1195 1196 /* Getting values from cgen_fields is handled by a collection of functions. 1197 They are distinguished by the type of the VALUE argument they return. 1198 TODO: floating point, inlining support, remove cases where result type 1199 not appropriate. */ 1200 1201 int 1202 epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1203 int opindex, 1204 const CGEN_FIELDS * fields) 1205 { 1206 int value; 1207 1208 switch (opindex) 1209 { 1210 case EPIPHANY_OPERAND_DIRECTION : 1211 value = fields->f_addsubx; 1212 break; 1213 case EPIPHANY_OPERAND_DISP11 : 1214 value = fields->f_disp11; 1215 break; 1216 case EPIPHANY_OPERAND_DISP3 : 1217 value = fields->f_disp3; 1218 break; 1219 case EPIPHANY_OPERAND_DPMI : 1220 value = fields->f_subd; 1221 break; 1222 case EPIPHANY_OPERAND_FRD : 1223 value = fields->f_rd; 1224 break; 1225 case EPIPHANY_OPERAND_FRD6 : 1226 value = fields->f_rd6; 1227 break; 1228 case EPIPHANY_OPERAND_FRM : 1229 value = fields->f_rm; 1230 break; 1231 case EPIPHANY_OPERAND_FRM6 : 1232 value = fields->f_rm6; 1233 break; 1234 case EPIPHANY_OPERAND_FRN : 1235 value = fields->f_rn; 1236 break; 1237 case EPIPHANY_OPERAND_FRN6 : 1238 value = fields->f_rn6; 1239 break; 1240 case EPIPHANY_OPERAND_IMM16 : 1241 value = fields->f_imm16; 1242 break; 1243 case EPIPHANY_OPERAND_IMM8 : 1244 value = fields->f_imm8; 1245 break; 1246 case EPIPHANY_OPERAND_RD : 1247 value = fields->f_rd; 1248 break; 1249 case EPIPHANY_OPERAND_RD6 : 1250 value = fields->f_rd6; 1251 break; 1252 case EPIPHANY_OPERAND_RM : 1253 value = fields->f_rm; 1254 break; 1255 case EPIPHANY_OPERAND_RM6 : 1256 value = fields->f_rm6; 1257 break; 1258 case EPIPHANY_OPERAND_RN : 1259 value = fields->f_rn; 1260 break; 1261 case EPIPHANY_OPERAND_RN6 : 1262 value = fields->f_rn6; 1263 break; 1264 case EPIPHANY_OPERAND_SD : 1265 value = fields->f_sd; 1266 break; 1267 case EPIPHANY_OPERAND_SD6 : 1268 value = fields->f_sd6; 1269 break; 1270 case EPIPHANY_OPERAND_SDDMA : 1271 value = fields->f_sd6; 1272 break; 1273 case EPIPHANY_OPERAND_SDMEM : 1274 value = fields->f_sd6; 1275 break; 1276 case EPIPHANY_OPERAND_SDMESH : 1277 value = fields->f_sd6; 1278 break; 1279 case EPIPHANY_OPERAND_SHIFT : 1280 value = fields->f_shift; 1281 break; 1282 case EPIPHANY_OPERAND_SIMM11 : 1283 value = fields->f_sdisp11; 1284 break; 1285 case EPIPHANY_OPERAND_SIMM24 : 1286 value = fields->f_simm24; 1287 break; 1288 case EPIPHANY_OPERAND_SIMM3 : 1289 value = fields->f_sdisp3; 1290 break; 1291 case EPIPHANY_OPERAND_SIMM8 : 1292 value = fields->f_simm8; 1293 break; 1294 case EPIPHANY_OPERAND_SN : 1295 value = fields->f_sn; 1296 break; 1297 case EPIPHANY_OPERAND_SN6 : 1298 value = fields->f_sn6; 1299 break; 1300 case EPIPHANY_OPERAND_SNDMA : 1301 value = fields->f_sn6; 1302 break; 1303 case EPIPHANY_OPERAND_SNMEM : 1304 value = fields->f_sn6; 1305 break; 1306 case EPIPHANY_OPERAND_SNMESH : 1307 value = fields->f_sn6; 1308 break; 1309 case EPIPHANY_OPERAND_SWI_NUM : 1310 value = fields->f_trap_num; 1311 break; 1312 case EPIPHANY_OPERAND_TRAPNUM6 : 1313 value = fields->f_trap_num; 1314 break; 1315 1316 default : 1317 /* xgettext:c-format */ 1318 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 1319 opindex); 1320 abort (); 1321 } 1322 1323 return value; 1324 } 1325 1326 bfd_vma 1327 epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1328 int opindex, 1329 const CGEN_FIELDS * fields) 1330 { 1331 bfd_vma value; 1332 1333 switch (opindex) 1334 { 1335 case EPIPHANY_OPERAND_DIRECTION : 1336 value = fields->f_addsubx; 1337 break; 1338 case EPIPHANY_OPERAND_DISP11 : 1339 value = fields->f_disp11; 1340 break; 1341 case EPIPHANY_OPERAND_DISP3 : 1342 value = fields->f_disp3; 1343 break; 1344 case EPIPHANY_OPERAND_DPMI : 1345 value = fields->f_subd; 1346 break; 1347 case EPIPHANY_OPERAND_FRD : 1348 value = fields->f_rd; 1349 break; 1350 case EPIPHANY_OPERAND_FRD6 : 1351 value = fields->f_rd6; 1352 break; 1353 case EPIPHANY_OPERAND_FRM : 1354 value = fields->f_rm; 1355 break; 1356 case EPIPHANY_OPERAND_FRM6 : 1357 value = fields->f_rm6; 1358 break; 1359 case EPIPHANY_OPERAND_FRN : 1360 value = fields->f_rn; 1361 break; 1362 case EPIPHANY_OPERAND_FRN6 : 1363 value = fields->f_rn6; 1364 break; 1365 case EPIPHANY_OPERAND_IMM16 : 1366 value = fields->f_imm16; 1367 break; 1368 case EPIPHANY_OPERAND_IMM8 : 1369 value = fields->f_imm8; 1370 break; 1371 case EPIPHANY_OPERAND_RD : 1372 value = fields->f_rd; 1373 break; 1374 case EPIPHANY_OPERAND_RD6 : 1375 value = fields->f_rd6; 1376 break; 1377 case EPIPHANY_OPERAND_RM : 1378 value = fields->f_rm; 1379 break; 1380 case EPIPHANY_OPERAND_RM6 : 1381 value = fields->f_rm6; 1382 break; 1383 case EPIPHANY_OPERAND_RN : 1384 value = fields->f_rn; 1385 break; 1386 case EPIPHANY_OPERAND_RN6 : 1387 value = fields->f_rn6; 1388 break; 1389 case EPIPHANY_OPERAND_SD : 1390 value = fields->f_sd; 1391 break; 1392 case EPIPHANY_OPERAND_SD6 : 1393 value = fields->f_sd6; 1394 break; 1395 case EPIPHANY_OPERAND_SDDMA : 1396 value = fields->f_sd6; 1397 break; 1398 case EPIPHANY_OPERAND_SDMEM : 1399 value = fields->f_sd6; 1400 break; 1401 case EPIPHANY_OPERAND_SDMESH : 1402 value = fields->f_sd6; 1403 break; 1404 case EPIPHANY_OPERAND_SHIFT : 1405 value = fields->f_shift; 1406 break; 1407 case EPIPHANY_OPERAND_SIMM11 : 1408 value = fields->f_sdisp11; 1409 break; 1410 case EPIPHANY_OPERAND_SIMM24 : 1411 value = fields->f_simm24; 1412 break; 1413 case EPIPHANY_OPERAND_SIMM3 : 1414 value = fields->f_sdisp3; 1415 break; 1416 case EPIPHANY_OPERAND_SIMM8 : 1417 value = fields->f_simm8; 1418 break; 1419 case EPIPHANY_OPERAND_SN : 1420 value = fields->f_sn; 1421 break; 1422 case EPIPHANY_OPERAND_SN6 : 1423 value = fields->f_sn6; 1424 break; 1425 case EPIPHANY_OPERAND_SNDMA : 1426 value = fields->f_sn6; 1427 break; 1428 case EPIPHANY_OPERAND_SNMEM : 1429 value = fields->f_sn6; 1430 break; 1431 case EPIPHANY_OPERAND_SNMESH : 1432 value = fields->f_sn6; 1433 break; 1434 case EPIPHANY_OPERAND_SWI_NUM : 1435 value = fields->f_trap_num; 1436 break; 1437 case EPIPHANY_OPERAND_TRAPNUM6 : 1438 value = fields->f_trap_num; 1439 break; 1440 1441 default : 1442 /* xgettext:c-format */ 1443 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 1444 opindex); 1445 abort (); 1446 } 1447 1448 return value; 1449 } 1450 1451 void epiphany_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1452 void epiphany_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1453 1454 /* Stuffing values in cgen_fields is handled by a collection of functions. 1455 They are distinguished by the type of the VALUE argument they accept. 1456 TODO: floating point, inlining support, remove cases where argument type 1457 not appropriate. */ 1458 1459 void 1460 epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1461 int opindex, 1462 CGEN_FIELDS * fields, 1463 int value) 1464 { 1465 switch (opindex) 1466 { 1467 case EPIPHANY_OPERAND_DIRECTION : 1468 fields->f_addsubx = value; 1469 break; 1470 case EPIPHANY_OPERAND_DISP11 : 1471 fields->f_disp11 = value; 1472 break; 1473 case EPIPHANY_OPERAND_DISP3 : 1474 fields->f_disp3 = value; 1475 break; 1476 case EPIPHANY_OPERAND_DPMI : 1477 fields->f_subd = value; 1478 break; 1479 case EPIPHANY_OPERAND_FRD : 1480 fields->f_rd = value; 1481 break; 1482 case EPIPHANY_OPERAND_FRD6 : 1483 fields->f_rd6 = value; 1484 break; 1485 case EPIPHANY_OPERAND_FRM : 1486 fields->f_rm = value; 1487 break; 1488 case EPIPHANY_OPERAND_FRM6 : 1489 fields->f_rm6 = value; 1490 break; 1491 case EPIPHANY_OPERAND_FRN : 1492 fields->f_rn = value; 1493 break; 1494 case EPIPHANY_OPERAND_FRN6 : 1495 fields->f_rn6 = value; 1496 break; 1497 case EPIPHANY_OPERAND_IMM16 : 1498 fields->f_imm16 = value; 1499 break; 1500 case EPIPHANY_OPERAND_IMM8 : 1501 fields->f_imm8 = value; 1502 break; 1503 case EPIPHANY_OPERAND_RD : 1504 fields->f_rd = value; 1505 break; 1506 case EPIPHANY_OPERAND_RD6 : 1507 fields->f_rd6 = value; 1508 break; 1509 case EPIPHANY_OPERAND_RM : 1510 fields->f_rm = value; 1511 break; 1512 case EPIPHANY_OPERAND_RM6 : 1513 fields->f_rm6 = value; 1514 break; 1515 case EPIPHANY_OPERAND_RN : 1516 fields->f_rn = value; 1517 break; 1518 case EPIPHANY_OPERAND_RN6 : 1519 fields->f_rn6 = value; 1520 break; 1521 case EPIPHANY_OPERAND_SD : 1522 fields->f_sd = value; 1523 break; 1524 case EPIPHANY_OPERAND_SD6 : 1525 fields->f_sd6 = value; 1526 break; 1527 case EPIPHANY_OPERAND_SDDMA : 1528 fields->f_sd6 = value; 1529 break; 1530 case EPIPHANY_OPERAND_SDMEM : 1531 fields->f_sd6 = value; 1532 break; 1533 case EPIPHANY_OPERAND_SDMESH : 1534 fields->f_sd6 = value; 1535 break; 1536 case EPIPHANY_OPERAND_SHIFT : 1537 fields->f_shift = value; 1538 break; 1539 case EPIPHANY_OPERAND_SIMM11 : 1540 fields->f_sdisp11 = value; 1541 break; 1542 case EPIPHANY_OPERAND_SIMM24 : 1543 fields->f_simm24 = value; 1544 break; 1545 case EPIPHANY_OPERAND_SIMM3 : 1546 fields->f_sdisp3 = value; 1547 break; 1548 case EPIPHANY_OPERAND_SIMM8 : 1549 fields->f_simm8 = value; 1550 break; 1551 case EPIPHANY_OPERAND_SN : 1552 fields->f_sn = value; 1553 break; 1554 case EPIPHANY_OPERAND_SN6 : 1555 fields->f_sn6 = value; 1556 break; 1557 case EPIPHANY_OPERAND_SNDMA : 1558 fields->f_sn6 = value; 1559 break; 1560 case EPIPHANY_OPERAND_SNMEM : 1561 fields->f_sn6 = value; 1562 break; 1563 case EPIPHANY_OPERAND_SNMESH : 1564 fields->f_sn6 = value; 1565 break; 1566 case EPIPHANY_OPERAND_SWI_NUM : 1567 fields->f_trap_num = value; 1568 break; 1569 case EPIPHANY_OPERAND_TRAPNUM6 : 1570 fields->f_trap_num = value; 1571 break; 1572 1573 default : 1574 /* xgettext:c-format */ 1575 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 1576 opindex); 1577 abort (); 1578 } 1579 } 1580 1581 void 1582 epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1583 int opindex, 1584 CGEN_FIELDS * fields, 1585 bfd_vma value) 1586 { 1587 switch (opindex) 1588 { 1589 case EPIPHANY_OPERAND_DIRECTION : 1590 fields->f_addsubx = value; 1591 break; 1592 case EPIPHANY_OPERAND_DISP11 : 1593 fields->f_disp11 = value; 1594 break; 1595 case EPIPHANY_OPERAND_DISP3 : 1596 fields->f_disp3 = value; 1597 break; 1598 case EPIPHANY_OPERAND_DPMI : 1599 fields->f_subd = value; 1600 break; 1601 case EPIPHANY_OPERAND_FRD : 1602 fields->f_rd = value; 1603 break; 1604 case EPIPHANY_OPERAND_FRD6 : 1605 fields->f_rd6 = value; 1606 break; 1607 case EPIPHANY_OPERAND_FRM : 1608 fields->f_rm = value; 1609 break; 1610 case EPIPHANY_OPERAND_FRM6 : 1611 fields->f_rm6 = value; 1612 break; 1613 case EPIPHANY_OPERAND_FRN : 1614 fields->f_rn = value; 1615 break; 1616 case EPIPHANY_OPERAND_FRN6 : 1617 fields->f_rn6 = value; 1618 break; 1619 case EPIPHANY_OPERAND_IMM16 : 1620 fields->f_imm16 = value; 1621 break; 1622 case EPIPHANY_OPERAND_IMM8 : 1623 fields->f_imm8 = value; 1624 break; 1625 case EPIPHANY_OPERAND_RD : 1626 fields->f_rd = value; 1627 break; 1628 case EPIPHANY_OPERAND_RD6 : 1629 fields->f_rd6 = value; 1630 break; 1631 case EPIPHANY_OPERAND_RM : 1632 fields->f_rm = value; 1633 break; 1634 case EPIPHANY_OPERAND_RM6 : 1635 fields->f_rm6 = value; 1636 break; 1637 case EPIPHANY_OPERAND_RN : 1638 fields->f_rn = value; 1639 break; 1640 case EPIPHANY_OPERAND_RN6 : 1641 fields->f_rn6 = value; 1642 break; 1643 case EPIPHANY_OPERAND_SD : 1644 fields->f_sd = value; 1645 break; 1646 case EPIPHANY_OPERAND_SD6 : 1647 fields->f_sd6 = value; 1648 break; 1649 case EPIPHANY_OPERAND_SDDMA : 1650 fields->f_sd6 = value; 1651 break; 1652 case EPIPHANY_OPERAND_SDMEM : 1653 fields->f_sd6 = value; 1654 break; 1655 case EPIPHANY_OPERAND_SDMESH : 1656 fields->f_sd6 = value; 1657 break; 1658 case EPIPHANY_OPERAND_SHIFT : 1659 fields->f_shift = value; 1660 break; 1661 case EPIPHANY_OPERAND_SIMM11 : 1662 fields->f_sdisp11 = value; 1663 break; 1664 case EPIPHANY_OPERAND_SIMM24 : 1665 fields->f_simm24 = value; 1666 break; 1667 case EPIPHANY_OPERAND_SIMM3 : 1668 fields->f_sdisp3 = value; 1669 break; 1670 case EPIPHANY_OPERAND_SIMM8 : 1671 fields->f_simm8 = value; 1672 break; 1673 case EPIPHANY_OPERAND_SN : 1674 fields->f_sn = value; 1675 break; 1676 case EPIPHANY_OPERAND_SN6 : 1677 fields->f_sn6 = value; 1678 break; 1679 case EPIPHANY_OPERAND_SNDMA : 1680 fields->f_sn6 = value; 1681 break; 1682 case EPIPHANY_OPERAND_SNMEM : 1683 fields->f_sn6 = value; 1684 break; 1685 case EPIPHANY_OPERAND_SNMESH : 1686 fields->f_sn6 = value; 1687 break; 1688 case EPIPHANY_OPERAND_SWI_NUM : 1689 fields->f_trap_num = value; 1690 break; 1691 case EPIPHANY_OPERAND_TRAPNUM6 : 1692 fields->f_trap_num = value; 1693 break; 1694 1695 default : 1696 /* xgettext:c-format */ 1697 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 1698 opindex); 1699 abort (); 1700 } 1701 } 1702 1703 /* Function to call before using the instruction builder tables. */ 1704 1705 void 1706 epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1707 { 1708 cd->insert_handlers = & epiphany_cgen_insert_handlers[0]; 1709 cd->extract_handlers = & epiphany_cgen_extract_handlers[0]; 1710 1711 cd->insert_operand = epiphany_cgen_insert_operand; 1712 cd->extract_operand = epiphany_cgen_extract_operand; 1713 1714 cd->get_int_operand = epiphany_cgen_get_int_operand; 1715 cd->set_int_operand = epiphany_cgen_set_int_operand; 1716 cd->get_vma_operand = epiphany_cgen_get_vma_operand; 1717 cd->set_vma_operand = epiphany_cgen_set_vma_operand; 1718 } 1719
Indexes created Mon Jun 29 00:24:49 UTC 2026