armemu.h revision 1.3
1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 3 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 16 17 extern ARMword isize; 18 extern int trace; 19 extern int disas; 20 extern int trace_funcs; 21 extern void print_insn (ARMword); 22 23 /* Condition code values. */ 24 #define EQ 0 25 #define NE 1 26 #define CS 2 27 #define CC 3 28 #define MI 4 29 #define PL 5 30 #define VS 6 31 #define VC 7 32 #define HI 8 33 #define LS 9 34 #define GE 10 35 #define LT 11 36 #define GT 12 37 #define LE 13 38 #define AL 14 39 #define NV 15 40 41 /* Shift Opcodes. */ 42 #define LSL 0 43 #define LSR 1 44 #define ASR 2 45 #define ROR 3 46 47 /* Macros to twiddle the status flags and mode. */ 48 #define NBIT ((unsigned)1L << 31) 49 #define ZBIT (1L << 30) 50 #define CBIT (1L << 29) 51 #define VBIT (1L << 28) 52 #define SBIT (1L << 27) 53 #define GE0 (1L << 16) 54 #define GE1 (1L << 17) 55 #define GE2 (1L << 18) 56 #define GE3 (1L << 19) 57 #define IBIT (1L << 7) 58 #define FBIT (1L << 6) 59 #define IFBITS (3L << 6) 60 #define R15IBIT (1L << 27) 61 #define R15FBIT (1L << 26) 62 #define R15IFBITS (3L << 26) 63 64 #define POS(i) ( (~(i)) >> 31 ) 65 #define NEG(i) ( (i) >> 31 ) 66 67 #ifdef MODET /* Thumb support. */ 68 /* ??? This bit is actually in the low order bit of the PC in the hardware. 69 It isn't clear if the simulator needs to model that or not. */ 70 #define TBIT (1L << 5) 71 #define TFLAG state->TFlag 72 #define SETT state->TFlag = 1 73 #define CLEART state->TFlag = 0 74 #define ASSIGNT(res) state->TFlag = res 75 #define INSN_SIZE (TFLAG ? 2 : 4) 76 #else 77 #define INSN_SIZE 4 78 #endif 79 80 #define NFLAG state->NFlag 81 #define SETN state->NFlag = 1 82 #define CLEARN state->NFlag = 0 83 #define ASSIGNN(res) state->NFlag = res 84 85 #define ZFLAG state->ZFlag 86 #define SETZ state->ZFlag = 1 87 #define CLEARZ state->ZFlag = 0 88 #define ASSIGNZ(res) state->ZFlag = res 89 90 #define CFLAG state->CFlag 91 #define SETC state->CFlag = 1 92 #define CLEARC state->CFlag = 0 93 #define ASSIGNC(res) state->CFlag = res 94 95 #define VFLAG state->VFlag 96 #define SETV state->VFlag = 1 97 #define CLEARV state->VFlag = 0 98 #define ASSIGNV(res) state->VFlag = res 99 100 #define SFLAG state->SFlag 101 #define SETS state->SFlag = 1 102 #define CLEARS state->SFlag = 0 103 #define ASSIGNS(res) state->SFlag = res 104 105 #define IFLAG (state->IFFlags >> 1) 106 #define FFLAG (state->IFFlags & 1) 107 #define IFFLAGS state->IFFlags 108 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) 109 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; 110 111 #define PSR_FBITS (0xff000000L) 112 #define PSR_SBITS (0x00ff0000L) 113 #define PSR_XBITS (0x0000ff00L) 114 #define PSR_CBITS (0x000000ffL) 115 116 #if defined MODE32 || defined MODET 117 #define CCBITS (0xf8000000L) 118 #else 119 #define CCBITS (0xf0000000L) 120 #endif 121 122 #define INTBITS (0xc0L) 123 124 #if defined MODET && defined MODE32 125 #define PCBITS (0xffffffffL) 126 #else 127 #define PCBITS (0xfffffffcL) 128 #endif 129 130 #define MODEBITS (0x1fL) 131 #define R15INTBITS (3L << 26) 132 133 #if defined MODET && defined MODE32 134 #define R15PCBITS (0x03ffffffL) 135 #else 136 #define R15PCBITS (0x03fffffcL) 137 #endif 138 139 #define R15PCMODEBITS (0x03ffffffL) 140 #define R15MODEBITS (0x3L) 141 142 #ifdef MODE32 143 #define PCMASK PCBITS 144 #define PCWRAP(pc) (pc) 145 #else 146 #define PCMASK R15PCBITS 147 #define PCWRAP(pc) ((pc) & R15PCBITS) 148 #endif 149 150 #define PC (state->Reg[15] & PCMASK) 151 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) 152 #define R15INT (state->Reg[15] & R15INTBITS) 153 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) 154 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) 155 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) 156 #define R15PC (state->Reg[15] & R15PCBITS) 157 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) 158 #define R15MODE (state->Reg[15] & R15MODEBITS) 159 160 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27)) 161 #define EINT (IFFLAGS << 6) 162 #define ER15INT (IFFLAGS << 26) 163 #define EMODE (state->Mode) 164 165 #ifdef MODET 166 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) 167 #else 168 #define CPSR (ECC | EINT | EMODE) 169 #endif 170 171 #ifdef MODE32 172 #define PATCHR15 173 #else 174 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC 175 #endif 176 177 #define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) 178 #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) 179 #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) 180 #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) 181 #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) 182 183 #define SETR15PSR(s) \ 184 do \ 185 { \ 186 if (state->Mode == USER26MODE) \ 187 { \ 188 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ 189 ASSIGNN ((state->Reg[15] & NBIT) != 0); \ 190 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ 191 ASSIGNC ((state->Reg[15] & CBIT) != 0); \ 192 ASSIGNV ((state->Reg[15] & VBIT) != 0); \ 193 } \ 194 else \ 195 { \ 196 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ 197 ARMul_R15Altered (state); \ 198 } \ 199 } \ 200 while (0) 201 202 #define SETABORT(i, m, d) \ 203 do \ 204 { \ 205 int SETABORT_mode = (m); \ 206 \ 207 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ 208 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ 209 | (i) | SETABORT_mode)); \ 210 state->Reg[14] = temp - (d); \ 211 } \ 212 while (0) 213 214 #ifndef MODE32 215 #define VECTORS 0x20 216 #define LEGALADDR 0x03ffffff 217 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) 218 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) 219 #endif 220 221 #define INTERNALABORT(address) \ 222 do \ 223 { \ 224 if (address < VECTORS) \ 225 state->Aborted = ARMul_DataAbortV; \ 226 else \ 227 state->Aborted = ARMul_AddrExceptnV; \ 228 } \ 229 while (0) 230 231 #ifdef MODE32 232 #define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) 233 #else 234 #define TAKEABORT \ 235 do \ 236 { \ 237 if (state->Aborted == ARMul_AddrExceptnV) \ 238 ARMul_Abort (state, ARMul_AddrExceptnV); \ 239 else \ 240 ARMul_Abort (state, ARMul_DataAbortV); \ 241 } \ 242 while (0) 243 #endif 244 245 #define CPTAKEABORT \ 246 do \ 247 { \ 248 if (!state->Aborted) \ 249 ARMul_Abort (state, ARMul_UndefinedInstrV); \ 250 else if (state->Aborted == ARMul_AddrExceptnV) \ 251 ARMul_Abort (state, ARMul_AddrExceptnV); \ 252 else \ 253 ARMul_Abort (state, ARMul_DataAbortV); \ 254 } \ 255 while (0); 256 257 258 /* Different ways to start the next instruction. */ 259 #define SEQ 0 260 #define NONSEQ 1 261 #define PCINCEDSEQ 2 262 #define PCINCEDNONSEQ 3 263 #define PRIMEPIPE 4 264 #define RESUME 8 265 266 #define NORMALCYCLE state->NextInstr = 0 267 #define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ 268 #define BUSUSEDINCPCS \ 269 do \ 270 { \ 271 if (! state->is_v4) \ 272 { \ 273 /* A standard PC inc and an S cycle. */ \ 274 state->Reg[15] += isize; \ 275 state->NextInstr = (state->NextInstr & 0xff) | 2; \ 276 } \ 277 } \ 278 while (0) 279 280 #define BUSUSEDINCPCN \ 281 do \ 282 { \ 283 if (state->is_v4) \ 284 BUSUSEDN; \ 285 else \ 286 { \ 287 /* A standard PC inc and an N cycle. */ \ 288 state->Reg[15] += isize; \ 289 state->NextInstr |= 3; \ 290 } \ 291 } \ 292 while (0) 293 294 #define INCPC \ 295 do \ 296 { \ 297 /* A standard PC inc. */ \ 298 state->Reg[15] += isize; \ 299 state->NextInstr |= 2; \ 300 } \ 301 while (0) 302 303 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE 304 305 /* Cycle based emulation. */ 306 307 #define OUTPUTCP(i,a,b) 308 #define NCYCLE 309 #define SCYCLE 310 #define ICYCLE 311 #define CCYCLE 312 #define NEXTCYCLE(c) 313 314 /* Macros to extract parts of instructions. */ 315 #define DESTReg (BITS (12, 15)) 316 #define LHSReg (BITS (16, 19)) 317 #define RHSReg (BITS ( 0, 3)) 318 319 #define DEST (state->Reg[DESTReg]) 320 321 #ifdef MODE32 322 #ifdef MODET 323 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg])) 324 #else 325 #define LHS (state->Reg[LHSReg]) 326 #endif 327 #else 328 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) 329 #endif 330 331 #define MULDESTReg (BITS (16, 19)) 332 #define MULLHSReg (BITS ( 0, 3)) 333 #define MULRHSReg (BITS ( 8, 11)) 334 #define MULACCReg (BITS (12, 15)) 335 336 #define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) 337 #define DPSImmRHS temp = BITS(0,11) ; \ 338 rhs = ARMul_ImmedTable[temp] ; \ 339 if (temp > 255) /* There was a shift. */ \ 340 ASSIGNC (rhs >> 31) ; 341 342 #ifdef MODE32 343 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 344 : GetDPRegRHS (state, instr)) 345 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 346 : GetDPSRegRHS (state, instr)) 347 #else 348 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 349 : GetDPRegRHS (state, instr)) 350 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 351 : GetDPSRegRHS (state, instr)) 352 #endif 353 354 #define LSBase state->Reg[LHSReg] 355 #define LSImmRHS (BITS(0,11)) 356 357 #ifdef MODE32 358 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ 359 : GetLSRegRHS (state, instr)) 360 #else 361 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 362 : GetLSRegRHS (state, instr)) 363 #endif 364 365 #define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ 366 (ARMword) ARMul_BitList[BITS (8, 15)] ) 367 #define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ 368 (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) 369 370 #define SWAPSRC (state->Reg[RHSReg]) 371 372 #define LSCOff (BITS (0, 7) << 2) 373 #define CPNum BITS (8, 11) 374 375 /* Determine if access to coprocessor CP is permitted. 376 The XScale has a register in CP15 which controls access to CP0 - CP13. */ 377 #define CP_ACCESS_ALLOWED(STATE, CP) \ 378 ( ((CP) >= 14) \ 379 || (! (STATE)->is_XScale) \ 380 || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) 381 382 /* Macro to rotate n right by b bits. */ 383 #define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) 384 385 /* Macros to store results of instructions. */ 386 #define WRITEDEST(d) \ 387 do \ 388 { \ 389 if (DESTReg == 15) \ 390 WriteR15 (state, d); \ 391 else \ 392 DEST = d; \ 393 } \ 394 while (0) 395 396 #define WRITESDEST(d) \ 397 do \ 398 { \ 399 if (DESTReg == 15) \ 400 WriteSR15 (state, d); \ 401 else \ 402 { \ 403 DEST = d; \ 404 ARMul_NegZero (state, d); \ 405 } \ 406 } \ 407 while (0) 408 409 #define WRITEDESTB(d) \ 410 do \ 411 { \ 412 if (DESTReg == 15) \ 413 WriteR15Load (state, d); \ 414 else \ 415 DEST = d; \ 416 } \ 417 while (0) 418 419 #define BYTETOBUS(data) ((data & 0xff) | \ 420 ((data & 0xff) << 8) | \ 421 ((data & 0xff) << 16) | \ 422 ((data & 0xff) << 24)) 423 424 #define BUSTOBYTE(address, data) \ 425 do \ 426 { \ 427 if (state->bigendSig) \ 428 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ 429 else \ 430 temp = (data >> ((address & 3) << 3)) & 0xff; \ 431 } \ 432 while (0) 433 434 #define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) 435 #define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) 436 #define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) 437 #define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) 438 439 #define POSBRANCH ((instr & 0x7fffff) << 2) 440 #define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) 441 442 443 /* Values for Emulate. */ 444 #define STOP 0 /* stop */ 445 #define CHANGEMODE 1 /* change mode */ 446 #define ONCE 2 /* execute just one interation */ 447 #define RUN 3 /* continuous execution */ 448 449 /* Stuff that is shared across modes. */ 450 extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ 451 extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ 452 extern char ARMul_BitList[]; /* Number of bits in a byte table. */ 453 454 #define EVENTLISTSIZE 1024L 455 456 /* Thumb support. */ 457 typedef enum 458 { 459 t_undefined, /* Undefined Thumb instruction. */ 460 t_decoded, /* Instruction decoded to ARM equivalent. */ 461 t_branch /* Thumb branch (already processed). */ 462 } 463 tdstate; 464 465 /* Macros to scrutinize instructions. */ 466 #define UNDEF_Test 467 #define UNDEF_Shift 468 #define UNDEF_MSRPC 469 #define UNDEF_MRSPC 470 #define UNDEF_MULPCDest 471 #define UNDEF_MULDestEQOp1 472 #define UNDEF_LSRBPC 473 #define UNDEF_LSRBaseEQOffWb 474 #define UNDEF_LSRBaseEQDestWb 475 #define UNDEF_LSRPCBaseWb 476 #define UNDEF_LSRPCOffWb 477 #define UNDEF_LSMNoRegs 478 #define UNDEF_LSMPCBase 479 #define UNDEF_LSMUserBankWb 480 #define UNDEF_LSMBaseInListWb 481 #define UNDEF_SWPPC 482 #define UNDEF_CoProHS 483 #define UNDEF_MCRPC 484 #define UNDEF_LSCPCBaseWb 485 #define UNDEF_UndefNotBounced 486 #define UNDEF_ShortInt 487 #define UNDEF_IllegalMode 488 #define UNDEF_Prog32SigChange 489 #define UNDEF_Data32SigChange 490 491 /* Prototypes for exported functions. */ 492 extern unsigned ARMul_NthReg (ARMword, unsigned); 493 extern int AddOverflow (ARMword, ARMword, ARMword); 494 extern int SubOverflow (ARMword, ARMword, ARMword); 495 extern ARMword ARMul_Emulate26 (ARMul_State *); 496 extern ARMword ARMul_Emulate32 (ARMul_State *); 497 extern unsigned IntPending (ARMul_State *); 498 extern void ARMul_CPSRAltered (ARMul_State *); 499 extern void ARMul_R15Altered (ARMul_State *); 500 extern ARMword ARMul_GetPC (ARMul_State *); 501 extern ARMword ARMul_GetNextPC (ARMul_State *); 502 extern ARMword ARMul_GetR15 (ARMul_State *); 503 extern ARMword ARMul_GetCPSR (ARMul_State *); 504 extern void ARMul_EnvokeEvent (ARMul_State *); 505 extern unsigned long ARMul_Time (ARMul_State *); 506 extern void ARMul_NegZero (ARMul_State *, ARMword); 507 extern void ARMul_SetPC (ARMul_State *, ARMword); 508 extern void ARMul_SetR15 (ARMul_State *, ARMword); 509 extern void ARMul_SetCPSR (ARMul_State *, ARMword); 510 extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); 511 extern void ARMul_Abort26 (ARMul_State *, ARMword); 512 extern void ARMul_Abort32 (ARMul_State *, ARMword); 513 extern ARMword ARMul_MRC (ARMul_State *, ARMword); 514 extern void ARMul_CDP (ARMul_State *, ARMword); 515 extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); 516 extern void ARMul_STC (ARMul_State *, ARMword, ARMword); 517 extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); 518 extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); 519 extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 520 extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); 521 extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 522 extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); 523 extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); 524 extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); 525 extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); 526 extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); 527 extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); 528 extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); 529 extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); 530 extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *)); 531 /* Coprocessor support functions. */ 532 extern unsigned ARMul_CoProInit (ARMul_State *); 533 extern void ARMul_CoProExit (ARMul_State *); 534 extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *, 535 ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *, 536 ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); 537 extern void ARMul_CoProDetach (ARMul_State *, unsigned); 538 extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); 539 540 extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); 541 extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); 542 extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); 543 extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); 544 extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); 545 extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); 546 extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); 547 extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); 548 extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); 549 extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); 550 extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); 551 extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); 552 extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); 553
Indexes created Sat Jun 27 00:24:51 UTC 2026