sem-switch.c revision 1.11
1 /* Simulator instruction semantics for iq2000bf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2024 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifdef DEFINE_LABELS 26 27 /* The labels have the case they have because the enum of insn types 28 is all uppercase and in the non-stdc case the insn symbol is built 29 into the enum name. */ 30 31 static struct { 32 int index; 33 void *label; 34 } labels[] = { 35 { IQ2000BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, 36 { IQ2000BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, 37 { IQ2000BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, 38 { IQ2000BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, 39 { IQ2000BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, 40 { IQ2000BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, 41 { IQ2000BF_INSN_ADD, && case_sem_INSN_ADD }, 42 { IQ2000BF_INSN_ADDI, && case_sem_INSN_ADDI }, 43 { IQ2000BF_INSN_ADDIU, && case_sem_INSN_ADDIU }, 44 { IQ2000BF_INSN_ADDU, && case_sem_INSN_ADDU }, 45 { IQ2000BF_INSN_ADO16, && case_sem_INSN_ADO16 }, 46 { IQ2000BF_INSN_AND, && case_sem_INSN_AND }, 47 { IQ2000BF_INSN_ANDI, && case_sem_INSN_ANDI }, 48 { IQ2000BF_INSN_ANDOI, && case_sem_INSN_ANDOI }, 49 { IQ2000BF_INSN_NOR, && case_sem_INSN_NOR }, 50 { IQ2000BF_INSN_OR, && case_sem_INSN_OR }, 51 { IQ2000BF_INSN_ORI, && case_sem_INSN_ORI }, 52 { IQ2000BF_INSN_RAM, && case_sem_INSN_RAM }, 53 { IQ2000BF_INSN_SLL, && case_sem_INSN_SLL }, 54 { IQ2000BF_INSN_SLLV, && case_sem_INSN_SLLV }, 55 { IQ2000BF_INSN_SLMV, && case_sem_INSN_SLMV }, 56 { IQ2000BF_INSN_SLT, && case_sem_INSN_SLT }, 57 { IQ2000BF_INSN_SLTI, && case_sem_INSN_SLTI }, 58 { IQ2000BF_INSN_SLTIU, && case_sem_INSN_SLTIU }, 59 { IQ2000BF_INSN_SLTU, && case_sem_INSN_SLTU }, 60 { IQ2000BF_INSN_SRA, && case_sem_INSN_SRA }, 61 { IQ2000BF_INSN_SRAV, && case_sem_INSN_SRAV }, 62 { IQ2000BF_INSN_SRL, && case_sem_INSN_SRL }, 63 { IQ2000BF_INSN_SRLV, && case_sem_INSN_SRLV }, 64 { IQ2000BF_INSN_SRMV, && case_sem_INSN_SRMV }, 65 { IQ2000BF_INSN_SUB, && case_sem_INSN_SUB }, 66 { IQ2000BF_INSN_SUBU, && case_sem_INSN_SUBU }, 67 { IQ2000BF_INSN_XOR, && case_sem_INSN_XOR }, 68 { IQ2000BF_INSN_XORI, && case_sem_INSN_XORI }, 69 { IQ2000BF_INSN_BBI, && case_sem_INSN_BBI }, 70 { IQ2000BF_INSN_BBIN, && case_sem_INSN_BBIN }, 71 { IQ2000BF_INSN_BBV, && case_sem_INSN_BBV }, 72 { IQ2000BF_INSN_BBVN, && case_sem_INSN_BBVN }, 73 { IQ2000BF_INSN_BEQ, && case_sem_INSN_BEQ }, 74 { IQ2000BF_INSN_BEQL, && case_sem_INSN_BEQL }, 75 { IQ2000BF_INSN_BGEZ, && case_sem_INSN_BGEZ }, 76 { IQ2000BF_INSN_BGEZAL, && case_sem_INSN_BGEZAL }, 77 { IQ2000BF_INSN_BGEZALL, && case_sem_INSN_BGEZALL }, 78 { IQ2000BF_INSN_BGEZL, && case_sem_INSN_BGEZL }, 79 { IQ2000BF_INSN_BLTZ, && case_sem_INSN_BLTZ }, 80 { IQ2000BF_INSN_BLTZL, && case_sem_INSN_BLTZL }, 81 { IQ2000BF_INSN_BLTZAL, && case_sem_INSN_BLTZAL }, 82 { IQ2000BF_INSN_BLTZALL, && case_sem_INSN_BLTZALL }, 83 { IQ2000BF_INSN_BMB0, && case_sem_INSN_BMB0 }, 84 { IQ2000BF_INSN_BMB1, && case_sem_INSN_BMB1 }, 85 { IQ2000BF_INSN_BMB2, && case_sem_INSN_BMB2 }, 86 { IQ2000BF_INSN_BMB3, && case_sem_INSN_BMB3 }, 87 { IQ2000BF_INSN_BNE, && case_sem_INSN_BNE }, 88 { IQ2000BF_INSN_BNEL, && case_sem_INSN_BNEL }, 89 { IQ2000BF_INSN_JALR, && case_sem_INSN_JALR }, 90 { IQ2000BF_INSN_JR, && case_sem_INSN_JR }, 91 { IQ2000BF_INSN_LB, && case_sem_INSN_LB }, 92 { IQ2000BF_INSN_LBU, && case_sem_INSN_LBU }, 93 { IQ2000BF_INSN_LH, && case_sem_INSN_LH }, 94 { IQ2000BF_INSN_LHU, && case_sem_INSN_LHU }, 95 { IQ2000BF_INSN_LUI, && case_sem_INSN_LUI }, 96 { IQ2000BF_INSN_LW, && case_sem_INSN_LW }, 97 { IQ2000BF_INSN_SB, && case_sem_INSN_SB }, 98 { IQ2000BF_INSN_SH, && case_sem_INSN_SH }, 99 { IQ2000BF_INSN_SW, && case_sem_INSN_SW }, 100 { IQ2000BF_INSN_BREAK, && case_sem_INSN_BREAK }, 101 { IQ2000BF_INSN_SYSCALL, && case_sem_INSN_SYSCALL }, 102 { IQ2000BF_INSN_ANDOUI, && case_sem_INSN_ANDOUI }, 103 { IQ2000BF_INSN_ORUI, && case_sem_INSN_ORUI }, 104 { IQ2000BF_INSN_BGTZ, && case_sem_INSN_BGTZ }, 105 { IQ2000BF_INSN_BGTZL, && case_sem_INSN_BGTZL }, 106 { IQ2000BF_INSN_BLEZ, && case_sem_INSN_BLEZ }, 107 { IQ2000BF_INSN_BLEZL, && case_sem_INSN_BLEZL }, 108 { IQ2000BF_INSN_MRGB, && case_sem_INSN_MRGB }, 109 { IQ2000BF_INSN_BCTXT, && case_sem_INSN_BCTXT }, 110 { IQ2000BF_INSN_BC0F, && case_sem_INSN_BC0F }, 111 { IQ2000BF_INSN_BC0FL, && case_sem_INSN_BC0FL }, 112 { IQ2000BF_INSN_BC3F, && case_sem_INSN_BC3F }, 113 { IQ2000BF_INSN_BC3FL, && case_sem_INSN_BC3FL }, 114 { IQ2000BF_INSN_BC0T, && case_sem_INSN_BC0T }, 115 { IQ2000BF_INSN_BC0TL, && case_sem_INSN_BC0TL }, 116 { IQ2000BF_INSN_BC3T, && case_sem_INSN_BC3T }, 117 { IQ2000BF_INSN_BC3TL, && case_sem_INSN_BC3TL }, 118 { IQ2000BF_INSN_CFC0, && case_sem_INSN_CFC0 }, 119 { IQ2000BF_INSN_CFC1, && case_sem_INSN_CFC1 }, 120 { IQ2000BF_INSN_CFC2, && case_sem_INSN_CFC2 }, 121 { IQ2000BF_INSN_CFC3, && case_sem_INSN_CFC3 }, 122 { IQ2000BF_INSN_CHKHDR, && case_sem_INSN_CHKHDR }, 123 { IQ2000BF_INSN_CTC0, && case_sem_INSN_CTC0 }, 124 { IQ2000BF_INSN_CTC1, && case_sem_INSN_CTC1 }, 125 { IQ2000BF_INSN_CTC2, && case_sem_INSN_CTC2 }, 126 { IQ2000BF_INSN_CTC3, && case_sem_INSN_CTC3 }, 127 { IQ2000BF_INSN_JCR, && case_sem_INSN_JCR }, 128 { IQ2000BF_INSN_LUC32, && case_sem_INSN_LUC32 }, 129 { IQ2000BF_INSN_LUC32L, && case_sem_INSN_LUC32L }, 130 { IQ2000BF_INSN_LUC64, && case_sem_INSN_LUC64 }, 131 { IQ2000BF_INSN_LUC64L, && case_sem_INSN_LUC64L }, 132 { IQ2000BF_INSN_LUK, && case_sem_INSN_LUK }, 133 { IQ2000BF_INSN_LULCK, && case_sem_INSN_LULCK }, 134 { IQ2000BF_INSN_LUM32, && case_sem_INSN_LUM32 }, 135 { IQ2000BF_INSN_LUM32L, && case_sem_INSN_LUM32L }, 136 { IQ2000BF_INSN_LUM64, && case_sem_INSN_LUM64 }, 137 { IQ2000BF_INSN_LUM64L, && case_sem_INSN_LUM64L }, 138 { IQ2000BF_INSN_LUR, && case_sem_INSN_LUR }, 139 { IQ2000BF_INSN_LURL, && case_sem_INSN_LURL }, 140 { IQ2000BF_INSN_LUULCK, && case_sem_INSN_LUULCK }, 141 { IQ2000BF_INSN_MFC0, && case_sem_INSN_MFC0 }, 142 { IQ2000BF_INSN_MFC1, && case_sem_INSN_MFC1 }, 143 { IQ2000BF_INSN_MFC2, && case_sem_INSN_MFC2 }, 144 { IQ2000BF_INSN_MFC3, && case_sem_INSN_MFC3 }, 145 { IQ2000BF_INSN_MTC0, && case_sem_INSN_MTC0 }, 146 { IQ2000BF_INSN_MTC1, && case_sem_INSN_MTC1 }, 147 { IQ2000BF_INSN_MTC2, && case_sem_INSN_MTC2 }, 148 { IQ2000BF_INSN_MTC3, && case_sem_INSN_MTC3 }, 149 { IQ2000BF_INSN_PKRL, && case_sem_INSN_PKRL }, 150 { IQ2000BF_INSN_PKRLR1, && case_sem_INSN_PKRLR1 }, 151 { IQ2000BF_INSN_PKRLR30, && case_sem_INSN_PKRLR30 }, 152 { IQ2000BF_INSN_RB, && case_sem_INSN_RB }, 153 { IQ2000BF_INSN_RBR1, && case_sem_INSN_RBR1 }, 154 { IQ2000BF_INSN_RBR30, && case_sem_INSN_RBR30 }, 155 { IQ2000BF_INSN_RFE, && case_sem_INSN_RFE }, 156 { IQ2000BF_INSN_RX, && case_sem_INSN_RX }, 157 { IQ2000BF_INSN_RXR1, && case_sem_INSN_RXR1 }, 158 { IQ2000BF_INSN_RXR30, && case_sem_INSN_RXR30 }, 159 { IQ2000BF_INSN_SLEEP, && case_sem_INSN_SLEEP }, 160 { IQ2000BF_INSN_SRRD, && case_sem_INSN_SRRD }, 161 { IQ2000BF_INSN_SRRDL, && case_sem_INSN_SRRDL }, 162 { IQ2000BF_INSN_SRULCK, && case_sem_INSN_SRULCK }, 163 { IQ2000BF_INSN_SRWR, && case_sem_INSN_SRWR }, 164 { IQ2000BF_INSN_SRWRU, && case_sem_INSN_SRWRU }, 165 { IQ2000BF_INSN_TRAPQFL, && case_sem_INSN_TRAPQFL }, 166 { IQ2000BF_INSN_TRAPQNE, && case_sem_INSN_TRAPQNE }, 167 { IQ2000BF_INSN_TRAPREL, && case_sem_INSN_TRAPREL }, 168 { IQ2000BF_INSN_WB, && case_sem_INSN_WB }, 169 { IQ2000BF_INSN_WBU, && case_sem_INSN_WBU }, 170 { IQ2000BF_INSN_WBR1, && case_sem_INSN_WBR1 }, 171 { IQ2000BF_INSN_WBR1U, && case_sem_INSN_WBR1U }, 172 { IQ2000BF_INSN_WBR30, && case_sem_INSN_WBR30 }, 173 { IQ2000BF_INSN_WBR30U, && case_sem_INSN_WBR30U }, 174 { IQ2000BF_INSN_WX, && case_sem_INSN_WX }, 175 { IQ2000BF_INSN_WXU, && case_sem_INSN_WXU }, 176 { IQ2000BF_INSN_WXR1, && case_sem_INSN_WXR1 }, 177 { IQ2000BF_INSN_WXR1U, && case_sem_INSN_WXR1U }, 178 { IQ2000BF_INSN_WXR30, && case_sem_INSN_WXR30 }, 179 { IQ2000BF_INSN_WXR30U, && case_sem_INSN_WXR30U }, 180 { IQ2000BF_INSN_LDW, && case_sem_INSN_LDW }, 181 { IQ2000BF_INSN_SDW, && case_sem_INSN_SDW }, 182 { IQ2000BF_INSN_J, && case_sem_INSN_J }, 183 { IQ2000BF_INSN_JAL, && case_sem_INSN_JAL }, 184 { IQ2000BF_INSN_BMB, && case_sem_INSN_BMB }, 185 { 0, 0 } 186 }; 187 int i; 188 189 for (i = 0; labels[i].label != 0; ++i) 190 { 191 #if FAST_P 192 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; 193 #else 194 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; 195 #endif 196 } 197 198 #undef DEFINE_LABELS 199 #endif /* DEFINE_LABELS */ 200 201 #ifdef DEFINE_SWITCH 202 203 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn 204 off frills like tracing and profiling. */ 205 /* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something 206 that can cause it to be optimized out. Another way would be to emit 207 special handlers into the instruction "stream". */ 208 209 #if FAST_P 210 #undef CGEN_TRACE_RESULT 211 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) 212 #endif 213 214 #undef GET_ATTR 215 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) 216 217 { 218 219 #if WITH_SCACHE_PBB 220 221 /* Branch to next handler without going around main loop. */ 222 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case 223 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) 224 225 #else /* ! WITH_SCACHE_PBB */ 226 227 #define NEXT(vpc) BREAK (sem) 228 #ifdef __GNUC__ 229 #if FAST_P 230 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) 231 #else 232 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) 233 #endif 234 #else 235 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) 236 #endif 237 238 #endif /* ! WITH_SCACHE_PBB */ 239 240 { 241 242 CASE (sem, INSN_X_INVALID) : /* --invalid-- */ 243 { 244 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 245 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 246 #define FLD(f) abuf->fields.sfmt_empty.f 247 int UNUSED written = 0; 248 IADDR UNUSED pc = abuf->addr; 249 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 250 251 { 252 /* Update the recorded pc in the cpu state struct. 253 Only necessary for WITH_SCACHE case, but to avoid the 254 conditional compilation .... */ 255 SET_H_PC (pc); 256 /* Virtual insns have zero size. Overwrite vpc with address of next insn 257 using the default-insn-bitsize spec. When executing insns in parallel 258 we may want to queue the fault and continue execution. */ 259 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 260 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); 261 } 262 263 #undef FLD 264 } 265 NEXT (vpc); 266 267 CASE (sem, INSN_X_AFTER) : /* --after-- */ 268 { 269 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 270 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 271 #define FLD(f) abuf->fields.sfmt_empty.f 272 int UNUSED written = 0; 273 IADDR UNUSED pc = abuf->addr; 274 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 275 276 { 277 #if WITH_SCACHE_PBB_IQ2000BF 278 iq2000bf_pbb_after (current_cpu, sem_arg); 279 #endif 280 } 281 282 #undef FLD 283 } 284 NEXT (vpc); 285 286 CASE (sem, INSN_X_BEFORE) : /* --before-- */ 287 { 288 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 289 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 290 #define FLD(f) abuf->fields.sfmt_empty.f 291 int UNUSED written = 0; 292 IADDR UNUSED pc = abuf->addr; 293 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 294 295 { 296 #if WITH_SCACHE_PBB_IQ2000BF 297 iq2000bf_pbb_before (current_cpu, sem_arg); 298 #endif 299 } 300 301 #undef FLD 302 } 303 NEXT (vpc); 304 305 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ 306 { 307 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 308 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 309 #define FLD(f) abuf->fields.sfmt_empty.f 310 int UNUSED written = 0; 311 IADDR UNUSED pc = abuf->addr; 312 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 313 314 { 315 #if WITH_SCACHE_PBB_IQ2000BF 316 #ifdef DEFINE_SWITCH 317 vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, 318 pbb_br_type, pbb_br_npc); 319 BREAK (sem); 320 #else 321 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ 322 vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, 323 CPU_PBB_BR_TYPE (current_cpu), 324 CPU_PBB_BR_NPC (current_cpu)); 325 #endif 326 #endif 327 } 328 329 #undef FLD 330 } 331 NEXT (vpc); 332 333 CASE (sem, INSN_X_CHAIN) : /* --chain-- */ 334 { 335 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 336 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 337 #define FLD(f) abuf->fields.sfmt_empty.f 338 int UNUSED written = 0; 339 IADDR UNUSED pc = abuf->addr; 340 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 341 342 { 343 #if WITH_SCACHE_PBB_IQ2000BF 344 vpc = iq2000bf_pbb_chain (current_cpu, sem_arg); 345 #ifdef DEFINE_SWITCH 346 BREAK (sem); 347 #endif 348 #endif 349 } 350 351 #undef FLD 352 } 353 NEXT (vpc); 354 355 CASE (sem, INSN_X_BEGIN) : /* --begin-- */ 356 { 357 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 358 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 359 #define FLD(f) abuf->fields.sfmt_empty.f 360 int UNUSED written = 0; 361 IADDR UNUSED pc = abuf->addr; 362 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 363 364 { 365 #if WITH_SCACHE_PBB_IQ2000BF 366 #if defined DEFINE_SWITCH || defined FAST_P 367 /* In the switch case FAST_P is a constant, allowing several optimizations 368 in any called inline functions. */ 369 vpc = iq2000bf_pbb_begin (current_cpu, FAST_P); 370 #else 371 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ 372 vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); 373 #else 374 vpc = iq2000bf_pbb_begin (current_cpu, 0); 375 #endif 376 #endif 377 #endif 378 } 379 380 #undef FLD 381 } 382 NEXT (vpc); 383 384 CASE (sem, INSN_ADD) : /* add $rd,$rs,$rt */ 385 { 386 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 387 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 388 #define FLD(f) abuf->fields.sfmt_mrgb.f 389 int UNUSED written = 0; 390 IADDR UNUSED pc = abuf->addr; 391 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 392 393 { 394 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 395 SET_H_GR (FLD (f_rd), opval); 396 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 397 } 398 399 #undef FLD 400 } 401 NEXT (vpc); 402 403 CASE (sem, INSN_ADDI) : /* addi $rt,$rs,$lo16 */ 404 { 405 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 406 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 407 #define FLD(f) abuf->fields.sfmt_addi.f 408 int UNUSED written = 0; 409 IADDR UNUSED pc = abuf->addr; 410 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 411 412 { 413 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 414 SET_H_GR (FLD (f_rt), opval); 415 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 416 } 417 418 #undef FLD 419 } 420 NEXT (vpc); 421 422 CASE (sem, INSN_ADDIU) : /* addiu $rt,$rs,$lo16 */ 423 { 424 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 425 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 426 #define FLD(f) abuf->fields.sfmt_addi.f 427 int UNUSED written = 0; 428 IADDR UNUSED pc = abuf->addr; 429 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 430 431 { 432 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); 433 SET_H_GR (FLD (f_rt), opval); 434 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 435 } 436 437 #undef FLD 438 } 439 NEXT (vpc); 440 441 CASE (sem, INSN_ADDU) : /* addu $rd,$rs,$rt */ 442 { 443 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 444 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 445 #define FLD(f) abuf->fields.sfmt_mrgb.f 446 int UNUSED written = 0; 447 IADDR UNUSED pc = abuf->addr; 448 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 449 450 { 451 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 452 SET_H_GR (FLD (f_rd), opval); 453 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 454 } 455 456 #undef FLD 457 } 458 NEXT (vpc); 459 460 CASE (sem, INSN_ADO16) : /* ado16 $rd,$rs,$rt */ 461 { 462 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 463 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 464 #define FLD(f) abuf->fields.sfmt_mrgb.f 465 int UNUSED written = 0; 466 IADDR UNUSED pc = abuf->addr; 467 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 468 469 { 470 HI tmp_high; 471 HI tmp_low; 472 tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535)); 473 tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16)); 474 { 475 SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low); 476 SET_H_GR (FLD (f_rd), opval); 477 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 478 } 479 } 480 481 #undef FLD 482 } 483 NEXT (vpc); 484 485 CASE (sem, INSN_AND) : /* and $rd,$rs,$rt */ 486 { 487 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 488 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 489 #define FLD(f) abuf->fields.sfmt_mrgb.f 490 int UNUSED written = 0; 491 IADDR UNUSED pc = abuf->addr; 492 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 493 494 { 495 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 496 SET_H_GR (FLD (f_rd), opval); 497 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 498 } 499 500 #undef FLD 501 } 502 NEXT (vpc); 503 504 CASE (sem, INSN_ANDI) : /* andi $rt,$rs,$lo16 */ 505 { 506 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 507 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 508 #define FLD(f) abuf->fields.sfmt_addi.f 509 int UNUSED written = 0; 510 IADDR UNUSED pc = abuf->addr; 511 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 512 513 { 514 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); 515 SET_H_GR (FLD (f_rt), opval); 516 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 517 } 518 519 #undef FLD 520 } 521 NEXT (vpc); 522 523 CASE (sem, INSN_ANDOI) : /* andoi $rt,$rs,$lo16 */ 524 { 525 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 526 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 527 #define FLD(f) abuf->fields.sfmt_addi.f 528 int UNUSED written = 0; 529 IADDR UNUSED pc = abuf->addr; 530 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 531 532 { 533 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm))))); 534 SET_H_GR (FLD (f_rt), opval); 535 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 536 } 537 538 #undef FLD 539 } 540 NEXT (vpc); 541 542 CASE (sem, INSN_NOR) : /* nor $rd,$rs,$rt */ 543 { 544 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 545 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 546 #define FLD(f) abuf->fields.sfmt_mrgb.f 547 int UNUSED written = 0; 548 IADDR UNUSED pc = abuf->addr; 549 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 550 551 { 552 SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))); 553 SET_H_GR (FLD (f_rd), opval); 554 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 555 } 556 557 #undef FLD 558 } 559 NEXT (vpc); 560 561 CASE (sem, INSN_OR) : /* or $rd,$rs,$rt */ 562 { 563 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 564 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 565 #define FLD(f) abuf->fields.sfmt_mrgb.f 566 int UNUSED written = 0; 567 IADDR UNUSED pc = abuf->addr; 568 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 569 570 { 571 SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 572 SET_H_GR (FLD (f_rd), opval); 573 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 574 } 575 576 #undef FLD 577 } 578 NEXT (vpc); 579 580 CASE (sem, INSN_ORI) : /* ori $rt,$rs,$lo16 */ 581 { 582 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 583 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 584 #define FLD(f) abuf->fields.sfmt_addi.f 585 int UNUSED written = 0; 586 IADDR UNUSED pc = abuf->addr; 587 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 588 589 { 590 SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); 591 SET_H_GR (FLD (f_rt), opval); 592 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 593 } 594 595 #undef FLD 596 } 597 NEXT (vpc); 598 599 CASE (sem, INSN_RAM) : /* ram $rd,$rt,$shamt,$maskl,$maskr */ 600 { 601 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 602 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 603 #define FLD(f) abuf->fields.sfmt_ram.f 604 int UNUSED written = 0; 605 IADDR UNUSED pc = abuf->addr; 606 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 607 608 { 609 { 610 SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); 611 SET_H_GR (FLD (f_rd), opval); 612 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 613 } 614 { 615 SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl))); 616 SET_H_GR (FLD (f_rd), opval); 617 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 618 } 619 { 620 SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs))); 621 SET_H_GR (FLD (f_rd), opval); 622 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 623 } 624 } 625 626 #undef FLD 627 } 628 NEXT (vpc); 629 630 CASE (sem, INSN_SLL) : /* sll $rd,$rt,$shamt */ 631 { 632 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 633 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 634 #define FLD(f) abuf->fields.sfmt_ram.f 635 int UNUSED written = 0; 636 IADDR UNUSED pc = abuf->addr; 637 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 638 639 { 640 SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); 641 SET_H_GR (FLD (f_rd), opval); 642 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 643 } 644 645 #undef FLD 646 } 647 NEXT (vpc); 648 649 CASE (sem, INSN_SLLV) : /* sllv $rd,$rt,$rs */ 650 { 651 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 652 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 653 #define FLD(f) abuf->fields.sfmt_mrgb.f 654 int UNUSED written = 0; 655 IADDR UNUSED pc = abuf->addr; 656 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 657 658 { 659 SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); 660 SET_H_GR (FLD (f_rd), opval); 661 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 662 } 663 664 #undef FLD 665 } 666 NEXT (vpc); 667 668 CASE (sem, INSN_SLMV) : /* slmv $rd,$rt,$rs,$shamt */ 669 { 670 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 671 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 672 #define FLD(f) abuf->fields.sfmt_ram.f 673 int UNUSED written = 0; 674 IADDR UNUSED pc = abuf->addr; 675 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 676 677 { 678 SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); 679 SET_H_GR (FLD (f_rd), opval); 680 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 681 } 682 683 #undef FLD 684 } 685 NEXT (vpc); 686 687 CASE (sem, INSN_SLT) : /* slt $rd,$rs,$rt */ 688 { 689 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 690 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 691 #define FLD(f) abuf->fields.sfmt_mrgb.f 692 int UNUSED written = 0; 693 IADDR UNUSED pc = abuf->addr; 694 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 695 696 if (LTSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 697 { 698 SI opval = 1; 699 SET_H_GR (FLD (f_rd), opval); 700 written |= (1 << 2); 701 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 702 } 703 } else { 704 { 705 SI opval = 0; 706 SET_H_GR (FLD (f_rd), opval); 707 written |= (1 << 2); 708 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 709 } 710 } 711 712 abuf->written = written; 713 #undef FLD 714 } 715 NEXT (vpc); 716 717 CASE (sem, INSN_SLTI) : /* slti $rt,$rs,$imm */ 718 { 719 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 720 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 721 #define FLD(f) abuf->fields.sfmt_addi.f 722 int UNUSED written = 0; 723 IADDR UNUSED pc = abuf->addr; 724 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 725 726 if (LTSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { 727 { 728 SI opval = 1; 729 SET_H_GR (FLD (f_rt), opval); 730 written |= (1 << 2); 731 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 732 } 733 } else { 734 { 735 SI opval = 0; 736 SET_H_GR (FLD (f_rt), opval); 737 written |= (1 << 2); 738 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 739 } 740 } 741 742 abuf->written = written; 743 #undef FLD 744 } 745 NEXT (vpc); 746 747 CASE (sem, INSN_SLTIU) : /* sltiu $rt,$rs,$imm */ 748 { 749 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 750 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 751 #define FLD(f) abuf->fields.sfmt_addi.f 752 int UNUSED written = 0; 753 IADDR UNUSED pc = abuf->addr; 754 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 755 756 if (LTUSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { 757 { 758 SI opval = 1; 759 SET_H_GR (FLD (f_rt), opval); 760 written |= (1 << 2); 761 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 762 } 763 } else { 764 { 765 SI opval = 0; 766 SET_H_GR (FLD (f_rt), opval); 767 written |= (1 << 2); 768 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 769 } 770 } 771 772 abuf->written = written; 773 #undef FLD 774 } 775 NEXT (vpc); 776 777 CASE (sem, INSN_SLTU) : /* sltu $rd,$rs,$rt */ 778 { 779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 780 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 781 #define FLD(f) abuf->fields.sfmt_mrgb.f 782 int UNUSED written = 0; 783 IADDR UNUSED pc = abuf->addr; 784 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 785 786 if (LTUSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 787 { 788 SI opval = 1; 789 SET_H_GR (FLD (f_rd), opval); 790 written |= (1 << 2); 791 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 792 } 793 } else { 794 { 795 SI opval = 0; 796 SET_H_GR (FLD (f_rd), opval); 797 written |= (1 << 2); 798 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 799 } 800 } 801 802 abuf->written = written; 803 #undef FLD 804 } 805 NEXT (vpc); 806 807 CASE (sem, INSN_SRA) : /* sra $rd,$rt,$shamt */ 808 { 809 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 810 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 811 #define FLD(f) abuf->fields.sfmt_ram.f 812 int UNUSED written = 0; 813 IADDR UNUSED pc = abuf->addr; 814 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 815 816 { 817 SI opval = SRASI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); 818 SET_H_GR (FLD (f_rd), opval); 819 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 820 } 821 822 #undef FLD 823 } 824 NEXT (vpc); 825 826 CASE (sem, INSN_SRAV) : /* srav $rd,$rt,$rs */ 827 { 828 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 829 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 830 #define FLD(f) abuf->fields.sfmt_mrgb.f 831 int UNUSED written = 0; 832 IADDR UNUSED pc = abuf->addr; 833 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 834 835 { 836 SI opval = SRASI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); 837 SET_H_GR (FLD (f_rd), opval); 838 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 839 } 840 841 #undef FLD 842 } 843 NEXT (vpc); 844 845 CASE (sem, INSN_SRL) : /* srl $rd,$rt,$shamt */ 846 { 847 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 848 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 849 #define FLD(f) abuf->fields.sfmt_ram.f 850 int UNUSED written = 0; 851 IADDR UNUSED pc = abuf->addr; 852 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 853 854 { 855 SI opval = SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); 856 SET_H_GR (FLD (f_rd), opval); 857 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 858 } 859 860 #undef FLD 861 } 862 NEXT (vpc); 863 864 CASE (sem, INSN_SRLV) : /* srlv $rd,$rt,$rs */ 865 { 866 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 867 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 868 #define FLD(f) abuf->fields.sfmt_mrgb.f 869 int UNUSED written = 0; 870 IADDR UNUSED pc = abuf->addr; 871 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 872 873 { 874 SI opval = SRLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); 875 SET_H_GR (FLD (f_rd), opval); 876 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 877 } 878 879 #undef FLD 880 } 881 NEXT (vpc); 882 883 CASE (sem, INSN_SRMV) : /* srmv $rd,$rt,$rs,$shamt */ 884 { 885 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 886 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 887 #define FLD(f) abuf->fields.sfmt_ram.f 888 int UNUSED written = 0; 889 IADDR UNUSED pc = abuf->addr; 890 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 891 892 { 893 SI opval = ANDSI (SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SLLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); 894 SET_H_GR (FLD (f_rd), opval); 895 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 896 } 897 898 #undef FLD 899 } 900 NEXT (vpc); 901 902 CASE (sem, INSN_SUB) : /* sub $rd,$rs,$rt */ 903 { 904 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 905 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 906 #define FLD(f) abuf->fields.sfmt_mrgb.f 907 int UNUSED written = 0; 908 IADDR UNUSED pc = abuf->addr; 909 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 910 911 { 912 SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 913 SET_H_GR (FLD (f_rd), opval); 914 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 915 } 916 917 #undef FLD 918 } 919 NEXT (vpc); 920 921 CASE (sem, INSN_SUBU) : /* subu $rd,$rs,$rt */ 922 { 923 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 924 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 925 #define FLD(f) abuf->fields.sfmt_mrgb.f 926 int UNUSED written = 0; 927 IADDR UNUSED pc = abuf->addr; 928 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 929 930 { 931 SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 932 SET_H_GR (FLD (f_rd), opval); 933 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 934 } 935 936 #undef FLD 937 } 938 NEXT (vpc); 939 940 CASE (sem, INSN_XOR) : /* xor $rd,$rs,$rt */ 941 { 942 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 943 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 944 #define FLD(f) abuf->fields.sfmt_mrgb.f 945 int UNUSED written = 0; 946 IADDR UNUSED pc = abuf->addr; 947 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 948 949 { 950 SI opval = XORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); 951 SET_H_GR (FLD (f_rd), opval); 952 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 953 } 954 955 #undef FLD 956 } 957 NEXT (vpc); 958 959 CASE (sem, INSN_XORI) : /* xori $rt,$rs,$lo16 */ 960 { 961 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 962 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 963 #define FLD(f) abuf->fields.sfmt_addi.f 964 int UNUSED written = 0; 965 IADDR UNUSED pc = abuf->addr; 966 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 967 968 { 969 SI opval = XORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); 970 SET_H_GR (FLD (f_rt), opval); 971 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 972 } 973 974 #undef FLD 975 } 976 NEXT (vpc); 977 978 CASE (sem, INSN_BBI) : /* bbi $rs($bitnum),$offset */ 979 { 980 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 981 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 982 #define FLD(f) abuf->fields.sfmt_bbi.f 983 int UNUSED written = 0; 984 IADDR UNUSED pc = abuf->addr; 985 SEM_BRANCH_INIT 986 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 987 988 if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt)))) { 989 { 990 { 991 USI opval = FLD (i_offset); 992 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 993 written |= (1 << 3); 994 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 995 } 996 } 997 } 998 999 abuf->written = written; 1000 SEM_BRANCH_FINI (vpc); 1001 #undef FLD 1002 } 1003 NEXT (vpc); 1004 1005 CASE (sem, INSN_BBIN) : /* bbin $rs($bitnum),$offset */ 1006 { 1007 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1008 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1009 #define FLD(f) abuf->fields.sfmt_bbi.f 1010 int UNUSED written = 0; 1011 IADDR UNUSED pc = abuf->addr; 1012 SEM_BRANCH_INIT 1013 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1014 1015 if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt))))) { 1016 { 1017 { 1018 USI opval = FLD (i_offset); 1019 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1020 written |= (1 << 3); 1021 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1022 } 1023 } 1024 } 1025 1026 abuf->written = written; 1027 SEM_BRANCH_FINI (vpc); 1028 #undef FLD 1029 } 1030 NEXT (vpc); 1031 1032 CASE (sem, INSN_BBV) : /* bbv $rs,$rt,$offset */ 1033 { 1034 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1035 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1036 #define FLD(f) abuf->fields.sfmt_bbi.f 1037 int UNUSED written = 0; 1038 IADDR UNUSED pc = abuf->addr; 1039 SEM_BRANCH_INIT 1040 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1041 1042 if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31)))) { 1043 { 1044 { 1045 USI opval = FLD (i_offset); 1046 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1047 written |= (1 << 3); 1048 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1049 } 1050 } 1051 } 1052 1053 abuf->written = written; 1054 SEM_BRANCH_FINI (vpc); 1055 #undef FLD 1056 } 1057 NEXT (vpc); 1058 1059 CASE (sem, INSN_BBVN) : /* bbvn $rs,$rt,$offset */ 1060 { 1061 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1062 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1063 #define FLD(f) abuf->fields.sfmt_bbi.f 1064 int UNUSED written = 0; 1065 IADDR UNUSED pc = abuf->addr; 1066 SEM_BRANCH_INIT 1067 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1068 1069 if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31))))) { 1070 { 1071 { 1072 USI opval = FLD (i_offset); 1073 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1074 written |= (1 << 3); 1075 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1076 } 1077 } 1078 } 1079 1080 abuf->written = written; 1081 SEM_BRANCH_FINI (vpc); 1082 #undef FLD 1083 } 1084 NEXT (vpc); 1085 1086 CASE (sem, INSN_BEQ) : /* beq $rs,$rt,$offset */ 1087 { 1088 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1089 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1090 #define FLD(f) abuf->fields.sfmt_bbi.f 1091 int UNUSED written = 0; 1092 IADDR UNUSED pc = abuf->addr; 1093 SEM_BRANCH_INIT 1094 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1095 1096 if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 1097 { 1098 { 1099 USI opval = FLD (i_offset); 1100 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1101 written |= (1 << 3); 1102 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1103 } 1104 } 1105 } 1106 1107 abuf->written = written; 1108 SEM_BRANCH_FINI (vpc); 1109 #undef FLD 1110 } 1111 NEXT (vpc); 1112 1113 CASE (sem, INSN_BEQL) : /* beql $rs,$rt,$offset */ 1114 { 1115 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1116 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1117 #define FLD(f) abuf->fields.sfmt_bbi.f 1118 int UNUSED written = 0; 1119 IADDR UNUSED pc = abuf->addr; 1120 SEM_BRANCH_INIT 1121 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1122 1123 if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 1124 { 1125 { 1126 USI opval = FLD (i_offset); 1127 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1128 written |= (1 << 3); 1129 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1130 } 1131 } 1132 } else { 1133 if (1) 1134 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1135 } 1136 1137 abuf->written = written; 1138 SEM_BRANCH_FINI (vpc); 1139 #undef FLD 1140 } 1141 NEXT (vpc); 1142 1143 CASE (sem, INSN_BGEZ) : /* bgez $rs,$offset */ 1144 { 1145 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1146 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1147 #define FLD(f) abuf->fields.sfmt_bbi.f 1148 int UNUSED written = 0; 1149 IADDR UNUSED pc = abuf->addr; 1150 SEM_BRANCH_INIT 1151 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1152 1153 if (GESI (GET_H_GR (FLD (f_rs)), 0)) { 1154 { 1155 { 1156 USI opval = FLD (i_offset); 1157 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1158 written |= (1 << 2); 1159 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1160 } 1161 } 1162 } 1163 1164 abuf->written = written; 1165 SEM_BRANCH_FINI (vpc); 1166 #undef FLD 1167 } 1168 NEXT (vpc); 1169 1170 CASE (sem, INSN_BGEZAL) : /* bgezal $rs,$offset */ 1171 { 1172 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1173 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1174 #define FLD(f) abuf->fields.sfmt_bbi.f 1175 int UNUSED written = 0; 1176 IADDR UNUSED pc = abuf->addr; 1177 SEM_BRANCH_INIT 1178 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1179 1180 if (GESI (GET_H_GR (FLD (f_rs)), 0)) { 1181 { 1182 { 1183 SI opval = ADDSI (pc, 8); 1184 SET_H_GR (((UINT) 31), opval); 1185 written |= (1 << 3); 1186 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1187 } 1188 { 1189 { 1190 USI opval = FLD (i_offset); 1191 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1192 written |= (1 << 4); 1193 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1194 } 1195 } 1196 } 1197 } 1198 1199 abuf->written = written; 1200 SEM_BRANCH_FINI (vpc); 1201 #undef FLD 1202 } 1203 NEXT (vpc); 1204 1205 CASE (sem, INSN_BGEZALL) : /* bgezall $rs,$offset */ 1206 { 1207 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1208 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1209 #define FLD(f) abuf->fields.sfmt_bbi.f 1210 int UNUSED written = 0; 1211 IADDR UNUSED pc = abuf->addr; 1212 SEM_BRANCH_INIT 1213 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1214 1215 if (GESI (GET_H_GR (FLD (f_rs)), 0)) { 1216 { 1217 { 1218 SI opval = ADDSI (pc, 8); 1219 SET_H_GR (((UINT) 31), opval); 1220 written |= (1 << 3); 1221 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1222 } 1223 { 1224 { 1225 USI opval = FLD (i_offset); 1226 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1227 written |= (1 << 4); 1228 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1229 } 1230 } 1231 } 1232 } else { 1233 if (1) 1234 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1235 } 1236 1237 abuf->written = written; 1238 SEM_BRANCH_FINI (vpc); 1239 #undef FLD 1240 } 1241 NEXT (vpc); 1242 1243 CASE (sem, INSN_BGEZL) : /* bgezl $rs,$offset */ 1244 { 1245 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1246 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1247 #define FLD(f) abuf->fields.sfmt_bbi.f 1248 int UNUSED written = 0; 1249 IADDR UNUSED pc = abuf->addr; 1250 SEM_BRANCH_INIT 1251 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1252 1253 if (GESI (GET_H_GR (FLD (f_rs)), 0)) { 1254 { 1255 { 1256 USI opval = FLD (i_offset); 1257 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1258 written |= (1 << 2); 1259 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1260 } 1261 } 1262 } else { 1263 if (1) 1264 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1265 } 1266 1267 abuf->written = written; 1268 SEM_BRANCH_FINI (vpc); 1269 #undef FLD 1270 } 1271 NEXT (vpc); 1272 1273 CASE (sem, INSN_BLTZ) : /* bltz $rs,$offset */ 1274 { 1275 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1276 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1277 #define FLD(f) abuf->fields.sfmt_bbi.f 1278 int UNUSED written = 0; 1279 IADDR UNUSED pc = abuf->addr; 1280 SEM_BRANCH_INIT 1281 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1282 1283 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { 1284 { 1285 { 1286 USI opval = FLD (i_offset); 1287 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1288 written |= (1 << 2); 1289 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1290 } 1291 } 1292 } 1293 1294 abuf->written = written; 1295 SEM_BRANCH_FINI (vpc); 1296 #undef FLD 1297 } 1298 NEXT (vpc); 1299 1300 CASE (sem, INSN_BLTZL) : /* bltzl $rs,$offset */ 1301 { 1302 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1303 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1304 #define FLD(f) abuf->fields.sfmt_bbi.f 1305 int UNUSED written = 0; 1306 IADDR UNUSED pc = abuf->addr; 1307 SEM_BRANCH_INIT 1308 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1309 1310 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { 1311 { 1312 { 1313 USI opval = FLD (i_offset); 1314 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1315 written |= (1 << 2); 1316 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1317 } 1318 } 1319 } else { 1320 if (1) 1321 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1322 } 1323 1324 abuf->written = written; 1325 SEM_BRANCH_FINI (vpc); 1326 #undef FLD 1327 } 1328 NEXT (vpc); 1329 1330 CASE (sem, INSN_BLTZAL) : /* bltzal $rs,$offset */ 1331 { 1332 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1333 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1334 #define FLD(f) abuf->fields.sfmt_bbi.f 1335 int UNUSED written = 0; 1336 IADDR UNUSED pc = abuf->addr; 1337 SEM_BRANCH_INIT 1338 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1339 1340 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { 1341 { 1342 { 1343 SI opval = ADDSI (pc, 8); 1344 SET_H_GR (((UINT) 31), opval); 1345 written |= (1 << 3); 1346 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1347 } 1348 { 1349 { 1350 USI opval = FLD (i_offset); 1351 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1352 written |= (1 << 4); 1353 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1354 } 1355 } 1356 } 1357 } 1358 1359 abuf->written = written; 1360 SEM_BRANCH_FINI (vpc); 1361 #undef FLD 1362 } 1363 NEXT (vpc); 1364 1365 CASE (sem, INSN_BLTZALL) : /* bltzall $rs,$offset */ 1366 { 1367 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1368 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1369 #define FLD(f) abuf->fields.sfmt_bbi.f 1370 int UNUSED written = 0; 1371 IADDR UNUSED pc = abuf->addr; 1372 SEM_BRANCH_INIT 1373 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1374 1375 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { 1376 { 1377 { 1378 SI opval = ADDSI (pc, 8); 1379 SET_H_GR (((UINT) 31), opval); 1380 written |= (1 << 3); 1381 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1382 } 1383 { 1384 { 1385 USI opval = FLD (i_offset); 1386 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1387 written |= (1 << 4); 1388 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1389 } 1390 } 1391 } 1392 } else { 1393 if (1) 1394 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1395 } 1396 1397 abuf->written = written; 1398 SEM_BRANCH_FINI (vpc); 1399 #undef FLD 1400 } 1401 NEXT (vpc); 1402 1403 CASE (sem, INSN_BMB0) : /* bmb0 $rs,$rt,$offset */ 1404 { 1405 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1406 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1407 #define FLD(f) abuf->fields.sfmt_bbi.f 1408 int UNUSED written = 0; 1409 IADDR UNUSED pc = abuf->addr; 1410 SEM_BRANCH_INIT 1411 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1412 1413 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { 1414 { 1415 { 1416 USI opval = FLD (i_offset); 1417 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1418 written |= (1 << 3); 1419 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1420 } 1421 } 1422 } 1423 1424 abuf->written = written; 1425 SEM_BRANCH_FINI (vpc); 1426 #undef FLD 1427 } 1428 NEXT (vpc); 1429 1430 CASE (sem, INSN_BMB1) : /* bmb1 $rs,$rt,$offset */ 1431 { 1432 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1433 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1434 #define FLD(f) abuf->fields.sfmt_bbi.f 1435 int UNUSED written = 0; 1436 IADDR UNUSED pc = abuf->addr; 1437 SEM_BRANCH_INIT 1438 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1439 1440 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { 1441 { 1442 { 1443 USI opval = FLD (i_offset); 1444 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1445 written |= (1 << 3); 1446 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1447 } 1448 } 1449 } 1450 1451 abuf->written = written; 1452 SEM_BRANCH_FINI (vpc); 1453 #undef FLD 1454 } 1455 NEXT (vpc); 1456 1457 CASE (sem, INSN_BMB2) : /* bmb2 $rs,$rt,$offset */ 1458 { 1459 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1460 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1461 #define FLD(f) abuf->fields.sfmt_bbi.f 1462 int UNUSED written = 0; 1463 IADDR UNUSED pc = abuf->addr; 1464 SEM_BRANCH_INIT 1465 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1466 1467 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { 1468 { 1469 { 1470 USI opval = FLD (i_offset); 1471 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1472 written |= (1 << 3); 1473 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1474 } 1475 } 1476 } 1477 1478 abuf->written = written; 1479 SEM_BRANCH_FINI (vpc); 1480 #undef FLD 1481 } 1482 NEXT (vpc); 1483 1484 CASE (sem, INSN_BMB3) : /* bmb3 $rs,$rt,$offset */ 1485 { 1486 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1487 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1488 #define FLD(f) abuf->fields.sfmt_bbi.f 1489 int UNUSED written = 0; 1490 IADDR UNUSED pc = abuf->addr; 1491 SEM_BRANCH_INIT 1492 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1493 1494 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { 1495 { 1496 { 1497 USI opval = FLD (i_offset); 1498 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1499 written |= (1 << 3); 1500 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1501 } 1502 } 1503 } 1504 1505 abuf->written = written; 1506 SEM_BRANCH_FINI (vpc); 1507 #undef FLD 1508 } 1509 NEXT (vpc); 1510 1511 CASE (sem, INSN_BNE) : /* bne $rs,$rt,$offset */ 1512 { 1513 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1514 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1515 #define FLD(f) abuf->fields.sfmt_bbi.f 1516 int UNUSED written = 0; 1517 IADDR UNUSED pc = abuf->addr; 1518 SEM_BRANCH_INIT 1519 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1520 1521 if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 1522 { 1523 { 1524 USI opval = FLD (i_offset); 1525 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1526 written |= (1 << 3); 1527 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1528 } 1529 } 1530 } 1531 1532 abuf->written = written; 1533 SEM_BRANCH_FINI (vpc); 1534 #undef FLD 1535 } 1536 NEXT (vpc); 1537 1538 CASE (sem, INSN_BNEL) : /* bnel $rs,$rt,$offset */ 1539 { 1540 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1541 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1542 #define FLD(f) abuf->fields.sfmt_bbi.f 1543 int UNUSED written = 0; 1544 IADDR UNUSED pc = abuf->addr; 1545 SEM_BRANCH_INIT 1546 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1547 1548 if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { 1549 { 1550 { 1551 USI opval = FLD (i_offset); 1552 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1553 written |= (1 << 3); 1554 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1555 } 1556 } 1557 } else { 1558 if (1) 1559 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1560 } 1561 1562 abuf->written = written; 1563 SEM_BRANCH_FINI (vpc); 1564 #undef FLD 1565 } 1566 NEXT (vpc); 1567 1568 CASE (sem, INSN_JALR) : /* jalr $rd,$rs */ 1569 { 1570 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1571 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1572 #define FLD(f) abuf->fields.sfmt_mrgb.f 1573 int UNUSED written = 0; 1574 IADDR UNUSED pc = abuf->addr; 1575 SEM_BRANCH_INIT 1576 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1577 1578 { 1579 { 1580 { 1581 SI opval = ADDSI (pc, 8); 1582 SET_H_GR (FLD (f_rd), opval); 1583 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1584 } 1585 { 1586 USI opval = GET_H_GR (FLD (f_rs)); 1587 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1588 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1589 } 1590 } 1591 } 1592 1593 SEM_BRANCH_FINI (vpc); 1594 #undef FLD 1595 } 1596 NEXT (vpc); 1597 1598 CASE (sem, INSN_JR) : /* jr $rs */ 1599 { 1600 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1601 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1602 #define FLD(f) abuf->fields.sfmt_bbi.f 1603 int UNUSED written = 0; 1604 IADDR UNUSED pc = abuf->addr; 1605 SEM_BRANCH_INIT 1606 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1607 1608 { 1609 { 1610 USI opval = GET_H_GR (FLD (f_rs)); 1611 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1612 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1613 } 1614 } 1615 1616 SEM_BRANCH_FINI (vpc); 1617 #undef FLD 1618 } 1619 NEXT (vpc); 1620 1621 CASE (sem, INSN_LB) : /* lb $rt,$lo16($base) */ 1622 { 1623 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1624 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1625 #define FLD(f) abuf->fields.sfmt_addi.f 1626 int UNUSED written = 0; 1627 IADDR UNUSED pc = abuf->addr; 1628 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1629 1630 { 1631 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 1632 SET_H_GR (FLD (f_rt), opval); 1633 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1634 } 1635 1636 #undef FLD 1637 } 1638 NEXT (vpc); 1639 1640 CASE (sem, INSN_LBU) : /* lbu $rt,$lo16($base) */ 1641 { 1642 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1643 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1644 #define FLD(f) abuf->fields.sfmt_addi.f 1645 int UNUSED written = 0; 1646 IADDR UNUSED pc = abuf->addr; 1647 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1648 1649 { 1650 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 1651 SET_H_GR (FLD (f_rt), opval); 1652 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1653 } 1654 1655 #undef FLD 1656 } 1657 NEXT (vpc); 1658 1659 CASE (sem, INSN_LH) : /* lh $rt,$lo16($base) */ 1660 { 1661 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1662 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1663 #define FLD(f) abuf->fields.sfmt_addi.f 1664 int UNUSED written = 0; 1665 IADDR UNUSED pc = abuf->addr; 1666 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1667 1668 { 1669 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 1670 SET_H_GR (FLD (f_rt), opval); 1671 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1672 } 1673 1674 #undef FLD 1675 } 1676 NEXT (vpc); 1677 1678 CASE (sem, INSN_LHU) : /* lhu $rt,$lo16($base) */ 1679 { 1680 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1681 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1682 #define FLD(f) abuf->fields.sfmt_addi.f 1683 int UNUSED written = 0; 1684 IADDR UNUSED pc = abuf->addr; 1685 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1686 1687 { 1688 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); 1689 SET_H_GR (FLD (f_rt), opval); 1690 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1691 } 1692 1693 #undef FLD 1694 } 1695 NEXT (vpc); 1696 1697 CASE (sem, INSN_LUI) : /* lui $rt,$hi16 */ 1698 { 1699 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1700 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1701 #define FLD(f) abuf->fields.sfmt_addi.f 1702 int UNUSED written = 0; 1703 IADDR UNUSED pc = abuf->addr; 1704 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1705 1706 { 1707 SI opval = SLLSI (FLD (f_imm), 16); 1708 SET_H_GR (FLD (f_rt), opval); 1709 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1710 } 1711 1712 #undef FLD 1713 } 1714 NEXT (vpc); 1715 1716 CASE (sem, INSN_LW) : /* lw $rt,$lo16($base) */ 1717 { 1718 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1719 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1720 #define FLD(f) abuf->fields.sfmt_addi.f 1721 int UNUSED written = 0; 1722 IADDR UNUSED pc = abuf->addr; 1723 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1724 1725 { 1726 SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))); 1727 SET_H_GR (FLD (f_rt), opval); 1728 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1729 } 1730 1731 #undef FLD 1732 } 1733 NEXT (vpc); 1734 1735 CASE (sem, INSN_SB) : /* sb $rt,$lo16($base) */ 1736 { 1737 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1738 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1739 #define FLD(f) abuf->fields.sfmt_addi.f 1740 int UNUSED written = 0; 1741 IADDR UNUSED pc = abuf->addr; 1742 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1743 1744 { 1745 QI opval = ANDQI (GET_H_GR (FLD (f_rt)), 255); 1746 SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1747 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1748 } 1749 1750 #undef FLD 1751 } 1752 NEXT (vpc); 1753 1754 CASE (sem, INSN_SH) : /* sh $rt,$lo16($base) */ 1755 { 1756 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1757 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1758 #define FLD(f) abuf->fields.sfmt_addi.f 1759 int UNUSED written = 0; 1760 IADDR UNUSED pc = abuf->addr; 1761 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1762 1763 { 1764 HI opval = ANDHI (GET_H_GR (FLD (f_rt)), 65535); 1765 SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1766 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1767 } 1768 1769 #undef FLD 1770 } 1771 NEXT (vpc); 1772 1773 CASE (sem, INSN_SW) : /* sw $rt,$lo16($base) */ 1774 { 1775 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1776 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1777 #define FLD(f) abuf->fields.sfmt_addi.f 1778 int UNUSED written = 0; 1779 IADDR UNUSED pc = abuf->addr; 1780 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1781 1782 { 1783 SI opval = GET_H_GR (FLD (f_rt)); 1784 SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); 1785 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 1786 } 1787 1788 #undef FLD 1789 } 1790 NEXT (vpc); 1791 1792 CASE (sem, INSN_BREAK) : /* break */ 1793 { 1794 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1795 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1796 #define FLD(f) abuf->fields.sfmt_empty.f 1797 int UNUSED written = 0; 1798 IADDR UNUSED pc = abuf->addr; 1799 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1800 1801 do_break (current_cpu, pc); 1802 1803 #undef FLD 1804 } 1805 NEXT (vpc); 1806 1807 CASE (sem, INSN_SYSCALL) : /* syscall */ 1808 { 1809 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1810 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1811 #define FLD(f) abuf->fields.sfmt_empty.f 1812 int UNUSED written = 0; 1813 IADDR UNUSED pc = abuf->addr; 1814 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1815 1816 do_syscall (current_cpu, pc); 1817 1818 #undef FLD 1819 } 1820 NEXT (vpc); 1821 1822 CASE (sem, INSN_ANDOUI) : /* andoui $rt,$rs,$hi16 */ 1823 { 1824 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1825 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1826 #define FLD(f) abuf->fields.sfmt_addi.f 1827 int UNUSED written = 0; 1828 IADDR UNUSED pc = abuf->addr; 1829 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1830 1831 { 1832 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (SLLSI (FLD (f_imm), 16), 65535)); 1833 SET_H_GR (FLD (f_rt), opval); 1834 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1835 } 1836 1837 #undef FLD 1838 } 1839 NEXT (vpc); 1840 1841 CASE (sem, INSN_ORUI) : /* orui $rt,$rs,$hi16 */ 1842 { 1843 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1844 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1845 #define FLD(f) abuf->fields.sfmt_addi.f 1846 int UNUSED written = 0; 1847 IADDR UNUSED pc = abuf->addr; 1848 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1849 1850 { 1851 SI opval = ORSI (GET_H_GR (FLD (f_rs)), SLLSI (FLD (f_imm), 16)); 1852 SET_H_GR (FLD (f_rt), opval); 1853 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1854 } 1855 1856 #undef FLD 1857 } 1858 NEXT (vpc); 1859 1860 CASE (sem, INSN_BGTZ) : /* bgtz $rs,$offset */ 1861 { 1862 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1863 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1864 #define FLD(f) abuf->fields.sfmt_bbi.f 1865 int UNUSED written = 0; 1866 IADDR UNUSED pc = abuf->addr; 1867 SEM_BRANCH_INIT 1868 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1869 1870 if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { 1871 { 1872 { 1873 USI opval = FLD (i_offset); 1874 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1875 written |= (1 << 2); 1876 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1877 } 1878 } 1879 } 1880 1881 abuf->written = written; 1882 SEM_BRANCH_FINI (vpc); 1883 #undef FLD 1884 } 1885 NEXT (vpc); 1886 1887 CASE (sem, INSN_BGTZL) : /* bgtzl $rs,$offset */ 1888 { 1889 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1890 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1891 #define FLD(f) abuf->fields.sfmt_bbi.f 1892 int UNUSED written = 0; 1893 IADDR UNUSED pc = abuf->addr; 1894 SEM_BRANCH_INIT 1895 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1896 1897 if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { 1898 { 1899 { 1900 USI opval = FLD (i_offset); 1901 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1902 written |= (1 << 2); 1903 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1904 } 1905 } 1906 } else { 1907 if (1) 1908 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1909 } 1910 1911 abuf->written = written; 1912 SEM_BRANCH_FINI (vpc); 1913 #undef FLD 1914 } 1915 NEXT (vpc); 1916 1917 CASE (sem, INSN_BLEZ) : /* blez $rs,$offset */ 1918 { 1919 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1920 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1921 #define FLD(f) abuf->fields.sfmt_bbi.f 1922 int UNUSED written = 0; 1923 IADDR UNUSED pc = abuf->addr; 1924 SEM_BRANCH_INIT 1925 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1926 1927 if (LESI (GET_H_GR (FLD (f_rs)), 0)) { 1928 { 1929 { 1930 USI opval = FLD (i_offset); 1931 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1932 written |= (1 << 2); 1933 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1934 } 1935 } 1936 } 1937 1938 abuf->written = written; 1939 SEM_BRANCH_FINI (vpc); 1940 #undef FLD 1941 } 1942 NEXT (vpc); 1943 1944 CASE (sem, INSN_BLEZL) : /* blezl $rs,$offset */ 1945 { 1946 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1947 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1948 #define FLD(f) abuf->fields.sfmt_bbi.f 1949 int UNUSED written = 0; 1950 IADDR UNUSED pc = abuf->addr; 1951 SEM_BRANCH_INIT 1952 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1953 1954 if (LESI (GET_H_GR (FLD (f_rs)), 0)) { 1955 { 1956 { 1957 USI opval = FLD (i_offset); 1958 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 1959 written |= (1 << 2); 1960 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1961 } 1962 } 1963 } else { 1964 if (1) 1965 SEM_SKIP_INSN (current_cpu, sem_arg, vpc); 1966 } 1967 1968 abuf->written = written; 1969 SEM_BRANCH_FINI (vpc); 1970 #undef FLD 1971 } 1972 NEXT (vpc); 1973 1974 CASE (sem, INSN_MRGB) : /* mrgb $rd,$rs,$rt,$mask */ 1975 { 1976 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1977 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1978 #define FLD(f) abuf->fields.sfmt_mrgb.f 1979 int UNUSED written = 0; 1980 IADDR UNUSED pc = abuf->addr; 1981 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1982 1983 { 1984 SI tmp_temp; 1985 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 0)))) { 1986 tmp_temp = ANDSI (GET_H_GR (FLD (f_rs)), 255); 1987 } else { 1988 tmp_temp = ANDSI (GET_H_GR (FLD (f_rt)), 255); 1989 } 1990 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 1)))) { 1991 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 65280)); 1992 } else { 1993 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 65280)); 1994 } 1995 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 2)))) { 1996 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 16711680)); 1997 } else { 1998 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 16711680)); 1999 } 2000 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 3)))) { 2001 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000)); 2002 } else { 2003 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000)); 2004 } 2005 { 2006 SI opval = tmp_temp; 2007 SET_H_GR (FLD (f_rd), opval); 2008 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2009 } 2010 } 2011 2012 #undef FLD 2013 } 2014 NEXT (vpc); 2015 2016 CASE (sem, INSN_BCTXT) : /* bctxt $rs,$offset */ 2017 { 2018 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2019 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2020 #define FLD(f) abuf->fields.sfmt_empty.f 2021 int UNUSED written = 0; 2022 IADDR UNUSED pc = abuf->addr; 2023 SEM_BRANCH_INIT 2024 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2025 2026 ((void) 0); /*nop*/ 2027 2028 SEM_BRANCH_FINI (vpc); 2029 #undef FLD 2030 } 2031 NEXT (vpc); 2032 2033 CASE (sem, INSN_BC0F) : /* bc0f $offset */ 2034 { 2035 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2036 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2037 #define FLD(f) abuf->fields.sfmt_empty.f 2038 int UNUSED written = 0; 2039 IADDR UNUSED pc = abuf->addr; 2040 SEM_BRANCH_INIT 2041 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2042 2043 ((void) 0); /*nop*/ 2044 2045 SEM_BRANCH_FINI (vpc); 2046 #undef FLD 2047 } 2048 NEXT (vpc); 2049 2050 CASE (sem, INSN_BC0FL) : /* bc0fl $offset */ 2051 { 2052 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2053 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2054 #define FLD(f) abuf->fields.sfmt_empty.f 2055 int UNUSED written = 0; 2056 IADDR UNUSED pc = abuf->addr; 2057 SEM_BRANCH_INIT 2058 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2059 2060 ((void) 0); /*nop*/ 2061 2062 SEM_BRANCH_FINI (vpc); 2063 #undef FLD 2064 } 2065 NEXT (vpc); 2066 2067 CASE (sem, INSN_BC3F) : /* bc3f $offset */ 2068 { 2069 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2070 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2071 #define FLD(f) abuf->fields.sfmt_empty.f 2072 int UNUSED written = 0; 2073 IADDR UNUSED pc = abuf->addr; 2074 SEM_BRANCH_INIT 2075 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2076 2077 ((void) 0); /*nop*/ 2078 2079 SEM_BRANCH_FINI (vpc); 2080 #undef FLD 2081 } 2082 NEXT (vpc); 2083 2084 CASE (sem, INSN_BC3FL) : /* bc3fl $offset */ 2085 { 2086 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2087 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2088 #define FLD(f) abuf->fields.sfmt_empty.f 2089 int UNUSED written = 0; 2090 IADDR UNUSED pc = abuf->addr; 2091 SEM_BRANCH_INIT 2092 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2093 2094 ((void) 0); /*nop*/ 2095 2096 SEM_BRANCH_FINI (vpc); 2097 #undef FLD 2098 } 2099 NEXT (vpc); 2100 2101 CASE (sem, INSN_BC0T) : /* bc0t $offset */ 2102 { 2103 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2104 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2105 #define FLD(f) abuf->fields.sfmt_empty.f 2106 int UNUSED written = 0; 2107 IADDR UNUSED pc = abuf->addr; 2108 SEM_BRANCH_INIT 2109 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2110 2111 ((void) 0); /*nop*/ 2112 2113 SEM_BRANCH_FINI (vpc); 2114 #undef FLD 2115 } 2116 NEXT (vpc); 2117 2118 CASE (sem, INSN_BC0TL) : /* bc0tl $offset */ 2119 { 2120 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2121 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2122 #define FLD(f) abuf->fields.sfmt_empty.f 2123 int UNUSED written = 0; 2124 IADDR UNUSED pc = abuf->addr; 2125 SEM_BRANCH_INIT 2126 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2127 2128 ((void) 0); /*nop*/ 2129 2130 SEM_BRANCH_FINI (vpc); 2131 #undef FLD 2132 } 2133 NEXT (vpc); 2134 2135 CASE (sem, INSN_BC3T) : /* bc3t $offset */ 2136 { 2137 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2138 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2139 #define FLD(f) abuf->fields.sfmt_empty.f 2140 int UNUSED written = 0; 2141 IADDR UNUSED pc = abuf->addr; 2142 SEM_BRANCH_INIT 2143 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2144 2145 ((void) 0); /*nop*/ 2146 2147 SEM_BRANCH_FINI (vpc); 2148 #undef FLD 2149 } 2150 NEXT (vpc); 2151 2152 CASE (sem, INSN_BC3TL) : /* bc3tl $offset */ 2153 { 2154 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2155 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2156 #define FLD(f) abuf->fields.sfmt_empty.f 2157 int UNUSED written = 0; 2158 IADDR UNUSED pc = abuf->addr; 2159 SEM_BRANCH_INIT 2160 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2161 2162 ((void) 0); /*nop*/ 2163 2164 SEM_BRANCH_FINI (vpc); 2165 #undef FLD 2166 } 2167 NEXT (vpc); 2168 2169 CASE (sem, INSN_CFC0) : /* cfc0 $rt,$rd */ 2170 { 2171 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2172 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2173 #define FLD(f) abuf->fields.sfmt_empty.f 2174 int UNUSED written = 0; 2175 IADDR UNUSED pc = abuf->addr; 2176 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2177 2178 ((void) 0); /*nop*/ 2179 2180 #undef FLD 2181 } 2182 NEXT (vpc); 2183 2184 CASE (sem, INSN_CFC1) : /* cfc1 $rt,$rd */ 2185 { 2186 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2187 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2188 #define FLD(f) abuf->fields.sfmt_empty.f 2189 int UNUSED written = 0; 2190 IADDR UNUSED pc = abuf->addr; 2191 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2192 2193 ((void) 0); /*nop*/ 2194 2195 #undef FLD 2196 } 2197 NEXT (vpc); 2198 2199 CASE (sem, INSN_CFC2) : /* cfc2 $rt,$rd */ 2200 { 2201 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2202 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2203 #define FLD(f) abuf->fields.sfmt_empty.f 2204 int UNUSED written = 0; 2205 IADDR UNUSED pc = abuf->addr; 2206 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2207 2208 ((void) 0); /*nop*/ 2209 2210 #undef FLD 2211 } 2212 NEXT (vpc); 2213 2214 CASE (sem, INSN_CFC3) : /* cfc3 $rt,$rd */ 2215 { 2216 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2217 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2218 #define FLD(f) abuf->fields.sfmt_empty.f 2219 int UNUSED written = 0; 2220 IADDR UNUSED pc = abuf->addr; 2221 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2222 2223 ((void) 0); /*nop*/ 2224 2225 #undef FLD 2226 } 2227 NEXT (vpc); 2228 2229 CASE (sem, INSN_CHKHDR) : /* chkhdr $rd,$rt */ 2230 { 2231 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2232 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2233 #define FLD(f) abuf->fields.sfmt_empty.f 2234 int UNUSED written = 0; 2235 IADDR UNUSED pc = abuf->addr; 2236 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2237 2238 ((void) 0); /*nop*/ 2239 2240 #undef FLD 2241 } 2242 NEXT (vpc); 2243 2244 CASE (sem, INSN_CTC0) : /* ctc0 $rt,$rd */ 2245 { 2246 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2247 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2248 #define FLD(f) abuf->fields.sfmt_empty.f 2249 int UNUSED written = 0; 2250 IADDR UNUSED pc = abuf->addr; 2251 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2252 2253 ((void) 0); /*nop*/ 2254 2255 #undef FLD 2256 } 2257 NEXT (vpc); 2258 2259 CASE (sem, INSN_CTC1) : /* ctc1 $rt,$rd */ 2260 { 2261 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2262 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2263 #define FLD(f) abuf->fields.sfmt_empty.f 2264 int UNUSED written = 0; 2265 IADDR UNUSED pc = abuf->addr; 2266 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2267 2268 ((void) 0); /*nop*/ 2269 2270 #undef FLD 2271 } 2272 NEXT (vpc); 2273 2274 CASE (sem, INSN_CTC2) : /* ctc2 $rt,$rd */ 2275 { 2276 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2277 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2278 #define FLD(f) abuf->fields.sfmt_empty.f 2279 int UNUSED written = 0; 2280 IADDR UNUSED pc = abuf->addr; 2281 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2282 2283 ((void) 0); /*nop*/ 2284 2285 #undef FLD 2286 } 2287 NEXT (vpc); 2288 2289 CASE (sem, INSN_CTC3) : /* ctc3 $rt,$rd */ 2290 { 2291 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2292 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2293 #define FLD(f) abuf->fields.sfmt_empty.f 2294 int UNUSED written = 0; 2295 IADDR UNUSED pc = abuf->addr; 2296 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2297 2298 ((void) 0); /*nop*/ 2299 2300 #undef FLD 2301 } 2302 NEXT (vpc); 2303 2304 CASE (sem, INSN_JCR) : /* jcr $rs */ 2305 { 2306 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2307 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2308 #define FLD(f) abuf->fields.sfmt_empty.f 2309 int UNUSED written = 0; 2310 IADDR UNUSED pc = abuf->addr; 2311 SEM_BRANCH_INIT 2312 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2313 2314 ((void) 0); /*nop*/ 2315 2316 SEM_BRANCH_FINI (vpc); 2317 #undef FLD 2318 } 2319 NEXT (vpc); 2320 2321 CASE (sem, INSN_LUC32) : /* luc32 $rt,$rd */ 2322 { 2323 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2324 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2325 #define FLD(f) abuf->fields.sfmt_empty.f 2326 int UNUSED written = 0; 2327 IADDR UNUSED pc = abuf->addr; 2328 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2329 2330 ((void) 0); /*nop*/ 2331 2332 #undef FLD 2333 } 2334 NEXT (vpc); 2335 2336 CASE (sem, INSN_LUC32L) : /* luc32l $rt,$rd */ 2337 { 2338 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2339 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2340 #define FLD(f) abuf->fields.sfmt_empty.f 2341 int UNUSED written = 0; 2342 IADDR UNUSED pc = abuf->addr; 2343 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2344 2345 ((void) 0); /*nop*/ 2346 2347 #undef FLD 2348 } 2349 NEXT (vpc); 2350 2351 CASE (sem, INSN_LUC64) : /* luc64 $rt,$rd */ 2352 { 2353 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2354 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2355 #define FLD(f) abuf->fields.sfmt_empty.f 2356 int UNUSED written = 0; 2357 IADDR UNUSED pc = abuf->addr; 2358 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2359 2360 ((void) 0); /*nop*/ 2361 2362 #undef FLD 2363 } 2364 NEXT (vpc); 2365 2366 CASE (sem, INSN_LUC64L) : /* luc64l $rt,$rd */ 2367 { 2368 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2369 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2370 #define FLD(f) abuf->fields.sfmt_empty.f 2371 int UNUSED written = 0; 2372 IADDR UNUSED pc = abuf->addr; 2373 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2374 2375 ((void) 0); /*nop*/ 2376 2377 #undef FLD 2378 } 2379 NEXT (vpc); 2380 2381 CASE (sem, INSN_LUK) : /* luk $rt,$rd */ 2382 { 2383 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2384 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2385 #define FLD(f) abuf->fields.sfmt_empty.f 2386 int UNUSED written = 0; 2387 IADDR UNUSED pc = abuf->addr; 2388 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2389 2390 ((void) 0); /*nop*/ 2391 2392 #undef FLD 2393 } 2394 NEXT (vpc); 2395 2396 CASE (sem, INSN_LULCK) : /* lulck $rt */ 2397 { 2398 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2399 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2400 #define FLD(f) abuf->fields.sfmt_empty.f 2401 int UNUSED written = 0; 2402 IADDR UNUSED pc = abuf->addr; 2403 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2404 2405 ((void) 0); /*nop*/ 2406 2407 #undef FLD 2408 } 2409 NEXT (vpc); 2410 2411 CASE (sem, INSN_LUM32) : /* lum32 $rt,$rd */ 2412 { 2413 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2414 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2415 #define FLD(f) abuf->fields.sfmt_empty.f 2416 int UNUSED written = 0; 2417 IADDR UNUSED pc = abuf->addr; 2418 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2419 2420 ((void) 0); /*nop*/ 2421 2422 #undef FLD 2423 } 2424 NEXT (vpc); 2425 2426 CASE (sem, INSN_LUM32L) : /* lum32l $rt,$rd */ 2427 { 2428 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2429 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2430 #define FLD(f) abuf->fields.sfmt_empty.f 2431 int UNUSED written = 0; 2432 IADDR UNUSED pc = abuf->addr; 2433 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2434 2435 ((void) 0); /*nop*/ 2436 2437 #undef FLD 2438 } 2439 NEXT (vpc); 2440 2441 CASE (sem, INSN_LUM64) : /* lum64 $rt,$rd */ 2442 { 2443 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2444 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2445 #define FLD(f) abuf->fields.sfmt_empty.f 2446 int UNUSED written = 0; 2447 IADDR UNUSED pc = abuf->addr; 2448 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2449 2450 ((void) 0); /*nop*/ 2451 2452 #undef FLD 2453 } 2454 NEXT (vpc); 2455 2456 CASE (sem, INSN_LUM64L) : /* lum64l $rt,$rd */ 2457 { 2458 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2459 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2460 #define FLD(f) abuf->fields.sfmt_empty.f 2461 int UNUSED written = 0; 2462 IADDR UNUSED pc = abuf->addr; 2463 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2464 2465 ((void) 0); /*nop*/ 2466 2467 #undef FLD 2468 } 2469 NEXT (vpc); 2470 2471 CASE (sem, INSN_LUR) : /* lur $rt,$rd */ 2472 { 2473 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2474 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2475 #define FLD(f) abuf->fields.sfmt_empty.f 2476 int UNUSED written = 0; 2477 IADDR UNUSED pc = abuf->addr; 2478 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2479 2480 ((void) 0); /*nop*/ 2481 2482 #undef FLD 2483 } 2484 NEXT (vpc); 2485 2486 CASE (sem, INSN_LURL) : /* lurl $rt,$rd */ 2487 { 2488 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2489 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2490 #define FLD(f) abuf->fields.sfmt_empty.f 2491 int UNUSED written = 0; 2492 IADDR UNUSED pc = abuf->addr; 2493 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2494 2495 ((void) 0); /*nop*/ 2496 2497 #undef FLD 2498 } 2499 NEXT (vpc); 2500 2501 CASE (sem, INSN_LUULCK) : /* luulck $rt */ 2502 { 2503 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2504 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2505 #define FLD(f) abuf->fields.sfmt_empty.f 2506 int UNUSED written = 0; 2507 IADDR UNUSED pc = abuf->addr; 2508 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2509 2510 ((void) 0); /*nop*/ 2511 2512 #undef FLD 2513 } 2514 NEXT (vpc); 2515 2516 CASE (sem, INSN_MFC0) : /* mfc0 $rt,$rd */ 2517 { 2518 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2519 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2520 #define FLD(f) abuf->fields.sfmt_empty.f 2521 int UNUSED written = 0; 2522 IADDR UNUSED pc = abuf->addr; 2523 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2524 2525 ((void) 0); /*nop*/ 2526 2527 #undef FLD 2528 } 2529 NEXT (vpc); 2530 2531 CASE (sem, INSN_MFC1) : /* mfc1 $rt,$rd */ 2532 { 2533 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2534 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2535 #define FLD(f) abuf->fields.sfmt_empty.f 2536 int UNUSED written = 0; 2537 IADDR UNUSED pc = abuf->addr; 2538 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2539 2540 ((void) 0); /*nop*/ 2541 2542 #undef FLD 2543 } 2544 NEXT (vpc); 2545 2546 CASE (sem, INSN_MFC2) : /* mfc2 $rt,$rd */ 2547 { 2548 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2549 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2550 #define FLD(f) abuf->fields.sfmt_empty.f 2551 int UNUSED written = 0; 2552 IADDR UNUSED pc = abuf->addr; 2553 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2554 2555 ((void) 0); /*nop*/ 2556 2557 #undef FLD 2558 } 2559 NEXT (vpc); 2560 2561 CASE (sem, INSN_MFC3) : /* mfc3 $rt,$rd */ 2562 { 2563 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2564 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2565 #define FLD(f) abuf->fields.sfmt_empty.f 2566 int UNUSED written = 0; 2567 IADDR UNUSED pc = abuf->addr; 2568 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2569 2570 ((void) 0); /*nop*/ 2571 2572 #undef FLD 2573 } 2574 NEXT (vpc); 2575 2576 CASE (sem, INSN_MTC0) : /* mtc0 $rt,$rd */ 2577 { 2578 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2579 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2580 #define FLD(f) abuf->fields.sfmt_empty.f 2581 int UNUSED written = 0; 2582 IADDR UNUSED pc = abuf->addr; 2583 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2584 2585 ((void) 0); /*nop*/ 2586 2587 #undef FLD 2588 } 2589 NEXT (vpc); 2590 2591 CASE (sem, INSN_MTC1) : /* mtc1 $rt,$rd */ 2592 { 2593 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2594 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2595 #define FLD(f) abuf->fields.sfmt_empty.f 2596 int UNUSED written = 0; 2597 IADDR UNUSED pc = abuf->addr; 2598 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2599 2600 ((void) 0); /*nop*/ 2601 2602 #undef FLD 2603 } 2604 NEXT (vpc); 2605 2606 CASE (sem, INSN_MTC2) : /* mtc2 $rt,$rd */ 2607 { 2608 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2609 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2610 #define FLD(f) abuf->fields.sfmt_empty.f 2611 int UNUSED written = 0; 2612 IADDR UNUSED pc = abuf->addr; 2613 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2614 2615 ((void) 0); /*nop*/ 2616 2617 #undef FLD 2618 } 2619 NEXT (vpc); 2620 2621 CASE (sem, INSN_MTC3) : /* mtc3 $rt,$rd */ 2622 { 2623 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2624 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2625 #define FLD(f) abuf->fields.sfmt_empty.f 2626 int UNUSED written = 0; 2627 IADDR UNUSED pc = abuf->addr; 2628 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2629 2630 ((void) 0); /*nop*/ 2631 2632 #undef FLD 2633 } 2634 NEXT (vpc); 2635 2636 CASE (sem, INSN_PKRL) : /* pkrl $rd,$rt */ 2637 { 2638 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2639 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2640 #define FLD(f) abuf->fields.sfmt_empty.f 2641 int UNUSED written = 0; 2642 IADDR UNUSED pc = abuf->addr; 2643 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2644 2645 ((void) 0); /*nop*/ 2646 2647 #undef FLD 2648 } 2649 NEXT (vpc); 2650 2651 CASE (sem, INSN_PKRLR1) : /* pkrlr1 $rt,$_index,$count */ 2652 { 2653 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2654 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2655 #define FLD(f) abuf->fields.sfmt_empty.f 2656 int UNUSED written = 0; 2657 IADDR UNUSED pc = abuf->addr; 2658 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2659 2660 ((void) 0); /*nop*/ 2661 2662 #undef FLD 2663 } 2664 NEXT (vpc); 2665 2666 CASE (sem, INSN_PKRLR30) : /* pkrlr30 $rt,$_index,$count */ 2667 { 2668 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2669 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2670 #define FLD(f) abuf->fields.sfmt_empty.f 2671 int UNUSED written = 0; 2672 IADDR UNUSED pc = abuf->addr; 2673 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2674 2675 ((void) 0); /*nop*/ 2676 2677 #undef FLD 2678 } 2679 NEXT (vpc); 2680 2681 CASE (sem, INSN_RB) : /* rb $rd,$rt */ 2682 { 2683 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2684 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2685 #define FLD(f) abuf->fields.sfmt_empty.f 2686 int UNUSED written = 0; 2687 IADDR UNUSED pc = abuf->addr; 2688 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2689 2690 ((void) 0); /*nop*/ 2691 2692 #undef FLD 2693 } 2694 NEXT (vpc); 2695 2696 CASE (sem, INSN_RBR1) : /* rbr1 $rt,$_index,$count */ 2697 { 2698 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2699 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2700 #define FLD(f) abuf->fields.sfmt_empty.f 2701 int UNUSED written = 0; 2702 IADDR UNUSED pc = abuf->addr; 2703 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2704 2705 ((void) 0); /*nop*/ 2706 2707 #undef FLD 2708 } 2709 NEXT (vpc); 2710 2711 CASE (sem, INSN_RBR30) : /* rbr30 $rt,$_index,$count */ 2712 { 2713 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2714 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2715 #define FLD(f) abuf->fields.sfmt_empty.f 2716 int UNUSED written = 0; 2717 IADDR UNUSED pc = abuf->addr; 2718 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2719 2720 ((void) 0); /*nop*/ 2721 2722 #undef FLD 2723 } 2724 NEXT (vpc); 2725 2726 CASE (sem, INSN_RFE) : /* rfe */ 2727 { 2728 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2729 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2730 #define FLD(f) abuf->fields.sfmt_empty.f 2731 int UNUSED written = 0; 2732 IADDR UNUSED pc = abuf->addr; 2733 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2734 2735 ((void) 0); /*nop*/ 2736 2737 #undef FLD 2738 } 2739 NEXT (vpc); 2740 2741 CASE (sem, INSN_RX) : /* rx $rd,$rt */ 2742 { 2743 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2744 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2745 #define FLD(f) abuf->fields.sfmt_empty.f 2746 int UNUSED written = 0; 2747 IADDR UNUSED pc = abuf->addr; 2748 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2749 2750 ((void) 0); /*nop*/ 2751 2752 #undef FLD 2753 } 2754 NEXT (vpc); 2755 2756 CASE (sem, INSN_RXR1) : /* rxr1 $rt,$_index,$count */ 2757 { 2758 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2759 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2760 #define FLD(f) abuf->fields.sfmt_empty.f 2761 int UNUSED written = 0; 2762 IADDR UNUSED pc = abuf->addr; 2763 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2764 2765 ((void) 0); /*nop*/ 2766 2767 #undef FLD 2768 } 2769 NEXT (vpc); 2770 2771 CASE (sem, INSN_RXR30) : /* rxr30 $rt,$_index,$count */ 2772 { 2773 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2774 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2775 #define FLD(f) abuf->fields.sfmt_empty.f 2776 int UNUSED written = 0; 2777 IADDR UNUSED pc = abuf->addr; 2778 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2779 2780 ((void) 0); /*nop*/ 2781 2782 #undef FLD 2783 } 2784 NEXT (vpc); 2785 2786 CASE (sem, INSN_SLEEP) : /* sleep */ 2787 { 2788 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2789 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2790 #define FLD(f) abuf->fields.sfmt_empty.f 2791 int UNUSED written = 0; 2792 IADDR UNUSED pc = abuf->addr; 2793 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2794 2795 ((void) 0); /*nop*/ 2796 2797 #undef FLD 2798 } 2799 NEXT (vpc); 2800 2801 CASE (sem, INSN_SRRD) : /* srrd $rt */ 2802 { 2803 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2804 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2805 #define FLD(f) abuf->fields.sfmt_empty.f 2806 int UNUSED written = 0; 2807 IADDR UNUSED pc = abuf->addr; 2808 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2809 2810 ((void) 0); /*nop*/ 2811 2812 #undef FLD 2813 } 2814 NEXT (vpc); 2815 2816 CASE (sem, INSN_SRRDL) : /* srrdl $rt */ 2817 { 2818 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2819 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2820 #define FLD(f) abuf->fields.sfmt_empty.f 2821 int UNUSED written = 0; 2822 IADDR UNUSED pc = abuf->addr; 2823 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2824 2825 ((void) 0); /*nop*/ 2826 2827 #undef FLD 2828 } 2829 NEXT (vpc); 2830 2831 CASE (sem, INSN_SRULCK) : /* srulck $rt */ 2832 { 2833 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2834 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2835 #define FLD(f) abuf->fields.sfmt_empty.f 2836 int UNUSED written = 0; 2837 IADDR UNUSED pc = abuf->addr; 2838 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2839 2840 ((void) 0); /*nop*/ 2841 2842 #undef FLD 2843 } 2844 NEXT (vpc); 2845 2846 CASE (sem, INSN_SRWR) : /* srwr $rt,$rd */ 2847 { 2848 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2849 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2850 #define FLD(f) abuf->fields.sfmt_empty.f 2851 int UNUSED written = 0; 2852 IADDR UNUSED pc = abuf->addr; 2853 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2854 2855 ((void) 0); /*nop*/ 2856 2857 #undef FLD 2858 } 2859 NEXT (vpc); 2860 2861 CASE (sem, INSN_SRWRU) : /* srwru $rt,$rd */ 2862 { 2863 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2864 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2865 #define FLD(f) abuf->fields.sfmt_empty.f 2866 int UNUSED written = 0; 2867 IADDR UNUSED pc = abuf->addr; 2868 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2869 2870 ((void) 0); /*nop*/ 2871 2872 #undef FLD 2873 } 2874 NEXT (vpc); 2875 2876 CASE (sem, INSN_TRAPQFL) : /* trapqfl */ 2877 { 2878 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2879 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2880 #define FLD(f) abuf->fields.sfmt_empty.f 2881 int UNUSED written = 0; 2882 IADDR UNUSED pc = abuf->addr; 2883 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2884 2885 ((void) 0); /*nop*/ 2886 2887 #undef FLD 2888 } 2889 NEXT (vpc); 2890 2891 CASE (sem, INSN_TRAPQNE) : /* trapqne */ 2892 { 2893 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2894 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2895 #define FLD(f) abuf->fields.sfmt_empty.f 2896 int UNUSED written = 0; 2897 IADDR UNUSED pc = abuf->addr; 2898 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2899 2900 ((void) 0); /*nop*/ 2901 2902 #undef FLD 2903 } 2904 NEXT (vpc); 2905 2906 CASE (sem, INSN_TRAPREL) : /* traprel $rt */ 2907 { 2908 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2909 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2910 #define FLD(f) abuf->fields.sfmt_empty.f 2911 int UNUSED written = 0; 2912 IADDR UNUSED pc = abuf->addr; 2913 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2914 2915 ((void) 0); /*nop*/ 2916 2917 #undef FLD 2918 } 2919 NEXT (vpc); 2920 2921 CASE (sem, INSN_WB) : /* wb $rd,$rt */ 2922 { 2923 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2924 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2925 #define FLD(f) abuf->fields.sfmt_empty.f 2926 int UNUSED written = 0; 2927 IADDR UNUSED pc = abuf->addr; 2928 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2929 2930 ((void) 0); /*nop*/ 2931 2932 #undef FLD 2933 } 2934 NEXT (vpc); 2935 2936 CASE (sem, INSN_WBU) : /* wbu $rd,$rt */ 2937 { 2938 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2939 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2940 #define FLD(f) abuf->fields.sfmt_empty.f 2941 int UNUSED written = 0; 2942 IADDR UNUSED pc = abuf->addr; 2943 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2944 2945 ((void) 0); /*nop*/ 2946 2947 #undef FLD 2948 } 2949 NEXT (vpc); 2950 2951 CASE (sem, INSN_WBR1) : /* wbr1 $rt,$_index,$count */ 2952 { 2953 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2954 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2955 #define FLD(f) abuf->fields.sfmt_empty.f 2956 int UNUSED written = 0; 2957 IADDR UNUSED pc = abuf->addr; 2958 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2959 2960 ((void) 0); /*nop*/ 2961 2962 #undef FLD 2963 } 2964 NEXT (vpc); 2965 2966 CASE (sem, INSN_WBR1U) : /* wbr1u $rt,$_index,$count */ 2967 { 2968 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2969 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2970 #define FLD(f) abuf->fields.sfmt_empty.f 2971 int UNUSED written = 0; 2972 IADDR UNUSED pc = abuf->addr; 2973 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2974 2975 ((void) 0); /*nop*/ 2976 2977 #undef FLD 2978 } 2979 NEXT (vpc); 2980 2981 CASE (sem, INSN_WBR30) : /* wbr30 $rt,$_index,$count */ 2982 { 2983 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2984 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2985 #define FLD(f) abuf->fields.sfmt_empty.f 2986 int UNUSED written = 0; 2987 IADDR UNUSED pc = abuf->addr; 2988 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2989 2990 ((void) 0); /*nop*/ 2991 2992 #undef FLD 2993 } 2994 NEXT (vpc); 2995 2996 CASE (sem, INSN_WBR30U) : /* wbr30u $rt,$_index,$count */ 2997 { 2998 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2999 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3000 #define FLD(f) abuf->fields.sfmt_empty.f 3001 int UNUSED written = 0; 3002 IADDR UNUSED pc = abuf->addr; 3003 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3004 3005 ((void) 0); /*nop*/ 3006 3007 #undef FLD 3008 } 3009 NEXT (vpc); 3010 3011 CASE (sem, INSN_WX) : /* wx $rd,$rt */ 3012 { 3013 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3014 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3015 #define FLD(f) abuf->fields.sfmt_empty.f 3016 int UNUSED written = 0; 3017 IADDR UNUSED pc = abuf->addr; 3018 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3019 3020 ((void) 0); /*nop*/ 3021 3022 #undef FLD 3023 } 3024 NEXT (vpc); 3025 3026 CASE (sem, INSN_WXU) : /* wxu $rd,$rt */ 3027 { 3028 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3029 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3030 #define FLD(f) abuf->fields.sfmt_empty.f 3031 int UNUSED written = 0; 3032 IADDR UNUSED pc = abuf->addr; 3033 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3034 3035 ((void) 0); /*nop*/ 3036 3037 #undef FLD 3038 } 3039 NEXT (vpc); 3040 3041 CASE (sem, INSN_WXR1) : /* wxr1 $rt,$_index,$count */ 3042 { 3043 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3044 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3045 #define FLD(f) abuf->fields.sfmt_empty.f 3046 int UNUSED written = 0; 3047 IADDR UNUSED pc = abuf->addr; 3048 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3049 3050 ((void) 0); /*nop*/ 3051 3052 #undef FLD 3053 } 3054 NEXT (vpc); 3055 3056 CASE (sem, INSN_WXR1U) : /* wxr1u $rt,$_index,$count */ 3057 { 3058 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3059 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3060 #define FLD(f) abuf->fields.sfmt_empty.f 3061 int UNUSED written = 0; 3062 IADDR UNUSED pc = abuf->addr; 3063 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3064 3065 ((void) 0); /*nop*/ 3066 3067 #undef FLD 3068 } 3069 NEXT (vpc); 3070 3071 CASE (sem, INSN_WXR30) : /* wxr30 $rt,$_index,$count */ 3072 { 3073 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3074 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3075 #define FLD(f) abuf->fields.sfmt_empty.f 3076 int UNUSED written = 0; 3077 IADDR UNUSED pc = abuf->addr; 3078 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3079 3080 ((void) 0); /*nop*/ 3081 3082 #undef FLD 3083 } 3084 NEXT (vpc); 3085 3086 CASE (sem, INSN_WXR30U) : /* wxr30u $rt,$_index,$count */ 3087 { 3088 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3089 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3090 #define FLD(f) abuf->fields.sfmt_empty.f 3091 int UNUSED written = 0; 3092 IADDR UNUSED pc = abuf->addr; 3093 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3094 3095 ((void) 0); /*nop*/ 3096 3097 #undef FLD 3098 } 3099 NEXT (vpc); 3100 3101 CASE (sem, INSN_LDW) : /* ldw $rt,$lo16($base) */ 3102 { 3103 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3104 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3105 #define FLD(f) abuf->fields.sfmt_addi.f 3106 int UNUSED written = 0; 3107 IADDR UNUSED pc = abuf->addr; 3108 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3109 3110 { 3111 SI tmp_addr; 3112 tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); 3113 { 3114 SI opval = GETMEMSI (current_cpu, pc, tmp_addr); 3115 SET_H_GR (ADDSI (FLD (f_rt), 1), opval); 3116 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3117 } 3118 { 3119 SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4)); 3120 SET_H_GR (FLD (f_rt), opval); 3121 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3122 } 3123 } 3124 3125 #undef FLD 3126 } 3127 NEXT (vpc); 3128 3129 CASE (sem, INSN_SDW) : /* sdw $rt,$lo16($base) */ 3130 { 3131 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3132 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3133 #define FLD(f) abuf->fields.sfmt_addi.f 3134 int UNUSED written = 0; 3135 IADDR UNUSED pc = abuf->addr; 3136 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3137 3138 { 3139 SI tmp_addr; 3140 tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); 3141 { 3142 SI opval = GET_H_GR (FLD (f_rt)); 3143 SETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4), opval); 3144 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 3145 } 3146 { 3147 SI opval = GET_H_GR (ADDSI (FLD (f_rt), 1)); 3148 SETMEMSI (current_cpu, pc, tmp_addr, opval); 3149 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 3150 } 3151 } 3152 3153 #undef FLD 3154 } 3155 NEXT (vpc); 3156 3157 CASE (sem, INSN_J) : /* j $jmptarg */ 3158 { 3159 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3160 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3161 #define FLD(f) abuf->fields.sfmt_j.f 3162 int UNUSED written = 0; 3163 IADDR UNUSED pc = abuf->addr; 3164 SEM_BRANCH_INIT 3165 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3166 3167 { 3168 { 3169 USI opval = FLD (i_jmptarg); 3170 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 3171 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 3172 } 3173 } 3174 3175 SEM_BRANCH_FINI (vpc); 3176 #undef FLD 3177 } 3178 NEXT (vpc); 3179 3180 CASE (sem, INSN_JAL) : /* jal $jmptarg */ 3181 { 3182 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3183 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3184 #define FLD(f) abuf->fields.sfmt_j.f 3185 int UNUSED written = 0; 3186 IADDR UNUSED pc = abuf->addr; 3187 SEM_BRANCH_INIT 3188 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3189 3190 { 3191 { 3192 { 3193 SI opval = ADDSI (pc, 8); 3194 SET_H_GR (((UINT) 31), opval); 3195 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3196 } 3197 { 3198 USI opval = FLD (i_jmptarg); 3199 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 3200 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 3201 } 3202 } 3203 } 3204 3205 SEM_BRANCH_FINI (vpc); 3206 #undef FLD 3207 } 3208 NEXT (vpc); 3209 3210 CASE (sem, INSN_BMB) : /* bmb $rs,$rt,$offset */ 3211 { 3212 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3213 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3214 #define FLD(f) abuf->fields.sfmt_bbi.f 3215 int UNUSED written = 0; 3216 IADDR UNUSED pc = abuf->addr; 3217 SEM_BRANCH_INIT 3218 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 3219 3220 { 3221 BI tmp_branch_; 3222 tmp_branch_ = 0; 3223 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { 3224 tmp_branch_ = 1; 3225 } 3226 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { 3227 tmp_branch_ = 1; 3228 } 3229 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { 3230 tmp_branch_ = 1; 3231 } 3232 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { 3233 tmp_branch_ = 1; 3234 } 3235 if (tmp_branch_) { 3236 { 3237 { 3238 USI opval = FLD (i_offset); 3239 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 3240 written |= (1 << 3); 3241 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 3242 } 3243 } 3244 } 3245 } 3246 3247 abuf->written = written; 3248 SEM_BRANCH_FINI (vpc); 3249 #undef FLD 3250 } 3251 NEXT (vpc); 3252 3253 3254 } 3255 ENDSWITCH (sem) /* End of semantic switch. */ 3256 3257 /* At this point `vpc' contains the next insn to execute. */ 3258 } 3259 3260 #undef DEFINE_SWITCH 3261 #endif /* DEFINE_SWITCH */ 3262
Indexes created Fri Apr 24 00:22:58 UTC 2026