modelx.c revision 1.1
1 /* Simulator model support for m32rxf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2014 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, see <http://www.gnu.org/licenses/>. 21 22 */ 23 24 #define WANT_CPU m32rxf 25 #define WANT_CPU_M32RXF 26 27 #include "sim-main.h" 28 29 /* The profiling data is recorded here, but is accessed via the profiling 30 mechanism. After all, this is information for profiling. */ 31 32 #if WITH_PROFILE_MODEL_P 33 34 /* Model handlers for each insn. */ 35 36 static int 37 model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg) 38 { 39 #define FLD(f) abuf->fields.sfmt_add.f 40 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 41 const IDESC * UNUSED idesc = abuf->idesc; 42 int cycles = 0; 43 { 44 int referenced = 0; 45 int UNUSED insn_referenced = abuf->written; 46 INT in_sr = -1; 47 INT in_dr = -1; 48 INT out_dr = -1; 49 in_sr = FLD (in_sr); 50 in_dr = FLD (in_dr); 51 out_dr = FLD (out_dr); 52 referenced |= 1 << 0; 53 referenced |= 1 << 1; 54 referenced |= 1 << 2; 55 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 56 } 57 return cycles; 58 #undef FLD 59 } 60 61 static int 62 model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg) 63 { 64 #define FLD(f) abuf->fields.sfmt_add3.f 65 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 66 const IDESC * UNUSED idesc = abuf->idesc; 67 int cycles = 0; 68 { 69 int referenced = 0; 70 int UNUSED insn_referenced = abuf->written; 71 INT in_sr = -1; 72 INT in_dr = -1; 73 INT out_dr = -1; 74 in_sr = FLD (in_sr); 75 out_dr = FLD (out_dr); 76 referenced |= 1 << 0; 77 referenced |= 1 << 2; 78 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 79 } 80 return cycles; 81 #undef FLD 82 } 83 84 static int 85 model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg) 86 { 87 #define FLD(f) abuf->fields.sfmt_add.f 88 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 89 const IDESC * UNUSED idesc = abuf->idesc; 90 int cycles = 0; 91 { 92 int referenced = 0; 93 int UNUSED insn_referenced = abuf->written; 94 INT in_sr = -1; 95 INT in_dr = -1; 96 INT out_dr = -1; 97 in_sr = FLD (in_sr); 98 in_dr = FLD (in_dr); 99 out_dr = FLD (out_dr); 100 referenced |= 1 << 0; 101 referenced |= 1 << 1; 102 referenced |= 1 << 2; 103 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 104 } 105 return cycles; 106 #undef FLD 107 } 108 109 static int 110 model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg) 111 { 112 #define FLD(f) abuf->fields.sfmt_and3.f 113 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 114 const IDESC * UNUSED idesc = abuf->idesc; 115 int cycles = 0; 116 { 117 int referenced = 0; 118 int UNUSED insn_referenced = abuf->written; 119 INT in_sr = -1; 120 INT in_dr = -1; 121 INT out_dr = -1; 122 in_sr = FLD (in_sr); 123 out_dr = FLD (out_dr); 124 referenced |= 1 << 0; 125 referenced |= 1 << 2; 126 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 127 } 128 return cycles; 129 #undef FLD 130 } 131 132 static int 133 model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg) 134 { 135 #define FLD(f) abuf->fields.sfmt_add.f 136 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 137 const IDESC * UNUSED idesc = abuf->idesc; 138 int cycles = 0; 139 { 140 int referenced = 0; 141 int UNUSED insn_referenced = abuf->written; 142 INT in_sr = -1; 143 INT in_dr = -1; 144 INT out_dr = -1; 145 in_sr = FLD (in_sr); 146 in_dr = FLD (in_dr); 147 out_dr = FLD (out_dr); 148 referenced |= 1 << 0; 149 referenced |= 1 << 1; 150 referenced |= 1 << 2; 151 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 152 } 153 return cycles; 154 #undef FLD 155 } 156 157 static int 158 model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg) 159 { 160 #define FLD(f) abuf->fields.sfmt_and3.f 161 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 162 const IDESC * UNUSED idesc = abuf->idesc; 163 int cycles = 0; 164 { 165 int referenced = 0; 166 int UNUSED insn_referenced = abuf->written; 167 INT in_sr = -1; 168 INT in_dr = -1; 169 INT out_dr = -1; 170 in_sr = FLD (in_sr); 171 out_dr = FLD (out_dr); 172 referenced |= 1 << 0; 173 referenced |= 1 << 2; 174 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 175 } 176 return cycles; 177 #undef FLD 178 } 179 180 static int 181 model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg) 182 { 183 #define FLD(f) abuf->fields.sfmt_add.f 184 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 185 const IDESC * UNUSED idesc = abuf->idesc; 186 int cycles = 0; 187 { 188 int referenced = 0; 189 int UNUSED insn_referenced = abuf->written; 190 INT in_sr = -1; 191 INT in_dr = -1; 192 INT out_dr = -1; 193 in_sr = FLD (in_sr); 194 in_dr = FLD (in_dr); 195 out_dr = FLD (out_dr); 196 referenced |= 1 << 0; 197 referenced |= 1 << 1; 198 referenced |= 1 << 2; 199 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 200 } 201 return cycles; 202 #undef FLD 203 } 204 205 static int 206 model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg) 207 { 208 #define FLD(f) abuf->fields.sfmt_and3.f 209 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 210 const IDESC * UNUSED idesc = abuf->idesc; 211 int cycles = 0; 212 { 213 int referenced = 0; 214 int UNUSED insn_referenced = abuf->written; 215 INT in_sr = -1; 216 INT in_dr = -1; 217 INT out_dr = -1; 218 in_sr = FLD (in_sr); 219 out_dr = FLD (out_dr); 220 referenced |= 1 << 0; 221 referenced |= 1 << 2; 222 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 223 } 224 return cycles; 225 #undef FLD 226 } 227 228 static int 229 model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg) 230 { 231 #define FLD(f) abuf->fields.sfmt_addi.f 232 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 233 const IDESC * UNUSED idesc = abuf->idesc; 234 int cycles = 0; 235 { 236 int referenced = 0; 237 int UNUSED insn_referenced = abuf->written; 238 INT in_sr = -1; 239 INT in_dr = -1; 240 INT out_dr = -1; 241 in_dr = FLD (in_dr); 242 out_dr = FLD (out_dr); 243 referenced |= 1 << 1; 244 referenced |= 1 << 2; 245 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 246 } 247 return cycles; 248 #undef FLD 249 } 250 251 static int 252 model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg) 253 { 254 #define FLD(f) abuf->fields.sfmt_add.f 255 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 256 const IDESC * UNUSED idesc = abuf->idesc; 257 int cycles = 0; 258 { 259 int referenced = 0; 260 int UNUSED insn_referenced = abuf->written; 261 INT in_sr = -1; 262 INT in_dr = -1; 263 INT out_dr = -1; 264 in_sr = FLD (in_sr); 265 in_dr = FLD (in_dr); 266 out_dr = FLD (out_dr); 267 referenced |= 1 << 0; 268 referenced |= 1 << 1; 269 referenced |= 1 << 2; 270 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 271 } 272 return cycles; 273 #undef FLD 274 } 275 276 static int 277 model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg) 278 { 279 #define FLD(f) abuf->fields.sfmt_add3.f 280 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 281 const IDESC * UNUSED idesc = abuf->idesc; 282 int cycles = 0; 283 { 284 int referenced = 0; 285 int UNUSED insn_referenced = abuf->written; 286 INT in_sr = -1; 287 INT in_dr = -1; 288 INT out_dr = -1; 289 in_sr = FLD (in_sr); 290 out_dr = FLD (out_dr); 291 referenced |= 1 << 0; 292 referenced |= 1 << 2; 293 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 294 } 295 return cycles; 296 #undef FLD 297 } 298 299 static int 300 model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg) 301 { 302 #define FLD(f) abuf->fields.sfmt_add.f 303 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 304 const IDESC * UNUSED idesc = abuf->idesc; 305 int cycles = 0; 306 { 307 int referenced = 0; 308 int UNUSED insn_referenced = abuf->written; 309 INT in_sr = -1; 310 INT in_dr = -1; 311 INT out_dr = -1; 312 in_sr = FLD (in_sr); 313 in_dr = FLD (in_dr); 314 out_dr = FLD (out_dr); 315 referenced |= 1 << 0; 316 referenced |= 1 << 1; 317 referenced |= 1 << 2; 318 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 319 } 320 return cycles; 321 #undef FLD 322 } 323 324 static int 325 model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg) 326 { 327 #define FLD(f) abuf->fields.sfmt_bl8.f 328 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 329 const IDESC * UNUSED idesc = abuf->idesc; 330 int cycles = 0; 331 { 332 int referenced = 0; 333 int UNUSED insn_referenced = abuf->written; 334 INT in_sr = -1; 335 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 336 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 337 } 338 return cycles; 339 #undef FLD 340 } 341 342 static int 343 model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg) 344 { 345 #define FLD(f) abuf->fields.sfmt_bl24.f 346 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 347 const IDESC * UNUSED idesc = abuf->idesc; 348 int cycles = 0; 349 { 350 int referenced = 0; 351 int UNUSED insn_referenced = abuf->written; 352 INT in_sr = -1; 353 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 354 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 355 } 356 return cycles; 357 #undef FLD 358 } 359 360 static int 361 model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg) 362 { 363 #define FLD(f) abuf->fields.sfmt_beq.f 364 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 365 const IDESC * UNUSED idesc = abuf->idesc; 366 int cycles = 0; 367 { 368 int referenced = 0; 369 int UNUSED insn_referenced = abuf->written; 370 INT in_sr = -1; 371 if (insn_referenced & (1 << 3)) referenced |= 1 << 1; 372 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 373 } 374 { 375 int referenced = 0; 376 int UNUSED insn_referenced = abuf->written; 377 INT in_src1 = -1; 378 INT in_src2 = -1; 379 in_src1 = FLD (in_src1); 380 in_src2 = FLD (in_src2); 381 referenced |= 1 << 0; 382 referenced |= 1 << 1; 383 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 384 } 385 return cycles; 386 #undef FLD 387 } 388 389 static int 390 model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg) 391 { 392 #define FLD(f) abuf->fields.sfmt_beq.f 393 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 394 const IDESC * UNUSED idesc = abuf->idesc; 395 int cycles = 0; 396 { 397 int referenced = 0; 398 int UNUSED insn_referenced = abuf->written; 399 INT in_sr = -1; 400 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 401 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 402 } 403 { 404 int referenced = 0; 405 int UNUSED insn_referenced = abuf->written; 406 INT in_src1 = -1; 407 INT in_src2 = -1; 408 in_src2 = FLD (in_src2); 409 referenced |= 1 << 1; 410 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 411 } 412 return cycles; 413 #undef FLD 414 } 415 416 static int 417 model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg) 418 { 419 #define FLD(f) abuf->fields.sfmt_beq.f 420 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 421 const IDESC * UNUSED idesc = abuf->idesc; 422 int cycles = 0; 423 { 424 int referenced = 0; 425 int UNUSED insn_referenced = abuf->written; 426 INT in_sr = -1; 427 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 428 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 429 } 430 { 431 int referenced = 0; 432 int UNUSED insn_referenced = abuf->written; 433 INT in_src1 = -1; 434 INT in_src2 = -1; 435 in_src2 = FLD (in_src2); 436 referenced |= 1 << 1; 437 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 438 } 439 return cycles; 440 #undef FLD 441 } 442 443 static int 444 model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg) 445 { 446 #define FLD(f) abuf->fields.sfmt_beq.f 447 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 448 const IDESC * UNUSED idesc = abuf->idesc; 449 int cycles = 0; 450 { 451 int referenced = 0; 452 int UNUSED insn_referenced = abuf->written; 453 INT in_sr = -1; 454 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 455 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 456 } 457 { 458 int referenced = 0; 459 int UNUSED insn_referenced = abuf->written; 460 INT in_src1 = -1; 461 INT in_src2 = -1; 462 in_src2 = FLD (in_src2); 463 referenced |= 1 << 1; 464 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 465 } 466 return cycles; 467 #undef FLD 468 } 469 470 static int 471 model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg) 472 { 473 #define FLD(f) abuf->fields.sfmt_beq.f 474 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 475 const IDESC * UNUSED idesc = abuf->idesc; 476 int cycles = 0; 477 { 478 int referenced = 0; 479 int UNUSED insn_referenced = abuf->written; 480 INT in_sr = -1; 481 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 482 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 483 } 484 { 485 int referenced = 0; 486 int UNUSED insn_referenced = abuf->written; 487 INT in_src1 = -1; 488 INT in_src2 = -1; 489 in_src2 = FLD (in_src2); 490 referenced |= 1 << 1; 491 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 492 } 493 return cycles; 494 #undef FLD 495 } 496 497 static int 498 model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg) 499 { 500 #define FLD(f) abuf->fields.sfmt_beq.f 501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 502 const IDESC * UNUSED idesc = abuf->idesc; 503 int cycles = 0; 504 { 505 int referenced = 0; 506 int UNUSED insn_referenced = abuf->written; 507 INT in_sr = -1; 508 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 509 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 510 } 511 { 512 int referenced = 0; 513 int UNUSED insn_referenced = abuf->written; 514 INT in_src1 = -1; 515 INT in_src2 = -1; 516 in_src2 = FLD (in_src2); 517 referenced |= 1 << 1; 518 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 519 } 520 return cycles; 521 #undef FLD 522 } 523 524 static int 525 model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg) 526 { 527 #define FLD(f) abuf->fields.sfmt_beq.f 528 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 529 const IDESC * UNUSED idesc = abuf->idesc; 530 int cycles = 0; 531 { 532 int referenced = 0; 533 int UNUSED insn_referenced = abuf->written; 534 INT in_sr = -1; 535 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 536 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 537 } 538 { 539 int referenced = 0; 540 int UNUSED insn_referenced = abuf->written; 541 INT in_src1 = -1; 542 INT in_src2 = -1; 543 in_src2 = FLD (in_src2); 544 referenced |= 1 << 1; 545 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 546 } 547 return cycles; 548 #undef FLD 549 } 550 551 static int 552 model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg) 553 { 554 #define FLD(f) abuf->fields.sfmt_bl8.f 555 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 556 const IDESC * UNUSED idesc = abuf->idesc; 557 int cycles = 0; 558 { 559 int referenced = 0; 560 int UNUSED insn_referenced = abuf->written; 561 INT in_sr = -1; 562 referenced |= 1 << 1; 563 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 564 } 565 return cycles; 566 #undef FLD 567 } 568 569 static int 570 model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg) 571 { 572 #define FLD(f) abuf->fields.sfmt_bl24.f 573 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 574 const IDESC * UNUSED idesc = abuf->idesc; 575 int cycles = 0; 576 { 577 int referenced = 0; 578 int UNUSED insn_referenced = abuf->written; 579 INT in_sr = -1; 580 referenced |= 1 << 1; 581 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 582 } 583 return cycles; 584 #undef FLD 585 } 586 587 static int 588 model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg) 589 { 590 #define FLD(f) abuf->fields.sfmt_bl8.f 591 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 592 const IDESC * UNUSED idesc = abuf->idesc; 593 int cycles = 0; 594 { 595 int referenced = 0; 596 int UNUSED insn_referenced = abuf->written; 597 INT in_sr = -1; 598 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 599 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 600 } 601 return cycles; 602 #undef FLD 603 } 604 605 static int 606 model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg) 607 { 608 #define FLD(f) abuf->fields.sfmt_bl24.f 609 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 610 const IDESC * UNUSED idesc = abuf->idesc; 611 int cycles = 0; 612 { 613 int referenced = 0; 614 int UNUSED insn_referenced = abuf->written; 615 INT in_sr = -1; 616 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 617 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 618 } 619 return cycles; 620 #undef FLD 621 } 622 623 static int 624 model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg) 625 { 626 #define FLD(f) abuf->fields.sfmt_bl8.f 627 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 628 const IDESC * UNUSED idesc = abuf->idesc; 629 int cycles = 0; 630 { 631 int referenced = 0; 632 int UNUSED insn_referenced = abuf->written; 633 INT in_sr = -1; 634 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 635 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 636 } 637 return cycles; 638 #undef FLD 639 } 640 641 static int 642 model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg) 643 { 644 #define FLD(f) abuf->fields.sfmt_bl24.f 645 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 646 const IDESC * UNUSED idesc = abuf->idesc; 647 int cycles = 0; 648 { 649 int referenced = 0; 650 int UNUSED insn_referenced = abuf->written; 651 INT in_sr = -1; 652 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 653 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 654 } 655 return cycles; 656 #undef FLD 657 } 658 659 static int 660 model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg) 661 { 662 #define FLD(f) abuf->fields.sfmt_beq.f 663 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 664 const IDESC * UNUSED idesc = abuf->idesc; 665 int cycles = 0; 666 { 667 int referenced = 0; 668 int UNUSED insn_referenced = abuf->written; 669 INT in_sr = -1; 670 if (insn_referenced & (1 << 3)) referenced |= 1 << 1; 671 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 672 } 673 { 674 int referenced = 0; 675 int UNUSED insn_referenced = abuf->written; 676 INT in_src1 = -1; 677 INT in_src2 = -1; 678 in_src1 = FLD (in_src1); 679 in_src2 = FLD (in_src2); 680 referenced |= 1 << 0; 681 referenced |= 1 << 1; 682 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 683 } 684 return cycles; 685 #undef FLD 686 } 687 688 static int 689 model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg) 690 { 691 #define FLD(f) abuf->fields.sfmt_bl8.f 692 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 693 const IDESC * UNUSED idesc = abuf->idesc; 694 int cycles = 0; 695 { 696 int referenced = 0; 697 int UNUSED insn_referenced = abuf->written; 698 INT in_sr = -1; 699 referenced |= 1 << 1; 700 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 701 } 702 return cycles; 703 #undef FLD 704 } 705 706 static int 707 model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg) 708 { 709 #define FLD(f) abuf->fields.sfmt_bl24.f 710 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 711 const IDESC * UNUSED idesc = abuf->idesc; 712 int cycles = 0; 713 { 714 int referenced = 0; 715 int UNUSED insn_referenced = abuf->written; 716 INT in_sr = -1; 717 referenced |= 1 << 1; 718 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 719 } 720 return cycles; 721 #undef FLD 722 } 723 724 static int 725 model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg) 726 { 727 #define FLD(f) abuf->fields.sfmt_bl8.f 728 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 729 const IDESC * UNUSED idesc = abuf->idesc; 730 int cycles = 0; 731 { 732 int referenced = 0; 733 int UNUSED insn_referenced = abuf->written; 734 INT in_sr = -1; 735 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 736 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 737 } 738 return cycles; 739 #undef FLD 740 } 741 742 static int 743 model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg) 744 { 745 #define FLD(f) abuf->fields.sfmt_bl24.f 746 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 747 const IDESC * UNUSED idesc = abuf->idesc; 748 int cycles = 0; 749 { 750 int referenced = 0; 751 int UNUSED insn_referenced = abuf->written; 752 INT in_sr = -1; 753 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 754 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 755 } 756 return cycles; 757 #undef FLD 758 } 759 760 static int 761 model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg) 762 { 763 #define FLD(f) abuf->fields.sfmt_st_plus.f 764 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 765 const IDESC * UNUSED idesc = abuf->idesc; 766 int cycles = 0; 767 { 768 int referenced = 0; 769 int UNUSED insn_referenced = abuf->written; 770 INT in_src1 = -1; 771 INT in_src2 = -1; 772 in_src1 = FLD (in_src1); 773 in_src2 = FLD (in_src2); 774 referenced |= 1 << 0; 775 referenced |= 1 << 1; 776 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 777 } 778 return cycles; 779 #undef FLD 780 } 781 782 static int 783 model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg) 784 { 785 #define FLD(f) abuf->fields.sfmt_st_d.f 786 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 787 const IDESC * UNUSED idesc = abuf->idesc; 788 int cycles = 0; 789 { 790 int referenced = 0; 791 int UNUSED insn_referenced = abuf->written; 792 INT in_src1 = -1; 793 INT in_src2 = -1; 794 in_src2 = FLD (in_src2); 795 referenced |= 1 << 1; 796 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 797 } 798 return cycles; 799 #undef FLD 800 } 801 802 static int 803 model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg) 804 { 805 #define FLD(f) abuf->fields.sfmt_st_plus.f 806 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 807 const IDESC * UNUSED idesc = abuf->idesc; 808 int cycles = 0; 809 { 810 int referenced = 0; 811 int UNUSED insn_referenced = abuf->written; 812 INT in_src1 = -1; 813 INT in_src2 = -1; 814 in_src1 = FLD (in_src1); 815 in_src2 = FLD (in_src2); 816 referenced |= 1 << 0; 817 referenced |= 1 << 1; 818 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 819 } 820 return cycles; 821 #undef FLD 822 } 823 824 static int 825 model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg) 826 { 827 #define FLD(f) abuf->fields.sfmt_st_d.f 828 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 829 const IDESC * UNUSED idesc = abuf->idesc; 830 int cycles = 0; 831 { 832 int referenced = 0; 833 int UNUSED insn_referenced = abuf->written; 834 INT in_src1 = -1; 835 INT in_src2 = -1; 836 in_src2 = FLD (in_src2); 837 referenced |= 1 << 1; 838 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 839 } 840 return cycles; 841 #undef FLD 842 } 843 844 static int 845 model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg) 846 { 847 #define FLD(f) abuf->fields.sfmt_st_plus.f 848 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 849 const IDESC * UNUSED idesc = abuf->idesc; 850 int cycles = 0; 851 { 852 int referenced = 0; 853 int UNUSED insn_referenced = abuf->written; 854 INT in_src1 = -1; 855 INT in_src2 = -1; 856 in_src1 = FLD (in_src1); 857 in_src2 = FLD (in_src2); 858 referenced |= 1 << 0; 859 referenced |= 1 << 1; 860 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 861 } 862 return cycles; 863 #undef FLD 864 } 865 866 static int 867 model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg) 868 { 869 #define FLD(f) abuf->fields.sfmt_st_plus.f 870 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 871 const IDESC * UNUSED idesc = abuf->idesc; 872 int cycles = 0; 873 { 874 int referenced = 0; 875 int UNUSED insn_referenced = abuf->written; 876 INT in_src1 = -1; 877 INT in_src2 = -1; 878 in_src2 = FLD (in_src2); 879 referenced |= 1 << 1; 880 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 881 } 882 return cycles; 883 #undef FLD 884 } 885 886 static int 887 model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg) 888 { 889 #define FLD(f) abuf->fields.sfmt_add.f 890 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 891 const IDESC * UNUSED idesc = abuf->idesc; 892 int cycles = 0; 893 { 894 int referenced = 0; 895 int UNUSED insn_referenced = abuf->written; 896 INT in_sr = -1; 897 INT in_dr = -1; 898 INT out_dr = -1; 899 in_sr = FLD (in_sr); 900 in_dr = FLD (in_dr); 901 out_dr = FLD (out_dr); 902 referenced |= 1 << 0; 903 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 904 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 905 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 906 } 907 return cycles; 908 #undef FLD 909 } 910 911 static int 912 model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg) 913 { 914 #define FLD(f) abuf->fields.sfmt_add.f 915 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 916 const IDESC * UNUSED idesc = abuf->idesc; 917 int cycles = 0; 918 { 919 int referenced = 0; 920 int UNUSED insn_referenced = abuf->written; 921 INT in_sr = -1; 922 INT in_dr = -1; 923 INT out_dr = -1; 924 in_sr = FLD (in_sr); 925 in_dr = FLD (in_dr); 926 out_dr = FLD (out_dr); 927 referenced |= 1 << 0; 928 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 929 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 930 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 931 } 932 return cycles; 933 #undef FLD 934 } 935 936 static int 937 model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg) 938 { 939 #define FLD(f) abuf->fields.sfmt_add.f 940 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 941 const IDESC * UNUSED idesc = abuf->idesc; 942 int cycles = 0; 943 { 944 int referenced = 0; 945 int UNUSED insn_referenced = abuf->written; 946 INT in_sr = -1; 947 INT in_dr = -1; 948 INT out_dr = -1; 949 in_sr = FLD (in_sr); 950 in_dr = FLD (in_dr); 951 out_dr = FLD (out_dr); 952 referenced |= 1 << 0; 953 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 954 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 955 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 956 } 957 return cycles; 958 #undef FLD 959 } 960 961 static int 962 model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg) 963 { 964 #define FLD(f) abuf->fields.sfmt_add.f 965 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 966 const IDESC * UNUSED idesc = abuf->idesc; 967 int cycles = 0; 968 { 969 int referenced = 0; 970 int UNUSED insn_referenced = abuf->written; 971 INT in_sr = -1; 972 INT in_dr = -1; 973 INT out_dr = -1; 974 in_sr = FLD (in_sr); 975 in_dr = FLD (in_dr); 976 out_dr = FLD (out_dr); 977 referenced |= 1 << 0; 978 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 979 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 980 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 981 } 982 return cycles; 983 #undef FLD 984 } 985 986 static int 987 model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg) 988 { 989 #define FLD(f) abuf->fields.sfmt_add.f 990 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 991 const IDESC * UNUSED idesc = abuf->idesc; 992 int cycles = 0; 993 { 994 int referenced = 0; 995 int UNUSED insn_referenced = abuf->written; 996 INT in_sr = -1; 997 INT in_dr = -1; 998 INT out_dr = -1; 999 in_sr = FLD (in_sr); 1000 in_dr = FLD (in_dr); 1001 out_dr = FLD (out_dr); 1002 referenced |= 1 << 0; 1003 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 1004 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 1005 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1006 } 1007 return cycles; 1008 #undef FLD 1009 } 1010 1011 static int 1012 model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg) 1013 { 1014 #define FLD(f) abuf->fields.sfmt_jl.f 1015 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1016 const IDESC * UNUSED idesc = abuf->idesc; 1017 int cycles = 0; 1018 { 1019 int referenced = 0; 1020 int UNUSED insn_referenced = abuf->written; 1021 INT in_sr = -1; 1022 in_sr = FLD (in_sr); 1023 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 1024 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 1025 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1026 } 1027 return cycles; 1028 #undef FLD 1029 } 1030 1031 static int 1032 model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg) 1033 { 1034 #define FLD(f) abuf->fields.sfmt_jl.f 1035 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1036 const IDESC * UNUSED idesc = abuf->idesc; 1037 int cycles = 0; 1038 { 1039 int referenced = 0; 1040 int UNUSED insn_referenced = abuf->written; 1041 INT in_sr = -1; 1042 in_sr = FLD (in_sr); 1043 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 1044 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 1045 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1046 } 1047 return cycles; 1048 #undef FLD 1049 } 1050 1051 static int 1052 model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg) 1053 { 1054 #define FLD(f) abuf->fields.sfmt_jl.f 1055 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1056 const IDESC * UNUSED idesc = abuf->idesc; 1057 int cycles = 0; 1058 { 1059 int referenced = 0; 1060 int UNUSED insn_referenced = abuf->written; 1061 INT in_sr = -1; 1062 in_sr = FLD (in_sr); 1063 referenced |= 1 << 0; 1064 referenced |= 1 << 1; 1065 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1066 } 1067 return cycles; 1068 #undef FLD 1069 } 1070 1071 static int 1072 model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg) 1073 { 1074 #define FLD(f) abuf->fields.sfmt_jl.f 1075 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1076 const IDESC * UNUSED idesc = abuf->idesc; 1077 int cycles = 0; 1078 { 1079 int referenced = 0; 1080 int UNUSED insn_referenced = abuf->written; 1081 INT in_sr = -1; 1082 in_sr = FLD (in_sr); 1083 referenced |= 1 << 0; 1084 referenced |= 1 << 1; 1085 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1086 } 1087 return cycles; 1088 #undef FLD 1089 } 1090 1091 static int 1092 model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg) 1093 { 1094 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1095 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1096 const IDESC * UNUSED idesc = abuf->idesc; 1097 int cycles = 0; 1098 { 1099 int referenced = 0; 1100 int UNUSED insn_referenced = abuf->written; 1101 INT in_sr = 0; 1102 INT out_dr = 0; 1103 in_sr = FLD (in_sr); 1104 out_dr = FLD (out_dr); 1105 referenced |= 1 << 0; 1106 referenced |= 1 << 1; 1107 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1108 } 1109 return cycles; 1110 #undef FLD 1111 } 1112 1113 static int 1114 model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg) 1115 { 1116 #define FLD(f) abuf->fields.sfmt_add3.f 1117 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1118 const IDESC * UNUSED idesc = abuf->idesc; 1119 int cycles = 0; 1120 { 1121 int referenced = 0; 1122 int UNUSED insn_referenced = abuf->written; 1123 INT in_sr = 0; 1124 INT out_dr = 0; 1125 in_sr = FLD (in_sr); 1126 out_dr = FLD (out_dr); 1127 referenced |= 1 << 0; 1128 referenced |= 1 << 1; 1129 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1130 } 1131 return cycles; 1132 #undef FLD 1133 } 1134 1135 static int 1136 model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg) 1137 { 1138 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1139 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1140 const IDESC * UNUSED idesc = abuf->idesc; 1141 int cycles = 0; 1142 { 1143 int referenced = 0; 1144 int UNUSED insn_referenced = abuf->written; 1145 INT in_sr = 0; 1146 INT out_dr = 0; 1147 in_sr = FLD (in_sr); 1148 out_dr = FLD (out_dr); 1149 referenced |= 1 << 0; 1150 referenced |= 1 << 1; 1151 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1152 } 1153 return cycles; 1154 #undef FLD 1155 } 1156 1157 static int 1158 model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg) 1159 { 1160 #define FLD(f) abuf->fields.sfmt_add3.f 1161 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1162 const IDESC * UNUSED idesc = abuf->idesc; 1163 int cycles = 0; 1164 { 1165 int referenced = 0; 1166 int UNUSED insn_referenced = abuf->written; 1167 INT in_sr = 0; 1168 INT out_dr = 0; 1169 in_sr = FLD (in_sr); 1170 out_dr = FLD (out_dr); 1171 referenced |= 1 << 0; 1172 referenced |= 1 << 1; 1173 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1174 } 1175 return cycles; 1176 #undef FLD 1177 } 1178 1179 static int 1180 model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg) 1181 { 1182 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1183 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1184 const IDESC * UNUSED idesc = abuf->idesc; 1185 int cycles = 0; 1186 { 1187 int referenced = 0; 1188 int UNUSED insn_referenced = abuf->written; 1189 INT in_sr = 0; 1190 INT out_dr = 0; 1191 in_sr = FLD (in_sr); 1192 out_dr = FLD (out_dr); 1193 referenced |= 1 << 0; 1194 referenced |= 1 << 1; 1195 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1196 } 1197 return cycles; 1198 #undef FLD 1199 } 1200 1201 static int 1202 model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg) 1203 { 1204 #define FLD(f) abuf->fields.sfmt_add3.f 1205 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1206 const IDESC * UNUSED idesc = abuf->idesc; 1207 int cycles = 0; 1208 { 1209 int referenced = 0; 1210 int UNUSED insn_referenced = abuf->written; 1211 INT in_sr = 0; 1212 INT out_dr = 0; 1213 in_sr = FLD (in_sr); 1214 out_dr = FLD (out_dr); 1215 referenced |= 1 << 0; 1216 referenced |= 1 << 1; 1217 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1218 } 1219 return cycles; 1220 #undef FLD 1221 } 1222 1223 static int 1224 model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg) 1225 { 1226 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1227 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1228 const IDESC * UNUSED idesc = abuf->idesc; 1229 int cycles = 0; 1230 { 1231 int referenced = 0; 1232 int UNUSED insn_referenced = abuf->written; 1233 INT in_sr = 0; 1234 INT out_dr = 0; 1235 in_sr = FLD (in_sr); 1236 out_dr = FLD (out_dr); 1237 referenced |= 1 << 0; 1238 referenced |= 1 << 1; 1239 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1240 } 1241 return cycles; 1242 #undef FLD 1243 } 1244 1245 static int 1246 model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg) 1247 { 1248 #define FLD(f) abuf->fields.sfmt_add3.f 1249 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1250 const IDESC * UNUSED idesc = abuf->idesc; 1251 int cycles = 0; 1252 { 1253 int referenced = 0; 1254 int UNUSED insn_referenced = abuf->written; 1255 INT in_sr = 0; 1256 INT out_dr = 0; 1257 in_sr = FLD (in_sr); 1258 out_dr = FLD (out_dr); 1259 referenced |= 1 << 0; 1260 referenced |= 1 << 1; 1261 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1262 } 1263 return cycles; 1264 #undef FLD 1265 } 1266 1267 static int 1268 model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg) 1269 { 1270 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1271 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1272 const IDESC * UNUSED idesc = abuf->idesc; 1273 int cycles = 0; 1274 { 1275 int referenced = 0; 1276 int UNUSED insn_referenced = abuf->written; 1277 INT in_sr = 0; 1278 INT out_dr = 0; 1279 in_sr = FLD (in_sr); 1280 out_dr = FLD (out_dr); 1281 referenced |= 1 << 0; 1282 referenced |= 1 << 1; 1283 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1284 } 1285 return cycles; 1286 #undef FLD 1287 } 1288 1289 static int 1290 model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg) 1291 { 1292 #define FLD(f) abuf->fields.sfmt_add3.f 1293 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1294 const IDESC * UNUSED idesc = abuf->idesc; 1295 int cycles = 0; 1296 { 1297 int referenced = 0; 1298 int UNUSED insn_referenced = abuf->written; 1299 INT in_sr = 0; 1300 INT out_dr = 0; 1301 in_sr = FLD (in_sr); 1302 out_dr = FLD (out_dr); 1303 referenced |= 1 << 0; 1304 referenced |= 1 << 1; 1305 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1306 } 1307 return cycles; 1308 #undef FLD 1309 } 1310 1311 static int 1312 model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg) 1313 { 1314 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1315 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1316 const IDESC * UNUSED idesc = abuf->idesc; 1317 int cycles = 0; 1318 { 1319 int referenced = 0; 1320 int UNUSED insn_referenced = abuf->written; 1321 INT in_sr = 0; 1322 INT out_dr = 0; 1323 in_sr = FLD (in_sr); 1324 out_dr = FLD (out_dr); 1325 referenced |= 1 << 0; 1326 referenced |= 1 << 1; 1327 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1328 } 1329 { 1330 int referenced = 0; 1331 int UNUSED insn_referenced = abuf->written; 1332 INT in_sr = -1; 1333 INT in_dr = -1; 1334 INT out_dr = -1; 1335 in_dr = FLD (in_sr); 1336 out_dr = FLD (out_sr); 1337 referenced |= 1 << 0; 1338 referenced |= 1 << 2; 1339 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 1340 } 1341 return cycles; 1342 #undef FLD 1343 } 1344 1345 static int 1346 model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg) 1347 { 1348 #define FLD(f) abuf->fields.sfmt_ld24.f 1349 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1350 const IDESC * UNUSED idesc = abuf->idesc; 1351 int cycles = 0; 1352 { 1353 int referenced = 0; 1354 int UNUSED insn_referenced = abuf->written; 1355 INT in_sr = -1; 1356 INT in_dr = -1; 1357 INT out_dr = -1; 1358 out_dr = FLD (out_dr); 1359 referenced |= 1 << 2; 1360 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1361 } 1362 return cycles; 1363 #undef FLD 1364 } 1365 1366 static int 1367 model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg) 1368 { 1369 #define FLD(f) abuf->fields.sfmt_addi.f 1370 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1371 const IDESC * UNUSED idesc = abuf->idesc; 1372 int cycles = 0; 1373 { 1374 int referenced = 0; 1375 int UNUSED insn_referenced = abuf->written; 1376 INT in_sr = -1; 1377 INT in_dr = -1; 1378 INT out_dr = -1; 1379 out_dr = FLD (out_dr); 1380 referenced |= 1 << 2; 1381 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1382 } 1383 return cycles; 1384 #undef FLD 1385 } 1386 1387 static int 1388 model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg) 1389 { 1390 #define FLD(f) abuf->fields.sfmt_add3.f 1391 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1392 const IDESC * UNUSED idesc = abuf->idesc; 1393 int cycles = 0; 1394 { 1395 int referenced = 0; 1396 int UNUSED insn_referenced = abuf->written; 1397 INT in_sr = -1; 1398 INT in_dr = -1; 1399 INT out_dr = -1; 1400 out_dr = FLD (out_dr); 1401 referenced |= 1 << 2; 1402 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1403 } 1404 return cycles; 1405 #undef FLD 1406 } 1407 1408 static int 1409 model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg) 1410 { 1411 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1412 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1413 const IDESC * UNUSED idesc = abuf->idesc; 1414 int cycles = 0; 1415 { 1416 int referenced = 0; 1417 int UNUSED insn_referenced = abuf->written; 1418 INT in_sr = 0; 1419 INT out_dr = 0; 1420 in_sr = FLD (in_sr); 1421 out_dr = FLD (out_dr); 1422 referenced |= 1 << 0; 1423 referenced |= 1 << 1; 1424 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1425 } 1426 return cycles; 1427 #undef FLD 1428 } 1429 1430 static int 1431 model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg) 1432 { 1433 #define FLD(f) abuf->fields.sfmt_machi_a.f 1434 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1435 const IDESC * UNUSED idesc = abuf->idesc; 1436 int cycles = 0; 1437 { 1438 int referenced = 0; 1439 int UNUSED insn_referenced = abuf->written; 1440 INT in_src1 = -1; 1441 INT in_src2 = -1; 1442 in_src1 = FLD (in_src1); 1443 in_src2 = FLD (in_src2); 1444 referenced |= 1 << 0; 1445 referenced |= 1 << 1; 1446 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1447 } 1448 return cycles; 1449 #undef FLD 1450 } 1451 1452 static int 1453 model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg) 1454 { 1455 #define FLD(f) abuf->fields.sfmt_machi_a.f 1456 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1457 const IDESC * UNUSED idesc = abuf->idesc; 1458 int cycles = 0; 1459 { 1460 int referenced = 0; 1461 int UNUSED insn_referenced = abuf->written; 1462 INT in_src1 = -1; 1463 INT in_src2 = -1; 1464 in_src1 = FLD (in_src1); 1465 in_src2 = FLD (in_src2); 1466 referenced |= 1 << 0; 1467 referenced |= 1 << 1; 1468 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1469 } 1470 return cycles; 1471 #undef FLD 1472 } 1473 1474 static int 1475 model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg) 1476 { 1477 #define FLD(f) abuf->fields.sfmt_machi_a.f 1478 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1479 const IDESC * UNUSED idesc = abuf->idesc; 1480 int cycles = 0; 1481 { 1482 int referenced = 0; 1483 int UNUSED insn_referenced = abuf->written; 1484 INT in_src1 = -1; 1485 INT in_src2 = -1; 1486 in_src1 = FLD (in_src1); 1487 in_src2 = FLD (in_src2); 1488 referenced |= 1 << 0; 1489 referenced |= 1 << 1; 1490 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1491 } 1492 return cycles; 1493 #undef FLD 1494 } 1495 1496 static int 1497 model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg) 1498 { 1499 #define FLD(f) abuf->fields.sfmt_machi_a.f 1500 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1501 const IDESC * UNUSED idesc = abuf->idesc; 1502 int cycles = 0; 1503 { 1504 int referenced = 0; 1505 int UNUSED insn_referenced = abuf->written; 1506 INT in_src1 = -1; 1507 INT in_src2 = -1; 1508 in_src1 = FLD (in_src1); 1509 in_src2 = FLD (in_src2); 1510 referenced |= 1 << 0; 1511 referenced |= 1 << 1; 1512 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1513 } 1514 return cycles; 1515 #undef FLD 1516 } 1517 1518 static int 1519 model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg) 1520 { 1521 #define FLD(f) abuf->fields.sfmt_add.f 1522 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1523 const IDESC * UNUSED idesc = abuf->idesc; 1524 int cycles = 0; 1525 { 1526 int referenced = 0; 1527 int UNUSED insn_referenced = abuf->written; 1528 INT in_sr = -1; 1529 INT in_dr = -1; 1530 INT out_dr = -1; 1531 in_sr = FLD (in_sr); 1532 in_dr = FLD (in_dr); 1533 out_dr = FLD (out_dr); 1534 referenced |= 1 << 0; 1535 referenced |= 1 << 1; 1536 referenced |= 1 << 2; 1537 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1538 } 1539 return cycles; 1540 #undef FLD 1541 } 1542 1543 static int 1544 model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg) 1545 { 1546 #define FLD(f) abuf->fields.sfmt_machi_a.f 1547 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1548 const IDESC * UNUSED idesc = abuf->idesc; 1549 int cycles = 0; 1550 { 1551 int referenced = 0; 1552 int UNUSED insn_referenced = abuf->written; 1553 INT in_src1 = -1; 1554 INT in_src2 = -1; 1555 in_src1 = FLD (in_src1); 1556 in_src2 = FLD (in_src2); 1557 referenced |= 1 << 0; 1558 referenced |= 1 << 1; 1559 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1560 } 1561 return cycles; 1562 #undef FLD 1563 } 1564 1565 static int 1566 model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg) 1567 { 1568 #define FLD(f) abuf->fields.sfmt_machi_a.f 1569 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1570 const IDESC * UNUSED idesc = abuf->idesc; 1571 int cycles = 0; 1572 { 1573 int referenced = 0; 1574 int UNUSED insn_referenced = abuf->written; 1575 INT in_src1 = -1; 1576 INT in_src2 = -1; 1577 in_src1 = FLD (in_src1); 1578 in_src2 = FLD (in_src2); 1579 referenced |= 1 << 0; 1580 referenced |= 1 << 1; 1581 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1582 } 1583 return cycles; 1584 #undef FLD 1585 } 1586 1587 static int 1588 model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg) 1589 { 1590 #define FLD(f) abuf->fields.sfmt_machi_a.f 1591 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1592 const IDESC * UNUSED idesc = abuf->idesc; 1593 int cycles = 0; 1594 { 1595 int referenced = 0; 1596 int UNUSED insn_referenced = abuf->written; 1597 INT in_src1 = -1; 1598 INT in_src2 = -1; 1599 in_src1 = FLD (in_src1); 1600 in_src2 = FLD (in_src2); 1601 referenced |= 1 << 0; 1602 referenced |= 1 << 1; 1603 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1604 } 1605 return cycles; 1606 #undef FLD 1607 } 1608 1609 static int 1610 model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg) 1611 { 1612 #define FLD(f) abuf->fields.sfmt_machi_a.f 1613 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1614 const IDESC * UNUSED idesc = abuf->idesc; 1615 int cycles = 0; 1616 { 1617 int referenced = 0; 1618 int UNUSED insn_referenced = abuf->written; 1619 INT in_src1 = -1; 1620 INT in_src2 = -1; 1621 in_src1 = FLD (in_src1); 1622 in_src2 = FLD (in_src2); 1623 referenced |= 1 << 0; 1624 referenced |= 1 << 1; 1625 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1626 } 1627 return cycles; 1628 #undef FLD 1629 } 1630 1631 static int 1632 model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg) 1633 { 1634 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1635 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1636 const IDESC * UNUSED idesc = abuf->idesc; 1637 int cycles = 0; 1638 { 1639 int referenced = 0; 1640 int UNUSED insn_referenced = abuf->written; 1641 INT in_sr = -1; 1642 INT in_dr = -1; 1643 INT out_dr = -1; 1644 in_sr = FLD (in_sr); 1645 out_dr = FLD (out_dr); 1646 referenced |= 1 << 0; 1647 referenced |= 1 << 2; 1648 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1649 } 1650 return cycles; 1651 #undef FLD 1652 } 1653 1654 static int 1655 model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg) 1656 { 1657 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1658 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1659 const IDESC * UNUSED idesc = abuf->idesc; 1660 int cycles = 0; 1661 { 1662 int referenced = 0; 1663 int UNUSED insn_referenced = abuf->written; 1664 INT in_sr = -1; 1665 INT in_dr = -1; 1666 INT out_dr = -1; 1667 out_dr = FLD (out_dr); 1668 referenced |= 1 << 2; 1669 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1670 } 1671 return cycles; 1672 #undef FLD 1673 } 1674 1675 static int 1676 model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg) 1677 { 1678 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1679 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1680 const IDESC * UNUSED idesc = abuf->idesc; 1681 int cycles = 0; 1682 { 1683 int referenced = 0; 1684 int UNUSED insn_referenced = abuf->written; 1685 INT in_sr = -1; 1686 INT in_dr = -1; 1687 INT out_dr = -1; 1688 out_dr = FLD (out_dr); 1689 referenced |= 1 << 2; 1690 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1691 } 1692 return cycles; 1693 #undef FLD 1694 } 1695 1696 static int 1697 model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg) 1698 { 1699 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1700 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1701 const IDESC * UNUSED idesc = abuf->idesc; 1702 int cycles = 0; 1703 { 1704 int referenced = 0; 1705 int UNUSED insn_referenced = abuf->written; 1706 INT in_sr = -1; 1707 INT in_dr = -1; 1708 INT out_dr = -1; 1709 out_dr = FLD (out_dr); 1710 referenced |= 1 << 2; 1711 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1712 } 1713 return cycles; 1714 #undef FLD 1715 } 1716 1717 static int 1718 model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg) 1719 { 1720 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1721 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1722 const IDESC * UNUSED idesc = abuf->idesc; 1723 int cycles = 0; 1724 { 1725 int referenced = 0; 1726 int UNUSED insn_referenced = abuf->written; 1727 INT in_sr = -1; 1728 INT in_dr = -1; 1729 INT out_dr = -1; 1730 out_dr = FLD (out_dr); 1731 referenced |= 1 << 2; 1732 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1733 } 1734 return cycles; 1735 #undef FLD 1736 } 1737 1738 static int 1739 model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg) 1740 { 1741 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1742 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1743 const IDESC * UNUSED idesc = abuf->idesc; 1744 int cycles = 0; 1745 { 1746 int referenced = 0; 1747 int UNUSED insn_referenced = abuf->written; 1748 INT in_sr = -1; 1749 INT in_dr = -1; 1750 INT out_dr = -1; 1751 in_sr = FLD (in_src1); 1752 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1753 } 1754 return cycles; 1755 #undef FLD 1756 } 1757 1758 static int 1759 model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg) 1760 { 1761 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1762 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1763 const IDESC * UNUSED idesc = abuf->idesc; 1764 int cycles = 0; 1765 { 1766 int referenced = 0; 1767 int UNUSED insn_referenced = abuf->written; 1768 INT in_sr = -1; 1769 INT in_dr = -1; 1770 INT out_dr = -1; 1771 in_sr = FLD (in_src1); 1772 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1773 } 1774 return cycles; 1775 #undef FLD 1776 } 1777 1778 static int 1779 model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg) 1780 { 1781 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1782 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1783 const IDESC * UNUSED idesc = abuf->idesc; 1784 int cycles = 0; 1785 { 1786 int referenced = 0; 1787 int UNUSED insn_referenced = abuf->written; 1788 INT in_sr = -1; 1789 INT in_dr = -1; 1790 INT out_dr = -1; 1791 in_sr = FLD (in_sr); 1792 referenced |= 1 << 0; 1793 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1794 } 1795 return cycles; 1796 #undef FLD 1797 } 1798 1799 static int 1800 model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg) 1801 { 1802 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1803 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1804 const IDESC * UNUSED idesc = abuf->idesc; 1805 int cycles = 0; 1806 { 1807 int referenced = 0; 1808 int UNUSED insn_referenced = abuf->written; 1809 INT in_sr = -1; 1810 INT in_dr = -1; 1811 INT out_dr = -1; 1812 in_sr = FLD (in_sr); 1813 out_dr = FLD (out_dr); 1814 referenced |= 1 << 0; 1815 referenced |= 1 << 2; 1816 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1817 } 1818 return cycles; 1819 #undef FLD 1820 } 1821 1822 static int 1823 model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg) 1824 { 1825 #define FLD(f) abuf->fields.sfmt_empty.f 1826 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1827 const IDESC * UNUSED idesc = abuf->idesc; 1828 int cycles = 0; 1829 { 1830 int referenced = 0; 1831 int UNUSED insn_referenced = abuf->written; 1832 INT in_sr = -1; 1833 INT in_dr = -1; 1834 INT out_dr = -1; 1835 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1836 } 1837 return cycles; 1838 #undef FLD 1839 } 1840 1841 static int 1842 model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg) 1843 { 1844 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1845 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1846 const IDESC * UNUSED idesc = abuf->idesc; 1847 int cycles = 0; 1848 { 1849 int referenced = 0; 1850 int UNUSED insn_referenced = abuf->written; 1851 INT in_sr = -1; 1852 INT in_dr = -1; 1853 INT out_dr = -1; 1854 in_sr = FLD (in_sr); 1855 out_dr = FLD (out_dr); 1856 referenced |= 1 << 0; 1857 referenced |= 1 << 2; 1858 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1859 } 1860 return cycles; 1861 #undef FLD 1862 } 1863 1864 static int 1865 model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg) 1866 { 1867 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1868 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1869 const IDESC * UNUSED idesc = abuf->idesc; 1870 int cycles = 0; 1871 { 1872 int referenced = 0; 1873 int UNUSED insn_referenced = abuf->written; 1874 INT in_src1 = -1; 1875 INT in_src2 = -1; 1876 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1877 } 1878 return cycles; 1879 #undef FLD 1880 } 1881 1882 static int 1883 model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg) 1884 { 1885 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1886 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1887 const IDESC * UNUSED idesc = abuf->idesc; 1888 int cycles = 0; 1889 { 1890 int referenced = 0; 1891 int UNUSED insn_referenced = abuf->written; 1892 INT in_src1 = -1; 1893 INT in_src2 = -1; 1894 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1895 } 1896 return cycles; 1897 #undef FLD 1898 } 1899 1900 static int 1901 model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg) 1902 { 1903 #define FLD(f) abuf->fields.sfmt_empty.f 1904 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1905 const IDESC * UNUSED idesc = abuf->idesc; 1906 int cycles = 0; 1907 { 1908 int referenced = 0; 1909 int UNUSED insn_referenced = abuf->written; 1910 INT in_sr = -1; 1911 INT in_dr = -1; 1912 INT out_dr = -1; 1913 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1914 } 1915 return cycles; 1916 #undef FLD 1917 } 1918 1919 static int 1920 model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg) 1921 { 1922 #define FLD(f) abuf->fields.sfmt_seth.f 1923 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1924 const IDESC * UNUSED idesc = abuf->idesc; 1925 int cycles = 0; 1926 { 1927 int referenced = 0; 1928 int UNUSED insn_referenced = abuf->written; 1929 INT in_sr = -1; 1930 INT in_dr = -1; 1931 INT out_dr = -1; 1932 out_dr = FLD (out_dr); 1933 referenced |= 1 << 2; 1934 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1935 } 1936 return cycles; 1937 #undef FLD 1938 } 1939 1940 static int 1941 model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg) 1942 { 1943 #define FLD(f) abuf->fields.sfmt_add.f 1944 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1945 const IDESC * UNUSED idesc = abuf->idesc; 1946 int cycles = 0; 1947 { 1948 int referenced = 0; 1949 int UNUSED insn_referenced = abuf->written; 1950 INT in_sr = -1; 1951 INT in_dr = -1; 1952 INT out_dr = -1; 1953 in_sr = FLD (in_sr); 1954 in_dr = FLD (in_dr); 1955 out_dr = FLD (out_dr); 1956 referenced |= 1 << 0; 1957 referenced |= 1 << 1; 1958 referenced |= 1 << 2; 1959 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1960 } 1961 return cycles; 1962 #undef FLD 1963 } 1964 1965 static int 1966 model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg) 1967 { 1968 #define FLD(f) abuf->fields.sfmt_add3.f 1969 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1970 const IDESC * UNUSED idesc = abuf->idesc; 1971 int cycles = 0; 1972 { 1973 int referenced = 0; 1974 int UNUSED insn_referenced = abuf->written; 1975 INT in_sr = -1; 1976 INT in_dr = -1; 1977 INT out_dr = -1; 1978 in_sr = FLD (in_sr); 1979 out_dr = FLD (out_dr); 1980 referenced |= 1 << 0; 1981 referenced |= 1 << 2; 1982 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1983 } 1984 return cycles; 1985 #undef FLD 1986 } 1987 1988 static int 1989 model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg) 1990 { 1991 #define FLD(f) abuf->fields.sfmt_slli.f 1992 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1993 const IDESC * UNUSED idesc = abuf->idesc; 1994 int cycles = 0; 1995 { 1996 int referenced = 0; 1997 int UNUSED insn_referenced = abuf->written; 1998 INT in_sr = -1; 1999 INT in_dr = -1; 2000 INT out_dr = -1; 2001 in_dr = FLD (in_dr); 2002 out_dr = FLD (out_dr); 2003 referenced |= 1 << 1; 2004 referenced |= 1 << 2; 2005 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2006 } 2007 return cycles; 2008 #undef FLD 2009 } 2010 2011 static int 2012 model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg) 2013 { 2014 #define FLD(f) abuf->fields.sfmt_add.f 2015 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2016 const IDESC * UNUSED idesc = abuf->idesc; 2017 int cycles = 0; 2018 { 2019 int referenced = 0; 2020 int UNUSED insn_referenced = abuf->written; 2021 INT in_sr = -1; 2022 INT in_dr = -1; 2023 INT out_dr = -1; 2024 in_sr = FLD (in_sr); 2025 in_dr = FLD (in_dr); 2026 out_dr = FLD (out_dr); 2027 referenced |= 1 << 0; 2028 referenced |= 1 << 1; 2029 referenced |= 1 << 2; 2030 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2031 } 2032 return cycles; 2033 #undef FLD 2034 } 2035 2036 static int 2037 model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg) 2038 { 2039 #define FLD(f) abuf->fields.sfmt_add3.f 2040 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2041 const IDESC * UNUSED idesc = abuf->idesc; 2042 int cycles = 0; 2043 { 2044 int referenced = 0; 2045 int UNUSED insn_referenced = abuf->written; 2046 INT in_sr = -1; 2047 INT in_dr = -1; 2048 INT out_dr = -1; 2049 in_sr = FLD (in_sr); 2050 out_dr = FLD (out_dr); 2051 referenced |= 1 << 0; 2052 referenced |= 1 << 2; 2053 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2054 } 2055 return cycles; 2056 #undef FLD 2057 } 2058 2059 static int 2060 model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg) 2061 { 2062 #define FLD(f) abuf->fields.sfmt_slli.f 2063 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2064 const IDESC * UNUSED idesc = abuf->idesc; 2065 int cycles = 0; 2066 { 2067 int referenced = 0; 2068 int UNUSED insn_referenced = abuf->written; 2069 INT in_sr = -1; 2070 INT in_dr = -1; 2071 INT out_dr = -1; 2072 in_dr = FLD (in_dr); 2073 out_dr = FLD (out_dr); 2074 referenced |= 1 << 1; 2075 referenced |= 1 << 2; 2076 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2077 } 2078 return cycles; 2079 #undef FLD 2080 } 2081 2082 static int 2083 model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg) 2084 { 2085 #define FLD(f) abuf->fields.sfmt_add.f 2086 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2087 const IDESC * UNUSED idesc = abuf->idesc; 2088 int cycles = 0; 2089 { 2090 int referenced = 0; 2091 int UNUSED insn_referenced = abuf->written; 2092 INT in_sr = -1; 2093 INT in_dr = -1; 2094 INT out_dr = -1; 2095 in_sr = FLD (in_sr); 2096 in_dr = FLD (in_dr); 2097 out_dr = FLD (out_dr); 2098 referenced |= 1 << 0; 2099 referenced |= 1 << 1; 2100 referenced |= 1 << 2; 2101 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2102 } 2103 return cycles; 2104 #undef FLD 2105 } 2106 2107 static int 2108 model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg) 2109 { 2110 #define FLD(f) abuf->fields.sfmt_add3.f 2111 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2112 const IDESC * UNUSED idesc = abuf->idesc; 2113 int cycles = 0; 2114 { 2115 int referenced = 0; 2116 int UNUSED insn_referenced = abuf->written; 2117 INT in_sr = -1; 2118 INT in_dr = -1; 2119 INT out_dr = -1; 2120 in_sr = FLD (in_sr); 2121 out_dr = FLD (out_dr); 2122 referenced |= 1 << 0; 2123 referenced |= 1 << 2; 2124 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2125 } 2126 return cycles; 2127 #undef FLD 2128 } 2129 2130 static int 2131 model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg) 2132 { 2133 #define FLD(f) abuf->fields.sfmt_slli.f 2134 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2135 const IDESC * UNUSED idesc = abuf->idesc; 2136 int cycles = 0; 2137 { 2138 int referenced = 0; 2139 int UNUSED insn_referenced = abuf->written; 2140 INT in_sr = -1; 2141 INT in_dr = -1; 2142 INT out_dr = -1; 2143 in_dr = FLD (in_dr); 2144 out_dr = FLD (out_dr); 2145 referenced |= 1 << 1; 2146 referenced |= 1 << 2; 2147 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2148 } 2149 return cycles; 2150 #undef FLD 2151 } 2152 2153 static int 2154 model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg) 2155 { 2156 #define FLD(f) abuf->fields.sfmt_st_plus.f 2157 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2158 const IDESC * UNUSED idesc = abuf->idesc; 2159 int cycles = 0; 2160 { 2161 int referenced = 0; 2162 int UNUSED insn_referenced = abuf->written; 2163 INT in_src1 = 0; 2164 INT in_src2 = 0; 2165 in_src1 = FLD (in_src1); 2166 in_src2 = FLD (in_src2); 2167 referenced |= 1 << 0; 2168 referenced |= 1 << 1; 2169 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2170 } 2171 return cycles; 2172 #undef FLD 2173 } 2174 2175 static int 2176 model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg) 2177 { 2178 #define FLD(f) abuf->fields.sfmt_st_d.f 2179 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2180 const IDESC * UNUSED idesc = abuf->idesc; 2181 int cycles = 0; 2182 { 2183 int referenced = 0; 2184 int UNUSED insn_referenced = abuf->written; 2185 INT in_src1 = 0; 2186 INT in_src2 = 0; 2187 in_src1 = FLD (in_src1); 2188 in_src2 = FLD (in_src2); 2189 referenced |= 1 << 0; 2190 referenced |= 1 << 1; 2191 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2192 } 2193 return cycles; 2194 #undef FLD 2195 } 2196 2197 static int 2198 model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg) 2199 { 2200 #define FLD(f) abuf->fields.sfmt_st_plus.f 2201 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2202 const IDESC * UNUSED idesc = abuf->idesc; 2203 int cycles = 0; 2204 { 2205 int referenced = 0; 2206 int UNUSED insn_referenced = abuf->written; 2207 INT in_src1 = 0; 2208 INT in_src2 = 0; 2209 in_src1 = FLD (in_src1); 2210 in_src2 = FLD (in_src2); 2211 referenced |= 1 << 0; 2212 referenced |= 1 << 1; 2213 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2214 } 2215 return cycles; 2216 #undef FLD 2217 } 2218 2219 static int 2220 model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg) 2221 { 2222 #define FLD(f) abuf->fields.sfmt_st_d.f 2223 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2224 const IDESC * UNUSED idesc = abuf->idesc; 2225 int cycles = 0; 2226 { 2227 int referenced = 0; 2228 int UNUSED insn_referenced = abuf->written; 2229 INT in_src1 = 0; 2230 INT in_src2 = 0; 2231 in_src1 = FLD (in_src1); 2232 in_src2 = FLD (in_src2); 2233 referenced |= 1 << 0; 2234 referenced |= 1 << 1; 2235 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2236 } 2237 return cycles; 2238 #undef FLD 2239 } 2240 2241 static int 2242 model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg) 2243 { 2244 #define FLD(f) abuf->fields.sfmt_st_plus.f 2245 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2246 const IDESC * UNUSED idesc = abuf->idesc; 2247 int cycles = 0; 2248 { 2249 int referenced = 0; 2250 int UNUSED insn_referenced = abuf->written; 2251 INT in_src1 = 0; 2252 INT in_src2 = 0; 2253 in_src1 = FLD (in_src1); 2254 in_src2 = FLD (in_src2); 2255 referenced |= 1 << 0; 2256 referenced |= 1 << 1; 2257 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2258 } 2259 return cycles; 2260 #undef FLD 2261 } 2262 2263 static int 2264 model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg) 2265 { 2266 #define FLD(f) abuf->fields.sfmt_st_d.f 2267 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2268 const IDESC * UNUSED idesc = abuf->idesc; 2269 int cycles = 0; 2270 { 2271 int referenced = 0; 2272 int UNUSED insn_referenced = abuf->written; 2273 INT in_src1 = 0; 2274 INT in_src2 = 0; 2275 in_src1 = FLD (in_src1); 2276 in_src2 = FLD (in_src2); 2277 referenced |= 1 << 0; 2278 referenced |= 1 << 1; 2279 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2280 } 2281 return cycles; 2282 #undef FLD 2283 } 2284 2285 static int 2286 model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg) 2287 { 2288 #define FLD(f) abuf->fields.sfmt_st_plus.f 2289 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2290 const IDESC * UNUSED idesc = abuf->idesc; 2291 int cycles = 0; 2292 { 2293 int referenced = 0; 2294 int UNUSED insn_referenced = abuf->written; 2295 INT in_src1 = 0; 2296 INT in_src2 = 0; 2297 in_src1 = FLD (in_src1); 2298 in_src2 = FLD (in_src2); 2299 referenced |= 1 << 0; 2300 referenced |= 1 << 1; 2301 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2302 } 2303 { 2304 int referenced = 0; 2305 int UNUSED insn_referenced = abuf->written; 2306 INT in_sr = -1; 2307 INT in_dr = -1; 2308 INT out_dr = -1; 2309 in_dr = FLD (in_src2); 2310 out_dr = FLD (out_src2); 2311 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2312 } 2313 return cycles; 2314 #undef FLD 2315 } 2316 2317 static int 2318 model_m32rx_sth_plus (SIM_CPU *current_cpu, void *sem_arg) 2319 { 2320 #define FLD(f) abuf->fields.sfmt_st_plus.f 2321 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2322 const IDESC * UNUSED idesc = abuf->idesc; 2323 int cycles = 0; 2324 { 2325 int referenced = 0; 2326 int UNUSED insn_referenced = abuf->written; 2327 INT in_src1 = 0; 2328 INT in_src2 = 0; 2329 in_src1 = FLD (in_src1); 2330 in_src2 = FLD (in_src2); 2331 referenced |= 1 << 0; 2332 referenced |= 1 << 1; 2333 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2334 } 2335 { 2336 int referenced = 0; 2337 int UNUSED insn_referenced = abuf->written; 2338 INT in_sr = -1; 2339 INT in_dr = -1; 2340 INT out_dr = -1; 2341 in_dr = FLD (in_src2); 2342 out_dr = FLD (out_src2); 2343 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2344 } 2345 return cycles; 2346 #undef FLD 2347 } 2348 2349 static int 2350 model_m32rx_stb_plus (SIM_CPU *current_cpu, void *sem_arg) 2351 { 2352 #define FLD(f) abuf->fields.sfmt_st_plus.f 2353 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2354 const IDESC * UNUSED idesc = abuf->idesc; 2355 int cycles = 0; 2356 { 2357 int referenced = 0; 2358 int UNUSED insn_referenced = abuf->written; 2359 INT in_src1 = 0; 2360 INT in_src2 = 0; 2361 in_src1 = FLD (in_src1); 2362 in_src2 = FLD (in_src2); 2363 referenced |= 1 << 0; 2364 referenced |= 1 << 1; 2365 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2366 } 2367 { 2368 int referenced = 0; 2369 int UNUSED insn_referenced = abuf->written; 2370 INT in_sr = -1; 2371 INT in_dr = -1; 2372 INT out_dr = -1; 2373 in_dr = FLD (in_src2); 2374 out_dr = FLD (out_src2); 2375 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2376 } 2377 return cycles; 2378 #undef FLD 2379 } 2380 2381 static int 2382 model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg) 2383 { 2384 #define FLD(f) abuf->fields.sfmt_st_plus.f 2385 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2386 const IDESC * UNUSED idesc = abuf->idesc; 2387 int cycles = 0; 2388 { 2389 int referenced = 0; 2390 int UNUSED insn_referenced = abuf->written; 2391 INT in_src1 = 0; 2392 INT in_src2 = 0; 2393 in_src1 = FLD (in_src1); 2394 in_src2 = FLD (in_src2); 2395 referenced |= 1 << 0; 2396 referenced |= 1 << 1; 2397 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2398 } 2399 { 2400 int referenced = 0; 2401 int UNUSED insn_referenced = abuf->written; 2402 INT in_sr = -1; 2403 INT in_dr = -1; 2404 INT out_dr = -1; 2405 in_dr = FLD (in_src2); 2406 out_dr = FLD (out_src2); 2407 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2408 } 2409 return cycles; 2410 #undef FLD 2411 } 2412 2413 static int 2414 model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg) 2415 { 2416 #define FLD(f) abuf->fields.sfmt_add.f 2417 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2418 const IDESC * UNUSED idesc = abuf->idesc; 2419 int cycles = 0; 2420 { 2421 int referenced = 0; 2422 int UNUSED insn_referenced = abuf->written; 2423 INT in_sr = -1; 2424 INT in_dr = -1; 2425 INT out_dr = -1; 2426 in_sr = FLD (in_sr); 2427 in_dr = FLD (in_dr); 2428 out_dr = FLD (out_dr); 2429 referenced |= 1 << 0; 2430 referenced |= 1 << 1; 2431 referenced |= 1 << 2; 2432 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2433 } 2434 return cycles; 2435 #undef FLD 2436 } 2437 2438 static int 2439 model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg) 2440 { 2441 #define FLD(f) abuf->fields.sfmt_add.f 2442 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2443 const IDESC * UNUSED idesc = abuf->idesc; 2444 int cycles = 0; 2445 { 2446 int referenced = 0; 2447 int UNUSED insn_referenced = abuf->written; 2448 INT in_sr = -1; 2449 INT in_dr = -1; 2450 INT out_dr = -1; 2451 in_sr = FLD (in_sr); 2452 in_dr = FLD (in_dr); 2453 out_dr = FLD (out_dr); 2454 referenced |= 1 << 0; 2455 referenced |= 1 << 1; 2456 referenced |= 1 << 2; 2457 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2458 } 2459 return cycles; 2460 #undef FLD 2461 } 2462 2463 static int 2464 model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg) 2465 { 2466 #define FLD(f) abuf->fields.sfmt_add.f 2467 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2468 const IDESC * UNUSED idesc = abuf->idesc; 2469 int cycles = 0; 2470 { 2471 int referenced = 0; 2472 int UNUSED insn_referenced = abuf->written; 2473 INT in_sr = -1; 2474 INT in_dr = -1; 2475 INT out_dr = -1; 2476 in_sr = FLD (in_sr); 2477 in_dr = FLD (in_dr); 2478 out_dr = FLD (out_dr); 2479 referenced |= 1 << 0; 2480 referenced |= 1 << 1; 2481 referenced |= 1 << 2; 2482 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2483 } 2484 return cycles; 2485 #undef FLD 2486 } 2487 2488 static int 2489 model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg) 2490 { 2491 #define FLD(f) abuf->fields.sfmt_trap.f 2492 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2493 const IDESC * UNUSED idesc = abuf->idesc; 2494 int cycles = 0; 2495 { 2496 int referenced = 0; 2497 int UNUSED insn_referenced = abuf->written; 2498 INT in_sr = -1; 2499 INT in_dr = -1; 2500 INT out_dr = -1; 2501 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2502 } 2503 return cycles; 2504 #undef FLD 2505 } 2506 2507 static int 2508 model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg) 2509 { 2510 #define FLD(f) abuf->fields.sfmt_st_plus.f 2511 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2512 const IDESC * UNUSED idesc = abuf->idesc; 2513 int cycles = 0; 2514 { 2515 int referenced = 0; 2516 int UNUSED insn_referenced = abuf->written; 2517 INT in_sr = 0; 2518 INT out_dr = 0; 2519 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 2520 } 2521 return cycles; 2522 #undef FLD 2523 } 2524 2525 static int 2526 model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg) 2527 { 2528 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2529 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2530 const IDESC * UNUSED idesc = abuf->idesc; 2531 int cycles = 0; 2532 { 2533 int referenced = 0; 2534 int UNUSED insn_referenced = abuf->written; 2535 INT in_sr = -1; 2536 INT in_dr = -1; 2537 INT out_dr = -1; 2538 in_sr = FLD (in_sr); 2539 out_dr = FLD (out_dr); 2540 referenced |= 1 << 0; 2541 referenced |= 1 << 2; 2542 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2543 } 2544 return cycles; 2545 #undef FLD 2546 } 2547 2548 static int 2549 model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg) 2550 { 2551 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2552 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2553 const IDESC * UNUSED idesc = abuf->idesc; 2554 int cycles = 0; 2555 { 2556 int referenced = 0; 2557 int UNUSED insn_referenced = abuf->written; 2558 INT in_sr = -1; 2559 INT in_dr = -1; 2560 INT out_dr = -1; 2561 in_sr = FLD (in_sr); 2562 out_dr = FLD (out_dr); 2563 referenced |= 1 << 0; 2564 referenced |= 1 << 2; 2565 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2566 } 2567 return cycles; 2568 #undef FLD 2569 } 2570 2571 static int 2572 model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg) 2573 { 2574 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2575 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2576 const IDESC * UNUSED idesc = abuf->idesc; 2577 int cycles = 0; 2578 { 2579 int referenced = 0; 2580 int UNUSED insn_referenced = abuf->written; 2581 INT in_sr = -1; 2582 INT in_dr = -1; 2583 INT out_dr = -1; 2584 in_sr = FLD (in_sr); 2585 out_dr = FLD (out_dr); 2586 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 2587 referenced |= 1 << 2; 2588 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2589 } 2590 return cycles; 2591 #undef FLD 2592 } 2593 2594 static int 2595 model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg) 2596 { 2597 #define FLD(f) abuf->fields.sfmt_st_plus.f 2598 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2599 const IDESC * UNUSED idesc = abuf->idesc; 2600 int cycles = 0; 2601 { 2602 int referenced = 0; 2603 int UNUSED insn_referenced = abuf->written; 2604 INT in_src1 = -1; 2605 INT in_src2 = -1; 2606 in_src2 = FLD (in_src2); 2607 referenced |= 1 << 1; 2608 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2609 } 2610 return cycles; 2611 #undef FLD 2612 } 2613 2614 static int 2615 model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg) 2616 { 2617 #define FLD(f) abuf->fields.sfmt_empty.f 2618 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2619 const IDESC * UNUSED idesc = abuf->idesc; 2620 int cycles = 0; 2621 { 2622 int referenced = 0; 2623 int UNUSED insn_referenced = abuf->written; 2624 INT in_src1 = -1; 2625 INT in_src2 = -1; 2626 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2627 } 2628 return cycles; 2629 #undef FLD 2630 } 2631 2632 static int 2633 model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg) 2634 { 2635 #define FLD(f) abuf->fields.sfmt_st_plus.f 2636 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2637 const IDESC * UNUSED idesc = abuf->idesc; 2638 int cycles = 0; 2639 { 2640 int referenced = 0; 2641 int UNUSED insn_referenced = abuf->written; 2642 INT in_src1 = -1; 2643 INT in_src2 = -1; 2644 in_src1 = FLD (in_src1); 2645 in_src2 = FLD (in_src2); 2646 referenced |= 1 << 0; 2647 referenced |= 1 << 1; 2648 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2649 } 2650 return cycles; 2651 #undef FLD 2652 } 2653 2654 static int 2655 model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg) 2656 { 2657 #define FLD(f) abuf->fields.sfmt_st_plus.f 2658 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2659 const IDESC * UNUSED idesc = abuf->idesc; 2660 int cycles = 0; 2661 { 2662 int referenced = 0; 2663 int UNUSED insn_referenced = abuf->written; 2664 INT in_src1 = -1; 2665 INT in_src2 = -1; 2666 in_src1 = FLD (in_src1); 2667 in_src2 = FLD (in_src2); 2668 referenced |= 1 << 0; 2669 referenced |= 1 << 1; 2670 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2671 } 2672 return cycles; 2673 #undef FLD 2674 } 2675 2676 static int 2677 model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg) 2678 { 2679 #define FLD(f) abuf->fields.sfmt_st_plus.f 2680 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2681 const IDESC * UNUSED idesc = abuf->idesc; 2682 int cycles = 0; 2683 { 2684 int referenced = 0; 2685 int UNUSED insn_referenced = abuf->written; 2686 INT in_src1 = -1; 2687 INT in_src2 = -1; 2688 in_src1 = FLD (in_src1); 2689 in_src2 = FLD (in_src2); 2690 referenced |= 1 << 0; 2691 referenced |= 1 << 1; 2692 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2693 } 2694 return cycles; 2695 #undef FLD 2696 } 2697 2698 static int 2699 model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg) 2700 { 2701 #define FLD(f) abuf->fields.sfmt_st_plus.f 2702 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2703 const IDESC * UNUSED idesc = abuf->idesc; 2704 int cycles = 0; 2705 { 2706 int referenced = 0; 2707 int UNUSED insn_referenced = abuf->written; 2708 INT in_src1 = -1; 2709 INT in_src2 = -1; 2710 in_src1 = FLD (in_src1); 2711 in_src2 = FLD (in_src2); 2712 referenced |= 1 << 0; 2713 referenced |= 1 << 1; 2714 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2715 } 2716 return cycles; 2717 #undef FLD 2718 } 2719 2720 static int 2721 model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg) 2722 { 2723 #define FLD(f) abuf->fields.sfmt_empty.f 2724 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2725 const IDESC * UNUSED idesc = abuf->idesc; 2726 int cycles = 0; 2727 { 2728 int referenced = 0; 2729 int UNUSED insn_referenced = abuf->written; 2730 INT in_sr = -1; 2731 INT in_dr = -1; 2732 INT out_dr = -1; 2733 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2734 } 2735 return cycles; 2736 #undef FLD 2737 } 2738 2739 static int 2740 model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg) 2741 { 2742 #define FLD(f) abuf->fields.sfmt_empty.f 2743 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2744 const IDESC * UNUSED idesc = abuf->idesc; 2745 int cycles = 0; 2746 { 2747 int referenced = 0; 2748 int UNUSED insn_referenced = abuf->written; 2749 INT in_sr = -1; 2750 INT in_dr = -1; 2751 INT out_dr = -1; 2752 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2753 } 2754 return cycles; 2755 #undef FLD 2756 } 2757 2758 static int 2759 model_m32rx_clrpsw (SIM_CPU *current_cpu, void *sem_arg) 2760 { 2761 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2762 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2763 const IDESC * UNUSED idesc = abuf->idesc; 2764 int cycles = 0; 2765 { 2766 int referenced = 0; 2767 int UNUSED insn_referenced = abuf->written; 2768 INT in_sr = -1; 2769 INT in_dr = -1; 2770 INT out_dr = -1; 2771 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2772 } 2773 return cycles; 2774 #undef FLD 2775 } 2776 2777 static int 2778 model_m32rx_setpsw (SIM_CPU *current_cpu, void *sem_arg) 2779 { 2780 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2781 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2782 const IDESC * UNUSED idesc = abuf->idesc; 2783 int cycles = 0; 2784 { 2785 int referenced = 0; 2786 int UNUSED insn_referenced = abuf->written; 2787 INT in_sr = -1; 2788 INT in_dr = -1; 2789 INT out_dr = -1; 2790 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2791 } 2792 return cycles; 2793 #undef FLD 2794 } 2795 2796 static int 2797 model_m32rx_bset (SIM_CPU *current_cpu, void *sem_arg) 2798 { 2799 #define FLD(f) abuf->fields.sfmt_bset.f 2800 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2801 const IDESC * UNUSED idesc = abuf->idesc; 2802 int cycles = 0; 2803 { 2804 int referenced = 0; 2805 int UNUSED insn_referenced = abuf->written; 2806 INT in_sr = -1; 2807 INT in_dr = -1; 2808 INT out_dr = -1; 2809 in_sr = FLD (in_sr); 2810 referenced |= 1 << 0; 2811 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2812 } 2813 return cycles; 2814 #undef FLD 2815 } 2816 2817 static int 2818 model_m32rx_bclr (SIM_CPU *current_cpu, void *sem_arg) 2819 { 2820 #define FLD(f) abuf->fields.sfmt_bset.f 2821 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2822 const IDESC * UNUSED idesc = abuf->idesc; 2823 int cycles = 0; 2824 { 2825 int referenced = 0; 2826 int UNUSED insn_referenced = abuf->written; 2827 INT in_sr = -1; 2828 INT in_dr = -1; 2829 INT out_dr = -1; 2830 in_sr = FLD (in_sr); 2831 referenced |= 1 << 0; 2832 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2833 } 2834 return cycles; 2835 #undef FLD 2836 } 2837 2838 static int 2839 model_m32rx_btst (SIM_CPU *current_cpu, void *sem_arg) 2840 { 2841 #define FLD(f) abuf->fields.sfmt_bset.f 2842 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2843 const IDESC * UNUSED idesc = abuf->idesc; 2844 int cycles = 0; 2845 { 2846 int referenced = 0; 2847 int UNUSED insn_referenced = abuf->written; 2848 INT in_sr = -1; 2849 INT in_dr = -1; 2850 INT out_dr = -1; 2851 in_sr = FLD (in_sr); 2852 referenced |= 1 << 0; 2853 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2854 } 2855 return cycles; 2856 #undef FLD 2857 } 2858 2859 /* We assume UNIT_NONE == 0 because the tables don't always terminate 2860 entries with it. */ 2861 2862 /* Model timing data for `m32rx'. */ 2863 2864 static const INSN_TIMING m32rx_timing[] = { 2865 { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2866 { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2867 { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2868 { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2869 { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2870 { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2871 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2872 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2873 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2874 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2875 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2876 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2877 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2878 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2879 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2880 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2881 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2882 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2883 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2884 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2885 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2886 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2887 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2888 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2889 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2890 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2891 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2892 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2893 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2894 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2895 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2896 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2897 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2898 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2899 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2900 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2901 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2902 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2903 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2904 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2905 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2906 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2907 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2908 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2909 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2910 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2911 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2912 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2913 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } }, 2914 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2915 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2916 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2917 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2918 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2919 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2920 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2921 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2922 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2923 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2924 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2925 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2926 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2927 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2928 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2929 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2930 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2931 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2932 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2933 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2934 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2935 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2936 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2937 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } }, 2938 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2939 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2940 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2941 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2942 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2943 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2944 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2945 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2946 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2947 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2948 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2949 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2950 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2951 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2952 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2953 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2954 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2955 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2956 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2957 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2958 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2959 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2960 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2961 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2962 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2963 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2964 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2965 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2966 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2967 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2968 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2969 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2970 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2971 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2972 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2973 { M32RXF_INSN_STH_PLUS, model_m32rx_sth_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2974 { M32RXF_INSN_STB_PLUS, model_m32rx_stb_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2975 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2976 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2977 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2978 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2979 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2980 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2981 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2982 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2983 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2984 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2985 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2986 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2987 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2988 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2989 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2990 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2991 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2992 { M32RXF_INSN_CLRPSW, model_m32rx_clrpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2993 { M32RXF_INSN_SETPSW, model_m32rx_setpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2994 { M32RXF_INSN_BSET, model_m32rx_bset, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2995 { M32RXF_INSN_BCLR, model_m32rx_bclr, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2996 { M32RXF_INSN_BTST, model_m32rx_btst, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2997 }; 2998 2999 #endif /* WITH_PROFILE_MODEL_P */ 3000 3001 static void 3002 m32rx_model_init (SIM_CPU *cpu) 3003 { 3004 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA)); 3005 } 3006 3007 #if WITH_PROFILE_MODEL_P 3008 #define TIMING_DATA(td) td 3009 #else 3010 #define TIMING_DATA(td) 0 3011 #endif 3012 3013 static const MODEL m32rx_models[] = 3014 { 3015 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init }, 3016 { 0 } 3017 }; 3018 3019 /* The properties of this cpu's implementation. */ 3020 3021 static const MACH_IMP_PROPERTIES m32rxf_imp_properties = 3022 { 3023 sizeof (SIM_CPU), 3024 #if WITH_SCACHE 3025 sizeof (SCACHE) 3026 #else 3027 0 3028 #endif 3029 }; 3030 3031 3032 static void 3033 m32rxf_prepare_run (SIM_CPU *cpu) 3034 { 3035 if (CPU_IDESC (cpu) == NULL) 3036 m32rxf_init_idesc_table (cpu); 3037 } 3038 3039 static const CGEN_INSN * 3040 m32rxf_get_idata (SIM_CPU *cpu, int inum) 3041 { 3042 return CPU_IDESC (cpu) [inum].idata; 3043 } 3044 3045 static void 3046 m32rx_init_cpu (SIM_CPU *cpu) 3047 { 3048 CPU_REG_FETCH (cpu) = m32rxf_fetch_register; 3049 CPU_REG_STORE (cpu) = m32rxf_store_register; 3050 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get; 3051 CPU_PC_STORE (cpu) = m32rxf_h_pc_set; 3052 CPU_GET_IDATA (cpu) = m32rxf_get_idata; 3053 CPU_MAX_INSNS (cpu) = M32RXF_INSN__MAX; 3054 CPU_INSN_NAME (cpu) = cgen_insn_name; 3055 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full; 3056 #if WITH_FAST 3057 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast; 3058 #else 3059 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full; 3060 #endif 3061 } 3062 3063 const MACH m32rx_mach = 3064 { 3065 "m32rx", "m32rx", MACH_M32RX, 3066 32, 32, & m32rx_models[0], & m32rxf_imp_properties, 3067 m32rx_init_cpu, 3068 m32rxf_prepare_run 3069 }; 3070 3071
Indexes created Thu May 07 00:24:58 UTC 2026