xref: /src/external/gpl3/gdb.old/dist/sim/testsuite/frv/mmachu.cgs

# frv testcase for mmachu $GRi,$GRj,$GRk
# mach: frv fr500 fr400

	.include "testutils.inc"

	start

	.global mmachu
mmachu:
	set_fr_iimmed  	3,2,fr7		; multiply small numbers
	set_fr_iimmed  	2,3,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	6,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	6,acc1

	set_fr_iimmed  	1,2,fr7		; multiply by 1
	set_fr_iimmed  	2,1,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	8,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	8,acc1

	set_fr_iimmed  	0,2,fr7		; multiply by 0
	set_fr_iimmed  	2,0,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	8,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	8,acc1

	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
	set_fr_iimmed  	2,0x3fff,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_limmed	0x0000,0x8006,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed	0x0000,0x8006,acc1

	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
	set_fr_iimmed  	2,0x4000,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_limmed	0x0001,0x0006,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed	0x0001,0x0006,acc1

	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
	set_fr_iimmed  	2,0x8000,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	0x00020006,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	0x00020006,acc1

	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
	set_fr_iimmed  	0x7fff,0x7fff,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_immed 	0x40010007,acc0
	test_accg_immed 	0,accg1
	test_acc_immed 	0x40010007,acc1

	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
	set_fr_iimmed  	0x8000,0x8000,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	0,accg0
	test_acc_limmed	0x8001,0x0007,acc0
	test_accg_immed 	0,accg1
	test_acc_limmed	0x8001,0x0007,acc1

	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
	set_fr_iimmed  	0xffff,0xffff,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
	test_accg_immed 	1,accg0
	test_acc_limmed	0x7fff,0x0008,acc0
	test_accg_immed 	1,accg1
	test_acc_limmed	0x7fff,0x0008,acc1

	set_accg_immed 	0xff,accg0		; saturation
	set_acc_immed	0xffffffff,acc0
	set_accg_immed 	0xff,accg1
	set_acc_immed	0xffffffff,acc1
	set_fr_iimmed  	1,1,fr7
	set_fr_iimmed  	1,1,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
	test_accg_immed 	0xff,accg0
	test_acc_limmed	0xffff,0xffff,acc0
	test_accg_immed 	0xff,accg1
	test_acc_limmed	0xffff,0xffff,acc1

	set_fr_iimmed  	0xffff,0x0000,fr7
	set_fr_iimmed  	0xffff,0xffff,fr8
	mmachu      	fr7,fr8,acc0
	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
	test_accg_immed 	0xff,accg0
	test_acc_limmed	0xffff,0xffff,acc0
	test_accg_immed 	0xff,accg1
	test_acc_limmed	0xffff,0xffff,acc1

	pass