1 1.1 christos # Hitachi H8 testcase 'bset', 'bclr' 2 1.1 christos # mach(): all 3 1.1 christos # as(h8300): --defsym sim_cpu=0 4 1.1 christos # as(h8300h): --defsym sim_cpu=1 5 1.1 christos # as(h8300s): --defsym sim_cpu=2 6 1.1 christos # as(h8sx): --defsym sim_cpu=3 7 1.1 christos # ld(h8300h): -m h8300helf 8 1.1 christos # ld(h8300s): -m h8300self 9 1.1 christos # ld(h8sx): -m h8300sxelf 10 1.1 christos 11 1.1 christos .include "testutils.inc" 12 1.1 christos 13 1.1 christos # Instructions tested: 14 1.1 christos # 15 1.1 christos # bset xx:3, rd8 ; 7 0 ?xxx rd8 16 1.1 christos # bclr xx:3, rd8 ; 7 2 ?xxx rd8 17 1.1 christos # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ???? 18 1.1 christos # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ???? 19 1.1 christos # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ???? 20 1.1 christos # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ???? 21 1.1 christos # bset reg8, rd8 ; 6 0 rs8 rd8 22 1.1 christos # bclr reg8, rd8 ; 6 2 rs8 rd8 23 1.1 christos # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ???? 24 1.1 christos # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ???? 25 1.1 christos # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ???? 26 1.1 christos # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ???? 27 1.1 christos # 28 1.1 christos # bset/eq xx:3, rd8 29 1.1 christos # bclr/eq xx:3, rd8 30 1.1 christos # bset/ne xx:3, rd8 31 1.1 christos # bclr/ne xx:3, rd8 32 1.1 christos 33 1.1 christos .data 34 1.1 christos byte_dst: .byte 0 35 1.1 christos 36 1.1 christos start 37 1.1 christos 38 1.1 christos bset_imm3_reg8: 39 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 40 1.1 christos 41 1.1 christos ;; bset xx:3, rd8 42 1.1 christos mov #0, r1l 43 1.1 christos set_ccr_zero 44 1.1 christos bset #0, r1l 45 1.1 christos test_cc_clear 46 1.1 christos test_h_gr8 1 r1l 47 1.1 christos 48 1.1 christos set_ccr_zero 49 1.1 christos bset #1, r1l 50 1.1 christos test_cc_clear 51 1.1 christos test_h_gr8 3 r1l 52 1.1 christos 53 1.1 christos set_ccr_zero 54 1.1 christos bset #2, r1l 55 1.1 christos test_cc_clear 56 1.1 christos test_h_gr8 7 r1l 57 1.1 christos 58 1.1 christos set_ccr_zero 59 1.1 christos bset #3, r1l 60 1.1 christos test_cc_clear 61 1.1 christos test_h_gr8 15 r1l 62 1.1 christos 63 1.1 christos set_ccr_zero 64 1.1 christos bset #4, r1l 65 1.1 christos test_cc_clear 66 1.1 christos test_h_gr8 31 r1l 67 1.1 christos 68 1.1 christos set_ccr_zero 69 1.1 christos bset #5, r1l 70 1.1 christos test_cc_clear 71 1.1 christos test_h_gr8 63 r1l 72 1.1 christos 73 1.1 christos set_ccr_zero 74 1.1 christos bset #6, r1l 75 1.1 christos test_cc_clear 76 1.1 christos test_h_gr8 127 r1l 77 1.1 christos 78 1.1 christos set_ccr_zero 79 1.1 christos bset #7, r1l 80 1.1 christos test_cc_clear 81 1.1 christos test_h_gr8 255 r1l 82 1.1 christos 83 1.1 christos .if (sim_cpu == h8300) 84 1.1 christos test_h_gr16 0xa5ff, r1 85 1.1 christos .else 86 1.1 christos test_h_gr32 0xa5a5a5ff er1 87 1.1 christos .endif 88 1.1 christos 89 1.1 christos bclr_imm3_reg8: 90 1.1 christos set_ccr_zero 91 1.1 christos bclr #7, r1l 92 1.1 christos test_cc_clear 93 1.1 christos test_h_gr8 127 r1l 94 1.1 christos 95 1.1 christos set_ccr_zero 96 1.1 christos bclr #6, r1l 97 1.1 christos test_cc_clear 98 1.1 christos test_h_gr8 63 r1l 99 1.1 christos 100 1.1 christos set_ccr_zero 101 1.1 christos bclr #5, r1l 102 1.1 christos test_cc_clear 103 1.1 christos test_h_gr8 31 r1l 104 1.1 christos 105 1.1 christos set_ccr_zero 106 1.1 christos bclr #4, r1l 107 1.1 christos test_cc_clear 108 1.1 christos test_h_gr8 15 r1l 109 1.1 christos 110 1.1 christos set_ccr_zero 111 1.1 christos bclr #3, r1l 112 1.1 christos test_cc_clear 113 1.1 christos test_h_gr8 7 r1l 114 1.1 christos 115 1.1 christos set_ccr_zero 116 1.1 christos bclr #2, r1l 117 1.1 christos test_cc_clear 118 1.1 christos test_h_gr8 3 r1l 119 1.1 christos 120 1.1 christos set_ccr_zero 121 1.1 christos bclr #1, r1l 122 1.1 christos test_cc_clear 123 1.1 christos test_h_gr8 1 r1l 124 1.1 christos 125 1.1 christos set_ccr_zero 126 1.1 christos bclr #0, r1l 127 1.1 christos test_cc_clear 128 1.1 christos test_h_gr8 0 r1l 129 1.1 christos 130 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 131 1.1 christos .if (sim_cpu == h8300) 132 1.1 christos test_h_gr16 0xa500 r1 133 1.1 christos .else 134 1.1 christos test_h_gr32 0xa5a5a500 er1 135 1.1 christos .endif 136 1.1 christos test_gr_a5a5 2 137 1.1 christos test_gr_a5a5 3 138 1.1 christos test_gr_a5a5 4 139 1.1 christos test_gr_a5a5 5 140 1.1 christos test_gr_a5a5 6 141 1.1 christos test_gr_a5a5 7 142 1.1 christos 143 1.1 christos .if (sim_cpu) 144 1.1 christos bset_imm3_ind: 145 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 146 1.1 christos 147 1.1 christos ;; bset xx:3, @erd 148 1.1 christos mov #byte_dst, er1 149 1.1 christos set_ccr_zero 150 1.1 christos bset #0, @er1 151 1.1 christos test_cc_clear 152 1.1 christos mov @er1, r2l 153 1.1 christos test_h_gr8 1 r2l 154 1.1 christos 155 1.1 christos set_ccr_zero 156 1.1 christos bset #1, @er1 157 1.1 christos test_cc_clear 158 1.1 christos mov @er1, r2l 159 1.1 christos test_h_gr8 3 r2l 160 1.1 christos 161 1.1 christos set_ccr_zero 162 1.1 christos bset #2, @er1 163 1.1 christos test_cc_clear 164 1.1 christos mov @er1, r2l 165 1.1 christos test_h_gr8 7 r2l 166 1.1 christos 167 1.1 christos set_ccr_zero 168 1.1 christos bset #3, @er1 169 1.1 christos test_cc_clear 170 1.1 christos mov @er1, r2l 171 1.1 christos test_h_gr8 15 r2l 172 1.1 christos 173 1.1 christos set_ccr_zero 174 1.1 christos bset #4, @er1 175 1.1 christos test_cc_clear 176 1.1 christos mov @er1, r2l 177 1.1 christos test_h_gr8 31 r2l 178 1.1 christos 179 1.1 christos set_ccr_zero 180 1.1 christos bset #5, @er1 181 1.1 christos test_cc_clear 182 1.1 christos mov @er1, r2l 183 1.1 christos test_h_gr8 63 r2l 184 1.1 christos 185 1.1 christos set_ccr_zero 186 1.1 christos bset #6, @er1 187 1.1 christos test_cc_clear 188 1.1 christos mov @er1, r2l 189 1.1 christos test_h_gr8 127 r2l 190 1.1 christos 191 1.1 christos set_ccr_zero 192 1.1 christos bset #7, @er1 193 1.1 christos test_cc_clear 194 1.1 christos mov @er1, r2l 195 1.1 christos test_h_gr8 255 r2l 196 1.1 christos 197 1.1 christos .if (sim_cpu == h8300) 198 1.1 christos test_h_gr16 0xa5ff r2 199 1.1 christos .else 200 1.1 christos test_h_gr32 0xa5a5a5ff er2 201 1.1 christos .endif 202 1.1 christos 203 1.1 christos bclr_imm3_ind: 204 1.1 christos set_ccr_zero 205 1.1 christos bclr #7, @er1 206 1.1 christos test_cc_clear 207 1.1 christos mov @er1, r2l 208 1.1 christos test_h_gr8 127 r2l 209 1.1 christos 210 1.1 christos set_ccr_zero 211 1.1 christos bclr #6, @er1 212 1.1 christos test_cc_clear 213 1.1 christos mov @er1, r2l 214 1.1 christos test_h_gr8 63 r2l 215 1.1 christos 216 1.1 christos set_ccr_zero 217 1.1 christos bclr #5, @er1 218 1.1 christos test_cc_clear 219 1.1 christos mov @er1, r2l 220 1.1 christos test_h_gr8 31 r2l 221 1.1 christos 222 1.1 christos set_ccr_zero 223 1.1 christos bclr #4, @er1 224 1.1 christos test_cc_clear 225 1.1 christos mov @er1, r2l 226 1.1 christos test_h_gr8 15 r2l 227 1.1 christos 228 1.1 christos set_ccr_zero 229 1.1 christos bclr #3, @er1 230 1.1 christos test_cc_clear 231 1.1 christos mov @er1, r2l 232 1.1 christos test_h_gr8 7 r2l 233 1.1 christos 234 1.1 christos set_ccr_zero 235 1.1 christos bclr #2, @er1 236 1.1 christos test_cc_clear 237 1.1 christos mov @er1, r2l 238 1.1 christos test_h_gr8 3 r2l 239 1.1 christos 240 1.1 christos set_ccr_zero 241 1.1 christos bclr #1, @er1 242 1.1 christos test_cc_clear 243 1.1 christos mov @er1, r2l 244 1.1 christos test_h_gr8 1 r2l 245 1.1 christos 246 1.1 christos set_ccr_zero 247 1.1 christos bclr #0, @er1 248 1.1 christos test_cc_clear 249 1.1 christos mov @er1, r2l 250 1.1 christos test_h_gr8 0 r2l 251 1.1 christos 252 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 253 1.1 christos .if (sim_cpu == h8300) 254 1.1 christos test_h_gr16 byte_dst r1 255 1.1 christos test_h_gr16 0xa500 r2 256 1.1 christos .else 257 1.1 christos test_h_gr32 byte_dst er1 258 1.1 christos test_h_gr32 0xa5a5a500 er2 259 1.1 christos .endif 260 1.1 christos test_gr_a5a5 3 261 1.1 christos test_gr_a5a5 4 262 1.1 christos test_gr_a5a5 5 263 1.1 christos test_gr_a5a5 6 264 1.1 christos test_gr_a5a5 7 265 1.1 christos 266 1.1 christos .if (sim_cpu > h8300h) 267 1.1 christos bset_imm3_abs16: 268 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 269 1.1 christos 270 1.1 christos ;; bset xx:3, @aa:16 271 1.1 christos set_ccr_zero 272 1.1 christos bset #0, @byte_dst:16 273 1.1 christos test_cc_clear 274 1.1 christos mov @byte_dst, r2l 275 1.1 christos test_h_gr8 1 r2l 276 1.1 christos 277 1.1 christos set_ccr_zero 278 1.1 christos bset #1, @byte_dst:16 279 1.1 christos test_cc_clear 280 1.1 christos mov @byte_dst, r2l 281 1.1 christos test_h_gr8 3 r2l 282 1.1 christos 283 1.1 christos set_ccr_zero 284 1.1 christos bset #2, @byte_dst:16 285 1.1 christos test_cc_clear 286 1.1 christos mov @byte_dst, r2l 287 1.1 christos test_h_gr8 7 r2l 288 1.1 christos 289 1.1 christos set_ccr_zero 290 1.1 christos bset #3, @byte_dst:16 291 1.1 christos test_cc_clear 292 1.1 christos mov @byte_dst, r2l 293 1.1 christos test_h_gr8 15 r2l 294 1.1 christos 295 1.1 christos set_ccr_zero 296 1.1 christos bset #4, @byte_dst:16 297 1.1 christos test_cc_clear 298 1.1 christos mov @byte_dst, r2l 299 1.1 christos test_h_gr8 31 r2l 300 1.1 christos 301 1.1 christos set_ccr_zero 302 1.1 christos bset #5, @byte_dst:16 303 1.1 christos test_cc_clear 304 1.1 christos mov @byte_dst, r2l 305 1.1 christos test_h_gr8 63 r2l 306 1.1 christos 307 1.1 christos set_ccr_zero 308 1.1 christos bset #6, @byte_dst:16 309 1.1 christos test_cc_clear 310 1.1 christos mov @byte_dst, r2l 311 1.1 christos test_h_gr8 127 r2l 312 1.1 christos 313 1.1 christos set_ccr_zero 314 1.1 christos bset #7, @byte_dst:16 315 1.1 christos test_cc_clear 316 1.1 christos mov @byte_dst, r2l 317 1.1 christos test_h_gr8 255 r2l 318 1.1 christos 319 1.1 christos .if (sim_cpu == h8300) 320 1.1 christos test_h_gr16 0xa5ff r2 321 1.1 christos .else 322 1.1 christos test_h_gr32 0xa5a5a5ff er2 323 1.1 christos .endif 324 1.1 christos 325 1.1 christos bclr_imm3_abs16: 326 1.1 christos set_ccr_zero 327 1.1 christos bclr #7, @byte_dst:16 328 1.1 christos test_cc_clear 329 1.1 christos mov @byte_dst, r2l 330 1.1 christos test_h_gr8 127 r2l 331 1.1 christos 332 1.1 christos set_ccr_zero 333 1.1 christos bclr #6, @byte_dst:16 334 1.1 christos test_cc_clear 335 1.1 christos mov @byte_dst, r2l 336 1.1 christos test_h_gr8 63 r2l 337 1.1 christos 338 1.1 christos set_ccr_zero 339 1.1 christos bclr #5, @byte_dst:16 340 1.1 christos test_cc_clear 341 1.1 christos mov @byte_dst, r2l 342 1.1 christos test_h_gr8 31 r2l 343 1.1 christos 344 1.1 christos set_ccr_zero 345 1.1 christos bclr #4, @byte_dst:16 346 1.1 christos test_cc_clear 347 1.1 christos mov @byte_dst, r2l 348 1.1 christos test_h_gr8 15 r2l 349 1.1 christos 350 1.1 christos set_ccr_zero 351 1.1 christos bclr #3, @byte_dst:16 352 1.1 christos test_cc_clear 353 1.1 christos mov @byte_dst, r2l 354 1.1 christos test_h_gr8 7 r2l 355 1.1 christos 356 1.1 christos set_ccr_zero 357 1.1 christos bclr #2, @byte_dst:16 358 1.1 christos test_cc_clear 359 1.1 christos mov @byte_dst, r2l 360 1.1 christos test_h_gr8 3 r2l 361 1.1 christos 362 1.1 christos set_ccr_zero 363 1.1 christos bclr #1, @byte_dst:16 364 1.1 christos test_cc_clear 365 1.1 christos mov @byte_dst, r2l 366 1.1 christos test_h_gr8 1 r2l 367 1.1 christos 368 1.1 christos set_ccr_zero 369 1.1 christos bclr #0, @byte_dst:16 370 1.1 christos test_cc_clear 371 1.1 christos mov @byte_dst, r2l 372 1.1 christos test_h_gr8 0 r2l 373 1.1 christos 374 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 375 1.1 christos test_gr_a5a5 1 376 1.1 christos .if (sim_cpu == h8300) 377 1.1 christos test_h_gr16 0xa500 r2 378 1.1 christos .else 379 1.1 christos test_h_gr32 0xa5a5a500 er2 380 1.1 christos .endif 381 1.1 christos test_gr_a5a5 3 382 1.1 christos test_gr_a5a5 4 383 1.1 christos test_gr_a5a5 5 384 1.1 christos test_gr_a5a5 6 385 1.1 christos test_gr_a5a5 7 386 1.1 christos .endif 387 1.1 christos .endif 388 1.1 christos 389 1.1 christos bset_rs8_rd8: 390 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 391 1.1 christos 392 1.1 christos ;; bset rs8, rd8 393 1.1 christos mov #0, r1h 394 1.1 christos mov #0, r1l 395 1.1 christos set_ccr_zero 396 1.1 christos bset r1h, r1l 397 1.1 christos test_cc_clear 398 1.1 christos test_h_gr8 1 r1l 399 1.1 christos 400 1.1 christos mov #1, r1h 401 1.1 christos set_ccr_zero 402 1.1 christos bset r1h, r1l 403 1.1 christos test_cc_clear 404 1.1 christos test_h_gr8 3 r1l 405 1.1 christos 406 1.1 christos mov #2, r1h 407 1.1 christos set_ccr_zero 408 1.1 christos bset r1h, r1l 409 1.1 christos test_cc_clear 410 1.1 christos test_h_gr8 7 r1l 411 1.1 christos 412 1.1 christos mov #3, r1h 413 1.1 christos set_ccr_zero 414 1.1 christos bset r1h, r1l 415 1.1 christos test_cc_clear 416 1.1 christos test_h_gr8 15 r1l 417 1.1 christos 418 1.1 christos mov #4, r1h 419 1.1 christos set_ccr_zero 420 1.1 christos bset r1h, r1l 421 1.1 christos test_cc_clear 422 1.1 christos test_h_gr8 31 r1l 423 1.1 christos 424 1.1 christos mov #5, r1h 425 1.1 christos set_ccr_zero 426 1.1 christos bset r1h, r1l 427 1.1 christos test_cc_clear 428 1.1 christos test_h_gr8 63 r1l 429 1.1 christos 430 1.1 christos mov #6, r1h 431 1.1 christos set_ccr_zero 432 1.1 christos bset r1h, r1l 433 1.1 christos test_cc_clear 434 1.1 christos test_h_gr8 127 r1l 435 1.1 christos 436 1.1 christos mov #7, r1h 437 1.1 christos set_ccr_zero 438 1.1 christos bset r1h, r1l 439 1.1 christos test_cc_clear 440 1.1 christos test_h_gr8 255 r1l 441 1.1 christos 442 1.1 christos .if (sim_cpu == h8300) 443 1.1 christos test_h_gr16 0x07ff, r1 444 1.1 christos .else 445 1.1 christos test_h_gr32 0xa5a507ff er1 446 1.1 christos .endif 447 1.1 christos 448 1.1 christos bclr_rs8_rd8: 449 1.1 christos mov #7, r1h 450 1.1 christos set_ccr_zero 451 1.1 christos bclr r1h, r1l 452 1.1 christos test_cc_clear 453 1.1 christos test_h_gr8 127 r1l 454 1.1 christos 455 1.1 christos mov #6, r1h 456 1.1 christos set_ccr_zero 457 1.1 christos bclr r1h, r1l 458 1.1 christos test_cc_clear 459 1.1 christos test_h_gr8 63 r1l 460 1.1 christos 461 1.1 christos mov #5, r1h 462 1.1 christos set_ccr_zero 463 1.1 christos bclr r1h, r1l 464 1.1 christos test_cc_clear 465 1.1 christos test_h_gr8 31 r1l 466 1.1 christos 467 1.1 christos mov #4, r1h 468 1.1 christos set_ccr_zero 469 1.1 christos bclr r1h, r1l 470 1.1 christos test_cc_clear 471 1.1 christos test_h_gr8 15 r1l 472 1.1 christos 473 1.1 christos mov #3, r1h 474 1.1 christos set_ccr_zero 475 1.1 christos bclr r1h, r1l 476 1.1 christos test_cc_clear 477 1.1 christos test_h_gr8 7 r1l 478 1.1 christos 479 1.1 christos mov #2, r1h 480 1.1 christos set_ccr_zero 481 1.1 christos bclr r1h, r1l 482 1.1 christos test_cc_clear 483 1.1 christos test_h_gr8 3 r1l 484 1.1 christos 485 1.1 christos mov #1, r1h 486 1.1 christos set_ccr_zero 487 1.1 christos bclr r1h, r1l 488 1.1 christos test_cc_clear 489 1.1 christos test_h_gr8 1 r1l 490 1.1 christos 491 1.1 christos mov #0, r1h 492 1.1 christos set_ccr_zero 493 1.1 christos bclr r1h, r1l 494 1.1 christos test_cc_clear 495 1.1 christos test_h_gr8 0 r1l 496 1.1 christos 497 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 498 1.1 christos .if (sim_cpu == h8300) 499 1.1 christos test_h_gr16 0x0000 r1 500 1.1 christos .else 501 1.1 christos test_h_gr32 0xa5a50000 er1 502 1.1 christos .endif 503 1.1 christos test_gr_a5a5 2 504 1.1 christos test_gr_a5a5 3 505 1.1 christos test_gr_a5a5 4 506 1.1 christos test_gr_a5a5 5 507 1.1 christos test_gr_a5a5 6 508 1.1 christos test_gr_a5a5 7 509 1.1 christos 510 1.1 christos .if (sim_cpu) 511 1.1 christos bset_rs8_ind: 512 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 513 1.1 christos 514 1.1 christos ;; bset rs8, @erd 515 1.1 christos mov #byte_dst, er1 516 1.1 christos mov #0, r2h 517 1.1 christos set_ccr_zero 518 1.1 christos bset r2h, @er1 519 1.1 christos test_cc_clear 520 1.1 christos mov @er1, r2l 521 1.1 christos test_h_gr8 1 r2l 522 1.1 christos 523 1.1 christos mov #1, r2h 524 1.1 christos set_ccr_zero 525 1.1 christos bset r2h, @er1 526 1.1 christos test_cc_clear 527 1.1 christos mov @er1, r2l 528 1.1 christos test_h_gr8 3 r2l 529 1.1 christos 530 1.1 christos mov #2, r2h 531 1.1 christos set_ccr_zero 532 1.1 christos bset r2h, @er1 533 1.1 christos test_cc_clear 534 1.1 christos mov @er1, r2l 535 1.1 christos test_h_gr8 7 r2l 536 1.1 christos 537 1.1 christos mov #3, r2h 538 1.1 christos set_ccr_zero 539 1.1 christos bset r2h, @er1 540 1.1 christos test_cc_clear 541 1.1 christos mov @er1, r2l 542 1.1 christos test_h_gr8 15 r2l 543 1.1 christos 544 1.1 christos mov #4, r2h 545 1.1 christos set_ccr_zero 546 1.1 christos bset r2h, @er1 547 1.1 christos test_cc_clear 548 1.1 christos mov @er1, r2l 549 1.1 christos test_h_gr8 31 r2l 550 1.1 christos 551 1.1 christos mov #5, r2h 552 1.1 christos set_ccr_zero 553 1.1 christos bset r2h, @er1 554 1.1 christos test_cc_clear 555 1.1 christos mov @er1, r2l 556 1.1 christos test_h_gr8 63 r2l 557 1.1 christos 558 1.1 christos mov #6, r2h 559 1.1 christos set_ccr_zero 560 1.1 christos bset r2h, @er1 561 1.1 christos test_cc_clear 562 1.1 christos mov @er1, r2l 563 1.1 christos test_h_gr8 127 r2l 564 1.1 christos 565 1.1 christos mov #7, r2h 566 1.1 christos set_ccr_zero 567 1.1 christos bset r2h, @er1 568 1.1 christos test_cc_clear 569 1.1 christos mov @er1, r2l 570 1.1 christos test_h_gr8 255 r2l 571 1.1 christos 572 1.1 christos .if (sim_cpu == h8300) 573 1.1 christos test_h_gr16 0x07ff r2 574 1.1 christos .else 575 1.1 christos test_h_gr32 0xa5a507ff er2 576 1.1 christos .endif 577 1.1 christos 578 1.1 christos bclr_rs8_ind: 579 1.1 christos mov #7, r2h 580 1.1 christos set_ccr_zero 581 1.1 christos bclr r2h, @er1 582 1.1 christos test_cc_clear 583 1.1 christos mov @er1, r2l 584 1.1 christos test_h_gr8 127 r2l 585 1.1 christos 586 1.1 christos mov #6, r2h 587 1.1 christos set_ccr_zero 588 1.1 christos bclr r2h, @er1 589 1.1 christos test_cc_clear 590 1.1 christos mov @er1, r2l 591 1.1 christos test_h_gr8 63 r2l 592 1.1 christos 593 1.1 christos mov #5, r2h 594 1.1 christos set_ccr_zero 595 1.1 christos bclr r2h, @er1 596 1.1 christos test_cc_clear 597 1.1 christos mov @er1, r2l 598 1.1 christos test_h_gr8 31 r2l 599 1.1 christos 600 1.1 christos mov #4, r2h 601 1.1 christos set_ccr_zero 602 1.1 christos bclr r2h, @er1 603 1.1 christos test_cc_clear 604 1.1 christos mov @er1, r2l 605 1.1 christos test_h_gr8 15 r2l 606 1.1 christos 607 1.1 christos mov #3, r2h 608 1.1 christos set_ccr_zero 609 1.1 christos bclr r2h, @er1 610 1.1 christos test_cc_clear 611 1.1 christos mov @er1, r2l 612 1.1 christos test_h_gr8 7 r2l 613 1.1 christos 614 1.1 christos mov #2, r2h 615 1.1 christos set_ccr_zero 616 1.1 christos bclr r2h, @er1 617 1.1 christos test_cc_clear 618 1.1 christos mov @er1, r2l 619 1.1 christos test_h_gr8 3 r2l 620 1.1 christos 621 1.1 christos mov #1, r2h 622 1.1 christos set_ccr_zero 623 1.1 christos bclr r2h, @er1 624 1.1 christos test_cc_clear 625 1.1 christos mov @er1, r2l 626 1.1 christos test_h_gr8 1 r2l 627 1.1 christos 628 1.1 christos mov #0, r2h 629 1.1 christos set_ccr_zero 630 1.1 christos bclr r2h, @er1 631 1.1 christos test_cc_clear 632 1.1 christos mov @er1, r2l 633 1.1 christos test_h_gr8 0 r2l 634 1.1 christos 635 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 636 1.1 christos .if (sim_cpu == h8300) 637 1.1 christos test_h_gr16 byte_dst r1 638 1.1 christos test_h_gr16 0x0000 r2 639 1.1 christos .else 640 1.1 christos test_h_gr32 byte_dst er1 641 1.1 christos test_h_gr32 0xa5a50000 er2 642 1.1 christos .endif 643 1.1 christos test_gr_a5a5 3 644 1.1 christos test_gr_a5a5 4 645 1.1 christos test_gr_a5a5 5 646 1.1 christos test_gr_a5a5 6 647 1.1 christos test_gr_a5a5 7 648 1.1 christos 649 1.1 christos .if (sim_cpu > h8300h) 650 1.1 christos bset_rs8_abs32: 651 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 652 1.1 christos 653 1.1 christos ;; bset rs8, @aa:32 654 1.1 christos mov #0, r2h 655 1.1 christos set_ccr_zero 656 1.1 christos bset r2h, @byte_dst:32 657 1.1 christos test_cc_clear 658 1.1 christos mov @byte_dst, r2l 659 1.1 christos test_h_gr8 1 r2l 660 1.1 christos 661 1.1 christos mov #1, r2h 662 1.1 christos set_ccr_zero 663 1.1 christos bset r2h, @byte_dst:32 664 1.1 christos test_cc_clear 665 1.1 christos mov @byte_dst, r2l 666 1.1 christos test_h_gr8 3 r2l 667 1.1 christos 668 1.1 christos mov #2, r2h 669 1.1 christos set_ccr_zero 670 1.1 christos bset r2h, @byte_dst:32 671 1.1 christos test_cc_clear 672 1.1 christos mov @byte_dst, r2l 673 1.1 christos test_h_gr8 7 r2l 674 1.1 christos 675 1.1 christos mov #3, r2h 676 1.1 christos set_ccr_zero 677 1.1 christos bset r2h, @byte_dst:32 678 1.1 christos test_cc_clear 679 1.1 christos mov @byte_dst, r2l 680 1.1 christos test_h_gr8 15 r2l 681 1.1 christos 682 1.1 christos mov #4, r2h 683 1.1 christos set_ccr_zero 684 1.1 christos bset r2h, @byte_dst:32 685 1.1 christos test_cc_clear 686 1.1 christos mov @byte_dst, r2l 687 1.1 christos test_h_gr8 31 r2l 688 1.1 christos 689 1.1 christos mov #5, r2h 690 1.1 christos set_ccr_zero 691 1.1 christos bset r2h, @byte_dst:32 692 1.1 christos test_cc_clear 693 1.1 christos mov @byte_dst, r2l 694 1.1 christos test_h_gr8 63 r2l 695 1.1 christos 696 1.1 christos mov #6, r2h 697 1.1 christos set_ccr_zero 698 1.1 christos bset r2h, @byte_dst:32 699 1.1 christos test_cc_clear 700 1.1 christos mov @byte_dst, r2l 701 1.1 christos test_h_gr8 127 r2l 702 1.1 christos 703 1.1 christos mov #7, r2h 704 1.1 christos set_ccr_zero 705 1.1 christos bset r2h, @byte_dst:32 706 1.1 christos test_cc_clear 707 1.1 christos mov @byte_dst, r2l 708 1.1 christos test_h_gr8 255 r2l 709 1.1 christos 710 1.1 christos .if (sim_cpu == h8300) 711 1.1 christos test_h_gr16 0x07ff r2 712 1.1 christos .else 713 1.1 christos test_h_gr32 0xa5a507ff er2 714 1.1 christos .endif 715 1.1 christos 716 1.1 christos bclr_rs8_abs32: 717 1.1 christos mov #7, r2h 718 1.1 christos set_ccr_zero 719 1.1 christos bclr r2h, @byte_dst:32 720 1.1 christos test_cc_clear 721 1.1 christos mov @byte_dst, r2l 722 1.1 christos test_h_gr8 127 r2l 723 1.1 christos 724 1.1 christos mov #6, r2h 725 1.1 christos set_ccr_zero 726 1.1 christos bclr r2h, @byte_dst:32 727 1.1 christos test_cc_clear 728 1.1 christos mov @byte_dst, r2l 729 1.1 christos test_h_gr8 63 r2l 730 1.1 christos 731 1.1 christos mov #5, r2h 732 1.1 christos set_ccr_zero 733 1.1 christos bclr r2h, @byte_dst:32 734 1.1 christos test_cc_clear 735 1.1 christos mov @byte_dst, r2l 736 1.1 christos test_h_gr8 31 r2l 737 1.1 christos 738 1.1 christos mov #4, r2h 739 1.1 christos set_ccr_zero 740 1.1 christos bclr r2h, @byte_dst:32 741 1.1 christos test_cc_clear 742 1.1 christos mov @byte_dst, r2l 743 1.1 christos test_h_gr8 15 r2l 744 1.1 christos 745 1.1 christos mov #3, r2h 746 1.1 christos set_ccr_zero 747 1.1 christos bclr r2h, @byte_dst:32 748 1.1 christos test_cc_clear 749 1.1 christos mov @byte_dst, r2l 750 1.1 christos test_h_gr8 7 r2l 751 1.1 christos 752 1.1 christos mov #2, r2h 753 1.1 christos set_ccr_zero 754 1.1 christos bclr r2h, @byte_dst:32 755 1.1 christos test_cc_clear 756 1.1 christos mov @byte_dst, r2l 757 1.1 christos test_h_gr8 3 r2l 758 1.1 christos 759 1.1 christos mov #1, r2h 760 1.1 christos set_ccr_zero 761 1.1 christos bclr r2h, @byte_dst:32 762 1.1 christos test_cc_clear 763 1.1 christos mov @byte_dst, r2l 764 1.1 christos test_h_gr8 1 r2l 765 1.1 christos 766 1.1 christos mov #0, r2h 767 1.1 christos set_ccr_zero 768 1.1 christos bclr r2h, @byte_dst:32 769 1.1 christos test_cc_clear 770 1.1 christos mov @byte_dst, r2l 771 1.1 christos test_h_gr8 0 r2l 772 1.1 christos 773 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 774 1.1 christos test_gr_a5a5 1 775 1.1 christos .if (sim_cpu == h8300) 776 1.1 christos test_h_gr16 0x0000 r2 777 1.1 christos .else 778 1.1 christos test_h_gr32 0xa5a50000 er2 779 1.1 christos .endif 780 1.1 christos test_gr_a5a5 3 781 1.1 christos test_gr_a5a5 4 782 1.1 christos test_gr_a5a5 5 783 1.1 christos test_gr_a5a5 6 784 1.1 christos test_gr_a5a5 7 785 1.1 christos .endif 786 1.1 christos .endif 787 1.1 christos 788 1.1 christos .if (sim_cpu == h8sx) 789 1.1 christos bset_eq_imm3_abs16: 790 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 791 1.1 christos 792 1.1 christos ;; bset/eq xx:3, rd8 793 1.1 christos mov #0, @byte_dst 794 1.1 christos set_ccr_zero 795 1.1 christos bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect. 796 1.1 christos test_cc_clear 797 1.1 christos mov @byte_dst, r1l 798 1.1 christos test_h_gr8 0 r1l 799 1.1 christos 800 1.1 christos set_ccr_zero 801 1.1 christos orc #4, ccr ; Set zero flag 802 1.1 christos bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed. 803 1.1 christos 804 1.1 christos test_neg_clear 805 1.1 christos test_zero_set 806 1.1 christos test_ovf_clear 807 1.1 christos test_carry_clear 808 1.1 christos 809 1.1 christos mov @byte_dst, r1l 810 1.1 christos test_h_gr8 1 r1l 811 1.1 christos 812 1.1 christos bclr_eq_imm3_abs32: 813 1.1 christos mov #1, @byte_dst 814 1.1 christos set_ccr_zero 815 1.1 christos bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect. 816 1.1 christos test_cc_clear 817 1.1 christos mov @byte_dst, r1l 818 1.1 christos test_h_gr8 1 r1l 819 1.1 christos 820 1.1 christos set_ccr_zero 821 1.1 christos orc #4, ccr ; Set zero flag 822 1.1 christos bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed. 823 1.1 christos test_neg_clear 824 1.1 christos test_zero_set 825 1.1 christos test_ovf_clear 826 1.1 christos test_carry_clear 827 1.1 christos mov @byte_dst, r1l 828 1.1 christos test_h_gr8 0 r1l 829 1.1 christos 830 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 831 1.1 christos test_h_gr32 0xa5a5a500 er1 832 1.1 christos test_gr_a5a5 2 833 1.1 christos test_gr_a5a5 3 834 1.1 christos test_gr_a5a5 4 835 1.1 christos test_gr_a5a5 5 836 1.1 christos test_gr_a5a5 6 837 1.1 christos test_gr_a5a5 7 838 1.1 christos 839 1.1 christos bset_ne_imm3_abs16: 840 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 841 1.1 christos 842 1.1 christos ;; bset/ne xx:3, aa:16 843 1.1 christos mov #0, @byte_dst 844 1.1 christos set_ccr_zero 845 1.1 christos orc #4, ccr ; Set zero flag 846 1.1 christos bset/ne #0, @byte_dst:16 ; Zero is set; should have no effect. 847 1.1 christos test_zero_set 848 1.1 christos test_neg_clear 849 1.1 christos test_ovf_clear 850 1.1 christos test_carry_clear 851 1.1 christos mov @byte_dst, r1l 852 1.1 christos test_h_gr8 0 r1l 853 1.1 christos 854 1.1 christos set_ccr_zero 855 1.1 christos bset/ne #0, @byte_dst:16 ; Zero is clear: operation should succeed. 856 1.1 christos test_cc_clear 857 1.1 christos mov @byte_dst, r1l 858 1.1 christos test_h_gr8 1 r1l 859 1.1 christos 860 1.1 christos bclr_ne_imm3_abs32: 861 1.1 christos mov #1, @byte_dst 862 1.1 christos set_ccr_zero 863 1.1 christos orc #4, ccr ; Set zero flag 864 1.1 christos ;; bclr/ne xx:3, aa:16 865 1.1 christos bclr/ne #0, @byte_dst:32 ; Zero is set, should have no effect. 866 1.1 christos test_neg_clear 867 1.1 christos test_zero_set 868 1.1 christos test_ovf_clear 869 1.1 christos test_carry_clear 870 1.1 christos mov @byte_dst, r1l 871 1.1 christos test_h_gr8 1 r1l 872 1.1 christos 873 1.1 christos set_ccr_zero 874 1.1 christos bclr/ne #0, @byte_dst:32 ; Zero is clear: operation should succeed. 875 1.1 christos test_cc_clear 876 1.1 christos mov @byte_dst, r1l 877 1.1 christos test_h_gr8 0 r1l 878 1.1 christos 879 1.1 christos test_gr_a5a5 0 ; Make sure other general regs not disturbed 880 1.1 christos test_h_gr32 0xa5a5a500 er1 881 1.1 christos test_gr_a5a5 2 882 1.1 christos test_gr_a5a5 3 883 1.1 christos test_gr_a5a5 4 884 1.1 christos test_gr_a5a5 5 885 1.1 christos test_gr_a5a5 6 886 1.1 christos test_gr_a5a5 7 887 1.1 christos .endif 888 1.1 christos 889 1.1 christos pass 890 1.1 christos exit 0 891
Indexes created Tue Sep 15 00:24:42 UTC 2026