rotxr.s revision 1.1
1 # Hitachi H8 testcase 'rotxr' 2 # mach(): h8300s h8sx 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .data 16 byte_dest: .byte 0xa5 17 .align 2 18 word_dest: .word 0xa5a5 19 .align 4 20 long_dest: .long 0xa5a5a5a5 21 22 .text 23 24 rotxr_b_reg8_1: 25 set_grs_a5a5 ; Fill all general regs with a fixed pattern 26 set_ccr_zero 27 28 rotxr.b r0l ; shift right arithmetic by one 29 ;;; .word 0x1308 30 31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 32 test_zero_clear 33 test_ovf_clear 34 test_neg_clear 35 36 test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 37 .if (sim_cpu) 38 test_h_gr32 0xa5a5a552 er0 39 .endif 40 test_gr_a5a5 1 ; Make sure other general regs not disturbed 41 test_gr_a5a5 2 42 test_gr_a5a5 3 43 test_gr_a5a5 4 44 test_gr_a5a5 5 45 test_gr_a5a5 6 46 test_gr_a5a5 7 47 48 .if (sim_cpu == h8sx) 49 rotxr_b_ind_1: 50 set_grs_a5a5 ; Fill all general regs with a fixed pattern 51 set_ccr_zero 52 53 mov #byte_dest, er0 54 rotxr.b @er0 ; shift right arithmetic by one, indirect 55 ;;; .word 0x7d00 56 ;;; .word 0x1300 57 58 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 59 test_zero_clear 60 test_ovf_clear 61 test_neg_clear 62 63 test_h_gr32 byte_dest er0 64 test_gr_a5a5 1 ; Make sure other general regs not disturbed 65 test_gr_a5a5 2 66 test_gr_a5a5 3 67 test_gr_a5a5 4 68 test_gr_a5a5 5 69 test_gr_a5a5 6 70 test_gr_a5a5 7 71 ; 1010 0101 -> 0101 0010 72 cmp.b #0x52, @byte_dest 73 beq .Lbind1 74 fail 75 .Lbind1: 76 mov #0xa5a5a5a5, @byte_dest 77 78 rotxr_b_postinc_1: 79 set_grs_a5a5 ; Fill all general regs with a fixed pattern 80 set_ccr_zero 81 82 mov #byte_dest, er0 83 rotxr.b @er0+ ; shift right arithmetic by one, postinc 84 ;;; .word 0x0174 85 ;;; .word 0x6c08 86 ;;; .word 0x1300 87 88 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 89 test_zero_clear 90 test_ovf_clear 91 test_neg_clear 92 93 test_h_gr32 byte_dest+1 er0 94 test_gr_a5a5 1 ; Make sure other general regs not disturbed 95 test_gr_a5a5 2 96 test_gr_a5a5 3 97 test_gr_a5a5 4 98 test_gr_a5a5 5 99 test_gr_a5a5 6 100 test_gr_a5a5 7 101 ; 1010 0101 -> 0101 0010 102 cmp.b #0x52, @byte_dest 103 beq .Lbpostinc1 104 fail 105 .Lbpostinc1: 106 mov #0xa5a5a5a5, @byte_dest 107 108 rotxr_b_postdec_1: 109 set_grs_a5a5 ; Fill all general regs with a fixed pattern 110 set_ccr_zero 111 112 mov #byte_dest, er0 113 rotxr.b @er0- ; shift right arithmetic by one, postdec 114 ;;; .word 0x0176 115 ;;; .word 0x6c08 116 ;;; .word 0x1300 117 118 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 119 test_zero_clear 120 test_ovf_clear 121 test_neg_clear 122 123 test_h_gr32 byte_dest-1 er0 124 test_gr_a5a5 1 ; Make sure other general regs not disturbed 125 test_gr_a5a5 2 126 test_gr_a5a5 3 127 test_gr_a5a5 4 128 test_gr_a5a5 5 129 test_gr_a5a5 6 130 test_gr_a5a5 7 131 ; 1010 0101 -> 0101 0010 132 cmp.b #0x52, @byte_dest 133 beq .Lbpostdec1 134 fail 135 .Lbpostdec1: 136 mov #0xa5a5a5a5, @byte_dest 137 138 rotxr_b_preinc_1: 139 set_grs_a5a5 ; Fill all general regs with a fixed pattern 140 set_ccr_zero 141 142 mov #byte_dest-1, er0 143 rotxr.b @+er0 ; shift right arithmetic by one, preinc 144 ;;; .word 0x0175 145 ;;; .word 0x6c08 146 ;;; .word 0x1300 147 148 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 149 test_zero_clear 150 test_ovf_clear 151 test_neg_clear 152 153 test_h_gr32 byte_dest er0 154 test_gr_a5a5 1 ; Make sure other general regs not disturbed 155 test_gr_a5a5 2 156 test_gr_a5a5 3 157 test_gr_a5a5 4 158 test_gr_a5a5 5 159 test_gr_a5a5 6 160 test_gr_a5a5 7 161 ; 1010 0101 -> 0101 0010 162 cmp.b #0x52, @byte_dest 163 beq .Lbpreinc1 164 fail 165 .Lbpreinc1: 166 mov #0xa5a5a5a5, @byte_dest 167 168 rotxr_b_predec_1: 169 set_grs_a5a5 ; Fill all general regs with a fixed pattern 170 set_ccr_zero 171 172 mov #byte_dest+1, er0 173 rotxr.b @-er0 ; shift right arithmetic by one, predec 174 ;;; .word 0x0177 175 ;;; .word 0x6c08 176 ;;; .word 0x1300 177 178 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 179 test_zero_clear 180 test_ovf_clear 181 test_neg_clear 182 183 test_h_gr32 byte_dest er0 184 test_gr_a5a5 1 ; Make sure other general regs not disturbed 185 test_gr_a5a5 2 186 test_gr_a5a5 3 187 test_gr_a5a5 4 188 test_gr_a5a5 5 189 test_gr_a5a5 6 190 test_gr_a5a5 7 191 ; 1010 0101 -> 0101 0010 192 cmp.b #0x52, @byte_dest 193 beq .Lbpredec1 194 fail 195 .Lbpredec1: 196 mov #0xa5a5a5a5, @byte_dest 197 198 rotxr_b_disp2_1: 199 set_grs_a5a5 ; Fill all general regs with a fixed pattern 200 set_ccr_zero 201 202 mov #byte_dest-2, er0 203 rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2 204 ;;; .word 0x0176 205 ;;; .word 0x6808 206 ;;; .word 0x1300 207 208 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 209 test_zero_clear 210 test_ovf_clear 211 test_neg_clear 212 213 test_h_gr32 byte_dest-2 er0 214 test_gr_a5a5 1 ; Make sure other general regs not disturbed 215 test_gr_a5a5 2 216 test_gr_a5a5 3 217 test_gr_a5a5 4 218 test_gr_a5a5 5 219 test_gr_a5a5 6 220 test_gr_a5a5 7 221 ; 1010 0101 -> 0101 0010 222 cmp.b #0x52, @byte_dest 223 beq .Lbdisp21 224 fail 225 .Lbdisp21: 226 mov #0xa5a5a5a5, @byte_dest 227 228 rotxr_b_disp16_1: 229 set_grs_a5a5 ; Fill all general regs with a fixed pattern 230 set_ccr_zero 231 232 mov #byte_dest-44, er0 233 rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16 234 ;;; .word 0x0174 235 ;;; .word 0x6e08 236 ;;; .word 44 237 ;;; .word 0x1300 238 239 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 240 test_zero_clear 241 test_ovf_clear 242 test_neg_clear 243 244 test_h_gr32 byte_dest-44 er0 245 test_gr_a5a5 1 ; Make sure other general regs not disturbed 246 test_gr_a5a5 2 247 test_gr_a5a5 3 248 test_gr_a5a5 4 249 test_gr_a5a5 5 250 test_gr_a5a5 6 251 test_gr_a5a5 7 252 ; 1010 0101 -> 0101 0010 253 cmp.b #0x52, @byte_dest 254 beq .Lbdisp161 255 fail 256 .Lbdisp161: 257 mov #0xa5a5a5a5, @byte_dest 258 259 rotxr_b_disp32_1: 260 set_grs_a5a5 ; Fill all general regs with a fixed pattern 261 set_ccr_zero 262 263 mov #byte_dest-666, er0 264 rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32 265 ;;; .word 0x7884 266 ;;; .word 0x6a28 267 ;;; .long 666 268 ;;; .word 0x1300 269 270 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 271 test_zero_clear 272 test_ovf_clear 273 test_neg_clear 274 275 test_h_gr32 byte_dest-666 er0 276 test_gr_a5a5 1 ; Make sure other general regs not disturbed 277 test_gr_a5a5 2 278 test_gr_a5a5 3 279 test_gr_a5a5 4 280 test_gr_a5a5 5 281 test_gr_a5a5 6 282 test_gr_a5a5 7 283 ; 1010 0101 -> 0101 0010 284 cmp.b #0x52, @byte_dest 285 beq .Lbdisp321 286 fail 287 .Lbdisp321: 288 mov #0xa5a5a5a5, @byte_dest 289 290 rotxr_b_abs16_1: 291 set_grs_a5a5 ; Fill all general regs with a fixed pattern 292 set_ccr_zero 293 294 rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16 295 ;;; .word 0x6a18 296 ;;; .word byte_dest 297 ;;; .word 0x1300 298 299 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 300 test_zero_clear 301 test_ovf_clear 302 test_neg_clear 303 304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 305 test_gr_a5a5 2 306 test_gr_a5a5 2 307 test_gr_a5a5 3 308 test_gr_a5a5 4 309 test_gr_a5a5 5 310 test_gr_a5a5 6 311 test_gr_a5a5 7 312 ; 1010 0101 -> 0101 0010 313 cmp.b #0x52, @byte_dest 314 beq .Lbabs161 315 fail 316 .Lbabs161: 317 mov #0xa5a5a5a5, @byte_dest 318 319 rotxr_b_abs32_1: 320 set_grs_a5a5 ; Fill all general regs with a fixed pattern 321 set_ccr_zero 322 323 rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32 324 ;;; .word 0x6a38 325 ;;; .long byte_dest 326 ;;; .word 0x1300 327 328 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 329 test_zero_clear 330 test_ovf_clear 331 test_neg_clear 332 333 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 334 test_gr_a5a5 2 335 test_gr_a5a5 2 336 test_gr_a5a5 3 337 test_gr_a5a5 4 338 test_gr_a5a5 5 339 test_gr_a5a5 6 340 test_gr_a5a5 7 341 ; 1010 0101 -> 0101 0010 342 cmp.b #0x52, @byte_dest 343 beq .Lbabs321 344 fail 345 .Lbabs321: 346 mov #0xa5a5a5a5, @byte_dest 347 .endif 348 349 rotxr_b_reg8_2: 350 set_grs_a5a5 ; Fill all general regs with a fixed pattern 351 set_ccr_zero 352 353 rotxr.b #2, r0l ; shift right arithmetic by two 354 ;;; .word 0x1348 355 356 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 357 test_zero_clear 358 test_ovf_clear 359 test_neg_set 360 361 test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001 362 .if (sim_cpu) 363 test_h_gr32 0xa5a5a5a9 er0 364 .endif 365 test_gr_a5a5 1 ; Make sure other general regs not disturbed 366 test_gr_a5a5 2 367 test_gr_a5a5 3 368 test_gr_a5a5 4 369 test_gr_a5a5 5 370 test_gr_a5a5 6 371 test_gr_a5a5 7 372 373 .if (sim_cpu == h8sx) 374 rotxr_b_ind_2: 375 set_grs_a5a5 ; Fill all general regs with a fixed pattern 376 set_ccr_zero 377 378 mov #byte_dest, er0 379 rotxr.b #2, @er0 ; shift right arithmetic by two, indirect 380 ;;; .word 0x7d00 381 ;;; .word 0x1340 382 383 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 384 test_zero_clear 385 test_ovf_clear 386 test_neg_set 387 388 test_h_gr32 byte_dest er0 389 test_gr_a5a5 1 ; Make sure other general regs not disturbed 390 test_gr_a5a5 2 391 test_gr_a5a5 3 392 test_gr_a5a5 4 393 test_gr_a5a5 5 394 test_gr_a5a5 6 395 test_gr_a5a5 7 396 ; 1010 0101 -> 1010 1001 397 cmp.b #0xa9, @byte_dest 398 beq .Lbind2 399 fail 400 .Lbind2: 401 mov #0xa5a5a5a5, @byte_dest 402 403 rotxr_b_postinc_2: 404 set_grs_a5a5 ; Fill all general regs with a fixed pattern 405 set_ccr_zero 406 407 mov #byte_dest, er0 408 rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc 409 ;;; .word 0x0174 410 ;;; .word 0x6c08 411 ;;; .word 0x1340 412 413 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 414 test_zero_clear 415 test_ovf_clear 416 test_neg_set 417 418 test_h_gr32 byte_dest+1 er0 419 test_gr_a5a5 1 ; Make sure other general regs not disturbed 420 test_gr_a5a5 2 421 test_gr_a5a5 3 422 test_gr_a5a5 4 423 test_gr_a5a5 5 424 test_gr_a5a5 6 425 test_gr_a5a5 7 426 ; 1010 0101 -> 1010 1001 427 cmp.b #0xa9, @byte_dest 428 beq .Lbpostinc2 429 fail 430 .Lbpostinc2: 431 mov #0xa5a5a5a5, @byte_dest 432 433 rotxr_b_postdec_2: 434 set_grs_a5a5 ; Fill all general regs with a fixed pattern 435 set_ccr_zero 436 437 mov #byte_dest, er0 438 rotxr.b #2, @er0- ; shift right arithmetic by two, postdec 439 ;;; .word 0x0176 440 ;;; .word 0x6c08 441 ;;; .word 0x1340 442 443 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 444 test_zero_clear 445 test_ovf_clear 446 test_neg_set 447 448 test_h_gr32 byte_dest-1 er0 449 test_gr_a5a5 1 ; Make sure other general regs not disturbed 450 test_gr_a5a5 2 451 test_gr_a5a5 3 452 test_gr_a5a5 4 453 test_gr_a5a5 5 454 test_gr_a5a5 6 455 test_gr_a5a5 7 456 ; 1010 0101 -> 1010 1001 457 cmp.b #0xa9, @byte_dest 458 beq .Lbpostdec2 459 fail 460 .Lbpostdec2: 461 mov #0xa5a5a5a5, @byte_dest 462 463 rotxr_b_preinc_2: 464 set_grs_a5a5 ; Fill all general regs with a fixed pattern 465 set_ccr_zero 466 467 mov #byte_dest-1, er0 468 rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc 469 ;;; .word 0x0175 470 ;;; .word 0x6c08 471 ;;; .word 0x1340 472 473 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 474 test_zero_clear 475 test_ovf_clear 476 test_neg_set 477 478 test_h_gr32 byte_dest er0 479 test_gr_a5a5 1 ; Make sure other general regs not disturbed 480 test_gr_a5a5 2 481 test_gr_a5a5 3 482 test_gr_a5a5 4 483 test_gr_a5a5 5 484 test_gr_a5a5 6 485 test_gr_a5a5 7 486 ; 1010 0101 -> 1010 1001 487 cmp.b #0xa9, @byte_dest 488 beq .Lbpreinc2 489 fail 490 .Lbpreinc2: 491 mov #0xa5a5a5a5, @byte_dest 492 493 rotxr_b_predec_2: 494 set_grs_a5a5 ; Fill all general regs with a fixed pattern 495 set_ccr_zero 496 497 mov #byte_dest+1, er0 498 rotxr.b #2, @-er0 ; shift right arithmetic by two, predec 499 ;;; .word 0x0177 500 ;;; .word 0x6c08 501 ;;; .word 0x1340 502 503 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 504 test_zero_clear 505 test_ovf_clear 506 test_neg_set 507 508 test_h_gr32 byte_dest er0 509 test_gr_a5a5 1 ; Make sure other general regs not disturbed 510 test_gr_a5a5 2 511 test_gr_a5a5 3 512 test_gr_a5a5 4 513 test_gr_a5a5 5 514 test_gr_a5a5 6 515 test_gr_a5a5 7 516 ; 1010 0101 -> 1010 1001 517 cmp.b #0xa9, @byte_dest 518 beq .Lbpredec2 519 fail 520 .Lbpredec2: 521 mov #0xa5a5a5a5, @byte_dest 522 523 rotxr_b_disp2_2: 524 set_grs_a5a5 ; Fill all general regs with a fixed pattern 525 set_ccr_zero 526 527 mov #byte_dest-2, er0 528 rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2 529 ;;; .word 0x0176 530 ;;; .word 0x6808 531 ;;; .word 0x1340 532 533 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 534 test_zero_clear 535 test_ovf_clear 536 test_neg_set 537 538 test_h_gr32 byte_dest-2 er0 539 test_gr_a5a5 1 ; Make sure other general regs not disturbed 540 test_gr_a5a5 2 541 test_gr_a5a5 3 542 test_gr_a5a5 4 543 test_gr_a5a5 5 544 test_gr_a5a5 6 545 test_gr_a5a5 7 546 ; 1010 0101 -> 1010 1001 547 cmp.b #0xa9, @byte_dest 548 beq .Lbdisp22 549 fail 550 .Lbdisp22: 551 mov #0xa5a5a5a5, @byte_dest 552 553 rotxr_b_disp16_2: 554 set_grs_a5a5 ; Fill all general regs with a fixed pattern 555 set_ccr_zero 556 557 mov #byte_dest-44, er0 558 rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16 559 ;;; .word 0x0174 560 ;;; .word 0x6e08 561 ;;; .word 44 562 ;;; .word 0x1340 563 564 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 565 test_zero_clear 566 test_ovf_clear 567 test_neg_set 568 569 test_h_gr32 byte_dest-44 er0 570 test_gr_a5a5 1 ; Make sure other general regs not disturbed 571 test_gr_a5a5 2 572 test_gr_a5a5 3 573 test_gr_a5a5 4 574 test_gr_a5a5 5 575 test_gr_a5a5 6 576 test_gr_a5a5 7 577 ; 1010 0101 -> 1010 1001 578 cmp.b #0xa9, @byte_dest 579 beq .Lbdisp162 580 fail 581 .Lbdisp162: 582 mov #0xa5a5a5a5, @byte_dest 583 584 rotxr_b_disp32_2: 585 set_grs_a5a5 ; Fill all general regs with a fixed pattern 586 set_ccr_zero 587 588 mov #byte_dest-666, er0 589 rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32 590 ;;; .word 0x7884 591 ;;; .word 0x6a28 592 ;;; .long 666 593 ;;; .word 0x1340 594 595 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 596 test_zero_clear 597 test_ovf_clear 598 test_neg_set 599 600 test_h_gr32 byte_dest-666 er0 601 test_gr_a5a5 1 ; Make sure other general regs not disturbed 602 test_gr_a5a5 2 603 test_gr_a5a5 3 604 test_gr_a5a5 4 605 test_gr_a5a5 5 606 test_gr_a5a5 6 607 test_gr_a5a5 7 608 ; 1010 0101 -> 1010 1001 609 cmp.b #0xa9, @byte_dest 610 beq .Lbdisp322 611 fail 612 .Lbdisp322: 613 mov #0xa5a5a5a5, @byte_dest 614 615 rotxr_b_abs16_2: 616 set_grs_a5a5 ; Fill all general regs with a fixed pattern 617 set_ccr_zero 618 619 rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16 620 ;;; .word 0x6a18 621 ;;; .word byte_dest 622 ;;; .word 0x1340 623 624 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 625 test_zero_clear 626 test_ovf_clear 627 test_neg_set 628 629 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 630 test_gr_a5a5 2 631 test_gr_a5a5 2 632 test_gr_a5a5 3 633 test_gr_a5a5 4 634 test_gr_a5a5 5 635 test_gr_a5a5 6 636 test_gr_a5a5 7 637 ; 1010 0101 -> 1010 1001 638 cmp.b #0xa9, @byte_dest 639 beq .Lbabs162 640 fail 641 .Lbabs162: 642 mov #0xa5a5a5a5, @byte_dest 643 644 rotxr_b_abs32_2: 645 set_grs_a5a5 ; Fill all general regs with a fixed pattern 646 set_ccr_zero 647 648 rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32 649 ;;; .word 0x6a38 650 ;;; .long byte_dest 651 ;;; .word 0x1340 652 653 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 654 test_zero_clear 655 test_ovf_clear 656 test_neg_set 657 658 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 659 test_gr_a5a5 2 660 test_gr_a5a5 2 661 test_gr_a5a5 3 662 test_gr_a5a5 4 663 test_gr_a5a5 5 664 test_gr_a5a5 6 665 test_gr_a5a5 7 666 ; 1010 0101 -> 1010 1001 667 cmp.b #0xa9, @byte_dest 668 beq .Lbabs322 669 fail 670 .Lbabs322: 671 mov #0xa5a5a5a5, @byte_dest 672 .endif 673 674 .if (sim_cpu) ; Not available in h8300 mode 675 rotxr_w_reg16_1: 676 set_grs_a5a5 ; Fill all general regs with a fixed pattern 677 set_ccr_zero 678 679 rotxr.w r0 ; shift right arithmetic by one 680 ;;; .word 0x1310 681 682 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 683 test_zero_clear 684 test_ovf_clear 685 test_neg_clear 686 687 test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 688 test_h_gr32 0xa5a552d2 er0 689 690 test_gr_a5a5 1 ; Make sure other general regs not disturbed 691 test_gr_a5a5 2 692 test_gr_a5a5 3 693 test_gr_a5a5 4 694 test_gr_a5a5 5 695 test_gr_a5a5 6 696 test_gr_a5a5 7 697 698 .if (sim_cpu == h8sx) 699 rotxr_w_ind_1: 700 set_grs_a5a5 ; Fill all general regs with a fixed pattern 701 set_ccr_zero 702 703 mov #word_dest, er0 704 rotxr.w @er0 ; shift right arithmetic by one, indirect 705 ;;; .word 0x7d80 706 ;;; .word 0x1310 707 708 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 709 test_zero_clear 710 test_ovf_clear 711 test_neg_clear 712 713 test_h_gr32 word_dest er0 714 test_gr_a5a5 1 ; Make sure other general regs not disturbed 715 test_gr_a5a5 2 716 test_gr_a5a5 3 717 test_gr_a5a5 4 718 test_gr_a5a5 5 719 test_gr_a5a5 6 720 test_gr_a5a5 7 721 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 722 cmp.w #0x52d2, @word_dest 723 beq .Lwind1 724 fail 725 .Lwind1: 726 mov #0xa5a5a5a5, @word_dest 727 728 rotxr_w_postinc_1: 729 set_grs_a5a5 ; Fill all general regs with a fixed pattern 730 set_ccr_zero 731 732 mov #word_dest, er0 733 rotxr.w @er0+ ; shift right arithmetic by one, postinc 734 ;;; .word 0x0154 735 ;;; .word 0x6d08 736 ;;; .word 0x1310 737 738 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 739 test_zero_clear 740 test_ovf_clear 741 test_neg_clear 742 743 test_h_gr32 word_dest+2 er0 744 test_gr_a5a5 1 ; Make sure other general regs not disturbed 745 test_gr_a5a5 2 746 test_gr_a5a5 3 747 test_gr_a5a5 4 748 test_gr_a5a5 5 749 test_gr_a5a5 6 750 test_gr_a5a5 7 751 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 752 cmp.w #0x52d2, @word_dest 753 beq .Lwpostinc1 754 fail 755 .Lwpostinc1: 756 mov #0xa5a5a5a5, @word_dest 757 758 rotxr_w_postdec_1: 759 set_grs_a5a5 ; Fill all general regs with a fixed pattern 760 set_ccr_zero 761 762 mov #word_dest, er0 763 rotxr.w @er0- ; shift right arithmetic by one, postdec 764 ;;; .word 0x0156 765 ;;; .word 0x6d08 766 ;;; .word 0x1310 767 768 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 769 test_zero_clear 770 test_ovf_clear 771 test_neg_clear 772 773 test_h_gr32 word_dest-2 er0 774 test_gr_a5a5 1 ; Make sure other general regs not disturbed 775 test_gr_a5a5 2 776 test_gr_a5a5 3 777 test_gr_a5a5 4 778 test_gr_a5a5 5 779 test_gr_a5a5 6 780 test_gr_a5a5 7 781 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 782 cmp.w #0x52d2, @word_dest 783 beq .Lwpostdec1 784 fail 785 .Lwpostdec1: 786 mov #0xa5a5a5a5, @word_dest 787 788 rotxr_w_preinc_1: 789 set_grs_a5a5 ; Fill all general regs with a fixed pattern 790 set_ccr_zero 791 792 mov #word_dest-2, er0 793 rotxr.w @+er0 ; shift right arithmetic by one, preinc 794 ;;; .word 0x0155 795 ;;; .word 0x6d08 796 ;;; .word 0x1310 797 798 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 799 test_zero_clear 800 test_ovf_clear 801 test_neg_clear 802 803 test_h_gr32 word_dest er0 804 test_gr_a5a5 1 ; Make sure other general regs not disturbed 805 test_gr_a5a5 2 806 test_gr_a5a5 3 807 test_gr_a5a5 4 808 test_gr_a5a5 5 809 test_gr_a5a5 6 810 test_gr_a5a5 7 811 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 812 cmp.w #0x52d2, @word_dest 813 beq .Lwpreinc1 814 fail 815 .Lwpreinc1: 816 mov #0xa5a5a5a5, @word_dest 817 818 rotxr_w_predec_1: 819 set_grs_a5a5 ; Fill all general regs with a fixed pattern 820 set_ccr_zero 821 822 mov #word_dest+2, er0 823 rotxr.w @-er0 ; shift right arithmetic by one, predec 824 ;;; .word 0x0157 825 ;;; .word 0x6d08 826 ;;; .word 0x1310 827 828 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 829 test_zero_clear 830 test_ovf_clear 831 test_neg_clear 832 833 test_h_gr32 word_dest er0 834 test_gr_a5a5 1 ; Make sure other general regs not disturbed 835 test_gr_a5a5 2 836 test_gr_a5a5 3 837 test_gr_a5a5 4 838 test_gr_a5a5 5 839 test_gr_a5a5 6 840 test_gr_a5a5 7 841 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 842 cmp.w #0x52d2, @word_dest 843 beq .Lwpredec1 844 fail 845 .Lwpredec1: 846 mov #0xa5a5a5a5, @word_dest 847 848 rotxr_w_disp2_1: 849 set_grs_a5a5 ; Fill all general regs with a fixed pattern 850 set_ccr_zero 851 852 mov #word_dest-4, er0 853 rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2 854 ;;; .word 0x0156 855 ;;; .word 0xa908 856 ;;; .word 0x1310 857 858 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 859 test_zero_clear 860 test_ovf_clear 861 test_neg_clear 862 863 test_h_gr32 word_dest-4 er0 864 test_gr_a5a5 1 ; Make sure other general regs not disturbed 865 test_gr_a5a5 2 866 test_gr_a5a5 3 867 test_gr_a5a5 4 868 test_gr_a5a5 5 869 test_gr_a5a5 6 870 test_gr_a5a5 7 871 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 872 cmp.w #0x52d2, @word_dest 873 beq .Lwdisp21 874 fail 875 .Lwdisp21: 876 mov #0xa5a5a5a5, @word_dest 877 878 rotxr_w_disp16_1: 879 set_grs_a5a5 ; Fill all general regs with a fixed pattern 880 set_ccr_zero 881 882 mov #word_dest-44, er0 883 rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16 884 ;;; .word 0x0154 885 ;;; .word 0x6f08 886 ;;; .word 44 887 ;;; .word 0x1310 888 889 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 890 test_zero_clear 891 test_ovf_clear 892 test_neg_clear 893 894 test_h_gr32 word_dest-44 er0 895 test_gr_a5a5 1 ; Make sure other general regs not disturbed 896 test_gr_a5a5 2 897 test_gr_a5a5 3 898 test_gr_a5a5 4 899 test_gr_a5a5 5 900 test_gr_a5a5 6 901 test_gr_a5a5 7 902 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 903 cmp.w #0x52d2, @word_dest 904 beq .Lwdisp161 905 fail 906 .Lwdisp161: 907 mov #0xa5a5a5a5, @word_dest 908 909 rotxr_w_disp32_1: 910 set_grs_a5a5 ; Fill all general regs with a fixed pattern 911 set_ccr_zero 912 913 mov #word_dest-666, er0 914 rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32 915 ;;; .word 0x7884 916 ;;; .word 0x6b28 917 ;;; .long 666 918 ;;; .word 0x1310 919 920 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 921 test_zero_clear 922 test_ovf_clear 923 test_neg_clear 924 925 test_h_gr32 word_dest-666 er0 926 test_gr_a5a5 1 ; Make sure other general regs not disturbed 927 test_gr_a5a5 2 928 test_gr_a5a5 3 929 test_gr_a5a5 4 930 test_gr_a5a5 5 931 test_gr_a5a5 6 932 test_gr_a5a5 7 933 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 934 cmp.w #0x52d2, @word_dest 935 beq .Lwdisp321 936 fail 937 .Lwdisp321: 938 mov #0xa5a5a5a5, @word_dest 939 940 rotxr_w_abs16_1: 941 set_grs_a5a5 ; Fill all general regs with a fixed pattern 942 set_ccr_zero 943 944 rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16 945 ;;; .word 0x6b18 946 ;;; .word word_dest 947 ;;; .word 0x1310 948 949 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 950 test_zero_clear 951 test_ovf_clear 952 test_neg_clear 953 954 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 955 test_gr_a5a5 1 956 test_gr_a5a5 2 957 test_gr_a5a5 3 958 test_gr_a5a5 4 959 test_gr_a5a5 5 960 test_gr_a5a5 6 961 test_gr_a5a5 7 962 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 963 cmp.w #0x52d2, @word_dest 964 beq .Lwabs161 965 fail 966 .Lwabs161: 967 mov #0xa5a5a5a5, @word_dest 968 969 rotxr_w_abs32_1: 970 set_grs_a5a5 ; Fill all general regs with a fixed pattern 971 set_ccr_zero 972 973 rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32 974 ;;; .word 0x6b38 975 ;;; .long word_dest 976 ;;; .word 0x1310 977 978 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 979 test_zero_clear 980 test_ovf_clear 981 test_neg_clear 982 983 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 984 test_gr_a5a5 1 985 test_gr_a5a5 2 986 test_gr_a5a5 3 987 test_gr_a5a5 4 988 test_gr_a5a5 5 989 test_gr_a5a5 6 990 test_gr_a5a5 7 991 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 992 cmp.w #0x52d2, @word_dest 993 beq .Lwabs321 994 fail 995 .Lwabs321: 996 mov #0xa5a5a5a5, @word_dest 997 .endif 998 999 rotxr_w_reg16_2: 1000 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1001 set_ccr_zero 1002 1003 rotxr.w #2, r0 ; shift right arithmetic by two 1004 ;;; .word 0x1350 1005 1006 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1007 test_zero_clear 1008 test_ovf_clear 1009 test_neg_set 1010 1011 test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1012 test_h_gr32 0xa5a5a969 er0 1013 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1014 test_gr_a5a5 2 1015 test_gr_a5a5 3 1016 test_gr_a5a5 4 1017 test_gr_a5a5 5 1018 test_gr_a5a5 6 1019 test_gr_a5a5 7 1020 1021 .if (sim_cpu == h8sx) 1022 rotxr_w_ind_2: 1023 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1024 set_ccr_zero 1025 1026 mov #word_dest, er0 1027 rotxr.w #2, @er0 ; shift right arithmetic by two, indirect 1028 ;;; .word 0x7d80 1029 ;;; .word 0x1350 1030 1031 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1032 test_zero_clear 1033 test_ovf_clear 1034 test_neg_set 1035 1036 test_h_gr32 word_dest er0 1037 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1038 test_gr_a5a5 2 1039 test_gr_a5a5 3 1040 test_gr_a5a5 4 1041 test_gr_a5a5 5 1042 test_gr_a5a5 6 1043 test_gr_a5a5 7 1044 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1045 cmp.w #0xa969, @word_dest 1046 beq .Lwind2 1047 fail 1048 .Lwind2: 1049 mov #0xa5a5a5a5, @word_dest 1050 1051 rotxr_w_postinc_2: 1052 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1053 set_ccr_zero 1054 1055 mov #word_dest, er0 1056 rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc 1057 ;;; .word 0x0154 1058 ;;; .word 0x6d08 1059 ;;; .word 0x1350 1060 1061 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1062 test_zero_clear 1063 test_ovf_clear 1064 test_neg_set 1065 1066 test_h_gr32 word_dest+2 er0 1067 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1068 test_gr_a5a5 2 1069 test_gr_a5a5 3 1070 test_gr_a5a5 4 1071 test_gr_a5a5 5 1072 test_gr_a5a5 6 1073 test_gr_a5a5 7 1074 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1075 cmp.w #0xa969, @word_dest 1076 beq .Lwpostinc2 1077 fail 1078 .Lwpostinc2: 1079 mov #0xa5a5a5a5, @word_dest 1080 1081 rotxr_w_postdec_2: 1082 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1083 set_ccr_zero 1084 1085 mov #word_dest, er0 1086 rotxr.w #2, @er0- ; shift right arithmetic by two, postdec 1087 ;;; .word 0x0156 1088 ;;; .word 0x6d08 1089 ;;; .word 0x1350 1090 1091 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1092 test_zero_clear 1093 test_ovf_clear 1094 test_neg_set 1095 1096 test_h_gr32 word_dest-2 er0 1097 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1098 test_gr_a5a5 2 1099 test_gr_a5a5 3 1100 test_gr_a5a5 4 1101 test_gr_a5a5 5 1102 test_gr_a5a5 6 1103 test_gr_a5a5 7 1104 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1105 cmp.w #0xa969, @word_dest 1106 beq .Lwpostdec2 1107 fail 1108 .Lwpostdec2: 1109 mov #0xa5a5a5a5, @word_dest 1110 1111 rotxr_w_preinc_2: 1112 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1113 set_ccr_zero 1114 1115 mov #word_dest-2, er0 1116 rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc 1117 ;;; .word 0x0155 1118 ;;; .word 0x6d08 1119 ;;; .word 0x1350 1120 1121 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1122 test_zero_clear 1123 test_ovf_clear 1124 test_neg_set 1125 1126 test_h_gr32 word_dest er0 1127 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1128 test_gr_a5a5 2 1129 test_gr_a5a5 3 1130 test_gr_a5a5 4 1131 test_gr_a5a5 5 1132 test_gr_a5a5 6 1133 test_gr_a5a5 7 1134 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1135 cmp.w #0xa969, @word_dest 1136 beq .Lwpreinc2 1137 fail 1138 .Lwpreinc2: 1139 mov #0xa5a5a5a5, @word_dest 1140 1141 rotxr_w_predec_2: 1142 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1143 set_ccr_zero 1144 1145 mov #word_dest+2, er0 1146 rotxr.w #2, @-er0 ; shift right arithmetic by two, predec 1147 ;;; .word 0x0157 1148 ;;; .word 0x6d08 1149 ;;; .word 0x1350 1150 1151 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1152 test_zero_clear 1153 test_ovf_clear 1154 test_neg_set 1155 1156 test_h_gr32 word_dest er0 1157 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1158 test_gr_a5a5 2 1159 test_gr_a5a5 3 1160 test_gr_a5a5 4 1161 test_gr_a5a5 5 1162 test_gr_a5a5 6 1163 test_gr_a5a5 7 1164 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1165 cmp.w #0xa969, @word_dest 1166 beq .Lwpredec2 1167 fail 1168 .Lwpredec2: 1169 mov #0xa5a5a5a5, @word_dest 1170 1171 rotxr_w_disp2_2: 1172 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1173 set_ccr_zero 1174 1175 mov #word_dest-4, er0 1176 rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 1177 ;;; .word 0x0156 1178 ;;; .word 0xa908 1179 ;;; .word 0x1350 1180 1181 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1182 test_zero_clear 1183 test_ovf_clear 1184 test_neg_set 1185 1186 test_h_gr32 word_dest-4 er0 1187 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1188 test_gr_a5a5 2 1189 test_gr_a5a5 3 1190 test_gr_a5a5 4 1191 test_gr_a5a5 5 1192 test_gr_a5a5 6 1193 test_gr_a5a5 7 1194 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1195 cmp.w #0xa969, @word_dest 1196 beq .Lwdisp22 1197 fail 1198 .Lwdisp22: 1199 mov #0xa5a5a5a5, @word_dest 1200 1201 rotxr_w_disp16_2: 1202 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1203 set_ccr_zero 1204 1205 mov #word_dest-44, er0 1206 rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16 1207 ;;; .word 0x0154 1208 ;;; .word 0x6f08 1209 ;;; .word 44 1210 ;;; .word 0x1350 1211 1212 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1213 test_zero_clear 1214 test_ovf_clear 1215 test_neg_set 1216 1217 test_h_gr32 word_dest-44 er0 1218 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1219 test_gr_a5a5 2 1220 test_gr_a5a5 3 1221 test_gr_a5a5 4 1222 test_gr_a5a5 5 1223 test_gr_a5a5 6 1224 test_gr_a5a5 7 1225 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1226 cmp.w #0xa969, @word_dest 1227 beq .Lwdisp162 1228 fail 1229 .Lwdisp162: 1230 mov #0xa5a5a5a5, @word_dest 1231 1232 rotxr_w_disp32_2: 1233 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1234 set_ccr_zero 1235 1236 mov #word_dest-666, er0 1237 rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32 1238 ;;; .word 0x7884 1239 ;;; .word 0x6b28 1240 ;;; .long 666 1241 ;;; .word 0x1350 1242 1243 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1244 test_zero_clear 1245 test_ovf_clear 1246 test_neg_set 1247 1248 test_h_gr32 word_dest-666 er0 1249 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1250 test_gr_a5a5 2 1251 test_gr_a5a5 3 1252 test_gr_a5a5 4 1253 test_gr_a5a5 5 1254 test_gr_a5a5 6 1255 test_gr_a5a5 7 1256 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1257 cmp.w #0xa969, @word_dest 1258 beq .Lwdisp322 1259 fail 1260 .Lwdisp322: 1261 mov #0xa5a5a5a5, @word_dest 1262 1263 rotxr_w_abs16_2: 1264 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1265 set_ccr_zero 1266 1267 rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16 1268 ;;; .word 0x6b18 1269 ;;; .word word_dest 1270 ;;; .word 0x1350 1271 1272 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1273 test_zero_clear 1274 test_ovf_clear 1275 test_neg_set 1276 1277 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1278 test_gr_a5a5 2 1279 test_gr_a5a5 2 1280 test_gr_a5a5 3 1281 test_gr_a5a5 4 1282 test_gr_a5a5 5 1283 test_gr_a5a5 6 1284 test_gr_a5a5 7 1285 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1286 cmp.w #0xa969, @word_dest 1287 beq .Lwabs162 1288 fail 1289 .Lwabs162: 1290 mov #0xa5a5a5a5, @word_dest 1291 1292 rotxr_w_abs32_2: 1293 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1294 set_ccr_zero 1295 1296 rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32 1297 ;;; .word 0x6b38 1298 ;;; .long word_dest 1299 ;;; .word 0x1350 1300 1301 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1302 test_zero_clear 1303 test_ovf_clear 1304 test_neg_set 1305 1306 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1307 test_gr_a5a5 2 1308 test_gr_a5a5 2 1309 test_gr_a5a5 3 1310 test_gr_a5a5 4 1311 test_gr_a5a5 5 1312 test_gr_a5a5 6 1313 test_gr_a5a5 7 1314 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001 1315 cmp.w #0xa969, @word_dest 1316 beq .Lwabs322 1317 fail 1318 .Lwabs322: 1319 mov #0xa5a5a5a5, @word_dest 1320 .endif 1321 1322 rotxr_l_reg32_1: 1323 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1324 set_ccr_zero 1325 1326 rotxr.l er0 ; shift right arithmetic by one, register 1327 ;;; .word 0x1330 1328 1329 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1330 test_zero_clear 1331 test_ovf_clear 1332 test_neg_clear 1333 1334 ; 1010 0101 1010 0101 1010 0101 1010 0101 1335 ; -> 0101 0010 1101 0010 1101 0010 1101 0010 1336 test_h_gr32 0x52d2d2d2 er0 1337 1338 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1339 test_gr_a5a5 2 1340 test_gr_a5a5 3 1341 test_gr_a5a5 4 1342 test_gr_a5a5 5 1343 test_gr_a5a5 6 1344 test_gr_a5a5 7 1345 1346 .if (sim_cpu == h8sx) 1347 rotxr_l_ind_1: 1348 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1349 set_ccr_zero 1350 1351 mov #long_dest, er0 1352 rotxr.l @er0 ; shift right arithmetic by one, indirect 1353 ;;; .word 0x0104 1354 ;;; .word 0xa908 1355 ;;; .word 0x1330 1356 1357 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1358 test_zero_clear 1359 test_ovf_clear 1360 test_neg_clear 1361 1362 test_h_gr32 long_dest er0 1363 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1364 test_gr_a5a5 2 1365 test_gr_a5a5 3 1366 test_gr_a5a5 4 1367 test_gr_a5a5 5 1368 test_gr_a5a5 6 1369 test_gr_a5a5 7 1370 ; 1010 0101 1010 0101 1010 0101 1010 0101 1371 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1372 cmp.l #0x52d2d2d2, @long_dest 1373 beq .Llind1 1374 fail 1375 .Llind1: 1376 mov #0xa5a5a5a5, @long_dest 1377 1378 rotxr_l_postinc_1: 1379 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1380 set_ccr_zero 1381 1382 mov #long_dest, er0 1383 rotxr.l @er0+ ; shift right arithmetic by one, postinc 1384 ;;; .word 0x0104 1385 ;;; .word 0x6d08 1386 ;;; .word 0x1330 1387 1388 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1389 test_zero_clear 1390 test_ovf_clear 1391 test_neg_clear 1392 1393 test_h_gr32 long_dest+4 er0 1394 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1395 test_gr_a5a5 2 1396 test_gr_a5a5 3 1397 test_gr_a5a5 4 1398 test_gr_a5a5 5 1399 test_gr_a5a5 6 1400 test_gr_a5a5 7 1401 ; 1010 0101 1010 0101 1010 0101 1010 0101 1402 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1403 cmp.l #0x52d2d2d2, @long_dest 1404 beq .Llpostinc1 1405 fail 1406 .Llpostinc1: 1407 mov #0xa5a5a5a5, @long_dest 1408 1409 rotxr_l_postdec_1: 1410 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1411 set_ccr_zero 1412 1413 mov #long_dest, er0 1414 rotxr.l @er0- ; shift right arithmetic by one, postdec 1415 ;;; .word 0x0106 1416 ;;; .word 0x6d08 1417 ;;; .word 0x1330 1418 1419 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1420 test_zero_clear 1421 test_ovf_clear 1422 test_neg_clear 1423 1424 test_h_gr32 long_dest-4 er0 1425 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1426 test_gr_a5a5 2 1427 test_gr_a5a5 3 1428 test_gr_a5a5 4 1429 test_gr_a5a5 5 1430 test_gr_a5a5 6 1431 test_gr_a5a5 7 1432 ; 1010 0101 1010 0101 1010 0101 1010 0101 1433 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1434 cmp.l #0x52d2d2d2, @long_dest 1435 beq .Llpostdec1 1436 fail 1437 .Llpostdec1: 1438 mov #0xa5a5a5a5, @long_dest 1439 1440 rotxr_l_preinc_1: 1441 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1442 set_ccr_zero 1443 1444 mov #long_dest-4, er0 1445 rotxr.l @+er0 ; shift right arithmetic by one, preinc 1446 ;;; .word 0x0105 1447 ;;; .word 0x6d08 1448 ;;; .word 0x1330 1449 1450 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1451 test_zero_clear 1452 test_ovf_clear 1453 test_neg_clear 1454 1455 test_h_gr32 long_dest er0 1456 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1457 test_gr_a5a5 2 1458 test_gr_a5a5 3 1459 test_gr_a5a5 4 1460 test_gr_a5a5 5 1461 test_gr_a5a5 6 1462 test_gr_a5a5 7 1463 ; 1010 0101 1010 0101 1010 0101 1010 0101 1464 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1465 cmp.l #0x52d2d2d2, @long_dest 1466 beq .Llpreinc1 1467 fail 1468 .Llpreinc1: 1469 mov #0xa5a5a5a5, @long_dest 1470 1471 rotxr_l_predec_1: 1472 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1473 set_ccr_zero 1474 1475 mov #long_dest+4, er0 1476 rotxr.l @-er0 ; shift right arithmetic by one, predec 1477 ;;; .word 0x0107 1478 ;;; .word 0x6d08 1479 ;;; .word 0x1330 1480 1481 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1482 test_zero_clear 1483 test_ovf_clear 1484 test_neg_clear 1485 1486 test_h_gr32 long_dest er0 1487 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1488 test_gr_a5a5 2 1489 test_gr_a5a5 3 1490 test_gr_a5a5 4 1491 test_gr_a5a5 5 1492 test_gr_a5a5 6 1493 test_gr_a5a5 7 1494 ; 1010 0101 1010 0101 1010 0101 1010 0101 1495 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1496 cmp.l #0x52d2d2d2, @long_dest 1497 beq .Llpredec1 1498 fail 1499 .Llpredec1: 1500 mov #0xa5a5a5a5, @long_dest 1501 1502 rotxr_l_disp2_1: 1503 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1504 set_ccr_zero 1505 1506 mov #long_dest-8, er0 1507 rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2 1508 ;;; .word 0x0106 1509 ;;; .word 0xa908 1510 ;;; .word 0x1330 1511 1512 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1513 test_zero_clear 1514 test_ovf_clear 1515 test_neg_clear 1516 1517 test_h_gr32 long_dest-8 er0 1518 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1519 test_gr_a5a5 2 1520 test_gr_a5a5 3 1521 test_gr_a5a5 4 1522 test_gr_a5a5 5 1523 test_gr_a5a5 6 1524 test_gr_a5a5 7 1525 ; 1010 0101 1010 0101 1010 0101 1010 0101 1526 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1527 cmp.l #0x52d2d2d2, @long_dest 1528 beq .Lldisp21 1529 fail 1530 .Lldisp21: 1531 mov #0xa5a5a5a5, @long_dest 1532 1533 rotxr_l_disp16_1: 1534 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1535 set_ccr_zero 1536 1537 mov #long_dest-44, er0 1538 rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16 1539 ;;; .word 0x0104 1540 ;;; .word 0x6f08 1541 ;;; .word 44 1542 ;;; .word 0x1330 1543 1544 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1545 test_zero_clear 1546 test_ovf_clear 1547 test_neg_clear 1548 1549 test_h_gr32 long_dest-44 er0 1550 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1551 test_gr_a5a5 2 1552 test_gr_a5a5 3 1553 test_gr_a5a5 4 1554 test_gr_a5a5 5 1555 test_gr_a5a5 6 1556 test_gr_a5a5 7 1557 ; 1010 0101 1010 0101 1010 0101 1010 0101 1558 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1559 cmp.l #0x52d2d2d2, @long_dest 1560 beq .Lldisp161 1561 fail 1562 .Lldisp161: 1563 mov #0xa5a5a5a5, @long_dest 1564 1565 rotxr_l_disp32_1: 1566 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1567 set_ccr_zero 1568 1569 mov #long_dest-666, er0 1570 rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32 1571 ;;; .word 0x7884 1572 ;;; .word 0x6b28 1573 ;;; .long 666 1574 ;;; .word 0x1330 1575 1576 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1577 test_zero_clear 1578 test_ovf_clear 1579 test_neg_clear 1580 1581 test_h_gr32 long_dest-666 er0 1582 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1583 test_gr_a5a5 2 1584 test_gr_a5a5 3 1585 test_gr_a5a5 4 1586 test_gr_a5a5 5 1587 test_gr_a5a5 6 1588 test_gr_a5a5 7 1589 ; 1010 0101 1010 0101 1010 0101 1010 0101 1590 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1591 cmp.l #0x52d2d2d2, @long_dest 1592 beq .Lldisp321 1593 fail 1594 .Lldisp321: 1595 mov #0xa5a5a5a5, @long_dest 1596 1597 rotxr_l_abs16_1: 1598 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1599 set_ccr_zero 1600 1601 rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16 1602 ;;; .word 0x0104 1603 ;;; .word 0x6b08 1604 ;;; .word long_dest 1605 ;;; .word 0x1330 1606 1607 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1608 test_zero_clear 1609 test_ovf_clear 1610 test_neg_clear 1611 1612 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1613 test_gr_a5a5 1 1614 test_gr_a5a5 2 1615 test_gr_a5a5 3 1616 test_gr_a5a5 4 1617 test_gr_a5a5 5 1618 test_gr_a5a5 6 1619 test_gr_a5a5 7 1620 ; 1010 0101 1010 0101 1010 0101 1010 0101 1621 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1622 cmp.l #0x52d2d2d2, @long_dest 1623 beq .Llabs161 1624 fail 1625 .Llabs161: 1626 mov #0xa5a5a5a5, @long_dest 1627 1628 rotxr_l_abs32_1: 1629 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1630 set_ccr_zero 1631 1632 rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32 1633 ;;; .word 0x0104 1634 ;;; .word 0x6b28 1635 ;;; .long long_dest 1636 ;;; .word 0x1330 1637 1638 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1639 test_zero_clear 1640 test_ovf_clear 1641 test_neg_clear 1642 1643 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1644 test_gr_a5a5 1 1645 test_gr_a5a5 2 1646 test_gr_a5a5 3 1647 test_gr_a5a5 4 1648 test_gr_a5a5 5 1649 test_gr_a5a5 6 1650 test_gr_a5a5 7 1651 ; 1010 0101 1010 0101 1010 0101 1010 0101 1652 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 1653 cmp.l #0x52d2d2d2, @long_dest 1654 beq .Llabs321 1655 fail 1656 .Llabs321: 1657 mov #0xa5a5a5a5, @long_dest 1658 .endif 1659 1660 rotxr_l_reg32_2: 1661 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1662 set_ccr_zero 1663 1664 rotxr.l #2, er0 ; shift right arithmetic by two, register 1665 ;;; .word 0x1370 1666 1667 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1668 test_zero_clear 1669 test_ovf_clear 1670 test_neg_set 1671 ; 1010 0101 1010 0101 1010 0101 1010 0101 1672 ; -> 1010 1001 0110 1001 0110 1001 0110 1001 1673 test_h_gr32 0xa9696969 er0 1674 1675 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1676 test_gr_a5a5 2 1677 test_gr_a5a5 3 1678 test_gr_a5a5 4 1679 test_gr_a5a5 5 1680 test_gr_a5a5 6 1681 test_gr_a5a5 7 1682 1683 .if (sim_cpu == h8sx) 1684 1685 rotxr_l_ind_2: 1686 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1687 set_ccr_zero 1688 1689 mov #long_dest, er0 1690 rotxr.l #2, @er0 ; shift right arithmetic by two, indirect 1691 ;;; .word 0x0104 1692 ;;; .word 0xa908 1693 ;;; .word 0x1370 1694 1695 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1696 test_zero_clear 1697 test_ovf_clear 1698 test_neg_set 1699 1700 test_h_gr32 long_dest er0 1701 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1702 test_gr_a5a5 2 1703 test_gr_a5a5 3 1704 test_gr_a5a5 4 1705 test_gr_a5a5 5 1706 test_gr_a5a5 6 1707 test_gr_a5a5 7 1708 ; 1010 0101 1010 0101 1010 0101 1010 0101 1709 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1710 cmp.l #0xa9696969, @long_dest 1711 beq .Llind2 1712 fail 1713 .Llind2: 1714 mov #0xa5a5a5a5, @long_dest 1715 1716 rotxr_l_postinc_2: 1717 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1718 set_ccr_zero 1719 1720 mov #long_dest, er0 1721 rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc 1722 ;;; .word 0x0104 1723 ;;; .word 0x6d08 1724 ;;; .word 0x1370 1725 1726 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1727 test_zero_clear 1728 test_ovf_clear 1729 test_neg_set 1730 1731 test_h_gr32 long_dest+4 er0 1732 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1733 test_gr_a5a5 2 1734 test_gr_a5a5 3 1735 test_gr_a5a5 4 1736 test_gr_a5a5 5 1737 test_gr_a5a5 6 1738 test_gr_a5a5 7 1739 ; 1010 0101 1010 0101 1010 0101 1010 0101 1740 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1741 cmp.l #0xa9696969, @long_dest 1742 beq .Llpostinc2 1743 fail 1744 .Llpostinc2: 1745 mov #0xa5a5a5a5, @long_dest 1746 1747 rotxr_l_postdec_2: 1748 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1749 set_ccr_zero 1750 1751 mov #long_dest, er0 1752 rotxr.l #2, @er0- ; shift right arithmetic by two, postdec 1753 ;;; .word 0x0106 1754 ;;; .word 0x6d08 1755 ;;; .word 0x1370 1756 1757 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1758 test_zero_clear 1759 test_ovf_clear 1760 test_neg_set 1761 1762 test_h_gr32 long_dest-4 er0 1763 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1764 test_gr_a5a5 2 1765 test_gr_a5a5 3 1766 test_gr_a5a5 4 1767 test_gr_a5a5 5 1768 test_gr_a5a5 6 1769 test_gr_a5a5 7 1770 ; 1010 0101 1010 0101 1010 0101 1010 0101 1771 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1772 cmp.l #0xa9696969, @long_dest 1773 beq .Llpostdec2 1774 fail 1775 .Llpostdec2: 1776 mov #0xa5a5a5a5, @long_dest 1777 1778 rotxr_l_preinc_2: 1779 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1780 set_ccr_zero 1781 1782 mov #long_dest-4, er0 1783 rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc 1784 ;;; .word 0x0105 1785 ;;; .word 0x6d08 1786 ;;; .word 0x1370 1787 1788 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1789 test_zero_clear 1790 test_ovf_clear 1791 test_neg_set 1792 1793 test_h_gr32 long_dest er0 1794 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1795 test_gr_a5a5 2 1796 test_gr_a5a5 3 1797 test_gr_a5a5 4 1798 test_gr_a5a5 5 1799 test_gr_a5a5 6 1800 test_gr_a5a5 7 1801 ; 1010 0101 1010 0101 1010 0101 1010 0101 1802 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1803 cmp.l #0xa9696969, @long_dest 1804 beq .Llpreinc2 1805 fail 1806 .Llpreinc2: 1807 mov #0xa5a5a5a5, @long_dest 1808 1809 rotxr_l_predec_2: 1810 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1811 set_ccr_zero 1812 1813 mov #long_dest+4, er0 1814 rotxr.l #2, @-er0 ; shift right arithmetic by two, predec 1815 ;;; .word 0x0107 1816 ;;; .word 0x6d08 1817 ;;; .word 0x1370 1818 1819 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1820 test_zero_clear 1821 test_ovf_clear 1822 test_neg_set 1823 1824 test_h_gr32 long_dest er0 1825 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1826 test_gr_a5a5 2 1827 test_gr_a5a5 3 1828 test_gr_a5a5 4 1829 test_gr_a5a5 5 1830 test_gr_a5a5 6 1831 test_gr_a5a5 7 1832 ; 1010 0101 1010 0101 1010 0101 1010 0101 1833 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1834 cmp.l #0xa9696969, @long_dest 1835 beq .Llpredec2 1836 fail 1837 .Llpredec2: 1838 mov #0xa5a5a5a5, @long_dest 1839 1840 rotxr_l_disp2_2: 1841 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1842 set_ccr_zero 1843 1844 mov #long_dest-8, er0 1845 rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 1846 ;;; .word 0x0106 1847 ;;; .word 0xa908 1848 ;;; .word 0x1370 1849 1850 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1851 test_zero_clear 1852 test_ovf_clear 1853 test_neg_set 1854 1855 test_h_gr32 long_dest-8 er0 1856 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1857 test_gr_a5a5 2 1858 test_gr_a5a5 3 1859 test_gr_a5a5 4 1860 test_gr_a5a5 5 1861 test_gr_a5a5 6 1862 test_gr_a5a5 7 1863 ; 1010 0101 1010 0101 1010 0101 1010 0101 1864 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1865 cmp.l #0xa9696969, @long_dest 1866 beq .Lldisp22 1867 fail 1868 .Lldisp22: 1869 mov #0xa5a5a5a5, @long_dest 1870 1871 rotxr_l_disp16_2: 1872 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1873 set_ccr_zero 1874 1875 mov #long_dest-44, er0 1876 rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16 1877 ;;; .word 0x0104 1878 ;;; .word 0x6f08 1879 ;;; .word 44 1880 ;;; .word 0x1370 1881 1882 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1883 test_zero_clear 1884 test_ovf_clear 1885 test_neg_set 1886 1887 test_h_gr32 long_dest-44 er0 1888 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1889 test_gr_a5a5 2 1890 test_gr_a5a5 3 1891 test_gr_a5a5 4 1892 test_gr_a5a5 5 1893 test_gr_a5a5 6 1894 test_gr_a5a5 7 1895 ; 1010 0101 1010 0101 1010 0101 1010 0101 1896 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1897 cmp.l #0xa9696969, @long_dest 1898 beq .Lldisp162 1899 fail 1900 .Lldisp162: 1901 mov #0xa5a5a5a5, @long_dest 1902 1903 rotxr_l_disp32_2: 1904 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1905 set_ccr_zero 1906 1907 mov #long_dest-666, er0 1908 rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32 1909 ;;; .word 0x7884 1910 ;;; .word 0x6b28 1911 ;;; .long 666 1912 ;;; .word 0x1370 1913 1914 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1915 test_zero_clear 1916 test_ovf_clear 1917 test_neg_set 1918 1919 test_h_gr32 long_dest-666 er0 1920 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1921 test_gr_a5a5 2 1922 test_gr_a5a5 3 1923 test_gr_a5a5 4 1924 test_gr_a5a5 5 1925 test_gr_a5a5 6 1926 test_gr_a5a5 7 1927 ; 1010 0101 1010 0101 1010 0101 1010 0101 1928 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1929 cmp.l #0xa9696969, @long_dest 1930 beq .Lldisp322 1931 fail 1932 .Lldisp322: 1933 mov #0xa5a5a5a5, @long_dest 1934 1935 rotxr_l_abs16_2: 1936 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1937 set_ccr_zero 1938 1939 rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16 1940 ;;; .word 0x0104 1941 ;;; .word 0x6b08 1942 ;;; .word long_dest 1943 ;;; .word 0x1370 1944 1945 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1946 test_zero_clear 1947 test_ovf_clear 1948 test_neg_set 1949 1950 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1951 test_gr_a5a5 1 1952 test_gr_a5a5 2 1953 test_gr_a5a5 3 1954 test_gr_a5a5 4 1955 test_gr_a5a5 5 1956 test_gr_a5a5 6 1957 test_gr_a5a5 7 1958 ; 1010 0101 1010 0101 1010 0101 1010 0101 1959 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1960 cmp.l #0xa9696969, @long_dest 1961 beq .Llabs162 1962 fail 1963 .Llabs162: 1964 mov #0xa5a5a5a5, @long_dest 1965 1966 rotxr_l_abs32_2: 1967 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1968 set_ccr_zero 1969 1970 rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32 1971 ;;; .word 0x0104 1972 ;;; .word 0x6b28 1973 ;;; .long long_dest 1974 ;;; .word 0x1370 1975 1976 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 1977 test_zero_clear 1978 test_ovf_clear 1979 test_neg_set 1980 1981 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1982 test_gr_a5a5 1 1983 test_gr_a5a5 2 1984 test_gr_a5a5 3 1985 test_gr_a5a5 4 1986 test_gr_a5a5 5 1987 test_gr_a5a5 6 1988 test_gr_a5a5 7 1989 ; 1010 0101 1010 0101 1010 0101 1010 0101 1990 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001 1991 cmp.l #0xa9696969, @long_dest 1992 beq .Llabs322 1993 fail 1994 .Llabs322: 1995 mov #0xa5a5a5a5, @long_dest 1996 1997 .endif 1998 .endif 1999 pass 2000 2001 exit 0 2002 2003
Indexes created Sun Jul 05 00:25:41 UTC 2026