1 1.1 christos # Hitachi H8 testcase 'shlr' 2 1.1 christos # mach(): h8300s h8sx 3 1.1 christos # as(h8300): --defsym sim_cpu=0 4 1.1 christos # as(h8300h): --defsym sim_cpu=1 5 1.1 christos # as(h8300s): --defsym sim_cpu=2 6 1.1 christos # as(h8sx): --defsym sim_cpu=3 7 1.1 christos # ld(h8300h): -m h8300helf 8 1.1 christos # ld(h8300s): -m h8300self 9 1.1 christos # ld(h8sx): -m h8300sxelf 10 1.1 christos 11 1.1 christos .include "testutils.inc" 12 1.1 christos 13 1.1 christos start 14 1.1 christos 15 1.1 christos .data 16 1.1 christos byte_dest: .byte 0xa5 17 1.1 christos .align 2 18 1.1 christos word_dest: .word 0xa5a5 19 1.1 christos .align 4 20 1.1 christos long_dest: .long 0xa5a5a5a5 21 1.1 christos 22 1.1 christos .text 23 1.1 christos 24 1.1 christos shlr_b_reg8_1: 25 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 26 1.1 christos set_ccr_zero 27 1.1 christos 28 1.1 christos shlr.b r0l ; shift right logical by one 29 1.1 christos ;;; .word 0x1108 30 1.1 christos 31 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 32 1.1 christos test_zero_clear 33 1.1 christos test_ovf_clear 34 1.1 christos test_neg_clear 35 1.1 christos 36 1.1 christos test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 37 1.1 christos .if (sim_cpu) 38 1.1 christos test_h_gr32 0xa5a5a552 er0 39 1.1 christos .endif 40 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 41 1.1 christos test_gr_a5a5 2 42 1.1 christos test_gr_a5a5 3 43 1.1 christos test_gr_a5a5 4 44 1.1 christos test_gr_a5a5 5 45 1.1 christos test_gr_a5a5 6 46 1.1 christos test_gr_a5a5 7 47 1.1 christos 48 1.1 christos .if (sim_cpu == h8sx) 49 1.1 christos shlr_b_ind_1: 50 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 51 1.1 christos set_ccr_zero 52 1.1 christos 53 1.1 christos mov #byte_dest, er0 54 1.1 christos shlr.b @er0 ; shift right logical by one, indirect 55 1.1 christos ;;; .word 0x7d00 56 1.1 christos ;;; .word 0x1100 57 1.1 christos 58 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 59 1.1 christos test_zero_clear 60 1.1 christos test_ovf_clear 61 1.1 christos test_neg_clear 62 1.1 christos 63 1.1 christos test_h_gr32 byte_dest er0 64 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 65 1.1 christos test_gr_a5a5 2 66 1.1 christos test_gr_a5a5 3 67 1.1 christos test_gr_a5a5 4 68 1.1 christos test_gr_a5a5 5 69 1.1 christos test_gr_a5a5 6 70 1.1 christos test_gr_a5a5 7 71 1.1 christos ; 1010 0101 -> 0101 0010 72 1.1 christos cmp.b #0x52, @byte_dest 73 1.1 christos beq .Lbind1 74 1.1 christos fail 75 1.1 christos .Lbind1: 76 1.1 christos mov.b #0xa5, @byte_dest 77 1.1 christos 78 1.1 christos shlr_b_postinc_1: 79 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 80 1.1 christos set_ccr_zero 81 1.1 christos 82 1.1 christos mov #byte_dest, er0 83 1.1 christos shlr.b @er0+ ; shift right logical by one, postinc 84 1.1 christos ;;; .word 0x0174 85 1.1 christos ;;; .word 0x6c08 86 1.1 christos ;;; .word 0x1100 87 1.1 christos 88 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 89 1.1 christos test_zero_clear 90 1.1 christos test_ovf_clear 91 1.1 christos test_neg_clear 92 1.1 christos 93 1.1 christos test_h_gr32 byte_dest+1 er0 94 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 95 1.1 christos test_gr_a5a5 2 96 1.1 christos test_gr_a5a5 3 97 1.1 christos test_gr_a5a5 4 98 1.1 christos test_gr_a5a5 5 99 1.1 christos test_gr_a5a5 6 100 1.1 christos test_gr_a5a5 7 101 1.1 christos ; 1010 0101 -> 0101 0010 102 1.1 christos cmp.b #0x52, @byte_dest 103 1.1 christos beq .Lbpostinc1 104 1.1 christos fail 105 1.1 christos .Lbpostinc1: 106 1.1 christos mov.b #0xa5, @byte_dest 107 1.1 christos 108 1.1 christos shlr_b_postdec_1: 109 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 110 1.1 christos set_ccr_zero 111 1.1 christos 112 1.1 christos mov #byte_dest, er0 113 1.1 christos shlr.b @er0- ; shift right logical by one, postdec 114 1.1 christos ;;; .word 0x0176 115 1.1 christos ;;; .word 0x6c08 116 1.1 christos ;;; .word 0x1100 117 1.1 christos 118 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 119 1.1 christos test_zero_clear 120 1.1 christos test_ovf_clear 121 1.1 christos test_neg_clear 122 1.1 christos 123 1.1 christos test_h_gr32 byte_dest-1 er0 124 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 125 1.1 christos test_gr_a5a5 2 126 1.1 christos test_gr_a5a5 3 127 1.1 christos test_gr_a5a5 4 128 1.1 christos test_gr_a5a5 5 129 1.1 christos test_gr_a5a5 6 130 1.1 christos test_gr_a5a5 7 131 1.1 christos ; 1010 0101 -> 0101 0010 132 1.1 christos cmp.b #0x52, @byte_dest 133 1.1 christos beq .Lbpostdec1 134 1.1 christos fail 135 1.1 christos .Lbpostdec1: 136 1.1 christos mov.b #0xa5, @byte_dest 137 1.1 christos 138 1.1 christos shlr_b_preinc_1: 139 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 140 1.1 christos set_ccr_zero 141 1.1 christos 142 1.1 christos mov #byte_dest-1, er0 143 1.1 christos shlr.b @+er0 ; shift right logical by one, preinc 144 1.1 christos ;;; .word 0x0175 145 1.1 christos ;;; .word 0x6c08 146 1.1 christos ;;; .word 0x1100 147 1.1 christos 148 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 149 1.1 christos test_zero_clear 150 1.1 christos test_ovf_clear 151 1.1 christos test_neg_clear 152 1.1 christos 153 1.1 christos test_h_gr32 byte_dest er0 154 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 155 1.1 christos test_gr_a5a5 2 156 1.1 christos test_gr_a5a5 3 157 1.1 christos test_gr_a5a5 4 158 1.1 christos test_gr_a5a5 5 159 1.1 christos test_gr_a5a5 6 160 1.1 christos test_gr_a5a5 7 161 1.1 christos ; 1010 0101 -> 0101 0010 162 1.1 christos cmp.b #0x52, @byte_dest 163 1.1 christos beq .Lbpreinc1 164 1.1 christos fail 165 1.1 christos .Lbpreinc1: 166 1.1 christos mov.b #0xa5, @byte_dest 167 1.1 christos 168 1.1 christos shlr_b_predec_1: 169 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 170 1.1 christos set_ccr_zero 171 1.1 christos 172 1.1 christos mov #byte_dest+1, er0 173 1.1 christos shlr.b @-er0 ; shift right logical by one, predec 174 1.1 christos ;;; .word 0x0177 175 1.1 christos ;;; .word 0x6c08 176 1.1 christos ;;; .word 0x1100 177 1.1 christos 178 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 179 1.1 christos test_zero_clear 180 1.1 christos test_ovf_clear 181 1.1 christos test_neg_clear 182 1.1 christos 183 1.1 christos test_h_gr32 byte_dest er0 184 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 185 1.1 christos test_gr_a5a5 2 186 1.1 christos test_gr_a5a5 3 187 1.1 christos test_gr_a5a5 4 188 1.1 christos test_gr_a5a5 5 189 1.1 christos test_gr_a5a5 6 190 1.1 christos test_gr_a5a5 7 191 1.1 christos ; 1010 0101 -> 0101 0010 192 1.1 christos cmp.b #0x52, @byte_dest 193 1.1 christos beq .Lbpredec1 194 1.1 christos fail 195 1.1 christos .Lbpredec1: 196 1.1 christos mov.b #0xa5, @byte_dest 197 1.1 christos 198 1.1 christos shlr_b_disp2_1: 199 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 200 1.1 christos set_ccr_zero 201 1.1 christos 202 1.1 christos mov #byte_dest-2, er0 203 1.1 christos shlr.b @(2:2, er0) ; shift right logical by one, disp2 204 1.1 christos ;;; .word 0x0176 205 1.1 christos ;;; .word 0x6808 206 1.1 christos ;;; .word 0x1100 207 1.1 christos 208 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 209 1.1 christos test_zero_clear 210 1.1 christos test_ovf_clear 211 1.1 christos test_neg_clear 212 1.1 christos 213 1.1 christos test_h_gr32 byte_dest-2 er0 214 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 215 1.1 christos test_gr_a5a5 2 216 1.1 christos test_gr_a5a5 3 217 1.1 christos test_gr_a5a5 4 218 1.1 christos test_gr_a5a5 5 219 1.1 christos test_gr_a5a5 6 220 1.1 christos test_gr_a5a5 7 221 1.1 christos ; 1010 0101 -> 0101 0010 222 1.1 christos cmp.b #0x52, @byte_dest 223 1.1 christos beq .Lbdisp21 224 1.1 christos fail 225 1.1 christos .Lbdisp21: 226 1.1 christos mov.b #0xa5, @byte_dest 227 1.1 christos 228 1.1 christos shlr_b_disp16_1: 229 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 230 1.1 christos set_ccr_zero 231 1.1 christos 232 1.1 christos mov #byte_dest-44, er0 233 1.1 christos shlr.b @(44:16, er0) ; shift right logical by one, disp16 234 1.1 christos ;;; .word 0x0174 235 1.1 christos ;;; .word 0x6e08 236 1.1 christos ;;; .word 44 237 1.1 christos ;;; .word 0x1100 238 1.1 christos 239 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 240 1.1 christos test_zero_clear 241 1.1 christos test_ovf_clear 242 1.1 christos test_neg_clear 243 1.1 christos 244 1.1 christos test_h_gr32 byte_dest-44 er0 245 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 246 1.1 christos test_gr_a5a5 2 247 1.1 christos test_gr_a5a5 3 248 1.1 christos test_gr_a5a5 4 249 1.1 christos test_gr_a5a5 5 250 1.1 christos test_gr_a5a5 6 251 1.1 christos test_gr_a5a5 7 252 1.1 christos ; 1010 0101 -> 0101 0010 253 1.1 christos cmp.b #0x52, @byte_dest 254 1.1 christos beq .Lbdisp161 255 1.1 christos fail 256 1.1 christos .Lbdisp161: 257 1.1 christos mov.b #0xa5, @byte_dest 258 1.1 christos 259 1.1 christos shlr_b_disp32_1: 260 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 261 1.1 christos set_ccr_zero 262 1.1 christos 263 1.1 christos mov #byte_dest-666, er0 264 1.1 christos shlr.b @(666:32, er0) ; shift right logical by one, disp32 265 1.1 christos ;;; .word 0x7884 266 1.1 christos ;;; .word 0x6a28 267 1.1 christos ;;; .long 666 268 1.1 christos ;;; .word 0x1100 269 1.1 christos 270 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 271 1.1 christos test_zero_clear 272 1.1 christos test_ovf_clear 273 1.1 christos test_neg_clear 274 1.1 christos 275 1.1 christos test_h_gr32 byte_dest-666 er0 276 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 277 1.1 christos test_gr_a5a5 2 278 1.1 christos test_gr_a5a5 3 279 1.1 christos test_gr_a5a5 4 280 1.1 christos test_gr_a5a5 5 281 1.1 christos test_gr_a5a5 6 282 1.1 christos test_gr_a5a5 7 283 1.1 christos ; 1010 0101 -> 0101 0010 284 1.1 christos cmp.b #0x52, @byte_dest 285 1.1 christos beq .Lbdisp321 286 1.1 christos fail 287 1.1 christos .Lbdisp321: 288 1.1 christos mov.b #0xa5, @byte_dest 289 1.1 christos 290 1.1 christos shlr_b_abs16_1: 291 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 292 1.1 christos set_ccr_zero 293 1.1 christos 294 1.1 christos shlr.b @byte_dest:16 ; shift right logical by one, abs16 295 1.1 christos ;;; .word 0x6a18 296 1.1 christos ;;; .word byte_dest 297 1.1 christos ;;; .word 0x1100 298 1.1 christos 299 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 300 1.1 christos test_zero_clear 301 1.1 christos test_ovf_clear 302 1.1 christos test_neg_clear 303 1.1 christos 304 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 305 1.1 christos test_gr_a5a5 2 306 1.1 christos test_gr_a5a5 2 307 1.1 christos test_gr_a5a5 3 308 1.1 christos test_gr_a5a5 4 309 1.1 christos test_gr_a5a5 5 310 1.1 christos test_gr_a5a5 6 311 1.1 christos test_gr_a5a5 7 312 1.1 christos ; 1010 0101 -> 0101 0010 313 1.1 christos cmp.b #0x52, @byte_dest 314 1.1 christos beq .Lbabs161 315 1.1 christos fail 316 1.1 christos .Lbabs161: 317 1.1 christos mov.b #0xa5, @byte_dest 318 1.1 christos 319 1.1 christos shlr_b_abs32_1: 320 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 321 1.1 christos set_ccr_zero 322 1.1 christos 323 1.1 christos shlr.b @byte_dest:32 ; shift right logical by one, abs32 324 1.1 christos ;;; .word 0x6a38 325 1.1 christos ;;; .long byte_dest 326 1.1 christos ;;; .word 0x1100 327 1.1 christos 328 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 329 1.1 christos test_zero_clear 330 1.1 christos test_ovf_clear 331 1.1 christos test_neg_clear 332 1.1 christos 333 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 334 1.1 christos test_gr_a5a5 2 335 1.1 christos test_gr_a5a5 2 336 1.1 christos test_gr_a5a5 3 337 1.1 christos test_gr_a5a5 4 338 1.1 christos test_gr_a5a5 5 339 1.1 christos test_gr_a5a5 6 340 1.1 christos test_gr_a5a5 7 341 1.1 christos ; 1010 0101 -> 0101 0010 342 1.1 christos cmp.b #0x52, @byte_dest 343 1.1 christos beq .Lbabs321 344 1.1 christos fail 345 1.1 christos .Lbabs321: 346 1.1 christos mov.b #0xa5, @byte_dest 347 1.1 christos .endif 348 1.1 christos 349 1.1 christos shlr_b_reg8_2: 350 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 351 1.1 christos set_ccr_zero 352 1.1 christos 353 1.1 christos shlr.b #2, r0l ; shift right logical by two 354 1.1 christos ;;; .word 0x1148 355 1.1 christos 356 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 357 1.1 christos test_zero_clear 358 1.1 christos test_ovf_clear 359 1.1 christos test_neg_clear 360 1.1 christos test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 361 1.1 christos .if (sim_cpu) 362 1.1 christos test_h_gr32 0xa5a5a529 er0 363 1.1 christos .endif 364 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 365 1.1 christos test_gr_a5a5 2 366 1.1 christos test_gr_a5a5 3 367 1.1 christos test_gr_a5a5 4 368 1.1 christos test_gr_a5a5 5 369 1.1 christos test_gr_a5a5 6 370 1.1 christos test_gr_a5a5 7 371 1.1 christos 372 1.1 christos .if (sim_cpu == h8sx) 373 1.1 christos shlr_b_ind_2: 374 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 375 1.1 christos set_ccr_zero 376 1.1 christos 377 1.1 christos mov #byte_dest, er0 378 1.1 christos shlr.b #2, @er0 ; shift right logical by two, indirect 379 1.1 christos ;;; .word 0x7d00 380 1.1 christos ;;; .word 0x1140 381 1.1 christos 382 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 383 1.1 christos test_zero_clear 384 1.1 christos test_ovf_clear 385 1.1 christos test_neg_clear 386 1.1 christos 387 1.1 christos test_h_gr32 byte_dest er0 388 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 389 1.1 christos test_gr_a5a5 2 390 1.1 christos test_gr_a5a5 3 391 1.1 christos test_gr_a5a5 4 392 1.1 christos test_gr_a5a5 5 393 1.1 christos test_gr_a5a5 6 394 1.1 christos test_gr_a5a5 7 395 1.1 christos ; 1010 0101 -> 0010 1001 396 1.1 christos cmp.b #0x29, @byte_dest 397 1.1 christos beq .Lbind2 398 1.1 christos fail 399 1.1 christos .Lbind2: 400 1.1 christos mov.b #0xa5, @byte_dest 401 1.1 christos 402 1.1 christos shlr_b_postinc_2: 403 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 404 1.1 christos set_ccr_zero 405 1.1 christos 406 1.1 christos mov #byte_dest, er0 407 1.1 christos shlr.b #2, @er0+ ; shift right logical by two, postinc 408 1.1 christos ;;; .word 0x0174 409 1.1 christos ;;; .word 0x6c08 410 1.1 christos ;;; .word 0x1140 411 1.1 christos 412 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 413 1.1 christos test_zero_clear 414 1.1 christos test_ovf_clear 415 1.1 christos test_neg_clear 416 1.1 christos 417 1.1 christos test_h_gr32 byte_dest+1 er0 418 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 419 1.1 christos test_gr_a5a5 2 420 1.1 christos test_gr_a5a5 3 421 1.1 christos test_gr_a5a5 4 422 1.1 christos test_gr_a5a5 5 423 1.1 christos test_gr_a5a5 6 424 1.1 christos test_gr_a5a5 7 425 1.1 christos ; 1010 0101 -> 0010 1001 426 1.1 christos cmp.b #0x29, @byte_dest 427 1.1 christos beq .Lbpostinc2 428 1.1 christos fail 429 1.1 christos .Lbpostinc2: 430 1.1 christos mov.b #0xa5, @byte_dest 431 1.1 christos 432 1.1 christos shlr_b_postdec_2: 433 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 434 1.1 christos set_ccr_zero 435 1.1 christos 436 1.1 christos mov #byte_dest, er0 437 1.1 christos shlr.b #2, @er0- ; shift right logical by two, postdec 438 1.1 christos ;;; .word 0x0176 439 1.1 christos ;;; .word 0x6c08 440 1.1 christos ;;; .word 0x1140 441 1.1 christos 442 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 443 1.1 christos test_zero_clear 444 1.1 christos test_ovf_clear 445 1.1 christos test_neg_clear 446 1.1 christos 447 1.1 christos test_h_gr32 byte_dest-1 er0 448 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 449 1.1 christos test_gr_a5a5 2 450 1.1 christos test_gr_a5a5 3 451 1.1 christos test_gr_a5a5 4 452 1.1 christos test_gr_a5a5 5 453 1.1 christos test_gr_a5a5 6 454 1.1 christos test_gr_a5a5 7 455 1.1 christos ; 1010 0101 -> 0010 1001 456 1.1 christos cmp.b #0x29, @byte_dest 457 1.1 christos beq .Lbpostdec2 458 1.1 christos fail 459 1.1 christos .Lbpostdec2: 460 1.1 christos mov.b #0xa5, @byte_dest 461 1.1 christos 462 1.1 christos shlr_b_preinc_2: 463 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 464 1.1 christos set_ccr_zero 465 1.1 christos 466 1.1 christos mov #byte_dest-1, er0 467 1.1 christos shlr.b #2, @+er0 ; shift right logical by two, preinc 468 1.1 christos ;;; .word 0x0175 469 1.1 christos ;;; .word 0x6c08 470 1.1 christos ;;; .word 0x1140 471 1.1 christos 472 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 473 1.1 christos test_zero_clear 474 1.1 christos test_ovf_clear 475 1.1 christos test_neg_clear 476 1.1 christos 477 1.1 christos test_h_gr32 byte_dest er0 478 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 479 1.1 christos test_gr_a5a5 2 480 1.1 christos test_gr_a5a5 3 481 1.1 christos test_gr_a5a5 4 482 1.1 christos test_gr_a5a5 5 483 1.1 christos test_gr_a5a5 6 484 1.1 christos test_gr_a5a5 7 485 1.1 christos ; 1010 0101 -> 0010 1001 486 1.1 christos cmp.b #0x29, @byte_dest 487 1.1 christos beq .Lbpreinc2 488 1.1 christos fail 489 1.1 christos .Lbpreinc2: 490 1.1 christos mov.b #0xa5, @byte_dest 491 1.1 christos 492 1.1 christos shlr_b_predec_2: 493 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 494 1.1 christos set_ccr_zero 495 1.1 christos 496 1.1 christos mov #byte_dest+1, er0 497 1.1 christos shlr.b #2, @-er0 ; shift right logical by two, predec 498 1.1 christos ;;; .word 0x0177 499 1.1 christos ;;; .word 0x6c08 500 1.1 christos ;;; .word 0x1140 501 1.1 christos 502 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 503 1.1 christos test_zero_clear 504 1.1 christos test_ovf_clear 505 1.1 christos test_neg_clear 506 1.1 christos 507 1.1 christos test_h_gr32 byte_dest er0 508 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 509 1.1 christos test_gr_a5a5 2 510 1.1 christos test_gr_a5a5 3 511 1.1 christos test_gr_a5a5 4 512 1.1 christos test_gr_a5a5 5 513 1.1 christos test_gr_a5a5 6 514 1.1 christos test_gr_a5a5 7 515 1.1 christos ; 1010 0101 -> 0010 1001 516 1.1 christos cmp.b #0x29, @byte_dest 517 1.1 christos beq .Lbpredec2 518 1.1 christos fail 519 1.1 christos .Lbpredec2: 520 1.1 christos mov.b #0xa5, @byte_dest 521 1.1 christos 522 1.1 christos shlr_b_disp2_2: 523 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 524 1.1 christos set_ccr_zero 525 1.1 christos 526 1.1 christos mov #byte_dest-2, er0 527 1.1 christos shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 528 1.1 christos ;;; .word 0x0176 529 1.1 christos ;;; .word 0x6808 530 1.1 christos ;;; .word 0x1140 531 1.1 christos 532 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 533 1.1 christos test_zero_clear 534 1.1 christos test_ovf_clear 535 1.1 christos test_neg_clear 536 1.1 christos 537 1.1 christos test_h_gr32 byte_dest-2 er0 538 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 539 1.1 christos test_gr_a5a5 2 540 1.1 christos test_gr_a5a5 3 541 1.1 christos test_gr_a5a5 4 542 1.1 christos test_gr_a5a5 5 543 1.1 christos test_gr_a5a5 6 544 1.1 christos test_gr_a5a5 7 545 1.1 christos ; 1010 0101 -> 0010 1001 546 1.1 christos cmp.b #0x29, @byte_dest 547 1.1 christos beq .Lbdisp22 548 1.1 christos fail 549 1.1 christos .Lbdisp22: 550 1.1 christos mov.b #0xa5, @byte_dest 551 1.1 christos 552 1.1 christos shlr_b_disp16_2: 553 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 554 1.1 christos set_ccr_zero 555 1.1 christos 556 1.1 christos mov #byte_dest-44, er0 557 1.1 christos shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 558 1.1 christos ;;; .word 0x0174 559 1.1 christos ;;; .word 0x6e08 560 1.1 christos ;;; .word 44 561 1.1 christos ;;; .word 0x1140 562 1.1 christos 563 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 564 1.1 christos test_zero_clear 565 1.1 christos test_ovf_clear 566 1.1 christos test_neg_clear 567 1.1 christos 568 1.1 christos test_h_gr32 byte_dest-44 er0 569 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 570 1.1 christos test_gr_a5a5 2 571 1.1 christos test_gr_a5a5 3 572 1.1 christos test_gr_a5a5 4 573 1.1 christos test_gr_a5a5 5 574 1.1 christos test_gr_a5a5 6 575 1.1 christos test_gr_a5a5 7 576 1.1 christos ; 1010 0101 -> 0010 1001 577 1.1 christos cmp.b #0x29, @byte_dest 578 1.1 christos beq .Lbdisp162 579 1.1 christos fail 580 1.1 christos .Lbdisp162: 581 1.1 christos mov.b #0xa5, @byte_dest 582 1.1 christos 583 1.1 christos shlr_b_disp32_2: 584 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 585 1.1 christos set_ccr_zero 586 1.1 christos 587 1.1 christos mov #byte_dest-666, er0 588 1.1 christos shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 589 1.1 christos ;;; .word 0x7884 590 1.1 christos ;;; .word 0x6a28 591 1.1 christos ;;; .long 666 592 1.1 christos ;;; .word 0x1140 593 1.1 christos 594 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 595 1.1 christos test_zero_clear 596 1.1 christos test_ovf_clear 597 1.1 christos test_neg_clear 598 1.1 christos 599 1.1 christos test_h_gr32 byte_dest-666 er0 600 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 601 1.1 christos test_gr_a5a5 2 602 1.1 christos test_gr_a5a5 3 603 1.1 christos test_gr_a5a5 4 604 1.1 christos test_gr_a5a5 5 605 1.1 christos test_gr_a5a5 6 606 1.1 christos test_gr_a5a5 7 607 1.1 christos ; 1010 0101 -> 0010 1001 608 1.1 christos cmp.b #0x29, @byte_dest 609 1.1 christos beq .Lbdisp322 610 1.1 christos fail 611 1.1 christos .Lbdisp322: 612 1.1 christos mov.b #0xa5, @byte_dest 613 1.1 christos 614 1.1 christos shlr_b_abs16_2: 615 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 616 1.1 christos set_ccr_zero 617 1.1 christos 618 1.1 christos shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 619 1.1 christos ;;; .word 0x6a18 620 1.1 christos ;;; .word byte_dest 621 1.1 christos ;;; .word 0x1140 622 1.1 christos 623 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 624 1.1 christos test_zero_clear 625 1.1 christos test_ovf_clear 626 1.1 christos test_neg_clear 627 1.1 christos 628 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 629 1.1 christos test_gr_a5a5 2 630 1.1 christos test_gr_a5a5 2 631 1.1 christos test_gr_a5a5 3 632 1.1 christos test_gr_a5a5 4 633 1.1 christos test_gr_a5a5 5 634 1.1 christos test_gr_a5a5 6 635 1.1 christos test_gr_a5a5 7 636 1.1 christos ; 1010 0101 -> 0010 1001 637 1.1 christos cmp.b #0x29, @byte_dest 638 1.1 christos beq .Lbabs162 639 1.1 christos fail 640 1.1 christos .Lbabs162: 641 1.1 christos mov.b #0xa5, @byte_dest 642 1.1 christos 643 1.1 christos shlr_b_abs32_2: 644 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 645 1.1 christos set_ccr_zero 646 1.1 christos 647 1.1 christos shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 648 1.1 christos ;;; .word 0x6a38 649 1.1 christos ;;; .long byte_dest 650 1.1 christos ;;; .word 0x1140 651 1.1 christos 652 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 653 1.1 christos test_zero_clear 654 1.1 christos test_ovf_clear 655 1.1 christos test_neg_clear 656 1.1 christos 657 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 658 1.1 christos test_gr_a5a5 2 659 1.1 christos test_gr_a5a5 2 660 1.1 christos test_gr_a5a5 3 661 1.1 christos test_gr_a5a5 4 662 1.1 christos test_gr_a5a5 5 663 1.1 christos test_gr_a5a5 6 664 1.1 christos test_gr_a5a5 7 665 1.1 christos ; 1010 0101 -> 0010 1001 666 1.1 christos cmp.b #0x29, @byte_dest 667 1.1 christos beq .Lbabs322 668 1.1 christos fail 669 1.1 christos .Lbabs322: 670 1.1 christos mov.b #0xa5, @byte_dest 671 1.1 christos 672 1.1 christos shlr_b_reg8_4: 673 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 674 1.1 christos set_ccr_zero 675 1.1 christos 676 1.1 christos shlr.b #4, r0l ; shift right logical by four 677 1.1 christos ;;; .word 0x11a8 678 1.1 christos 679 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 680 1.1 christos test_zero_clear 681 1.1 christos test_ovf_clear 682 1.1 christos test_neg_clear 683 1.1 christos 684 1.1 christos test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 685 1.1 christos test_h_gr32 0xa5a5a50a er0 686 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 687 1.1 christos test_gr_a5a5 2 688 1.1 christos test_gr_a5a5 3 689 1.1 christos test_gr_a5a5 4 690 1.1 christos test_gr_a5a5 5 691 1.1 christos test_gr_a5a5 6 692 1.1 christos test_gr_a5a5 7 693 1.1 christos 694 1.1 christos shlr_b_reg8_reg8: 695 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 696 1.1 christos set_ccr_zero 697 1.1 christos 698 1.1 christos mov #5, r0h 699 1.1 christos shlr.b r0h, r0l ; shift right logical by register value 700 1.1 christos 701 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 702 1.1 christos test_zero_clear 703 1.1 christos test_ovf_clear 704 1.1 christos test_neg_clear 705 1.1 christos 706 1.1 christos test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 707 1.1 christos test_h_gr32 0xa5a50505 er0 708 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 709 1.1 christos test_gr_a5a5 2 710 1.1 christos test_gr_a5a5 3 711 1.1 christos test_gr_a5a5 4 712 1.1 christos test_gr_a5a5 5 713 1.1 christos test_gr_a5a5 6 714 1.1 christos test_gr_a5a5 7 715 1.1 christos 716 1.1 christos shlr_b_ind_4: 717 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 718 1.1 christos set_ccr_zero 719 1.1 christos 720 1.1 christos mov #byte_dest, er0 721 1.1 christos shlr.b #4, @er0 ; shift right logical by four, indirect 722 1.1 christos ;;; .word 0x7d00 723 1.1 christos ;;; .word 0x11a0 724 1.1 christos 725 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 726 1.1 christos test_zero_clear 727 1.1 christos test_ovf_clear 728 1.1 christos test_neg_clear 729 1.1 christos 730 1.1 christos test_h_gr32 byte_dest er0 731 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 732 1.1 christos test_gr_a5a5 2 733 1.1 christos test_gr_a5a5 3 734 1.1 christos test_gr_a5a5 4 735 1.1 christos test_gr_a5a5 5 736 1.1 christos test_gr_a5a5 6 737 1.1 christos test_gr_a5a5 7 738 1.1 christos ; 1010 0101 -> 0000 1010 739 1.1 christos cmp.b #0x0a, @byte_dest 740 1.1 christos beq .Lbind4 741 1.1 christos fail 742 1.1 christos .Lbind4: 743 1.1 christos mov.b #0xa5, @byte_dest 744 1.1 christos 745 1.1 christos shlr_b_postinc_4: 746 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 747 1.1 christos set_ccr_zero 748 1.1 christos 749 1.1 christos mov #byte_dest, er0 750 1.1 christos shlr.b #4, @er0+ ; shift right logical by four, postinc 751 1.1 christos ;;; .word 0x0174 752 1.1 christos ;;; .word 0x6c08 753 1.1 christos ;;; .word 0x11a0 754 1.1 christos 755 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 756 1.1 christos test_zero_clear 757 1.1 christos test_ovf_clear 758 1.1 christos test_neg_clear 759 1.1 christos 760 1.1 christos test_h_gr32 byte_dest+1 er0 761 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 762 1.1 christos test_gr_a5a5 2 763 1.1 christos test_gr_a5a5 3 764 1.1 christos test_gr_a5a5 4 765 1.1 christos test_gr_a5a5 5 766 1.1 christos test_gr_a5a5 6 767 1.1 christos test_gr_a5a5 7 768 1.1 christos ; 1010 0101 -> 0000 1010 769 1.1 christos cmp.b #0x0a, @byte_dest 770 1.1 christos beq .Lbpostinc4 771 1.1 christos fail 772 1.1 christos .Lbpostinc4: 773 1.1 christos mov.b #0xa5, @byte_dest 774 1.1 christos 775 1.1 christos shlr_b_postdec_4: 776 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 777 1.1 christos set_ccr_zero 778 1.1 christos 779 1.1 christos mov #byte_dest, er0 780 1.1 christos shlr.b #4, @er0- ; shift right logical by four, postdec 781 1.1 christos ;;; .word 0x0176 782 1.1 christos ;;; .word 0x6c08 783 1.1 christos ;;; .word 0x11a0 784 1.1 christos 785 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 786 1.1 christos test_zero_clear 787 1.1 christos test_ovf_clear 788 1.1 christos test_neg_clear 789 1.1 christos 790 1.1 christos test_h_gr32 byte_dest-1 er0 791 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 792 1.1 christos test_gr_a5a5 2 793 1.1 christos test_gr_a5a5 3 794 1.1 christos test_gr_a5a5 4 795 1.1 christos test_gr_a5a5 5 796 1.1 christos test_gr_a5a5 6 797 1.1 christos test_gr_a5a5 7 798 1.1 christos ; 1010 0101 -> 0000 1010 799 1.1 christos cmp.b #0x0a, @byte_dest 800 1.1 christos beq .Lbpostdec4 801 1.1 christos fail 802 1.1 christos .Lbpostdec4: 803 1.1 christos mov.b #0xa5, @byte_dest 804 1.1 christos 805 1.1 christos shlr_b_preinc_4: 806 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 807 1.1 christos set_ccr_zero 808 1.1 christos 809 1.1 christos mov #byte_dest-1, er0 810 1.1 christos shlr.b #4, @+er0 ; shift right logical by four, preinc 811 1.1 christos ;;; .word 0x0175 812 1.1 christos ;;; .word 0x6c08 813 1.1 christos ;;; .word 0x11a0 814 1.1 christos 815 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 816 1.1 christos test_zero_clear 817 1.1 christos test_ovf_clear 818 1.1 christos test_neg_clear 819 1.1 christos 820 1.1 christos test_h_gr32 byte_dest er0 821 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 822 1.1 christos test_gr_a5a5 2 823 1.1 christos test_gr_a5a5 3 824 1.1 christos test_gr_a5a5 4 825 1.1 christos test_gr_a5a5 5 826 1.1 christos test_gr_a5a5 6 827 1.1 christos test_gr_a5a5 7 828 1.1 christos ; 1010 0101 -> 0000 1010 829 1.1 christos cmp.b #0x0a, @byte_dest 830 1.1 christos beq .Lbpreinc4 831 1.1 christos fail 832 1.1 christos .Lbpreinc4: 833 1.1 christos mov.b #0xa5, @byte_dest 834 1.1 christos 835 1.1 christos shlr_b_predec_4: 836 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 837 1.1 christos set_ccr_zero 838 1.1 christos 839 1.1 christos mov #byte_dest+1, er0 840 1.1 christos shlr.b #4, @-er0 ; shift right logical by four, predec 841 1.1 christos ;;; .word 0x0177 842 1.1 christos ;;; .word 0x6c08 843 1.1 christos ;;; .word 0x11a0 844 1.1 christos 845 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 846 1.1 christos test_zero_clear 847 1.1 christos test_ovf_clear 848 1.1 christos test_neg_clear 849 1.1 christos 850 1.1 christos test_h_gr32 byte_dest er0 851 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 852 1.1 christos test_gr_a5a5 2 853 1.1 christos test_gr_a5a5 3 854 1.1 christos test_gr_a5a5 4 855 1.1 christos test_gr_a5a5 5 856 1.1 christos test_gr_a5a5 6 857 1.1 christos test_gr_a5a5 7 858 1.1 christos ; 1010 0101 -> 0000 1010 859 1.1 christos cmp.b #0x0a, @byte_dest 860 1.1 christos beq .Lbpredec4 861 1.1 christos fail 862 1.1 christos .Lbpredec4: 863 1.1 christos mov.b #0xa5, @byte_dest 864 1.1 christos 865 1.1 christos shlr_b_disp2_4: 866 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 867 1.1 christos set_ccr_zero 868 1.1 christos 869 1.1 christos mov #byte_dest-2, er0 870 1.1 christos shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 871 1.1 christos ;;; .word 0x0176 872 1.1 christos ;;; .word 0x6808 873 1.1 christos ;;; .word 0x11a0 874 1.1 christos 875 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 876 1.1 christos test_zero_clear 877 1.1 christos test_ovf_clear 878 1.1 christos test_neg_clear 879 1.1 christos 880 1.1 christos test_h_gr32 byte_dest-2 er0 881 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 882 1.1 christos test_gr_a5a5 2 883 1.1 christos test_gr_a5a5 3 884 1.1 christos test_gr_a5a5 4 885 1.1 christos test_gr_a5a5 5 886 1.1 christos test_gr_a5a5 6 887 1.1 christos test_gr_a5a5 7 888 1.1 christos ; 1010 0101 -> 0000 1010 889 1.1 christos cmp.b #0x0a, @byte_dest 890 1.1 christos beq .Lbdisp24 891 1.1 christos fail 892 1.1 christos .Lbdisp24: 893 1.1 christos mov.b #0xa5, @byte_dest 894 1.1 christos 895 1.1 christos shlr_b_disp16_4: 896 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 897 1.1 christos set_ccr_zero 898 1.1 christos 899 1.1 christos mov #byte_dest-44, er0 900 1.1 christos shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 901 1.1 christos ;;; .word 0x0174 902 1.1 christos ;;; .word 0x6e08 903 1.1 christos ;;; .word 44 904 1.1 christos ;;; .word 0x11a0 905 1.1 christos 906 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 907 1.1 christos test_zero_clear 908 1.1 christos test_ovf_clear 909 1.1 christos test_neg_clear 910 1.1 christos 911 1.1 christos test_h_gr32 byte_dest-44 er0 912 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 913 1.1 christos test_gr_a5a5 2 914 1.1 christos test_gr_a5a5 3 915 1.1 christos test_gr_a5a5 4 916 1.1 christos test_gr_a5a5 5 917 1.1 christos test_gr_a5a5 6 918 1.1 christos test_gr_a5a5 7 919 1.1 christos ; 1010 0101 -> 0000 1010 920 1.1 christos cmp.b #0x0a, @byte_dest 921 1.1 christos beq .Lbdisp164 922 1.1 christos fail 923 1.1 christos .Lbdisp164: 924 1.1 christos mov.b #0xa5, @byte_dest 925 1.1 christos 926 1.1 christos shlr_b_disp32_4: 927 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 928 1.1 christos set_ccr_zero 929 1.1 christos 930 1.1 christos mov #byte_dest-666, er0 931 1.1 christos shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 932 1.1 christos ;;; .word 0x7884 933 1.1 christos ;;; .word 0x6a28 934 1.1 christos ;;; .long 666 935 1.1 christos ;;; .word 0x11a0 936 1.1 christos 937 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 938 1.1 christos test_zero_clear 939 1.1 christos test_ovf_clear 940 1.1 christos test_neg_clear 941 1.1 christos 942 1.1 christos test_h_gr32 byte_dest-666 er0 943 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 944 1.1 christos test_gr_a5a5 2 945 1.1 christos test_gr_a5a5 3 946 1.1 christos test_gr_a5a5 4 947 1.1 christos test_gr_a5a5 5 948 1.1 christos test_gr_a5a5 6 949 1.1 christos test_gr_a5a5 7 950 1.1 christos ; 1010 0101 -> 0000 1010 951 1.1 christos cmp.b #0x0a, @byte_dest 952 1.1 christos beq .Lbdisp324 953 1.1 christos fail 954 1.1 christos .Lbdisp324: 955 1.1 christos mov.b #0xa5, @byte_dest 956 1.1 christos 957 1.1 christos shlr_b_abs16_4: 958 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 959 1.1 christos set_ccr_zero 960 1.1 christos 961 1.1 christos shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 962 1.1 christos ;;; .word 0x6a18 963 1.1 christos ;;; .word byte_dest 964 1.1 christos ;;; .word 0x11a0 965 1.1 christos 966 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 967 1.1 christos test_zero_clear 968 1.1 christos test_ovf_clear 969 1.1 christos test_neg_clear 970 1.1 christos 971 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 972 1.1 christos test_gr_a5a5 2 973 1.1 christos test_gr_a5a5 2 974 1.1 christos test_gr_a5a5 3 975 1.1 christos test_gr_a5a5 4 976 1.1 christos test_gr_a5a5 5 977 1.1 christos test_gr_a5a5 6 978 1.1 christos test_gr_a5a5 7 979 1.1 christos ; 1010 0101 -> 0000 1010 980 1.1 christos cmp.b #0x0a, @byte_dest 981 1.1 christos beq .Lbabs164 982 1.1 christos fail 983 1.1 christos .Lbabs164: 984 1.1 christos mov.b #0xa5, @byte_dest 985 1.1 christos 986 1.1 christos shlr_b_abs32_4: 987 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 988 1.1 christos set_ccr_zero 989 1.1 christos 990 1.1 christos shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 991 1.1 christos ;;; .word 0x6a38 992 1.1 christos ;;; .long byte_dest 993 1.1 christos ;;; .word 0x11a0 994 1.1 christos 995 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 996 1.1 christos test_zero_clear 997 1.1 christos test_ovf_clear 998 1.1 christos test_neg_clear 999 1.1 christos 1000 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1001 1.1 christos test_gr_a5a5 2 1002 1.1 christos test_gr_a5a5 2 1003 1.1 christos test_gr_a5a5 3 1004 1.1 christos test_gr_a5a5 4 1005 1.1 christos test_gr_a5a5 5 1006 1.1 christos test_gr_a5a5 6 1007 1.1 christos test_gr_a5a5 7 1008 1.1 christos ; 1010 0101 -> 0000 1010 1009 1.1 christos cmp.b #0x0a, @byte_dest 1010 1.1 christos beq .Lbabs324 1011 1.1 christos fail 1012 1.1 christos .Lbabs324: 1013 1.1 christos mov.b #0xa5, @byte_dest 1014 1.1 christos .endif 1015 1.1 christos 1016 1.1 christos .if (sim_cpu == h8sx) 1017 1.1 christos shlr_w_imm5_1: 1018 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1019 1.1 christos set_ccr_zero 1020 1.1 christos 1021 1.1 christos shlr.w #15:5, r0 ; shift right logical by 5-bit immediate 1022 1.1 christos ;;; .word 0x038f 1023 1.1 christos ;;; .word 0x1110 1024 1.1 christos 1025 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1026 1.1 christos test_zero_clear 1027 1.1 christos test_ovf_clear 1028 1.1 christos test_neg_clear 1029 1.1 christos 1030 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 1031 1.1 christos test_h_gr32 0xa5a50001 er0 1032 1.1 christos 1033 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1034 1.1 christos test_gr_a5a5 2 1035 1.1 christos test_gr_a5a5 3 1036 1.1 christos test_gr_a5a5 4 1037 1.1 christos test_gr_a5a5 5 1038 1.1 christos test_gr_a5a5 6 1039 1.1 christos test_gr_a5a5 7 1040 1.1 christos .endif 1041 1.1 christos 1042 1.1 christos .if (sim_cpu) ; Not available in h8300 mode 1043 1.1 christos shlr_w_reg16_1: 1044 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1045 1.1 christos set_ccr_zero 1046 1.1 christos 1047 1.1 christos shlr.w r0 ; shift right logical by one 1048 1.1 christos ;;; .word 0x1110 1049 1.1 christos 1050 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1051 1.1 christos test_zero_clear 1052 1.1 christos test_ovf_clear 1053 1.1 christos test_neg_clear 1054 1.1 christos test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1055 1.1 christos test_h_gr32 0xa5a552d2 er0 1056 1.1 christos 1057 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1058 1.1 christos test_gr_a5a5 2 1059 1.1 christos test_gr_a5a5 3 1060 1.1 christos test_gr_a5a5 4 1061 1.1 christos test_gr_a5a5 5 1062 1.1 christos test_gr_a5a5 6 1063 1.1 christos test_gr_a5a5 7 1064 1.1 christos 1065 1.1 christos .if (sim_cpu == h8sx) 1066 1.1 christos shlr_w_ind_1: 1067 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1068 1.1 christos set_ccr_zero 1069 1.1 christos 1070 1.1 christos mov #word_dest, er0 1071 1.1 christos shlr.w @er0 ; shift right logical by one, indirect 1072 1.1 christos ;;; .word 0x7d80 1073 1.1 christos ;;; .word 0x1110 1074 1.1 christos 1075 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1076 1.1 christos test_zero_clear 1077 1.1 christos test_ovf_clear 1078 1.1 christos test_neg_clear 1079 1.1 christos 1080 1.1 christos test_h_gr32 word_dest er0 1081 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1082 1.1 christos test_gr_a5a5 2 1083 1.1 christos test_gr_a5a5 3 1084 1.1 christos test_gr_a5a5 4 1085 1.1 christos test_gr_a5a5 5 1086 1.1 christos test_gr_a5a5 6 1087 1.1 christos test_gr_a5a5 7 1088 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1089 1.1 christos cmp.w #0x52d2, @word_dest 1090 1.1 christos beq .Lwind1 1091 1.1 christos fail 1092 1.1 christos .Lwind1: 1093 1.1 christos mov.w #0xa5a5, @word_dest 1094 1.1 christos 1095 1.1 christos shlr_w_postinc_1: 1096 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1097 1.1 christos set_ccr_zero 1098 1.1 christos 1099 1.1 christos mov #word_dest, er0 1100 1.1 christos shlr.w @er0+ ; shift right logical by one, postinc 1101 1.1 christos ;;; .word 0x0154 1102 1.1 christos ;;; .word 0x6d08 1103 1.1 christos ;;; .word 0x1110 1104 1.1 christos 1105 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1106 1.1 christos test_zero_clear 1107 1.1 christos test_ovf_clear 1108 1.1 christos test_neg_clear 1109 1.1 christos 1110 1.1 christos test_h_gr32 word_dest+2 er0 1111 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1112 1.1 christos test_gr_a5a5 2 1113 1.1 christos test_gr_a5a5 3 1114 1.1 christos test_gr_a5a5 4 1115 1.1 christos test_gr_a5a5 5 1116 1.1 christos test_gr_a5a5 6 1117 1.1 christos test_gr_a5a5 7 1118 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1119 1.1 christos cmp.w #0x52d2, @word_dest 1120 1.1 christos beq .Lwpostinc1 1121 1.1 christos fail 1122 1.1 christos .Lwpostinc1: 1123 1.1 christos mov.w #0xa5a5, @word_dest 1124 1.1 christos 1125 1.1 christos shlr_w_postdec_1: 1126 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1127 1.1 christos set_ccr_zero 1128 1.1 christos 1129 1.1 christos mov #word_dest, er0 1130 1.1 christos shlr.w @er0- ; shift right logical by one, postdec 1131 1.1 christos ;;; .word 0x0156 1132 1.1 christos ;;; .word 0x6d08 1133 1.1 christos ;;; .word 0x1110 1134 1.1 christos 1135 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1136 1.1 christos test_zero_clear 1137 1.1 christos test_ovf_clear 1138 1.1 christos test_neg_clear 1139 1.1 christos 1140 1.1 christos test_h_gr32 word_dest-2 er0 1141 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1142 1.1 christos test_gr_a5a5 2 1143 1.1 christos test_gr_a5a5 3 1144 1.1 christos test_gr_a5a5 4 1145 1.1 christos test_gr_a5a5 5 1146 1.1 christos test_gr_a5a5 6 1147 1.1 christos test_gr_a5a5 7 1148 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1149 1.1 christos cmp.w #0x52d2, @word_dest 1150 1.1 christos beq .Lwpostdec1 1151 1.1 christos fail 1152 1.1 christos .Lwpostdec1: 1153 1.1 christos mov.w #0xa5a5, @word_dest 1154 1.1 christos 1155 1.1 christos shlr_w_preinc_1: 1156 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1157 1.1 christos set_ccr_zero 1158 1.1 christos 1159 1.1 christos mov #word_dest-2, er0 1160 1.1 christos shlr.w @+er0 ; shift right logical by one, preinc 1161 1.1 christos ;;; .word 0x0155 1162 1.1 christos ;;; .word 0x6d08 1163 1.1 christos ;;; .word 0x1110 1164 1.1 christos 1165 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1166 1.1 christos test_zero_clear 1167 1.1 christos test_ovf_clear 1168 1.1 christos test_neg_clear 1169 1.1 christos 1170 1.1 christos test_h_gr32 word_dest er0 1171 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1172 1.1 christos test_gr_a5a5 2 1173 1.1 christos test_gr_a5a5 3 1174 1.1 christos test_gr_a5a5 4 1175 1.1 christos test_gr_a5a5 5 1176 1.1 christos test_gr_a5a5 6 1177 1.1 christos test_gr_a5a5 7 1178 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1179 1.1 christos cmp.w #0x52d2, @word_dest 1180 1.1 christos beq .Lwpreinc1 1181 1.1 christos fail 1182 1.1 christos .Lwpreinc1: 1183 1.1 christos mov.w #0xa5a5, @word_dest 1184 1.1 christos 1185 1.1 christos shlr_w_predec_1: 1186 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1187 1.1 christos set_ccr_zero 1188 1.1 christos 1189 1.1 christos mov #word_dest+2, er0 1190 1.1 christos shlr.w @-er0 ; shift right logical by one, predec 1191 1.1 christos ;;; .word 0x0157 1192 1.1 christos ;;; .word 0x6d08 1193 1.1 christos ;;; .word 0x1110 1194 1.1 christos 1195 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1196 1.1 christos test_zero_clear 1197 1.1 christos test_ovf_clear 1198 1.1 christos test_neg_clear 1199 1.1 christos 1200 1.1 christos test_h_gr32 word_dest er0 1201 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1202 1.1 christos test_gr_a5a5 2 1203 1.1 christos test_gr_a5a5 3 1204 1.1 christos test_gr_a5a5 4 1205 1.1 christos test_gr_a5a5 5 1206 1.1 christos test_gr_a5a5 6 1207 1.1 christos test_gr_a5a5 7 1208 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1209 1.1 christos cmp.w #0x52d2, @word_dest 1210 1.1 christos beq .Lwpredec1 1211 1.1 christos fail 1212 1.1 christos .Lwpredec1: 1213 1.1 christos mov.w #0xa5a5, @word_dest 1214 1.1 christos 1215 1.1 christos shlr_w_disp2_1: 1216 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1217 1.1 christos set_ccr_zero 1218 1.1 christos 1219 1.1 christos mov #word_dest-4, er0 1220 1.1 christos shlr.w @(4:2, er0) ; shift right logical by one, disp2 1221 1.1 christos ;;; .word 0x0156 1222 1.1 christos ;;; .word 0x6908 1223 1.1 christos ;;; .word 0x1110 1224 1.1 christos 1225 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1226 1.1 christos test_zero_clear 1227 1.1 christos test_ovf_clear 1228 1.1 christos test_neg_clear 1229 1.1 christos 1230 1.1 christos test_h_gr32 word_dest-4 er0 1231 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1232 1.1 christos test_gr_a5a5 2 1233 1.1 christos test_gr_a5a5 3 1234 1.1 christos test_gr_a5a5 4 1235 1.1 christos test_gr_a5a5 5 1236 1.1 christos test_gr_a5a5 6 1237 1.1 christos test_gr_a5a5 7 1238 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1239 1.1 christos cmp.w #0x52d2, @word_dest 1240 1.1 christos beq .Lwdisp21 1241 1.1 christos fail 1242 1.1 christos .Lwdisp21: 1243 1.1 christos mov.w #0xa5a5, @word_dest 1244 1.1 christos 1245 1.1 christos shlr_w_disp16_1: 1246 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1247 1.1 christos set_ccr_zero 1248 1.1 christos 1249 1.1 christos mov #word_dest-44, er0 1250 1.1 christos shlr.w @(44:16, er0) ; shift right logical by one, disp16 1251 1.1 christos ;;; .word 0x0154 1252 1.1 christos ;;; .word 0x6f08 1253 1.1 christos ;;; .word 44 1254 1.1 christos ;;; .word 0x1110 1255 1.1 christos 1256 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1257 1.1 christos test_zero_clear 1258 1.1 christos test_ovf_clear 1259 1.1 christos test_neg_clear 1260 1.1 christos 1261 1.1 christos test_h_gr32 word_dest-44 er0 1262 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1263 1.1 christos test_gr_a5a5 2 1264 1.1 christos test_gr_a5a5 3 1265 1.1 christos test_gr_a5a5 4 1266 1.1 christos test_gr_a5a5 5 1267 1.1 christos test_gr_a5a5 6 1268 1.1 christos test_gr_a5a5 7 1269 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1270 1.1 christos cmp.w #0x52d2, @word_dest 1271 1.1 christos beq .Lwdisp161 1272 1.1 christos fail 1273 1.1 christos .Lwdisp161: 1274 1.1 christos mov.w #0xa5a5, @word_dest 1275 1.1 christos 1276 1.1 christos shlr_w_disp32_1: 1277 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1278 1.1 christos set_ccr_zero 1279 1.1 christos 1280 1.1 christos mov #word_dest-666, er0 1281 1.1 christos shlr.w @(666:32, er0) ; shift right logical by one, disp32 1282 1.1 christos ;;; .word 0x7884 1283 1.1 christos ;;; .word 0x6b28 1284 1.1 christos ;;; .long 666 1285 1.1 christos ;;; .word 0x1110 1286 1.1 christos 1287 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1288 1.1 christos test_zero_clear 1289 1.1 christos test_ovf_clear 1290 1.1 christos test_neg_clear 1291 1.1 christos 1292 1.1 christos test_h_gr32 word_dest-666 er0 1293 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1294 1.1 christos test_gr_a5a5 2 1295 1.1 christos test_gr_a5a5 3 1296 1.1 christos test_gr_a5a5 4 1297 1.1 christos test_gr_a5a5 5 1298 1.1 christos test_gr_a5a5 6 1299 1.1 christos test_gr_a5a5 7 1300 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1301 1.1 christos cmp.w #0x52d2, @word_dest 1302 1.1 christos beq .Lwdisp321 1303 1.1 christos fail 1304 1.1 christos .Lwdisp321: 1305 1.1 christos mov.w #0xa5a5, @word_dest 1306 1.1 christos 1307 1.1 christos shlr_w_abs16_1: 1308 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1309 1.1 christos set_ccr_zero 1310 1.1 christos 1311 1.1 christos shlr.w @word_dest:16 ; shift right logical by one, abs16 1312 1.1 christos ;;; .word 0x6b18 1313 1.1 christos ;;; .word word_dest 1314 1.1 christos ;;; .word 0x1110 1315 1.1 christos 1316 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1317 1.1 christos test_zero_clear 1318 1.1 christos test_ovf_clear 1319 1.1 christos test_neg_clear 1320 1.1 christos 1321 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1322 1.1 christos test_gr_a5a5 1 1323 1.1 christos test_gr_a5a5 2 1324 1.1 christos test_gr_a5a5 3 1325 1.1 christos test_gr_a5a5 4 1326 1.1 christos test_gr_a5a5 5 1327 1.1 christos test_gr_a5a5 6 1328 1.1 christos test_gr_a5a5 7 1329 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1330 1.1 christos cmp.w #0x52d2, @word_dest 1331 1.1 christos beq .Lwabs161 1332 1.1 christos fail 1333 1.1 christos .Lwabs161: 1334 1.1 christos mov.w #0xa5a5, @word_dest 1335 1.1 christos 1336 1.1 christos shlr_w_abs32_1: 1337 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1338 1.1 christos set_ccr_zero 1339 1.1 christos 1340 1.1 christos shlr.w @word_dest:32 ; shift right logical by one, abs32 1341 1.1 christos ;;; .word 0x6b38 1342 1.1 christos ;;; .long word_dest 1343 1.1 christos ;;; .word 0x1110 1344 1.1 christos 1345 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1346 1.1 christos test_zero_clear 1347 1.1 christos test_ovf_clear 1348 1.1 christos test_neg_clear 1349 1.1 christos 1350 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1351 1.1 christos test_gr_a5a5 1 1352 1.1 christos test_gr_a5a5 2 1353 1.1 christos test_gr_a5a5 3 1354 1.1 christos test_gr_a5a5 4 1355 1.1 christos test_gr_a5a5 5 1356 1.1 christos test_gr_a5a5 6 1357 1.1 christos test_gr_a5a5 7 1358 1.1 christos ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1359 1.1 christos cmp.w #0x52d2, @word_dest 1360 1.1 christos beq .Lwabs321 1361 1.1 christos fail 1362 1.1 christos .Lwabs321: 1363 1.1 christos mov.w #0xa5a5, @word_dest 1364 1.1 christos .endif 1365 1.1 christos 1366 1.1 christos shlr_w_reg16_2: 1367 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1368 1.1 christos set_ccr_zero 1369 1.1 christos 1370 1.1 christos shlr.w #2, r0 ; shift right logical by two 1371 1.1 christos ;;; .word 0x1150 1372 1.1 christos 1373 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1374 1.1 christos test_zero_clear 1375 1.1 christos test_ovf_clear 1376 1.1 christos test_neg_clear 1377 1.1 christos 1378 1.1 christos test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1379 1.1 christos test_h_gr32 0xa5a52969 er0 1380 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1381 1.1 christos test_gr_a5a5 2 1382 1.1 christos test_gr_a5a5 3 1383 1.1 christos test_gr_a5a5 4 1384 1.1 christos test_gr_a5a5 5 1385 1.1 christos test_gr_a5a5 6 1386 1.1 christos test_gr_a5a5 7 1387 1.1 christos 1388 1.1 christos .if (sim_cpu == h8sx) 1389 1.1 christos shlr_w_ind_2: 1390 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1391 1.1 christos set_ccr_zero 1392 1.1 christos 1393 1.1 christos mov #word_dest, er0 1394 1.1 christos shlr.w #2, @er0 ; shift right logical by two, indirect 1395 1.1 christos ;;; .word 0x7d80 1396 1.1 christos ;;; .word 0x1150 1397 1.1 christos 1398 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1399 1.1 christos test_zero_clear 1400 1.1 christos test_ovf_clear 1401 1.1 christos test_neg_clear 1402 1.1 christos 1403 1.1 christos test_h_gr32 word_dest er0 1404 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1405 1.1 christos test_gr_a5a5 2 1406 1.1 christos test_gr_a5a5 3 1407 1.1 christos test_gr_a5a5 4 1408 1.1 christos test_gr_a5a5 5 1409 1.1 christos test_gr_a5a5 6 1410 1.1 christos test_gr_a5a5 7 1411 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1412 1.1 christos cmp.w #0x2969, @word_dest 1413 1.1 christos beq .Lwind2 1414 1.1 christos fail 1415 1.1 christos .Lwind2: 1416 1.1 christos mov.w #0xa5a5, @word_dest 1417 1.1 christos 1418 1.1 christos shlr_w_postinc_2: 1419 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1420 1.1 christos set_ccr_zero 1421 1.1 christos 1422 1.1 christos mov #word_dest, er0 1423 1.1 christos shlr.w #2, @er0+ ; shift right logical by two, postinc 1424 1.1 christos ;;; .word 0x0154 1425 1.1 christos ;;; .word 0x6d08 1426 1.1 christos ;;; .word 0x1150 1427 1.1 christos 1428 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1429 1.1 christos test_zero_clear 1430 1.1 christos test_ovf_clear 1431 1.1 christos test_neg_clear 1432 1.1 christos 1433 1.1 christos test_h_gr32 word_dest+2 er0 1434 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1435 1.1 christos test_gr_a5a5 2 1436 1.1 christos test_gr_a5a5 3 1437 1.1 christos test_gr_a5a5 4 1438 1.1 christos test_gr_a5a5 5 1439 1.1 christos test_gr_a5a5 6 1440 1.1 christos test_gr_a5a5 7 1441 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1442 1.1 christos cmp.w #0x2969, @word_dest 1443 1.1 christos beq .Lwpostinc2 1444 1.1 christos fail 1445 1.1 christos .Lwpostinc2: 1446 1.1 christos mov.w #0xa5a5, @word_dest 1447 1.1 christos 1448 1.1 christos shlr_w_postdec_2: 1449 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1450 1.1 christos set_ccr_zero 1451 1.1 christos 1452 1.1 christos mov #word_dest, er0 1453 1.1 christos shlr.w #2, @er0- ; shift right logical by two, postdec 1454 1.1 christos ;;; .word 0x0156 1455 1.1 christos ;;; .word 0x6d08 1456 1.1 christos ;;; .word 0x1150 1457 1.1 christos 1458 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1459 1.1 christos test_zero_clear 1460 1.1 christos test_ovf_clear 1461 1.1 christos test_neg_clear 1462 1.1 christos 1463 1.1 christos test_h_gr32 word_dest-2 er0 1464 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1465 1.1 christos test_gr_a5a5 2 1466 1.1 christos test_gr_a5a5 3 1467 1.1 christos test_gr_a5a5 4 1468 1.1 christos test_gr_a5a5 5 1469 1.1 christos test_gr_a5a5 6 1470 1.1 christos test_gr_a5a5 7 1471 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1472 1.1 christos cmp.w #0x2969, @word_dest 1473 1.1 christos beq .Lwpostdec2 1474 1.1 christos fail 1475 1.1 christos .Lwpostdec2: 1476 1.1 christos mov.w #0xa5a5, @word_dest 1477 1.1 christos 1478 1.1 christos shlr_w_preinc_2: 1479 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1480 1.1 christos set_ccr_zero 1481 1.1 christos 1482 1.1 christos mov #word_dest-2, er0 1483 1.1 christos shlr.w #2, @+er0 ; shift right logical by two, preinc 1484 1.1 christos ;;; .word 0x0155 1485 1.1 christos ;;; .word 0x6d08 1486 1.1 christos ;;; .word 0x1150 1487 1.1 christos 1488 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1489 1.1 christos test_zero_clear 1490 1.1 christos test_ovf_clear 1491 1.1 christos test_neg_clear 1492 1.1 christos 1493 1.1 christos test_h_gr32 word_dest er0 1494 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1495 1.1 christos test_gr_a5a5 2 1496 1.1 christos test_gr_a5a5 3 1497 1.1 christos test_gr_a5a5 4 1498 1.1 christos test_gr_a5a5 5 1499 1.1 christos test_gr_a5a5 6 1500 1.1 christos test_gr_a5a5 7 1501 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1502 1.1 christos cmp.w #0x2969, @word_dest 1503 1.1 christos beq .Lwpreinc2 1504 1.1 christos fail 1505 1.1 christos .Lwpreinc2: 1506 1.1 christos mov.w #0xa5a5, @word_dest 1507 1.1 christos 1508 1.1 christos shlr_w_predec_2: 1509 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1510 1.1 christos set_ccr_zero 1511 1.1 christos 1512 1.1 christos mov #word_dest+2, er0 1513 1.1 christos shlr.w #2, @-er0 ; shift right logical by two, predec 1514 1.1 christos ;;; .word 0x0157 1515 1.1 christos ;;; .word 0x6d08 1516 1.1 christos ;;; .word 0x1150 1517 1.1 christos 1518 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1519 1.1 christos test_zero_clear 1520 1.1 christos test_ovf_clear 1521 1.1 christos test_neg_clear 1522 1.1 christos 1523 1.1 christos test_h_gr32 word_dest er0 1524 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1525 1.1 christos test_gr_a5a5 2 1526 1.1 christos test_gr_a5a5 3 1527 1.1 christos test_gr_a5a5 4 1528 1.1 christos test_gr_a5a5 5 1529 1.1 christos test_gr_a5a5 6 1530 1.1 christos test_gr_a5a5 7 1531 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1532 1.1 christos cmp.w #0x2969, @word_dest 1533 1.1 christos beq .Lwpredec2 1534 1.1 christos fail 1535 1.1 christos .Lwpredec2: 1536 1.1 christos mov.w #0xa5a5, @word_dest 1537 1.1 christos 1538 1.1 christos shlr_w_disp2_2: 1539 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1540 1.1 christos set_ccr_zero 1541 1.1 christos 1542 1.1 christos mov #word_dest-4, er0 1543 1.1 christos shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 1544 1.1 christos ;;; .word 0x0156 1545 1.1 christos ;;; .word 0x6908 1546 1.1 christos ;;; .word 0x1150 1547 1.1 christos 1548 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1549 1.1 christos test_zero_clear 1550 1.1 christos test_ovf_clear 1551 1.1 christos test_neg_clear 1552 1.1 christos 1553 1.1 christos test_h_gr32 word_dest-4 er0 1554 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1555 1.1 christos test_gr_a5a5 2 1556 1.1 christos test_gr_a5a5 3 1557 1.1 christos test_gr_a5a5 4 1558 1.1 christos test_gr_a5a5 5 1559 1.1 christos test_gr_a5a5 6 1560 1.1 christos test_gr_a5a5 7 1561 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1562 1.1 christos cmp.w #0x2969, @word_dest 1563 1.1 christos beq .Lwdisp22 1564 1.1 christos fail 1565 1.1 christos .Lwdisp22: 1566 1.1 christos mov.w #0xa5a5, @word_dest 1567 1.1 christos 1568 1.1 christos shlr_w_disp16_2: 1569 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1570 1.1 christos set_ccr_zero 1571 1.1 christos 1572 1.1 christos mov #word_dest-44, er0 1573 1.1 christos shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 1574 1.1 christos ;;; .word 0x0154 1575 1.1 christos ;;; .word 0x6f08 1576 1.1 christos ;;; .word 44 1577 1.1 christos ;;; .word 0x1150 1578 1.1 christos 1579 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1580 1.1 christos test_zero_clear 1581 1.1 christos test_ovf_clear 1582 1.1 christos test_neg_clear 1583 1.1 christos 1584 1.1 christos test_h_gr32 word_dest-44 er0 1585 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1586 1.1 christos test_gr_a5a5 2 1587 1.1 christos test_gr_a5a5 3 1588 1.1 christos test_gr_a5a5 4 1589 1.1 christos test_gr_a5a5 5 1590 1.1 christos test_gr_a5a5 6 1591 1.1 christos test_gr_a5a5 7 1592 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1593 1.1 christos cmp.w #0x2969, @word_dest 1594 1.1 christos beq .Lwdisp162 1595 1.1 christos fail 1596 1.1 christos .Lwdisp162: 1597 1.1 christos mov.w #0xa5a5, @word_dest 1598 1.1 christos 1599 1.1 christos shlr_w_disp32_2: 1600 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1601 1.1 christos set_ccr_zero 1602 1.1 christos 1603 1.1 christos mov #word_dest-666, er0 1604 1.1 christos shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 1605 1.1 christos ;;; .word 0x7884 1606 1.1 christos ;;; .word 0x6b28 1607 1.1 christos ;;; .long 666 1608 1.1 christos ;;; .word 0x1150 1609 1.1 christos 1610 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1611 1.1 christos test_zero_clear 1612 1.1 christos test_ovf_clear 1613 1.1 christos test_neg_clear 1614 1.1 christos 1615 1.1 christos test_h_gr32 word_dest-666 er0 1616 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1617 1.1 christos test_gr_a5a5 2 1618 1.1 christos test_gr_a5a5 3 1619 1.1 christos test_gr_a5a5 4 1620 1.1 christos test_gr_a5a5 5 1621 1.1 christos test_gr_a5a5 6 1622 1.1 christos test_gr_a5a5 7 1623 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1624 1.1 christos cmp.w #0x2969, @word_dest 1625 1.1 christos beq .Lwdisp322 1626 1.1 christos fail 1627 1.1 christos .Lwdisp322: 1628 1.1 christos mov.w #0xa5a5, @word_dest 1629 1.1 christos 1630 1.1 christos shlr_w_abs16_2: 1631 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1632 1.1 christos set_ccr_zero 1633 1.1 christos 1634 1.1 christos shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 1635 1.1 christos ;;; .word 0x6b18 1636 1.1 christos ;;; .word word_dest 1637 1.1 christos ;;; .word 0x1150 1638 1.1 christos 1639 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1640 1.1 christos test_zero_clear 1641 1.1 christos test_ovf_clear 1642 1.1 christos test_neg_clear 1643 1.1 christos 1644 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1645 1.1 christos test_gr_a5a5 2 1646 1.1 christos test_gr_a5a5 2 1647 1.1 christos test_gr_a5a5 3 1648 1.1 christos test_gr_a5a5 4 1649 1.1 christos test_gr_a5a5 5 1650 1.1 christos test_gr_a5a5 6 1651 1.1 christos test_gr_a5a5 7 1652 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1653 1.1 christos cmp.w #0x2969, @word_dest 1654 1.1 christos beq .Lwabs162 1655 1.1 christos fail 1656 1.1 christos .Lwabs162: 1657 1.1 christos mov.w #0xa5a5, @word_dest 1658 1.1 christos 1659 1.1 christos shlr_w_abs32_2: 1660 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1661 1.1 christos set_ccr_zero 1662 1.1 christos 1663 1.1 christos shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 1664 1.1 christos ;;; .word 0x6b38 1665 1.1 christos ;;; .long word_dest 1666 1.1 christos ;;; .word 0x1150 1667 1.1 christos 1668 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1669 1.1 christos test_zero_clear 1670 1.1 christos test_ovf_clear 1671 1.1 christos test_neg_clear 1672 1.1 christos 1673 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1674 1.1 christos test_gr_a5a5 2 1675 1.1 christos test_gr_a5a5 2 1676 1.1 christos test_gr_a5a5 3 1677 1.1 christos test_gr_a5a5 4 1678 1.1 christos test_gr_a5a5 5 1679 1.1 christos test_gr_a5a5 6 1680 1.1 christos test_gr_a5a5 7 1681 1.1 christos ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1682 1.1 christos cmp.w #0x2969, @word_dest 1683 1.1 christos beq .Lwabs322 1684 1.1 christos fail 1685 1.1 christos .Lwabs322: 1686 1.1 christos mov.w #0xa5a5, @word_dest 1687 1.1 christos 1688 1.1 christos shlr_w_reg16_4: 1689 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1690 1.1 christos set_ccr_zero 1691 1.1 christos 1692 1.1 christos shlr.w #4, r0 ; shift right logical by four 1693 1.1 christos ;;; .word 0x1120 1694 1.1 christos 1695 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1696 1.1 christos test_zero_clear 1697 1.1 christos test_ovf_clear 1698 1.1 christos test_neg_clear 1699 1.1 christos 1700 1.1 christos test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1701 1.1 christos test_h_gr32 0xa5a50a5a er0 1702 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1703 1.1 christos test_gr_a5a5 2 1704 1.1 christos test_gr_a5a5 3 1705 1.1 christos test_gr_a5a5 4 1706 1.1 christos test_gr_a5a5 5 1707 1.1 christos test_gr_a5a5 6 1708 1.1 christos test_gr_a5a5 7 1709 1.1 christos 1710 1.1 christos shlr_w_reg16_reg8: 1711 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1712 1.1 christos set_ccr_zero 1713 1.1 christos 1714 1.1 christos mov #5, r1l 1715 1.1 christos shlr.w r1l, r0 ; shift right logical by register value 1716 1.1 christos 1717 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1718 1.1 christos test_zero_clear 1719 1.1 christos test_ovf_clear 1720 1.1 christos test_neg_clear 1721 1.1 christos 1722 1.1 christos test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 1723 1.1 christos test_h_gr32 0xa5a5052d er0 1724 1.1 christos test_h_gr32 0xa5a5a505 er1 1725 1.1 christos test_gr_a5a5 2 ; Make sure other general regs not disturbed 1726 1.1 christos test_gr_a5a5 3 1727 1.1 christos test_gr_a5a5 4 1728 1.1 christos test_gr_a5a5 5 1729 1.1 christos test_gr_a5a5 6 1730 1.1 christos test_gr_a5a5 7 1731 1.1 christos 1732 1.1 christos shlr_w_ind_4: 1733 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1734 1.1 christos set_ccr_zero 1735 1.1 christos 1736 1.1 christos mov #word_dest, er0 1737 1.1 christos shlr.w #4, @er0 ; shift right logical by four, indirect 1738 1.1 christos ;;; .word 0x7d80 1739 1.1 christos ;;; .word 0x1120 1740 1.1 christos 1741 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1742 1.1 christos test_zero_clear 1743 1.1 christos test_ovf_clear 1744 1.1 christos test_neg_clear 1745 1.1 christos 1746 1.1 christos test_h_gr32 word_dest er0 1747 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1748 1.1 christos test_gr_a5a5 2 1749 1.1 christos test_gr_a5a5 3 1750 1.1 christos test_gr_a5a5 4 1751 1.1 christos test_gr_a5a5 5 1752 1.1 christos test_gr_a5a5 6 1753 1.1 christos test_gr_a5a5 7 1754 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1755 1.1 christos cmp.w #0x0a5a, @word_dest 1756 1.1 christos beq .Lwind4 1757 1.1 christos fail 1758 1.1 christos .Lwind4: 1759 1.1 christos mov.w #0xa5a5, @word_dest 1760 1.1 christos 1761 1.1 christos shlr_w_postinc_4: 1762 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1763 1.1 christos set_ccr_zero 1764 1.1 christos 1765 1.1 christos mov #word_dest, er0 1766 1.1 christos shlr.w #4, @er0+ ; shift right logical by four, postinc 1767 1.1 christos ;;; .word 0x0154 1768 1.1 christos ;;; .word 0x6d08 1769 1.1 christos ;;; .word 0x1120 1770 1.1 christos 1771 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1772 1.1 christos test_zero_clear 1773 1.1 christos test_ovf_clear 1774 1.1 christos test_neg_clear 1775 1.1 christos 1776 1.1 christos test_h_gr32 word_dest+2 er0 1777 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1778 1.1 christos test_gr_a5a5 2 1779 1.1 christos test_gr_a5a5 3 1780 1.1 christos test_gr_a5a5 4 1781 1.1 christos test_gr_a5a5 5 1782 1.1 christos test_gr_a5a5 6 1783 1.1 christos test_gr_a5a5 7 1784 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1785 1.1 christos cmp.w #0x0a5a, @word_dest 1786 1.1 christos beq .Lwpostinc4 1787 1.1 christos fail 1788 1.1 christos .Lwpostinc4: 1789 1.1 christos mov.w #0xa5a5, @word_dest 1790 1.1 christos 1791 1.1 christos shlr_w_postdec_4: 1792 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1793 1.1 christos set_ccr_zero 1794 1.1 christos 1795 1.1 christos mov #word_dest, er0 1796 1.1 christos shlr.w #4, @er0- ; shift right logical by four, postdec 1797 1.1 christos ;;; .word 0x0156 1798 1.1 christos ;;; .word 0x6d08 1799 1.1 christos ;;; .word 0x1120 1800 1.1 christos 1801 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1802 1.1 christos test_zero_clear 1803 1.1 christos test_ovf_clear 1804 1.1 christos test_neg_clear 1805 1.1 christos 1806 1.1 christos test_h_gr32 word_dest-2 er0 1807 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1808 1.1 christos test_gr_a5a5 2 1809 1.1 christos test_gr_a5a5 3 1810 1.1 christos test_gr_a5a5 4 1811 1.1 christos test_gr_a5a5 5 1812 1.1 christos test_gr_a5a5 6 1813 1.1 christos test_gr_a5a5 7 1814 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1815 1.1 christos cmp.w #0x0a5a, @word_dest 1816 1.1 christos beq .Lwpostdec4 1817 1.1 christos fail 1818 1.1 christos .Lwpostdec4: 1819 1.1 christos mov.w #0xa5a5, @word_dest 1820 1.1 christos 1821 1.1 christos shlr_w_preinc_4: 1822 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1823 1.1 christos set_ccr_zero 1824 1.1 christos 1825 1.1 christos mov #word_dest-2, er0 1826 1.1 christos shlr.w #4, @+er0 ; shift right logical by four, preinc 1827 1.1 christos ;;; .word 0x0155 1828 1.1 christos ;;; .word 0x6d08 1829 1.1 christos ;;; .word 0x1120 1830 1.1 christos 1831 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1832 1.1 christos test_zero_clear 1833 1.1 christos test_ovf_clear 1834 1.1 christos test_neg_clear 1835 1.1 christos 1836 1.1 christos test_h_gr32 word_dest er0 1837 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1838 1.1 christos test_gr_a5a5 2 1839 1.1 christos test_gr_a5a5 3 1840 1.1 christos test_gr_a5a5 4 1841 1.1 christos test_gr_a5a5 5 1842 1.1 christos test_gr_a5a5 6 1843 1.1 christos test_gr_a5a5 7 1844 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1845 1.1 christos cmp.w #0x0a5a, @word_dest 1846 1.1 christos beq .Lwpreinc4 1847 1.1 christos fail 1848 1.1 christos .Lwpreinc4: 1849 1.1 christos mov.w #0xa5a5, @word_dest 1850 1.1 christos 1851 1.1 christos shlr_w_predec_4: 1852 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1853 1.1 christos set_ccr_zero 1854 1.1 christos 1855 1.1 christos mov #word_dest+2, er0 1856 1.1 christos shlr.w #4, @-er0 ; shift right logical by four, predec 1857 1.1 christos ;;; .word 0x0157 1858 1.1 christos ;;; .word 0x6d08 1859 1.1 christos ;;; .word 0x1120 1860 1.1 christos 1861 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1862 1.1 christos test_zero_clear 1863 1.1 christos test_ovf_clear 1864 1.1 christos test_neg_clear 1865 1.1 christos 1866 1.1 christos test_h_gr32 word_dest er0 1867 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1868 1.1 christos test_gr_a5a5 2 1869 1.1 christos test_gr_a5a5 3 1870 1.1 christos test_gr_a5a5 4 1871 1.1 christos test_gr_a5a5 5 1872 1.1 christos test_gr_a5a5 6 1873 1.1 christos test_gr_a5a5 7 1874 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1875 1.1 christos cmp.w #0x0a5a, @word_dest 1876 1.1 christos beq .Lwpredec4 1877 1.1 christos fail 1878 1.1 christos .Lwpredec4: 1879 1.1 christos mov.w #0xa5a5, @word_dest 1880 1.1 christos 1881 1.1 christos shlr_w_disp2_4: 1882 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1883 1.1 christos set_ccr_zero 1884 1.1 christos 1885 1.1 christos mov #word_dest-4, er0 1886 1.1 christos shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 1887 1.1 christos ;;; .word 0x0156 1888 1.1 christos ;;; .word 0x6908 1889 1.1 christos ;;; .word 0x1120 1890 1.1 christos 1891 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1892 1.1 christos test_zero_clear 1893 1.1 christos test_ovf_clear 1894 1.1 christos test_neg_clear 1895 1.1 christos 1896 1.1 christos test_h_gr32 word_dest-4 er0 1897 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1898 1.1 christos test_gr_a5a5 2 1899 1.1 christos test_gr_a5a5 3 1900 1.1 christos test_gr_a5a5 4 1901 1.1 christos test_gr_a5a5 5 1902 1.1 christos test_gr_a5a5 6 1903 1.1 christos test_gr_a5a5 7 1904 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1905 1.1 christos cmp.w #0x0a5a, @word_dest 1906 1.1 christos beq .Lwdisp24 1907 1.1 christos fail 1908 1.1 christos .Lwdisp24: 1909 1.1 christos mov.w #0xa5a5, @word_dest 1910 1.1 christos 1911 1.1 christos shlr_w_disp16_4: 1912 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1913 1.1 christos set_ccr_zero 1914 1.1 christos 1915 1.1 christos mov #word_dest-44, er0 1916 1.1 christos shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 1917 1.1 christos ;;; .word 0x0154 1918 1.1 christos ;;; .word 0x6f08 1919 1.1 christos ;;; .word 44 1920 1.1 christos ;;; .word 0x1120 1921 1.1 christos 1922 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1923 1.1 christos test_zero_clear 1924 1.1 christos test_ovf_clear 1925 1.1 christos test_neg_clear 1926 1.1 christos 1927 1.1 christos test_h_gr32 word_dest-44 er0 1928 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1929 1.1 christos test_gr_a5a5 2 1930 1.1 christos test_gr_a5a5 3 1931 1.1 christos test_gr_a5a5 4 1932 1.1 christos test_gr_a5a5 5 1933 1.1 christos test_gr_a5a5 6 1934 1.1 christos test_gr_a5a5 7 1935 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1936 1.1 christos cmp.w #0x0a5a, @word_dest 1937 1.1 christos beq .Lwdisp164 1938 1.1 christos fail 1939 1.1 christos .Lwdisp164: 1940 1.1 christos mov.w #0xa5a5, @word_dest 1941 1.1 christos 1942 1.1 christos shlr_w_disp32_4: 1943 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1944 1.1 christos set_ccr_zero 1945 1.1 christos 1946 1.1 christos mov #word_dest-666, er0 1947 1.1 christos shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 1948 1.1 christos ;;; .word 0x7884 1949 1.1 christos ;;; .word 0x6b28 1950 1.1 christos ;;; .long 666 1951 1.1 christos ;;; .word 0x1120 1952 1.1 christos 1953 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1954 1.1 christos test_zero_clear 1955 1.1 christos test_ovf_clear 1956 1.1 christos test_neg_clear 1957 1.1 christos 1958 1.1 christos test_h_gr32 word_dest-666 er0 1959 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 1960 1.1 christos test_gr_a5a5 2 1961 1.1 christos test_gr_a5a5 3 1962 1.1 christos test_gr_a5a5 4 1963 1.1 christos test_gr_a5a5 5 1964 1.1 christos test_gr_a5a5 6 1965 1.1 christos test_gr_a5a5 7 1966 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1967 1.1 christos cmp.w #0x0a5a, @word_dest 1968 1.1 christos beq .Lwdisp324 1969 1.1 christos fail 1970 1.1 christos .Lwdisp324: 1971 1.1 christos mov.w #0xa5a5, @word_dest 1972 1.1 christos 1973 1.1 christos shlr_w_abs16_4: 1974 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 1975 1.1 christos set_ccr_zero 1976 1.1 christos 1977 1.1 christos shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 1978 1.1 christos ;;; .word 0x6b18 1979 1.1 christos ;;; .word word_dest 1980 1.1 christos ;;; .word 0x1120 1981 1.1 christos 1982 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1983 1.1 christos test_zero_clear 1984 1.1 christos test_ovf_clear 1985 1.1 christos test_neg_clear 1986 1.1 christos 1987 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1988 1.1 christos test_gr_a5a5 2 1989 1.1 christos test_gr_a5a5 2 1990 1.1 christos test_gr_a5a5 3 1991 1.1 christos test_gr_a5a5 4 1992 1.1 christos test_gr_a5a5 5 1993 1.1 christos test_gr_a5a5 6 1994 1.1 christos test_gr_a5a5 7 1995 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1996 1.1 christos cmp.w #0x0a5a, @word_dest 1997 1.1 christos beq .Lwabs164 1998 1.1 christos fail 1999 1.1 christos .Lwabs164: 2000 1.1 christos mov.w #0xa5a5, @word_dest 2001 1.1 christos 2002 1.1 christos shlr_w_abs32_4: 2003 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2004 1.1 christos set_ccr_zero 2005 1.1 christos 2006 1.1 christos shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 2007 1.1 christos ;;; .word 0x6b38 2008 1.1 christos ;;; .long word_dest 2009 1.1 christos ;;; .word 0x1120 2010 1.1 christos 2011 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2012 1.1 christos test_zero_clear 2013 1.1 christos test_ovf_clear 2014 1.1 christos test_neg_clear 2015 1.1 christos 2016 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2017 1.1 christos test_gr_a5a5 2 2018 1.1 christos test_gr_a5a5 2 2019 1.1 christos test_gr_a5a5 3 2020 1.1 christos test_gr_a5a5 4 2021 1.1 christos test_gr_a5a5 5 2022 1.1 christos test_gr_a5a5 6 2023 1.1 christos test_gr_a5a5 7 2024 1.1 christos ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 2025 1.1 christos cmp.w #0x0a5a, @word_dest 2026 1.1 christos beq .Lwabs324 2027 1.1 christos fail 2028 1.1 christos .Lwabs324: 2029 1.1 christos mov.w #0xa5a5, @word_dest 2030 1.1 christos 2031 1.1 christos shlr_w_reg16_8: 2032 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2033 1.1 christos set_ccr_zero 2034 1.1 christos 2035 1.1 christos shlr.w #8, r0 ; shift right logical by eight 2036 1.1 christos ;;; .word 0x1160 2037 1.1 christos 2038 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2039 1.1 christos test_zero_clear 2040 1.1 christos test_ovf_clear 2041 1.1 christos test_neg_clear 2042 1.1 christos 2043 1.1 christos test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2044 1.1 christos test_h_gr32 0xa5a500a5 er0 2045 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2046 1.1 christos test_gr_a5a5 2 2047 1.1 christos test_gr_a5a5 3 2048 1.1 christos test_gr_a5a5 4 2049 1.1 christos test_gr_a5a5 5 2050 1.1 christos test_gr_a5a5 6 2051 1.1 christos test_gr_a5a5 7 2052 1.1 christos 2053 1.1 christos shlr_w_ind_8: 2054 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2055 1.1 christos set_ccr_zero 2056 1.1 christos 2057 1.1 christos mov #word_dest, er0 2058 1.1 christos shlr.w #8, @er0 ; shift right logical by eight, indirect 2059 1.1 christos ;;; .word 0x7d80 2060 1.1 christos ;;; .word 0x1160 2061 1.1 christos 2062 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2063 1.1 christos test_zero_clear 2064 1.1 christos test_ovf_clear 2065 1.1 christos test_neg_clear 2066 1.1 christos 2067 1.1 christos test_h_gr32 word_dest er0 2068 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2069 1.1 christos test_gr_a5a5 2 2070 1.1 christos test_gr_a5a5 3 2071 1.1 christos test_gr_a5a5 4 2072 1.1 christos test_gr_a5a5 5 2073 1.1 christos test_gr_a5a5 6 2074 1.1 christos test_gr_a5a5 7 2075 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2076 1.1 christos cmp.w #0x00a5, @word_dest 2077 1.1 christos beq .Lwind8 2078 1.1 christos fail 2079 1.1 christos .Lwind8: 2080 1.1 christos mov.w #0xa5a5, @word_dest 2081 1.1 christos 2082 1.1 christos shlr_w_postinc_8: 2083 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2084 1.1 christos set_ccr_zero 2085 1.1 christos 2086 1.1 christos mov #word_dest, er0 2087 1.1 christos shlr.w #8, @er0+ ; shift right logical by eight, postinc 2088 1.1 christos ;;; .word 0x0154 2089 1.1 christos ;;; .word 0x6d08 2090 1.1 christos ;;; .word 0x1160 2091 1.1 christos 2092 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2093 1.1 christos test_zero_clear 2094 1.1 christos test_ovf_clear 2095 1.1 christos test_neg_clear 2096 1.1 christos 2097 1.1 christos test_h_gr32 word_dest+2 er0 2098 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2099 1.1 christos test_gr_a5a5 2 2100 1.1 christos test_gr_a5a5 3 2101 1.1 christos test_gr_a5a5 4 2102 1.1 christos test_gr_a5a5 5 2103 1.1 christos test_gr_a5a5 6 2104 1.1 christos test_gr_a5a5 7 2105 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2106 1.1 christos cmp.w #0x00a5, @word_dest 2107 1.1 christos beq .Lwpostinc8 2108 1.1 christos fail 2109 1.1 christos .Lwpostinc8: 2110 1.1 christos mov.w #0xa5a5, @word_dest 2111 1.1 christos 2112 1.1 christos shlr_w_postdec_8: 2113 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2114 1.1 christos set_ccr_zero 2115 1.1 christos 2116 1.1 christos mov #word_dest, er0 2117 1.1 christos shlr.w #8, @er0- ; shift right logical by eight, postdec 2118 1.1 christos ;;; .word 0x0156 2119 1.1 christos ;;; .word 0x6d08 2120 1.1 christos ;;; .word 0x1160 2121 1.1 christos 2122 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2123 1.1 christos test_zero_clear 2124 1.1 christos test_ovf_clear 2125 1.1 christos test_neg_clear 2126 1.1 christos 2127 1.1 christos test_h_gr32 word_dest-2 er0 2128 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2129 1.1 christos test_gr_a5a5 2 2130 1.1 christos test_gr_a5a5 3 2131 1.1 christos test_gr_a5a5 4 2132 1.1 christos test_gr_a5a5 5 2133 1.1 christos test_gr_a5a5 6 2134 1.1 christos test_gr_a5a5 7 2135 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2136 1.1 christos cmp.w #0x00a5, @word_dest 2137 1.1 christos beq .Lwpostdec8 2138 1.1 christos fail 2139 1.1 christos .Lwpostdec8: 2140 1.1 christos mov.w #0xa5a5, @word_dest 2141 1.1 christos 2142 1.1 christos shlr_w_preinc_8: 2143 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2144 1.1 christos set_ccr_zero 2145 1.1 christos 2146 1.1 christos mov #word_dest-2, er0 2147 1.1 christos shlr.w #8, @+er0 ; shift right logical by eight, preinc 2148 1.1 christos ;;; .word 0x0155 2149 1.1 christos ;;; .word 0x6d08 2150 1.1 christos ;;; .word 0x1160 2151 1.1 christos 2152 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2153 1.1 christos test_zero_clear 2154 1.1 christos test_ovf_clear 2155 1.1 christos test_neg_clear 2156 1.1 christos 2157 1.1 christos test_h_gr32 word_dest er0 2158 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2159 1.1 christos test_gr_a5a5 2 2160 1.1 christos test_gr_a5a5 3 2161 1.1 christos test_gr_a5a5 4 2162 1.1 christos test_gr_a5a5 5 2163 1.1 christos test_gr_a5a5 6 2164 1.1 christos test_gr_a5a5 7 2165 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2166 1.1 christos cmp.w #0x00a5, @word_dest 2167 1.1 christos beq .Lwpreinc8 2168 1.1 christos fail 2169 1.1 christos .Lwpreinc8: 2170 1.1 christos mov.w #0xa5a5, @word_dest 2171 1.1 christos 2172 1.1 christos shlr_w_predec_8: 2173 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2174 1.1 christos set_ccr_zero 2175 1.1 christos 2176 1.1 christos mov #word_dest+2, er0 2177 1.1 christos shlr.w #8, @-er0 ; shift right logical by eight, predec 2178 1.1 christos ;;; .word 0x0157 2179 1.1 christos ;;; .word 0x6d08 2180 1.1 christos ;;; .word 0x1160 2181 1.1 christos 2182 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2183 1.1 christos test_zero_clear 2184 1.1 christos test_ovf_clear 2185 1.1 christos test_neg_clear 2186 1.1 christos 2187 1.1 christos test_h_gr32 word_dest er0 2188 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2189 1.1 christos test_gr_a5a5 2 2190 1.1 christos test_gr_a5a5 3 2191 1.1 christos test_gr_a5a5 4 2192 1.1 christos test_gr_a5a5 5 2193 1.1 christos test_gr_a5a5 6 2194 1.1 christos test_gr_a5a5 7 2195 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2196 1.1 christos cmp.w #0x00a5, @word_dest 2197 1.1 christos beq .Lwpredec8 2198 1.1 christos fail 2199 1.1 christos .Lwpredec8: 2200 1.1 christos mov.w #0xa5a5, @word_dest 2201 1.1 christos 2202 1.1 christos shlr_w_disp2_8: 2203 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2204 1.1 christos set_ccr_zero 2205 1.1 christos 2206 1.1 christos mov #word_dest-4, er0 2207 1.1 christos shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 2208 1.1 christos ;;; .word 0x0156 2209 1.1 christos ;;; .word 0x6908 2210 1.1 christos ;;; .word 0x1160 2211 1.1 christos 2212 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2213 1.1 christos test_zero_clear 2214 1.1 christos test_ovf_clear 2215 1.1 christos test_neg_clear 2216 1.1 christos 2217 1.1 christos test_h_gr32 word_dest-4 er0 2218 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2219 1.1 christos test_gr_a5a5 2 2220 1.1 christos test_gr_a5a5 3 2221 1.1 christos test_gr_a5a5 4 2222 1.1 christos test_gr_a5a5 5 2223 1.1 christos test_gr_a5a5 6 2224 1.1 christos test_gr_a5a5 7 2225 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2226 1.1 christos cmp.w #0x00a5, @word_dest 2227 1.1 christos beq .Lwdisp28 2228 1.1 christos fail 2229 1.1 christos .Lwdisp28: 2230 1.1 christos mov.w #0xa5a5, @word_dest 2231 1.1 christos 2232 1.1 christos shlr_w_disp16_8: 2233 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2234 1.1 christos set_ccr_zero 2235 1.1 christos 2236 1.1 christos mov #word_dest-44, er0 2237 1.1 christos shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 2238 1.1 christos ;;; .word 0x0154 2239 1.1 christos ;;; .word 0x6f08 2240 1.1 christos ;;; .word 44 2241 1.1 christos ;;; .word 0x1160 2242 1.1 christos 2243 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2244 1.1 christos test_zero_clear 2245 1.1 christos test_ovf_clear 2246 1.1 christos test_neg_clear 2247 1.1 christos 2248 1.1 christos test_h_gr32 word_dest-44 er0 2249 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2250 1.1 christos test_gr_a5a5 2 2251 1.1 christos test_gr_a5a5 3 2252 1.1 christos test_gr_a5a5 4 2253 1.1 christos test_gr_a5a5 5 2254 1.1 christos test_gr_a5a5 6 2255 1.1 christos test_gr_a5a5 7 2256 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2257 1.1 christos cmp.w #0x00a5, @word_dest 2258 1.1 christos beq .Lwdisp168 2259 1.1 christos fail 2260 1.1 christos .Lwdisp168: 2261 1.1 christos mov.w #0xa5a5, @word_dest 2262 1.1 christos 2263 1.1 christos shlr_w_disp32_8: 2264 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2265 1.1 christos set_ccr_zero 2266 1.1 christos 2267 1.1 christos mov #word_dest-666, er0 2268 1.1 christos shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 2269 1.1 christos ;;; .word 0x7884 2270 1.1 christos ;;; .word 0x6b28 2271 1.1 christos ;;; .long 666 2272 1.1 christos ;;; .word 0x1160 2273 1.1 christos 2274 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2275 1.1 christos test_zero_clear 2276 1.1 christos test_ovf_clear 2277 1.1 christos test_neg_clear 2278 1.1 christos 2279 1.1 christos test_h_gr32 word_dest-666 er0 2280 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2281 1.1 christos test_gr_a5a5 2 2282 1.1 christos test_gr_a5a5 3 2283 1.1 christos test_gr_a5a5 4 2284 1.1 christos test_gr_a5a5 5 2285 1.1 christos test_gr_a5a5 6 2286 1.1 christos test_gr_a5a5 7 2287 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2288 1.1 christos cmp.w #0x00a5, @word_dest 2289 1.1 christos beq .Lwdisp328 2290 1.1 christos fail 2291 1.1 christos .Lwdisp328: 2292 1.1 christos mov.w #0xa5a5, @word_dest 2293 1.1 christos 2294 1.1 christos shlr_w_abs16_8: 2295 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2296 1.1 christos set_ccr_zero 2297 1.1 christos 2298 1.1 christos shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 2299 1.1 christos ;;; .word 0x6b18 2300 1.1 christos ;;; .word word_dest 2301 1.1 christos ;;; .word 0x1160 2302 1.1 christos 2303 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2304 1.1 christos test_zero_clear 2305 1.1 christos test_ovf_clear 2306 1.1 christos test_neg_clear 2307 1.1 christos 2308 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2309 1.1 christos test_gr_a5a5 2 2310 1.1 christos test_gr_a5a5 2 2311 1.1 christos test_gr_a5a5 3 2312 1.1 christos test_gr_a5a5 4 2313 1.1 christos test_gr_a5a5 5 2314 1.1 christos test_gr_a5a5 6 2315 1.1 christos test_gr_a5a5 7 2316 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2317 1.1 christos cmp.w #0x00a5, @word_dest 2318 1.1 christos beq .Lwabs168 2319 1.1 christos fail 2320 1.1 christos .Lwabs168: 2321 1.1 christos mov.w #0xa5a5, @word_dest 2322 1.1 christos 2323 1.1 christos shlr_w_abs32_8: 2324 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2325 1.1 christos set_ccr_zero 2326 1.1 christos 2327 1.1 christos shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 2328 1.1 christos ;;; .word 0x6b38 2329 1.1 christos ;;; .long word_dest 2330 1.1 christos ;;; .word 0x1160 2331 1.1 christos 2332 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2333 1.1 christos test_zero_clear 2334 1.1 christos test_ovf_clear 2335 1.1 christos test_neg_clear 2336 1.1 christos 2337 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2338 1.1 christos test_gr_a5a5 2 2339 1.1 christos test_gr_a5a5 2 2340 1.1 christos test_gr_a5a5 3 2341 1.1 christos test_gr_a5a5 4 2342 1.1 christos test_gr_a5a5 5 2343 1.1 christos test_gr_a5a5 6 2344 1.1 christos test_gr_a5a5 7 2345 1.1 christos ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2346 1.1 christos cmp.w #0x00a5, @word_dest 2347 1.1 christos beq .Lwabs328 2348 1.1 christos fail 2349 1.1 christos .Lwabs328: 2350 1.1 christos mov.w #0xa5a5, @word_dest 2351 1.1 christos 2352 1.1 christos shlr_l_imm5_1: 2353 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2354 1.1 christos set_ccr_zero 2355 1.1 christos 2356 1.1 christos shlr.l #31:5, er0 ; shift right logical by 5-bit immediate 2357 1.1 christos ;;; .word 0x0399 2358 1.1 christos ;;; .word 0x1130 2359 1.1 christos 2360 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2361 1.1 christos test_zero_clear 2362 1.1 christos test_ovf_clear 2363 1.1 christos test_neg_clear 2364 1.1 christos 2365 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2366 1.1 christos ; -> 0000 0000 0000 0000 0000 0000 0000 0001 2367 1.1 christos test_h_gr32 0x1 er0 2368 1.1 christos 2369 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2370 1.1 christos test_gr_a5a5 2 2371 1.1 christos test_gr_a5a5 3 2372 1.1 christos test_gr_a5a5 4 2373 1.1 christos test_gr_a5a5 5 2374 1.1 christos test_gr_a5a5 6 2375 1.1 christos test_gr_a5a5 7 2376 1.1 christos .endif 2377 1.1 christos 2378 1.1 christos shlr_l_reg32_1: 2379 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2380 1.1 christos set_ccr_zero 2381 1.1 christos 2382 1.1 christos shlr.l er0 ; shift right logical by one, register 2383 1.1 christos ;;; .word 0x1130 2384 1.1 christos 2385 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2386 1.1 christos test_zero_clear 2387 1.1 christos test_ovf_clear 2388 1.1 christos test_neg_clear 2389 1.1 christos 2390 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2391 1.1 christos ; -> 0101 0010 1101 0010 1101 0010 1101 0010 2392 1.1 christos test_h_gr32 0x52d2d2d2 er0 2393 1.1 christos 2394 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2395 1.1 christos test_gr_a5a5 2 2396 1.1 christos test_gr_a5a5 3 2397 1.1 christos test_gr_a5a5 4 2398 1.1 christos test_gr_a5a5 5 2399 1.1 christos test_gr_a5a5 6 2400 1.1 christos test_gr_a5a5 7 2401 1.1 christos 2402 1.1 christos .if (sim_cpu == h8sx) 2403 1.1 christos shlr_l_ind_1: 2404 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2405 1.1 christos set_ccr_zero 2406 1.1 christos 2407 1.1 christos mov #long_dest, er0 2408 1.1 christos shlr.l @er0 ; shift right logical by one, indirect 2409 1.1 christos ;;; .word 0x0104 2410 1.1 christos ;;; .word 0x6908 2411 1.1 christos ;;; .word 0x1130 2412 1.1 christos 2413 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2414 1.1 christos test_zero_clear 2415 1.1 christos test_ovf_clear 2416 1.1 christos test_neg_clear 2417 1.1 christos 2418 1.1 christos test_h_gr32 long_dest er0 2419 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2420 1.1 christos test_gr_a5a5 2 2421 1.1 christos test_gr_a5a5 3 2422 1.1 christos test_gr_a5a5 4 2423 1.1 christos test_gr_a5a5 5 2424 1.1 christos test_gr_a5a5 6 2425 1.1 christos test_gr_a5a5 7 2426 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2427 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2428 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2429 1.1 christos beq .Llind1 2430 1.1 christos fail 2431 1.1 christos .Llind1: 2432 1.1 christos mov #0xa5a5a5a5, @long_dest 2433 1.1 christos 2434 1.1 christos shlr_l_postinc_1: 2435 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2436 1.1 christos set_ccr_zero 2437 1.1 christos 2438 1.1 christos mov #long_dest, er0 2439 1.1 christos shlr.l @er0+ ; shift right logical by one, postinc 2440 1.1 christos ;;; .word 0x0104 2441 1.1 christos ;;; .word 0x6d08 2442 1.1 christos ;;; .word 0x1130 2443 1.1 christos 2444 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2445 1.1 christos test_zero_clear 2446 1.1 christos test_ovf_clear 2447 1.1 christos test_neg_clear 2448 1.1 christos 2449 1.1 christos test_h_gr32 long_dest+4 er0 2450 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2451 1.1 christos test_gr_a5a5 2 2452 1.1 christos test_gr_a5a5 3 2453 1.1 christos test_gr_a5a5 4 2454 1.1 christos test_gr_a5a5 5 2455 1.1 christos test_gr_a5a5 6 2456 1.1 christos test_gr_a5a5 7 2457 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2458 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2459 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2460 1.1 christos beq .Llpostinc1 2461 1.1 christos fail 2462 1.1 christos .Llpostinc1: 2463 1.1 christos mov #0xa5a5a5a5, @long_dest 2464 1.1 christos 2465 1.1 christos shlr_l_postdec_1: 2466 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2467 1.1 christos set_ccr_zero 2468 1.1 christos 2469 1.1 christos mov #long_dest, er0 2470 1.1 christos shlr.l @er0- ; shift right logical by one, postdec 2471 1.1 christos ;;; .word 0x0106 2472 1.1 christos ;;; .word 0x6d08 2473 1.1 christos ;;; .word 0x1130 2474 1.1 christos 2475 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2476 1.1 christos test_zero_clear 2477 1.1 christos test_ovf_clear 2478 1.1 christos test_neg_clear 2479 1.1 christos 2480 1.1 christos test_h_gr32 long_dest-4 er0 2481 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2482 1.1 christos test_gr_a5a5 2 2483 1.1 christos test_gr_a5a5 3 2484 1.1 christos test_gr_a5a5 4 2485 1.1 christos test_gr_a5a5 5 2486 1.1 christos test_gr_a5a5 6 2487 1.1 christos test_gr_a5a5 7 2488 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2489 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2490 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2491 1.1 christos beq .Llpostdec1 2492 1.1 christos fail 2493 1.1 christos .Llpostdec1: 2494 1.1 christos mov #0xa5a5a5a5, @long_dest 2495 1.1 christos 2496 1.1 christos shlr_l_preinc_1: 2497 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2498 1.1 christos set_ccr_zero 2499 1.1 christos 2500 1.1 christos mov #long_dest-4, er0 2501 1.1 christos shlr.l @+er0 ; shift right logical by one, preinc 2502 1.1 christos ;;; .word 0x0105 2503 1.1 christos ;;; .word 0x6d08 2504 1.1 christos ;;; .word 0x1130 2505 1.1 christos 2506 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2507 1.1 christos test_zero_clear 2508 1.1 christos test_ovf_clear 2509 1.1 christos test_neg_clear 2510 1.1 christos 2511 1.1 christos test_h_gr32 long_dest er0 2512 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2513 1.1 christos test_gr_a5a5 2 2514 1.1 christos test_gr_a5a5 3 2515 1.1 christos test_gr_a5a5 4 2516 1.1 christos test_gr_a5a5 5 2517 1.1 christos test_gr_a5a5 6 2518 1.1 christos test_gr_a5a5 7 2519 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2520 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2521 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2522 1.1 christos beq .Llpreinc1 2523 1.1 christos fail 2524 1.1 christos .Llpreinc1: 2525 1.1 christos mov #0xa5a5a5a5, @long_dest 2526 1.1 christos 2527 1.1 christos shlr_l_predec_1: 2528 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2529 1.1 christos set_ccr_zero 2530 1.1 christos 2531 1.1 christos mov #long_dest+4, er0 2532 1.1 christos shlr.l @-er0 ; shift right logical by one, predec 2533 1.1 christos ;;; .word 0x0107 2534 1.1 christos ;;; .word 0x6d08 2535 1.1 christos ;;; .word 0x1130 2536 1.1 christos 2537 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2538 1.1 christos test_zero_clear 2539 1.1 christos test_ovf_clear 2540 1.1 christos test_neg_clear 2541 1.1 christos 2542 1.1 christos test_h_gr32 long_dest er0 2543 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2544 1.1 christos test_gr_a5a5 2 2545 1.1 christos test_gr_a5a5 3 2546 1.1 christos test_gr_a5a5 4 2547 1.1 christos test_gr_a5a5 5 2548 1.1 christos test_gr_a5a5 6 2549 1.1 christos test_gr_a5a5 7 2550 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2551 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2552 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2553 1.1 christos beq .Llpredec1 2554 1.1 christos fail 2555 1.1 christos .Llpredec1: 2556 1.1 christos mov #0xa5a5a5a5, @long_dest 2557 1.1 christos 2558 1.1 christos shlr_l_disp2_1: 2559 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2560 1.1 christos set_ccr_zero 2561 1.1 christos 2562 1.1 christos mov #long_dest-8, er0 2563 1.1 christos shlr.l @(8:2, er0) ; shift right logical by one, disp2 2564 1.1 christos ;;; .word 0x0106 2565 1.1 christos ;;; .word 0x6908 2566 1.1 christos ;;; .word 0x1130 2567 1.1 christos 2568 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2569 1.1 christos test_zero_clear 2570 1.1 christos test_ovf_clear 2571 1.1 christos test_neg_clear 2572 1.1 christos 2573 1.1 christos test_h_gr32 long_dest-8 er0 2574 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2575 1.1 christos test_gr_a5a5 2 2576 1.1 christos test_gr_a5a5 3 2577 1.1 christos test_gr_a5a5 4 2578 1.1 christos test_gr_a5a5 5 2579 1.1 christos test_gr_a5a5 6 2580 1.1 christos test_gr_a5a5 7 2581 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2582 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2583 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2584 1.1 christos beq .Lldisp21 2585 1.1 christos fail 2586 1.1 christos .Lldisp21: 2587 1.1 christos mov #0xa5a5a5a5, @long_dest 2588 1.1 christos 2589 1.1 christos shlr_l_disp16_1: 2590 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2591 1.1 christos set_ccr_zero 2592 1.1 christos 2593 1.1 christos mov #long_dest-44, er0 2594 1.1 christos shlr.l @(44:16, er0) ; shift right logical by one, disp16 2595 1.1 christos ;;; .word 0x0104 2596 1.1 christos ;;; .word 0x6f08 2597 1.1 christos ;;; .word 44 2598 1.1 christos ;;; .word 0x1130 2599 1.1 christos 2600 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2601 1.1 christos test_zero_clear 2602 1.1 christos test_ovf_clear 2603 1.1 christos test_neg_clear 2604 1.1 christos 2605 1.1 christos test_h_gr32 long_dest-44 er0 2606 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2607 1.1 christos test_gr_a5a5 2 2608 1.1 christos test_gr_a5a5 3 2609 1.1 christos test_gr_a5a5 4 2610 1.1 christos test_gr_a5a5 5 2611 1.1 christos test_gr_a5a5 6 2612 1.1 christos test_gr_a5a5 7 2613 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2614 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2615 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2616 1.1 christos beq .Lldisp161 2617 1.1 christos fail 2618 1.1 christos .Lldisp161: 2619 1.1 christos mov #0xa5a5a5a5, @long_dest 2620 1.1 christos 2621 1.1 christos shlr_l_disp32_1: 2622 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2623 1.1 christos set_ccr_zero 2624 1.1 christos 2625 1.1 christos mov #long_dest-666, er0 2626 1.1 christos shlr.l @(666:32, er0) ; shift right logical by one, disp32 2627 1.1 christos ;;; .word 0x7884 2628 1.1 christos ;;; .word 0x6b28 2629 1.1 christos ;;; .long 666 2630 1.1 christos ;;; .word 0x1130 2631 1.1 christos 2632 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2633 1.1 christos test_zero_clear 2634 1.1 christos test_ovf_clear 2635 1.1 christos test_neg_clear 2636 1.1 christos 2637 1.1 christos test_h_gr32 long_dest-666 er0 2638 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2639 1.1 christos test_gr_a5a5 2 2640 1.1 christos test_gr_a5a5 3 2641 1.1 christos test_gr_a5a5 4 2642 1.1 christos test_gr_a5a5 5 2643 1.1 christos test_gr_a5a5 6 2644 1.1 christos test_gr_a5a5 7 2645 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2646 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2647 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2648 1.1 christos beq .Lldisp321 2649 1.1 christos fail 2650 1.1 christos .Lldisp321: 2651 1.1 christos mov #0xa5a5a5a5, @long_dest 2652 1.1 christos 2653 1.1 christos shlr_l_abs16_1: 2654 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2655 1.1 christos set_ccr_zero 2656 1.1 christos 2657 1.1 christos shlr.l @long_dest:16 ; shift right logical by one, abs16 2658 1.1 christos ;;; .word 0x0104 2659 1.1 christos ;;; .word 0x6b08 2660 1.1 christos ;;; .word long_dest 2661 1.1 christos ;;; .word 0x1130 2662 1.1 christos 2663 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2664 1.1 christos test_zero_clear 2665 1.1 christos test_ovf_clear 2666 1.1 christos test_neg_clear 2667 1.1 christos 2668 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2669 1.1 christos test_gr_a5a5 1 2670 1.1 christos test_gr_a5a5 2 2671 1.1 christos test_gr_a5a5 3 2672 1.1 christos test_gr_a5a5 4 2673 1.1 christos test_gr_a5a5 5 2674 1.1 christos test_gr_a5a5 6 2675 1.1 christos test_gr_a5a5 7 2676 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2677 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2678 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2679 1.1 christos beq .Llabs161 2680 1.1 christos fail 2681 1.1 christos .Llabs161: 2682 1.1 christos mov #0xa5a5a5a5, @long_dest 2683 1.1 christos 2684 1.1 christos shlr_l_abs32_1: 2685 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2686 1.1 christos set_ccr_zero 2687 1.1 christos 2688 1.1 christos shlr.l @long_dest:32 ; shift right logical by one, abs32 2689 1.1 christos ;;; .word 0x0104 2690 1.1 christos ;;; .word 0x6b28 2691 1.1 christos ;;; .long long_dest 2692 1.1 christos ;;; .word 0x1130 2693 1.1 christos 2694 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2695 1.1 christos test_zero_clear 2696 1.1 christos test_ovf_clear 2697 1.1 christos test_neg_clear 2698 1.1 christos 2699 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2700 1.1 christos test_gr_a5a5 1 2701 1.1 christos test_gr_a5a5 2 2702 1.1 christos test_gr_a5a5 3 2703 1.1 christos test_gr_a5a5 4 2704 1.1 christos test_gr_a5a5 5 2705 1.1 christos test_gr_a5a5 6 2706 1.1 christos test_gr_a5a5 7 2707 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2708 1.1 christos ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2709 1.1 christos cmp.l #0x52d2d2d2, @long_dest 2710 1.1 christos beq .Llabs321 2711 1.1 christos fail 2712 1.1 christos .Llabs321: 2713 1.1 christos mov #0xa5a5a5a5, @long_dest 2714 1.1 christos .endif 2715 1.1 christos 2716 1.1 christos shlr_l_reg32_2: 2717 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2718 1.1 christos set_ccr_zero 2719 1.1 christos 2720 1.1 christos shlr.l #2, er0 ; shift right logical by two, register 2721 1.1 christos ;;; .word 0x1170 2722 1.1 christos 2723 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2724 1.1 christos test_zero_clear 2725 1.1 christos test_ovf_clear 2726 1.1 christos test_neg_clear 2727 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2728 1.1 christos ; -> 0010 1001 0110 1001 0110 1001 0110 1001 2729 1.1 christos test_h_gr32 0x29696969 er0 2730 1.1 christos 2731 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2732 1.1 christos test_gr_a5a5 2 2733 1.1 christos test_gr_a5a5 3 2734 1.1 christos test_gr_a5a5 4 2735 1.1 christos test_gr_a5a5 5 2736 1.1 christos test_gr_a5a5 6 2737 1.1 christos test_gr_a5a5 7 2738 1.1 christos 2739 1.1 christos .if (sim_cpu == h8sx) 2740 1.1 christos 2741 1.1 christos shlr_l_ind_2: 2742 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2743 1.1 christos set_ccr_zero 2744 1.1 christos 2745 1.1 christos mov #long_dest, er0 2746 1.1 christos shlr.l #2, @er0 ; shift right logical by two, indirect 2747 1.1 christos ;;; .word 0x0104 2748 1.1 christos ;;; .word 0x6908 2749 1.1 christos ;;; .word 0x1170 2750 1.1 christos 2751 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2752 1.1 christos test_zero_clear 2753 1.1 christos test_ovf_clear 2754 1.1 christos test_neg_clear 2755 1.1 christos 2756 1.1 christos test_h_gr32 long_dest er0 2757 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2758 1.1 christos test_gr_a5a5 2 2759 1.1 christos test_gr_a5a5 3 2760 1.1 christos test_gr_a5a5 4 2761 1.1 christos test_gr_a5a5 5 2762 1.1 christos test_gr_a5a5 6 2763 1.1 christos test_gr_a5a5 7 2764 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2765 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2766 1.1 christos cmp.l #0x29696969, @long_dest 2767 1.1 christos beq .Llind2 2768 1.1 christos fail 2769 1.1 christos .Llind2: 2770 1.1 christos mov #0xa5a5a5a5, @long_dest 2771 1.1 christos 2772 1.1 christos shlr_l_postinc_2: 2773 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2774 1.1 christos set_ccr_zero 2775 1.1 christos 2776 1.1 christos mov #long_dest, er0 2777 1.1 christos shlr.l #2, @er0+ ; shift right logical by two, postinc 2778 1.1 christos ;;; .word 0x0104 2779 1.1 christos ;;; .word 0x6d08 2780 1.1 christos ;;; .word 0x1170 2781 1.1 christos 2782 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2783 1.1 christos test_zero_clear 2784 1.1 christos test_ovf_clear 2785 1.1 christos test_neg_clear 2786 1.1 christos 2787 1.1 christos test_h_gr32 long_dest+4 er0 2788 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2789 1.1 christos test_gr_a5a5 2 2790 1.1 christos test_gr_a5a5 3 2791 1.1 christos test_gr_a5a5 4 2792 1.1 christos test_gr_a5a5 5 2793 1.1 christos test_gr_a5a5 6 2794 1.1 christos test_gr_a5a5 7 2795 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2796 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2797 1.1 christos cmp.l #0x29696969, @long_dest 2798 1.1 christos beq .Llpostinc2 2799 1.1 christos fail 2800 1.1 christos .Llpostinc2: 2801 1.1 christos mov #0xa5a5a5a5, @long_dest 2802 1.1 christos 2803 1.1 christos shlr_l_postdec_2: 2804 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2805 1.1 christos set_ccr_zero 2806 1.1 christos 2807 1.1 christos mov #long_dest, er0 2808 1.1 christos shlr.l #2, @er0- ; shift right logical by two, postdec 2809 1.1 christos ;;; .word 0x0106 2810 1.1 christos ;;; .word 0x6d08 2811 1.1 christos ;;; .word 0x1170 2812 1.1 christos 2813 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2814 1.1 christos test_zero_clear 2815 1.1 christos test_ovf_clear 2816 1.1 christos test_neg_clear 2817 1.1 christos 2818 1.1 christos test_h_gr32 long_dest-4 er0 2819 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2820 1.1 christos test_gr_a5a5 2 2821 1.1 christos test_gr_a5a5 3 2822 1.1 christos test_gr_a5a5 4 2823 1.1 christos test_gr_a5a5 5 2824 1.1 christos test_gr_a5a5 6 2825 1.1 christos test_gr_a5a5 7 2826 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2827 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2828 1.1 christos cmp.l #0x29696969, @long_dest 2829 1.1 christos beq .Llpostdec2 2830 1.1 christos fail 2831 1.1 christos .Llpostdec2: 2832 1.1 christos mov #0xa5a5a5a5, @long_dest 2833 1.1 christos 2834 1.1 christos shlr_l_preinc_2: 2835 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2836 1.1 christos set_ccr_zero 2837 1.1 christos 2838 1.1 christos mov #long_dest-4, er0 2839 1.1 christos shlr.l #2, @+er0 ; shift right logical by two, preinc 2840 1.1 christos ;;; .word 0x0105 2841 1.1 christos ;;; .word 0x6d08 2842 1.1 christos ;;; .word 0x1170 2843 1.1 christos 2844 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2845 1.1 christos test_zero_clear 2846 1.1 christos test_ovf_clear 2847 1.1 christos test_neg_clear 2848 1.1 christos 2849 1.1 christos test_h_gr32 long_dest er0 2850 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2851 1.1 christos test_gr_a5a5 2 2852 1.1 christos test_gr_a5a5 3 2853 1.1 christos test_gr_a5a5 4 2854 1.1 christos test_gr_a5a5 5 2855 1.1 christos test_gr_a5a5 6 2856 1.1 christos test_gr_a5a5 7 2857 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2858 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2859 1.1 christos cmp.l #0x29696969, @long_dest 2860 1.1 christos beq .Llpreinc2 2861 1.1 christos fail 2862 1.1 christos .Llpreinc2: 2863 1.1 christos mov #0xa5a5a5a5, @long_dest 2864 1.1 christos 2865 1.1 christos shlr_l_predec_2: 2866 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2867 1.1 christos set_ccr_zero 2868 1.1 christos 2869 1.1 christos mov #long_dest+4, er0 2870 1.1 christos shlr.l #2, @-er0 ; shift right logical by two, predec 2871 1.1 christos ;;; .word 0x0107 2872 1.1 christos ;;; .word 0x6d08 2873 1.1 christos ;;; .word 0x1170 2874 1.1 christos 2875 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2876 1.1 christos test_zero_clear 2877 1.1 christos test_ovf_clear 2878 1.1 christos test_neg_clear 2879 1.1 christos 2880 1.1 christos test_h_gr32 long_dest er0 2881 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2882 1.1 christos test_gr_a5a5 2 2883 1.1 christos test_gr_a5a5 3 2884 1.1 christos test_gr_a5a5 4 2885 1.1 christos test_gr_a5a5 5 2886 1.1 christos test_gr_a5a5 6 2887 1.1 christos test_gr_a5a5 7 2888 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2889 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2890 1.1 christos cmp.l #0x29696969, @long_dest 2891 1.1 christos beq .Llpredec2 2892 1.1 christos fail 2893 1.1 christos .Llpredec2: 2894 1.1 christos mov #0xa5a5a5a5, @long_dest 2895 1.1 christos 2896 1.1 christos shlr_l_disp2_2: 2897 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2898 1.1 christos set_ccr_zero 2899 1.1 christos 2900 1.1 christos mov #long_dest-8, er0 2901 1.1 christos shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 2902 1.1 christos ;;; .word 0x0106 2903 1.1 christos ;;; .word 0x6908 2904 1.1 christos ;;; .word 0x1170 2905 1.1 christos 2906 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2907 1.1 christos test_zero_clear 2908 1.1 christos test_ovf_clear 2909 1.1 christos test_neg_clear 2910 1.1 christos 2911 1.1 christos test_h_gr32 long_dest-8 er0 2912 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2913 1.1 christos test_gr_a5a5 2 2914 1.1 christos test_gr_a5a5 3 2915 1.1 christos test_gr_a5a5 4 2916 1.1 christos test_gr_a5a5 5 2917 1.1 christos test_gr_a5a5 6 2918 1.1 christos test_gr_a5a5 7 2919 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2920 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2921 1.1 christos cmp.l #0x29696969, @long_dest 2922 1.1 christos beq .Lldisp22 2923 1.1 christos fail 2924 1.1 christos .Lldisp22: 2925 1.1 christos mov #0xa5a5a5a5, @long_dest 2926 1.1 christos 2927 1.1 christos shlr_l_disp16_2: 2928 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2929 1.1 christos set_ccr_zero 2930 1.1 christos 2931 1.1 christos mov #long_dest-44, er0 2932 1.1 christos shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 2933 1.1 christos ;;; .word 0x0104 2934 1.1 christos ;;; .word 0x6f08 2935 1.1 christos ;;; .word 44 2936 1.1 christos ;;; .word 0x1170 2937 1.1 christos 2938 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2939 1.1 christos test_zero_clear 2940 1.1 christos test_ovf_clear 2941 1.1 christos test_neg_clear 2942 1.1 christos 2943 1.1 christos test_h_gr32 long_dest-44 er0 2944 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2945 1.1 christos test_gr_a5a5 2 2946 1.1 christos test_gr_a5a5 3 2947 1.1 christos test_gr_a5a5 4 2948 1.1 christos test_gr_a5a5 5 2949 1.1 christos test_gr_a5a5 6 2950 1.1 christos test_gr_a5a5 7 2951 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2952 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2953 1.1 christos cmp.l #0x29696969, @long_dest 2954 1.1 christos beq .Lldisp162 2955 1.1 christos fail 2956 1.1 christos .Lldisp162: 2957 1.1 christos mov #0xa5a5a5a5, @long_dest 2958 1.1 christos 2959 1.1 christos shlr_l_disp32_2: 2960 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2961 1.1 christos set_ccr_zero 2962 1.1 christos 2963 1.1 christos mov #long_dest-666, er0 2964 1.1 christos shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 2965 1.1 christos ;;; .word 0x7884 2966 1.1 christos ;;; .word 0x6b28 2967 1.1 christos ;;; .long 666 2968 1.1 christos ;;; .word 0x1170 2969 1.1 christos 2970 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2971 1.1 christos test_zero_clear 2972 1.1 christos test_ovf_clear 2973 1.1 christos test_neg_clear 2974 1.1 christos 2975 1.1 christos test_h_gr32 long_dest-666 er0 2976 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 2977 1.1 christos test_gr_a5a5 2 2978 1.1 christos test_gr_a5a5 3 2979 1.1 christos test_gr_a5a5 4 2980 1.1 christos test_gr_a5a5 5 2981 1.1 christos test_gr_a5a5 6 2982 1.1 christos test_gr_a5a5 7 2983 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 2984 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2985 1.1 christos cmp.l #0x29696969, @long_dest 2986 1.1 christos beq .Lldisp322 2987 1.1 christos fail 2988 1.1 christos .Lldisp322: 2989 1.1 christos mov #0xa5a5a5a5, @long_dest 2990 1.1 christos 2991 1.1 christos shlr_l_abs16_2: 2992 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 2993 1.1 christos set_ccr_zero 2994 1.1 christos 2995 1.1 christos shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 2996 1.1 christos ;;; .word 0x0104 2997 1.1 christos ;;; .word 0x6b08 2998 1.1 christos ;;; .word long_dest 2999 1.1 christos ;;; .word 0x1170 3000 1.1 christos 3001 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3002 1.1 christos test_zero_clear 3003 1.1 christos test_ovf_clear 3004 1.1 christos test_neg_clear 3005 1.1 christos 3006 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3007 1.1 christos test_gr_a5a5 1 3008 1.1 christos test_gr_a5a5 2 3009 1.1 christos test_gr_a5a5 3 3010 1.1 christos test_gr_a5a5 4 3011 1.1 christos test_gr_a5a5 5 3012 1.1 christos test_gr_a5a5 6 3013 1.1 christos test_gr_a5a5 7 3014 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3015 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 3016 1.1 christos cmp.l #0x29696969, @long_dest 3017 1.1 christos beq .Llabs162 3018 1.1 christos fail 3019 1.1 christos .Llabs162: 3020 1.1 christos mov #0xa5a5a5a5, @long_dest 3021 1.1 christos 3022 1.1 christos shlr_l_abs32_2: 3023 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3024 1.1 christos set_ccr_zero 3025 1.1 christos 3026 1.1 christos shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 3027 1.1 christos ;;; .word 0x0104 3028 1.1 christos ;;; .word 0x6b28 3029 1.1 christos ;;; .long long_dest 3030 1.1 christos ;;; .word 0x1170 3031 1.1 christos 3032 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3033 1.1 christos test_zero_clear 3034 1.1 christos test_ovf_clear 3035 1.1 christos test_neg_clear 3036 1.1 christos 3037 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3038 1.1 christos test_gr_a5a5 1 3039 1.1 christos test_gr_a5a5 2 3040 1.1 christos test_gr_a5a5 3 3041 1.1 christos test_gr_a5a5 4 3042 1.1 christos test_gr_a5a5 5 3043 1.1 christos test_gr_a5a5 6 3044 1.1 christos test_gr_a5a5 7 3045 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3046 1.1 christos ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 3047 1.1 christos cmp.l #0x29696969, @long_dest 3048 1.1 christos beq .Llabs322 3049 1.1 christos fail 3050 1.1 christos .Llabs322: 3051 1.1 christos mov #0xa5a5a5a5, @long_dest 3052 1.1 christos 3053 1.1 christos shlr_l_reg32_4: 3054 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3055 1.1 christos set_ccr_zero 3056 1.1 christos 3057 1.1 christos shlr.l #4, er0 ; shift right logical by four, register 3058 1.1 christos ;;; .word 0x1138 3059 1.1 christos 3060 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3061 1.1 christos test_zero_clear 3062 1.1 christos test_ovf_clear 3063 1.1 christos test_neg_clear 3064 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3065 1.1 christos ; -> 0000 1010 0101 1010 0101 1010 0101 1010 3066 1.1 christos test_h_gr32 0x0a5a5a5a er0 3067 1.1 christos 3068 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3069 1.1 christos test_gr_a5a5 2 3070 1.1 christos test_gr_a5a5 3 3071 1.1 christos test_gr_a5a5 4 3072 1.1 christos test_gr_a5a5 5 3073 1.1 christos test_gr_a5a5 6 3074 1.1 christos test_gr_a5a5 7 3075 1.1 christos 3076 1.1 christos shlr_l_reg32_reg8: 3077 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3078 1.1 christos set_ccr_zero 3079 1.1 christos 3080 1.1 christos mov #5, r1l 3081 1.1 christos shlr.l r1l, er0 ; shift right logical by value of register 3082 1.1 christos 3083 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3084 1.1 christos test_zero_clear 3085 1.1 christos test_ovf_clear 3086 1.1 christos test_neg_clear 3087 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3088 1.1 christos ; -> 0000 0101 0010 1101 0010 1101 0010 1101 3089 1.1 christos test_h_gr32 0x052d2d2d er0 3090 1.1 christos test_h_gr32 0xa5a5a505 er1 3091 1.1 christos 3092 1.1 christos test_gr_a5a5 2 ; Make sure other general regs not disturbed 3093 1.1 christos test_gr_a5a5 3 3094 1.1 christos test_gr_a5a5 4 3095 1.1 christos test_gr_a5a5 5 3096 1.1 christos test_gr_a5a5 6 3097 1.1 christos test_gr_a5a5 7 3098 1.1 christos 3099 1.1 christos shlr_l_ind_4: 3100 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3101 1.1 christos set_ccr_zero 3102 1.1 christos 3103 1.1 christos mov #long_dest, er0 3104 1.1 christos shlr.l #4, @er0 ; shift right logical by four, indirect 3105 1.1 christos ;;; .word 0x0104 3106 1.1 christos ;;; .word 0x6908 3107 1.1 christos ;;; .word 0x1138 3108 1.1 christos 3109 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3110 1.1 christos test_zero_clear 3111 1.1 christos test_ovf_clear 3112 1.1 christos test_neg_clear 3113 1.1 christos 3114 1.1 christos test_h_gr32 long_dest er0 3115 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3116 1.1 christos test_gr_a5a5 2 3117 1.1 christos test_gr_a5a5 3 3118 1.1 christos test_gr_a5a5 4 3119 1.1 christos test_gr_a5a5 5 3120 1.1 christos test_gr_a5a5 6 3121 1.1 christos test_gr_a5a5 7 3122 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3123 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3124 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3125 1.1 christos beq .Llind4 3126 1.1 christos fail 3127 1.1 christos .Llind4: 3128 1.1 christos mov #0xa5a5a5a5, @long_dest 3129 1.1 christos 3130 1.1 christos shlr_l_postinc_4: 3131 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3132 1.1 christos set_ccr_zero 3133 1.1 christos 3134 1.1 christos mov #long_dest, er0 3135 1.1 christos shlr.l #4, @er0+ ; shift right logical by four, postinc 3136 1.1 christos ;;; .word 0x0104 3137 1.1 christos ;;; .word 0x6d08 3138 1.1 christos ;;; .word 0x1138 3139 1.1 christos 3140 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3141 1.1 christos test_zero_clear 3142 1.1 christos test_ovf_clear 3143 1.1 christos test_neg_clear 3144 1.1 christos 3145 1.1 christos test_h_gr32 long_dest+4 er0 3146 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3147 1.1 christos test_gr_a5a5 2 3148 1.1 christos test_gr_a5a5 3 3149 1.1 christos test_gr_a5a5 4 3150 1.1 christos test_gr_a5a5 5 3151 1.1 christos test_gr_a5a5 6 3152 1.1 christos test_gr_a5a5 7 3153 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3154 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3155 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3156 1.1 christos beq .Llpostinc4 3157 1.1 christos fail 3158 1.1 christos .Llpostinc4: 3159 1.1 christos mov #0xa5a5a5a5, @long_dest 3160 1.1 christos 3161 1.1 christos shlr_l_postdec_4: 3162 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3163 1.1 christos set_ccr_zero 3164 1.1 christos 3165 1.1 christos mov #long_dest, er0 3166 1.1 christos shlr.l #4, @er0- ; shift right logical by four, postdec 3167 1.1 christos ;;; .word 0x0106 3168 1.1 christos ;;; .word 0x6d08 3169 1.1 christos ;;; .word 0x1138 3170 1.1 christos 3171 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3172 1.1 christos test_zero_clear 3173 1.1 christos test_ovf_clear 3174 1.1 christos test_neg_clear 3175 1.1 christos 3176 1.1 christos test_h_gr32 long_dest-4 er0 3177 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3178 1.1 christos test_gr_a5a5 2 3179 1.1 christos test_gr_a5a5 3 3180 1.1 christos test_gr_a5a5 4 3181 1.1 christos test_gr_a5a5 5 3182 1.1 christos test_gr_a5a5 6 3183 1.1 christos test_gr_a5a5 7 3184 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3185 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3186 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3187 1.1 christos beq .Llpostdec4 3188 1.1 christos fail 3189 1.1 christos .Llpostdec4: 3190 1.1 christos mov #0xa5a5a5a5, @long_dest 3191 1.1 christos 3192 1.1 christos shlr_l_preinc_4: 3193 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3194 1.1 christos set_ccr_zero 3195 1.1 christos 3196 1.1 christos mov #long_dest-4, er0 3197 1.1 christos shlr.l #4, @+er0 ; shift right logical by four, preinc 3198 1.1 christos ;;; .word 0x0105 3199 1.1 christos ;;; .word 0x6d08 3200 1.1 christos ;;; .word 0x1138 3201 1.1 christos 3202 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3203 1.1 christos test_zero_clear 3204 1.1 christos test_ovf_clear 3205 1.1 christos test_neg_clear 3206 1.1 christos 3207 1.1 christos test_h_gr32 long_dest er0 3208 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3209 1.1 christos test_gr_a5a5 2 3210 1.1 christos test_gr_a5a5 3 3211 1.1 christos test_gr_a5a5 4 3212 1.1 christos test_gr_a5a5 5 3213 1.1 christos test_gr_a5a5 6 3214 1.1 christos test_gr_a5a5 7 3215 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3216 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3217 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3218 1.1 christos beq .Llpreinc4 3219 1.1 christos fail 3220 1.1 christos .Llpreinc4: 3221 1.1 christos mov #0xa5a5a5a5, @long_dest 3222 1.1 christos 3223 1.1 christos shlr_l_predec_4: 3224 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3225 1.1 christos set_ccr_zero 3226 1.1 christos 3227 1.1 christos mov #long_dest+4, er0 3228 1.1 christos shlr.l #4, @-er0 ; shift right logical by four, predec 3229 1.1 christos ;;; .word 0x0107 3230 1.1 christos ;;; .word 0x6d08 3231 1.1 christos ;;; .word 0x1138 3232 1.1 christos 3233 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3234 1.1 christos test_zero_clear 3235 1.1 christos test_ovf_clear 3236 1.1 christos test_neg_clear 3237 1.1 christos 3238 1.1 christos test_h_gr32 long_dest er0 3239 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3240 1.1 christos test_gr_a5a5 2 3241 1.1 christos test_gr_a5a5 3 3242 1.1 christos test_gr_a5a5 4 3243 1.1 christos test_gr_a5a5 5 3244 1.1 christos test_gr_a5a5 6 3245 1.1 christos test_gr_a5a5 7 3246 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3247 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3248 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3249 1.1 christos beq .Llpredec4 3250 1.1 christos fail 3251 1.1 christos .Llpredec4: 3252 1.1 christos mov #0xa5a5a5a5, @long_dest 3253 1.1 christos 3254 1.1 christos shlr_l_disp2_4: 3255 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3256 1.1 christos set_ccr_zero 3257 1.1 christos 3258 1.1 christos mov #long_dest-8, er0 3259 1.1 christos shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 3260 1.1 christos ;;; .word 0x0106 3261 1.1 christos ;;; .word 0x6908 3262 1.1 christos ;;; .word 0x1138 3263 1.1 christos 3264 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3265 1.1 christos test_zero_clear 3266 1.1 christos test_ovf_clear 3267 1.1 christos test_neg_clear 3268 1.1 christos 3269 1.1 christos test_h_gr32 long_dest-8 er0 3270 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3271 1.1 christos test_gr_a5a5 2 3272 1.1 christos test_gr_a5a5 3 3273 1.1 christos test_gr_a5a5 4 3274 1.1 christos test_gr_a5a5 5 3275 1.1 christos test_gr_a5a5 6 3276 1.1 christos test_gr_a5a5 7 3277 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3278 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3279 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3280 1.1 christos beq .Lldisp24 3281 1.1 christos fail 3282 1.1 christos .Lldisp24: 3283 1.1 christos mov #0xa5a5a5a5, @long_dest 3284 1.1 christos 3285 1.1 christos shlr_l_disp16_4: 3286 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3287 1.1 christos set_ccr_zero 3288 1.1 christos 3289 1.1 christos mov #long_dest-44, er0 3290 1.1 christos shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 3291 1.1 christos ;;; .word 0x0104 3292 1.1 christos ;;; .word 0x6f08 3293 1.1 christos ;;; .word 44 3294 1.1 christos ;;; .word 0x1138 3295 1.1 christos 3296 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3297 1.1 christos test_zero_clear 3298 1.1 christos test_ovf_clear 3299 1.1 christos test_neg_clear 3300 1.1 christos 3301 1.1 christos test_h_gr32 long_dest-44 er0 3302 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3303 1.1 christos test_gr_a5a5 2 3304 1.1 christos test_gr_a5a5 3 3305 1.1 christos test_gr_a5a5 4 3306 1.1 christos test_gr_a5a5 5 3307 1.1 christos test_gr_a5a5 6 3308 1.1 christos test_gr_a5a5 7 3309 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3310 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3311 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3312 1.1 christos beq .Lldisp164 3313 1.1 christos fail 3314 1.1 christos .Lldisp164: 3315 1.1 christos mov #0xa5a5a5a5, @long_dest 3316 1.1 christos 3317 1.1 christos shlr_l_disp32_4: 3318 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3319 1.1 christos set_ccr_zero 3320 1.1 christos 3321 1.1 christos mov #long_dest-666, er0 3322 1.1 christos shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 3323 1.1 christos ;;; .word 0x7884 3324 1.1 christos ;;; .word 0x6b28 3325 1.1 christos ;;; .long 666 3326 1.1 christos ;;; .word 0x1138 3327 1.1 christos 3328 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3329 1.1 christos test_zero_clear 3330 1.1 christos test_ovf_clear 3331 1.1 christos test_neg_clear 3332 1.1 christos 3333 1.1 christos test_h_gr32 long_dest-666 er0 3334 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3335 1.1 christos test_gr_a5a5 2 3336 1.1 christos test_gr_a5a5 3 3337 1.1 christos test_gr_a5a5 4 3338 1.1 christos test_gr_a5a5 5 3339 1.1 christos test_gr_a5a5 6 3340 1.1 christos test_gr_a5a5 7 3341 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3342 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3343 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3344 1.1 christos beq .Lldisp324 3345 1.1 christos fail 3346 1.1 christos .Lldisp324: 3347 1.1 christos mov #0xa5a5a5a5, @long_dest 3348 1.1 christos 3349 1.1 christos shlr_l_abs16_4: 3350 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3351 1.1 christos set_ccr_zero 3352 1.1 christos 3353 1.1 christos shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 3354 1.1 christos ;;; .word 0x0104 3355 1.1 christos ;;; .word 0x6b08 3356 1.1 christos ;;; .word long_dest 3357 1.1 christos ;;; .word 0x1138 3358 1.1 christos 3359 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3360 1.1 christos test_zero_clear 3361 1.1 christos test_ovf_clear 3362 1.1 christos test_neg_clear 3363 1.1 christos 3364 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3365 1.1 christos test_gr_a5a5 1 3366 1.1 christos test_gr_a5a5 2 3367 1.1 christos test_gr_a5a5 3 3368 1.1 christos test_gr_a5a5 4 3369 1.1 christos test_gr_a5a5 5 3370 1.1 christos test_gr_a5a5 6 3371 1.1 christos test_gr_a5a5 7 3372 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3373 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3374 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3375 1.1 christos beq .Llabs164 3376 1.1 christos fail 3377 1.1 christos .Llabs164: 3378 1.1 christos mov #0xa5a5a5a5, @long_dest 3379 1.1 christos 3380 1.1 christos shlr_l_abs32_4: 3381 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3382 1.1 christos set_ccr_zero 3383 1.1 christos 3384 1.1 christos shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 3385 1.1 christos ;;; .word 0x0104 3386 1.1 christos ;;; .word 0x6b28 3387 1.1 christos ;;; .long long_dest 3388 1.1 christos ;;; .word 0x1138 3389 1.1 christos 3390 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3391 1.1 christos test_zero_clear 3392 1.1 christos test_ovf_clear 3393 1.1 christos test_neg_clear 3394 1.1 christos 3395 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3396 1.1 christos test_gr_a5a5 1 3397 1.1 christos test_gr_a5a5 2 3398 1.1 christos test_gr_a5a5 3 3399 1.1 christos test_gr_a5a5 4 3400 1.1 christos test_gr_a5a5 5 3401 1.1 christos test_gr_a5a5 6 3402 1.1 christos test_gr_a5a5 7 3403 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3404 1.1 christos ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3405 1.1 christos cmp.l #0x0a5a5a5a, @long_dest 3406 1.1 christos beq .Llabs324 3407 1.1 christos fail 3408 1.1 christos .Llabs324: 3409 1.1 christos mov #0xa5a5a5a5, @long_dest 3410 1.1 christos 3411 1.1 christos shlr_l_reg32_8: 3412 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3413 1.1 christos set_ccr_zero 3414 1.1 christos 3415 1.1 christos shlr.l #8, er0 ; shift right logical by eight, register 3416 1.1 christos ;;; .word 0x1178 3417 1.1 christos 3418 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3419 1.1 christos test_zero_clear 3420 1.1 christos test_ovf_clear 3421 1.1 christos test_neg_clear 3422 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3423 1.1 christos ; -> 0000 0000 1010 0101 1010 0101 1010 0101 3424 1.1 christos test_h_gr32 0x00a5a5a5 er0 3425 1.1 christos 3426 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3427 1.1 christos test_gr_a5a5 2 3428 1.1 christos test_gr_a5a5 3 3429 1.1 christos test_gr_a5a5 4 3430 1.1 christos test_gr_a5a5 5 3431 1.1 christos test_gr_a5a5 6 3432 1.1 christos test_gr_a5a5 7 3433 1.1 christos 3434 1.1 christos shlr_l_ind_8: 3435 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3436 1.1 christos set_ccr_zero 3437 1.1 christos 3438 1.1 christos mov #long_dest, er0 3439 1.1 christos shlr.l #8, @er0 ; shift right logical by eight, indirect 3440 1.1 christos ;;; .word 0x0104 3441 1.1 christos ;;; .word 0x6908 3442 1.1 christos ;;; .word 0x1178 3443 1.1 christos 3444 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3445 1.1 christos test_zero_clear 3446 1.1 christos test_ovf_clear 3447 1.1 christos test_neg_clear 3448 1.1 christos 3449 1.1 christos test_h_gr32 long_dest er0 3450 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3451 1.1 christos test_gr_a5a5 2 3452 1.1 christos test_gr_a5a5 3 3453 1.1 christos test_gr_a5a5 4 3454 1.1 christos test_gr_a5a5 5 3455 1.1 christos test_gr_a5a5 6 3456 1.1 christos test_gr_a5a5 7 3457 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3458 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3459 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3460 1.1 christos beq .Llind8 3461 1.1 christos fail 3462 1.1 christos .Llind8: 3463 1.1 christos mov #0xa5a5a5a5, @long_dest 3464 1.1 christos 3465 1.1 christos shlr_l_postinc_8: 3466 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3467 1.1 christos set_ccr_zero 3468 1.1 christos 3469 1.1 christos mov #long_dest, er0 3470 1.1 christos shlr.l #8, @er0+ ; shift right logical by eight, postinc 3471 1.1 christos ;;; .word 0x0104 3472 1.1 christos ;;; .word 0x6d08 3473 1.1 christos ;;; .word 0x1178 3474 1.1 christos 3475 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3476 1.1 christos test_zero_clear 3477 1.1 christos test_ovf_clear 3478 1.1 christos test_neg_clear 3479 1.1 christos 3480 1.1 christos test_h_gr32 long_dest+4 er0 3481 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3482 1.1 christos test_gr_a5a5 2 3483 1.1 christos test_gr_a5a5 3 3484 1.1 christos test_gr_a5a5 4 3485 1.1 christos test_gr_a5a5 5 3486 1.1 christos test_gr_a5a5 6 3487 1.1 christos test_gr_a5a5 7 3488 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3489 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3490 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3491 1.1 christos beq .Llpostinc8 3492 1.1 christos fail 3493 1.1 christos .Llpostinc8: 3494 1.1 christos mov #0xa5a5a5a5, @long_dest 3495 1.1 christos 3496 1.1 christos shlr_l_postdec_8: 3497 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3498 1.1 christos set_ccr_zero 3499 1.1 christos 3500 1.1 christos mov #long_dest, er0 3501 1.1 christos shlr.l #8, @er0- ; shift right logical by eight, postdec 3502 1.1 christos ;;; .word 0x0106 3503 1.1 christos ;;; .word 0x6d08 3504 1.1 christos ;;; .word 0x1178 3505 1.1 christos 3506 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3507 1.1 christos test_zero_clear 3508 1.1 christos test_ovf_clear 3509 1.1 christos test_neg_clear 3510 1.1 christos 3511 1.1 christos test_h_gr32 long_dest-4 er0 3512 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3513 1.1 christos test_gr_a5a5 2 3514 1.1 christos test_gr_a5a5 3 3515 1.1 christos test_gr_a5a5 4 3516 1.1 christos test_gr_a5a5 5 3517 1.1 christos test_gr_a5a5 6 3518 1.1 christos test_gr_a5a5 7 3519 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3520 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3521 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3522 1.1 christos beq .Llpostdec8 3523 1.1 christos fail 3524 1.1 christos .Llpostdec8: 3525 1.1 christos mov #0xa5a5a5a5, @long_dest 3526 1.1 christos 3527 1.1 christos shlr_l_preinc_8: 3528 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3529 1.1 christos set_ccr_zero 3530 1.1 christos 3531 1.1 christos mov #long_dest-4, er0 3532 1.1 christos shlr.l #8, @+er0 ; shift right logical by eight, preinc 3533 1.1 christos ;;; .word 0x0105 3534 1.1 christos ;;; .word 0x6d08 3535 1.1 christos ;;; .word 0x1178 3536 1.1 christos 3537 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3538 1.1 christos test_zero_clear 3539 1.1 christos test_ovf_clear 3540 1.1 christos test_neg_clear 3541 1.1 christos 3542 1.1 christos test_h_gr32 long_dest er0 3543 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3544 1.1 christos test_gr_a5a5 2 3545 1.1 christos test_gr_a5a5 3 3546 1.1 christos test_gr_a5a5 4 3547 1.1 christos test_gr_a5a5 5 3548 1.1 christos test_gr_a5a5 6 3549 1.1 christos test_gr_a5a5 7 3550 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3551 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3552 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3553 1.1 christos beq .Llpreinc8 3554 1.1 christos fail 3555 1.1 christos .Llpreinc8: 3556 1.1 christos mov #0xa5a5a5a5, @long_dest 3557 1.1 christos 3558 1.1 christos shlr_l_predec_8: 3559 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3560 1.1 christos set_ccr_zero 3561 1.1 christos 3562 1.1 christos mov #long_dest+4, er0 3563 1.1 christos shlr.l #8, @-er0 ; shift right logical by eight, predec 3564 1.1 christos ;;; .word 0x0107 3565 1.1 christos ;;; .word 0x6d08 3566 1.1 christos ;;; .word 0x1178 3567 1.1 christos 3568 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3569 1.1 christos test_zero_clear 3570 1.1 christos test_ovf_clear 3571 1.1 christos test_neg_clear 3572 1.1 christos 3573 1.1 christos test_h_gr32 long_dest er0 3574 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3575 1.1 christos test_gr_a5a5 2 3576 1.1 christos test_gr_a5a5 3 3577 1.1 christos test_gr_a5a5 4 3578 1.1 christos test_gr_a5a5 5 3579 1.1 christos test_gr_a5a5 6 3580 1.1 christos test_gr_a5a5 7 3581 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3582 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3583 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3584 1.1 christos beq .Llpredec8 3585 1.1 christos fail 3586 1.1 christos .Llpredec8: 3587 1.1 christos mov #0xa5a5a5a5, @long_dest 3588 1.1 christos 3589 1.1 christos shlr_l_disp2_8: 3590 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3591 1.1 christos set_ccr_zero 3592 1.1 christos 3593 1.1 christos mov #long_dest-8, er0 3594 1.1 christos shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 3595 1.1 christos ;;; .word 0x0106 3596 1.1 christos ;;; .word 0x6908 3597 1.1 christos ;;; .word 0x1178 3598 1.1 christos 3599 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3600 1.1 christos test_zero_clear 3601 1.1 christos test_ovf_clear 3602 1.1 christos test_neg_clear 3603 1.1 christos 3604 1.1 christos test_h_gr32 long_dest-8 er0 3605 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3606 1.1 christos test_gr_a5a5 2 3607 1.1 christos test_gr_a5a5 3 3608 1.1 christos test_gr_a5a5 4 3609 1.1 christos test_gr_a5a5 5 3610 1.1 christos test_gr_a5a5 6 3611 1.1 christos test_gr_a5a5 7 3612 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3613 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3614 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3615 1.1 christos beq .Lldisp28 3616 1.1 christos fail 3617 1.1 christos .Lldisp28: 3618 1.1 christos mov #0xa5a5a5a5, @long_dest 3619 1.1 christos 3620 1.1 christos shlr_l_disp16_8: 3621 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3622 1.1 christos set_ccr_zero 3623 1.1 christos 3624 1.1 christos mov #long_dest-44, er0 3625 1.1 christos shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 3626 1.1 christos ;;; .word 0x0104 3627 1.1 christos ;;; .word 0x6f08 3628 1.1 christos ;;; .word 44 3629 1.1 christos ;;; .word 0x1178 3630 1.1 christos 3631 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3632 1.1 christos test_zero_clear 3633 1.1 christos test_ovf_clear 3634 1.1 christos test_neg_clear 3635 1.1 christos 3636 1.1 christos test_h_gr32 long_dest-44 er0 3637 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3638 1.1 christos test_gr_a5a5 2 3639 1.1 christos test_gr_a5a5 3 3640 1.1 christos test_gr_a5a5 4 3641 1.1 christos test_gr_a5a5 5 3642 1.1 christos test_gr_a5a5 6 3643 1.1 christos test_gr_a5a5 7 3644 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3645 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3646 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3647 1.1 christos beq .Lldisp168 3648 1.1 christos fail 3649 1.1 christos .Lldisp168: 3650 1.1 christos mov #0xa5a5a5a5, @long_dest 3651 1.1 christos 3652 1.1 christos shlr_l_disp32_8: 3653 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3654 1.1 christos set_ccr_zero 3655 1.1 christos 3656 1.1 christos mov #long_dest-666, er0 3657 1.1 christos shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 3658 1.1 christos ;;; .word 0x7884 3659 1.1 christos ;;; .word 0x6b28 3660 1.1 christos ;;; .long 666 3661 1.1 christos ;;; .word 0x1178 3662 1.1 christos 3663 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3664 1.1 christos test_zero_clear 3665 1.1 christos test_ovf_clear 3666 1.1 christos test_neg_clear 3667 1.1 christos 3668 1.1 christos test_h_gr32 long_dest-666 er0 3669 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3670 1.1 christos test_gr_a5a5 2 3671 1.1 christos test_gr_a5a5 3 3672 1.1 christos test_gr_a5a5 4 3673 1.1 christos test_gr_a5a5 5 3674 1.1 christos test_gr_a5a5 6 3675 1.1 christos test_gr_a5a5 7 3676 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3677 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3678 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3679 1.1 christos beq .Lldisp328 3680 1.1 christos fail 3681 1.1 christos .Lldisp328: 3682 1.1 christos mov #0xa5a5a5a5, @long_dest 3683 1.1 christos 3684 1.1 christos shlr_l_abs16_8: 3685 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3686 1.1 christos set_ccr_zero 3687 1.1 christos 3688 1.1 christos shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 3689 1.1 christos ;;; .word 0x0104 3690 1.1 christos ;;; .word 0x6b08 3691 1.1 christos ;;; .word long_dest 3692 1.1 christos ;;; .word 0x1178 3693 1.1 christos 3694 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3695 1.1 christos test_zero_clear 3696 1.1 christos test_ovf_clear 3697 1.1 christos test_neg_clear 3698 1.1 christos 3699 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3700 1.1 christos test_gr_a5a5 1 3701 1.1 christos test_gr_a5a5 2 3702 1.1 christos test_gr_a5a5 3 3703 1.1 christos test_gr_a5a5 4 3704 1.1 christos test_gr_a5a5 5 3705 1.1 christos test_gr_a5a5 6 3706 1.1 christos test_gr_a5a5 7 3707 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3708 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3709 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3710 1.1 christos beq .Llabs168 3711 1.1 christos fail 3712 1.1 christos .Llabs168: 3713 1.1 christos mov #0xa5a5a5a5, @long_dest 3714 1.1 christos 3715 1.1 christos shlr_l_abs32_8: 3716 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3717 1.1 christos set_ccr_zero 3718 1.1 christos 3719 1.1 christos shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 3720 1.1 christos ;;; .word 0x0104 3721 1.1 christos ;;; .word 0x6b28 3722 1.1 christos ;;; .long long_dest 3723 1.1 christos ;;; .word 0x1178 3724 1.1 christos 3725 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3726 1.1 christos test_zero_clear 3727 1.1 christos test_ovf_clear 3728 1.1 christos test_neg_clear 3729 1.1 christos 3730 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3731 1.1 christos test_gr_a5a5 1 3732 1.1 christos test_gr_a5a5 2 3733 1.1 christos test_gr_a5a5 3 3734 1.1 christos test_gr_a5a5 4 3735 1.1 christos test_gr_a5a5 5 3736 1.1 christos test_gr_a5a5 6 3737 1.1 christos test_gr_a5a5 7 3738 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3739 1.1 christos ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3740 1.1 christos cmp.l #0x00a5a5a5, @long_dest 3741 1.1 christos beq .Llabs328 3742 1.1 christos fail 3743 1.1 christos .Llabs328: 3744 1.1 christos mov #0xa5a5a5a5, @long_dest 3745 1.1 christos 3746 1.1 christos shlr_l_reg32_16: 3747 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3748 1.1 christos set_ccr_zero 3749 1.1 christos 3750 1.1 christos shlr.l #16, er0 ; shift right logical by sixteen, register 3751 1.1 christos ;;; .word 0x11f8 3752 1.1 christos 3753 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3754 1.1 christos test_zero_clear 3755 1.1 christos test_ovf_clear 3756 1.1 christos test_neg_clear 3757 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3758 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3759 1.1 christos test_h_gr32 0x0000a5a5 er0 3760 1.1 christos 3761 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3762 1.1 christos test_gr_a5a5 2 3763 1.1 christos test_gr_a5a5 3 3764 1.1 christos test_gr_a5a5 4 3765 1.1 christos test_gr_a5a5 5 3766 1.1 christos test_gr_a5a5 6 3767 1.1 christos test_gr_a5a5 7 3768 1.1 christos 3769 1.1 christos shlr_l_ind_16: 3770 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3771 1.1 christos set_ccr_zero 3772 1.1 christos 3773 1.1 christos mov #long_dest, er0 3774 1.1 christos shlr.l #16, @er0 ; shift right logical by sixteen, indirect 3775 1.1 christos ;;; .word 0x0104 3776 1.1 christos ;;; .word 0x6908 3777 1.1 christos ;;; .word 0x11f8 3778 1.1 christos 3779 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3780 1.1 christos test_zero_clear 3781 1.1 christos test_ovf_clear 3782 1.1 christos test_neg_clear 3783 1.1 christos 3784 1.1 christos test_h_gr32 long_dest er0 3785 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3786 1.1 christos test_gr_a5a5 2 3787 1.1 christos test_gr_a5a5 3 3788 1.1 christos test_gr_a5a5 4 3789 1.1 christos test_gr_a5a5 5 3790 1.1 christos test_gr_a5a5 6 3791 1.1 christos test_gr_a5a5 7 3792 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3793 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3794 1.1 christos cmp.l #0x0000a5a5, @long_dest 3795 1.1 christos beq .Llind16 3796 1.1 christos fail 3797 1.1 christos .Llind16: 3798 1.1 christos mov #0xa5a5a5a5, @long_dest 3799 1.1 christos 3800 1.1 christos shlr_l_postinc_16: 3801 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3802 1.1 christos set_ccr_zero 3803 1.1 christos 3804 1.1 christos mov #long_dest, er0 3805 1.1 christos shlr.l #16, @er0+ ; shift right logical by sixteen, postinc 3806 1.1 christos ;;; .word 0x0104 3807 1.1 christos ;;; .word 0x6d08 3808 1.1 christos ;;; .word 0x11f8 3809 1.1 christos 3810 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3811 1.1 christos test_zero_clear 3812 1.1 christos test_ovf_clear 3813 1.1 christos test_neg_clear 3814 1.1 christos 3815 1.1 christos test_h_gr32 long_dest+4 er0 3816 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3817 1.1 christos test_gr_a5a5 2 3818 1.1 christos test_gr_a5a5 3 3819 1.1 christos test_gr_a5a5 4 3820 1.1 christos test_gr_a5a5 5 3821 1.1 christos test_gr_a5a5 6 3822 1.1 christos test_gr_a5a5 7 3823 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3824 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3825 1.1 christos cmp.l #0x0000a5a5, @long_dest 3826 1.1 christos beq .Llpostinc16 3827 1.1 christos fail 3828 1.1 christos .Llpostinc16: 3829 1.1 christos mov #0xa5a5a5a5, @long_dest 3830 1.1 christos 3831 1.1 christos shlr_l_postdec_16: 3832 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3833 1.1 christos set_ccr_zero 3834 1.1 christos 3835 1.1 christos mov #long_dest, er0 3836 1.1 christos shlr.l #16, @er0- ; shift right logical by sixteen, postdec 3837 1.1 christos ;;; .word 0x0106 3838 1.1 christos ;;; .word 0x6d08 3839 1.1 christos ;;; .word 0x11f8 3840 1.1 christos 3841 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3842 1.1 christos test_zero_clear 3843 1.1 christos test_ovf_clear 3844 1.1 christos test_neg_clear 3845 1.1 christos 3846 1.1 christos test_h_gr32 long_dest-4 er0 3847 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3848 1.1 christos test_gr_a5a5 2 3849 1.1 christos test_gr_a5a5 3 3850 1.1 christos test_gr_a5a5 4 3851 1.1 christos test_gr_a5a5 5 3852 1.1 christos test_gr_a5a5 6 3853 1.1 christos test_gr_a5a5 7 3854 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3855 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3856 1.1 christos cmp.l #0x0000a5a5, @long_dest 3857 1.1 christos beq .Llpostdec16 3858 1.1 christos fail 3859 1.1 christos .Llpostdec16: 3860 1.1 christos mov #0xa5a5a5a5, @long_dest 3861 1.1 christos 3862 1.1 christos shlr_l_preinc_16: 3863 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3864 1.1 christos set_ccr_zero 3865 1.1 christos 3866 1.1 christos mov #long_dest-4, er0 3867 1.1 christos shlr.l #16, @+er0 ; shift right logical by sixteen, preinc 3868 1.1 christos ;;; .word 0x0105 3869 1.1 christos ;;; .word 0x6d08 3870 1.1 christos ;;; .word 0x11f8 3871 1.1 christos 3872 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3873 1.1 christos test_zero_clear 3874 1.1 christos test_ovf_clear 3875 1.1 christos test_neg_clear 3876 1.1 christos 3877 1.1 christos test_h_gr32 long_dest er0 3878 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3879 1.1 christos test_gr_a5a5 2 3880 1.1 christos test_gr_a5a5 3 3881 1.1 christos test_gr_a5a5 4 3882 1.1 christos test_gr_a5a5 5 3883 1.1 christos test_gr_a5a5 6 3884 1.1 christos test_gr_a5a5 7 3885 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3886 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3887 1.1 christos cmp.l #0x0000a5a5, @long_dest 3888 1.1 christos beq .Llpreinc16 3889 1.1 christos fail 3890 1.1 christos .Llpreinc16: 3891 1.1 christos mov #0xa5a5a5a5, @long_dest 3892 1.1 christos 3893 1.1 christos shlr_l_predec_16: 3894 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3895 1.1 christos set_ccr_zero 3896 1.1 christos 3897 1.1 christos mov #long_dest+4, er0 3898 1.1 christos shlr.l #16, @-er0 ; shift right logical by sixteen, predec 3899 1.1 christos ;;; .word 0x0107 3900 1.1 christos ;;; .word 0x6d08 3901 1.1 christos ;;; .word 0x11f8 3902 1.1 christos 3903 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3904 1.1 christos test_zero_clear 3905 1.1 christos test_ovf_clear 3906 1.1 christos test_neg_clear 3907 1.1 christos 3908 1.1 christos test_h_gr32 long_dest er0 3909 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3910 1.1 christos test_gr_a5a5 2 3911 1.1 christos test_gr_a5a5 3 3912 1.1 christos test_gr_a5a5 4 3913 1.1 christos test_gr_a5a5 5 3914 1.1 christos test_gr_a5a5 6 3915 1.1 christos test_gr_a5a5 7 3916 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3917 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3918 1.1 christos cmp.l #0x0000a5a5, @long_dest 3919 1.1 christos beq .Llpredec16 3920 1.1 christos fail 3921 1.1 christos .Llpredec16: 3922 1.1 christos mov #0xa5a5a5a5, @long_dest 3923 1.1 christos 3924 1.1 christos shlr_l_disp2_16: 3925 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3926 1.1 christos set_ccr_zero 3927 1.1 christos 3928 1.1 christos mov #long_dest-8, er0 3929 1.1 christos shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 3930 1.1 christos ;;; .word 0x0106 3931 1.1 christos ;;; .word 0x6908 3932 1.1 christos ;;; .word 0x11f8 3933 1.1 christos 3934 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3935 1.1 christos test_zero_clear 3936 1.1 christos test_ovf_clear 3937 1.1 christos test_neg_clear 3938 1.1 christos 3939 1.1 christos test_h_gr32 long_dest-8 er0 3940 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3941 1.1 christos test_gr_a5a5 2 3942 1.1 christos test_gr_a5a5 3 3943 1.1 christos test_gr_a5a5 4 3944 1.1 christos test_gr_a5a5 5 3945 1.1 christos test_gr_a5a5 6 3946 1.1 christos test_gr_a5a5 7 3947 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3948 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3949 1.1 christos cmp.l #0x0000a5a5, @long_dest 3950 1.1 christos beq .Lldisp216 3951 1.1 christos fail 3952 1.1 christos .Lldisp216: 3953 1.1 christos mov #0xa5a5a5a5, @long_dest 3954 1.1 christos 3955 1.1 christos shlr_l_disp16_16: 3956 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3957 1.1 christos set_ccr_zero 3958 1.1 christos 3959 1.1 christos mov #long_dest-44, er0 3960 1.1 christos shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 3961 1.1 christos ;;; .word 0x0104 3962 1.1 christos ;;; .word 0x6f08 3963 1.1 christos ;;; .word 44 3964 1.1 christos ;;; .word 0x11f8 3965 1.1 christos 3966 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3967 1.1 christos test_zero_clear 3968 1.1 christos test_ovf_clear 3969 1.1 christos test_neg_clear 3970 1.1 christos 3971 1.1 christos test_h_gr32 long_dest-44 er0 3972 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 3973 1.1 christos test_gr_a5a5 2 3974 1.1 christos test_gr_a5a5 3 3975 1.1 christos test_gr_a5a5 4 3976 1.1 christos test_gr_a5a5 5 3977 1.1 christos test_gr_a5a5 6 3978 1.1 christos test_gr_a5a5 7 3979 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 3980 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3981 1.1 christos cmp.l #0x0000a5a5, @long_dest 3982 1.1 christos beq .Lldisp1616 3983 1.1 christos fail 3984 1.1 christos .Lldisp1616: 3985 1.1 christos mov #0xa5a5a5a5, @long_dest 3986 1.1 christos 3987 1.1 christos shlr_l_disp32_16: 3988 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 3989 1.1 christos set_ccr_zero 3990 1.1 christos 3991 1.1 christos mov #long_dest-666, er0 3992 1.1 christos shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 3993 1.1 christos ;;; .word 0x7884 3994 1.1 christos ;;; .word 0x6b28 3995 1.1 christos ;;; .long 666 3996 1.1 christos ;;; .word 0x11f8 3997 1.1 christos 3998 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3999 1.1 christos test_zero_clear 4000 1.1 christos test_ovf_clear 4001 1.1 christos test_neg_clear 4002 1.1 christos 4003 1.1 christos test_h_gr32 long_dest-666 er0 4004 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 4005 1.1 christos test_gr_a5a5 2 4006 1.1 christos test_gr_a5a5 3 4007 1.1 christos test_gr_a5a5 4 4008 1.1 christos test_gr_a5a5 5 4009 1.1 christos test_gr_a5a5 6 4010 1.1 christos test_gr_a5a5 7 4011 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 4012 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4013 1.1 christos cmp.l #0x0000a5a5, @long_dest 4014 1.1 christos beq .Lldisp3216 4015 1.1 christos fail 4016 1.1 christos .Lldisp3216: 4017 1.1 christos mov #0xa5a5a5a5, @long_dest 4018 1.1 christos 4019 1.1 christos shlr_l_abs16_16: 4020 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 4021 1.1 christos set_ccr_zero 4022 1.1 christos 4023 1.1 christos shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 4024 1.1 christos ;;; .word 0x0104 4025 1.1 christos ;;; .word 0x6b08 4026 1.1 christos ;;; .word long_dest 4027 1.1 christos ;;; .word 0x11f8 4028 1.1 christos 4029 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 4030 1.1 christos test_zero_clear 4031 1.1 christos test_ovf_clear 4032 1.1 christos test_neg_clear 4033 1.1 christos 4034 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 4035 1.1 christos test_gr_a5a5 1 4036 1.1 christos test_gr_a5a5 2 4037 1.1 christos test_gr_a5a5 3 4038 1.1 christos test_gr_a5a5 4 4039 1.1 christos test_gr_a5a5 5 4040 1.1 christos test_gr_a5a5 6 4041 1.1 christos test_gr_a5a5 7 4042 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 4043 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4044 1.1 christos cmp.l #0x0000a5a5, @long_dest 4045 1.1 christos beq .Llabs1616 4046 1.1 christos fail 4047 1.1 christos .Llabs1616: 4048 1.1 christos mov #0xa5a5a5a5, @long_dest 4049 1.1 christos 4050 1.1 christos shlr_l_abs32_16: 4051 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 4052 1.1 christos set_ccr_zero 4053 1.1 christos 4054 1.1 christos shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 4055 1.1 christos ;;; .word 0x0104 4056 1.1 christos ;;; .word 0x6b28 4057 1.1 christos ;;; .long long_dest 4058 1.1 christos ;;; .word 0x11f8 4059 1.1 christos 4060 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 4061 1.1 christos test_zero_clear 4062 1.1 christos test_ovf_clear 4063 1.1 christos test_neg_clear 4064 1.1 christos 4065 1.1 christos test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 4066 1.1 christos test_gr_a5a5 1 4067 1.1 christos test_gr_a5a5 2 4068 1.1 christos test_gr_a5a5 3 4069 1.1 christos test_gr_a5a5 4 4070 1.1 christos test_gr_a5a5 5 4071 1.1 christos test_gr_a5a5 6 4072 1.1 christos test_gr_a5a5 7 4073 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 4074 1.1 christos ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4075 1.1 christos cmp.l #0x0000a5a5, @long_dest 4076 1.1 christos beq .Llabs3216 4077 1.1 christos fail 4078 1.1 christos .Llabs3216: 4079 1.1 christos mov #0xa5a5a5a5, @long_dest 4080 1.1 christos .endif 4081 1.1 christos .endif 4082 1.1 christos pass 4083 1.1 christos 4084 1.1 christos exit 0 4085 1.1 christos 4086
Indexes created Wed Apr 29 00:23:26 UTC 2026