shlr.s revision 1.1
1 # Hitachi H8 testcase 'shlr' 2 # mach(): h8300s h8sx 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .data 16 byte_dest: .byte 0xa5 17 .align 2 18 word_dest: .word 0xa5a5 19 .align 4 20 long_dest: .long 0xa5a5a5a5 21 22 .text 23 24 shlr_b_reg8_1: 25 set_grs_a5a5 ; Fill all general regs with a fixed pattern 26 set_ccr_zero 27 28 shlr.b r0l ; shift right logical by one 29 ;;; .word 0x1108 30 31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 32 test_zero_clear 33 test_ovf_clear 34 test_neg_clear 35 36 test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010 37 .if (sim_cpu) 38 test_h_gr32 0xa5a5a552 er0 39 .endif 40 test_gr_a5a5 1 ; Make sure other general regs not disturbed 41 test_gr_a5a5 2 42 test_gr_a5a5 3 43 test_gr_a5a5 4 44 test_gr_a5a5 5 45 test_gr_a5a5 6 46 test_gr_a5a5 7 47 48 .if (sim_cpu == h8sx) 49 shlr_b_ind_1: 50 set_grs_a5a5 ; Fill all general regs with a fixed pattern 51 set_ccr_zero 52 53 mov #byte_dest, er0 54 shlr.b @er0 ; shift right logical by one, indirect 55 ;;; .word 0x7d00 56 ;;; .word 0x1100 57 58 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 59 test_zero_clear 60 test_ovf_clear 61 test_neg_clear 62 63 test_h_gr32 byte_dest er0 64 test_gr_a5a5 1 ; Make sure other general regs not disturbed 65 test_gr_a5a5 2 66 test_gr_a5a5 3 67 test_gr_a5a5 4 68 test_gr_a5a5 5 69 test_gr_a5a5 6 70 test_gr_a5a5 7 71 ; 1010 0101 -> 0101 0010 72 cmp.b #0x52, @byte_dest 73 beq .Lbind1 74 fail 75 .Lbind1: 76 mov.b #0xa5, @byte_dest 77 78 shlr_b_postinc_1: 79 set_grs_a5a5 ; Fill all general regs with a fixed pattern 80 set_ccr_zero 81 82 mov #byte_dest, er0 83 shlr.b @er0+ ; shift right logical by one, postinc 84 ;;; .word 0x0174 85 ;;; .word 0x6c08 86 ;;; .word 0x1100 87 88 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 89 test_zero_clear 90 test_ovf_clear 91 test_neg_clear 92 93 test_h_gr32 byte_dest+1 er0 94 test_gr_a5a5 1 ; Make sure other general regs not disturbed 95 test_gr_a5a5 2 96 test_gr_a5a5 3 97 test_gr_a5a5 4 98 test_gr_a5a5 5 99 test_gr_a5a5 6 100 test_gr_a5a5 7 101 ; 1010 0101 -> 0101 0010 102 cmp.b #0x52, @byte_dest 103 beq .Lbpostinc1 104 fail 105 .Lbpostinc1: 106 mov.b #0xa5, @byte_dest 107 108 shlr_b_postdec_1: 109 set_grs_a5a5 ; Fill all general regs with a fixed pattern 110 set_ccr_zero 111 112 mov #byte_dest, er0 113 shlr.b @er0- ; shift right logical by one, postdec 114 ;;; .word 0x0176 115 ;;; .word 0x6c08 116 ;;; .word 0x1100 117 118 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 119 test_zero_clear 120 test_ovf_clear 121 test_neg_clear 122 123 test_h_gr32 byte_dest-1 er0 124 test_gr_a5a5 1 ; Make sure other general regs not disturbed 125 test_gr_a5a5 2 126 test_gr_a5a5 3 127 test_gr_a5a5 4 128 test_gr_a5a5 5 129 test_gr_a5a5 6 130 test_gr_a5a5 7 131 ; 1010 0101 -> 0101 0010 132 cmp.b #0x52, @byte_dest 133 beq .Lbpostdec1 134 fail 135 .Lbpostdec1: 136 mov.b #0xa5, @byte_dest 137 138 shlr_b_preinc_1: 139 set_grs_a5a5 ; Fill all general regs with a fixed pattern 140 set_ccr_zero 141 142 mov #byte_dest-1, er0 143 shlr.b @+er0 ; shift right logical by one, preinc 144 ;;; .word 0x0175 145 ;;; .word 0x6c08 146 ;;; .word 0x1100 147 148 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 149 test_zero_clear 150 test_ovf_clear 151 test_neg_clear 152 153 test_h_gr32 byte_dest er0 154 test_gr_a5a5 1 ; Make sure other general regs not disturbed 155 test_gr_a5a5 2 156 test_gr_a5a5 3 157 test_gr_a5a5 4 158 test_gr_a5a5 5 159 test_gr_a5a5 6 160 test_gr_a5a5 7 161 ; 1010 0101 -> 0101 0010 162 cmp.b #0x52, @byte_dest 163 beq .Lbpreinc1 164 fail 165 .Lbpreinc1: 166 mov.b #0xa5, @byte_dest 167 168 shlr_b_predec_1: 169 set_grs_a5a5 ; Fill all general regs with a fixed pattern 170 set_ccr_zero 171 172 mov #byte_dest+1, er0 173 shlr.b @-er0 ; shift right logical by one, predec 174 ;;; .word 0x0177 175 ;;; .word 0x6c08 176 ;;; .word 0x1100 177 178 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 179 test_zero_clear 180 test_ovf_clear 181 test_neg_clear 182 183 test_h_gr32 byte_dest er0 184 test_gr_a5a5 1 ; Make sure other general regs not disturbed 185 test_gr_a5a5 2 186 test_gr_a5a5 3 187 test_gr_a5a5 4 188 test_gr_a5a5 5 189 test_gr_a5a5 6 190 test_gr_a5a5 7 191 ; 1010 0101 -> 0101 0010 192 cmp.b #0x52, @byte_dest 193 beq .Lbpredec1 194 fail 195 .Lbpredec1: 196 mov.b #0xa5, @byte_dest 197 198 shlr_b_disp2_1: 199 set_grs_a5a5 ; Fill all general regs with a fixed pattern 200 set_ccr_zero 201 202 mov #byte_dest-2, er0 203 shlr.b @(2:2, er0) ; shift right logical by one, disp2 204 ;;; .word 0x0176 205 ;;; .word 0x6808 206 ;;; .word 0x1100 207 208 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 209 test_zero_clear 210 test_ovf_clear 211 test_neg_clear 212 213 test_h_gr32 byte_dest-2 er0 214 test_gr_a5a5 1 ; Make sure other general regs not disturbed 215 test_gr_a5a5 2 216 test_gr_a5a5 3 217 test_gr_a5a5 4 218 test_gr_a5a5 5 219 test_gr_a5a5 6 220 test_gr_a5a5 7 221 ; 1010 0101 -> 0101 0010 222 cmp.b #0x52, @byte_dest 223 beq .Lbdisp21 224 fail 225 .Lbdisp21: 226 mov.b #0xa5, @byte_dest 227 228 shlr_b_disp16_1: 229 set_grs_a5a5 ; Fill all general regs with a fixed pattern 230 set_ccr_zero 231 232 mov #byte_dest-44, er0 233 shlr.b @(44:16, er0) ; shift right logical by one, disp16 234 ;;; .word 0x0174 235 ;;; .word 0x6e08 236 ;;; .word 44 237 ;;; .word 0x1100 238 239 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 240 test_zero_clear 241 test_ovf_clear 242 test_neg_clear 243 244 test_h_gr32 byte_dest-44 er0 245 test_gr_a5a5 1 ; Make sure other general regs not disturbed 246 test_gr_a5a5 2 247 test_gr_a5a5 3 248 test_gr_a5a5 4 249 test_gr_a5a5 5 250 test_gr_a5a5 6 251 test_gr_a5a5 7 252 ; 1010 0101 -> 0101 0010 253 cmp.b #0x52, @byte_dest 254 beq .Lbdisp161 255 fail 256 .Lbdisp161: 257 mov.b #0xa5, @byte_dest 258 259 shlr_b_disp32_1: 260 set_grs_a5a5 ; Fill all general regs with a fixed pattern 261 set_ccr_zero 262 263 mov #byte_dest-666, er0 264 shlr.b @(666:32, er0) ; shift right logical by one, disp32 265 ;;; .word 0x7884 266 ;;; .word 0x6a28 267 ;;; .long 666 268 ;;; .word 0x1100 269 270 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 271 test_zero_clear 272 test_ovf_clear 273 test_neg_clear 274 275 test_h_gr32 byte_dest-666 er0 276 test_gr_a5a5 1 ; Make sure other general regs not disturbed 277 test_gr_a5a5 2 278 test_gr_a5a5 3 279 test_gr_a5a5 4 280 test_gr_a5a5 5 281 test_gr_a5a5 6 282 test_gr_a5a5 7 283 ; 1010 0101 -> 0101 0010 284 cmp.b #0x52, @byte_dest 285 beq .Lbdisp321 286 fail 287 .Lbdisp321: 288 mov.b #0xa5, @byte_dest 289 290 shlr_b_abs16_1: 291 set_grs_a5a5 ; Fill all general regs with a fixed pattern 292 set_ccr_zero 293 294 shlr.b @byte_dest:16 ; shift right logical by one, abs16 295 ;;; .word 0x6a18 296 ;;; .word byte_dest 297 ;;; .word 0x1100 298 299 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 300 test_zero_clear 301 test_ovf_clear 302 test_neg_clear 303 304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 305 test_gr_a5a5 2 306 test_gr_a5a5 2 307 test_gr_a5a5 3 308 test_gr_a5a5 4 309 test_gr_a5a5 5 310 test_gr_a5a5 6 311 test_gr_a5a5 7 312 ; 1010 0101 -> 0101 0010 313 cmp.b #0x52, @byte_dest 314 beq .Lbabs161 315 fail 316 .Lbabs161: 317 mov.b #0xa5, @byte_dest 318 319 shlr_b_abs32_1: 320 set_grs_a5a5 ; Fill all general regs with a fixed pattern 321 set_ccr_zero 322 323 shlr.b @byte_dest:32 ; shift right logical by one, abs32 324 ;;; .word 0x6a38 325 ;;; .long byte_dest 326 ;;; .word 0x1100 327 328 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 329 test_zero_clear 330 test_ovf_clear 331 test_neg_clear 332 333 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 334 test_gr_a5a5 2 335 test_gr_a5a5 2 336 test_gr_a5a5 3 337 test_gr_a5a5 4 338 test_gr_a5a5 5 339 test_gr_a5a5 6 340 test_gr_a5a5 7 341 ; 1010 0101 -> 0101 0010 342 cmp.b #0x52, @byte_dest 343 beq .Lbabs321 344 fail 345 .Lbabs321: 346 mov.b #0xa5, @byte_dest 347 .endif 348 349 shlr_b_reg8_2: 350 set_grs_a5a5 ; Fill all general regs with a fixed pattern 351 set_ccr_zero 352 353 shlr.b #2, r0l ; shift right logical by two 354 ;;; .word 0x1148 355 356 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 357 test_zero_clear 358 test_ovf_clear 359 test_neg_clear 360 test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001 361 .if (sim_cpu) 362 test_h_gr32 0xa5a5a529 er0 363 .endif 364 test_gr_a5a5 1 ; Make sure other general regs not disturbed 365 test_gr_a5a5 2 366 test_gr_a5a5 3 367 test_gr_a5a5 4 368 test_gr_a5a5 5 369 test_gr_a5a5 6 370 test_gr_a5a5 7 371 372 .if (sim_cpu == h8sx) 373 shlr_b_ind_2: 374 set_grs_a5a5 ; Fill all general regs with a fixed pattern 375 set_ccr_zero 376 377 mov #byte_dest, er0 378 shlr.b #2, @er0 ; shift right logical by two, indirect 379 ;;; .word 0x7d00 380 ;;; .word 0x1140 381 382 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 383 test_zero_clear 384 test_ovf_clear 385 test_neg_clear 386 387 test_h_gr32 byte_dest er0 388 test_gr_a5a5 1 ; Make sure other general regs not disturbed 389 test_gr_a5a5 2 390 test_gr_a5a5 3 391 test_gr_a5a5 4 392 test_gr_a5a5 5 393 test_gr_a5a5 6 394 test_gr_a5a5 7 395 ; 1010 0101 -> 0010 1001 396 cmp.b #0x29, @byte_dest 397 beq .Lbind2 398 fail 399 .Lbind2: 400 mov.b #0xa5, @byte_dest 401 402 shlr_b_postinc_2: 403 set_grs_a5a5 ; Fill all general regs with a fixed pattern 404 set_ccr_zero 405 406 mov #byte_dest, er0 407 shlr.b #2, @er0+ ; shift right logical by two, postinc 408 ;;; .word 0x0174 409 ;;; .word 0x6c08 410 ;;; .word 0x1140 411 412 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 413 test_zero_clear 414 test_ovf_clear 415 test_neg_clear 416 417 test_h_gr32 byte_dest+1 er0 418 test_gr_a5a5 1 ; Make sure other general regs not disturbed 419 test_gr_a5a5 2 420 test_gr_a5a5 3 421 test_gr_a5a5 4 422 test_gr_a5a5 5 423 test_gr_a5a5 6 424 test_gr_a5a5 7 425 ; 1010 0101 -> 0010 1001 426 cmp.b #0x29, @byte_dest 427 beq .Lbpostinc2 428 fail 429 .Lbpostinc2: 430 mov.b #0xa5, @byte_dest 431 432 shlr_b_postdec_2: 433 set_grs_a5a5 ; Fill all general regs with a fixed pattern 434 set_ccr_zero 435 436 mov #byte_dest, er0 437 shlr.b #2, @er0- ; shift right logical by two, postdec 438 ;;; .word 0x0176 439 ;;; .word 0x6c08 440 ;;; .word 0x1140 441 442 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 443 test_zero_clear 444 test_ovf_clear 445 test_neg_clear 446 447 test_h_gr32 byte_dest-1 er0 448 test_gr_a5a5 1 ; Make sure other general regs not disturbed 449 test_gr_a5a5 2 450 test_gr_a5a5 3 451 test_gr_a5a5 4 452 test_gr_a5a5 5 453 test_gr_a5a5 6 454 test_gr_a5a5 7 455 ; 1010 0101 -> 0010 1001 456 cmp.b #0x29, @byte_dest 457 beq .Lbpostdec2 458 fail 459 .Lbpostdec2: 460 mov.b #0xa5, @byte_dest 461 462 shlr_b_preinc_2: 463 set_grs_a5a5 ; Fill all general regs with a fixed pattern 464 set_ccr_zero 465 466 mov #byte_dest-1, er0 467 shlr.b #2, @+er0 ; shift right logical by two, preinc 468 ;;; .word 0x0175 469 ;;; .word 0x6c08 470 ;;; .word 0x1140 471 472 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 473 test_zero_clear 474 test_ovf_clear 475 test_neg_clear 476 477 test_h_gr32 byte_dest er0 478 test_gr_a5a5 1 ; Make sure other general regs not disturbed 479 test_gr_a5a5 2 480 test_gr_a5a5 3 481 test_gr_a5a5 4 482 test_gr_a5a5 5 483 test_gr_a5a5 6 484 test_gr_a5a5 7 485 ; 1010 0101 -> 0010 1001 486 cmp.b #0x29, @byte_dest 487 beq .Lbpreinc2 488 fail 489 .Lbpreinc2: 490 mov.b #0xa5, @byte_dest 491 492 shlr_b_predec_2: 493 set_grs_a5a5 ; Fill all general regs with a fixed pattern 494 set_ccr_zero 495 496 mov #byte_dest+1, er0 497 shlr.b #2, @-er0 ; shift right logical by two, predec 498 ;;; .word 0x0177 499 ;;; .word 0x6c08 500 ;;; .word 0x1140 501 502 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 503 test_zero_clear 504 test_ovf_clear 505 test_neg_clear 506 507 test_h_gr32 byte_dest er0 508 test_gr_a5a5 1 ; Make sure other general regs not disturbed 509 test_gr_a5a5 2 510 test_gr_a5a5 3 511 test_gr_a5a5 4 512 test_gr_a5a5 5 513 test_gr_a5a5 6 514 test_gr_a5a5 7 515 ; 1010 0101 -> 0010 1001 516 cmp.b #0x29, @byte_dest 517 beq .Lbpredec2 518 fail 519 .Lbpredec2: 520 mov.b #0xa5, @byte_dest 521 522 shlr_b_disp2_2: 523 set_grs_a5a5 ; Fill all general regs with a fixed pattern 524 set_ccr_zero 525 526 mov #byte_dest-2, er0 527 shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2 528 ;;; .word 0x0176 529 ;;; .word 0x6808 530 ;;; .word 0x1140 531 532 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 533 test_zero_clear 534 test_ovf_clear 535 test_neg_clear 536 537 test_h_gr32 byte_dest-2 er0 538 test_gr_a5a5 1 ; Make sure other general regs not disturbed 539 test_gr_a5a5 2 540 test_gr_a5a5 3 541 test_gr_a5a5 4 542 test_gr_a5a5 5 543 test_gr_a5a5 6 544 test_gr_a5a5 7 545 ; 1010 0101 -> 0010 1001 546 cmp.b #0x29, @byte_dest 547 beq .Lbdisp22 548 fail 549 .Lbdisp22: 550 mov.b #0xa5, @byte_dest 551 552 shlr_b_disp16_2: 553 set_grs_a5a5 ; Fill all general regs with a fixed pattern 554 set_ccr_zero 555 556 mov #byte_dest-44, er0 557 shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16 558 ;;; .word 0x0174 559 ;;; .word 0x6e08 560 ;;; .word 44 561 ;;; .word 0x1140 562 563 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 564 test_zero_clear 565 test_ovf_clear 566 test_neg_clear 567 568 test_h_gr32 byte_dest-44 er0 569 test_gr_a5a5 1 ; Make sure other general regs not disturbed 570 test_gr_a5a5 2 571 test_gr_a5a5 3 572 test_gr_a5a5 4 573 test_gr_a5a5 5 574 test_gr_a5a5 6 575 test_gr_a5a5 7 576 ; 1010 0101 -> 0010 1001 577 cmp.b #0x29, @byte_dest 578 beq .Lbdisp162 579 fail 580 .Lbdisp162: 581 mov.b #0xa5, @byte_dest 582 583 shlr_b_disp32_2: 584 set_grs_a5a5 ; Fill all general regs with a fixed pattern 585 set_ccr_zero 586 587 mov #byte_dest-666, er0 588 shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32 589 ;;; .word 0x7884 590 ;;; .word 0x6a28 591 ;;; .long 666 592 ;;; .word 0x1140 593 594 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 595 test_zero_clear 596 test_ovf_clear 597 test_neg_clear 598 599 test_h_gr32 byte_dest-666 er0 600 test_gr_a5a5 1 ; Make sure other general regs not disturbed 601 test_gr_a5a5 2 602 test_gr_a5a5 3 603 test_gr_a5a5 4 604 test_gr_a5a5 5 605 test_gr_a5a5 6 606 test_gr_a5a5 7 607 ; 1010 0101 -> 0010 1001 608 cmp.b #0x29, @byte_dest 609 beq .Lbdisp322 610 fail 611 .Lbdisp322: 612 mov.b #0xa5, @byte_dest 613 614 shlr_b_abs16_2: 615 set_grs_a5a5 ; Fill all general regs with a fixed pattern 616 set_ccr_zero 617 618 shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16 619 ;;; .word 0x6a18 620 ;;; .word byte_dest 621 ;;; .word 0x1140 622 623 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 624 test_zero_clear 625 test_ovf_clear 626 test_neg_clear 627 628 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 629 test_gr_a5a5 2 630 test_gr_a5a5 2 631 test_gr_a5a5 3 632 test_gr_a5a5 4 633 test_gr_a5a5 5 634 test_gr_a5a5 6 635 test_gr_a5a5 7 636 ; 1010 0101 -> 0010 1001 637 cmp.b #0x29, @byte_dest 638 beq .Lbabs162 639 fail 640 .Lbabs162: 641 mov.b #0xa5, @byte_dest 642 643 shlr_b_abs32_2: 644 set_grs_a5a5 ; Fill all general regs with a fixed pattern 645 set_ccr_zero 646 647 shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32 648 ;;; .word 0x6a38 649 ;;; .long byte_dest 650 ;;; .word 0x1140 651 652 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 653 test_zero_clear 654 test_ovf_clear 655 test_neg_clear 656 657 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 658 test_gr_a5a5 2 659 test_gr_a5a5 2 660 test_gr_a5a5 3 661 test_gr_a5a5 4 662 test_gr_a5a5 5 663 test_gr_a5a5 6 664 test_gr_a5a5 7 665 ; 1010 0101 -> 0010 1001 666 cmp.b #0x29, @byte_dest 667 beq .Lbabs322 668 fail 669 .Lbabs322: 670 mov.b #0xa5, @byte_dest 671 672 shlr_b_reg8_4: 673 set_grs_a5a5 ; Fill all general regs with a fixed pattern 674 set_ccr_zero 675 676 shlr.b #4, r0l ; shift right logical by four 677 ;;; .word 0x11a8 678 679 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 680 test_zero_clear 681 test_ovf_clear 682 test_neg_clear 683 684 test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010 685 test_h_gr32 0xa5a5a50a er0 686 test_gr_a5a5 1 ; Make sure other general regs not disturbed 687 test_gr_a5a5 2 688 test_gr_a5a5 3 689 test_gr_a5a5 4 690 test_gr_a5a5 5 691 test_gr_a5a5 6 692 test_gr_a5a5 7 693 694 shlr_b_reg8_reg8: 695 set_grs_a5a5 ; Fill all general regs with a fixed pattern 696 set_ccr_zero 697 698 mov #5, r0h 699 shlr.b r0h, r0l ; shift right logical by register value 700 701 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 702 test_zero_clear 703 test_ovf_clear 704 test_neg_clear 705 706 test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101 707 test_h_gr32 0xa5a50505 er0 708 test_gr_a5a5 1 ; Make sure other general regs not disturbed 709 test_gr_a5a5 2 710 test_gr_a5a5 3 711 test_gr_a5a5 4 712 test_gr_a5a5 5 713 test_gr_a5a5 6 714 test_gr_a5a5 7 715 716 shlr_b_ind_4: 717 set_grs_a5a5 ; Fill all general regs with a fixed pattern 718 set_ccr_zero 719 720 mov #byte_dest, er0 721 shlr.b #4, @er0 ; shift right logical by four, indirect 722 ;;; .word 0x7d00 723 ;;; .word 0x11a0 724 725 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 726 test_zero_clear 727 test_ovf_clear 728 test_neg_clear 729 730 test_h_gr32 byte_dest er0 731 test_gr_a5a5 1 ; Make sure other general regs not disturbed 732 test_gr_a5a5 2 733 test_gr_a5a5 3 734 test_gr_a5a5 4 735 test_gr_a5a5 5 736 test_gr_a5a5 6 737 test_gr_a5a5 7 738 ; 1010 0101 -> 0000 1010 739 cmp.b #0x0a, @byte_dest 740 beq .Lbind4 741 fail 742 .Lbind4: 743 mov.b #0xa5, @byte_dest 744 745 shlr_b_postinc_4: 746 set_grs_a5a5 ; Fill all general regs with a fixed pattern 747 set_ccr_zero 748 749 mov #byte_dest, er0 750 shlr.b #4, @er0+ ; shift right logical by four, postinc 751 ;;; .word 0x0174 752 ;;; .word 0x6c08 753 ;;; .word 0x11a0 754 755 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 756 test_zero_clear 757 test_ovf_clear 758 test_neg_clear 759 760 test_h_gr32 byte_dest+1 er0 761 test_gr_a5a5 1 ; Make sure other general regs not disturbed 762 test_gr_a5a5 2 763 test_gr_a5a5 3 764 test_gr_a5a5 4 765 test_gr_a5a5 5 766 test_gr_a5a5 6 767 test_gr_a5a5 7 768 ; 1010 0101 -> 0000 1010 769 cmp.b #0x0a, @byte_dest 770 beq .Lbpostinc4 771 fail 772 .Lbpostinc4: 773 mov.b #0xa5, @byte_dest 774 775 shlr_b_postdec_4: 776 set_grs_a5a5 ; Fill all general regs with a fixed pattern 777 set_ccr_zero 778 779 mov #byte_dest, er0 780 shlr.b #4, @er0- ; shift right logical by four, postdec 781 ;;; .word 0x0176 782 ;;; .word 0x6c08 783 ;;; .word 0x11a0 784 785 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 786 test_zero_clear 787 test_ovf_clear 788 test_neg_clear 789 790 test_h_gr32 byte_dest-1 er0 791 test_gr_a5a5 1 ; Make sure other general regs not disturbed 792 test_gr_a5a5 2 793 test_gr_a5a5 3 794 test_gr_a5a5 4 795 test_gr_a5a5 5 796 test_gr_a5a5 6 797 test_gr_a5a5 7 798 ; 1010 0101 -> 0000 1010 799 cmp.b #0x0a, @byte_dest 800 beq .Lbpostdec4 801 fail 802 .Lbpostdec4: 803 mov.b #0xa5, @byte_dest 804 805 shlr_b_preinc_4: 806 set_grs_a5a5 ; Fill all general regs with a fixed pattern 807 set_ccr_zero 808 809 mov #byte_dest-1, er0 810 shlr.b #4, @+er0 ; shift right logical by four, preinc 811 ;;; .word 0x0175 812 ;;; .word 0x6c08 813 ;;; .word 0x11a0 814 815 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 816 test_zero_clear 817 test_ovf_clear 818 test_neg_clear 819 820 test_h_gr32 byte_dest er0 821 test_gr_a5a5 1 ; Make sure other general regs not disturbed 822 test_gr_a5a5 2 823 test_gr_a5a5 3 824 test_gr_a5a5 4 825 test_gr_a5a5 5 826 test_gr_a5a5 6 827 test_gr_a5a5 7 828 ; 1010 0101 -> 0000 1010 829 cmp.b #0x0a, @byte_dest 830 beq .Lbpreinc4 831 fail 832 .Lbpreinc4: 833 mov.b #0xa5, @byte_dest 834 835 shlr_b_predec_4: 836 set_grs_a5a5 ; Fill all general regs with a fixed pattern 837 set_ccr_zero 838 839 mov #byte_dest+1, er0 840 shlr.b #4, @-er0 ; shift right logical by four, predec 841 ;;; .word 0x0177 842 ;;; .word 0x6c08 843 ;;; .word 0x11a0 844 845 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 846 test_zero_clear 847 test_ovf_clear 848 test_neg_clear 849 850 test_h_gr32 byte_dest er0 851 test_gr_a5a5 1 ; Make sure other general regs not disturbed 852 test_gr_a5a5 2 853 test_gr_a5a5 3 854 test_gr_a5a5 4 855 test_gr_a5a5 5 856 test_gr_a5a5 6 857 test_gr_a5a5 7 858 ; 1010 0101 -> 0000 1010 859 cmp.b #0x0a, @byte_dest 860 beq .Lbpredec4 861 fail 862 .Lbpredec4: 863 mov.b #0xa5, @byte_dest 864 865 shlr_b_disp2_4: 866 set_grs_a5a5 ; Fill all general regs with a fixed pattern 867 set_ccr_zero 868 869 mov #byte_dest-2, er0 870 shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2 871 ;;; .word 0x0176 872 ;;; .word 0x6808 873 ;;; .word 0x11a0 874 875 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 876 test_zero_clear 877 test_ovf_clear 878 test_neg_clear 879 880 test_h_gr32 byte_dest-2 er0 881 test_gr_a5a5 1 ; Make sure other general regs not disturbed 882 test_gr_a5a5 2 883 test_gr_a5a5 3 884 test_gr_a5a5 4 885 test_gr_a5a5 5 886 test_gr_a5a5 6 887 test_gr_a5a5 7 888 ; 1010 0101 -> 0000 1010 889 cmp.b #0x0a, @byte_dest 890 beq .Lbdisp24 891 fail 892 .Lbdisp24: 893 mov.b #0xa5, @byte_dest 894 895 shlr_b_disp16_4: 896 set_grs_a5a5 ; Fill all general regs with a fixed pattern 897 set_ccr_zero 898 899 mov #byte_dest-44, er0 900 shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16 901 ;;; .word 0x0174 902 ;;; .word 0x6e08 903 ;;; .word 44 904 ;;; .word 0x11a0 905 906 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 907 test_zero_clear 908 test_ovf_clear 909 test_neg_clear 910 911 test_h_gr32 byte_dest-44 er0 912 test_gr_a5a5 1 ; Make sure other general regs not disturbed 913 test_gr_a5a5 2 914 test_gr_a5a5 3 915 test_gr_a5a5 4 916 test_gr_a5a5 5 917 test_gr_a5a5 6 918 test_gr_a5a5 7 919 ; 1010 0101 -> 0000 1010 920 cmp.b #0x0a, @byte_dest 921 beq .Lbdisp164 922 fail 923 .Lbdisp164: 924 mov.b #0xa5, @byte_dest 925 926 shlr_b_disp32_4: 927 set_grs_a5a5 ; Fill all general regs with a fixed pattern 928 set_ccr_zero 929 930 mov #byte_dest-666, er0 931 shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32 932 ;;; .word 0x7884 933 ;;; .word 0x6a28 934 ;;; .long 666 935 ;;; .word 0x11a0 936 937 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 938 test_zero_clear 939 test_ovf_clear 940 test_neg_clear 941 942 test_h_gr32 byte_dest-666 er0 943 test_gr_a5a5 1 ; Make sure other general regs not disturbed 944 test_gr_a5a5 2 945 test_gr_a5a5 3 946 test_gr_a5a5 4 947 test_gr_a5a5 5 948 test_gr_a5a5 6 949 test_gr_a5a5 7 950 ; 1010 0101 -> 0000 1010 951 cmp.b #0x0a, @byte_dest 952 beq .Lbdisp324 953 fail 954 .Lbdisp324: 955 mov.b #0xa5, @byte_dest 956 957 shlr_b_abs16_4: 958 set_grs_a5a5 ; Fill all general regs with a fixed pattern 959 set_ccr_zero 960 961 shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16 962 ;;; .word 0x6a18 963 ;;; .word byte_dest 964 ;;; .word 0x11a0 965 966 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 967 test_zero_clear 968 test_ovf_clear 969 test_neg_clear 970 971 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 972 test_gr_a5a5 2 973 test_gr_a5a5 2 974 test_gr_a5a5 3 975 test_gr_a5a5 4 976 test_gr_a5a5 5 977 test_gr_a5a5 6 978 test_gr_a5a5 7 979 ; 1010 0101 -> 0000 1010 980 cmp.b #0x0a, @byte_dest 981 beq .Lbabs164 982 fail 983 .Lbabs164: 984 mov.b #0xa5, @byte_dest 985 986 shlr_b_abs32_4: 987 set_grs_a5a5 ; Fill all general regs with a fixed pattern 988 set_ccr_zero 989 990 shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32 991 ;;; .word 0x6a38 992 ;;; .long byte_dest 993 ;;; .word 0x11a0 994 995 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 996 test_zero_clear 997 test_ovf_clear 998 test_neg_clear 999 1000 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1001 test_gr_a5a5 2 1002 test_gr_a5a5 2 1003 test_gr_a5a5 3 1004 test_gr_a5a5 4 1005 test_gr_a5a5 5 1006 test_gr_a5a5 6 1007 test_gr_a5a5 7 1008 ; 1010 0101 -> 0000 1010 1009 cmp.b #0x0a, @byte_dest 1010 beq .Lbabs324 1011 fail 1012 .Lbabs324: 1013 mov.b #0xa5, @byte_dest 1014 .endif 1015 1016 .if (sim_cpu == h8sx) 1017 shlr_w_imm5_1: 1018 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1019 set_ccr_zero 1020 1021 shlr.w #15:5, r0 ; shift right logical by 5-bit immediate 1022 ;;; .word 0x038f 1023 ;;; .word 0x1110 1024 1025 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1026 test_zero_clear 1027 test_ovf_clear 1028 test_neg_clear 1029 1030 ; 1010 0101 1010 0101 -> 0000 0000 0000 0001 1031 test_h_gr32 0xa5a50001 er0 1032 1033 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1034 test_gr_a5a5 2 1035 test_gr_a5a5 3 1036 test_gr_a5a5 4 1037 test_gr_a5a5 5 1038 test_gr_a5a5 6 1039 test_gr_a5a5 7 1040 .endif 1041 1042 .if (sim_cpu) ; Not available in h8300 mode 1043 shlr_w_reg16_1: 1044 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1045 set_ccr_zero 1046 1047 shlr.w r0 ; shift right logical by one 1048 ;;; .word 0x1110 1049 1050 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1051 test_zero_clear 1052 test_ovf_clear 1053 test_neg_clear 1054 test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1055 test_h_gr32 0xa5a552d2 er0 1056 1057 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1058 test_gr_a5a5 2 1059 test_gr_a5a5 3 1060 test_gr_a5a5 4 1061 test_gr_a5a5 5 1062 test_gr_a5a5 6 1063 test_gr_a5a5 7 1064 1065 .if (sim_cpu == h8sx) 1066 shlr_w_ind_1: 1067 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1068 set_ccr_zero 1069 1070 mov #word_dest, er0 1071 shlr.w @er0 ; shift right logical by one, indirect 1072 ;;; .word 0x7d80 1073 ;;; .word 0x1110 1074 1075 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1076 test_zero_clear 1077 test_ovf_clear 1078 test_neg_clear 1079 1080 test_h_gr32 word_dest er0 1081 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1082 test_gr_a5a5 2 1083 test_gr_a5a5 3 1084 test_gr_a5a5 4 1085 test_gr_a5a5 5 1086 test_gr_a5a5 6 1087 test_gr_a5a5 7 1088 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1089 cmp.w #0x52d2, @word_dest 1090 beq .Lwind1 1091 fail 1092 .Lwind1: 1093 mov.w #0xa5a5, @word_dest 1094 1095 shlr_w_postinc_1: 1096 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1097 set_ccr_zero 1098 1099 mov #word_dest, er0 1100 shlr.w @er0+ ; shift right logical by one, postinc 1101 ;;; .word 0x0154 1102 ;;; .word 0x6d08 1103 ;;; .word 0x1110 1104 1105 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1106 test_zero_clear 1107 test_ovf_clear 1108 test_neg_clear 1109 1110 test_h_gr32 word_dest+2 er0 1111 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1112 test_gr_a5a5 2 1113 test_gr_a5a5 3 1114 test_gr_a5a5 4 1115 test_gr_a5a5 5 1116 test_gr_a5a5 6 1117 test_gr_a5a5 7 1118 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1119 cmp.w #0x52d2, @word_dest 1120 beq .Lwpostinc1 1121 fail 1122 .Lwpostinc1: 1123 mov.w #0xa5a5, @word_dest 1124 1125 shlr_w_postdec_1: 1126 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1127 set_ccr_zero 1128 1129 mov #word_dest, er0 1130 shlr.w @er0- ; shift right logical by one, postdec 1131 ;;; .word 0x0156 1132 ;;; .word 0x6d08 1133 ;;; .word 0x1110 1134 1135 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1136 test_zero_clear 1137 test_ovf_clear 1138 test_neg_clear 1139 1140 test_h_gr32 word_dest-2 er0 1141 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1142 test_gr_a5a5 2 1143 test_gr_a5a5 3 1144 test_gr_a5a5 4 1145 test_gr_a5a5 5 1146 test_gr_a5a5 6 1147 test_gr_a5a5 7 1148 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1149 cmp.w #0x52d2, @word_dest 1150 beq .Lwpostdec1 1151 fail 1152 .Lwpostdec1: 1153 mov.w #0xa5a5, @word_dest 1154 1155 shlr_w_preinc_1: 1156 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1157 set_ccr_zero 1158 1159 mov #word_dest-2, er0 1160 shlr.w @+er0 ; shift right logical by one, preinc 1161 ;;; .word 0x0155 1162 ;;; .word 0x6d08 1163 ;;; .word 0x1110 1164 1165 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1166 test_zero_clear 1167 test_ovf_clear 1168 test_neg_clear 1169 1170 test_h_gr32 word_dest er0 1171 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1172 test_gr_a5a5 2 1173 test_gr_a5a5 3 1174 test_gr_a5a5 4 1175 test_gr_a5a5 5 1176 test_gr_a5a5 6 1177 test_gr_a5a5 7 1178 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1179 cmp.w #0x52d2, @word_dest 1180 beq .Lwpreinc1 1181 fail 1182 .Lwpreinc1: 1183 mov.w #0xa5a5, @word_dest 1184 1185 shlr_w_predec_1: 1186 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1187 set_ccr_zero 1188 1189 mov #word_dest+2, er0 1190 shlr.w @-er0 ; shift right logical by one, predec 1191 ;;; .word 0x0157 1192 ;;; .word 0x6d08 1193 ;;; .word 0x1110 1194 1195 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1196 test_zero_clear 1197 test_ovf_clear 1198 test_neg_clear 1199 1200 test_h_gr32 word_dest er0 1201 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1202 test_gr_a5a5 2 1203 test_gr_a5a5 3 1204 test_gr_a5a5 4 1205 test_gr_a5a5 5 1206 test_gr_a5a5 6 1207 test_gr_a5a5 7 1208 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1209 cmp.w #0x52d2, @word_dest 1210 beq .Lwpredec1 1211 fail 1212 .Lwpredec1: 1213 mov.w #0xa5a5, @word_dest 1214 1215 shlr_w_disp2_1: 1216 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1217 set_ccr_zero 1218 1219 mov #word_dest-4, er0 1220 shlr.w @(4:2, er0) ; shift right logical by one, disp2 1221 ;;; .word 0x0156 1222 ;;; .word 0x6908 1223 ;;; .word 0x1110 1224 1225 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1226 test_zero_clear 1227 test_ovf_clear 1228 test_neg_clear 1229 1230 test_h_gr32 word_dest-4 er0 1231 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1232 test_gr_a5a5 2 1233 test_gr_a5a5 3 1234 test_gr_a5a5 4 1235 test_gr_a5a5 5 1236 test_gr_a5a5 6 1237 test_gr_a5a5 7 1238 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1239 cmp.w #0x52d2, @word_dest 1240 beq .Lwdisp21 1241 fail 1242 .Lwdisp21: 1243 mov.w #0xa5a5, @word_dest 1244 1245 shlr_w_disp16_1: 1246 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1247 set_ccr_zero 1248 1249 mov #word_dest-44, er0 1250 shlr.w @(44:16, er0) ; shift right logical by one, disp16 1251 ;;; .word 0x0154 1252 ;;; .word 0x6f08 1253 ;;; .word 44 1254 ;;; .word 0x1110 1255 1256 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1257 test_zero_clear 1258 test_ovf_clear 1259 test_neg_clear 1260 1261 test_h_gr32 word_dest-44 er0 1262 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1263 test_gr_a5a5 2 1264 test_gr_a5a5 3 1265 test_gr_a5a5 4 1266 test_gr_a5a5 5 1267 test_gr_a5a5 6 1268 test_gr_a5a5 7 1269 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1270 cmp.w #0x52d2, @word_dest 1271 beq .Lwdisp161 1272 fail 1273 .Lwdisp161: 1274 mov.w #0xa5a5, @word_dest 1275 1276 shlr_w_disp32_1: 1277 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1278 set_ccr_zero 1279 1280 mov #word_dest-666, er0 1281 shlr.w @(666:32, er0) ; shift right logical by one, disp32 1282 ;;; .word 0x7884 1283 ;;; .word 0x6b28 1284 ;;; .long 666 1285 ;;; .word 0x1110 1286 1287 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1288 test_zero_clear 1289 test_ovf_clear 1290 test_neg_clear 1291 1292 test_h_gr32 word_dest-666 er0 1293 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1294 test_gr_a5a5 2 1295 test_gr_a5a5 3 1296 test_gr_a5a5 4 1297 test_gr_a5a5 5 1298 test_gr_a5a5 6 1299 test_gr_a5a5 7 1300 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1301 cmp.w #0x52d2, @word_dest 1302 beq .Lwdisp321 1303 fail 1304 .Lwdisp321: 1305 mov.w #0xa5a5, @word_dest 1306 1307 shlr_w_abs16_1: 1308 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1309 set_ccr_zero 1310 1311 shlr.w @word_dest:16 ; shift right logical by one, abs16 1312 ;;; .word 0x6b18 1313 ;;; .word word_dest 1314 ;;; .word 0x1110 1315 1316 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1317 test_zero_clear 1318 test_ovf_clear 1319 test_neg_clear 1320 1321 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1322 test_gr_a5a5 1 1323 test_gr_a5a5 2 1324 test_gr_a5a5 3 1325 test_gr_a5a5 4 1326 test_gr_a5a5 5 1327 test_gr_a5a5 6 1328 test_gr_a5a5 7 1329 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1330 cmp.w #0x52d2, @word_dest 1331 beq .Lwabs161 1332 fail 1333 .Lwabs161: 1334 mov.w #0xa5a5, @word_dest 1335 1336 shlr_w_abs32_1: 1337 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1338 set_ccr_zero 1339 1340 shlr.w @word_dest:32 ; shift right logical by one, abs32 1341 ;;; .word 0x6b38 1342 ;;; .long word_dest 1343 ;;; .word 0x1110 1344 1345 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 1346 test_zero_clear 1347 test_ovf_clear 1348 test_neg_clear 1349 1350 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1351 test_gr_a5a5 1 1352 test_gr_a5a5 2 1353 test_gr_a5a5 3 1354 test_gr_a5a5 4 1355 test_gr_a5a5 5 1356 test_gr_a5a5 6 1357 test_gr_a5a5 7 1358 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010 1359 cmp.w #0x52d2, @word_dest 1360 beq .Lwabs321 1361 fail 1362 .Lwabs321: 1363 mov.w #0xa5a5, @word_dest 1364 .endif 1365 1366 shlr_w_reg16_2: 1367 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1368 set_ccr_zero 1369 1370 shlr.w #2, r0 ; shift right logical by two 1371 ;;; .word 0x1150 1372 1373 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1374 test_zero_clear 1375 test_ovf_clear 1376 test_neg_clear 1377 1378 test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1379 test_h_gr32 0xa5a52969 er0 1380 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1381 test_gr_a5a5 2 1382 test_gr_a5a5 3 1383 test_gr_a5a5 4 1384 test_gr_a5a5 5 1385 test_gr_a5a5 6 1386 test_gr_a5a5 7 1387 1388 .if (sim_cpu == h8sx) 1389 shlr_w_ind_2: 1390 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1391 set_ccr_zero 1392 1393 mov #word_dest, er0 1394 shlr.w #2, @er0 ; shift right logical by two, indirect 1395 ;;; .word 0x7d80 1396 ;;; .word 0x1150 1397 1398 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1399 test_zero_clear 1400 test_ovf_clear 1401 test_neg_clear 1402 1403 test_h_gr32 word_dest er0 1404 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1405 test_gr_a5a5 2 1406 test_gr_a5a5 3 1407 test_gr_a5a5 4 1408 test_gr_a5a5 5 1409 test_gr_a5a5 6 1410 test_gr_a5a5 7 1411 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1412 cmp.w #0x2969, @word_dest 1413 beq .Lwind2 1414 fail 1415 .Lwind2: 1416 mov.w #0xa5a5, @word_dest 1417 1418 shlr_w_postinc_2: 1419 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1420 set_ccr_zero 1421 1422 mov #word_dest, er0 1423 shlr.w #2, @er0+ ; shift right logical by two, postinc 1424 ;;; .word 0x0154 1425 ;;; .word 0x6d08 1426 ;;; .word 0x1150 1427 1428 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1429 test_zero_clear 1430 test_ovf_clear 1431 test_neg_clear 1432 1433 test_h_gr32 word_dest+2 er0 1434 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1435 test_gr_a5a5 2 1436 test_gr_a5a5 3 1437 test_gr_a5a5 4 1438 test_gr_a5a5 5 1439 test_gr_a5a5 6 1440 test_gr_a5a5 7 1441 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1442 cmp.w #0x2969, @word_dest 1443 beq .Lwpostinc2 1444 fail 1445 .Lwpostinc2: 1446 mov.w #0xa5a5, @word_dest 1447 1448 shlr_w_postdec_2: 1449 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1450 set_ccr_zero 1451 1452 mov #word_dest, er0 1453 shlr.w #2, @er0- ; shift right logical by two, postdec 1454 ;;; .word 0x0156 1455 ;;; .word 0x6d08 1456 ;;; .word 0x1150 1457 1458 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1459 test_zero_clear 1460 test_ovf_clear 1461 test_neg_clear 1462 1463 test_h_gr32 word_dest-2 er0 1464 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1465 test_gr_a5a5 2 1466 test_gr_a5a5 3 1467 test_gr_a5a5 4 1468 test_gr_a5a5 5 1469 test_gr_a5a5 6 1470 test_gr_a5a5 7 1471 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1472 cmp.w #0x2969, @word_dest 1473 beq .Lwpostdec2 1474 fail 1475 .Lwpostdec2: 1476 mov.w #0xa5a5, @word_dest 1477 1478 shlr_w_preinc_2: 1479 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1480 set_ccr_zero 1481 1482 mov #word_dest-2, er0 1483 shlr.w #2, @+er0 ; shift right logical by two, preinc 1484 ;;; .word 0x0155 1485 ;;; .word 0x6d08 1486 ;;; .word 0x1150 1487 1488 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1489 test_zero_clear 1490 test_ovf_clear 1491 test_neg_clear 1492 1493 test_h_gr32 word_dest er0 1494 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1495 test_gr_a5a5 2 1496 test_gr_a5a5 3 1497 test_gr_a5a5 4 1498 test_gr_a5a5 5 1499 test_gr_a5a5 6 1500 test_gr_a5a5 7 1501 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1502 cmp.w #0x2969, @word_dest 1503 beq .Lwpreinc2 1504 fail 1505 .Lwpreinc2: 1506 mov.w #0xa5a5, @word_dest 1507 1508 shlr_w_predec_2: 1509 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1510 set_ccr_zero 1511 1512 mov #word_dest+2, er0 1513 shlr.w #2, @-er0 ; shift right logical by two, predec 1514 ;;; .word 0x0157 1515 ;;; .word 0x6d08 1516 ;;; .word 0x1150 1517 1518 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1519 test_zero_clear 1520 test_ovf_clear 1521 test_neg_clear 1522 1523 test_h_gr32 word_dest er0 1524 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1525 test_gr_a5a5 2 1526 test_gr_a5a5 3 1527 test_gr_a5a5 4 1528 test_gr_a5a5 5 1529 test_gr_a5a5 6 1530 test_gr_a5a5 7 1531 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1532 cmp.w #0x2969, @word_dest 1533 beq .Lwpredec2 1534 fail 1535 .Lwpredec2: 1536 mov.w #0xa5a5, @word_dest 1537 1538 shlr_w_disp2_2: 1539 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1540 set_ccr_zero 1541 1542 mov #word_dest-4, er0 1543 shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 1544 ;;; .word 0x0156 1545 ;;; .word 0x6908 1546 ;;; .word 0x1150 1547 1548 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1549 test_zero_clear 1550 test_ovf_clear 1551 test_neg_clear 1552 1553 test_h_gr32 word_dest-4 er0 1554 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1555 test_gr_a5a5 2 1556 test_gr_a5a5 3 1557 test_gr_a5a5 4 1558 test_gr_a5a5 5 1559 test_gr_a5a5 6 1560 test_gr_a5a5 7 1561 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1562 cmp.w #0x2969, @word_dest 1563 beq .Lwdisp22 1564 fail 1565 .Lwdisp22: 1566 mov.w #0xa5a5, @word_dest 1567 1568 shlr_w_disp16_2: 1569 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1570 set_ccr_zero 1571 1572 mov #word_dest-44, er0 1573 shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16 1574 ;;; .word 0x0154 1575 ;;; .word 0x6f08 1576 ;;; .word 44 1577 ;;; .word 0x1150 1578 1579 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1580 test_zero_clear 1581 test_ovf_clear 1582 test_neg_clear 1583 1584 test_h_gr32 word_dest-44 er0 1585 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1586 test_gr_a5a5 2 1587 test_gr_a5a5 3 1588 test_gr_a5a5 4 1589 test_gr_a5a5 5 1590 test_gr_a5a5 6 1591 test_gr_a5a5 7 1592 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1593 cmp.w #0x2969, @word_dest 1594 beq .Lwdisp162 1595 fail 1596 .Lwdisp162: 1597 mov.w #0xa5a5, @word_dest 1598 1599 shlr_w_disp32_2: 1600 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1601 set_ccr_zero 1602 1603 mov #word_dest-666, er0 1604 shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32 1605 ;;; .word 0x7884 1606 ;;; .word 0x6b28 1607 ;;; .long 666 1608 ;;; .word 0x1150 1609 1610 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1611 test_zero_clear 1612 test_ovf_clear 1613 test_neg_clear 1614 1615 test_h_gr32 word_dest-666 er0 1616 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1617 test_gr_a5a5 2 1618 test_gr_a5a5 3 1619 test_gr_a5a5 4 1620 test_gr_a5a5 5 1621 test_gr_a5a5 6 1622 test_gr_a5a5 7 1623 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1624 cmp.w #0x2969, @word_dest 1625 beq .Lwdisp322 1626 fail 1627 .Lwdisp322: 1628 mov.w #0xa5a5, @word_dest 1629 1630 shlr_w_abs16_2: 1631 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1632 set_ccr_zero 1633 1634 shlr.w #2, @word_dest:16 ; shift right logical by two, abs16 1635 ;;; .word 0x6b18 1636 ;;; .word word_dest 1637 ;;; .word 0x1150 1638 1639 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1640 test_zero_clear 1641 test_ovf_clear 1642 test_neg_clear 1643 1644 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1645 test_gr_a5a5 2 1646 test_gr_a5a5 2 1647 test_gr_a5a5 3 1648 test_gr_a5a5 4 1649 test_gr_a5a5 5 1650 test_gr_a5a5 6 1651 test_gr_a5a5 7 1652 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1653 cmp.w #0x2969, @word_dest 1654 beq .Lwabs162 1655 fail 1656 .Lwabs162: 1657 mov.w #0xa5a5, @word_dest 1658 1659 shlr_w_abs32_2: 1660 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1661 set_ccr_zero 1662 1663 shlr.w #2, @word_dest:32 ; shift right logical by two, abs32 1664 ;;; .word 0x6b38 1665 ;;; .long word_dest 1666 ;;; .word 0x1150 1667 1668 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1669 test_zero_clear 1670 test_ovf_clear 1671 test_neg_clear 1672 1673 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1674 test_gr_a5a5 2 1675 test_gr_a5a5 2 1676 test_gr_a5a5 3 1677 test_gr_a5a5 4 1678 test_gr_a5a5 5 1679 test_gr_a5a5 6 1680 test_gr_a5a5 7 1681 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001 1682 cmp.w #0x2969, @word_dest 1683 beq .Lwabs322 1684 fail 1685 .Lwabs322: 1686 mov.w #0xa5a5, @word_dest 1687 1688 shlr_w_reg16_4: 1689 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1690 set_ccr_zero 1691 1692 shlr.w #4, r0 ; shift right logical by four 1693 ;;; .word 0x1120 1694 1695 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1696 test_zero_clear 1697 test_ovf_clear 1698 test_neg_clear 1699 1700 test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1701 test_h_gr32 0xa5a50a5a er0 1702 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1703 test_gr_a5a5 2 1704 test_gr_a5a5 3 1705 test_gr_a5a5 4 1706 test_gr_a5a5 5 1707 test_gr_a5a5 6 1708 test_gr_a5a5 7 1709 1710 shlr_w_reg16_reg8: 1711 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1712 set_ccr_zero 1713 1714 mov #5, r1l 1715 shlr.w r1l, r0 ; shift right logical by register value 1716 1717 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1718 test_zero_clear 1719 test_ovf_clear 1720 test_neg_clear 1721 1722 test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101 1723 test_h_gr32 0xa5a5052d er0 1724 test_h_gr32 0xa5a5a505 er1 1725 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1726 test_gr_a5a5 3 1727 test_gr_a5a5 4 1728 test_gr_a5a5 5 1729 test_gr_a5a5 6 1730 test_gr_a5a5 7 1731 1732 shlr_w_ind_4: 1733 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1734 set_ccr_zero 1735 1736 mov #word_dest, er0 1737 shlr.w #4, @er0 ; shift right logical by four, indirect 1738 ;;; .word 0x7d80 1739 ;;; .word 0x1120 1740 1741 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1742 test_zero_clear 1743 test_ovf_clear 1744 test_neg_clear 1745 1746 test_h_gr32 word_dest er0 1747 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1748 test_gr_a5a5 2 1749 test_gr_a5a5 3 1750 test_gr_a5a5 4 1751 test_gr_a5a5 5 1752 test_gr_a5a5 6 1753 test_gr_a5a5 7 1754 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1755 cmp.w #0x0a5a, @word_dest 1756 beq .Lwind4 1757 fail 1758 .Lwind4: 1759 mov.w #0xa5a5, @word_dest 1760 1761 shlr_w_postinc_4: 1762 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1763 set_ccr_zero 1764 1765 mov #word_dest, er0 1766 shlr.w #4, @er0+ ; shift right logical by four, postinc 1767 ;;; .word 0x0154 1768 ;;; .word 0x6d08 1769 ;;; .word 0x1120 1770 1771 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1772 test_zero_clear 1773 test_ovf_clear 1774 test_neg_clear 1775 1776 test_h_gr32 word_dest+2 er0 1777 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1778 test_gr_a5a5 2 1779 test_gr_a5a5 3 1780 test_gr_a5a5 4 1781 test_gr_a5a5 5 1782 test_gr_a5a5 6 1783 test_gr_a5a5 7 1784 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1785 cmp.w #0x0a5a, @word_dest 1786 beq .Lwpostinc4 1787 fail 1788 .Lwpostinc4: 1789 mov.w #0xa5a5, @word_dest 1790 1791 shlr_w_postdec_4: 1792 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1793 set_ccr_zero 1794 1795 mov #word_dest, er0 1796 shlr.w #4, @er0- ; shift right logical by four, postdec 1797 ;;; .word 0x0156 1798 ;;; .word 0x6d08 1799 ;;; .word 0x1120 1800 1801 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1802 test_zero_clear 1803 test_ovf_clear 1804 test_neg_clear 1805 1806 test_h_gr32 word_dest-2 er0 1807 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1808 test_gr_a5a5 2 1809 test_gr_a5a5 3 1810 test_gr_a5a5 4 1811 test_gr_a5a5 5 1812 test_gr_a5a5 6 1813 test_gr_a5a5 7 1814 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1815 cmp.w #0x0a5a, @word_dest 1816 beq .Lwpostdec4 1817 fail 1818 .Lwpostdec4: 1819 mov.w #0xa5a5, @word_dest 1820 1821 shlr_w_preinc_4: 1822 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1823 set_ccr_zero 1824 1825 mov #word_dest-2, er0 1826 shlr.w #4, @+er0 ; shift right logical by four, preinc 1827 ;;; .word 0x0155 1828 ;;; .word 0x6d08 1829 ;;; .word 0x1120 1830 1831 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1832 test_zero_clear 1833 test_ovf_clear 1834 test_neg_clear 1835 1836 test_h_gr32 word_dest er0 1837 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1838 test_gr_a5a5 2 1839 test_gr_a5a5 3 1840 test_gr_a5a5 4 1841 test_gr_a5a5 5 1842 test_gr_a5a5 6 1843 test_gr_a5a5 7 1844 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1845 cmp.w #0x0a5a, @word_dest 1846 beq .Lwpreinc4 1847 fail 1848 .Lwpreinc4: 1849 mov.w #0xa5a5, @word_dest 1850 1851 shlr_w_predec_4: 1852 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1853 set_ccr_zero 1854 1855 mov #word_dest+2, er0 1856 shlr.w #4, @-er0 ; shift right logical by four, predec 1857 ;;; .word 0x0157 1858 ;;; .word 0x6d08 1859 ;;; .word 0x1120 1860 1861 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1862 test_zero_clear 1863 test_ovf_clear 1864 test_neg_clear 1865 1866 test_h_gr32 word_dest er0 1867 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1868 test_gr_a5a5 2 1869 test_gr_a5a5 3 1870 test_gr_a5a5 4 1871 test_gr_a5a5 5 1872 test_gr_a5a5 6 1873 test_gr_a5a5 7 1874 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1875 cmp.w #0x0a5a, @word_dest 1876 beq .Lwpredec4 1877 fail 1878 .Lwpredec4: 1879 mov.w #0xa5a5, @word_dest 1880 1881 shlr_w_disp2_4: 1882 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1883 set_ccr_zero 1884 1885 mov #word_dest-4, er0 1886 shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 1887 ;;; .word 0x0156 1888 ;;; .word 0x6908 1889 ;;; .word 0x1120 1890 1891 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1892 test_zero_clear 1893 test_ovf_clear 1894 test_neg_clear 1895 1896 test_h_gr32 word_dest-4 er0 1897 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1898 test_gr_a5a5 2 1899 test_gr_a5a5 3 1900 test_gr_a5a5 4 1901 test_gr_a5a5 5 1902 test_gr_a5a5 6 1903 test_gr_a5a5 7 1904 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1905 cmp.w #0x0a5a, @word_dest 1906 beq .Lwdisp24 1907 fail 1908 .Lwdisp24: 1909 mov.w #0xa5a5, @word_dest 1910 1911 shlr_w_disp16_4: 1912 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1913 set_ccr_zero 1914 1915 mov #word_dest-44, er0 1916 shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16 1917 ;;; .word 0x0154 1918 ;;; .word 0x6f08 1919 ;;; .word 44 1920 ;;; .word 0x1120 1921 1922 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1923 test_zero_clear 1924 test_ovf_clear 1925 test_neg_clear 1926 1927 test_h_gr32 word_dest-44 er0 1928 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1929 test_gr_a5a5 2 1930 test_gr_a5a5 3 1931 test_gr_a5a5 4 1932 test_gr_a5a5 5 1933 test_gr_a5a5 6 1934 test_gr_a5a5 7 1935 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1936 cmp.w #0x0a5a, @word_dest 1937 beq .Lwdisp164 1938 fail 1939 .Lwdisp164: 1940 mov.w #0xa5a5, @word_dest 1941 1942 shlr_w_disp32_4: 1943 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1944 set_ccr_zero 1945 1946 mov #word_dest-666, er0 1947 shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32 1948 ;;; .word 0x7884 1949 ;;; .word 0x6b28 1950 ;;; .long 666 1951 ;;; .word 0x1120 1952 1953 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1954 test_zero_clear 1955 test_ovf_clear 1956 test_neg_clear 1957 1958 test_h_gr32 word_dest-666 er0 1959 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1960 test_gr_a5a5 2 1961 test_gr_a5a5 3 1962 test_gr_a5a5 4 1963 test_gr_a5a5 5 1964 test_gr_a5a5 6 1965 test_gr_a5a5 7 1966 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1967 cmp.w #0x0a5a, @word_dest 1968 beq .Lwdisp324 1969 fail 1970 .Lwdisp324: 1971 mov.w #0xa5a5, @word_dest 1972 1973 shlr_w_abs16_4: 1974 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1975 set_ccr_zero 1976 1977 shlr.w #4, @word_dest:16 ; shift right logical by four, abs16 1978 ;;; .word 0x6b18 1979 ;;; .word word_dest 1980 ;;; .word 0x1120 1981 1982 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 1983 test_zero_clear 1984 test_ovf_clear 1985 test_neg_clear 1986 1987 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1988 test_gr_a5a5 2 1989 test_gr_a5a5 2 1990 test_gr_a5a5 3 1991 test_gr_a5a5 4 1992 test_gr_a5a5 5 1993 test_gr_a5a5 6 1994 test_gr_a5a5 7 1995 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 1996 cmp.w #0x0a5a, @word_dest 1997 beq .Lwabs164 1998 fail 1999 .Lwabs164: 2000 mov.w #0xa5a5, @word_dest 2001 2002 shlr_w_abs32_4: 2003 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2004 set_ccr_zero 2005 2006 shlr.w #4, @word_dest:32 ; shift right logical by four, abs32 2007 ;;; .word 0x6b38 2008 ;;; .long word_dest 2009 ;;; .word 0x1120 2010 2011 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2012 test_zero_clear 2013 test_ovf_clear 2014 test_neg_clear 2015 2016 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2017 test_gr_a5a5 2 2018 test_gr_a5a5 2 2019 test_gr_a5a5 3 2020 test_gr_a5a5 4 2021 test_gr_a5a5 5 2022 test_gr_a5a5 6 2023 test_gr_a5a5 7 2024 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010 2025 cmp.w #0x0a5a, @word_dest 2026 beq .Lwabs324 2027 fail 2028 .Lwabs324: 2029 mov.w #0xa5a5, @word_dest 2030 2031 shlr_w_reg16_8: 2032 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2033 set_ccr_zero 2034 2035 shlr.w #8, r0 ; shift right logical by eight 2036 ;;; .word 0x1160 2037 2038 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2039 test_zero_clear 2040 test_ovf_clear 2041 test_neg_clear 2042 2043 test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2044 test_h_gr32 0xa5a500a5 er0 2045 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2046 test_gr_a5a5 2 2047 test_gr_a5a5 3 2048 test_gr_a5a5 4 2049 test_gr_a5a5 5 2050 test_gr_a5a5 6 2051 test_gr_a5a5 7 2052 2053 shlr_w_ind_8: 2054 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2055 set_ccr_zero 2056 2057 mov #word_dest, er0 2058 shlr.w #8, @er0 ; shift right logical by eight, indirect 2059 ;;; .word 0x7d80 2060 ;;; .word 0x1160 2061 2062 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2063 test_zero_clear 2064 test_ovf_clear 2065 test_neg_clear 2066 2067 test_h_gr32 word_dest er0 2068 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2069 test_gr_a5a5 2 2070 test_gr_a5a5 3 2071 test_gr_a5a5 4 2072 test_gr_a5a5 5 2073 test_gr_a5a5 6 2074 test_gr_a5a5 7 2075 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2076 cmp.w #0x00a5, @word_dest 2077 beq .Lwind8 2078 fail 2079 .Lwind8: 2080 mov.w #0xa5a5, @word_dest 2081 2082 shlr_w_postinc_8: 2083 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2084 set_ccr_zero 2085 2086 mov #word_dest, er0 2087 shlr.w #8, @er0+ ; shift right logical by eight, postinc 2088 ;;; .word 0x0154 2089 ;;; .word 0x6d08 2090 ;;; .word 0x1160 2091 2092 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2093 test_zero_clear 2094 test_ovf_clear 2095 test_neg_clear 2096 2097 test_h_gr32 word_dest+2 er0 2098 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2099 test_gr_a5a5 2 2100 test_gr_a5a5 3 2101 test_gr_a5a5 4 2102 test_gr_a5a5 5 2103 test_gr_a5a5 6 2104 test_gr_a5a5 7 2105 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2106 cmp.w #0x00a5, @word_dest 2107 beq .Lwpostinc8 2108 fail 2109 .Lwpostinc8: 2110 mov.w #0xa5a5, @word_dest 2111 2112 shlr_w_postdec_8: 2113 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2114 set_ccr_zero 2115 2116 mov #word_dest, er0 2117 shlr.w #8, @er0- ; shift right logical by eight, postdec 2118 ;;; .word 0x0156 2119 ;;; .word 0x6d08 2120 ;;; .word 0x1160 2121 2122 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2123 test_zero_clear 2124 test_ovf_clear 2125 test_neg_clear 2126 2127 test_h_gr32 word_dest-2 er0 2128 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2129 test_gr_a5a5 2 2130 test_gr_a5a5 3 2131 test_gr_a5a5 4 2132 test_gr_a5a5 5 2133 test_gr_a5a5 6 2134 test_gr_a5a5 7 2135 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2136 cmp.w #0x00a5, @word_dest 2137 beq .Lwpostdec8 2138 fail 2139 .Lwpostdec8: 2140 mov.w #0xa5a5, @word_dest 2141 2142 shlr_w_preinc_8: 2143 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2144 set_ccr_zero 2145 2146 mov #word_dest-2, er0 2147 shlr.w #8, @+er0 ; shift right logical by eight, preinc 2148 ;;; .word 0x0155 2149 ;;; .word 0x6d08 2150 ;;; .word 0x1160 2151 2152 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2153 test_zero_clear 2154 test_ovf_clear 2155 test_neg_clear 2156 2157 test_h_gr32 word_dest er0 2158 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2159 test_gr_a5a5 2 2160 test_gr_a5a5 3 2161 test_gr_a5a5 4 2162 test_gr_a5a5 5 2163 test_gr_a5a5 6 2164 test_gr_a5a5 7 2165 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2166 cmp.w #0x00a5, @word_dest 2167 beq .Lwpreinc8 2168 fail 2169 .Lwpreinc8: 2170 mov.w #0xa5a5, @word_dest 2171 2172 shlr_w_predec_8: 2173 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2174 set_ccr_zero 2175 2176 mov #word_dest+2, er0 2177 shlr.w #8, @-er0 ; shift right logical by eight, predec 2178 ;;; .word 0x0157 2179 ;;; .word 0x6d08 2180 ;;; .word 0x1160 2181 2182 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2183 test_zero_clear 2184 test_ovf_clear 2185 test_neg_clear 2186 2187 test_h_gr32 word_dest er0 2188 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2189 test_gr_a5a5 2 2190 test_gr_a5a5 3 2191 test_gr_a5a5 4 2192 test_gr_a5a5 5 2193 test_gr_a5a5 6 2194 test_gr_a5a5 7 2195 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2196 cmp.w #0x00a5, @word_dest 2197 beq .Lwpredec8 2198 fail 2199 .Lwpredec8: 2200 mov.w #0xa5a5, @word_dest 2201 2202 shlr_w_disp2_8: 2203 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2204 set_ccr_zero 2205 2206 mov #word_dest-4, er0 2207 shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 2208 ;;; .word 0x0156 2209 ;;; .word 0x6908 2210 ;;; .word 0x1160 2211 2212 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2213 test_zero_clear 2214 test_ovf_clear 2215 test_neg_clear 2216 2217 test_h_gr32 word_dest-4 er0 2218 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2219 test_gr_a5a5 2 2220 test_gr_a5a5 3 2221 test_gr_a5a5 4 2222 test_gr_a5a5 5 2223 test_gr_a5a5 6 2224 test_gr_a5a5 7 2225 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2226 cmp.w #0x00a5, @word_dest 2227 beq .Lwdisp28 2228 fail 2229 .Lwdisp28: 2230 mov.w #0xa5a5, @word_dest 2231 2232 shlr_w_disp16_8: 2233 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2234 set_ccr_zero 2235 2236 mov #word_dest-44, er0 2237 shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16 2238 ;;; .word 0x0154 2239 ;;; .word 0x6f08 2240 ;;; .word 44 2241 ;;; .word 0x1160 2242 2243 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2244 test_zero_clear 2245 test_ovf_clear 2246 test_neg_clear 2247 2248 test_h_gr32 word_dest-44 er0 2249 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2250 test_gr_a5a5 2 2251 test_gr_a5a5 3 2252 test_gr_a5a5 4 2253 test_gr_a5a5 5 2254 test_gr_a5a5 6 2255 test_gr_a5a5 7 2256 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2257 cmp.w #0x00a5, @word_dest 2258 beq .Lwdisp168 2259 fail 2260 .Lwdisp168: 2261 mov.w #0xa5a5, @word_dest 2262 2263 shlr_w_disp32_8: 2264 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2265 set_ccr_zero 2266 2267 mov #word_dest-666, er0 2268 shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32 2269 ;;; .word 0x7884 2270 ;;; .word 0x6b28 2271 ;;; .long 666 2272 ;;; .word 0x1160 2273 2274 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2275 test_zero_clear 2276 test_ovf_clear 2277 test_neg_clear 2278 2279 test_h_gr32 word_dest-666 er0 2280 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2281 test_gr_a5a5 2 2282 test_gr_a5a5 3 2283 test_gr_a5a5 4 2284 test_gr_a5a5 5 2285 test_gr_a5a5 6 2286 test_gr_a5a5 7 2287 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2288 cmp.w #0x00a5, @word_dest 2289 beq .Lwdisp328 2290 fail 2291 .Lwdisp328: 2292 mov.w #0xa5a5, @word_dest 2293 2294 shlr_w_abs16_8: 2295 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2296 set_ccr_zero 2297 2298 shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16 2299 ;;; .word 0x6b18 2300 ;;; .word word_dest 2301 ;;; .word 0x1160 2302 2303 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2304 test_zero_clear 2305 test_ovf_clear 2306 test_neg_clear 2307 2308 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2309 test_gr_a5a5 2 2310 test_gr_a5a5 2 2311 test_gr_a5a5 3 2312 test_gr_a5a5 4 2313 test_gr_a5a5 5 2314 test_gr_a5a5 6 2315 test_gr_a5a5 7 2316 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2317 cmp.w #0x00a5, @word_dest 2318 beq .Lwabs168 2319 fail 2320 .Lwabs168: 2321 mov.w #0xa5a5, @word_dest 2322 2323 shlr_w_abs32_8: 2324 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2325 set_ccr_zero 2326 2327 shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32 2328 ;;; .word 0x6b38 2329 ;;; .long word_dest 2330 ;;; .word 0x1160 2331 2332 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2333 test_zero_clear 2334 test_ovf_clear 2335 test_neg_clear 2336 2337 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2338 test_gr_a5a5 2 2339 test_gr_a5a5 2 2340 test_gr_a5a5 3 2341 test_gr_a5a5 4 2342 test_gr_a5a5 5 2343 test_gr_a5a5 6 2344 test_gr_a5a5 7 2345 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101 2346 cmp.w #0x00a5, @word_dest 2347 beq .Lwabs328 2348 fail 2349 .Lwabs328: 2350 mov.w #0xa5a5, @word_dest 2351 2352 shlr_l_imm5_1: 2353 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2354 set_ccr_zero 2355 2356 shlr.l #31:5, er0 ; shift right logical by 5-bit immediate 2357 ;;; .word 0x0399 2358 ;;; .word 0x1130 2359 2360 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2361 test_zero_clear 2362 test_ovf_clear 2363 test_neg_clear 2364 2365 ; 1010 0101 1010 0101 1010 0101 1010 0101 2366 ; -> 0000 0000 0000 0000 0000 0000 0000 0001 2367 test_h_gr32 0x1 er0 2368 2369 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2370 test_gr_a5a5 2 2371 test_gr_a5a5 3 2372 test_gr_a5a5 4 2373 test_gr_a5a5 5 2374 test_gr_a5a5 6 2375 test_gr_a5a5 7 2376 .endif 2377 2378 shlr_l_reg32_1: 2379 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2380 set_ccr_zero 2381 2382 shlr.l er0 ; shift right logical by one, register 2383 ;;; .word 0x1130 2384 2385 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2386 test_zero_clear 2387 test_ovf_clear 2388 test_neg_clear 2389 2390 ; 1010 0101 1010 0101 1010 0101 1010 0101 2391 ; -> 0101 0010 1101 0010 1101 0010 1101 0010 2392 test_h_gr32 0x52d2d2d2 er0 2393 2394 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2395 test_gr_a5a5 2 2396 test_gr_a5a5 3 2397 test_gr_a5a5 4 2398 test_gr_a5a5 5 2399 test_gr_a5a5 6 2400 test_gr_a5a5 7 2401 2402 .if (sim_cpu == h8sx) 2403 shlr_l_ind_1: 2404 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2405 set_ccr_zero 2406 2407 mov #long_dest, er0 2408 shlr.l @er0 ; shift right logical by one, indirect 2409 ;;; .word 0x0104 2410 ;;; .word 0x6908 2411 ;;; .word 0x1130 2412 2413 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2414 test_zero_clear 2415 test_ovf_clear 2416 test_neg_clear 2417 2418 test_h_gr32 long_dest er0 2419 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2420 test_gr_a5a5 2 2421 test_gr_a5a5 3 2422 test_gr_a5a5 4 2423 test_gr_a5a5 5 2424 test_gr_a5a5 6 2425 test_gr_a5a5 7 2426 ; 1010 0101 1010 0101 1010 0101 1010 0101 2427 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2428 cmp.l #0x52d2d2d2, @long_dest 2429 beq .Llind1 2430 fail 2431 .Llind1: 2432 mov #0xa5a5a5a5, @long_dest 2433 2434 shlr_l_postinc_1: 2435 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2436 set_ccr_zero 2437 2438 mov #long_dest, er0 2439 shlr.l @er0+ ; shift right logical by one, postinc 2440 ;;; .word 0x0104 2441 ;;; .word 0x6d08 2442 ;;; .word 0x1130 2443 2444 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2445 test_zero_clear 2446 test_ovf_clear 2447 test_neg_clear 2448 2449 test_h_gr32 long_dest+4 er0 2450 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2451 test_gr_a5a5 2 2452 test_gr_a5a5 3 2453 test_gr_a5a5 4 2454 test_gr_a5a5 5 2455 test_gr_a5a5 6 2456 test_gr_a5a5 7 2457 ; 1010 0101 1010 0101 1010 0101 1010 0101 2458 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2459 cmp.l #0x52d2d2d2, @long_dest 2460 beq .Llpostinc1 2461 fail 2462 .Llpostinc1: 2463 mov #0xa5a5a5a5, @long_dest 2464 2465 shlr_l_postdec_1: 2466 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2467 set_ccr_zero 2468 2469 mov #long_dest, er0 2470 shlr.l @er0- ; shift right logical by one, postdec 2471 ;;; .word 0x0106 2472 ;;; .word 0x6d08 2473 ;;; .word 0x1130 2474 2475 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2476 test_zero_clear 2477 test_ovf_clear 2478 test_neg_clear 2479 2480 test_h_gr32 long_dest-4 er0 2481 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2482 test_gr_a5a5 2 2483 test_gr_a5a5 3 2484 test_gr_a5a5 4 2485 test_gr_a5a5 5 2486 test_gr_a5a5 6 2487 test_gr_a5a5 7 2488 ; 1010 0101 1010 0101 1010 0101 1010 0101 2489 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2490 cmp.l #0x52d2d2d2, @long_dest 2491 beq .Llpostdec1 2492 fail 2493 .Llpostdec1: 2494 mov #0xa5a5a5a5, @long_dest 2495 2496 shlr_l_preinc_1: 2497 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2498 set_ccr_zero 2499 2500 mov #long_dest-4, er0 2501 shlr.l @+er0 ; shift right logical by one, preinc 2502 ;;; .word 0x0105 2503 ;;; .word 0x6d08 2504 ;;; .word 0x1130 2505 2506 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2507 test_zero_clear 2508 test_ovf_clear 2509 test_neg_clear 2510 2511 test_h_gr32 long_dest er0 2512 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2513 test_gr_a5a5 2 2514 test_gr_a5a5 3 2515 test_gr_a5a5 4 2516 test_gr_a5a5 5 2517 test_gr_a5a5 6 2518 test_gr_a5a5 7 2519 ; 1010 0101 1010 0101 1010 0101 1010 0101 2520 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2521 cmp.l #0x52d2d2d2, @long_dest 2522 beq .Llpreinc1 2523 fail 2524 .Llpreinc1: 2525 mov #0xa5a5a5a5, @long_dest 2526 2527 shlr_l_predec_1: 2528 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2529 set_ccr_zero 2530 2531 mov #long_dest+4, er0 2532 shlr.l @-er0 ; shift right logical by one, predec 2533 ;;; .word 0x0107 2534 ;;; .word 0x6d08 2535 ;;; .word 0x1130 2536 2537 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2538 test_zero_clear 2539 test_ovf_clear 2540 test_neg_clear 2541 2542 test_h_gr32 long_dest er0 2543 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2544 test_gr_a5a5 2 2545 test_gr_a5a5 3 2546 test_gr_a5a5 4 2547 test_gr_a5a5 5 2548 test_gr_a5a5 6 2549 test_gr_a5a5 7 2550 ; 1010 0101 1010 0101 1010 0101 1010 0101 2551 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2552 cmp.l #0x52d2d2d2, @long_dest 2553 beq .Llpredec1 2554 fail 2555 .Llpredec1: 2556 mov #0xa5a5a5a5, @long_dest 2557 2558 shlr_l_disp2_1: 2559 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2560 set_ccr_zero 2561 2562 mov #long_dest-8, er0 2563 shlr.l @(8:2, er0) ; shift right logical by one, disp2 2564 ;;; .word 0x0106 2565 ;;; .word 0x6908 2566 ;;; .word 0x1130 2567 2568 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2569 test_zero_clear 2570 test_ovf_clear 2571 test_neg_clear 2572 2573 test_h_gr32 long_dest-8 er0 2574 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2575 test_gr_a5a5 2 2576 test_gr_a5a5 3 2577 test_gr_a5a5 4 2578 test_gr_a5a5 5 2579 test_gr_a5a5 6 2580 test_gr_a5a5 7 2581 ; 1010 0101 1010 0101 1010 0101 1010 0101 2582 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2583 cmp.l #0x52d2d2d2, @long_dest 2584 beq .Lldisp21 2585 fail 2586 .Lldisp21: 2587 mov #0xa5a5a5a5, @long_dest 2588 2589 shlr_l_disp16_1: 2590 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2591 set_ccr_zero 2592 2593 mov #long_dest-44, er0 2594 shlr.l @(44:16, er0) ; shift right logical by one, disp16 2595 ;;; .word 0x0104 2596 ;;; .word 0x6f08 2597 ;;; .word 44 2598 ;;; .word 0x1130 2599 2600 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2601 test_zero_clear 2602 test_ovf_clear 2603 test_neg_clear 2604 2605 test_h_gr32 long_dest-44 er0 2606 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2607 test_gr_a5a5 2 2608 test_gr_a5a5 3 2609 test_gr_a5a5 4 2610 test_gr_a5a5 5 2611 test_gr_a5a5 6 2612 test_gr_a5a5 7 2613 ; 1010 0101 1010 0101 1010 0101 1010 0101 2614 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2615 cmp.l #0x52d2d2d2, @long_dest 2616 beq .Lldisp161 2617 fail 2618 .Lldisp161: 2619 mov #0xa5a5a5a5, @long_dest 2620 2621 shlr_l_disp32_1: 2622 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2623 set_ccr_zero 2624 2625 mov #long_dest-666, er0 2626 shlr.l @(666:32, er0) ; shift right logical by one, disp32 2627 ;;; .word 0x7884 2628 ;;; .word 0x6b28 2629 ;;; .long 666 2630 ;;; .word 0x1130 2631 2632 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2633 test_zero_clear 2634 test_ovf_clear 2635 test_neg_clear 2636 2637 test_h_gr32 long_dest-666 er0 2638 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2639 test_gr_a5a5 2 2640 test_gr_a5a5 3 2641 test_gr_a5a5 4 2642 test_gr_a5a5 5 2643 test_gr_a5a5 6 2644 test_gr_a5a5 7 2645 ; 1010 0101 1010 0101 1010 0101 1010 0101 2646 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2647 cmp.l #0x52d2d2d2, @long_dest 2648 beq .Lldisp321 2649 fail 2650 .Lldisp321: 2651 mov #0xa5a5a5a5, @long_dest 2652 2653 shlr_l_abs16_1: 2654 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2655 set_ccr_zero 2656 2657 shlr.l @long_dest:16 ; shift right logical by one, abs16 2658 ;;; .word 0x0104 2659 ;;; .word 0x6b08 2660 ;;; .word long_dest 2661 ;;; .word 0x1130 2662 2663 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2664 test_zero_clear 2665 test_ovf_clear 2666 test_neg_clear 2667 2668 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2669 test_gr_a5a5 1 2670 test_gr_a5a5 2 2671 test_gr_a5a5 3 2672 test_gr_a5a5 4 2673 test_gr_a5a5 5 2674 test_gr_a5a5 6 2675 test_gr_a5a5 7 2676 ; 1010 0101 1010 0101 1010 0101 1010 0101 2677 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2678 cmp.l #0x52d2d2d2, @long_dest 2679 beq .Llabs161 2680 fail 2681 .Llabs161: 2682 mov #0xa5a5a5a5, @long_dest 2683 2684 shlr_l_abs32_1: 2685 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2686 set_ccr_zero 2687 2688 shlr.l @long_dest:32 ; shift right logical by one, abs32 2689 ;;; .word 0x0104 2690 ;;; .word 0x6b28 2691 ;;; .long long_dest 2692 ;;; .word 0x1130 2693 2694 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 2695 test_zero_clear 2696 test_ovf_clear 2697 test_neg_clear 2698 2699 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 2700 test_gr_a5a5 1 2701 test_gr_a5a5 2 2702 test_gr_a5a5 3 2703 test_gr_a5a5 4 2704 test_gr_a5a5 5 2705 test_gr_a5a5 6 2706 test_gr_a5a5 7 2707 ; 1010 0101 1010 0101 1010 0101 1010 0101 2708 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010 2709 cmp.l #0x52d2d2d2, @long_dest 2710 beq .Llabs321 2711 fail 2712 .Llabs321: 2713 mov #0xa5a5a5a5, @long_dest 2714 .endif 2715 2716 shlr_l_reg32_2: 2717 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2718 set_ccr_zero 2719 2720 shlr.l #2, er0 ; shift right logical by two, register 2721 ;;; .word 0x1170 2722 2723 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2724 test_zero_clear 2725 test_ovf_clear 2726 test_neg_clear 2727 ; 1010 0101 1010 0101 1010 0101 1010 0101 2728 ; -> 0010 1001 0110 1001 0110 1001 0110 1001 2729 test_h_gr32 0x29696969 er0 2730 2731 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2732 test_gr_a5a5 2 2733 test_gr_a5a5 3 2734 test_gr_a5a5 4 2735 test_gr_a5a5 5 2736 test_gr_a5a5 6 2737 test_gr_a5a5 7 2738 2739 .if (sim_cpu == h8sx) 2740 2741 shlr_l_ind_2: 2742 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2743 set_ccr_zero 2744 2745 mov #long_dest, er0 2746 shlr.l #2, @er0 ; shift right logical by two, indirect 2747 ;;; .word 0x0104 2748 ;;; .word 0x6908 2749 ;;; .word 0x1170 2750 2751 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2752 test_zero_clear 2753 test_ovf_clear 2754 test_neg_clear 2755 2756 test_h_gr32 long_dest er0 2757 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2758 test_gr_a5a5 2 2759 test_gr_a5a5 3 2760 test_gr_a5a5 4 2761 test_gr_a5a5 5 2762 test_gr_a5a5 6 2763 test_gr_a5a5 7 2764 ; 1010 0101 1010 0101 1010 0101 1010 0101 2765 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2766 cmp.l #0x29696969, @long_dest 2767 beq .Llind2 2768 fail 2769 .Llind2: 2770 mov #0xa5a5a5a5, @long_dest 2771 2772 shlr_l_postinc_2: 2773 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2774 set_ccr_zero 2775 2776 mov #long_dest, er0 2777 shlr.l #2, @er0+ ; shift right logical by two, postinc 2778 ;;; .word 0x0104 2779 ;;; .word 0x6d08 2780 ;;; .word 0x1170 2781 2782 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2783 test_zero_clear 2784 test_ovf_clear 2785 test_neg_clear 2786 2787 test_h_gr32 long_dest+4 er0 2788 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2789 test_gr_a5a5 2 2790 test_gr_a5a5 3 2791 test_gr_a5a5 4 2792 test_gr_a5a5 5 2793 test_gr_a5a5 6 2794 test_gr_a5a5 7 2795 ; 1010 0101 1010 0101 1010 0101 1010 0101 2796 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2797 cmp.l #0x29696969, @long_dest 2798 beq .Llpostinc2 2799 fail 2800 .Llpostinc2: 2801 mov #0xa5a5a5a5, @long_dest 2802 2803 shlr_l_postdec_2: 2804 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2805 set_ccr_zero 2806 2807 mov #long_dest, er0 2808 shlr.l #2, @er0- ; shift right logical by two, postdec 2809 ;;; .word 0x0106 2810 ;;; .word 0x6d08 2811 ;;; .word 0x1170 2812 2813 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2814 test_zero_clear 2815 test_ovf_clear 2816 test_neg_clear 2817 2818 test_h_gr32 long_dest-4 er0 2819 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2820 test_gr_a5a5 2 2821 test_gr_a5a5 3 2822 test_gr_a5a5 4 2823 test_gr_a5a5 5 2824 test_gr_a5a5 6 2825 test_gr_a5a5 7 2826 ; 1010 0101 1010 0101 1010 0101 1010 0101 2827 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2828 cmp.l #0x29696969, @long_dest 2829 beq .Llpostdec2 2830 fail 2831 .Llpostdec2: 2832 mov #0xa5a5a5a5, @long_dest 2833 2834 shlr_l_preinc_2: 2835 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2836 set_ccr_zero 2837 2838 mov #long_dest-4, er0 2839 shlr.l #2, @+er0 ; shift right logical by two, preinc 2840 ;;; .word 0x0105 2841 ;;; .word 0x6d08 2842 ;;; .word 0x1170 2843 2844 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2845 test_zero_clear 2846 test_ovf_clear 2847 test_neg_clear 2848 2849 test_h_gr32 long_dest er0 2850 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2851 test_gr_a5a5 2 2852 test_gr_a5a5 3 2853 test_gr_a5a5 4 2854 test_gr_a5a5 5 2855 test_gr_a5a5 6 2856 test_gr_a5a5 7 2857 ; 1010 0101 1010 0101 1010 0101 1010 0101 2858 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2859 cmp.l #0x29696969, @long_dest 2860 beq .Llpreinc2 2861 fail 2862 .Llpreinc2: 2863 mov #0xa5a5a5a5, @long_dest 2864 2865 shlr_l_predec_2: 2866 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2867 set_ccr_zero 2868 2869 mov #long_dest+4, er0 2870 shlr.l #2, @-er0 ; shift right logical by two, predec 2871 ;;; .word 0x0107 2872 ;;; .word 0x6d08 2873 ;;; .word 0x1170 2874 2875 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2876 test_zero_clear 2877 test_ovf_clear 2878 test_neg_clear 2879 2880 test_h_gr32 long_dest er0 2881 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2882 test_gr_a5a5 2 2883 test_gr_a5a5 3 2884 test_gr_a5a5 4 2885 test_gr_a5a5 5 2886 test_gr_a5a5 6 2887 test_gr_a5a5 7 2888 ; 1010 0101 1010 0101 1010 0101 1010 0101 2889 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2890 cmp.l #0x29696969, @long_dest 2891 beq .Llpredec2 2892 fail 2893 .Llpredec2: 2894 mov #0xa5a5a5a5, @long_dest 2895 2896 shlr_l_disp2_2: 2897 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2898 set_ccr_zero 2899 2900 mov #long_dest-8, er0 2901 shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 2902 ;;; .word 0x0106 2903 ;;; .word 0x6908 2904 ;;; .word 0x1170 2905 2906 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2907 test_zero_clear 2908 test_ovf_clear 2909 test_neg_clear 2910 2911 test_h_gr32 long_dest-8 er0 2912 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2913 test_gr_a5a5 2 2914 test_gr_a5a5 3 2915 test_gr_a5a5 4 2916 test_gr_a5a5 5 2917 test_gr_a5a5 6 2918 test_gr_a5a5 7 2919 ; 1010 0101 1010 0101 1010 0101 1010 0101 2920 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2921 cmp.l #0x29696969, @long_dest 2922 beq .Lldisp22 2923 fail 2924 .Lldisp22: 2925 mov #0xa5a5a5a5, @long_dest 2926 2927 shlr_l_disp16_2: 2928 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2929 set_ccr_zero 2930 2931 mov #long_dest-44, er0 2932 shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16 2933 ;;; .word 0x0104 2934 ;;; .word 0x6f08 2935 ;;; .word 44 2936 ;;; .word 0x1170 2937 2938 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2939 test_zero_clear 2940 test_ovf_clear 2941 test_neg_clear 2942 2943 test_h_gr32 long_dest-44 er0 2944 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2945 test_gr_a5a5 2 2946 test_gr_a5a5 3 2947 test_gr_a5a5 4 2948 test_gr_a5a5 5 2949 test_gr_a5a5 6 2950 test_gr_a5a5 7 2951 ; 1010 0101 1010 0101 1010 0101 1010 0101 2952 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2953 cmp.l #0x29696969, @long_dest 2954 beq .Lldisp162 2955 fail 2956 .Lldisp162: 2957 mov #0xa5a5a5a5, @long_dest 2958 2959 shlr_l_disp32_2: 2960 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2961 set_ccr_zero 2962 2963 mov #long_dest-666, er0 2964 shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32 2965 ;;; .word 0x7884 2966 ;;; .word 0x6b28 2967 ;;; .long 666 2968 ;;; .word 0x1170 2969 2970 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 2971 test_zero_clear 2972 test_ovf_clear 2973 test_neg_clear 2974 2975 test_h_gr32 long_dest-666 er0 2976 test_gr_a5a5 1 ; Make sure other general regs not disturbed 2977 test_gr_a5a5 2 2978 test_gr_a5a5 3 2979 test_gr_a5a5 4 2980 test_gr_a5a5 5 2981 test_gr_a5a5 6 2982 test_gr_a5a5 7 2983 ; 1010 0101 1010 0101 1010 0101 1010 0101 2984 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 2985 cmp.l #0x29696969, @long_dest 2986 beq .Lldisp322 2987 fail 2988 .Lldisp322: 2989 mov #0xa5a5a5a5, @long_dest 2990 2991 shlr_l_abs16_2: 2992 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2993 set_ccr_zero 2994 2995 shlr.l #2, @long_dest:16 ; shift right logical by two, abs16 2996 ;;; .word 0x0104 2997 ;;; .word 0x6b08 2998 ;;; .word long_dest 2999 ;;; .word 0x1170 3000 3001 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3002 test_zero_clear 3003 test_ovf_clear 3004 test_neg_clear 3005 3006 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3007 test_gr_a5a5 1 3008 test_gr_a5a5 2 3009 test_gr_a5a5 3 3010 test_gr_a5a5 4 3011 test_gr_a5a5 5 3012 test_gr_a5a5 6 3013 test_gr_a5a5 7 3014 ; 1010 0101 1010 0101 1010 0101 1010 0101 3015 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 3016 cmp.l #0x29696969, @long_dest 3017 beq .Llabs162 3018 fail 3019 .Llabs162: 3020 mov #0xa5a5a5a5, @long_dest 3021 3022 shlr_l_abs32_2: 3023 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3024 set_ccr_zero 3025 3026 shlr.l #2, @long_dest:32 ; shift right logical by two, abs32 3027 ;;; .word 0x0104 3028 ;;; .word 0x6b28 3029 ;;; .long long_dest 3030 ;;; .word 0x1170 3031 3032 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3033 test_zero_clear 3034 test_ovf_clear 3035 test_neg_clear 3036 3037 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3038 test_gr_a5a5 1 3039 test_gr_a5a5 2 3040 test_gr_a5a5 3 3041 test_gr_a5a5 4 3042 test_gr_a5a5 5 3043 test_gr_a5a5 6 3044 test_gr_a5a5 7 3045 ; 1010 0101 1010 0101 1010 0101 1010 0101 3046 ;; -> 0010 1001 0110 1001 0110 1001 0110 1001 3047 cmp.l #0x29696969, @long_dest 3048 beq .Llabs322 3049 fail 3050 .Llabs322: 3051 mov #0xa5a5a5a5, @long_dest 3052 3053 shlr_l_reg32_4: 3054 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3055 set_ccr_zero 3056 3057 shlr.l #4, er0 ; shift right logical by four, register 3058 ;;; .word 0x1138 3059 3060 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3061 test_zero_clear 3062 test_ovf_clear 3063 test_neg_clear 3064 ; 1010 0101 1010 0101 1010 0101 1010 0101 3065 ; -> 0000 1010 0101 1010 0101 1010 0101 1010 3066 test_h_gr32 0x0a5a5a5a er0 3067 3068 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3069 test_gr_a5a5 2 3070 test_gr_a5a5 3 3071 test_gr_a5a5 4 3072 test_gr_a5a5 5 3073 test_gr_a5a5 6 3074 test_gr_a5a5 7 3075 3076 shlr_l_reg32_reg8: 3077 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3078 set_ccr_zero 3079 3080 mov #5, r1l 3081 shlr.l r1l, er0 ; shift right logical by value of register 3082 3083 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3084 test_zero_clear 3085 test_ovf_clear 3086 test_neg_clear 3087 ; 1010 0101 1010 0101 1010 0101 1010 0101 3088 ; -> 0000 0101 0010 1101 0010 1101 0010 1101 3089 test_h_gr32 0x052d2d2d er0 3090 test_h_gr32 0xa5a5a505 er1 3091 3092 test_gr_a5a5 2 ; Make sure other general regs not disturbed 3093 test_gr_a5a5 3 3094 test_gr_a5a5 4 3095 test_gr_a5a5 5 3096 test_gr_a5a5 6 3097 test_gr_a5a5 7 3098 3099 shlr_l_ind_4: 3100 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3101 set_ccr_zero 3102 3103 mov #long_dest, er0 3104 shlr.l #4, @er0 ; shift right logical by four, indirect 3105 ;;; .word 0x0104 3106 ;;; .word 0x6908 3107 ;;; .word 0x1138 3108 3109 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3110 test_zero_clear 3111 test_ovf_clear 3112 test_neg_clear 3113 3114 test_h_gr32 long_dest er0 3115 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3116 test_gr_a5a5 2 3117 test_gr_a5a5 3 3118 test_gr_a5a5 4 3119 test_gr_a5a5 5 3120 test_gr_a5a5 6 3121 test_gr_a5a5 7 3122 ; 1010 0101 1010 0101 1010 0101 1010 0101 3123 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3124 cmp.l #0x0a5a5a5a, @long_dest 3125 beq .Llind4 3126 fail 3127 .Llind4: 3128 mov #0xa5a5a5a5, @long_dest 3129 3130 shlr_l_postinc_4: 3131 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3132 set_ccr_zero 3133 3134 mov #long_dest, er0 3135 shlr.l #4, @er0+ ; shift right logical by four, postinc 3136 ;;; .word 0x0104 3137 ;;; .word 0x6d08 3138 ;;; .word 0x1138 3139 3140 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3141 test_zero_clear 3142 test_ovf_clear 3143 test_neg_clear 3144 3145 test_h_gr32 long_dest+4 er0 3146 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3147 test_gr_a5a5 2 3148 test_gr_a5a5 3 3149 test_gr_a5a5 4 3150 test_gr_a5a5 5 3151 test_gr_a5a5 6 3152 test_gr_a5a5 7 3153 ; 1010 0101 1010 0101 1010 0101 1010 0101 3154 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3155 cmp.l #0x0a5a5a5a, @long_dest 3156 beq .Llpostinc4 3157 fail 3158 .Llpostinc4: 3159 mov #0xa5a5a5a5, @long_dest 3160 3161 shlr_l_postdec_4: 3162 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3163 set_ccr_zero 3164 3165 mov #long_dest, er0 3166 shlr.l #4, @er0- ; shift right logical by four, postdec 3167 ;;; .word 0x0106 3168 ;;; .word 0x6d08 3169 ;;; .word 0x1138 3170 3171 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3172 test_zero_clear 3173 test_ovf_clear 3174 test_neg_clear 3175 3176 test_h_gr32 long_dest-4 er0 3177 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3178 test_gr_a5a5 2 3179 test_gr_a5a5 3 3180 test_gr_a5a5 4 3181 test_gr_a5a5 5 3182 test_gr_a5a5 6 3183 test_gr_a5a5 7 3184 ; 1010 0101 1010 0101 1010 0101 1010 0101 3185 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3186 cmp.l #0x0a5a5a5a, @long_dest 3187 beq .Llpostdec4 3188 fail 3189 .Llpostdec4: 3190 mov #0xa5a5a5a5, @long_dest 3191 3192 shlr_l_preinc_4: 3193 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3194 set_ccr_zero 3195 3196 mov #long_dest-4, er0 3197 shlr.l #4, @+er0 ; shift right logical by four, preinc 3198 ;;; .word 0x0105 3199 ;;; .word 0x6d08 3200 ;;; .word 0x1138 3201 3202 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3203 test_zero_clear 3204 test_ovf_clear 3205 test_neg_clear 3206 3207 test_h_gr32 long_dest er0 3208 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3209 test_gr_a5a5 2 3210 test_gr_a5a5 3 3211 test_gr_a5a5 4 3212 test_gr_a5a5 5 3213 test_gr_a5a5 6 3214 test_gr_a5a5 7 3215 ; 1010 0101 1010 0101 1010 0101 1010 0101 3216 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3217 cmp.l #0x0a5a5a5a, @long_dest 3218 beq .Llpreinc4 3219 fail 3220 .Llpreinc4: 3221 mov #0xa5a5a5a5, @long_dest 3222 3223 shlr_l_predec_4: 3224 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3225 set_ccr_zero 3226 3227 mov #long_dest+4, er0 3228 shlr.l #4, @-er0 ; shift right logical by four, predec 3229 ;;; .word 0x0107 3230 ;;; .word 0x6d08 3231 ;;; .word 0x1138 3232 3233 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3234 test_zero_clear 3235 test_ovf_clear 3236 test_neg_clear 3237 3238 test_h_gr32 long_dest er0 3239 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3240 test_gr_a5a5 2 3241 test_gr_a5a5 3 3242 test_gr_a5a5 4 3243 test_gr_a5a5 5 3244 test_gr_a5a5 6 3245 test_gr_a5a5 7 3246 ; 1010 0101 1010 0101 1010 0101 1010 0101 3247 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3248 cmp.l #0x0a5a5a5a, @long_dest 3249 beq .Llpredec4 3250 fail 3251 .Llpredec4: 3252 mov #0xa5a5a5a5, @long_dest 3253 3254 shlr_l_disp2_4: 3255 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3256 set_ccr_zero 3257 3258 mov #long_dest-8, er0 3259 shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 3260 ;;; .word 0x0106 3261 ;;; .word 0x6908 3262 ;;; .word 0x1138 3263 3264 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3265 test_zero_clear 3266 test_ovf_clear 3267 test_neg_clear 3268 3269 test_h_gr32 long_dest-8 er0 3270 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3271 test_gr_a5a5 2 3272 test_gr_a5a5 3 3273 test_gr_a5a5 4 3274 test_gr_a5a5 5 3275 test_gr_a5a5 6 3276 test_gr_a5a5 7 3277 ; 1010 0101 1010 0101 1010 0101 1010 0101 3278 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3279 cmp.l #0x0a5a5a5a, @long_dest 3280 beq .Lldisp24 3281 fail 3282 .Lldisp24: 3283 mov #0xa5a5a5a5, @long_dest 3284 3285 shlr_l_disp16_4: 3286 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3287 set_ccr_zero 3288 3289 mov #long_dest-44, er0 3290 shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16 3291 ;;; .word 0x0104 3292 ;;; .word 0x6f08 3293 ;;; .word 44 3294 ;;; .word 0x1138 3295 3296 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3297 test_zero_clear 3298 test_ovf_clear 3299 test_neg_clear 3300 3301 test_h_gr32 long_dest-44 er0 3302 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3303 test_gr_a5a5 2 3304 test_gr_a5a5 3 3305 test_gr_a5a5 4 3306 test_gr_a5a5 5 3307 test_gr_a5a5 6 3308 test_gr_a5a5 7 3309 ; 1010 0101 1010 0101 1010 0101 1010 0101 3310 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3311 cmp.l #0x0a5a5a5a, @long_dest 3312 beq .Lldisp164 3313 fail 3314 .Lldisp164: 3315 mov #0xa5a5a5a5, @long_dest 3316 3317 shlr_l_disp32_4: 3318 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3319 set_ccr_zero 3320 3321 mov #long_dest-666, er0 3322 shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32 3323 ;;; .word 0x7884 3324 ;;; .word 0x6b28 3325 ;;; .long 666 3326 ;;; .word 0x1138 3327 3328 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3329 test_zero_clear 3330 test_ovf_clear 3331 test_neg_clear 3332 3333 test_h_gr32 long_dest-666 er0 3334 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3335 test_gr_a5a5 2 3336 test_gr_a5a5 3 3337 test_gr_a5a5 4 3338 test_gr_a5a5 5 3339 test_gr_a5a5 6 3340 test_gr_a5a5 7 3341 ; 1010 0101 1010 0101 1010 0101 1010 0101 3342 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3343 cmp.l #0x0a5a5a5a, @long_dest 3344 beq .Lldisp324 3345 fail 3346 .Lldisp324: 3347 mov #0xa5a5a5a5, @long_dest 3348 3349 shlr_l_abs16_4: 3350 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3351 set_ccr_zero 3352 3353 shlr.l #4, @long_dest:16 ; shift right logical by four, abs16 3354 ;;; .word 0x0104 3355 ;;; .word 0x6b08 3356 ;;; .word long_dest 3357 ;;; .word 0x1138 3358 3359 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3360 test_zero_clear 3361 test_ovf_clear 3362 test_neg_clear 3363 3364 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3365 test_gr_a5a5 1 3366 test_gr_a5a5 2 3367 test_gr_a5a5 3 3368 test_gr_a5a5 4 3369 test_gr_a5a5 5 3370 test_gr_a5a5 6 3371 test_gr_a5a5 7 3372 ; 1010 0101 1010 0101 1010 0101 1010 0101 3373 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3374 cmp.l #0x0a5a5a5a, @long_dest 3375 beq .Llabs164 3376 fail 3377 .Llabs164: 3378 mov #0xa5a5a5a5, @long_dest 3379 3380 shlr_l_abs32_4: 3381 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3382 set_ccr_zero 3383 3384 shlr.l #4, @long_dest:32 ; shift right logical by four, abs32 3385 ;;; .word 0x0104 3386 ;;; .word 0x6b28 3387 ;;; .long long_dest 3388 ;;; .word 0x1138 3389 3390 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 3391 test_zero_clear 3392 test_ovf_clear 3393 test_neg_clear 3394 3395 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3396 test_gr_a5a5 1 3397 test_gr_a5a5 2 3398 test_gr_a5a5 3 3399 test_gr_a5a5 4 3400 test_gr_a5a5 5 3401 test_gr_a5a5 6 3402 test_gr_a5a5 7 3403 ; 1010 0101 1010 0101 1010 0101 1010 0101 3404 ;; -> 0000 1010 0101 1010 0101 1010 0101 1010 3405 cmp.l #0x0a5a5a5a, @long_dest 3406 beq .Llabs324 3407 fail 3408 .Llabs324: 3409 mov #0xa5a5a5a5, @long_dest 3410 3411 shlr_l_reg32_8: 3412 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3413 set_ccr_zero 3414 3415 shlr.l #8, er0 ; shift right logical by eight, register 3416 ;;; .word 0x1178 3417 3418 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3419 test_zero_clear 3420 test_ovf_clear 3421 test_neg_clear 3422 ; 1010 0101 1010 0101 1010 0101 1010 0101 3423 ; -> 0000 0000 1010 0101 1010 0101 1010 0101 3424 test_h_gr32 0x00a5a5a5 er0 3425 3426 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3427 test_gr_a5a5 2 3428 test_gr_a5a5 3 3429 test_gr_a5a5 4 3430 test_gr_a5a5 5 3431 test_gr_a5a5 6 3432 test_gr_a5a5 7 3433 3434 shlr_l_ind_8: 3435 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3436 set_ccr_zero 3437 3438 mov #long_dest, er0 3439 shlr.l #8, @er0 ; shift right logical by eight, indirect 3440 ;;; .word 0x0104 3441 ;;; .word 0x6908 3442 ;;; .word 0x1178 3443 3444 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3445 test_zero_clear 3446 test_ovf_clear 3447 test_neg_clear 3448 3449 test_h_gr32 long_dest er0 3450 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3451 test_gr_a5a5 2 3452 test_gr_a5a5 3 3453 test_gr_a5a5 4 3454 test_gr_a5a5 5 3455 test_gr_a5a5 6 3456 test_gr_a5a5 7 3457 ; 1010 0101 1010 0101 1010 0101 1010 0101 3458 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3459 cmp.l #0x00a5a5a5, @long_dest 3460 beq .Llind8 3461 fail 3462 .Llind8: 3463 mov #0xa5a5a5a5, @long_dest 3464 3465 shlr_l_postinc_8: 3466 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3467 set_ccr_zero 3468 3469 mov #long_dest, er0 3470 shlr.l #8, @er0+ ; shift right logical by eight, postinc 3471 ;;; .word 0x0104 3472 ;;; .word 0x6d08 3473 ;;; .word 0x1178 3474 3475 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3476 test_zero_clear 3477 test_ovf_clear 3478 test_neg_clear 3479 3480 test_h_gr32 long_dest+4 er0 3481 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3482 test_gr_a5a5 2 3483 test_gr_a5a5 3 3484 test_gr_a5a5 4 3485 test_gr_a5a5 5 3486 test_gr_a5a5 6 3487 test_gr_a5a5 7 3488 ; 1010 0101 1010 0101 1010 0101 1010 0101 3489 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3490 cmp.l #0x00a5a5a5, @long_dest 3491 beq .Llpostinc8 3492 fail 3493 .Llpostinc8: 3494 mov #0xa5a5a5a5, @long_dest 3495 3496 shlr_l_postdec_8: 3497 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3498 set_ccr_zero 3499 3500 mov #long_dest, er0 3501 shlr.l #8, @er0- ; shift right logical by eight, postdec 3502 ;;; .word 0x0106 3503 ;;; .word 0x6d08 3504 ;;; .word 0x1178 3505 3506 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3507 test_zero_clear 3508 test_ovf_clear 3509 test_neg_clear 3510 3511 test_h_gr32 long_dest-4 er0 3512 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3513 test_gr_a5a5 2 3514 test_gr_a5a5 3 3515 test_gr_a5a5 4 3516 test_gr_a5a5 5 3517 test_gr_a5a5 6 3518 test_gr_a5a5 7 3519 ; 1010 0101 1010 0101 1010 0101 1010 0101 3520 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3521 cmp.l #0x00a5a5a5, @long_dest 3522 beq .Llpostdec8 3523 fail 3524 .Llpostdec8: 3525 mov #0xa5a5a5a5, @long_dest 3526 3527 shlr_l_preinc_8: 3528 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3529 set_ccr_zero 3530 3531 mov #long_dest-4, er0 3532 shlr.l #8, @+er0 ; shift right logical by eight, preinc 3533 ;;; .word 0x0105 3534 ;;; .word 0x6d08 3535 ;;; .word 0x1178 3536 3537 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3538 test_zero_clear 3539 test_ovf_clear 3540 test_neg_clear 3541 3542 test_h_gr32 long_dest er0 3543 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3544 test_gr_a5a5 2 3545 test_gr_a5a5 3 3546 test_gr_a5a5 4 3547 test_gr_a5a5 5 3548 test_gr_a5a5 6 3549 test_gr_a5a5 7 3550 ; 1010 0101 1010 0101 1010 0101 1010 0101 3551 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3552 cmp.l #0x00a5a5a5, @long_dest 3553 beq .Llpreinc8 3554 fail 3555 .Llpreinc8: 3556 mov #0xa5a5a5a5, @long_dest 3557 3558 shlr_l_predec_8: 3559 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3560 set_ccr_zero 3561 3562 mov #long_dest+4, er0 3563 shlr.l #8, @-er0 ; shift right logical by eight, predec 3564 ;;; .word 0x0107 3565 ;;; .word 0x6d08 3566 ;;; .word 0x1178 3567 3568 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3569 test_zero_clear 3570 test_ovf_clear 3571 test_neg_clear 3572 3573 test_h_gr32 long_dest er0 3574 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3575 test_gr_a5a5 2 3576 test_gr_a5a5 3 3577 test_gr_a5a5 4 3578 test_gr_a5a5 5 3579 test_gr_a5a5 6 3580 test_gr_a5a5 7 3581 ; 1010 0101 1010 0101 1010 0101 1010 0101 3582 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3583 cmp.l #0x00a5a5a5, @long_dest 3584 beq .Llpredec8 3585 fail 3586 .Llpredec8: 3587 mov #0xa5a5a5a5, @long_dest 3588 3589 shlr_l_disp2_8: 3590 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3591 set_ccr_zero 3592 3593 mov #long_dest-8, er0 3594 shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 3595 ;;; .word 0x0106 3596 ;;; .word 0x6908 3597 ;;; .word 0x1178 3598 3599 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3600 test_zero_clear 3601 test_ovf_clear 3602 test_neg_clear 3603 3604 test_h_gr32 long_dest-8 er0 3605 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3606 test_gr_a5a5 2 3607 test_gr_a5a5 3 3608 test_gr_a5a5 4 3609 test_gr_a5a5 5 3610 test_gr_a5a5 6 3611 test_gr_a5a5 7 3612 ; 1010 0101 1010 0101 1010 0101 1010 0101 3613 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3614 cmp.l #0x00a5a5a5, @long_dest 3615 beq .Lldisp28 3616 fail 3617 .Lldisp28: 3618 mov #0xa5a5a5a5, @long_dest 3619 3620 shlr_l_disp16_8: 3621 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3622 set_ccr_zero 3623 3624 mov #long_dest-44, er0 3625 shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16 3626 ;;; .word 0x0104 3627 ;;; .word 0x6f08 3628 ;;; .word 44 3629 ;;; .word 0x1178 3630 3631 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3632 test_zero_clear 3633 test_ovf_clear 3634 test_neg_clear 3635 3636 test_h_gr32 long_dest-44 er0 3637 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3638 test_gr_a5a5 2 3639 test_gr_a5a5 3 3640 test_gr_a5a5 4 3641 test_gr_a5a5 5 3642 test_gr_a5a5 6 3643 test_gr_a5a5 7 3644 ; 1010 0101 1010 0101 1010 0101 1010 0101 3645 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3646 cmp.l #0x00a5a5a5, @long_dest 3647 beq .Lldisp168 3648 fail 3649 .Lldisp168: 3650 mov #0xa5a5a5a5, @long_dest 3651 3652 shlr_l_disp32_8: 3653 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3654 set_ccr_zero 3655 3656 mov #long_dest-666, er0 3657 shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32 3658 ;;; .word 0x7884 3659 ;;; .word 0x6b28 3660 ;;; .long 666 3661 ;;; .word 0x1178 3662 3663 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3664 test_zero_clear 3665 test_ovf_clear 3666 test_neg_clear 3667 3668 test_h_gr32 long_dest-666 er0 3669 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3670 test_gr_a5a5 2 3671 test_gr_a5a5 3 3672 test_gr_a5a5 4 3673 test_gr_a5a5 5 3674 test_gr_a5a5 6 3675 test_gr_a5a5 7 3676 ; 1010 0101 1010 0101 1010 0101 1010 0101 3677 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3678 cmp.l #0x00a5a5a5, @long_dest 3679 beq .Lldisp328 3680 fail 3681 .Lldisp328: 3682 mov #0xa5a5a5a5, @long_dest 3683 3684 shlr_l_abs16_8: 3685 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3686 set_ccr_zero 3687 3688 shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16 3689 ;;; .word 0x0104 3690 ;;; .word 0x6b08 3691 ;;; .word long_dest 3692 ;;; .word 0x1178 3693 3694 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3695 test_zero_clear 3696 test_ovf_clear 3697 test_neg_clear 3698 3699 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3700 test_gr_a5a5 1 3701 test_gr_a5a5 2 3702 test_gr_a5a5 3 3703 test_gr_a5a5 4 3704 test_gr_a5a5 5 3705 test_gr_a5a5 6 3706 test_gr_a5a5 7 3707 ; 1010 0101 1010 0101 1010 0101 1010 0101 3708 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3709 cmp.l #0x00a5a5a5, @long_dest 3710 beq .Llabs168 3711 fail 3712 .Llabs168: 3713 mov #0xa5a5a5a5, @long_dest 3714 3715 shlr_l_abs32_8: 3716 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3717 set_ccr_zero 3718 3719 shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32 3720 ;;; .word 0x0104 3721 ;;; .word 0x6b28 3722 ;;; .long long_dest 3723 ;;; .word 0x1178 3724 3725 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3726 test_zero_clear 3727 test_ovf_clear 3728 test_neg_clear 3729 3730 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 3731 test_gr_a5a5 1 3732 test_gr_a5a5 2 3733 test_gr_a5a5 3 3734 test_gr_a5a5 4 3735 test_gr_a5a5 5 3736 test_gr_a5a5 6 3737 test_gr_a5a5 7 3738 ; 1010 0101 1010 0101 1010 0101 1010 0101 3739 ;; -> 0000 0000 1010 0101 1010 0101 1010 0101 3740 cmp.l #0x00a5a5a5, @long_dest 3741 beq .Llabs328 3742 fail 3743 .Llabs328: 3744 mov #0xa5a5a5a5, @long_dest 3745 3746 shlr_l_reg32_16: 3747 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3748 set_ccr_zero 3749 3750 shlr.l #16, er0 ; shift right logical by sixteen, register 3751 ;;; .word 0x11f8 3752 3753 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3754 test_zero_clear 3755 test_ovf_clear 3756 test_neg_clear 3757 ; 1010 0101 1010 0101 1010 0101 1010 0101 3758 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3759 test_h_gr32 0x0000a5a5 er0 3760 3761 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3762 test_gr_a5a5 2 3763 test_gr_a5a5 3 3764 test_gr_a5a5 4 3765 test_gr_a5a5 5 3766 test_gr_a5a5 6 3767 test_gr_a5a5 7 3768 3769 shlr_l_ind_16: 3770 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3771 set_ccr_zero 3772 3773 mov #long_dest, er0 3774 shlr.l #16, @er0 ; shift right logical by sixteen, indirect 3775 ;;; .word 0x0104 3776 ;;; .word 0x6908 3777 ;;; .word 0x11f8 3778 3779 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3780 test_zero_clear 3781 test_ovf_clear 3782 test_neg_clear 3783 3784 test_h_gr32 long_dest er0 3785 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3786 test_gr_a5a5 2 3787 test_gr_a5a5 3 3788 test_gr_a5a5 4 3789 test_gr_a5a5 5 3790 test_gr_a5a5 6 3791 test_gr_a5a5 7 3792 ; 1010 0101 1010 0101 1010 0101 1010 0101 3793 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3794 cmp.l #0x0000a5a5, @long_dest 3795 beq .Llind16 3796 fail 3797 .Llind16: 3798 mov #0xa5a5a5a5, @long_dest 3799 3800 shlr_l_postinc_16: 3801 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3802 set_ccr_zero 3803 3804 mov #long_dest, er0 3805 shlr.l #16, @er0+ ; shift right logical by sixteen, postinc 3806 ;;; .word 0x0104 3807 ;;; .word 0x6d08 3808 ;;; .word 0x11f8 3809 3810 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3811 test_zero_clear 3812 test_ovf_clear 3813 test_neg_clear 3814 3815 test_h_gr32 long_dest+4 er0 3816 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3817 test_gr_a5a5 2 3818 test_gr_a5a5 3 3819 test_gr_a5a5 4 3820 test_gr_a5a5 5 3821 test_gr_a5a5 6 3822 test_gr_a5a5 7 3823 ; 1010 0101 1010 0101 1010 0101 1010 0101 3824 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3825 cmp.l #0x0000a5a5, @long_dest 3826 beq .Llpostinc16 3827 fail 3828 .Llpostinc16: 3829 mov #0xa5a5a5a5, @long_dest 3830 3831 shlr_l_postdec_16: 3832 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3833 set_ccr_zero 3834 3835 mov #long_dest, er0 3836 shlr.l #16, @er0- ; shift right logical by sixteen, postdec 3837 ;;; .word 0x0106 3838 ;;; .word 0x6d08 3839 ;;; .word 0x11f8 3840 3841 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3842 test_zero_clear 3843 test_ovf_clear 3844 test_neg_clear 3845 3846 test_h_gr32 long_dest-4 er0 3847 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3848 test_gr_a5a5 2 3849 test_gr_a5a5 3 3850 test_gr_a5a5 4 3851 test_gr_a5a5 5 3852 test_gr_a5a5 6 3853 test_gr_a5a5 7 3854 ; 1010 0101 1010 0101 1010 0101 1010 0101 3855 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3856 cmp.l #0x0000a5a5, @long_dest 3857 beq .Llpostdec16 3858 fail 3859 .Llpostdec16: 3860 mov #0xa5a5a5a5, @long_dest 3861 3862 shlr_l_preinc_16: 3863 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3864 set_ccr_zero 3865 3866 mov #long_dest-4, er0 3867 shlr.l #16, @+er0 ; shift right logical by sixteen, preinc 3868 ;;; .word 0x0105 3869 ;;; .word 0x6d08 3870 ;;; .word 0x11f8 3871 3872 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3873 test_zero_clear 3874 test_ovf_clear 3875 test_neg_clear 3876 3877 test_h_gr32 long_dest er0 3878 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3879 test_gr_a5a5 2 3880 test_gr_a5a5 3 3881 test_gr_a5a5 4 3882 test_gr_a5a5 5 3883 test_gr_a5a5 6 3884 test_gr_a5a5 7 3885 ; 1010 0101 1010 0101 1010 0101 1010 0101 3886 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3887 cmp.l #0x0000a5a5, @long_dest 3888 beq .Llpreinc16 3889 fail 3890 .Llpreinc16: 3891 mov #0xa5a5a5a5, @long_dest 3892 3893 shlr_l_predec_16: 3894 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3895 set_ccr_zero 3896 3897 mov #long_dest+4, er0 3898 shlr.l #16, @-er0 ; shift right logical by sixteen, predec 3899 ;;; .word 0x0107 3900 ;;; .word 0x6d08 3901 ;;; .word 0x11f8 3902 3903 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3904 test_zero_clear 3905 test_ovf_clear 3906 test_neg_clear 3907 3908 test_h_gr32 long_dest er0 3909 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3910 test_gr_a5a5 2 3911 test_gr_a5a5 3 3912 test_gr_a5a5 4 3913 test_gr_a5a5 5 3914 test_gr_a5a5 6 3915 test_gr_a5a5 7 3916 ; 1010 0101 1010 0101 1010 0101 1010 0101 3917 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3918 cmp.l #0x0000a5a5, @long_dest 3919 beq .Llpredec16 3920 fail 3921 .Llpredec16: 3922 mov #0xa5a5a5a5, @long_dest 3923 3924 shlr_l_disp2_16: 3925 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3926 set_ccr_zero 3927 3928 mov #long_dest-8, er0 3929 shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 3930 ;;; .word 0x0106 3931 ;;; .word 0x6908 3932 ;;; .word 0x11f8 3933 3934 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3935 test_zero_clear 3936 test_ovf_clear 3937 test_neg_clear 3938 3939 test_h_gr32 long_dest-8 er0 3940 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3941 test_gr_a5a5 2 3942 test_gr_a5a5 3 3943 test_gr_a5a5 4 3944 test_gr_a5a5 5 3945 test_gr_a5a5 6 3946 test_gr_a5a5 7 3947 ; 1010 0101 1010 0101 1010 0101 1010 0101 3948 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3949 cmp.l #0x0000a5a5, @long_dest 3950 beq .Lldisp216 3951 fail 3952 .Lldisp216: 3953 mov #0xa5a5a5a5, @long_dest 3954 3955 shlr_l_disp16_16: 3956 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3957 set_ccr_zero 3958 3959 mov #long_dest-44, er0 3960 shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16 3961 ;;; .word 0x0104 3962 ;;; .word 0x6f08 3963 ;;; .word 44 3964 ;;; .word 0x11f8 3965 3966 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3967 test_zero_clear 3968 test_ovf_clear 3969 test_neg_clear 3970 3971 test_h_gr32 long_dest-44 er0 3972 test_gr_a5a5 1 ; Make sure other general regs not disturbed 3973 test_gr_a5a5 2 3974 test_gr_a5a5 3 3975 test_gr_a5a5 4 3976 test_gr_a5a5 5 3977 test_gr_a5a5 6 3978 test_gr_a5a5 7 3979 ; 1010 0101 1010 0101 1010 0101 1010 0101 3980 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 3981 cmp.l #0x0000a5a5, @long_dest 3982 beq .Lldisp1616 3983 fail 3984 .Lldisp1616: 3985 mov #0xa5a5a5a5, @long_dest 3986 3987 shlr_l_disp32_16: 3988 set_grs_a5a5 ; Fill all general regs with a fixed pattern 3989 set_ccr_zero 3990 3991 mov #long_dest-666, er0 3992 shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32 3993 ;;; .word 0x7884 3994 ;;; .word 0x6b28 3995 ;;; .long 666 3996 ;;; .word 0x11f8 3997 3998 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 3999 test_zero_clear 4000 test_ovf_clear 4001 test_neg_clear 4002 4003 test_h_gr32 long_dest-666 er0 4004 test_gr_a5a5 1 ; Make sure other general regs not disturbed 4005 test_gr_a5a5 2 4006 test_gr_a5a5 3 4007 test_gr_a5a5 4 4008 test_gr_a5a5 5 4009 test_gr_a5a5 6 4010 test_gr_a5a5 7 4011 ; 1010 0101 1010 0101 1010 0101 1010 0101 4012 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4013 cmp.l #0x0000a5a5, @long_dest 4014 beq .Lldisp3216 4015 fail 4016 .Lldisp3216: 4017 mov #0xa5a5a5a5, @long_dest 4018 4019 shlr_l_abs16_16: 4020 set_grs_a5a5 ; Fill all general regs with a fixed pattern 4021 set_ccr_zero 4022 4023 shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16 4024 ;;; .word 0x0104 4025 ;;; .word 0x6b08 4026 ;;; .word long_dest 4027 ;;; .word 0x11f8 4028 4029 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 4030 test_zero_clear 4031 test_ovf_clear 4032 test_neg_clear 4033 4034 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 4035 test_gr_a5a5 1 4036 test_gr_a5a5 2 4037 test_gr_a5a5 3 4038 test_gr_a5a5 4 4039 test_gr_a5a5 5 4040 test_gr_a5a5 6 4041 test_gr_a5a5 7 4042 ; 1010 0101 1010 0101 1010 0101 1010 0101 4043 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4044 cmp.l #0x0000a5a5, @long_dest 4045 beq .Llabs1616 4046 fail 4047 .Llabs1616: 4048 mov #0xa5a5a5a5, @long_dest 4049 4050 shlr_l_abs32_16: 4051 set_grs_a5a5 ; Fill all general regs with a fixed pattern 4052 set_ccr_zero 4053 4054 shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32 4055 ;;; .word 0x0104 4056 ;;; .word 0x6b28 4057 ;;; .long long_dest 4058 ;;; .word 0x11f8 4059 4060 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 4061 test_zero_clear 4062 test_ovf_clear 4063 test_neg_clear 4064 4065 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 4066 test_gr_a5a5 1 4067 test_gr_a5a5 2 4068 test_gr_a5a5 3 4069 test_gr_a5a5 4 4070 test_gr_a5a5 5 4071 test_gr_a5a5 6 4072 test_gr_a5a5 7 4073 ; 1010 0101 1010 0101 1010 0101 1010 0101 4074 ;; -> 0000 0000 0000 0000 1010 0101 1010 0101 4075 cmp.l #0x0000a5a5, @long_dest 4076 beq .Llabs3216 4077 fail 4078 .Llabs3216: 4079 mov #0xa5a5a5a5, @long_dest 4080 .endif 4081 .endif 4082 pass 4083 4084 exit 0 4085 4086
Indexes created Fri May 08 00:25:09 UTC 2026