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trap.cgs revision 1.1 
      1 # m32r testcase for trap #$uimm4
      2 # mach(): m32r m32rx
      3 # sim: --environment virtual
      4 
      5 	.include "testutils.inc"
      6 
      7 	start
      8 
      9 	.global trap
     10 trap:
     11 
     12 ; Test 1: bbpsw = 0, bpsw = 1, psw = 0
     13 
     14 	; bbsm = 0, bie = 0, bbcond = 0
     15 	mvi_h_gr r4, 0
     16 	mvtc r4, cr8
     17 
     18 	; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
     19 	mvi_h_gr r4, 0xc100
     20 	mvtc r4, cr0
     21 
     22 	; bbpc = 0
     23 	mvaddr_h_gr r4, 0
     24 	mvtc r4, bbpc
     25 
     26 	; bpc = 42
     27 	mvaddr_h_gr r4, 42
     28 	mvtc r4, bpc
     29 
     30 	; Copy trap2_handler to trap area of memory.
     31 	ld24 r0,#0x48 ; address of trap 2 handler
     32 	ld24 r1,#trap2_handler
     33 	ld r2,@r1
     34 	st r2,@r0
     35 	; Set up return address.
     36 	ld24 r5,#trap2_ret1
     37 
     38 trap_insn1:
     39 	trap #2
     40 	fail
     41 
     42 trap2_ret1:
     43 	; test bbsm = 1, bbie = 1, bbcond = 1
     44 	mvfc r4, cr8
     45 	test_h_gr r4, 0xc1
     46 
     47 	; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0
     48 	mvfc r4, cr0
     49 	test_h_gr r4, 0
     50 
     51 	; test bbpc = 42
     52 	mvfc r4, bbpc
     53 	test_h_gr r4, 42
     54 
     55 	; test bpc = proper return address
     56 	mvfc r4, bpc
     57 	test_h_gr r4, trap_insn1 + 4
     58 
     59 ; Test 2: bbpsw = 1, bpsw = 0, psw = 1
     60 
     61 	; bbsm = 1, bie = 1, bbcond = 1
     62 	mvi_h_gr r4, 0xc1
     63 	mvtc r4, cr8
     64 
     65 	; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
     66 	mvi_h_gr r4, 0xc1
     67 	mvtc r4, cr0
     68 
     69 	; bbpc = 42
     70 	mvaddr_h_gr r4, 42
     71 	mvtc r4, bbpc
     72 
     73 	; bpc = 0
     74 	mvaddr_h_gr r4, 0
     75 	mvtc r4, bpc
     76 
     77 	; Set up return address.
     78 	ld24 r5,#trap2_ret2
     79 
     80 trap_insn2:
     81 	trap #2
     82 	fail
     83 
     84 trap2_ret2:
     85 	; test bbsm = 0, bbie = 0, bbcond = 0
     86 	mvfc r4, cr8
     87 	test_h_gr r4, 0
     88 
     89 	; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0
     90 	mvfc r4, cr0
     91 	test_h_gr r4, 0xc180
     92 
     93 	; test bbpc = 0
     94 	mvfc r4, bbpc
     95 	test_h_gr r4, 0
     96 
     97 	; test bpc = proper return address
     98 	mvfc r4, bpc
     99 	test_h_gr r4, trap_insn2 + 4
    100 
    101 	pass
    102 
    103 	.data
    104 
    105 ; Don't use rte as it will undo the effects of trap we're testing.
    106 
    107 	.p2align 2
    108 trap2_handler:
    109 	jmp r5
    110 	nop
    111