linux-aarch64-low.cc revision 1.1.1.3
1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for 2 GDB. 3 4 Copyright (C) 2009-2024 Free Software Foundation, Inc. 5 Contributed by ARM Ltd. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "linux-low.h" 23 #include "nat/aarch64-linux.h" 24 #include "nat/aarch64-linux-hw-point.h" 25 #include "arch/aarch64-insn.h" 26 #include "linux-aarch32-low.h" 27 #include "elf/common.h" 28 #include "ax.h" 29 #include "tracepoint.h" 30 #include "debug.h" 31 32 #include <signal.h> 33 #include <sys/user.h> 34 #include "nat/gdb_ptrace.h" 35 #include <asm/ptrace.h> 36 #include <inttypes.h> 37 #include <endian.h> 38 #include <sys/uio.h> 39 40 #include "gdb_proc_service.h" 41 #include "arch/aarch64.h" 42 #include "arch/aarch64-mte-linux.h" 43 #include "arch/aarch64-scalable-linux.h" 44 #include "linux-aarch32-tdesc.h" 45 #include "linux-aarch64-tdesc.h" 46 #include "nat/aarch64-mte-linux-ptrace.h" 47 #include "nat/aarch64-scalable-linux-ptrace.h" 48 #include "tdesc.h" 49 50 #ifdef HAVE_SYS_REG_H 51 #include <sys/reg.h> 52 #endif 53 54 #ifdef HAVE_GETAUXVAL 55 #include <sys/auxv.h> 56 #endif 57 58 /* Linux target op definitions for the AArch64 architecture. */ 59 60 class aarch64_target : public linux_process_target 61 { 62 public: 63 64 const regs_info *get_regs_info () override; 65 66 int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; 67 68 int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; 69 70 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; 71 72 bool supports_z_point_type (char z_type) override; 73 74 bool supports_tracepoints () override; 75 76 bool supports_fast_tracepoints () override; 77 78 int install_fast_tracepoint_jump_pad 79 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 80 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 81 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 82 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 83 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 84 char *err) override; 85 86 int get_min_fast_tracepoint_insn_len () override; 87 88 struct emit_ops *emit_ops () override; 89 90 bool supports_memory_tagging () override; 91 92 bool fetch_memtags (CORE_ADDR address, size_t len, 93 gdb::byte_vector &tags, int type) override; 94 95 bool store_memtags (CORE_ADDR address, size_t len, 96 const gdb::byte_vector &tags, int type) override; 97 98 protected: 99 100 void low_arch_setup () override; 101 102 bool low_cannot_fetch_register (int regno) override; 103 104 bool low_cannot_store_register (int regno) override; 105 106 bool low_supports_breakpoints () override; 107 108 CORE_ADDR low_get_pc (regcache *regcache) override; 109 110 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; 111 112 bool low_breakpoint_at (CORE_ADDR pc) override; 113 114 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 115 int size, raw_breakpoint *bp) override; 116 117 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 118 int size, raw_breakpoint *bp) override; 119 120 bool low_stopped_by_watchpoint () override; 121 122 CORE_ADDR low_stopped_data_address () override; 123 124 bool low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, 125 int direction) override; 126 127 arch_process_info *low_new_process () override; 128 129 void low_delete_process (arch_process_info *info) override; 130 131 void low_new_thread (lwp_info *) override; 132 133 void low_delete_thread (arch_lwp_info *) override; 134 135 void low_new_fork (process_info *parent, process_info *child) override; 136 137 void low_prepare_to_resume (lwp_info *lwp) override; 138 139 int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override; 140 141 bool low_supports_range_stepping () override; 142 143 bool low_supports_catch_syscall () override; 144 145 void low_get_syscall_trapinfo (regcache *regcache, int *sysno) override; 146 }; 147 148 /* The singleton target ops object. */ 149 150 static aarch64_target the_aarch64_target; 151 152 bool 153 aarch64_target::low_cannot_fetch_register (int regno) 154 { 155 gdb_assert_not_reached ("linux target op low_cannot_fetch_register " 156 "is not implemented by the target"); 157 } 158 159 bool 160 aarch64_target::low_cannot_store_register (int regno) 161 { 162 gdb_assert_not_reached ("linux target op low_cannot_store_register " 163 "is not implemented by the target"); 164 } 165 166 void 167 aarch64_target::low_prepare_to_resume (lwp_info *lwp) 168 { 169 aarch64_linux_prepare_to_resume (lwp); 170 } 171 172 /* Per-process arch-specific data we want to keep. */ 173 174 struct arch_process_info 175 { 176 /* Hardware breakpoint/watchpoint data. 177 The reason for them to be per-process rather than per-thread is 178 due to the lack of information in the gdbserver environment; 179 gdbserver is not told that whether a requested hardware 180 breakpoint/watchpoint is thread specific or not, so it has to set 181 each hw bp/wp for every thread in the current process. The 182 higher level bp/wp management in gdb will resume a thread if a hw 183 bp/wp trap is not expected for it. Since the hw bp/wp setting is 184 same for each thread, it is reasonable for the data to live here. 185 */ 186 struct aarch64_debug_reg_state debug_reg_state; 187 }; 188 189 /* Return true if the size of register 0 is 8 byte. */ 190 191 static int 192 is_64bit_tdesc (void) 193 { 194 /* We may not have a current thread at this point, so go straight to 195 the process's target description. */ 196 return register_size (current_process ()->tdesc, 0) == 8; 197 } 198 199 static void 200 aarch64_fill_gregset (struct regcache *regcache, void *buf) 201 { 202 struct user_pt_regs *regset = (struct user_pt_regs *) buf; 203 int i; 204 205 for (i = 0; i < AARCH64_X_REGS_NUM; i++) 206 collect_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]); 207 collect_register (regcache, AARCH64_SP_REGNUM, ®set->sp); 208 collect_register (regcache, AARCH64_PC_REGNUM, ®set->pc); 209 collect_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate); 210 } 211 212 static void 213 aarch64_store_gregset (struct regcache *regcache, const void *buf) 214 { 215 const struct user_pt_regs *regset = (const struct user_pt_regs *) buf; 216 int i; 217 218 for (i = 0; i < AARCH64_X_REGS_NUM; i++) 219 supply_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]); 220 supply_register (regcache, AARCH64_SP_REGNUM, ®set->sp); 221 supply_register (regcache, AARCH64_PC_REGNUM, ®set->pc); 222 supply_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate); 223 } 224 225 static void 226 aarch64_fill_fpregset (struct regcache *regcache, void *buf) 227 { 228 struct user_fpsimd_state *regset = (struct user_fpsimd_state *) buf; 229 int i; 230 231 for (i = 0; i < AARCH64_V_REGS_NUM; i++) 232 collect_register (regcache, AARCH64_V0_REGNUM + i, ®set->vregs[i]); 233 collect_register (regcache, AARCH64_FPSR_REGNUM, ®set->fpsr); 234 collect_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr); 235 } 236 237 static void 238 aarch64_store_fpregset (struct regcache *regcache, const void *buf) 239 { 240 const struct user_fpsimd_state *regset 241 = (const struct user_fpsimd_state *) buf; 242 int i; 243 244 for (i = 0; i < AARCH64_V_REGS_NUM; i++) 245 supply_register (regcache, AARCH64_V0_REGNUM + i, ®set->vregs[i]); 246 supply_register (regcache, AARCH64_FPSR_REGNUM, ®set->fpsr); 247 supply_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr); 248 } 249 250 /* Store the pauth registers to regcache. */ 251 252 static void 253 aarch64_store_pauthregset (struct regcache *regcache, const void *buf) 254 { 255 uint64_t *pauth_regset = (uint64_t *) buf; 256 int pauth_base = find_regno (regcache->tdesc, "pauth_dmask"); 257 258 if (pauth_base == 0) 259 return; 260 261 supply_register (regcache, AARCH64_PAUTH_DMASK_REGNUM (pauth_base), 262 &pauth_regset[0]); 263 supply_register (regcache, AARCH64_PAUTH_CMASK_REGNUM (pauth_base), 264 &pauth_regset[1]); 265 } 266 267 /* Fill BUF with the MTE registers from the regcache. */ 268 269 static void 270 aarch64_fill_mteregset (struct regcache *regcache, void *buf) 271 { 272 uint64_t *mte_regset = (uint64_t *) buf; 273 int mte_base = find_regno (regcache->tdesc, "tag_ctl"); 274 275 collect_register (regcache, mte_base, mte_regset); 276 } 277 278 /* Store the MTE registers to regcache. */ 279 280 static void 281 aarch64_store_mteregset (struct regcache *regcache, const void *buf) 282 { 283 uint64_t *mte_regset = (uint64_t *) buf; 284 int mte_base = find_regno (regcache->tdesc, "tag_ctl"); 285 286 /* Tag Control register */ 287 supply_register (regcache, mte_base, mte_regset); 288 } 289 290 /* Fill BUF with TLS register from the regcache. */ 291 292 static void 293 aarch64_fill_tlsregset (struct regcache *regcache, void *buf) 294 { 295 gdb_byte *tls_buf = (gdb_byte *) buf; 296 int tls_regnum = find_regno (regcache->tdesc, "tpidr"); 297 298 collect_register (regcache, tls_regnum, tls_buf); 299 300 /* Read TPIDR2, if it exists. */ 301 std::optional<int> regnum = find_regno_no_throw (regcache->tdesc, "tpidr2"); 302 303 if (regnum.has_value ()) 304 collect_register (regcache, *regnum, tls_buf + sizeof (uint64_t)); 305 } 306 307 /* Store TLS register to regcache. */ 308 309 static void 310 aarch64_store_tlsregset (struct regcache *regcache, const void *buf) 311 { 312 gdb_byte *tls_buf = (gdb_byte *) buf; 313 int tls_regnum = find_regno (regcache->tdesc, "tpidr"); 314 315 supply_register (regcache, tls_regnum, tls_buf); 316 317 /* Write TPIDR2, if it exists. */ 318 std::optional<int> regnum = find_regno_no_throw (regcache->tdesc, "tpidr2"); 319 320 if (regnum.has_value ()) 321 supply_register (regcache, *regnum, tls_buf + sizeof (uint64_t)); 322 } 323 324 bool 325 aarch64_target::low_supports_breakpoints () 326 { 327 return true; 328 } 329 330 /* Implementation of linux target ops method "low_get_pc". */ 331 332 CORE_ADDR 333 aarch64_target::low_get_pc (regcache *regcache) 334 { 335 if (register_size (regcache->tdesc, 0) == 8) 336 return linux_get_pc_64bit (regcache); 337 else 338 return linux_get_pc_32bit (regcache); 339 } 340 341 /* Implementation of linux target ops method "low_set_pc". */ 342 343 void 344 aarch64_target::low_set_pc (regcache *regcache, CORE_ADDR pc) 345 { 346 if (register_size (regcache->tdesc, 0) == 8) 347 linux_set_pc_64bit (regcache, pc); 348 else 349 linux_set_pc_32bit (regcache, pc); 350 } 351 352 #define aarch64_breakpoint_len 4 353 354 /* AArch64 BRK software debug mode instruction. 355 This instruction needs to match gdb/aarch64-tdep.c 356 (aarch64_default_breakpoint). */ 357 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; 358 359 /* Implementation of linux target ops method "low_breakpoint_at". */ 360 361 bool 362 aarch64_target::low_breakpoint_at (CORE_ADDR where) 363 { 364 if (is_64bit_tdesc ()) 365 { 366 gdb_byte insn[aarch64_breakpoint_len]; 367 368 read_memory (where, (unsigned char *) &insn, aarch64_breakpoint_len); 369 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0) 370 return true; 371 372 return false; 373 } 374 else 375 return arm_breakpoint_at (where); 376 } 377 378 static void 379 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) 380 { 381 int i; 382 383 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) 384 { 385 state->dr_addr_bp[i] = 0; 386 state->dr_ctrl_bp[i] = 0; 387 state->dr_ref_count_bp[i] = 0; 388 } 389 390 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) 391 { 392 state->dr_addr_wp[i] = 0; 393 state->dr_ctrl_wp[i] = 0; 394 state->dr_ref_count_wp[i] = 0; 395 } 396 } 397 398 /* Return the pointer to the debug register state structure in the 399 current process' arch-specific data area. */ 400 401 struct aarch64_debug_reg_state * 402 aarch64_get_debug_reg_state (pid_t pid) 403 { 404 struct process_info *proc = find_process_pid (pid); 405 406 return &proc->priv->arch_private->debug_reg_state; 407 } 408 409 /* Implementation of target ops method "supports_z_point_type". */ 410 411 bool 412 aarch64_target::supports_z_point_type (char z_type) 413 { 414 switch (z_type) 415 { 416 case Z_PACKET_SW_BP: 417 case Z_PACKET_HW_BP: 418 case Z_PACKET_WRITE_WP: 419 case Z_PACKET_READ_WP: 420 case Z_PACKET_ACCESS_WP: 421 return true; 422 default: 423 return false; 424 } 425 } 426 427 /* Implementation of linux target ops method "low_insert_point". 428 429 It actually only records the info of the to-be-inserted bp/wp; 430 the actual insertion will happen when threads are resumed. */ 431 432 int 433 aarch64_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 434 int len, raw_breakpoint *bp) 435 { 436 int ret; 437 enum target_hw_bp_type targ_type; 438 struct aarch64_debug_reg_state *state 439 = aarch64_get_debug_reg_state (pid_of (current_thread)); 440 441 if (show_debug_regs) 442 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n", 443 (unsigned long) addr, len); 444 445 /* Determine the type from the raw breakpoint type. */ 446 targ_type = raw_bkpt_type_to_target_hw_bp_type (type); 447 448 if (targ_type != hw_execute) 449 { 450 if (aarch64_region_ok_for_watchpoint (addr, len)) 451 ret = aarch64_handle_watchpoint (targ_type, addr, len, 452 1 /* is_insert */, 453 current_lwp_ptid (), state); 454 else 455 ret = -1; 456 } 457 else 458 { 459 if (len == 3) 460 { 461 /* LEN is 3 means the breakpoint is set on a 32-bit thumb 462 instruction. Set it to 2 to correctly encode length bit 463 mask in hardware/watchpoint control register. */ 464 len = 2; 465 } 466 ret = aarch64_handle_breakpoint (targ_type, addr, len, 467 1 /* is_insert */, current_lwp_ptid (), 468 state); 469 } 470 471 if (show_debug_regs) 472 aarch64_show_debug_reg_state (state, "insert_point", addr, len, 473 targ_type); 474 475 return ret; 476 } 477 478 /* Implementation of linux target ops method "low_remove_point". 479 480 It actually only records the info of the to-be-removed bp/wp, 481 the actual removal will be done when threads are resumed. */ 482 483 int 484 aarch64_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 485 int len, raw_breakpoint *bp) 486 { 487 int ret; 488 enum target_hw_bp_type targ_type; 489 struct aarch64_debug_reg_state *state 490 = aarch64_get_debug_reg_state (pid_of (current_thread)); 491 492 if (show_debug_regs) 493 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n", 494 (unsigned long) addr, len); 495 496 /* Determine the type from the raw breakpoint type. */ 497 targ_type = raw_bkpt_type_to_target_hw_bp_type (type); 498 499 /* Set up state pointers. */ 500 if (targ_type != hw_execute) 501 ret = 502 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */, 503 current_lwp_ptid (), state); 504 else 505 { 506 if (len == 3) 507 { 508 /* LEN is 3 means the breakpoint is set on a 32-bit thumb 509 instruction. Set it to 2 to correctly encode length bit 510 mask in hardware/watchpoint control register. */ 511 len = 2; 512 } 513 ret = aarch64_handle_breakpoint (targ_type, addr, len, 514 0 /* is_insert */, current_lwp_ptid (), 515 state); 516 } 517 518 if (show_debug_regs) 519 aarch64_show_debug_reg_state (state, "remove_point", addr, len, 520 targ_type); 521 522 return ret; 523 } 524 525 static CORE_ADDR 526 aarch64_remove_non_address_bits (CORE_ADDR pointer) 527 { 528 /* By default, we assume TBI and discard the top 8 bits plus the 529 VA range select bit (55). */ 530 CORE_ADDR mask = AARCH64_TOP_BITS_MASK; 531 532 /* Check if PAC is available for this target. */ 533 if (tdesc_contains_feature (current_process ()->tdesc, 534 "org.gnu.gdb.aarch64.pauth")) 535 { 536 /* Fetch the PAC masks. These masks are per-process, so we can just 537 fetch data from whatever thread we have at the moment. 538 539 Also, we have both a code mask and a data mask. For now they are the 540 same, but this may change in the future. */ 541 542 struct regcache *regs = get_thread_regcache (current_thread, 1); 543 CORE_ADDR dmask = regcache_raw_get_unsigned_by_name (regs, "pauth_dmask"); 544 CORE_ADDR cmask = regcache_raw_get_unsigned_by_name (regs, "pauth_cmask"); 545 mask |= aarch64_mask_from_pac_registers (cmask, dmask); 546 } 547 548 return aarch64_remove_top_bits (pointer, mask); 549 } 550 551 /* Implementation of linux target ops method "low_stopped_data_address". */ 552 553 CORE_ADDR 554 aarch64_target::low_stopped_data_address () 555 { 556 siginfo_t siginfo; 557 int pid; 558 struct aarch64_debug_reg_state *state; 559 560 pid = lwpid_of (current_thread); 561 562 /* Get the siginfo. */ 563 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) 564 return (CORE_ADDR) 0; 565 566 /* Need to be a hardware breakpoint/watchpoint trap. */ 567 if (siginfo.si_signo != SIGTRAP 568 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) 569 return (CORE_ADDR) 0; 570 571 /* Make sure to ignore the top byte, otherwise we may not recognize a 572 hardware watchpoint hit. The stopped data addresses coming from the 573 kernel can potentially be tagged addresses. */ 574 const CORE_ADDR addr_trap 575 = aarch64_remove_non_address_bits ((CORE_ADDR) siginfo.si_addr); 576 577 /* Check if the address matches any watched address. */ 578 state = aarch64_get_debug_reg_state (pid_of (current_thread)); 579 CORE_ADDR result; 580 if (aarch64_stopped_data_address (state, addr_trap, &result)) 581 return result; 582 583 return (CORE_ADDR) 0; 584 } 585 586 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */ 587 588 bool 589 aarch64_target::low_stopped_by_watchpoint () 590 { 591 return (low_stopped_data_address () != 0); 592 } 593 594 /* Fetch the thread-local storage pointer for libthread_db. */ 595 596 ps_err_e 597 ps_get_thread_area (struct ps_prochandle *ph, 598 lwpid_t lwpid, int idx, void **base) 599 { 600 return aarch64_ps_get_thread_area (ph, lwpid, idx, base, 601 is_64bit_tdesc ()); 602 } 603 604 /* Implementation of linux target ops method "low_siginfo_fixup". */ 605 606 bool 607 aarch64_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, 608 int direction) 609 { 610 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ 611 if (!is_64bit_tdesc ()) 612 { 613 if (direction == 0) 614 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, 615 native); 616 else 617 aarch64_siginfo_from_compat_siginfo (native, 618 (struct compat_siginfo *) inf); 619 620 return true; 621 } 622 623 return false; 624 } 625 626 /* Implementation of linux target ops method "low_new_process". */ 627 628 arch_process_info * 629 aarch64_target::low_new_process () 630 { 631 struct arch_process_info *info = XCNEW (struct arch_process_info); 632 633 aarch64_init_debug_reg_state (&info->debug_reg_state); 634 635 return info; 636 } 637 638 /* Implementation of linux target ops method "low_delete_process". */ 639 640 void 641 aarch64_target::low_delete_process (arch_process_info *info) 642 { 643 xfree (info); 644 } 645 646 void 647 aarch64_target::low_new_thread (lwp_info *lwp) 648 { 649 aarch64_linux_new_thread (lwp); 650 } 651 652 void 653 aarch64_target::low_delete_thread (arch_lwp_info *arch_lwp) 654 { 655 aarch64_linux_delete_thread (arch_lwp); 656 } 657 658 /* Implementation of linux target ops method "low_new_fork". */ 659 660 void 661 aarch64_target::low_new_fork (process_info *parent, 662 process_info *child) 663 { 664 /* These are allocated by linux_add_process. */ 665 gdb_assert (parent->priv != NULL 666 && parent->priv->arch_private != NULL); 667 gdb_assert (child->priv != NULL 668 && child->priv->arch_private != NULL); 669 670 /* Linux kernel before 2.6.33 commit 671 72f674d203cd230426437cdcf7dd6f681dad8b0d 672 will inherit hardware debug registers from parent 673 on fork/vfork/clone. Newer Linux kernels create such tasks with 674 zeroed debug registers. 675 676 GDB core assumes the child inherits the watchpoints/hw 677 breakpoints of the parent, and will remove them all from the 678 forked off process. Copy the debug registers mirrors into the 679 new process so that all breakpoints and watchpoints can be 680 removed together. The debug registers mirror will become zeroed 681 in the end before detaching the forked off process, thus making 682 this compatible with older Linux kernels too. */ 683 684 *child->priv->arch_private = *parent->priv->arch_private; 685 } 686 687 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */ 688 689 static void 690 aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, 691 ATTRIBUTE_UNUSED const void *buf) 692 { 693 /* BUF is unused here since we collect the data straight from a ptrace 694 request in aarch64_sve_regs_copy_to_reg_buf, therefore bypassing 695 gdbserver's own call to ptrace. */ 696 697 int tid = lwpid_of (current_thread); 698 699 /* Update the register cache. aarch64_sve_regs_copy_to_reg_buf handles 700 fetching the NT_ARM_SVE state from thread TID. */ 701 aarch64_sve_regs_copy_to_reg_buf (tid, regcache); 702 } 703 704 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */ 705 706 static void 707 aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf) 708 { 709 int tid = lwpid_of (current_thread); 710 711 /* Update the thread SVE state. aarch64_sve_regs_copy_from_reg_buf 712 handles writing the SVE/FPSIMD state back to thread TID. */ 713 aarch64_sve_regs_copy_from_reg_buf (tid, regcache); 714 715 /* We need to return the expected data in BUF, so copy whatever the kernel 716 already has to BUF. */ 717 gdb::byte_vector sve_state = aarch64_fetch_sve_regset (tid); 718 memcpy (buf, sve_state.data (), sve_state.size ()); 719 } 720 721 /* Wrapper for aarch64_za_regs_copy_to_reg_buf, to help copying NT_ARM_ZA 722 state from the thread (BUF) to the register cache. */ 723 724 static void 725 aarch64_za_regs_copy_to_regcache (struct regcache *regcache, 726 ATTRIBUTE_UNUSED const void *buf) 727 { 728 /* BUF is unused here since we collect the data straight from a ptrace 729 request, therefore bypassing gdbserver's own call to ptrace. */ 730 int tid = lwpid_of (current_thread); 731 732 int za_regnum = find_regno (regcache->tdesc, "za"); 733 int svg_regnum = find_regno (regcache->tdesc, "svg"); 734 int svcr_regnum = find_regno (regcache->tdesc, "svcr"); 735 736 /* Update the register cache. aarch64_za_regs_copy_to_reg_buf handles 737 fetching the NT_ARM_ZA state from thread TID. */ 738 aarch64_za_regs_copy_to_reg_buf (tid, regcache, za_regnum, svg_regnum, 739 svcr_regnum); 740 } 741 742 /* Wrapper for aarch64_za_regs_copy_from_reg_buf, to help copying NT_ARM_ZA 743 state from the register cache to the thread (BUF). */ 744 745 static void 746 aarch64_za_regs_copy_from_regcache (struct regcache *regcache, void *buf) 747 { 748 int tid = lwpid_of (current_thread); 749 750 int za_regnum = find_regno (regcache->tdesc, "za"); 751 int svg_regnum = find_regno (regcache->tdesc, "svg"); 752 int svcr_regnum = find_regno (regcache->tdesc, "svcr"); 753 754 /* Update the thread NT_ARM_ZA state. aarch64_za_regs_copy_from_reg_buf 755 handles writing the ZA state back to thread TID. */ 756 aarch64_za_regs_copy_from_reg_buf (tid, regcache, za_regnum, svg_regnum, 757 svcr_regnum); 758 759 /* We need to return the expected data in BUF, so copy whatever the kernel 760 already has to BUF. */ 761 762 /* Obtain a dump of ZA from ptrace. */ 763 gdb::byte_vector za_state = aarch64_fetch_za_regset (tid); 764 memcpy (buf, za_state.data (), za_state.size ()); 765 } 766 767 /* Wrapper for aarch64_zt_regs_copy_to_reg_buf, to help copying NT_ARM_ZT 768 state from the thread (BUF) to the register cache. */ 769 770 static void 771 aarch64_zt_regs_copy_to_regcache (struct regcache *regcache, 772 ATTRIBUTE_UNUSED const void *buf) 773 { 774 /* BUF is unused here since we collect the data straight from a ptrace 775 request, therefore bypassing gdbserver's own call to ptrace. */ 776 int tid = lwpid_of (current_thread); 777 778 int zt_regnum = find_regno (regcache->tdesc, "zt0"); 779 780 /* Update the register cache. aarch64_zt_regs_copy_to_reg_buf handles 781 fetching the NT_ARM_ZT state from thread TID. */ 782 aarch64_zt_regs_copy_to_reg_buf (tid, regcache, zt_regnum); 783 } 784 785 /* Wrapper for aarch64_zt_regs_copy_from_reg_buf, to help copying NT_ARM_ZT 786 state from the register cache to the thread (BUF). */ 787 788 static void 789 aarch64_zt_regs_copy_from_regcache (struct regcache *regcache, void *buf) 790 { 791 int tid = lwpid_of (current_thread); 792 793 int zt_regnum = find_regno (regcache->tdesc, "zt0"); 794 795 /* Update the thread NT_ARM_ZT state. aarch64_zt_regs_copy_from_reg_buf 796 handles writing the ZT state back to thread TID. */ 797 aarch64_zt_regs_copy_from_reg_buf (tid, regcache, zt_regnum); 798 799 /* We need to return the expected data in BUF, so copy whatever the kernel 800 already has to BUF. */ 801 802 /* Obtain a dump of NT_ARM_ZT from ptrace. */ 803 gdb::byte_vector zt_state = aarch64_fetch_zt_regset (tid); 804 memcpy (buf, zt_state.data (), zt_state.size ()); 805 } 806 807 /* Array containing all the possible register sets for AArch64/Linux. During 808 architecture setup, these will be checked against the HWCAP/HWCAP2 bits for 809 validity and enabled/disabled accordingly. 810 811 Their sizes are set to 0 here, but they will be adjusted later depending 812 on whether each register set is available or not. */ 813 static struct regset_info aarch64_regsets[] = 814 { 815 /* GPR registers. */ 816 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 817 0, GENERAL_REGS, 818 aarch64_fill_gregset, aarch64_store_gregset }, 819 /* Floating Point (FPU) registers. */ 820 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, 821 0, FP_REGS, 822 aarch64_fill_fpregset, aarch64_store_fpregset 823 }, 824 /* Scalable Vector Extension (SVE) registers. */ 825 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, 826 0, EXTENDED_REGS, 827 aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache 828 }, 829 /* Scalable Matrix Extension (SME) ZA register. */ 830 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZA, 831 0, EXTENDED_REGS, 832 aarch64_za_regs_copy_from_regcache, aarch64_za_regs_copy_to_regcache 833 }, 834 /* Scalable Matrix Extension 2 (SME2) ZT registers. */ 835 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZT, 836 0, EXTENDED_REGS, 837 aarch64_zt_regs_copy_from_regcache, aarch64_zt_regs_copy_to_regcache 838 }, 839 /* PAC registers. */ 840 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, 841 0, OPTIONAL_REGS, 842 nullptr, aarch64_store_pauthregset }, 843 /* Tagged address control / MTE registers. */ 844 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, 845 0, OPTIONAL_REGS, 846 aarch64_fill_mteregset, aarch64_store_mteregset }, 847 /* TLS register. */ 848 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TLS, 849 0, OPTIONAL_REGS, 850 aarch64_fill_tlsregset, aarch64_store_tlsregset }, 851 NULL_REGSET 852 }; 853 854 static struct regsets_info aarch64_regsets_info = 855 { 856 aarch64_regsets, /* regsets */ 857 0, /* num_regsets */ 858 nullptr, /* disabled_regsets */ 859 }; 860 861 static struct regs_info regs_info_aarch64 = 862 { 863 nullptr, /* regset_bitmap */ 864 nullptr, /* usrregs */ 865 &aarch64_regsets_info, 866 }; 867 868 /* Given FEATURES, adjust the available register sets by setting their 869 sizes. A size of 0 means the register set is disabled and won't be 870 used. */ 871 872 static void 873 aarch64_adjust_register_sets (const struct aarch64_features &features) 874 { 875 struct regset_info *regset; 876 877 for (regset = aarch64_regsets; regset->size >= 0; regset++) 878 { 879 switch (regset->nt_type) 880 { 881 case NT_PRSTATUS: 882 /* General purpose registers are always present. */ 883 regset->size = sizeof (struct user_pt_regs); 884 break; 885 case NT_FPREGSET: 886 /* This is unavailable when SVE is present. */ 887 if (features.vq == 0) 888 regset->size = sizeof (struct user_fpsimd_state); 889 break; 890 case NT_ARM_SVE: 891 if (features.vq > 0) 892 regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE); 893 break; 894 case NT_ARM_PAC_MASK: 895 if (features.pauth) 896 regset->size = AARCH64_PAUTH_REGS_SIZE; 897 break; 898 case NT_ARM_TAGGED_ADDR_CTRL: 899 if (features.mte) 900 regset->size = AARCH64_LINUX_SIZEOF_MTE; 901 break; 902 case NT_ARM_TLS: 903 if (features.tls > 0) 904 regset->size = AARCH64_TLS_REGISTER_SIZE * features.tls; 905 break; 906 case NT_ARM_ZA: 907 if (features.svq > 0) 908 regset->size = ZA_PT_SIZE (features.svq); 909 break; 910 case NT_ARM_ZT: 911 if (features.sme2) 912 regset->size = AARCH64_SME2_ZT0_SIZE; 913 break; 914 default: 915 gdb_assert_not_reached ("Unknown register set found."); 916 } 917 } 918 } 919 920 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ 921 #define AARCH64_HWCAP_PACA (1 << 30) 922 923 /* Implementation of linux target ops method "low_arch_setup". */ 924 925 void 926 aarch64_target::low_arch_setup () 927 { 928 unsigned int machine; 929 int is_elf64; 930 int tid; 931 932 tid = lwpid_of (current_thread); 933 934 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); 935 936 if (is_elf64) 937 { 938 struct aarch64_features features; 939 int pid = current_thread->id.pid (); 940 941 features.vq = aarch64_sve_get_vq (tid); 942 /* A-profile PAC is 64-bit only. */ 943 features.pauth = linux_get_hwcap (pid, 8) & AARCH64_HWCAP_PACA; 944 /* A-profile MTE is 64-bit only. */ 945 features.mte = linux_get_hwcap2 (pid, 8) & HWCAP2_MTE; 946 features.tls = aarch64_tls_register_count (tid); 947 948 /* Scalable Matrix Extension feature and size check. */ 949 if (linux_get_hwcap2 (pid, 8) & HWCAP2_SME) 950 features.svq = aarch64_za_get_svq (tid); 951 952 /* Scalable Matrix Extension 2 feature check. */ 953 CORE_ADDR hwcap2 = linux_get_hwcap2 (pid, 8); 954 if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1)) 955 { 956 /* Make sure ptrace supports NT_ARM_ZT. */ 957 features.sme2 = supports_zt_registers (tid); 958 } 959 960 current_process ()->tdesc = aarch64_linux_read_description (features); 961 962 /* Adjust the register sets we should use for this particular set of 963 features. */ 964 aarch64_adjust_register_sets (features); 965 } 966 else 967 current_process ()->tdesc = aarch32_linux_read_description (); 968 969 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread)); 970 } 971 972 /* Implementation of linux target ops method "get_regs_info". */ 973 974 const regs_info * 975 aarch64_target::get_regs_info () 976 { 977 if (!is_64bit_tdesc ()) 978 return ®s_info_aarch32; 979 980 /* AArch64 64-bit registers. */ 981 return ®s_info_aarch64; 982 } 983 984 /* Implementation of target ops method "supports_tracepoints". */ 985 986 bool 987 aarch64_target::supports_tracepoints () 988 { 989 if (current_thread == NULL) 990 return true; 991 else 992 { 993 /* We don't support tracepoints on aarch32 now. */ 994 return is_64bit_tdesc (); 995 } 996 } 997 998 /* Implementation of linux target ops method "low_get_thread_area". */ 999 1000 int 1001 aarch64_target::low_get_thread_area (int lwpid, CORE_ADDR *addrp) 1002 { 1003 struct iovec iovec; 1004 uint64_t reg; 1005 1006 iovec.iov_base = ® 1007 iovec.iov_len = sizeof (reg); 1008 1009 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) 1010 return -1; 1011 1012 *addrp = reg; 1013 1014 return 0; 1015 } 1016 1017 bool 1018 aarch64_target::low_supports_catch_syscall () 1019 { 1020 return true; 1021 } 1022 1023 /* Implementation of linux target ops method "low_get_syscall_trapinfo". */ 1024 1025 void 1026 aarch64_target::low_get_syscall_trapinfo (regcache *regcache, int *sysno) 1027 { 1028 int use_64bit = register_size (regcache->tdesc, 0) == 8; 1029 1030 if (use_64bit) 1031 { 1032 long l_sysno; 1033 1034 collect_register_by_name (regcache, "x8", &l_sysno); 1035 *sysno = (int) l_sysno; 1036 } 1037 else 1038 collect_register_by_name (regcache, "r7", sysno); 1039 } 1040 1041 /* List of condition codes that we need. */ 1042 1043 enum aarch64_condition_codes 1044 { 1045 EQ = 0x0, 1046 NE = 0x1, 1047 LO = 0x3, 1048 GE = 0xa, 1049 LT = 0xb, 1050 GT = 0xc, 1051 LE = 0xd, 1052 }; 1053 1054 enum aarch64_operand_type 1055 { 1056 OPERAND_IMMEDIATE, 1057 OPERAND_REGISTER, 1058 }; 1059 1060 /* Representation of an operand. At this time, it only supports register 1061 and immediate types. */ 1062 1063 struct aarch64_operand 1064 { 1065 /* Type of the operand. */ 1066 enum aarch64_operand_type type; 1067 1068 /* Value of the operand according to the type. */ 1069 union 1070 { 1071 uint32_t imm; 1072 struct aarch64_register reg; 1073 }; 1074 }; 1075 1076 /* List of registers that we are currently using, we can add more here as 1077 we need to use them. */ 1078 1079 /* General purpose scratch registers (64 bit). */ 1080 static const struct aarch64_register x0 = { 0, 1 }; 1081 static const struct aarch64_register x1 = { 1, 1 }; 1082 static const struct aarch64_register x2 = { 2, 1 }; 1083 static const struct aarch64_register x3 = { 3, 1 }; 1084 static const struct aarch64_register x4 = { 4, 1 }; 1085 1086 /* General purpose scratch registers (32 bit). */ 1087 static const struct aarch64_register w0 = { 0, 0 }; 1088 static const struct aarch64_register w2 = { 2, 0 }; 1089 1090 /* Intra-procedure scratch registers. */ 1091 static const struct aarch64_register ip0 = { 16, 1 }; 1092 1093 /* Special purpose registers. */ 1094 static const struct aarch64_register fp = { 29, 1 }; 1095 static const struct aarch64_register lr = { 30, 1 }; 1096 static const struct aarch64_register sp = { 31, 1 }; 1097 static const struct aarch64_register xzr = { 31, 1 }; 1098 1099 /* Dynamically allocate a new register. If we know the register 1100 statically, we should make it a global as above instead of using this 1101 helper function. */ 1102 1103 static struct aarch64_register 1104 aarch64_register (unsigned num, int is64) 1105 { 1106 return (struct aarch64_register) { num, is64 }; 1107 } 1108 1109 /* Helper function to create a register operand, for instructions with 1110 different types of operands. 1111 1112 For example: 1113 p += emit_mov (p, x0, register_operand (x1)); */ 1114 1115 static struct aarch64_operand 1116 register_operand (struct aarch64_register reg) 1117 { 1118 struct aarch64_operand operand; 1119 1120 operand.type = OPERAND_REGISTER; 1121 operand.reg = reg; 1122 1123 return operand; 1124 } 1125 1126 /* Helper function to create an immediate operand, for instructions with 1127 different types of operands. 1128 1129 For example: 1130 p += emit_mov (p, x0, immediate_operand (12)); */ 1131 1132 static struct aarch64_operand 1133 immediate_operand (uint32_t imm) 1134 { 1135 struct aarch64_operand operand; 1136 1137 operand.type = OPERAND_IMMEDIATE; 1138 operand.imm = imm; 1139 1140 return operand; 1141 } 1142 1143 /* Helper function to create an offset memory operand. 1144 1145 For example: 1146 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */ 1147 1148 static struct aarch64_memory_operand 1149 offset_memory_operand (int32_t offset) 1150 { 1151 return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset }; 1152 } 1153 1154 /* Helper function to create a pre-index memory operand. 1155 1156 For example: 1157 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */ 1158 1159 static struct aarch64_memory_operand 1160 preindex_memory_operand (int32_t index) 1161 { 1162 return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index }; 1163 } 1164 1165 /* Helper function to create a post-index memory operand. 1166 1167 For example: 1168 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */ 1169 1170 static struct aarch64_memory_operand 1171 postindex_memory_operand (int32_t index) 1172 { 1173 return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index }; 1174 } 1175 1176 /* System control registers. These special registers can be written and 1177 read with the MRS and MSR instructions. 1178 1179 - NZCV: Condition flags. GDB refers to this register under the CPSR 1180 name. 1181 - FPSR: Floating-point status register. 1182 - FPCR: Floating-point control registers. 1183 - TPIDR_EL0: Software thread ID register. */ 1184 1185 enum aarch64_system_control_registers 1186 { 1187 /* op0 op1 crn crm op2 */ 1188 NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0, 1189 FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1, 1190 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0, 1191 TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2 1192 }; 1193 1194 /* Write a BLR instruction into *BUF. 1195 1196 BLR rn 1197 1198 RN is the register to branch to. */ 1199 1200 static int 1201 emit_blr (uint32_t *buf, struct aarch64_register rn) 1202 { 1203 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5)); 1204 } 1205 1206 /* Write a RET instruction into *BUF. 1207 1208 RET xn 1209 1210 RN is the register to branch to. */ 1211 1212 static int 1213 emit_ret (uint32_t *buf, struct aarch64_register rn) 1214 { 1215 return aarch64_emit_insn (buf, RET | ENCODE (rn.num, 5, 5)); 1216 } 1217 1218 static int 1219 emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode, 1220 struct aarch64_register rt, 1221 struct aarch64_register rt2, 1222 struct aarch64_register rn, 1223 struct aarch64_memory_operand operand) 1224 { 1225 uint32_t opc; 1226 uint32_t pre_index; 1227 uint32_t write_back; 1228 1229 if (rt.is64) 1230 opc = ENCODE (2, 2, 30); 1231 else 1232 opc = ENCODE (0, 2, 30); 1233 1234 switch (operand.type) 1235 { 1236 case MEMORY_OPERAND_OFFSET: 1237 { 1238 pre_index = ENCODE (1, 1, 24); 1239 write_back = ENCODE (0, 1, 23); 1240 break; 1241 } 1242 case MEMORY_OPERAND_POSTINDEX: 1243 { 1244 pre_index = ENCODE (0, 1, 24); 1245 write_back = ENCODE (1, 1, 23); 1246 break; 1247 } 1248 case MEMORY_OPERAND_PREINDEX: 1249 { 1250 pre_index = ENCODE (1, 1, 24); 1251 write_back = ENCODE (1, 1, 23); 1252 break; 1253 } 1254 default: 1255 return 0; 1256 } 1257 1258 return aarch64_emit_insn (buf, opcode | opc | pre_index | write_back 1259 | ENCODE (operand.index >> 3, 7, 15) 1260 | ENCODE (rt2.num, 5, 10) 1261 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); 1262 } 1263 1264 /* Write a STP instruction into *BUF. 1265 1266 STP rt, rt2, [rn, #offset] 1267 STP rt, rt2, [rn, #index]! 1268 STP rt, rt2, [rn], #index 1269 1270 RT and RT2 are the registers to store. 1271 RN is the base address register. 1272 OFFSET is the immediate to add to the base address. It is limited to a 1273 -512 .. 504 range (7 bits << 3). */ 1274 1275 static int 1276 emit_stp (uint32_t *buf, struct aarch64_register rt, 1277 struct aarch64_register rt2, struct aarch64_register rn, 1278 struct aarch64_memory_operand operand) 1279 { 1280 return emit_load_store_pair (buf, STP, rt, rt2, rn, operand); 1281 } 1282 1283 /* Write a LDP instruction into *BUF. 1284 1285 LDP rt, rt2, [rn, #offset] 1286 LDP rt, rt2, [rn, #index]! 1287 LDP rt, rt2, [rn], #index 1288 1289 RT and RT2 are the registers to store. 1290 RN is the base address register. 1291 OFFSET is the immediate to add to the base address. It is limited to a 1292 -512 .. 504 range (7 bits << 3). */ 1293 1294 static int 1295 emit_ldp (uint32_t *buf, struct aarch64_register rt, 1296 struct aarch64_register rt2, struct aarch64_register rn, 1297 struct aarch64_memory_operand operand) 1298 { 1299 return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand); 1300 } 1301 1302 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF. 1303 1304 LDP qt, qt2, [rn, #offset] 1305 1306 RT and RT2 are the Q registers to store. 1307 RN is the base address register. 1308 OFFSET is the immediate to add to the base address. It is limited to 1309 -1024 .. 1008 range (7 bits << 4). */ 1310 1311 static int 1312 emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, 1313 struct aarch64_register rn, int32_t offset) 1314 { 1315 uint32_t opc = ENCODE (2, 2, 30); 1316 uint32_t pre_index = ENCODE (1, 1, 24); 1317 1318 return aarch64_emit_insn (buf, LDP_SIMD_VFP | opc | pre_index 1319 | ENCODE (offset >> 4, 7, 15) 1320 | ENCODE (rt2, 5, 10) 1321 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); 1322 } 1323 1324 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF. 1325 1326 STP qt, qt2, [rn, #offset] 1327 1328 RT and RT2 are the Q registers to store. 1329 RN is the base address register. 1330 OFFSET is the immediate to add to the base address. It is limited to 1331 -1024 .. 1008 range (7 bits << 4). */ 1332 1333 static int 1334 emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, 1335 struct aarch64_register rn, int32_t offset) 1336 { 1337 uint32_t opc = ENCODE (2, 2, 30); 1338 uint32_t pre_index = ENCODE (1, 1, 24); 1339 1340 return aarch64_emit_insn (buf, STP_SIMD_VFP | opc | pre_index 1341 | ENCODE (offset >> 4, 7, 15) 1342 | ENCODE (rt2, 5, 10) 1343 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); 1344 } 1345 1346 /* Write a LDRH instruction into *BUF. 1347 1348 LDRH wt, [xn, #offset] 1349 LDRH wt, [xn, #index]! 1350 LDRH wt, [xn], #index 1351 1352 RT is the register to store. 1353 RN is the base address register. 1354 OFFSET is the immediate to add to the base address. It is limited to 1355 0 .. 32760 range (12 bits << 3). */ 1356 1357 static int 1358 emit_ldrh (uint32_t *buf, struct aarch64_register rt, 1359 struct aarch64_register rn, 1360 struct aarch64_memory_operand operand) 1361 { 1362 return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand); 1363 } 1364 1365 /* Write a LDRB instruction into *BUF. 1366 1367 LDRB wt, [xn, #offset] 1368 LDRB wt, [xn, #index]! 1369 LDRB wt, [xn], #index 1370 1371 RT is the register to store. 1372 RN is the base address register. 1373 OFFSET is the immediate to add to the base address. It is limited to 1374 0 .. 32760 range (12 bits << 3). */ 1375 1376 static int 1377 emit_ldrb (uint32_t *buf, struct aarch64_register rt, 1378 struct aarch64_register rn, 1379 struct aarch64_memory_operand operand) 1380 { 1381 return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand); 1382 } 1383 1384 1385 1386 /* Write a STR instruction into *BUF. 1387 1388 STR rt, [rn, #offset] 1389 STR rt, [rn, #index]! 1390 STR rt, [rn], #index 1391 1392 RT is the register to store. 1393 RN is the base address register. 1394 OFFSET is the immediate to add to the base address. It is limited to 1395 0 .. 32760 range (12 bits << 3). */ 1396 1397 static int 1398 emit_str (uint32_t *buf, struct aarch64_register rt, 1399 struct aarch64_register rn, 1400 struct aarch64_memory_operand operand) 1401 { 1402 return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand); 1403 } 1404 1405 /* Helper function emitting an exclusive load or store instruction. */ 1406 1407 static int 1408 emit_load_store_exclusive (uint32_t *buf, uint32_t size, 1409 enum aarch64_opcodes opcode, 1410 struct aarch64_register rs, 1411 struct aarch64_register rt, 1412 struct aarch64_register rt2, 1413 struct aarch64_register rn) 1414 { 1415 return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) 1416 | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10) 1417 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); 1418 } 1419 1420 /* Write a LAXR instruction into *BUF. 1421 1422 LDAXR rt, [xn] 1423 1424 RT is the destination register. 1425 RN is the base address register. */ 1426 1427 static int 1428 emit_ldaxr (uint32_t *buf, struct aarch64_register rt, 1429 struct aarch64_register rn) 1430 { 1431 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt, 1432 xzr, rn); 1433 } 1434 1435 /* Write a STXR instruction into *BUF. 1436 1437 STXR ws, rt, [xn] 1438 1439 RS is the result register, it indicates if the store succeeded or not. 1440 RT is the destination register. 1441 RN is the base address register. */ 1442 1443 static int 1444 emit_stxr (uint32_t *buf, struct aarch64_register rs, 1445 struct aarch64_register rt, struct aarch64_register rn) 1446 { 1447 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt, 1448 xzr, rn); 1449 } 1450 1451 /* Write a STLR instruction into *BUF. 1452 1453 STLR rt, [xn] 1454 1455 RT is the register to store. 1456 RN is the base address register. */ 1457 1458 static int 1459 emit_stlr (uint32_t *buf, struct aarch64_register rt, 1460 struct aarch64_register rn) 1461 { 1462 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt, 1463 xzr, rn); 1464 } 1465 1466 /* Helper function for data processing instructions with register sources. */ 1467 1468 static int 1469 emit_data_processing_reg (uint32_t *buf, uint32_t opcode, 1470 struct aarch64_register rd, 1471 struct aarch64_register rn, 1472 struct aarch64_register rm) 1473 { 1474 uint32_t size = ENCODE (rd.is64, 1, 31); 1475 1476 return aarch64_emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16) 1477 | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0)); 1478 } 1479 1480 /* Helper function for data processing instructions taking either a register 1481 or an immediate. */ 1482 1483 static int 1484 emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode, 1485 struct aarch64_register rd, 1486 struct aarch64_register rn, 1487 struct aarch64_operand operand) 1488 { 1489 uint32_t size = ENCODE (rd.is64, 1, 31); 1490 /* The opcode is different for register and immediate source operands. */ 1491 uint32_t operand_opcode; 1492 1493 if (operand.type == OPERAND_IMMEDIATE) 1494 { 1495 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */ 1496 operand_opcode = ENCODE (8, 4, 25); 1497 1498 return aarch64_emit_insn (buf, opcode | operand_opcode | size 1499 | ENCODE (operand.imm, 12, 10) 1500 | ENCODE (rn.num, 5, 5) 1501 | ENCODE (rd.num, 5, 0)); 1502 } 1503 else 1504 { 1505 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */ 1506 operand_opcode = ENCODE (5, 4, 25); 1507 1508 return emit_data_processing_reg (buf, opcode | operand_opcode, rd, 1509 rn, operand.reg); 1510 } 1511 } 1512 1513 /* Write an ADD instruction into *BUF. 1514 1515 ADD rd, rn, #imm 1516 ADD rd, rn, rm 1517 1518 This function handles both an immediate and register add. 1519 1520 RD is the destination register. 1521 RN is the input register. 1522 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or 1523 OPERAND_REGISTER. */ 1524 1525 static int 1526 emit_add (uint32_t *buf, struct aarch64_register rd, 1527 struct aarch64_register rn, struct aarch64_operand operand) 1528 { 1529 return emit_data_processing (buf, ADD, rd, rn, operand); 1530 } 1531 1532 /* Write a SUB instruction into *BUF. 1533 1534 SUB rd, rn, #imm 1535 SUB rd, rn, rm 1536 1537 This function handles both an immediate and register sub. 1538 1539 RD is the destination register. 1540 RN is the input register. 1541 IMM is the immediate to substract to RN. */ 1542 1543 static int 1544 emit_sub (uint32_t *buf, struct aarch64_register rd, 1545 struct aarch64_register rn, struct aarch64_operand operand) 1546 { 1547 return emit_data_processing (buf, SUB, rd, rn, operand); 1548 } 1549 1550 /* Write a MOV instruction into *BUF. 1551 1552 MOV rd, #imm 1553 MOV rd, rm 1554 1555 This function handles both a wide immediate move and a register move, 1556 with the condition that the source register is not xzr. xzr and the 1557 stack pointer share the same encoding and this function only supports 1558 the stack pointer. 1559 1560 RD is the destination register. 1561 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or 1562 OPERAND_REGISTER. */ 1563 1564 static int 1565 emit_mov (uint32_t *buf, struct aarch64_register rd, 1566 struct aarch64_operand operand) 1567 { 1568 if (operand.type == OPERAND_IMMEDIATE) 1569 { 1570 uint32_t size = ENCODE (rd.is64, 1, 31); 1571 /* Do not shift the immediate. */ 1572 uint32_t shift = ENCODE (0, 2, 21); 1573 1574 return aarch64_emit_insn (buf, MOV | size | shift 1575 | ENCODE (operand.imm, 16, 5) 1576 | ENCODE (rd.num, 5, 0)); 1577 } 1578 else 1579 return emit_add (buf, rd, operand.reg, immediate_operand (0)); 1580 } 1581 1582 /* Write a MOVK instruction into *BUF. 1583 1584 MOVK rd, #imm, lsl #shift 1585 1586 RD is the destination register. 1587 IMM is the immediate. 1588 SHIFT is the logical shift left to apply to IMM. */ 1589 1590 static int 1591 emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm, 1592 unsigned shift) 1593 { 1594 uint32_t size = ENCODE (rd.is64, 1, 31); 1595 1596 return aarch64_emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) | 1597 ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0)); 1598 } 1599 1600 /* Write instructions into *BUF in order to move ADDR into a register. 1601 ADDR can be a 64-bit value. 1602 1603 This function will emit a series of MOV and MOVK instructions, such as: 1604 1605 MOV xd, #(addr) 1606 MOVK xd, #(addr >> 16), lsl #16 1607 MOVK xd, #(addr >> 32), lsl #32 1608 MOVK xd, #(addr >> 48), lsl #48 */ 1609 1610 static int 1611 emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr) 1612 { 1613 uint32_t *p = buf; 1614 1615 /* The MOV (wide immediate) instruction clears to top bits of the 1616 register. */ 1617 p += emit_mov (p, rd, immediate_operand (addr & 0xffff)); 1618 1619 if ((addr >> 16) != 0) 1620 p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1); 1621 else 1622 return p - buf; 1623 1624 if ((addr >> 32) != 0) 1625 p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2); 1626 else 1627 return p - buf; 1628 1629 if ((addr >> 48) != 0) 1630 p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3); 1631 1632 return p - buf; 1633 } 1634 1635 /* Write a SUBS instruction into *BUF. 1636 1637 SUBS rd, rn, rm 1638 1639 This instruction update the condition flags. 1640 1641 RD is the destination register. 1642 RN and RM are the source registers. */ 1643 1644 static int 1645 emit_subs (uint32_t *buf, struct aarch64_register rd, 1646 struct aarch64_register rn, struct aarch64_operand operand) 1647 { 1648 return emit_data_processing (buf, SUBS, rd, rn, operand); 1649 } 1650 1651 /* Write a CMP instruction into *BUF. 1652 1653 CMP rn, rm 1654 1655 This instruction is an alias of SUBS xzr, rn, rm. 1656 1657 RN and RM are the registers to compare. */ 1658 1659 static int 1660 emit_cmp (uint32_t *buf, struct aarch64_register rn, 1661 struct aarch64_operand operand) 1662 { 1663 return emit_subs (buf, xzr, rn, operand); 1664 } 1665 1666 /* Write a AND instruction into *BUF. 1667 1668 AND rd, rn, rm 1669 1670 RD is the destination register. 1671 RN and RM are the source registers. */ 1672 1673 static int 1674 emit_and (uint32_t *buf, struct aarch64_register rd, 1675 struct aarch64_register rn, struct aarch64_register rm) 1676 { 1677 return emit_data_processing_reg (buf, AND, rd, rn, rm); 1678 } 1679 1680 /* Write a ORR instruction into *BUF. 1681 1682 ORR rd, rn, rm 1683 1684 RD is the destination register. 1685 RN and RM are the source registers. */ 1686 1687 static int 1688 emit_orr (uint32_t *buf, struct aarch64_register rd, 1689 struct aarch64_register rn, struct aarch64_register rm) 1690 { 1691 return emit_data_processing_reg (buf, ORR, rd, rn, rm); 1692 } 1693 1694 /* Write a ORN instruction into *BUF. 1695 1696 ORN rd, rn, rm 1697 1698 RD is the destination register. 1699 RN and RM are the source registers. */ 1700 1701 static int 1702 emit_orn (uint32_t *buf, struct aarch64_register rd, 1703 struct aarch64_register rn, struct aarch64_register rm) 1704 { 1705 return emit_data_processing_reg (buf, ORN, rd, rn, rm); 1706 } 1707 1708 /* Write a EOR instruction into *BUF. 1709 1710 EOR rd, rn, rm 1711 1712 RD is the destination register. 1713 RN and RM are the source registers. */ 1714 1715 static int 1716 emit_eor (uint32_t *buf, struct aarch64_register rd, 1717 struct aarch64_register rn, struct aarch64_register rm) 1718 { 1719 return emit_data_processing_reg (buf, EOR, rd, rn, rm); 1720 } 1721 1722 /* Write a MVN instruction into *BUF. 1723 1724 MVN rd, rm 1725 1726 This is an alias for ORN rd, xzr, rm. 1727 1728 RD is the destination register. 1729 RM is the source register. */ 1730 1731 static int 1732 emit_mvn (uint32_t *buf, struct aarch64_register rd, 1733 struct aarch64_register rm) 1734 { 1735 return emit_orn (buf, rd, xzr, rm); 1736 } 1737 1738 /* Write a LSLV instruction into *BUF. 1739 1740 LSLV rd, rn, rm 1741 1742 RD is the destination register. 1743 RN and RM are the source registers. */ 1744 1745 static int 1746 emit_lslv (uint32_t *buf, struct aarch64_register rd, 1747 struct aarch64_register rn, struct aarch64_register rm) 1748 { 1749 return emit_data_processing_reg (buf, LSLV, rd, rn, rm); 1750 } 1751 1752 /* Write a LSRV instruction into *BUF. 1753 1754 LSRV rd, rn, rm 1755 1756 RD is the destination register. 1757 RN and RM are the source registers. */ 1758 1759 static int 1760 emit_lsrv (uint32_t *buf, struct aarch64_register rd, 1761 struct aarch64_register rn, struct aarch64_register rm) 1762 { 1763 return emit_data_processing_reg (buf, LSRV, rd, rn, rm); 1764 } 1765 1766 /* Write a ASRV instruction into *BUF. 1767 1768 ASRV rd, rn, rm 1769 1770 RD is the destination register. 1771 RN and RM are the source registers. */ 1772 1773 static int 1774 emit_asrv (uint32_t *buf, struct aarch64_register rd, 1775 struct aarch64_register rn, struct aarch64_register rm) 1776 { 1777 return emit_data_processing_reg (buf, ASRV, rd, rn, rm); 1778 } 1779 1780 /* Write a MUL instruction into *BUF. 1781 1782 MUL rd, rn, rm 1783 1784 RD is the destination register. 1785 RN and RM are the source registers. */ 1786 1787 static int 1788 emit_mul (uint32_t *buf, struct aarch64_register rd, 1789 struct aarch64_register rn, struct aarch64_register rm) 1790 { 1791 return emit_data_processing_reg (buf, MUL, rd, rn, rm); 1792 } 1793 1794 /* Write a MRS instruction into *BUF. The register size is 64-bit. 1795 1796 MRS xt, system_reg 1797 1798 RT is the destination register. 1799 SYSTEM_REG is special purpose register to read. */ 1800 1801 static int 1802 emit_mrs (uint32_t *buf, struct aarch64_register rt, 1803 enum aarch64_system_control_registers system_reg) 1804 { 1805 return aarch64_emit_insn (buf, MRS | ENCODE (system_reg, 15, 5) 1806 | ENCODE (rt.num, 5, 0)); 1807 } 1808 1809 /* Write a MSR instruction into *BUF. The register size is 64-bit. 1810 1811 MSR system_reg, xt 1812 1813 SYSTEM_REG is special purpose register to write. 1814 RT is the input register. */ 1815 1816 static int 1817 emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg, 1818 struct aarch64_register rt) 1819 { 1820 return aarch64_emit_insn (buf, MSR | ENCODE (system_reg, 15, 5) 1821 | ENCODE (rt.num, 5, 0)); 1822 } 1823 1824 /* Write a SEVL instruction into *BUF. 1825 1826 This is a hint instruction telling the hardware to trigger an event. */ 1827 1828 static int 1829 emit_sevl (uint32_t *buf) 1830 { 1831 return aarch64_emit_insn (buf, SEVL); 1832 } 1833 1834 /* Write a WFE instruction into *BUF. 1835 1836 This is a hint instruction telling the hardware to wait for an event. */ 1837 1838 static int 1839 emit_wfe (uint32_t *buf) 1840 { 1841 return aarch64_emit_insn (buf, WFE); 1842 } 1843 1844 /* Write a SBFM instruction into *BUF. 1845 1846 SBFM rd, rn, #immr, #imms 1847 1848 This instruction moves the bits from #immr to #imms into the 1849 destination, sign extending the result. 1850 1851 RD is the destination register. 1852 RN is the source register. 1853 IMMR is the bit number to start at (least significant bit). 1854 IMMS is the bit number to stop at (most significant bit). */ 1855 1856 static int 1857 emit_sbfm (uint32_t *buf, struct aarch64_register rd, 1858 struct aarch64_register rn, uint32_t immr, uint32_t imms) 1859 { 1860 uint32_t size = ENCODE (rd.is64, 1, 31); 1861 uint32_t n = ENCODE (rd.is64, 1, 22); 1862 1863 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16) 1864 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) 1865 | ENCODE (rd.num, 5, 0)); 1866 } 1867 1868 /* Write a SBFX instruction into *BUF. 1869 1870 SBFX rd, rn, #lsb, #width 1871 1872 This instruction moves #width bits from #lsb into the destination, sign 1873 extending the result. This is an alias for: 1874 1875 SBFM rd, rn, #lsb, #(lsb + width - 1) 1876 1877 RD is the destination register. 1878 RN is the source register. 1879 LSB is the bit number to start at (least significant bit). 1880 WIDTH is the number of bits to move. */ 1881 1882 static int 1883 emit_sbfx (uint32_t *buf, struct aarch64_register rd, 1884 struct aarch64_register rn, uint32_t lsb, uint32_t width) 1885 { 1886 return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1); 1887 } 1888 1889 /* Write a UBFM instruction into *BUF. 1890 1891 UBFM rd, rn, #immr, #imms 1892 1893 This instruction moves the bits from #immr to #imms into the 1894 destination, extending the result with zeros. 1895 1896 RD is the destination register. 1897 RN is the source register. 1898 IMMR is the bit number to start at (least significant bit). 1899 IMMS is the bit number to stop at (most significant bit). */ 1900 1901 static int 1902 emit_ubfm (uint32_t *buf, struct aarch64_register rd, 1903 struct aarch64_register rn, uint32_t immr, uint32_t imms) 1904 { 1905 uint32_t size = ENCODE (rd.is64, 1, 31); 1906 uint32_t n = ENCODE (rd.is64, 1, 22); 1907 1908 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16) 1909 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) 1910 | ENCODE (rd.num, 5, 0)); 1911 } 1912 1913 /* Write a UBFX instruction into *BUF. 1914 1915 UBFX rd, rn, #lsb, #width 1916 1917 This instruction moves #width bits from #lsb into the destination, 1918 extending the result with zeros. This is an alias for: 1919 1920 UBFM rd, rn, #lsb, #(lsb + width - 1) 1921 1922 RD is the destination register. 1923 RN is the source register. 1924 LSB is the bit number to start at (least significant bit). 1925 WIDTH is the number of bits to move. */ 1926 1927 static int 1928 emit_ubfx (uint32_t *buf, struct aarch64_register rd, 1929 struct aarch64_register rn, uint32_t lsb, uint32_t width) 1930 { 1931 return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1); 1932 } 1933 1934 /* Write a CSINC instruction into *BUF. 1935 1936 CSINC rd, rn, rm, cond 1937 1938 This instruction conditionally increments rn or rm and places the result 1939 in rd. rn is chosen is the condition is true. 1940 1941 RD is the destination register. 1942 RN and RM are the source registers. 1943 COND is the encoded condition. */ 1944 1945 static int 1946 emit_csinc (uint32_t *buf, struct aarch64_register rd, 1947 struct aarch64_register rn, struct aarch64_register rm, 1948 unsigned cond) 1949 { 1950 uint32_t size = ENCODE (rd.is64, 1, 31); 1951 1952 return aarch64_emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16) 1953 | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5) 1954 | ENCODE (rd.num, 5, 0)); 1955 } 1956 1957 /* Write a CSET instruction into *BUF. 1958 1959 CSET rd, cond 1960 1961 This instruction conditionally write 1 or 0 in the destination register. 1962 1 is written if the condition is true. This is an alias for: 1963 1964 CSINC rd, xzr, xzr, !cond 1965 1966 Note that the condition needs to be inverted. 1967 1968 RD is the destination register. 1969 RN and RM are the source registers. 1970 COND is the encoded condition. */ 1971 1972 static int 1973 emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond) 1974 { 1975 /* The least significant bit of the condition needs toggling in order to 1976 invert it. */ 1977 return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1); 1978 } 1979 1980 /* Write LEN instructions from BUF into the inferior memory at *TO. 1981 1982 Note instructions are always little endian on AArch64, unlike data. */ 1983 1984 static void 1985 append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf) 1986 { 1987 size_t byte_len = len * sizeof (uint32_t); 1988 #if (__BYTE_ORDER == __BIG_ENDIAN) 1989 uint32_t *le_buf = (uint32_t *) xmalloc (byte_len); 1990 size_t i; 1991 1992 for (i = 0; i < len; i++) 1993 le_buf[i] = htole32 (buf[i]); 1994 1995 target_write_memory (*to, (const unsigned char *) le_buf, byte_len); 1996 1997 xfree (le_buf); 1998 #else 1999 target_write_memory (*to, (const unsigned char *) buf, byte_len); 2000 #endif 2001 2002 *to += byte_len; 2003 } 2004 2005 /* Sub-class of struct aarch64_insn_data, store information of 2006 instruction relocation for fast tracepoint. Visitor can 2007 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save 2008 the relocated instructions in buffer pointed by INSN_PTR. */ 2009 2010 struct aarch64_insn_relocation_data 2011 { 2012 struct aarch64_insn_data base; 2013 2014 /* The new address the instruction is relocated to. */ 2015 CORE_ADDR new_addr; 2016 /* Pointer to the buffer of relocated instruction(s). */ 2017 uint32_t *insn_ptr; 2018 }; 2019 2020 /* Implementation of aarch64_insn_visitor method "b". */ 2021 2022 static void 2023 aarch64_ftrace_insn_reloc_b (const int is_bl, const int32_t offset, 2024 struct aarch64_insn_data *data) 2025 { 2026 struct aarch64_insn_relocation_data *insn_reloc 2027 = (struct aarch64_insn_relocation_data *) data; 2028 int64_t new_offset 2029 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2030 2031 if (can_encode_int32 (new_offset, 28)) 2032 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, is_bl, new_offset); 2033 } 2034 2035 /* Implementation of aarch64_insn_visitor method "b_cond". */ 2036 2037 static void 2038 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond, const int32_t offset, 2039 struct aarch64_insn_data *data) 2040 { 2041 struct aarch64_insn_relocation_data *insn_reloc 2042 = (struct aarch64_insn_relocation_data *) data; 2043 int64_t new_offset 2044 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2045 2046 if (can_encode_int32 (new_offset, 21)) 2047 { 2048 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 2049 new_offset); 2050 } 2051 else if (can_encode_int32 (new_offset, 28)) 2052 { 2053 /* The offset is out of range for a conditional branch 2054 instruction but not for a unconditional branch. We can use 2055 the following instructions instead: 2056 2057 B.COND TAKEN ; If cond is true, then jump to TAKEN. 2058 B NOT_TAKEN ; Else jump over TAKEN and continue. 2059 TAKEN: 2060 B #(offset - 8) 2061 NOT_TAKEN: 2062 2063 */ 2064 2065 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 8); 2066 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2067 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8); 2068 } 2069 } 2070 2071 /* Implementation of aarch64_insn_visitor method "cb". */ 2072 2073 static void 2074 aarch64_ftrace_insn_reloc_cb (const int32_t offset, const int is_cbnz, 2075 const unsigned rn, int is64, 2076 struct aarch64_insn_data *data) 2077 { 2078 struct aarch64_insn_relocation_data *insn_reloc 2079 = (struct aarch64_insn_relocation_data *) data; 2080 int64_t new_offset 2081 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2082 2083 if (can_encode_int32 (new_offset, 21)) 2084 { 2085 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz, 2086 aarch64_register (rn, is64), new_offset); 2087 } 2088 else if (can_encode_int32 (new_offset, 28)) 2089 { 2090 /* The offset is out of range for a compare and branch 2091 instruction but not for a unconditional branch. We can use 2092 the following instructions instead: 2093 2094 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. 2095 B NOT_TAKEN ; Else jump over TAKEN and continue. 2096 TAKEN: 2097 B #(offset - 8) 2098 NOT_TAKEN: 2099 2100 */ 2101 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz, 2102 aarch64_register (rn, is64), 8); 2103 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2104 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8); 2105 } 2106 } 2107 2108 /* Implementation of aarch64_insn_visitor method "tb". */ 2109 2110 static void 2111 aarch64_ftrace_insn_reloc_tb (const int32_t offset, int is_tbnz, 2112 const unsigned rt, unsigned bit, 2113 struct aarch64_insn_data *data) 2114 { 2115 struct aarch64_insn_relocation_data *insn_reloc 2116 = (struct aarch64_insn_relocation_data *) data; 2117 int64_t new_offset 2118 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2119 2120 if (can_encode_int32 (new_offset, 16)) 2121 { 2122 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit, 2123 aarch64_register (rt, 1), new_offset); 2124 } 2125 else if (can_encode_int32 (new_offset, 28)) 2126 { 2127 /* The offset is out of range for a test bit and branch 2128 instruction but not for a unconditional branch. We can use 2129 the following instructions instead: 2130 2131 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. 2132 B NOT_TAKEN ; Else jump over TAKEN and continue. 2133 TAKEN: 2134 B #(offset - 8) 2135 NOT_TAKEN: 2136 2137 */ 2138 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit, 2139 aarch64_register (rt, 1), 8); 2140 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2141 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 2142 new_offset - 8); 2143 } 2144 } 2145 2146 /* Implementation of aarch64_insn_visitor method "adr". */ 2147 2148 static void 2149 aarch64_ftrace_insn_reloc_adr (const int32_t offset, const unsigned rd, 2150 const int is_adrp, 2151 struct aarch64_insn_data *data) 2152 { 2153 struct aarch64_insn_relocation_data *insn_reloc 2154 = (struct aarch64_insn_relocation_data *) data; 2155 /* We know exactly the address the ADR{P,} instruction will compute. 2156 We can just write it to the destination register. */ 2157 CORE_ADDR address = data->insn_addr + offset; 2158 2159 if (is_adrp) 2160 { 2161 /* Clear the lower 12 bits of the offset to get the 4K page. */ 2162 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2163 aarch64_register (rd, 1), 2164 address & ~0xfff); 2165 } 2166 else 2167 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2168 aarch64_register (rd, 1), address); 2169 } 2170 2171 /* Implementation of aarch64_insn_visitor method "ldr_literal". */ 2172 2173 static void 2174 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset, const int is_sw, 2175 const unsigned rt, const int is64, 2176 struct aarch64_insn_data *data) 2177 { 2178 struct aarch64_insn_relocation_data *insn_reloc 2179 = (struct aarch64_insn_relocation_data *) data; 2180 CORE_ADDR address = data->insn_addr + offset; 2181 2182 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2183 aarch64_register (rt, 1), address); 2184 2185 /* We know exactly what address to load from, and what register we 2186 can use: 2187 2188 MOV xd, #(oldloc + offset) 2189 MOVK xd, #((oldloc + offset) >> 16), lsl #16 2190 ... 2191 2192 LDR xd, [xd] ; or LDRSW xd, [xd] 2193 2194 */ 2195 2196 if (is_sw) 2197 insn_reloc->insn_ptr += emit_ldrsw (insn_reloc->insn_ptr, 2198 aarch64_register (rt, 1), 2199 aarch64_register (rt, 1), 2200 offset_memory_operand (0)); 2201 else 2202 insn_reloc->insn_ptr += emit_ldr (insn_reloc->insn_ptr, 2203 aarch64_register (rt, is64), 2204 aarch64_register (rt, 1), 2205 offset_memory_operand (0)); 2206 } 2207 2208 /* Implementation of aarch64_insn_visitor method "others". */ 2209 2210 static void 2211 aarch64_ftrace_insn_reloc_others (const uint32_t insn, 2212 struct aarch64_insn_data *data) 2213 { 2214 struct aarch64_insn_relocation_data *insn_reloc 2215 = (struct aarch64_insn_relocation_data *) data; 2216 2217 /* The instruction is not PC relative. Just re-emit it at the new 2218 location. */ 2219 insn_reloc->insn_ptr += aarch64_emit_insn (insn_reloc->insn_ptr, insn); 2220 } 2221 2222 static const struct aarch64_insn_visitor visitor = 2223 { 2224 aarch64_ftrace_insn_reloc_b, 2225 aarch64_ftrace_insn_reloc_b_cond, 2226 aarch64_ftrace_insn_reloc_cb, 2227 aarch64_ftrace_insn_reloc_tb, 2228 aarch64_ftrace_insn_reloc_adr, 2229 aarch64_ftrace_insn_reloc_ldr_literal, 2230 aarch64_ftrace_insn_reloc_others, 2231 }; 2232 2233 bool 2234 aarch64_target::supports_fast_tracepoints () 2235 { 2236 return true; 2237 } 2238 2239 /* Implementation of target ops method 2240 "install_fast_tracepoint_jump_pad". */ 2241 2242 int 2243 aarch64_target::install_fast_tracepoint_jump_pad 2244 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 2245 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 2246 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 2247 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 2248 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 2249 char *err) 2250 { 2251 uint32_t buf[256]; 2252 uint32_t *p = buf; 2253 int64_t offset; 2254 int i; 2255 uint32_t insn; 2256 CORE_ADDR buildaddr = *jump_entry; 2257 struct aarch64_insn_relocation_data insn_data; 2258 2259 /* We need to save the current state on the stack both to restore it 2260 later and to collect register values when the tracepoint is hit. 2261 2262 The saved registers are pushed in a layout that needs to be in sync 2263 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on 2264 the supply_fast_tracepoint_registers function will fill in the 2265 register cache from a pointer to saved registers on the stack we build 2266 here. 2267 2268 For simplicity, we set the size of each cell on the stack to 16 bytes. 2269 This way one cell can hold any register type, from system registers 2270 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer 2271 has to be 16 bytes aligned anyway. 2272 2273 Note that the CPSR register does not exist on AArch64. Instead we 2274 can access system bits describing the process state with the 2275 MRS/MSR instructions, namely the condition flags. We save them as 2276 if they are part of a CPSR register because that's how GDB 2277 interprets these system bits. At the moment, only the condition 2278 flags are saved in CPSR (NZCV). 2279 2280 Stack layout, each cell is 16 bytes (descending): 2281 2282 High *-------- SIMD&FP registers from 31 down to 0. --------* 2283 | q31 | 2284 . . 2285 . . 32 cells 2286 . . 2287 | q0 | 2288 *---- General purpose registers from 30 down to 0. ----* 2289 | x30 | 2290 . . 2291 . . 31 cells 2292 . . 2293 | x0 | 2294 *------------- Special purpose registers. -------------* 2295 | SP | 2296 | PC | 2297 | CPSR (NZCV) | 5 cells 2298 | FPSR | 2299 | FPCR | <- SP + 16 2300 *------------- collecting_t object --------------------* 2301 | TPIDR_EL0 | struct tracepoint * | 2302 Low *------------------------------------------------------* 2303 2304 After this stack is set up, we issue a call to the collector, passing 2305 it the saved registers at (SP + 16). */ 2306 2307 /* Push SIMD&FP registers on the stack: 2308 2309 SUB sp, sp, #(32 * 16) 2310 2311 STP q30, q31, [sp, #(30 * 16)] 2312 ... 2313 STP q0, q1, [sp] 2314 2315 */ 2316 p += emit_sub (p, sp, sp, immediate_operand (32 * 16)); 2317 for (i = 30; i >= 0; i -= 2) 2318 p += emit_stp_q_offset (p, i, i + 1, sp, i * 16); 2319 2320 /* Push general purpose registers on the stack. Note that we do not need 2321 to push x31 as it represents the xzr register and not the stack 2322 pointer in a STR instruction. 2323 2324 SUB sp, sp, #(31 * 16) 2325 2326 STR x30, [sp, #(30 * 16)] 2327 ... 2328 STR x0, [sp] 2329 2330 */ 2331 p += emit_sub (p, sp, sp, immediate_operand (31 * 16)); 2332 for (i = 30; i >= 0; i -= 1) 2333 p += emit_str (p, aarch64_register (i, 1), sp, 2334 offset_memory_operand (i * 16)); 2335 2336 /* Make space for 5 more cells. 2337 2338 SUB sp, sp, #(5 * 16) 2339 2340 */ 2341 p += emit_sub (p, sp, sp, immediate_operand (5 * 16)); 2342 2343 2344 /* Save SP: 2345 2346 ADD x4, sp, #((32 + 31 + 5) * 16) 2347 STR x4, [sp, #(4 * 16)] 2348 2349 */ 2350 p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16)); 2351 p += emit_str (p, x4, sp, offset_memory_operand (4 * 16)); 2352 2353 /* Save PC (tracepoint address): 2354 2355 MOV x3, #(tpaddr) 2356 ... 2357 2358 STR x3, [sp, #(3 * 16)] 2359 2360 */ 2361 2362 p += emit_mov_addr (p, x3, tpaddr); 2363 p += emit_str (p, x3, sp, offset_memory_operand (3 * 16)); 2364 2365 /* Save CPSR (NZCV), FPSR and FPCR: 2366 2367 MRS x2, nzcv 2368 MRS x1, fpsr 2369 MRS x0, fpcr 2370 2371 STR x2, [sp, #(2 * 16)] 2372 STR x1, [sp, #(1 * 16)] 2373 STR x0, [sp, #(0 * 16)] 2374 2375 */ 2376 p += emit_mrs (p, x2, NZCV); 2377 p += emit_mrs (p, x1, FPSR); 2378 p += emit_mrs (p, x0, FPCR); 2379 p += emit_str (p, x2, sp, offset_memory_operand (2 * 16)); 2380 p += emit_str (p, x1, sp, offset_memory_operand (1 * 16)); 2381 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16)); 2382 2383 /* Push the collecting_t object. It consist of the address of the 2384 tracepoint and an ID for the current thread. We get the latter by 2385 reading the tpidr_el0 system register. It corresponds to the 2386 NT_ARM_TLS register accessible with ptrace. 2387 2388 MOV x0, #(tpoint) 2389 ... 2390 2391 MRS x1, tpidr_el0 2392 2393 STP x0, x1, [sp, #-16]! 2394 2395 */ 2396 2397 p += emit_mov_addr (p, x0, tpoint); 2398 p += emit_mrs (p, x1, TPIDR_EL0); 2399 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16)); 2400 2401 /* Spin-lock: 2402 2403 The shared memory for the lock is at lockaddr. It will hold zero 2404 if no-one is holding the lock, otherwise it contains the address of 2405 the collecting_t object on the stack of the thread which acquired it. 2406 2407 At this stage, the stack pointer points to this thread's collecting_t 2408 object. 2409 2410 We use the following registers: 2411 - x0: Address of the lock. 2412 - x1: Pointer to collecting_t object. 2413 - x2: Scratch register. 2414 2415 MOV x0, #(lockaddr) 2416 ... 2417 MOV x1, sp 2418 2419 ; Trigger an event local to this core. So the following WFE 2420 ; instruction is ignored. 2421 SEVL 2422 again: 2423 ; Wait for an event. The event is triggered by either the SEVL 2424 ; or STLR instructions (store release). 2425 WFE 2426 2427 ; Atomically read at lockaddr. This marks the memory location as 2428 ; exclusive. This instruction also has memory constraints which 2429 ; make sure all previous data reads and writes are done before 2430 ; executing it. 2431 LDAXR x2, [x0] 2432 2433 ; Try again if another thread holds the lock. 2434 CBNZ x2, again 2435 2436 ; We can lock it! Write the address of the collecting_t object. 2437 ; This instruction will fail if the memory location is not marked 2438 ; as exclusive anymore. If it succeeds, it will remove the 2439 ; exclusive mark on the memory location. This way, if another 2440 ; thread executes this instruction before us, we will fail and try 2441 ; all over again. 2442 STXR w2, x1, [x0] 2443 CBNZ w2, again 2444 2445 */ 2446 2447 p += emit_mov_addr (p, x0, lockaddr); 2448 p += emit_mov (p, x1, register_operand (sp)); 2449 2450 p += emit_sevl (p); 2451 p += emit_wfe (p); 2452 p += emit_ldaxr (p, x2, x0); 2453 p += emit_cb (p, 1, w2, -2 * 4); 2454 p += emit_stxr (p, w2, x1, x0); 2455 p += emit_cb (p, 1, x2, -4 * 4); 2456 2457 /* Call collector (struct tracepoint *, unsigned char *): 2458 2459 MOV x0, #(tpoint) 2460 ... 2461 2462 ; Saved registers start after the collecting_t object. 2463 ADD x1, sp, #16 2464 2465 ; We use an intra-procedure-call scratch register. 2466 MOV ip0, #(collector) 2467 ... 2468 2469 ; And call back to C! 2470 BLR ip0 2471 2472 */ 2473 2474 p += emit_mov_addr (p, x0, tpoint); 2475 p += emit_add (p, x1, sp, immediate_operand (16)); 2476 2477 p += emit_mov_addr (p, ip0, collector); 2478 p += emit_blr (p, ip0); 2479 2480 /* Release the lock. 2481 2482 MOV x0, #(lockaddr) 2483 ... 2484 2485 ; This instruction is a normal store with memory ordering 2486 ; constraints. Thanks to this we do not have to put a data 2487 ; barrier instruction to make sure all data read and writes are done 2488 ; before this instruction is executed. Furthermore, this instruction 2489 ; will trigger an event, letting other threads know they can grab 2490 ; the lock. 2491 STLR xzr, [x0] 2492 2493 */ 2494 p += emit_mov_addr (p, x0, lockaddr); 2495 p += emit_stlr (p, xzr, x0); 2496 2497 /* Free collecting_t object: 2498 2499 ADD sp, sp, #16 2500 2501 */ 2502 p += emit_add (p, sp, sp, immediate_operand (16)); 2503 2504 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose 2505 registers from the stack. 2506 2507 LDR x2, [sp, #(2 * 16)] 2508 LDR x1, [sp, #(1 * 16)] 2509 LDR x0, [sp, #(0 * 16)] 2510 2511 MSR NZCV, x2 2512 MSR FPSR, x1 2513 MSR FPCR, x0 2514 2515 ADD sp, sp #(5 * 16) 2516 2517 */ 2518 p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16)); 2519 p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16)); 2520 p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16)); 2521 p += emit_msr (p, NZCV, x2); 2522 p += emit_msr (p, FPSR, x1); 2523 p += emit_msr (p, FPCR, x0); 2524 2525 p += emit_add (p, sp, sp, immediate_operand (5 * 16)); 2526 2527 /* Pop general purpose registers: 2528 2529 LDR x0, [sp] 2530 ... 2531 LDR x30, [sp, #(30 * 16)] 2532 2533 ADD sp, sp, #(31 * 16) 2534 2535 */ 2536 for (i = 0; i <= 30; i += 1) 2537 p += emit_ldr (p, aarch64_register (i, 1), sp, 2538 offset_memory_operand (i * 16)); 2539 p += emit_add (p, sp, sp, immediate_operand (31 * 16)); 2540 2541 /* Pop SIMD&FP registers: 2542 2543 LDP q0, q1, [sp] 2544 ... 2545 LDP q30, q31, [sp, #(30 * 16)] 2546 2547 ADD sp, sp, #(32 * 16) 2548 2549 */ 2550 for (i = 0; i <= 30; i += 2) 2551 p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16); 2552 p += emit_add (p, sp, sp, immediate_operand (32 * 16)); 2553 2554 /* Write the code into the inferior memory. */ 2555 append_insns (&buildaddr, p - buf, buf); 2556 2557 /* Now emit the relocated instruction. */ 2558 *adjusted_insn_addr = buildaddr; 2559 target_read_uint32 (tpaddr, &insn); 2560 2561 insn_data.base.insn_addr = tpaddr; 2562 insn_data.new_addr = buildaddr; 2563 insn_data.insn_ptr = buf; 2564 2565 aarch64_relocate_instruction (insn, &visitor, 2566 (struct aarch64_insn_data *) &insn_data); 2567 2568 /* We may not have been able to relocate the instruction. */ 2569 if (insn_data.insn_ptr == buf) 2570 { 2571 sprintf (err, 2572 "E.Could not relocate instruction from %s to %s.", 2573 core_addr_to_string_nz (tpaddr), 2574 core_addr_to_string_nz (buildaddr)); 2575 return 1; 2576 } 2577 else 2578 append_insns (&buildaddr, insn_data.insn_ptr - buf, buf); 2579 *adjusted_insn_addr_end = buildaddr; 2580 2581 /* Go back to the start of the buffer. */ 2582 p = buf; 2583 2584 /* Emit a branch back from the jump pad. */ 2585 offset = (tpaddr + orig_size - buildaddr); 2586 if (!can_encode_int32 (offset, 28)) 2587 { 2588 sprintf (err, 2589 "E.Jump back from jump pad too far from tracepoint " 2590 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).", 2591 offset); 2592 return 1; 2593 } 2594 2595 p += emit_b (p, 0, offset); 2596 append_insns (&buildaddr, p - buf, buf); 2597 2598 /* Give the caller a branch instruction into the jump pad. */ 2599 offset = (*jump_entry - tpaddr); 2600 if (!can_encode_int32 (offset, 28)) 2601 { 2602 sprintf (err, 2603 "E.Jump pad too far from tracepoint " 2604 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).", 2605 offset); 2606 return 1; 2607 } 2608 2609 emit_b ((uint32_t *) jjump_pad_insn, 0, offset); 2610 *jjump_pad_insn_size = 4; 2611 2612 /* Return the end address of our pad. */ 2613 *jump_entry = buildaddr; 2614 2615 return 0; 2616 } 2617 2618 /* Helper function writing LEN instructions from START into 2619 current_insn_ptr. */ 2620 2621 static void 2622 emit_ops_insns (const uint32_t *start, int len) 2623 { 2624 CORE_ADDR buildaddr = current_insn_ptr; 2625 2626 threads_debug_printf ("Adding %d instructions at %s", 2627 len, paddress (buildaddr)); 2628 2629 append_insns (&buildaddr, len, start); 2630 current_insn_ptr = buildaddr; 2631 } 2632 2633 /* Pop a register from the stack. */ 2634 2635 static int 2636 emit_pop (uint32_t *buf, struct aarch64_register rt) 2637 { 2638 return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16)); 2639 } 2640 2641 /* Push a register on the stack. */ 2642 2643 static int 2644 emit_push (uint32_t *buf, struct aarch64_register rt) 2645 { 2646 return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16)); 2647 } 2648 2649 /* Implementation of emit_ops method "emit_prologue". */ 2650 2651 static void 2652 aarch64_emit_prologue (void) 2653 { 2654 uint32_t buf[16]; 2655 uint32_t *p = buf; 2656 2657 /* This function emit a prologue for the following function prototype: 2658 2659 enum eval_result_type f (unsigned char *regs, 2660 ULONGEST *value); 2661 2662 The first argument is a buffer of raw registers. The second 2663 argument is the result of 2664 evaluating the expression, which will be set to whatever is on top of 2665 the stack at the end. 2666 2667 The stack set up by the prologue is as such: 2668 2669 High *------------------------------------------------------* 2670 | LR | 2671 | FP | <- FP 2672 | x1 (ULONGEST *value) | 2673 | x0 (unsigned char *regs) | 2674 Low *------------------------------------------------------* 2675 2676 As we are implementing a stack machine, each opcode can expand the 2677 stack so we never know how far we are from the data saved by this 2678 prologue. In order to be able refer to value and regs later, we save 2679 the current stack pointer in the frame pointer. This way, it is not 2680 clobbered when calling C functions. 2681 2682 Finally, throughout every operation, we are using register x0 as the 2683 top of the stack, and x1 as a scratch register. */ 2684 2685 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16)); 2686 p += emit_str (p, lr, sp, offset_memory_operand (3 * 8)); 2687 p += emit_str (p, fp, sp, offset_memory_operand (2 * 8)); 2688 2689 p += emit_add (p, fp, sp, immediate_operand (2 * 8)); 2690 2691 2692 emit_ops_insns (buf, p - buf); 2693 } 2694 2695 /* Implementation of emit_ops method "emit_epilogue". */ 2696 2697 static void 2698 aarch64_emit_epilogue (void) 2699 { 2700 uint32_t buf[16]; 2701 uint32_t *p = buf; 2702 2703 /* Store the result of the expression (x0) in *value. */ 2704 p += emit_sub (p, x1, fp, immediate_operand (1 * 8)); 2705 p += emit_ldr (p, x1, x1, offset_memory_operand (0)); 2706 p += emit_str (p, x0, x1, offset_memory_operand (0)); 2707 2708 /* Restore the previous state. */ 2709 p += emit_add (p, sp, fp, immediate_operand (2 * 8)); 2710 p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0)); 2711 2712 /* Return expr_eval_no_error. */ 2713 p += emit_mov (p, x0, immediate_operand (expr_eval_no_error)); 2714 p += emit_ret (p, lr); 2715 2716 emit_ops_insns (buf, p - buf); 2717 } 2718 2719 /* Implementation of emit_ops method "emit_add". */ 2720 2721 static void 2722 aarch64_emit_add (void) 2723 { 2724 uint32_t buf[16]; 2725 uint32_t *p = buf; 2726 2727 p += emit_pop (p, x1); 2728 p += emit_add (p, x0, x1, register_operand (x0)); 2729 2730 emit_ops_insns (buf, p - buf); 2731 } 2732 2733 /* Implementation of emit_ops method "emit_sub". */ 2734 2735 static void 2736 aarch64_emit_sub (void) 2737 { 2738 uint32_t buf[16]; 2739 uint32_t *p = buf; 2740 2741 p += emit_pop (p, x1); 2742 p += emit_sub (p, x0, x1, register_operand (x0)); 2743 2744 emit_ops_insns (buf, p - buf); 2745 } 2746 2747 /* Implementation of emit_ops method "emit_mul". */ 2748 2749 static void 2750 aarch64_emit_mul (void) 2751 { 2752 uint32_t buf[16]; 2753 uint32_t *p = buf; 2754 2755 p += emit_pop (p, x1); 2756 p += emit_mul (p, x0, x1, x0); 2757 2758 emit_ops_insns (buf, p - buf); 2759 } 2760 2761 /* Implementation of emit_ops method "emit_lsh". */ 2762 2763 static void 2764 aarch64_emit_lsh (void) 2765 { 2766 uint32_t buf[16]; 2767 uint32_t *p = buf; 2768 2769 p += emit_pop (p, x1); 2770 p += emit_lslv (p, x0, x1, x0); 2771 2772 emit_ops_insns (buf, p - buf); 2773 } 2774 2775 /* Implementation of emit_ops method "emit_rsh_signed". */ 2776 2777 static void 2778 aarch64_emit_rsh_signed (void) 2779 { 2780 uint32_t buf[16]; 2781 uint32_t *p = buf; 2782 2783 p += emit_pop (p, x1); 2784 p += emit_asrv (p, x0, x1, x0); 2785 2786 emit_ops_insns (buf, p - buf); 2787 } 2788 2789 /* Implementation of emit_ops method "emit_rsh_unsigned". */ 2790 2791 static void 2792 aarch64_emit_rsh_unsigned (void) 2793 { 2794 uint32_t buf[16]; 2795 uint32_t *p = buf; 2796 2797 p += emit_pop (p, x1); 2798 p += emit_lsrv (p, x0, x1, x0); 2799 2800 emit_ops_insns (buf, p - buf); 2801 } 2802 2803 /* Implementation of emit_ops method "emit_ext". */ 2804 2805 static void 2806 aarch64_emit_ext (int arg) 2807 { 2808 uint32_t buf[16]; 2809 uint32_t *p = buf; 2810 2811 p += emit_sbfx (p, x0, x0, 0, arg); 2812 2813 emit_ops_insns (buf, p - buf); 2814 } 2815 2816 /* Implementation of emit_ops method "emit_log_not". */ 2817 2818 static void 2819 aarch64_emit_log_not (void) 2820 { 2821 uint32_t buf[16]; 2822 uint32_t *p = buf; 2823 2824 /* If the top of the stack is 0, replace it with 1. Else replace it with 2825 0. */ 2826 2827 p += emit_cmp (p, x0, immediate_operand (0)); 2828 p += emit_cset (p, x0, EQ); 2829 2830 emit_ops_insns (buf, p - buf); 2831 } 2832 2833 /* Implementation of emit_ops method "emit_bit_and". */ 2834 2835 static void 2836 aarch64_emit_bit_and (void) 2837 { 2838 uint32_t buf[16]; 2839 uint32_t *p = buf; 2840 2841 p += emit_pop (p, x1); 2842 p += emit_and (p, x0, x0, x1); 2843 2844 emit_ops_insns (buf, p - buf); 2845 } 2846 2847 /* Implementation of emit_ops method "emit_bit_or". */ 2848 2849 static void 2850 aarch64_emit_bit_or (void) 2851 { 2852 uint32_t buf[16]; 2853 uint32_t *p = buf; 2854 2855 p += emit_pop (p, x1); 2856 p += emit_orr (p, x0, x0, x1); 2857 2858 emit_ops_insns (buf, p - buf); 2859 } 2860 2861 /* Implementation of emit_ops method "emit_bit_xor". */ 2862 2863 static void 2864 aarch64_emit_bit_xor (void) 2865 { 2866 uint32_t buf[16]; 2867 uint32_t *p = buf; 2868 2869 p += emit_pop (p, x1); 2870 p += emit_eor (p, x0, x0, x1); 2871 2872 emit_ops_insns (buf, p - buf); 2873 } 2874 2875 /* Implementation of emit_ops method "emit_bit_not". */ 2876 2877 static void 2878 aarch64_emit_bit_not (void) 2879 { 2880 uint32_t buf[16]; 2881 uint32_t *p = buf; 2882 2883 p += emit_mvn (p, x0, x0); 2884 2885 emit_ops_insns (buf, p - buf); 2886 } 2887 2888 /* Implementation of emit_ops method "emit_equal". */ 2889 2890 static void 2891 aarch64_emit_equal (void) 2892 { 2893 uint32_t buf[16]; 2894 uint32_t *p = buf; 2895 2896 p += emit_pop (p, x1); 2897 p += emit_cmp (p, x0, register_operand (x1)); 2898 p += emit_cset (p, x0, EQ); 2899 2900 emit_ops_insns (buf, p - buf); 2901 } 2902 2903 /* Implementation of emit_ops method "emit_less_signed". */ 2904 2905 static void 2906 aarch64_emit_less_signed (void) 2907 { 2908 uint32_t buf[16]; 2909 uint32_t *p = buf; 2910 2911 p += emit_pop (p, x1); 2912 p += emit_cmp (p, x1, register_operand (x0)); 2913 p += emit_cset (p, x0, LT); 2914 2915 emit_ops_insns (buf, p - buf); 2916 } 2917 2918 /* Implementation of emit_ops method "emit_less_unsigned". */ 2919 2920 static void 2921 aarch64_emit_less_unsigned (void) 2922 { 2923 uint32_t buf[16]; 2924 uint32_t *p = buf; 2925 2926 p += emit_pop (p, x1); 2927 p += emit_cmp (p, x1, register_operand (x0)); 2928 p += emit_cset (p, x0, LO); 2929 2930 emit_ops_insns (buf, p - buf); 2931 } 2932 2933 /* Implementation of emit_ops method "emit_ref". */ 2934 2935 static void 2936 aarch64_emit_ref (int size) 2937 { 2938 uint32_t buf[16]; 2939 uint32_t *p = buf; 2940 2941 switch (size) 2942 { 2943 case 1: 2944 p += emit_ldrb (p, w0, x0, offset_memory_operand (0)); 2945 break; 2946 case 2: 2947 p += emit_ldrh (p, w0, x0, offset_memory_operand (0)); 2948 break; 2949 case 4: 2950 p += emit_ldr (p, w0, x0, offset_memory_operand (0)); 2951 break; 2952 case 8: 2953 p += emit_ldr (p, x0, x0, offset_memory_operand (0)); 2954 break; 2955 default: 2956 /* Unknown size, bail on compilation. */ 2957 emit_error = 1; 2958 break; 2959 } 2960 2961 emit_ops_insns (buf, p - buf); 2962 } 2963 2964 /* Implementation of emit_ops method "emit_if_goto". */ 2965 2966 static void 2967 aarch64_emit_if_goto (int *offset_p, int *size_p) 2968 { 2969 uint32_t buf[16]; 2970 uint32_t *p = buf; 2971 2972 /* The Z flag is set or cleared here. */ 2973 p += emit_cmp (p, x0, immediate_operand (0)); 2974 /* This instruction must not change the Z flag. */ 2975 p += emit_pop (p, x0); 2976 /* Branch over the next instruction if x0 == 0. */ 2977 p += emit_bcond (p, EQ, 8); 2978 2979 /* The NOP instruction will be patched with an unconditional branch. */ 2980 if (offset_p) 2981 *offset_p = (p - buf) * 4; 2982 if (size_p) 2983 *size_p = 4; 2984 p += emit_nop (p); 2985 2986 emit_ops_insns (buf, p - buf); 2987 } 2988 2989 /* Implementation of emit_ops method "emit_goto". */ 2990 2991 static void 2992 aarch64_emit_goto (int *offset_p, int *size_p) 2993 { 2994 uint32_t buf[16]; 2995 uint32_t *p = buf; 2996 2997 /* The NOP instruction will be patched with an unconditional branch. */ 2998 if (offset_p) 2999 *offset_p = 0; 3000 if (size_p) 3001 *size_p = 4; 3002 p += emit_nop (p); 3003 3004 emit_ops_insns (buf, p - buf); 3005 } 3006 3007 /* Implementation of emit_ops method "write_goto_address". */ 3008 3009 static void 3010 aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) 3011 { 3012 uint32_t insn; 3013 3014 emit_b (&insn, 0, to - from); 3015 append_insns (&from, 1, &insn); 3016 } 3017 3018 /* Implementation of emit_ops method "emit_const". */ 3019 3020 static void 3021 aarch64_emit_const (LONGEST num) 3022 { 3023 uint32_t buf[16]; 3024 uint32_t *p = buf; 3025 3026 p += emit_mov_addr (p, x0, num); 3027 3028 emit_ops_insns (buf, p - buf); 3029 } 3030 3031 /* Implementation of emit_ops method "emit_call". */ 3032 3033 static void 3034 aarch64_emit_call (CORE_ADDR fn) 3035 { 3036 uint32_t buf[16]; 3037 uint32_t *p = buf; 3038 3039 p += emit_mov_addr (p, ip0, fn); 3040 p += emit_blr (p, ip0); 3041 3042 emit_ops_insns (buf, p - buf); 3043 } 3044 3045 /* Implementation of emit_ops method "emit_reg". */ 3046 3047 static void 3048 aarch64_emit_reg (int reg) 3049 { 3050 uint32_t buf[16]; 3051 uint32_t *p = buf; 3052 3053 /* Set x0 to unsigned char *regs. */ 3054 p += emit_sub (p, x0, fp, immediate_operand (2 * 8)); 3055 p += emit_ldr (p, x0, x0, offset_memory_operand (0)); 3056 p += emit_mov (p, x1, immediate_operand (reg)); 3057 3058 emit_ops_insns (buf, p - buf); 3059 3060 aarch64_emit_call (get_raw_reg_func_addr ()); 3061 } 3062 3063 /* Implementation of emit_ops method "emit_pop". */ 3064 3065 static void 3066 aarch64_emit_pop (void) 3067 { 3068 uint32_t buf[16]; 3069 uint32_t *p = buf; 3070 3071 p += emit_pop (p, x0); 3072 3073 emit_ops_insns (buf, p - buf); 3074 } 3075 3076 /* Implementation of emit_ops method "emit_stack_flush". */ 3077 3078 static void 3079 aarch64_emit_stack_flush (void) 3080 { 3081 uint32_t buf[16]; 3082 uint32_t *p = buf; 3083 3084 p += emit_push (p, x0); 3085 3086 emit_ops_insns (buf, p - buf); 3087 } 3088 3089 /* Implementation of emit_ops method "emit_zero_ext". */ 3090 3091 static void 3092 aarch64_emit_zero_ext (int arg) 3093 { 3094 uint32_t buf[16]; 3095 uint32_t *p = buf; 3096 3097 p += emit_ubfx (p, x0, x0, 0, arg); 3098 3099 emit_ops_insns (buf, p - buf); 3100 } 3101 3102 /* Implementation of emit_ops method "emit_swap". */ 3103 3104 static void 3105 aarch64_emit_swap (void) 3106 { 3107 uint32_t buf[16]; 3108 uint32_t *p = buf; 3109 3110 p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16)); 3111 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16)); 3112 p += emit_mov (p, x0, register_operand (x1)); 3113 3114 emit_ops_insns (buf, p - buf); 3115 } 3116 3117 /* Implementation of emit_ops method "emit_stack_adjust". */ 3118 3119 static void 3120 aarch64_emit_stack_adjust (int n) 3121 { 3122 /* This is not needed with our design. */ 3123 uint32_t buf[16]; 3124 uint32_t *p = buf; 3125 3126 p += emit_add (p, sp, sp, immediate_operand (n * 16)); 3127 3128 emit_ops_insns (buf, p - buf); 3129 } 3130 3131 /* Implementation of emit_ops method "emit_int_call_1". */ 3132 3133 static void 3134 aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1) 3135 { 3136 uint32_t buf[16]; 3137 uint32_t *p = buf; 3138 3139 p += emit_mov (p, x0, immediate_operand (arg1)); 3140 3141 emit_ops_insns (buf, p - buf); 3142 3143 aarch64_emit_call (fn); 3144 } 3145 3146 /* Implementation of emit_ops method "emit_void_call_2". */ 3147 3148 static void 3149 aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1) 3150 { 3151 uint32_t buf[16]; 3152 uint32_t *p = buf; 3153 3154 /* Push x0 on the stack. */ 3155 aarch64_emit_stack_flush (); 3156 3157 /* Setup arguments for the function call: 3158 3159 x0: arg1 3160 x1: top of the stack 3161 3162 MOV x1, x0 3163 MOV x0, #arg1 */ 3164 3165 p += emit_mov (p, x1, register_operand (x0)); 3166 p += emit_mov (p, x0, immediate_operand (arg1)); 3167 3168 emit_ops_insns (buf, p - buf); 3169 3170 aarch64_emit_call (fn); 3171 3172 /* Restore x0. */ 3173 aarch64_emit_pop (); 3174 } 3175 3176 /* Implementation of emit_ops method "emit_eq_goto". */ 3177 3178 static void 3179 aarch64_emit_eq_goto (int *offset_p, int *size_p) 3180 { 3181 uint32_t buf[16]; 3182 uint32_t *p = buf; 3183 3184 p += emit_pop (p, x1); 3185 p += emit_cmp (p, x1, register_operand (x0)); 3186 /* Branch over the next instruction if x0 != x1. */ 3187 p += emit_bcond (p, NE, 8); 3188 /* The NOP instruction will be patched with an unconditional branch. */ 3189 if (offset_p) 3190 *offset_p = (p - buf) * 4; 3191 if (size_p) 3192 *size_p = 4; 3193 p += emit_nop (p); 3194 3195 emit_ops_insns (buf, p - buf); 3196 } 3197 3198 /* Implementation of emit_ops method "emit_ne_goto". */ 3199 3200 static void 3201 aarch64_emit_ne_goto (int *offset_p, int *size_p) 3202 { 3203 uint32_t buf[16]; 3204 uint32_t *p = buf; 3205 3206 p += emit_pop (p, x1); 3207 p += emit_cmp (p, x1, register_operand (x0)); 3208 /* Branch over the next instruction if x0 == x1. */ 3209 p += emit_bcond (p, EQ, 8); 3210 /* The NOP instruction will be patched with an unconditional branch. */ 3211 if (offset_p) 3212 *offset_p = (p - buf) * 4; 3213 if (size_p) 3214 *size_p = 4; 3215 p += emit_nop (p); 3216 3217 emit_ops_insns (buf, p - buf); 3218 } 3219 3220 /* Implementation of emit_ops method "emit_lt_goto". */ 3221 3222 static void 3223 aarch64_emit_lt_goto (int *offset_p, int *size_p) 3224 { 3225 uint32_t buf[16]; 3226 uint32_t *p = buf; 3227 3228 p += emit_pop (p, x1); 3229 p += emit_cmp (p, x1, register_operand (x0)); 3230 /* Branch over the next instruction if x0 >= x1. */ 3231 p += emit_bcond (p, GE, 8); 3232 /* The NOP instruction will be patched with an unconditional branch. */ 3233 if (offset_p) 3234 *offset_p = (p - buf) * 4; 3235 if (size_p) 3236 *size_p = 4; 3237 p += emit_nop (p); 3238 3239 emit_ops_insns (buf, p - buf); 3240 } 3241 3242 /* Implementation of emit_ops method "emit_le_goto". */ 3243 3244 static void 3245 aarch64_emit_le_goto (int *offset_p, int *size_p) 3246 { 3247 uint32_t buf[16]; 3248 uint32_t *p = buf; 3249 3250 p += emit_pop (p, x1); 3251 p += emit_cmp (p, x1, register_operand (x0)); 3252 /* Branch over the next instruction if x0 > x1. */ 3253 p += emit_bcond (p, GT, 8); 3254 /* The NOP instruction will be patched with an unconditional branch. */ 3255 if (offset_p) 3256 *offset_p = (p - buf) * 4; 3257 if (size_p) 3258 *size_p = 4; 3259 p += emit_nop (p); 3260 3261 emit_ops_insns (buf, p - buf); 3262 } 3263 3264 /* Implementation of emit_ops method "emit_gt_goto". */ 3265 3266 static void 3267 aarch64_emit_gt_goto (int *offset_p, int *size_p) 3268 { 3269 uint32_t buf[16]; 3270 uint32_t *p = buf; 3271 3272 p += emit_pop (p, x1); 3273 p += emit_cmp (p, x1, register_operand (x0)); 3274 /* Branch over the next instruction if x0 <= x1. */ 3275 p += emit_bcond (p, LE, 8); 3276 /* The NOP instruction will be patched with an unconditional branch. */ 3277 if (offset_p) 3278 *offset_p = (p - buf) * 4; 3279 if (size_p) 3280 *size_p = 4; 3281 p += emit_nop (p); 3282 3283 emit_ops_insns (buf, p - buf); 3284 } 3285 3286 /* Implementation of emit_ops method "emit_ge_got". */ 3287 3288 static void 3289 aarch64_emit_ge_got (int *offset_p, int *size_p) 3290 { 3291 uint32_t buf[16]; 3292 uint32_t *p = buf; 3293 3294 p += emit_pop (p, x1); 3295 p += emit_cmp (p, x1, register_operand (x0)); 3296 /* Branch over the next instruction if x0 <= x1. */ 3297 p += emit_bcond (p, LT, 8); 3298 /* The NOP instruction will be patched with an unconditional branch. */ 3299 if (offset_p) 3300 *offset_p = (p - buf) * 4; 3301 if (size_p) 3302 *size_p = 4; 3303 p += emit_nop (p); 3304 3305 emit_ops_insns (buf, p - buf); 3306 } 3307 3308 static struct emit_ops aarch64_emit_ops_impl = 3309 { 3310 aarch64_emit_prologue, 3311 aarch64_emit_epilogue, 3312 aarch64_emit_add, 3313 aarch64_emit_sub, 3314 aarch64_emit_mul, 3315 aarch64_emit_lsh, 3316 aarch64_emit_rsh_signed, 3317 aarch64_emit_rsh_unsigned, 3318 aarch64_emit_ext, 3319 aarch64_emit_log_not, 3320 aarch64_emit_bit_and, 3321 aarch64_emit_bit_or, 3322 aarch64_emit_bit_xor, 3323 aarch64_emit_bit_not, 3324 aarch64_emit_equal, 3325 aarch64_emit_less_signed, 3326 aarch64_emit_less_unsigned, 3327 aarch64_emit_ref, 3328 aarch64_emit_if_goto, 3329 aarch64_emit_goto, 3330 aarch64_write_goto_address, 3331 aarch64_emit_const, 3332 aarch64_emit_call, 3333 aarch64_emit_reg, 3334 aarch64_emit_pop, 3335 aarch64_emit_stack_flush, 3336 aarch64_emit_zero_ext, 3337 aarch64_emit_swap, 3338 aarch64_emit_stack_adjust, 3339 aarch64_emit_int_call_1, 3340 aarch64_emit_void_call_2, 3341 aarch64_emit_eq_goto, 3342 aarch64_emit_ne_goto, 3343 aarch64_emit_lt_goto, 3344 aarch64_emit_le_goto, 3345 aarch64_emit_gt_goto, 3346 aarch64_emit_ge_got, 3347 }; 3348 3349 /* Implementation of target ops method "emit_ops". */ 3350 3351 emit_ops * 3352 aarch64_target::emit_ops () 3353 { 3354 return &aarch64_emit_ops_impl; 3355 } 3356 3357 /* Implementation of target ops method 3358 "get_min_fast_tracepoint_insn_len". */ 3359 3360 int 3361 aarch64_target::get_min_fast_tracepoint_insn_len () 3362 { 3363 return 4; 3364 } 3365 3366 /* Implementation of linux target ops method "low_supports_range_stepping". */ 3367 3368 bool 3369 aarch64_target::low_supports_range_stepping () 3370 { 3371 return true; 3372 } 3373 3374 /* Implementation of target ops method "sw_breakpoint_from_kind". */ 3375 3376 const gdb_byte * 3377 aarch64_target::sw_breakpoint_from_kind (int kind, int *size) 3378 { 3379 if (is_64bit_tdesc ()) 3380 { 3381 *size = aarch64_breakpoint_len; 3382 return aarch64_breakpoint; 3383 } 3384 else 3385 return arm_sw_breakpoint_from_kind (kind, size); 3386 } 3387 3388 /* Implementation of target ops method "breakpoint_kind_from_pc". */ 3389 3390 int 3391 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) 3392 { 3393 if (is_64bit_tdesc ()) 3394 return aarch64_breakpoint_len; 3395 else 3396 return arm_breakpoint_kind_from_pc (pcptr); 3397 } 3398 3399 /* Implementation of the target ops method 3400 "breakpoint_kind_from_current_state". */ 3401 3402 int 3403 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) 3404 { 3405 if (is_64bit_tdesc ()) 3406 return aarch64_breakpoint_len; 3407 else 3408 return arm_breakpoint_kind_from_current_state (pcptr); 3409 } 3410 3411 /* Returns true if memory tagging is supported. */ 3412 bool 3413 aarch64_target::supports_memory_tagging () 3414 { 3415 if (current_thread == NULL) 3416 { 3417 /* We don't have any processes running, so don't attempt to 3418 use linux_get_hwcap2 as it will try to fetch the current 3419 thread id. Instead, just fetch the auxv from the self 3420 PID. */ 3421 #ifdef HAVE_GETAUXVAL 3422 return (getauxval (AT_HWCAP2) & HWCAP2_MTE) != 0; 3423 #else 3424 return true; 3425 #endif 3426 } 3427 3428 return (linux_get_hwcap2 (current_thread->id.pid (), 8) & HWCAP2_MTE) != 0; 3429 } 3430 3431 bool 3432 aarch64_target::fetch_memtags (CORE_ADDR address, size_t len, 3433 gdb::byte_vector &tags, int type) 3434 { 3435 /* Allocation tags are per-process, so any tid is fine. */ 3436 int tid = lwpid_of (current_thread); 3437 3438 /* Allocation tag? */ 3439 if (type == static_cast <int> (aarch64_memtag_type::mte_allocation)) 3440 return aarch64_mte_fetch_memtags (tid, address, len, tags); 3441 3442 return false; 3443 } 3444 3445 bool 3446 aarch64_target::store_memtags (CORE_ADDR address, size_t len, 3447 const gdb::byte_vector &tags, int type) 3448 { 3449 /* Allocation tags are per-process, so any tid is fine. */ 3450 int tid = lwpid_of (current_thread); 3451 3452 /* Allocation tag? */ 3453 if (type == static_cast <int> (aarch64_memtag_type::mte_allocation)) 3454 return aarch64_mte_store_memtags (tid, address, len, tags); 3455 3456 return false; 3457 } 3458 3459 /* The linux target ops object. */ 3460 3461 linux_process_target *the_linux_target = &the_aarch64_target; 3462 3463 void 3464 initialize_low_arch (void) 3465 { 3466 initialize_low_arch_aarch32 (); 3467 3468 initialize_regsets_info (&aarch64_regsets_info); 3469 } 3470
Indexes created Sun Mar 01 05:31:48 UTC 2026