linux-aarch64-low.cc revision 1.1.1.4
1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for 2 GDB. 3 4 Copyright (C) 2009-2024 Free Software Foundation, Inc. 5 Contributed by ARM Ltd. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "linux-low.h" 23 #include "nat/aarch64-linux.h" 24 #include "nat/aarch64-linux-hw-point.h" 25 #include "arch/aarch64-insn.h" 26 #include "linux-aarch32-low.h" 27 #include "elf/common.h" 28 #include "ax.h" 29 #include "tracepoint.h" 30 #include "debug.h" 31 32 #include <signal.h> 33 #include <sys/user.h> 34 #include "nat/gdb_ptrace.h" 35 #include <asm/ptrace.h> 36 #include <inttypes.h> 37 #include <endian.h> 38 #include <sys/uio.h> 39 40 #include "gdb_proc_service.h" 41 #include "arch/aarch64.h" 42 #include "arch/aarch64-mte-linux.h" 43 #include "arch/aarch64-scalable-linux.h" 44 #include "linux-aarch32-tdesc.h" 45 #include "linux-aarch64-tdesc.h" 46 #include "nat/aarch64-mte-linux-ptrace.h" 47 #include "nat/aarch64-scalable-linux-ptrace.h" 48 #include "tdesc.h" 49 50 #ifdef HAVE_SYS_REG_H 51 #include <sys/reg.h> 52 #endif 53 54 #ifdef HAVE_GETAUXVAL 55 #include <sys/auxv.h> 56 #endif 57 58 /* Linux target op definitions for the AArch64 architecture. */ 59 60 class aarch64_target : public linux_process_target 61 { 62 public: 63 64 const regs_info *get_regs_info () override; 65 66 int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; 67 68 int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; 69 70 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; 71 72 bool supports_z_point_type (char z_type) override; 73 74 bool supports_tracepoints () override; 75 76 bool supports_fast_tracepoints () override; 77 78 int install_fast_tracepoint_jump_pad 79 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 80 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 81 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 82 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 83 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 84 char *err) override; 85 86 int get_min_fast_tracepoint_insn_len () override; 87 88 struct emit_ops *emit_ops () override; 89 90 bool supports_memory_tagging () override; 91 92 bool fetch_memtags (CORE_ADDR address, size_t len, 93 gdb::byte_vector &tags, int type) override; 94 95 bool store_memtags (CORE_ADDR address, size_t len, 96 const gdb::byte_vector &tags, int type) override; 97 98 protected: 99 100 void low_arch_setup () override; 101 102 bool low_cannot_fetch_register (int regno) override; 103 104 bool low_cannot_store_register (int regno) override; 105 106 bool low_supports_breakpoints () override; 107 108 CORE_ADDR low_get_pc (regcache *regcache) override; 109 110 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; 111 112 bool low_breakpoint_at (CORE_ADDR pc) override; 113 114 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 115 int size, raw_breakpoint *bp) override; 116 117 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 118 int size, raw_breakpoint *bp) override; 119 120 bool low_stopped_by_watchpoint () override; 121 122 CORE_ADDR low_stopped_data_address () override; 123 124 bool low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, 125 int direction) override; 126 127 arch_process_info *low_new_process () override; 128 129 void low_delete_process (arch_process_info *info) override; 130 131 void low_new_thread (lwp_info *) override; 132 133 void low_delete_thread (arch_lwp_info *) override; 134 135 void low_new_fork (process_info *parent, process_info *child) override; 136 137 void low_prepare_to_resume (lwp_info *lwp) override; 138 139 int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override; 140 141 bool low_supports_range_stepping () override; 142 143 bool low_supports_catch_syscall () override; 144 145 void low_get_syscall_trapinfo (regcache *regcache, int *sysno) override; 146 }; 147 148 /* The singleton target ops object. */ 149 150 static aarch64_target the_aarch64_target; 151 152 bool 153 aarch64_target::low_cannot_fetch_register (int regno) 154 { 155 gdb_assert_not_reached ("linux target op low_cannot_fetch_register " 156 "is not implemented by the target"); 157 } 158 159 bool 160 aarch64_target::low_cannot_store_register (int regno) 161 { 162 gdb_assert_not_reached ("linux target op low_cannot_store_register " 163 "is not implemented by the target"); 164 } 165 166 void 167 aarch64_target::low_prepare_to_resume (lwp_info *lwp) 168 { 169 aarch64_linux_prepare_to_resume (lwp); 170 } 171 172 /* Per-process arch-specific data we want to keep. */ 173 174 struct arch_process_info 175 { 176 /* Hardware breakpoint/watchpoint data. 177 The reason for them to be per-process rather than per-thread is 178 due to the lack of information in the gdbserver environment; 179 gdbserver is not told that whether a requested hardware 180 breakpoint/watchpoint is thread specific or not, so it has to set 181 each hw bp/wp for every thread in the current process. The 182 higher level bp/wp management in gdb will resume a thread if a hw 183 bp/wp trap is not expected for it. Since the hw bp/wp setting is 184 same for each thread, it is reasonable for the data to live here. 185 */ 186 struct aarch64_debug_reg_state debug_reg_state; 187 }; 188 189 /* Return true if the size of register 0 is 8 byte. */ 190 191 static int 192 is_64bit_tdesc (void) 193 { 194 /* We may not have a current thread at this point, so go straight to 195 the process's target description. */ 196 return register_size (current_process ()->tdesc, 0) == 8; 197 } 198 199 static void 200 aarch64_fill_gregset (struct regcache *regcache, void *buf) 201 { 202 struct user_pt_regs *regset = (struct user_pt_regs *) buf; 203 int i; 204 205 for (i = 0; i < AARCH64_X_REGS_NUM; i++) 206 collect_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]); 207 collect_register (regcache, AARCH64_SP_REGNUM, ®set->sp); 208 collect_register (regcache, AARCH64_PC_REGNUM, ®set->pc); 209 collect_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate); 210 } 211 212 static void 213 aarch64_store_gregset (struct regcache *regcache, const void *buf) 214 { 215 const struct user_pt_regs *regset = (const struct user_pt_regs *) buf; 216 int i; 217 218 for (i = 0; i < AARCH64_X_REGS_NUM; i++) 219 supply_register (regcache, AARCH64_X0_REGNUM + i, ®set->regs[i]); 220 supply_register (regcache, AARCH64_SP_REGNUM, ®set->sp); 221 supply_register (regcache, AARCH64_PC_REGNUM, ®set->pc); 222 supply_register (regcache, AARCH64_CPSR_REGNUM, ®set->pstate); 223 } 224 225 static void 226 aarch64_fill_fpregset (struct regcache *regcache, void *buf) 227 { 228 struct user_fpsimd_state *regset = (struct user_fpsimd_state *) buf; 229 int i; 230 231 for (i = 0; i < AARCH64_V_REGS_NUM; i++) 232 collect_register (regcache, AARCH64_V0_REGNUM + i, ®set->vregs[i]); 233 collect_register (regcache, AARCH64_FPSR_REGNUM, ®set->fpsr); 234 collect_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr); 235 } 236 237 static void 238 aarch64_store_fpregset (struct regcache *regcache, const void *buf) 239 { 240 const struct user_fpsimd_state *regset 241 = (const struct user_fpsimd_state *) buf; 242 int i; 243 244 for (i = 0; i < AARCH64_V_REGS_NUM; i++) 245 supply_register (regcache, AARCH64_V0_REGNUM + i, ®set->vregs[i]); 246 supply_register (regcache, AARCH64_FPSR_REGNUM, ®set->fpsr); 247 supply_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr); 248 } 249 250 /* Store the pauth registers to regcache. */ 251 252 static void 253 aarch64_store_pauthregset (struct regcache *regcache, const void *buf) 254 { 255 uint64_t *pauth_regset = (uint64_t *) buf; 256 int pauth_base = find_regno (regcache->tdesc, "pauth_dmask"); 257 258 if (pauth_base == 0) 259 return; 260 261 supply_register (regcache, AARCH64_PAUTH_DMASK_REGNUM (pauth_base), 262 &pauth_regset[0]); 263 supply_register (regcache, AARCH64_PAUTH_CMASK_REGNUM (pauth_base), 264 &pauth_regset[1]); 265 } 266 267 /* Fill BUF with the MTE registers from the regcache. */ 268 269 static void 270 aarch64_fill_mteregset (struct regcache *regcache, void *buf) 271 { 272 uint64_t *mte_regset = (uint64_t *) buf; 273 int mte_base = find_regno (regcache->tdesc, "tag_ctl"); 274 275 collect_register (regcache, mte_base, mte_regset); 276 } 277 278 /* Store the MTE registers to regcache. */ 279 280 static void 281 aarch64_store_mteregset (struct regcache *regcache, const void *buf) 282 { 283 uint64_t *mte_regset = (uint64_t *) buf; 284 int mte_base = find_regno (regcache->tdesc, "tag_ctl"); 285 286 /* Tag Control register */ 287 supply_register (regcache, mte_base, mte_regset); 288 } 289 290 /* Fill BUF with TLS register from the regcache. */ 291 292 static void 293 aarch64_fill_tlsregset (struct regcache *regcache, void *buf) 294 { 295 gdb_byte *tls_buf = (gdb_byte *) buf; 296 int tls_regnum = find_regno (regcache->tdesc, "tpidr"); 297 298 collect_register (regcache, tls_regnum, tls_buf); 299 300 /* Read TPIDR2, if it exists. */ 301 std::optional<int> regnum = find_regno_no_throw (regcache->tdesc, "tpidr2"); 302 303 if (regnum.has_value ()) 304 collect_register (regcache, *regnum, tls_buf + sizeof (uint64_t)); 305 } 306 307 /* Store TLS register to regcache. */ 308 309 static void 310 aarch64_store_tlsregset (struct regcache *regcache, const void *buf) 311 { 312 gdb_byte *tls_buf = (gdb_byte *) buf; 313 int tls_regnum = find_regno (regcache->tdesc, "tpidr"); 314 315 supply_register (regcache, tls_regnum, tls_buf); 316 317 /* Write TPIDR2, if it exists. */ 318 std::optional<int> regnum = find_regno_no_throw (regcache->tdesc, "tpidr2"); 319 320 if (regnum.has_value ()) 321 supply_register (regcache, *regnum, tls_buf + sizeof (uint64_t)); 322 } 323 324 bool 325 aarch64_target::low_supports_breakpoints () 326 { 327 return true; 328 } 329 330 /* Implementation of linux target ops method "low_get_pc". */ 331 332 CORE_ADDR 333 aarch64_target::low_get_pc (regcache *regcache) 334 { 335 if (register_size (regcache->tdesc, 0) == 8) 336 return linux_get_pc_64bit (regcache); 337 else 338 return linux_get_pc_32bit (regcache); 339 } 340 341 /* Implementation of linux target ops method "low_set_pc". */ 342 343 void 344 aarch64_target::low_set_pc (regcache *regcache, CORE_ADDR pc) 345 { 346 if (register_size (regcache->tdesc, 0) == 8) 347 linux_set_pc_64bit (regcache, pc); 348 else 349 linux_set_pc_32bit (regcache, pc); 350 } 351 352 #define aarch64_breakpoint_len 4 353 354 /* AArch64 BRK software debug mode instruction. 355 This instruction needs to match gdb/aarch64-tdep.c 356 (aarch64_default_breakpoint). */ 357 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; 358 359 /* Implementation of linux target ops method "low_breakpoint_at". */ 360 361 bool 362 aarch64_target::low_breakpoint_at (CORE_ADDR where) 363 { 364 if (is_64bit_tdesc ()) 365 { 366 gdb_byte insn[aarch64_breakpoint_len]; 367 368 read_memory (where, (unsigned char *) &insn, aarch64_breakpoint_len); 369 if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0) 370 return true; 371 372 return false; 373 } 374 else 375 return arm_breakpoint_at (where); 376 } 377 378 static void 379 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) 380 { 381 int i; 382 383 for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) 384 { 385 state->dr_addr_bp[i] = 0; 386 state->dr_ctrl_bp[i] = 0; 387 state->dr_ref_count_bp[i] = 0; 388 } 389 390 for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) 391 { 392 state->dr_addr_wp[i] = 0; 393 state->dr_ctrl_wp[i] = 0; 394 state->dr_ref_count_wp[i] = 0; 395 } 396 } 397 398 /* Return the pointer to the debug register state structure in the 399 current process' arch-specific data area. */ 400 401 struct aarch64_debug_reg_state * 402 aarch64_get_debug_reg_state (pid_t pid) 403 { 404 struct process_info *proc = find_process_pid (pid); 405 406 return &proc->priv->arch_private->debug_reg_state; 407 } 408 409 /* Implementation of target ops method "supports_z_point_type". */ 410 411 bool 412 aarch64_target::supports_z_point_type (char z_type) 413 { 414 switch (z_type) 415 { 416 case Z_PACKET_SW_BP: 417 case Z_PACKET_HW_BP: 418 case Z_PACKET_WRITE_WP: 419 case Z_PACKET_READ_WP: 420 case Z_PACKET_ACCESS_WP: 421 return true; 422 default: 423 return false; 424 } 425 } 426 427 /* Implementation of linux target ops method "low_insert_point". 428 429 It actually only records the info of the to-be-inserted bp/wp; 430 the actual insertion will happen when threads are resumed. */ 431 432 int 433 aarch64_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 434 int len, raw_breakpoint *bp) 435 { 436 int ret; 437 enum target_hw_bp_type targ_type; 438 struct aarch64_debug_reg_state *state 439 = aarch64_get_debug_reg_state (current_thread->id.pid ()); 440 441 if (show_debug_regs) 442 fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n", 443 (unsigned long) addr, len); 444 445 /* Determine the type from the raw breakpoint type. */ 446 targ_type = raw_bkpt_type_to_target_hw_bp_type (type); 447 448 if (targ_type != hw_execute) 449 { 450 if (aarch64_region_ok_for_watchpoint (addr, len)) 451 ret = aarch64_handle_watchpoint (targ_type, addr, len, 452 1 /* is_insert */, 453 current_lwp_ptid (), state); 454 else 455 ret = -1; 456 } 457 else 458 { 459 if (len == 3) 460 { 461 /* LEN is 3 means the breakpoint is set on a 32-bit thumb 462 instruction. Set it to 2 to correctly encode length bit 463 mask in hardware/watchpoint control register. */ 464 len = 2; 465 } 466 ret = aarch64_handle_breakpoint (targ_type, addr, len, 467 1 /* is_insert */, current_lwp_ptid (), 468 state); 469 } 470 471 if (show_debug_regs) 472 aarch64_show_debug_reg_state (state, "insert_point", addr, len, 473 targ_type); 474 475 return ret; 476 } 477 478 /* Implementation of linux target ops method "low_remove_point". 479 480 It actually only records the info of the to-be-removed bp/wp, 481 the actual removal will be done when threads are resumed. */ 482 483 int 484 aarch64_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 485 int len, raw_breakpoint *bp) 486 { 487 int ret; 488 enum target_hw_bp_type targ_type; 489 struct aarch64_debug_reg_state *state 490 = aarch64_get_debug_reg_state (current_thread->id.pid ()); 491 492 if (show_debug_regs) 493 fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n", 494 (unsigned long) addr, len); 495 496 /* Determine the type from the raw breakpoint type. */ 497 targ_type = raw_bkpt_type_to_target_hw_bp_type (type); 498 499 /* Set up state pointers. */ 500 if (targ_type != hw_execute) 501 ret = 502 aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */, 503 current_lwp_ptid (), state); 504 else 505 { 506 if (len == 3) 507 { 508 /* LEN is 3 means the breakpoint is set on a 32-bit thumb 509 instruction. Set it to 2 to correctly encode length bit 510 mask in hardware/watchpoint control register. */ 511 len = 2; 512 } 513 ret = aarch64_handle_breakpoint (targ_type, addr, len, 514 0 /* is_insert */, current_lwp_ptid (), 515 state); 516 } 517 518 if (show_debug_regs) 519 aarch64_show_debug_reg_state (state, "remove_point", addr, len, 520 targ_type); 521 522 return ret; 523 } 524 525 static CORE_ADDR 526 aarch64_remove_non_address_bits (CORE_ADDR pointer) 527 { 528 /* By default, we assume TBI and discard the top 8 bits plus the 529 VA range select bit (55). */ 530 CORE_ADDR mask = AARCH64_TOP_BITS_MASK; 531 532 /* Check if PAC is available for this target. */ 533 if (tdesc_contains_feature (current_process ()->tdesc, 534 "org.gnu.gdb.aarch64.pauth")) 535 { 536 /* Fetch the PAC masks. These masks are per-process, so we can just 537 fetch data from whatever thread we have at the moment. 538 539 Also, we have both a code mask and a data mask. For now they are the 540 same, but this may change in the future. */ 541 542 struct regcache *regs = get_thread_regcache (current_thread, 1); 543 CORE_ADDR dmask = regcache_raw_get_unsigned_by_name (regs, "pauth_dmask"); 544 CORE_ADDR cmask = regcache_raw_get_unsigned_by_name (regs, "pauth_cmask"); 545 mask |= aarch64_mask_from_pac_registers (cmask, dmask); 546 } 547 548 return aarch64_remove_top_bits (pointer, mask); 549 } 550 551 /* Implementation of linux target ops method "low_stopped_data_address". */ 552 553 CORE_ADDR 554 aarch64_target::low_stopped_data_address () 555 { 556 siginfo_t siginfo; 557 struct aarch64_debug_reg_state *state; 558 int pid = current_thread->id.lwp (); 559 560 /* Get the siginfo. */ 561 if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) 562 return (CORE_ADDR) 0; 563 564 /* Need to be a hardware breakpoint/watchpoint trap. */ 565 if (siginfo.si_signo != SIGTRAP 566 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) 567 return (CORE_ADDR) 0; 568 569 /* Make sure to ignore the top byte, otherwise we may not recognize a 570 hardware watchpoint hit. The stopped data addresses coming from the 571 kernel can potentially be tagged addresses. */ 572 const CORE_ADDR addr_trap 573 = aarch64_remove_non_address_bits ((CORE_ADDR) siginfo.si_addr); 574 575 /* Check if the address matches any watched address. */ 576 state = aarch64_get_debug_reg_state (current_thread->id.pid ()); 577 CORE_ADDR result; 578 if (aarch64_stopped_data_address (state, addr_trap, &result)) 579 return result; 580 581 return (CORE_ADDR) 0; 582 } 583 584 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */ 585 586 bool 587 aarch64_target::low_stopped_by_watchpoint () 588 { 589 return (low_stopped_data_address () != 0); 590 } 591 592 /* Fetch the thread-local storage pointer for libthread_db. */ 593 594 ps_err_e 595 ps_get_thread_area (struct ps_prochandle *ph, 596 lwpid_t lwpid, int idx, void **base) 597 { 598 return aarch64_ps_get_thread_area (ph, lwpid, idx, base, 599 is_64bit_tdesc ()); 600 } 601 602 /* Implementation of linux target ops method "low_siginfo_fixup". */ 603 604 bool 605 aarch64_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, 606 int direction) 607 { 608 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ 609 if (!is_64bit_tdesc ()) 610 { 611 if (direction == 0) 612 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, 613 native); 614 else 615 aarch64_siginfo_from_compat_siginfo (native, 616 (struct compat_siginfo *) inf); 617 618 return true; 619 } 620 621 return false; 622 } 623 624 /* Implementation of linux target ops method "low_new_process". */ 625 626 arch_process_info * 627 aarch64_target::low_new_process () 628 { 629 struct arch_process_info *info = XCNEW (struct arch_process_info); 630 631 aarch64_init_debug_reg_state (&info->debug_reg_state); 632 633 return info; 634 } 635 636 /* Implementation of linux target ops method "low_delete_process". */ 637 638 void 639 aarch64_target::low_delete_process (arch_process_info *info) 640 { 641 xfree (info); 642 } 643 644 void 645 aarch64_target::low_new_thread (lwp_info *lwp) 646 { 647 aarch64_linux_new_thread (lwp); 648 } 649 650 void 651 aarch64_target::low_delete_thread (arch_lwp_info *arch_lwp) 652 { 653 aarch64_linux_delete_thread (arch_lwp); 654 } 655 656 /* Implementation of linux target ops method "low_new_fork". */ 657 658 void 659 aarch64_target::low_new_fork (process_info *parent, 660 process_info *child) 661 { 662 /* These are allocated by linux_add_process. */ 663 gdb_assert (parent->priv != NULL 664 && parent->priv->arch_private != NULL); 665 gdb_assert (child->priv != NULL 666 && child->priv->arch_private != NULL); 667 668 /* Linux kernel before 2.6.33 commit 669 72f674d203cd230426437cdcf7dd6f681dad8b0d 670 will inherit hardware debug registers from parent 671 on fork/vfork/clone. Newer Linux kernels create such tasks with 672 zeroed debug registers. 673 674 GDB core assumes the child inherits the watchpoints/hw 675 breakpoints of the parent, and will remove them all from the 676 forked off process. Copy the debug registers mirrors into the 677 new process so that all breakpoints and watchpoints can be 678 removed together. The debug registers mirror will become zeroed 679 in the end before detaching the forked off process, thus making 680 this compatible with older Linux kernels too. */ 681 682 *child->priv->arch_private = *parent->priv->arch_private; 683 } 684 685 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */ 686 687 static void 688 aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, 689 ATTRIBUTE_UNUSED const void *buf) 690 { 691 /* BUF is unused here since we collect the data straight from a ptrace 692 request in aarch64_sve_regs_copy_to_reg_buf, therefore bypassing 693 gdbserver's own call to ptrace. */ 694 695 int tid = current_thread->id.lwp (); 696 697 /* Update the register cache. aarch64_sve_regs_copy_to_reg_buf handles 698 fetching the NT_ARM_SVE state from thread TID. */ 699 aarch64_sve_regs_copy_to_reg_buf (tid, regcache); 700 } 701 702 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */ 703 704 static void 705 aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf) 706 { 707 int tid = current_thread->id.lwp (); 708 709 /* Update the thread SVE state. aarch64_sve_regs_copy_from_reg_buf 710 handles writing the SVE/FPSIMD state back to thread TID. */ 711 aarch64_sve_regs_copy_from_reg_buf (tid, regcache); 712 713 /* We need to return the expected data in BUF, so copy whatever the kernel 714 already has to BUF. */ 715 gdb::byte_vector sve_state = aarch64_fetch_sve_regset (tid); 716 memcpy (buf, sve_state.data (), sve_state.size ()); 717 } 718 719 /* Wrapper for aarch64_za_regs_copy_to_reg_buf, to help copying NT_ARM_ZA 720 state from the thread (BUF) to the register cache. */ 721 722 static void 723 aarch64_za_regs_copy_to_regcache (struct regcache *regcache, 724 ATTRIBUTE_UNUSED const void *buf) 725 { 726 /* BUF is unused here since we collect the data straight from a ptrace 727 request, therefore bypassing gdbserver's own call to ptrace. */ 728 int tid = current_thread->id.lwp (); 729 730 int za_regnum = find_regno (regcache->tdesc, "za"); 731 int svg_regnum = find_regno (regcache->tdesc, "svg"); 732 int svcr_regnum = find_regno (regcache->tdesc, "svcr"); 733 734 /* Update the register cache. aarch64_za_regs_copy_to_reg_buf handles 735 fetching the NT_ARM_ZA state from thread TID. */ 736 aarch64_za_regs_copy_to_reg_buf (tid, regcache, za_regnum, svg_regnum, 737 svcr_regnum); 738 } 739 740 /* Wrapper for aarch64_za_regs_copy_from_reg_buf, to help copying NT_ARM_ZA 741 state from the register cache to the thread (BUF). */ 742 743 static void 744 aarch64_za_regs_copy_from_regcache (struct regcache *regcache, void *buf) 745 { 746 int tid = current_thread->id.lwp (); 747 748 int za_regnum = find_regno (regcache->tdesc, "za"); 749 int svg_regnum = find_regno (regcache->tdesc, "svg"); 750 int svcr_regnum = find_regno (regcache->tdesc, "svcr"); 751 752 /* Update the thread NT_ARM_ZA state. aarch64_za_regs_copy_from_reg_buf 753 handles writing the ZA state back to thread TID. */ 754 aarch64_za_regs_copy_from_reg_buf (tid, regcache, za_regnum, svg_regnum, 755 svcr_regnum); 756 757 /* We need to return the expected data in BUF, so copy whatever the kernel 758 already has to BUF. */ 759 760 /* Obtain a dump of ZA from ptrace. */ 761 gdb::byte_vector za_state = aarch64_fetch_za_regset (tid); 762 memcpy (buf, za_state.data (), za_state.size ()); 763 } 764 765 /* Wrapper for aarch64_zt_regs_copy_to_reg_buf, to help copying NT_ARM_ZT 766 state from the thread (BUF) to the register cache. */ 767 768 static void 769 aarch64_zt_regs_copy_to_regcache (struct regcache *regcache, 770 ATTRIBUTE_UNUSED const void *buf) 771 { 772 /* BUF is unused here since we collect the data straight from a ptrace 773 request, therefore bypassing gdbserver's own call to ptrace. */ 774 int tid = current_thread->id.lwp (); 775 776 int zt_regnum = find_regno (regcache->tdesc, "zt0"); 777 778 /* Update the register cache. aarch64_zt_regs_copy_to_reg_buf handles 779 fetching the NT_ARM_ZT state from thread TID. */ 780 aarch64_zt_regs_copy_to_reg_buf (tid, regcache, zt_regnum); 781 } 782 783 /* Wrapper for aarch64_zt_regs_copy_from_reg_buf, to help copying NT_ARM_ZT 784 state from the register cache to the thread (BUF). */ 785 786 static void 787 aarch64_zt_regs_copy_from_regcache (struct regcache *regcache, void *buf) 788 { 789 int tid = current_thread->id.lwp (); 790 791 int zt_regnum = find_regno (regcache->tdesc, "zt0"); 792 793 /* Update the thread NT_ARM_ZT state. aarch64_zt_regs_copy_from_reg_buf 794 handles writing the ZT state back to thread TID. */ 795 aarch64_zt_regs_copy_from_reg_buf (tid, regcache, zt_regnum); 796 797 /* We need to return the expected data in BUF, so copy whatever the kernel 798 already has to BUF. */ 799 800 /* Obtain a dump of NT_ARM_ZT from ptrace. */ 801 gdb::byte_vector zt_state = aarch64_fetch_zt_regset (tid); 802 memcpy (buf, zt_state.data (), zt_state.size ()); 803 } 804 805 /* Array containing all the possible register sets for AArch64/Linux. During 806 architecture setup, these will be checked against the HWCAP/HWCAP2 bits for 807 validity and enabled/disabled accordingly. 808 809 Their sizes are set to 0 here, but they will be adjusted later depending 810 on whether each register set is available or not. */ 811 static struct regset_info aarch64_regsets[] = 812 { 813 /* GPR registers. */ 814 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 815 0, GENERAL_REGS, 816 aarch64_fill_gregset, aarch64_store_gregset }, 817 /* Floating Point (FPU) registers. */ 818 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, 819 0, FP_REGS, 820 aarch64_fill_fpregset, aarch64_store_fpregset 821 }, 822 /* Scalable Vector Extension (SVE) registers. */ 823 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, 824 0, EXTENDED_REGS, 825 aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache 826 }, 827 /* Scalable Matrix Extension (SME) ZA register. */ 828 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZA, 829 0, EXTENDED_REGS, 830 aarch64_za_regs_copy_from_regcache, aarch64_za_regs_copy_to_regcache 831 }, 832 /* Scalable Matrix Extension 2 (SME2) ZT registers. */ 833 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_ZT, 834 0, EXTENDED_REGS, 835 aarch64_zt_regs_copy_from_regcache, aarch64_zt_regs_copy_to_regcache 836 }, 837 /* PAC registers. */ 838 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, 839 0, OPTIONAL_REGS, 840 nullptr, aarch64_store_pauthregset }, 841 /* Tagged address control / MTE registers. */ 842 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, 843 0, OPTIONAL_REGS, 844 aarch64_fill_mteregset, aarch64_store_mteregset }, 845 /* TLS register. */ 846 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TLS, 847 0, OPTIONAL_REGS, 848 aarch64_fill_tlsregset, aarch64_store_tlsregset }, 849 NULL_REGSET 850 }; 851 852 static struct regsets_info aarch64_regsets_info = 853 { 854 aarch64_regsets, /* regsets */ 855 0, /* num_regsets */ 856 nullptr, /* disabled_regsets */ 857 }; 858 859 static struct regs_info regs_info_aarch64 = 860 { 861 nullptr, /* regset_bitmap */ 862 nullptr, /* usrregs */ 863 &aarch64_regsets_info, 864 }; 865 866 /* Given FEATURES, adjust the available register sets by setting their 867 sizes. A size of 0 means the register set is disabled and won't be 868 used. */ 869 870 static void 871 aarch64_adjust_register_sets (const struct aarch64_features &features) 872 { 873 struct regset_info *regset; 874 875 for (regset = aarch64_regsets; regset->size >= 0; regset++) 876 { 877 switch (regset->nt_type) 878 { 879 case NT_PRSTATUS: 880 /* General purpose registers are always present. */ 881 regset->size = sizeof (struct user_pt_regs); 882 break; 883 case NT_FPREGSET: 884 /* This is unavailable when SVE is present. */ 885 if (features.vq == 0) 886 regset->size = sizeof (struct user_fpsimd_state); 887 break; 888 case NT_ARM_SVE: 889 if (features.vq > 0) 890 regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE); 891 break; 892 case NT_ARM_PAC_MASK: 893 if (features.pauth) 894 regset->size = AARCH64_PAUTH_REGS_SIZE; 895 break; 896 case NT_ARM_TAGGED_ADDR_CTRL: 897 if (features.mte) 898 regset->size = AARCH64_LINUX_SIZEOF_MTE; 899 break; 900 case NT_ARM_TLS: 901 if (features.tls > 0) 902 regset->size = AARCH64_TLS_REGISTER_SIZE * features.tls; 903 break; 904 case NT_ARM_ZA: 905 if (features.svq > 0) 906 regset->size = ZA_PT_SIZE (features.svq); 907 break; 908 case NT_ARM_ZT: 909 if (features.sme2) 910 regset->size = AARCH64_SME2_ZT0_SIZE; 911 break; 912 default: 913 gdb_assert_not_reached ("Unknown register set found."); 914 } 915 } 916 } 917 918 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ 919 #define AARCH64_HWCAP_PACA (1 << 30) 920 921 /* Implementation of linux target ops method "low_arch_setup". */ 922 923 void 924 aarch64_target::low_arch_setup () 925 { 926 unsigned int machine; 927 int is_elf64; 928 int tid = current_thread->id.lwp (); 929 930 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); 931 932 if (is_elf64) 933 { 934 struct aarch64_features features; 935 int pid = current_thread->id.pid (); 936 937 features.vq = aarch64_sve_get_vq (tid); 938 /* A-profile PAC is 64-bit only. */ 939 features.pauth = linux_get_hwcap (pid, 8) & AARCH64_HWCAP_PACA; 940 /* A-profile MTE is 64-bit only. */ 941 features.mte = linux_get_hwcap2 (pid, 8) & HWCAP2_MTE; 942 features.tls = aarch64_tls_register_count (tid); 943 944 /* Scalable Matrix Extension feature and size check. */ 945 if (linux_get_hwcap2 (pid, 8) & HWCAP2_SME) 946 features.svq = aarch64_za_get_svq (tid); 947 948 /* Scalable Matrix Extension 2 feature check. */ 949 CORE_ADDR hwcap2 = linux_get_hwcap2 (pid, 8); 950 if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1)) 951 { 952 /* Make sure ptrace supports NT_ARM_ZT. */ 953 features.sme2 = supports_zt_registers (tid); 954 } 955 956 current_process ()->tdesc = aarch64_linux_read_description (features); 957 958 /* Adjust the register sets we should use for this particular set of 959 features. */ 960 aarch64_adjust_register_sets (features); 961 } 962 else 963 current_process ()->tdesc = aarch32_linux_read_description (); 964 965 aarch64_linux_get_debug_reg_capacity (current_thread->id.lwp ()); 966 } 967 968 /* Implementation of linux target ops method "get_regs_info". */ 969 970 const regs_info * 971 aarch64_target::get_regs_info () 972 { 973 if (!is_64bit_tdesc ()) 974 return ®s_info_aarch32; 975 976 /* AArch64 64-bit registers. */ 977 return ®s_info_aarch64; 978 } 979 980 /* Implementation of target ops method "supports_tracepoints". */ 981 982 bool 983 aarch64_target::supports_tracepoints () 984 { 985 if (current_thread == NULL) 986 return true; 987 else 988 { 989 /* We don't support tracepoints on aarch32 now. */ 990 return is_64bit_tdesc (); 991 } 992 } 993 994 /* Implementation of linux target ops method "low_get_thread_area". */ 995 996 int 997 aarch64_target::low_get_thread_area (int lwpid, CORE_ADDR *addrp) 998 { 999 struct iovec iovec; 1000 uint64_t reg; 1001 1002 iovec.iov_base = ® 1003 iovec.iov_len = sizeof (reg); 1004 1005 if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) 1006 return -1; 1007 1008 *addrp = reg; 1009 1010 return 0; 1011 } 1012 1013 bool 1014 aarch64_target::low_supports_catch_syscall () 1015 { 1016 return true; 1017 } 1018 1019 /* Implementation of linux target ops method "low_get_syscall_trapinfo". */ 1020 1021 void 1022 aarch64_target::low_get_syscall_trapinfo (regcache *regcache, int *sysno) 1023 { 1024 int use_64bit = register_size (regcache->tdesc, 0) == 8; 1025 1026 if (use_64bit) 1027 { 1028 long l_sysno; 1029 1030 collect_register_by_name (regcache, "x8", &l_sysno); 1031 *sysno = (int) l_sysno; 1032 } 1033 else 1034 collect_register_by_name (regcache, "r7", sysno); 1035 } 1036 1037 /* List of condition codes that we need. */ 1038 1039 enum aarch64_condition_codes 1040 { 1041 EQ = 0x0, 1042 NE = 0x1, 1043 LO = 0x3, 1044 GE = 0xa, 1045 LT = 0xb, 1046 GT = 0xc, 1047 LE = 0xd, 1048 }; 1049 1050 enum aarch64_operand_type 1051 { 1052 OPERAND_IMMEDIATE, 1053 OPERAND_REGISTER, 1054 }; 1055 1056 /* Representation of an operand. At this time, it only supports register 1057 and immediate types. */ 1058 1059 struct aarch64_operand 1060 { 1061 /* Type of the operand. */ 1062 enum aarch64_operand_type type; 1063 1064 /* Value of the operand according to the type. */ 1065 union 1066 { 1067 uint32_t imm; 1068 struct aarch64_register reg; 1069 }; 1070 }; 1071 1072 /* List of registers that we are currently using, we can add more here as 1073 we need to use them. */ 1074 1075 /* General purpose scratch registers (64 bit). */ 1076 static const struct aarch64_register x0 = { 0, 1 }; 1077 static const struct aarch64_register x1 = { 1, 1 }; 1078 static const struct aarch64_register x2 = { 2, 1 }; 1079 static const struct aarch64_register x3 = { 3, 1 }; 1080 static const struct aarch64_register x4 = { 4, 1 }; 1081 1082 /* General purpose scratch registers (32 bit). */ 1083 static const struct aarch64_register w0 = { 0, 0 }; 1084 static const struct aarch64_register w2 = { 2, 0 }; 1085 1086 /* Intra-procedure scratch registers. */ 1087 static const struct aarch64_register ip0 = { 16, 1 }; 1088 1089 /* Special purpose registers. */ 1090 static const struct aarch64_register fp = { 29, 1 }; 1091 static const struct aarch64_register lr = { 30, 1 }; 1092 static const struct aarch64_register sp = { 31, 1 }; 1093 static const struct aarch64_register xzr = { 31, 1 }; 1094 1095 /* Dynamically allocate a new register. If we know the register 1096 statically, we should make it a global as above instead of using this 1097 helper function. */ 1098 1099 static struct aarch64_register 1100 aarch64_register (unsigned num, int is64) 1101 { 1102 return (struct aarch64_register) { num, is64 }; 1103 } 1104 1105 /* Helper function to create a register operand, for instructions with 1106 different types of operands. 1107 1108 For example: 1109 p += emit_mov (p, x0, register_operand (x1)); */ 1110 1111 static struct aarch64_operand 1112 register_operand (struct aarch64_register reg) 1113 { 1114 struct aarch64_operand operand; 1115 1116 operand.type = OPERAND_REGISTER; 1117 operand.reg = reg; 1118 1119 return operand; 1120 } 1121 1122 /* Helper function to create an immediate operand, for instructions with 1123 different types of operands. 1124 1125 For example: 1126 p += emit_mov (p, x0, immediate_operand (12)); */ 1127 1128 static struct aarch64_operand 1129 immediate_operand (uint32_t imm) 1130 { 1131 struct aarch64_operand operand; 1132 1133 operand.type = OPERAND_IMMEDIATE; 1134 operand.imm = imm; 1135 1136 return operand; 1137 } 1138 1139 /* Helper function to create an offset memory operand. 1140 1141 For example: 1142 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */ 1143 1144 static struct aarch64_memory_operand 1145 offset_memory_operand (int32_t offset) 1146 { 1147 return (struct aarch64_memory_operand) { MEMORY_OPERAND_OFFSET, offset }; 1148 } 1149 1150 /* Helper function to create a pre-index memory operand. 1151 1152 For example: 1153 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */ 1154 1155 static struct aarch64_memory_operand 1156 preindex_memory_operand (int32_t index) 1157 { 1158 return (struct aarch64_memory_operand) { MEMORY_OPERAND_PREINDEX, index }; 1159 } 1160 1161 /* Helper function to create a post-index memory operand. 1162 1163 For example: 1164 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */ 1165 1166 static struct aarch64_memory_operand 1167 postindex_memory_operand (int32_t index) 1168 { 1169 return (struct aarch64_memory_operand) { MEMORY_OPERAND_POSTINDEX, index }; 1170 } 1171 1172 /* System control registers. These special registers can be written and 1173 read with the MRS and MSR instructions. 1174 1175 - NZCV: Condition flags. GDB refers to this register under the CPSR 1176 name. 1177 - FPSR: Floating-point status register. 1178 - FPCR: Floating-point control registers. 1179 - TPIDR_EL0: Software thread ID register. */ 1180 1181 enum aarch64_system_control_registers 1182 { 1183 /* op0 op1 crn crm op2 */ 1184 NZCV = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0, 1185 FPSR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1, 1186 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0, 1187 TPIDR_EL0 = (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2 1188 }; 1189 1190 /* Write a BLR instruction into *BUF. 1191 1192 BLR rn 1193 1194 RN is the register to branch to. */ 1195 1196 static int 1197 emit_blr (uint32_t *buf, struct aarch64_register rn) 1198 { 1199 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5)); 1200 } 1201 1202 /* Write a RET instruction into *BUF. 1203 1204 RET xn 1205 1206 RN is the register to branch to. */ 1207 1208 static int 1209 emit_ret (uint32_t *buf, struct aarch64_register rn) 1210 { 1211 return aarch64_emit_insn (buf, RET | ENCODE (rn.num, 5, 5)); 1212 } 1213 1214 static int 1215 emit_load_store_pair (uint32_t *buf, enum aarch64_opcodes opcode, 1216 struct aarch64_register rt, 1217 struct aarch64_register rt2, 1218 struct aarch64_register rn, 1219 struct aarch64_memory_operand operand) 1220 { 1221 uint32_t opc; 1222 uint32_t pre_index; 1223 uint32_t write_back; 1224 1225 if (rt.is64) 1226 opc = ENCODE (2, 2, 30); 1227 else 1228 opc = ENCODE (0, 2, 30); 1229 1230 switch (operand.type) 1231 { 1232 case MEMORY_OPERAND_OFFSET: 1233 { 1234 pre_index = ENCODE (1, 1, 24); 1235 write_back = ENCODE (0, 1, 23); 1236 break; 1237 } 1238 case MEMORY_OPERAND_POSTINDEX: 1239 { 1240 pre_index = ENCODE (0, 1, 24); 1241 write_back = ENCODE (1, 1, 23); 1242 break; 1243 } 1244 case MEMORY_OPERAND_PREINDEX: 1245 { 1246 pre_index = ENCODE (1, 1, 24); 1247 write_back = ENCODE (1, 1, 23); 1248 break; 1249 } 1250 default: 1251 return 0; 1252 } 1253 1254 return aarch64_emit_insn (buf, opcode | opc | pre_index | write_back 1255 | ENCODE (operand.index >> 3, 7, 15) 1256 | ENCODE (rt2.num, 5, 10) 1257 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); 1258 } 1259 1260 /* Write a STP instruction into *BUF. 1261 1262 STP rt, rt2, [rn, #offset] 1263 STP rt, rt2, [rn, #index]! 1264 STP rt, rt2, [rn], #index 1265 1266 RT and RT2 are the registers to store. 1267 RN is the base address register. 1268 OFFSET is the immediate to add to the base address. It is limited to a 1269 -512 .. 504 range (7 bits << 3). */ 1270 1271 static int 1272 emit_stp (uint32_t *buf, struct aarch64_register rt, 1273 struct aarch64_register rt2, struct aarch64_register rn, 1274 struct aarch64_memory_operand operand) 1275 { 1276 return emit_load_store_pair (buf, STP, rt, rt2, rn, operand); 1277 } 1278 1279 /* Write a LDP instruction into *BUF. 1280 1281 LDP rt, rt2, [rn, #offset] 1282 LDP rt, rt2, [rn, #index]! 1283 LDP rt, rt2, [rn], #index 1284 1285 RT and RT2 are the registers to store. 1286 RN is the base address register. 1287 OFFSET is the immediate to add to the base address. It is limited to a 1288 -512 .. 504 range (7 bits << 3). */ 1289 1290 static int 1291 emit_ldp (uint32_t *buf, struct aarch64_register rt, 1292 struct aarch64_register rt2, struct aarch64_register rn, 1293 struct aarch64_memory_operand operand) 1294 { 1295 return emit_load_store_pair (buf, LDP, rt, rt2, rn, operand); 1296 } 1297 1298 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF. 1299 1300 LDP qt, qt2, [rn, #offset] 1301 1302 RT and RT2 are the Q registers to store. 1303 RN is the base address register. 1304 OFFSET is the immediate to add to the base address. It is limited to 1305 -1024 .. 1008 range (7 bits << 4). */ 1306 1307 static int 1308 emit_ldp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, 1309 struct aarch64_register rn, int32_t offset) 1310 { 1311 uint32_t opc = ENCODE (2, 2, 30); 1312 uint32_t pre_index = ENCODE (1, 1, 24); 1313 1314 return aarch64_emit_insn (buf, LDP_SIMD_VFP | opc | pre_index 1315 | ENCODE (offset >> 4, 7, 15) 1316 | ENCODE (rt2, 5, 10) 1317 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); 1318 } 1319 1320 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF. 1321 1322 STP qt, qt2, [rn, #offset] 1323 1324 RT and RT2 are the Q registers to store. 1325 RN is the base address register. 1326 OFFSET is the immediate to add to the base address. It is limited to 1327 -1024 .. 1008 range (7 bits << 4). */ 1328 1329 static int 1330 emit_stp_q_offset (uint32_t *buf, unsigned rt, unsigned rt2, 1331 struct aarch64_register rn, int32_t offset) 1332 { 1333 uint32_t opc = ENCODE (2, 2, 30); 1334 uint32_t pre_index = ENCODE (1, 1, 24); 1335 1336 return aarch64_emit_insn (buf, STP_SIMD_VFP | opc | pre_index 1337 | ENCODE (offset >> 4, 7, 15) 1338 | ENCODE (rt2, 5, 10) 1339 | ENCODE (rn.num, 5, 5) | ENCODE (rt, 5, 0)); 1340 } 1341 1342 /* Write a LDRH instruction into *BUF. 1343 1344 LDRH wt, [xn, #offset] 1345 LDRH wt, [xn, #index]! 1346 LDRH wt, [xn], #index 1347 1348 RT is the register to store. 1349 RN is the base address register. 1350 OFFSET is the immediate to add to the base address. It is limited to 1351 0 .. 32760 range (12 bits << 3). */ 1352 1353 static int 1354 emit_ldrh (uint32_t *buf, struct aarch64_register rt, 1355 struct aarch64_register rn, 1356 struct aarch64_memory_operand operand) 1357 { 1358 return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand); 1359 } 1360 1361 /* Write a LDRB instruction into *BUF. 1362 1363 LDRB wt, [xn, #offset] 1364 LDRB wt, [xn, #index]! 1365 LDRB wt, [xn], #index 1366 1367 RT is the register to store. 1368 RN is the base address register. 1369 OFFSET is the immediate to add to the base address. It is limited to 1370 0 .. 32760 range (12 bits << 3). */ 1371 1372 static int 1373 emit_ldrb (uint32_t *buf, struct aarch64_register rt, 1374 struct aarch64_register rn, 1375 struct aarch64_memory_operand operand) 1376 { 1377 return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand); 1378 } 1379 1380 1381 1382 /* Write a STR instruction into *BUF. 1383 1384 STR rt, [rn, #offset] 1385 STR rt, [rn, #index]! 1386 STR rt, [rn], #index 1387 1388 RT is the register to store. 1389 RN is the base address register. 1390 OFFSET is the immediate to add to the base address. It is limited to 1391 0 .. 32760 range (12 bits << 3). */ 1392 1393 static int 1394 emit_str (uint32_t *buf, struct aarch64_register rt, 1395 struct aarch64_register rn, 1396 struct aarch64_memory_operand operand) 1397 { 1398 return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand); 1399 } 1400 1401 /* Helper function emitting an exclusive load or store instruction. */ 1402 1403 static int 1404 emit_load_store_exclusive (uint32_t *buf, uint32_t size, 1405 enum aarch64_opcodes opcode, 1406 struct aarch64_register rs, 1407 struct aarch64_register rt, 1408 struct aarch64_register rt2, 1409 struct aarch64_register rn) 1410 { 1411 return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) 1412 | ENCODE (rs.num, 5, 16) | ENCODE (rt2.num, 5, 10) 1413 | ENCODE (rn.num, 5, 5) | ENCODE (rt.num, 5, 0)); 1414 } 1415 1416 /* Write a LAXR instruction into *BUF. 1417 1418 LDAXR rt, [xn] 1419 1420 RT is the destination register. 1421 RN is the base address register. */ 1422 1423 static int 1424 emit_ldaxr (uint32_t *buf, struct aarch64_register rt, 1425 struct aarch64_register rn) 1426 { 1427 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, LDAXR, xzr, rt, 1428 xzr, rn); 1429 } 1430 1431 /* Write a STXR instruction into *BUF. 1432 1433 STXR ws, rt, [xn] 1434 1435 RS is the result register, it indicates if the store succeeded or not. 1436 RT is the destination register. 1437 RN is the base address register. */ 1438 1439 static int 1440 emit_stxr (uint32_t *buf, struct aarch64_register rs, 1441 struct aarch64_register rt, struct aarch64_register rn) 1442 { 1443 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STXR, rs, rt, 1444 xzr, rn); 1445 } 1446 1447 /* Write a STLR instruction into *BUF. 1448 1449 STLR rt, [xn] 1450 1451 RT is the register to store. 1452 RN is the base address register. */ 1453 1454 static int 1455 emit_stlr (uint32_t *buf, struct aarch64_register rt, 1456 struct aarch64_register rn) 1457 { 1458 return emit_load_store_exclusive (buf, rt.is64 ? 3 : 2, STLR, xzr, rt, 1459 xzr, rn); 1460 } 1461 1462 /* Helper function for data processing instructions with register sources. */ 1463 1464 static int 1465 emit_data_processing_reg (uint32_t *buf, uint32_t opcode, 1466 struct aarch64_register rd, 1467 struct aarch64_register rn, 1468 struct aarch64_register rm) 1469 { 1470 uint32_t size = ENCODE (rd.is64, 1, 31); 1471 1472 return aarch64_emit_insn (buf, opcode | size | ENCODE (rm.num, 5, 16) 1473 | ENCODE (rn.num, 5, 5) | ENCODE (rd.num, 5, 0)); 1474 } 1475 1476 /* Helper function for data processing instructions taking either a register 1477 or an immediate. */ 1478 1479 static int 1480 emit_data_processing (uint32_t *buf, enum aarch64_opcodes opcode, 1481 struct aarch64_register rd, 1482 struct aarch64_register rn, 1483 struct aarch64_operand operand) 1484 { 1485 uint32_t size = ENCODE (rd.is64, 1, 31); 1486 /* The opcode is different for register and immediate source operands. */ 1487 uint32_t operand_opcode; 1488 1489 if (operand.type == OPERAND_IMMEDIATE) 1490 { 1491 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */ 1492 operand_opcode = ENCODE (8, 4, 25); 1493 1494 return aarch64_emit_insn (buf, opcode | operand_opcode | size 1495 | ENCODE (operand.imm, 12, 10) 1496 | ENCODE (rn.num, 5, 5) 1497 | ENCODE (rd.num, 5, 0)); 1498 } 1499 else 1500 { 1501 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */ 1502 operand_opcode = ENCODE (5, 4, 25); 1503 1504 return emit_data_processing_reg (buf, opcode | operand_opcode, rd, 1505 rn, operand.reg); 1506 } 1507 } 1508 1509 /* Write an ADD instruction into *BUF. 1510 1511 ADD rd, rn, #imm 1512 ADD rd, rn, rm 1513 1514 This function handles both an immediate and register add. 1515 1516 RD is the destination register. 1517 RN is the input register. 1518 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or 1519 OPERAND_REGISTER. */ 1520 1521 static int 1522 emit_add (uint32_t *buf, struct aarch64_register rd, 1523 struct aarch64_register rn, struct aarch64_operand operand) 1524 { 1525 return emit_data_processing (buf, ADD, rd, rn, operand); 1526 } 1527 1528 /* Write a SUB instruction into *BUF. 1529 1530 SUB rd, rn, #imm 1531 SUB rd, rn, rm 1532 1533 This function handles both an immediate and register sub. 1534 1535 RD is the destination register. 1536 RN is the input register. 1537 IMM is the immediate to subtract to RN. */ 1538 1539 static int 1540 emit_sub (uint32_t *buf, struct aarch64_register rd, 1541 struct aarch64_register rn, struct aarch64_operand operand) 1542 { 1543 return emit_data_processing (buf, SUB, rd, rn, operand); 1544 } 1545 1546 /* Write a MOV instruction into *BUF. 1547 1548 MOV rd, #imm 1549 MOV rd, rm 1550 1551 This function handles both a wide immediate move and a register move, 1552 with the condition that the source register is not xzr. xzr and the 1553 stack pointer share the same encoding and this function only supports 1554 the stack pointer. 1555 1556 RD is the destination register. 1557 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or 1558 OPERAND_REGISTER. */ 1559 1560 static int 1561 emit_mov (uint32_t *buf, struct aarch64_register rd, 1562 struct aarch64_operand operand) 1563 { 1564 if (operand.type == OPERAND_IMMEDIATE) 1565 { 1566 uint32_t size = ENCODE (rd.is64, 1, 31); 1567 /* Do not shift the immediate. */ 1568 uint32_t shift = ENCODE (0, 2, 21); 1569 1570 return aarch64_emit_insn (buf, MOV | size | shift 1571 | ENCODE (operand.imm, 16, 5) 1572 | ENCODE (rd.num, 5, 0)); 1573 } 1574 else 1575 return emit_add (buf, rd, operand.reg, immediate_operand (0)); 1576 } 1577 1578 /* Write a MOVK instruction into *BUF. 1579 1580 MOVK rd, #imm, lsl #shift 1581 1582 RD is the destination register. 1583 IMM is the immediate. 1584 SHIFT is the logical shift left to apply to IMM. */ 1585 1586 static int 1587 emit_movk (uint32_t *buf, struct aarch64_register rd, uint32_t imm, 1588 unsigned shift) 1589 { 1590 uint32_t size = ENCODE (rd.is64, 1, 31); 1591 1592 return aarch64_emit_insn (buf, MOVK | size | ENCODE (shift, 2, 21) | 1593 ENCODE (imm, 16, 5) | ENCODE (rd.num, 5, 0)); 1594 } 1595 1596 /* Write instructions into *BUF in order to move ADDR into a register. 1597 ADDR can be a 64-bit value. 1598 1599 This function will emit a series of MOV and MOVK instructions, such as: 1600 1601 MOV xd, #(addr) 1602 MOVK xd, #(addr >> 16), lsl #16 1603 MOVK xd, #(addr >> 32), lsl #32 1604 MOVK xd, #(addr >> 48), lsl #48 */ 1605 1606 static int 1607 emit_mov_addr (uint32_t *buf, struct aarch64_register rd, CORE_ADDR addr) 1608 { 1609 uint32_t *p = buf; 1610 1611 /* The MOV (wide immediate) instruction clears to top bits of the 1612 register. */ 1613 p += emit_mov (p, rd, immediate_operand (addr & 0xffff)); 1614 1615 if ((addr >> 16) != 0) 1616 p += emit_movk (p, rd, (addr >> 16) & 0xffff, 1); 1617 else 1618 return p - buf; 1619 1620 if ((addr >> 32) != 0) 1621 p += emit_movk (p, rd, (addr >> 32) & 0xffff, 2); 1622 else 1623 return p - buf; 1624 1625 if ((addr >> 48) != 0) 1626 p += emit_movk (p, rd, (addr >> 48) & 0xffff, 3); 1627 1628 return p - buf; 1629 } 1630 1631 /* Write a SUBS instruction into *BUF. 1632 1633 SUBS rd, rn, rm 1634 1635 This instruction update the condition flags. 1636 1637 RD is the destination register. 1638 RN and RM are the source registers. */ 1639 1640 static int 1641 emit_subs (uint32_t *buf, struct aarch64_register rd, 1642 struct aarch64_register rn, struct aarch64_operand operand) 1643 { 1644 return emit_data_processing (buf, SUBS, rd, rn, operand); 1645 } 1646 1647 /* Write a CMP instruction into *BUF. 1648 1649 CMP rn, rm 1650 1651 This instruction is an alias of SUBS xzr, rn, rm. 1652 1653 RN and RM are the registers to compare. */ 1654 1655 static int 1656 emit_cmp (uint32_t *buf, struct aarch64_register rn, 1657 struct aarch64_operand operand) 1658 { 1659 return emit_subs (buf, xzr, rn, operand); 1660 } 1661 1662 /* Write a AND instruction into *BUF. 1663 1664 AND rd, rn, rm 1665 1666 RD is the destination register. 1667 RN and RM are the source registers. */ 1668 1669 static int 1670 emit_and (uint32_t *buf, struct aarch64_register rd, 1671 struct aarch64_register rn, struct aarch64_register rm) 1672 { 1673 return emit_data_processing_reg (buf, AND, rd, rn, rm); 1674 } 1675 1676 /* Write a ORR instruction into *BUF. 1677 1678 ORR rd, rn, rm 1679 1680 RD is the destination register. 1681 RN and RM are the source registers. */ 1682 1683 static int 1684 emit_orr (uint32_t *buf, struct aarch64_register rd, 1685 struct aarch64_register rn, struct aarch64_register rm) 1686 { 1687 return emit_data_processing_reg (buf, ORR, rd, rn, rm); 1688 } 1689 1690 /* Write a ORN instruction into *BUF. 1691 1692 ORN rd, rn, rm 1693 1694 RD is the destination register. 1695 RN and RM are the source registers. */ 1696 1697 static int 1698 emit_orn (uint32_t *buf, struct aarch64_register rd, 1699 struct aarch64_register rn, struct aarch64_register rm) 1700 { 1701 return emit_data_processing_reg (buf, ORN, rd, rn, rm); 1702 } 1703 1704 /* Write a EOR instruction into *BUF. 1705 1706 EOR rd, rn, rm 1707 1708 RD is the destination register. 1709 RN and RM are the source registers. */ 1710 1711 static int 1712 emit_eor (uint32_t *buf, struct aarch64_register rd, 1713 struct aarch64_register rn, struct aarch64_register rm) 1714 { 1715 return emit_data_processing_reg (buf, EOR, rd, rn, rm); 1716 } 1717 1718 /* Write a MVN instruction into *BUF. 1719 1720 MVN rd, rm 1721 1722 This is an alias for ORN rd, xzr, rm. 1723 1724 RD is the destination register. 1725 RM is the source register. */ 1726 1727 static int 1728 emit_mvn (uint32_t *buf, struct aarch64_register rd, 1729 struct aarch64_register rm) 1730 { 1731 return emit_orn (buf, rd, xzr, rm); 1732 } 1733 1734 /* Write a LSLV instruction into *BUF. 1735 1736 LSLV rd, rn, rm 1737 1738 RD is the destination register. 1739 RN and RM are the source registers. */ 1740 1741 static int 1742 emit_lslv (uint32_t *buf, struct aarch64_register rd, 1743 struct aarch64_register rn, struct aarch64_register rm) 1744 { 1745 return emit_data_processing_reg (buf, LSLV, rd, rn, rm); 1746 } 1747 1748 /* Write a LSRV instruction into *BUF. 1749 1750 LSRV rd, rn, rm 1751 1752 RD is the destination register. 1753 RN and RM are the source registers. */ 1754 1755 static int 1756 emit_lsrv (uint32_t *buf, struct aarch64_register rd, 1757 struct aarch64_register rn, struct aarch64_register rm) 1758 { 1759 return emit_data_processing_reg (buf, LSRV, rd, rn, rm); 1760 } 1761 1762 /* Write a ASRV instruction into *BUF. 1763 1764 ASRV rd, rn, rm 1765 1766 RD is the destination register. 1767 RN and RM are the source registers. */ 1768 1769 static int 1770 emit_asrv (uint32_t *buf, struct aarch64_register rd, 1771 struct aarch64_register rn, struct aarch64_register rm) 1772 { 1773 return emit_data_processing_reg (buf, ASRV, rd, rn, rm); 1774 } 1775 1776 /* Write a MUL instruction into *BUF. 1777 1778 MUL rd, rn, rm 1779 1780 RD is the destination register. 1781 RN and RM are the source registers. */ 1782 1783 static int 1784 emit_mul (uint32_t *buf, struct aarch64_register rd, 1785 struct aarch64_register rn, struct aarch64_register rm) 1786 { 1787 return emit_data_processing_reg (buf, MUL, rd, rn, rm); 1788 } 1789 1790 /* Write a MRS instruction into *BUF. The register size is 64-bit. 1791 1792 MRS xt, system_reg 1793 1794 RT is the destination register. 1795 SYSTEM_REG is special purpose register to read. */ 1796 1797 static int 1798 emit_mrs (uint32_t *buf, struct aarch64_register rt, 1799 enum aarch64_system_control_registers system_reg) 1800 { 1801 return aarch64_emit_insn (buf, MRS | ENCODE (system_reg, 15, 5) 1802 | ENCODE (rt.num, 5, 0)); 1803 } 1804 1805 /* Write a MSR instruction into *BUF. The register size is 64-bit. 1806 1807 MSR system_reg, xt 1808 1809 SYSTEM_REG is special purpose register to write. 1810 RT is the input register. */ 1811 1812 static int 1813 emit_msr (uint32_t *buf, enum aarch64_system_control_registers system_reg, 1814 struct aarch64_register rt) 1815 { 1816 return aarch64_emit_insn (buf, MSR | ENCODE (system_reg, 15, 5) 1817 | ENCODE (rt.num, 5, 0)); 1818 } 1819 1820 /* Write a SEVL instruction into *BUF. 1821 1822 This is a hint instruction telling the hardware to trigger an event. */ 1823 1824 static int 1825 emit_sevl (uint32_t *buf) 1826 { 1827 return aarch64_emit_insn (buf, SEVL); 1828 } 1829 1830 /* Write a WFE instruction into *BUF. 1831 1832 This is a hint instruction telling the hardware to wait for an event. */ 1833 1834 static int 1835 emit_wfe (uint32_t *buf) 1836 { 1837 return aarch64_emit_insn (buf, WFE); 1838 } 1839 1840 /* Write a SBFM instruction into *BUF. 1841 1842 SBFM rd, rn, #immr, #imms 1843 1844 This instruction moves the bits from #immr to #imms into the 1845 destination, sign extending the result. 1846 1847 RD is the destination register. 1848 RN is the source register. 1849 IMMR is the bit number to start at (least significant bit). 1850 IMMS is the bit number to stop at (most significant bit). */ 1851 1852 static int 1853 emit_sbfm (uint32_t *buf, struct aarch64_register rd, 1854 struct aarch64_register rn, uint32_t immr, uint32_t imms) 1855 { 1856 uint32_t size = ENCODE (rd.is64, 1, 31); 1857 uint32_t n = ENCODE (rd.is64, 1, 22); 1858 1859 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16) 1860 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) 1861 | ENCODE (rd.num, 5, 0)); 1862 } 1863 1864 /* Write a SBFX instruction into *BUF. 1865 1866 SBFX rd, rn, #lsb, #width 1867 1868 This instruction moves #width bits from #lsb into the destination, sign 1869 extending the result. This is an alias for: 1870 1871 SBFM rd, rn, #lsb, #(lsb + width - 1) 1872 1873 RD is the destination register. 1874 RN is the source register. 1875 LSB is the bit number to start at (least significant bit). 1876 WIDTH is the number of bits to move. */ 1877 1878 static int 1879 emit_sbfx (uint32_t *buf, struct aarch64_register rd, 1880 struct aarch64_register rn, uint32_t lsb, uint32_t width) 1881 { 1882 return emit_sbfm (buf, rd, rn, lsb, lsb + width - 1); 1883 } 1884 1885 /* Write a UBFM instruction into *BUF. 1886 1887 UBFM rd, rn, #immr, #imms 1888 1889 This instruction moves the bits from #immr to #imms into the 1890 destination, extending the result with zeros. 1891 1892 RD is the destination register. 1893 RN is the source register. 1894 IMMR is the bit number to start at (least significant bit). 1895 IMMS is the bit number to stop at (most significant bit). */ 1896 1897 static int 1898 emit_ubfm (uint32_t *buf, struct aarch64_register rd, 1899 struct aarch64_register rn, uint32_t immr, uint32_t imms) 1900 { 1901 uint32_t size = ENCODE (rd.is64, 1, 31); 1902 uint32_t n = ENCODE (rd.is64, 1, 22); 1903 1904 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16) 1905 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5) 1906 | ENCODE (rd.num, 5, 0)); 1907 } 1908 1909 /* Write a UBFX instruction into *BUF. 1910 1911 UBFX rd, rn, #lsb, #width 1912 1913 This instruction moves #width bits from #lsb into the destination, 1914 extending the result with zeros. This is an alias for: 1915 1916 UBFM rd, rn, #lsb, #(lsb + width - 1) 1917 1918 RD is the destination register. 1919 RN is the source register. 1920 LSB is the bit number to start at (least significant bit). 1921 WIDTH is the number of bits to move. */ 1922 1923 static int 1924 emit_ubfx (uint32_t *buf, struct aarch64_register rd, 1925 struct aarch64_register rn, uint32_t lsb, uint32_t width) 1926 { 1927 return emit_ubfm (buf, rd, rn, lsb, lsb + width - 1); 1928 } 1929 1930 /* Write a CSINC instruction into *BUF. 1931 1932 CSINC rd, rn, rm, cond 1933 1934 This instruction conditionally increments rn or rm and places the result 1935 in rd. rn is chosen is the condition is true. 1936 1937 RD is the destination register. 1938 RN and RM are the source registers. 1939 COND is the encoded condition. */ 1940 1941 static int 1942 emit_csinc (uint32_t *buf, struct aarch64_register rd, 1943 struct aarch64_register rn, struct aarch64_register rm, 1944 unsigned cond) 1945 { 1946 uint32_t size = ENCODE (rd.is64, 1, 31); 1947 1948 return aarch64_emit_insn (buf, CSINC | size | ENCODE (rm.num, 5, 16) 1949 | ENCODE (cond, 4, 12) | ENCODE (rn.num, 5, 5) 1950 | ENCODE (rd.num, 5, 0)); 1951 } 1952 1953 /* Write a CSET instruction into *BUF. 1954 1955 CSET rd, cond 1956 1957 This instruction conditionally write 1 or 0 in the destination register. 1958 1 is written if the condition is true. This is an alias for: 1959 1960 CSINC rd, xzr, xzr, !cond 1961 1962 Note that the condition needs to be inverted. 1963 1964 RD is the destination register. 1965 RN and RM are the source registers. 1966 COND is the encoded condition. */ 1967 1968 static int 1969 emit_cset (uint32_t *buf, struct aarch64_register rd, unsigned cond) 1970 { 1971 /* The least significant bit of the condition needs toggling in order to 1972 invert it. */ 1973 return emit_csinc (buf, rd, xzr, xzr, cond ^ 0x1); 1974 } 1975 1976 /* Write LEN instructions from BUF into the inferior memory at *TO. 1977 1978 Note instructions are always little endian on AArch64, unlike data. */ 1979 1980 static void 1981 append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf) 1982 { 1983 size_t byte_len = len * sizeof (uint32_t); 1984 #if (__BYTE_ORDER == __BIG_ENDIAN) 1985 uint32_t *le_buf = (uint32_t *) xmalloc (byte_len); 1986 size_t i; 1987 1988 for (i = 0; i < len; i++) 1989 le_buf[i] = htole32 (buf[i]); 1990 1991 target_write_memory (*to, (const unsigned char *) le_buf, byte_len); 1992 1993 xfree (le_buf); 1994 #else 1995 target_write_memory (*to, (const unsigned char *) buf, byte_len); 1996 #endif 1997 1998 *to += byte_len; 1999 } 2000 2001 /* Sub-class of struct aarch64_insn_data, store information of 2002 instruction relocation for fast tracepoint. Visitor can 2003 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save 2004 the relocated instructions in buffer pointed by INSN_PTR. */ 2005 2006 struct aarch64_insn_relocation_data 2007 { 2008 struct aarch64_insn_data base; 2009 2010 /* The new address the instruction is relocated to. */ 2011 CORE_ADDR new_addr; 2012 /* Pointer to the buffer of relocated instruction(s). */ 2013 uint32_t *insn_ptr; 2014 }; 2015 2016 /* Implementation of aarch64_insn_visitor method "b". */ 2017 2018 static void 2019 aarch64_ftrace_insn_reloc_b (const int is_bl, const int32_t offset, 2020 struct aarch64_insn_data *data) 2021 { 2022 struct aarch64_insn_relocation_data *insn_reloc 2023 = (struct aarch64_insn_relocation_data *) data; 2024 int64_t new_offset 2025 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2026 2027 if (can_encode_int32 (new_offset, 28)) 2028 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, is_bl, new_offset); 2029 } 2030 2031 /* Implementation of aarch64_insn_visitor method "b_cond". */ 2032 2033 static void 2034 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond, const int32_t offset, 2035 struct aarch64_insn_data *data) 2036 { 2037 struct aarch64_insn_relocation_data *insn_reloc 2038 = (struct aarch64_insn_relocation_data *) data; 2039 int64_t new_offset 2040 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2041 2042 if (can_encode_int32 (new_offset, 21)) 2043 { 2044 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 2045 new_offset); 2046 } 2047 else if (can_encode_int32 (new_offset, 28)) 2048 { 2049 /* The offset is out of range for a conditional branch 2050 instruction but not for a unconditional branch. We can use 2051 the following instructions instead: 2052 2053 B.COND TAKEN ; If cond is true, then jump to TAKEN. 2054 B NOT_TAKEN ; Else jump over TAKEN and continue. 2055 TAKEN: 2056 B #(offset - 8) 2057 NOT_TAKEN: 2058 2059 */ 2060 2061 insn_reloc->insn_ptr += emit_bcond (insn_reloc->insn_ptr, cond, 8); 2062 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2063 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8); 2064 } 2065 } 2066 2067 /* Implementation of aarch64_insn_visitor method "cb". */ 2068 2069 static void 2070 aarch64_ftrace_insn_reloc_cb (const int32_t offset, const int is_cbnz, 2071 const unsigned rn, int is64, 2072 struct aarch64_insn_data *data) 2073 { 2074 struct aarch64_insn_relocation_data *insn_reloc 2075 = (struct aarch64_insn_relocation_data *) data; 2076 int64_t new_offset 2077 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2078 2079 if (can_encode_int32 (new_offset, 21)) 2080 { 2081 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz, 2082 aarch64_register (rn, is64), new_offset); 2083 } 2084 else if (can_encode_int32 (new_offset, 28)) 2085 { 2086 /* The offset is out of range for a compare and branch 2087 instruction but not for a unconditional branch. We can use 2088 the following instructions instead: 2089 2090 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. 2091 B NOT_TAKEN ; Else jump over TAKEN and continue. 2092 TAKEN: 2093 B #(offset - 8) 2094 NOT_TAKEN: 2095 2096 */ 2097 insn_reloc->insn_ptr += emit_cb (insn_reloc->insn_ptr, is_cbnz, 2098 aarch64_register (rn, is64), 8); 2099 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2100 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, new_offset - 8); 2101 } 2102 } 2103 2104 /* Implementation of aarch64_insn_visitor method "tb". */ 2105 2106 static void 2107 aarch64_ftrace_insn_reloc_tb (const int32_t offset, int is_tbnz, 2108 const unsigned rt, unsigned bit, 2109 struct aarch64_insn_data *data) 2110 { 2111 struct aarch64_insn_relocation_data *insn_reloc 2112 = (struct aarch64_insn_relocation_data *) data; 2113 int64_t new_offset 2114 = insn_reloc->base.insn_addr - insn_reloc->new_addr + offset; 2115 2116 if (can_encode_int32 (new_offset, 16)) 2117 { 2118 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit, 2119 aarch64_register (rt, 1), new_offset); 2120 } 2121 else if (can_encode_int32 (new_offset, 28)) 2122 { 2123 /* The offset is out of range for a test bit and branch 2124 instruction but not for a unconditional branch. We can use 2125 the following instructions instead: 2126 2127 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. 2128 B NOT_TAKEN ; Else jump over TAKEN and continue. 2129 TAKEN: 2130 B #(offset - 8) 2131 NOT_TAKEN: 2132 2133 */ 2134 insn_reloc->insn_ptr += emit_tb (insn_reloc->insn_ptr, is_tbnz, bit, 2135 aarch64_register (rt, 1), 8); 2136 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 8); 2137 insn_reloc->insn_ptr += emit_b (insn_reloc->insn_ptr, 0, 2138 new_offset - 8); 2139 } 2140 } 2141 2142 /* Implementation of aarch64_insn_visitor method "adr". */ 2143 2144 static void 2145 aarch64_ftrace_insn_reloc_adr (const int32_t offset, const unsigned rd, 2146 const int is_adrp, 2147 struct aarch64_insn_data *data) 2148 { 2149 struct aarch64_insn_relocation_data *insn_reloc 2150 = (struct aarch64_insn_relocation_data *) data; 2151 /* We know exactly the address the ADR{P,} instruction will compute. 2152 We can just write it to the destination register. */ 2153 CORE_ADDR address = data->insn_addr + offset; 2154 2155 if (is_adrp) 2156 { 2157 /* Clear the lower 12 bits of the offset to get the 4K page. */ 2158 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2159 aarch64_register (rd, 1), 2160 address & ~0xfff); 2161 } 2162 else 2163 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2164 aarch64_register (rd, 1), address); 2165 } 2166 2167 /* Implementation of aarch64_insn_visitor method "ldr_literal". */ 2168 2169 static void 2170 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset, const int is_sw, 2171 const unsigned rt, const int is64, 2172 struct aarch64_insn_data *data) 2173 { 2174 struct aarch64_insn_relocation_data *insn_reloc 2175 = (struct aarch64_insn_relocation_data *) data; 2176 CORE_ADDR address = data->insn_addr + offset; 2177 2178 insn_reloc->insn_ptr += emit_mov_addr (insn_reloc->insn_ptr, 2179 aarch64_register (rt, 1), address); 2180 2181 /* We know exactly what address to load from, and what register we 2182 can use: 2183 2184 MOV xd, #(oldloc + offset) 2185 MOVK xd, #((oldloc + offset) >> 16), lsl #16 2186 ... 2187 2188 LDR xd, [xd] ; or LDRSW xd, [xd] 2189 2190 */ 2191 2192 if (is_sw) 2193 insn_reloc->insn_ptr += emit_ldrsw (insn_reloc->insn_ptr, 2194 aarch64_register (rt, 1), 2195 aarch64_register (rt, 1), 2196 offset_memory_operand (0)); 2197 else 2198 insn_reloc->insn_ptr += emit_ldr (insn_reloc->insn_ptr, 2199 aarch64_register (rt, is64), 2200 aarch64_register (rt, 1), 2201 offset_memory_operand (0)); 2202 } 2203 2204 /* Implementation of aarch64_insn_visitor method "others". */ 2205 2206 static void 2207 aarch64_ftrace_insn_reloc_others (const uint32_t insn, 2208 struct aarch64_insn_data *data) 2209 { 2210 struct aarch64_insn_relocation_data *insn_reloc 2211 = (struct aarch64_insn_relocation_data *) data; 2212 2213 /* The instruction is not PC relative. Just re-emit it at the new 2214 location. */ 2215 insn_reloc->insn_ptr += aarch64_emit_insn (insn_reloc->insn_ptr, insn); 2216 } 2217 2218 static const struct aarch64_insn_visitor visitor = 2219 { 2220 aarch64_ftrace_insn_reloc_b, 2221 aarch64_ftrace_insn_reloc_b_cond, 2222 aarch64_ftrace_insn_reloc_cb, 2223 aarch64_ftrace_insn_reloc_tb, 2224 aarch64_ftrace_insn_reloc_adr, 2225 aarch64_ftrace_insn_reloc_ldr_literal, 2226 aarch64_ftrace_insn_reloc_others, 2227 }; 2228 2229 bool 2230 aarch64_target::supports_fast_tracepoints () 2231 { 2232 return true; 2233 } 2234 2235 /* Implementation of target ops method 2236 "install_fast_tracepoint_jump_pad". */ 2237 2238 int 2239 aarch64_target::install_fast_tracepoint_jump_pad 2240 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 2241 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 2242 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 2243 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 2244 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 2245 char *err) 2246 { 2247 uint32_t buf[256]; 2248 uint32_t *p = buf; 2249 int64_t offset; 2250 int i; 2251 uint32_t insn; 2252 CORE_ADDR buildaddr = *jump_entry; 2253 struct aarch64_insn_relocation_data insn_data; 2254 2255 /* We need to save the current state on the stack both to restore it 2256 later and to collect register values when the tracepoint is hit. 2257 2258 The saved registers are pushed in a layout that needs to be in sync 2259 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on 2260 the supply_fast_tracepoint_registers function will fill in the 2261 register cache from a pointer to saved registers on the stack we build 2262 here. 2263 2264 For simplicity, we set the size of each cell on the stack to 16 bytes. 2265 This way one cell can hold any register type, from system registers 2266 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer 2267 has to be 16 bytes aligned anyway. 2268 2269 Note that the CPSR register does not exist on AArch64. Instead we 2270 can access system bits describing the process state with the 2271 MRS/MSR instructions, namely the condition flags. We save them as 2272 if they are part of a CPSR register because that's how GDB 2273 interprets these system bits. At the moment, only the condition 2274 flags are saved in CPSR (NZCV). 2275 2276 Stack layout, each cell is 16 bytes (descending): 2277 2278 High *-------- SIMD&FP registers from 31 down to 0. --------* 2279 | q31 | 2280 . . 2281 . . 32 cells 2282 . . 2283 | q0 | 2284 *---- General purpose registers from 30 down to 0. ----* 2285 | x30 | 2286 . . 2287 . . 31 cells 2288 . . 2289 | x0 | 2290 *------------- Special purpose registers. -------------* 2291 | SP | 2292 | PC | 2293 | CPSR (NZCV) | 5 cells 2294 | FPSR | 2295 | FPCR | <- SP + 16 2296 *------------- collecting_t object --------------------* 2297 | TPIDR_EL0 | struct tracepoint * | 2298 Low *------------------------------------------------------* 2299 2300 After this stack is set up, we issue a call to the collector, passing 2301 it the saved registers at (SP + 16). */ 2302 2303 /* Push SIMD&FP registers on the stack: 2304 2305 SUB sp, sp, #(32 * 16) 2306 2307 STP q30, q31, [sp, #(30 * 16)] 2308 ... 2309 STP q0, q1, [sp] 2310 2311 */ 2312 p += emit_sub (p, sp, sp, immediate_operand (32 * 16)); 2313 for (i = 30; i >= 0; i -= 2) 2314 p += emit_stp_q_offset (p, i, i + 1, sp, i * 16); 2315 2316 /* Push general purpose registers on the stack. Note that we do not need 2317 to push x31 as it represents the xzr register and not the stack 2318 pointer in a STR instruction. 2319 2320 SUB sp, sp, #(31 * 16) 2321 2322 STR x30, [sp, #(30 * 16)] 2323 ... 2324 STR x0, [sp] 2325 2326 */ 2327 p += emit_sub (p, sp, sp, immediate_operand (31 * 16)); 2328 for (i = 30; i >= 0; i -= 1) 2329 p += emit_str (p, aarch64_register (i, 1), sp, 2330 offset_memory_operand (i * 16)); 2331 2332 /* Make space for 5 more cells. 2333 2334 SUB sp, sp, #(5 * 16) 2335 2336 */ 2337 p += emit_sub (p, sp, sp, immediate_operand (5 * 16)); 2338 2339 2340 /* Save SP: 2341 2342 ADD x4, sp, #((32 + 31 + 5) * 16) 2343 STR x4, [sp, #(4 * 16)] 2344 2345 */ 2346 p += emit_add (p, x4, sp, immediate_operand ((32 + 31 + 5) * 16)); 2347 p += emit_str (p, x4, sp, offset_memory_operand (4 * 16)); 2348 2349 /* Save PC (tracepoint address): 2350 2351 MOV x3, #(tpaddr) 2352 ... 2353 2354 STR x3, [sp, #(3 * 16)] 2355 2356 */ 2357 2358 p += emit_mov_addr (p, x3, tpaddr); 2359 p += emit_str (p, x3, sp, offset_memory_operand (3 * 16)); 2360 2361 /* Save CPSR (NZCV), FPSR and FPCR: 2362 2363 MRS x2, nzcv 2364 MRS x1, fpsr 2365 MRS x0, fpcr 2366 2367 STR x2, [sp, #(2 * 16)] 2368 STR x1, [sp, #(1 * 16)] 2369 STR x0, [sp, #(0 * 16)] 2370 2371 */ 2372 p += emit_mrs (p, x2, NZCV); 2373 p += emit_mrs (p, x1, FPSR); 2374 p += emit_mrs (p, x0, FPCR); 2375 p += emit_str (p, x2, sp, offset_memory_operand (2 * 16)); 2376 p += emit_str (p, x1, sp, offset_memory_operand (1 * 16)); 2377 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16)); 2378 2379 /* Push the collecting_t object. It consist of the address of the 2380 tracepoint and an ID for the current thread. We get the latter by 2381 reading the tpidr_el0 system register. It corresponds to the 2382 NT_ARM_TLS register accessible with ptrace. 2383 2384 MOV x0, #(tpoint) 2385 ... 2386 2387 MRS x1, tpidr_el0 2388 2389 STP x0, x1, [sp, #-16]! 2390 2391 */ 2392 2393 p += emit_mov_addr (p, x0, tpoint); 2394 p += emit_mrs (p, x1, TPIDR_EL0); 2395 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-16)); 2396 2397 /* Spin-lock: 2398 2399 The shared memory for the lock is at lockaddr. It will hold zero 2400 if no-one is holding the lock, otherwise it contains the address of 2401 the collecting_t object on the stack of the thread which acquired it. 2402 2403 At this stage, the stack pointer points to this thread's collecting_t 2404 object. 2405 2406 We use the following registers: 2407 - x0: Address of the lock. 2408 - x1: Pointer to collecting_t object. 2409 - x2: Scratch register. 2410 2411 MOV x0, #(lockaddr) 2412 ... 2413 MOV x1, sp 2414 2415 ; Trigger an event local to this core. So the following WFE 2416 ; instruction is ignored. 2417 SEVL 2418 again: 2419 ; Wait for an event. The event is triggered by either the SEVL 2420 ; or STLR instructions (store release). 2421 WFE 2422 2423 ; Atomically read at lockaddr. This marks the memory location as 2424 ; exclusive. This instruction also has memory constraints which 2425 ; make sure all previous data reads and writes are done before 2426 ; executing it. 2427 LDAXR x2, [x0] 2428 2429 ; Try again if another thread holds the lock. 2430 CBNZ x2, again 2431 2432 ; We can lock it! Write the address of the collecting_t object. 2433 ; This instruction will fail if the memory location is not marked 2434 ; as exclusive anymore. If it succeeds, it will remove the 2435 ; exclusive mark on the memory location. This way, if another 2436 ; thread executes this instruction before us, we will fail and try 2437 ; all over again. 2438 STXR w2, x1, [x0] 2439 CBNZ w2, again 2440 2441 */ 2442 2443 p += emit_mov_addr (p, x0, lockaddr); 2444 p += emit_mov (p, x1, register_operand (sp)); 2445 2446 p += emit_sevl (p); 2447 p += emit_wfe (p); 2448 p += emit_ldaxr (p, x2, x0); 2449 p += emit_cb (p, 1, w2, -2 * 4); 2450 p += emit_stxr (p, w2, x1, x0); 2451 p += emit_cb (p, 1, x2, -4 * 4); 2452 2453 /* Call collector (struct tracepoint *, unsigned char *): 2454 2455 MOV x0, #(tpoint) 2456 ... 2457 2458 ; Saved registers start after the collecting_t object. 2459 ADD x1, sp, #16 2460 2461 ; We use an intra-procedure-call scratch register. 2462 MOV ip0, #(collector) 2463 ... 2464 2465 ; And call back to C! 2466 BLR ip0 2467 2468 */ 2469 2470 p += emit_mov_addr (p, x0, tpoint); 2471 p += emit_add (p, x1, sp, immediate_operand (16)); 2472 2473 p += emit_mov_addr (p, ip0, collector); 2474 p += emit_blr (p, ip0); 2475 2476 /* Release the lock. 2477 2478 MOV x0, #(lockaddr) 2479 ... 2480 2481 ; This instruction is a normal store with memory ordering 2482 ; constraints. Thanks to this we do not have to put a data 2483 ; barrier instruction to make sure all data read and writes are done 2484 ; before this instruction is executed. Furthermore, this instruction 2485 ; will trigger an event, letting other threads know they can grab 2486 ; the lock. 2487 STLR xzr, [x0] 2488 2489 */ 2490 p += emit_mov_addr (p, x0, lockaddr); 2491 p += emit_stlr (p, xzr, x0); 2492 2493 /* Free collecting_t object: 2494 2495 ADD sp, sp, #16 2496 2497 */ 2498 p += emit_add (p, sp, sp, immediate_operand (16)); 2499 2500 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose 2501 registers from the stack. 2502 2503 LDR x2, [sp, #(2 * 16)] 2504 LDR x1, [sp, #(1 * 16)] 2505 LDR x0, [sp, #(0 * 16)] 2506 2507 MSR NZCV, x2 2508 MSR FPSR, x1 2509 MSR FPCR, x0 2510 2511 ADD sp, sp #(5 * 16) 2512 2513 */ 2514 p += emit_ldr (p, x2, sp, offset_memory_operand (2 * 16)); 2515 p += emit_ldr (p, x1, sp, offset_memory_operand (1 * 16)); 2516 p += emit_ldr (p, x0, sp, offset_memory_operand (0 * 16)); 2517 p += emit_msr (p, NZCV, x2); 2518 p += emit_msr (p, FPSR, x1); 2519 p += emit_msr (p, FPCR, x0); 2520 2521 p += emit_add (p, sp, sp, immediate_operand (5 * 16)); 2522 2523 /* Pop general purpose registers: 2524 2525 LDR x0, [sp] 2526 ... 2527 LDR x30, [sp, #(30 * 16)] 2528 2529 ADD sp, sp, #(31 * 16) 2530 2531 */ 2532 for (i = 0; i <= 30; i += 1) 2533 p += emit_ldr (p, aarch64_register (i, 1), sp, 2534 offset_memory_operand (i * 16)); 2535 p += emit_add (p, sp, sp, immediate_operand (31 * 16)); 2536 2537 /* Pop SIMD&FP registers: 2538 2539 LDP q0, q1, [sp] 2540 ... 2541 LDP q30, q31, [sp, #(30 * 16)] 2542 2543 ADD sp, sp, #(32 * 16) 2544 2545 */ 2546 for (i = 0; i <= 30; i += 2) 2547 p += emit_ldp_q_offset (p, i, i + 1, sp, i * 16); 2548 p += emit_add (p, sp, sp, immediate_operand (32 * 16)); 2549 2550 /* Write the code into the inferior memory. */ 2551 append_insns (&buildaddr, p - buf, buf); 2552 2553 /* Now emit the relocated instruction. */ 2554 *adjusted_insn_addr = buildaddr; 2555 target_read_uint32 (tpaddr, &insn); 2556 2557 insn_data.base.insn_addr = tpaddr; 2558 insn_data.new_addr = buildaddr; 2559 insn_data.insn_ptr = buf; 2560 2561 aarch64_relocate_instruction (insn, &visitor, 2562 (struct aarch64_insn_data *) &insn_data); 2563 2564 /* We may not have been able to relocate the instruction. */ 2565 if (insn_data.insn_ptr == buf) 2566 { 2567 sprintf (err, 2568 "E.Could not relocate instruction from %s to %s.", 2569 core_addr_to_string_nz (tpaddr), 2570 core_addr_to_string_nz (buildaddr)); 2571 return 1; 2572 } 2573 else 2574 append_insns (&buildaddr, insn_data.insn_ptr - buf, buf); 2575 *adjusted_insn_addr_end = buildaddr; 2576 2577 /* Go back to the start of the buffer. */ 2578 p = buf; 2579 2580 /* Emit a branch back from the jump pad. */ 2581 offset = (tpaddr + orig_size - buildaddr); 2582 if (!can_encode_int32 (offset, 28)) 2583 { 2584 sprintf (err, 2585 "E.Jump back from jump pad too far from tracepoint " 2586 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).", 2587 offset); 2588 return 1; 2589 } 2590 2591 p += emit_b (p, 0, offset); 2592 append_insns (&buildaddr, p - buf, buf); 2593 2594 /* Give the caller a branch instruction into the jump pad. */ 2595 offset = (*jump_entry - tpaddr); 2596 if (!can_encode_int32 (offset, 28)) 2597 { 2598 sprintf (err, 2599 "E.Jump pad too far from tracepoint " 2600 "(offset 0x%" PRIx64 " cannot be encoded in 28 bits).", 2601 offset); 2602 return 1; 2603 } 2604 2605 emit_b ((uint32_t *) jjump_pad_insn, 0, offset); 2606 *jjump_pad_insn_size = 4; 2607 2608 /* Return the end address of our pad. */ 2609 *jump_entry = buildaddr; 2610 2611 return 0; 2612 } 2613 2614 /* Helper function writing LEN instructions from START into 2615 current_insn_ptr. */ 2616 2617 static void 2618 emit_ops_insns (const uint32_t *start, int len) 2619 { 2620 CORE_ADDR buildaddr = current_insn_ptr; 2621 2622 threads_debug_printf ("Adding %d instructions at %s", 2623 len, paddress (buildaddr)); 2624 2625 append_insns (&buildaddr, len, start); 2626 current_insn_ptr = buildaddr; 2627 } 2628 2629 /* Pop a register from the stack. */ 2630 2631 static int 2632 emit_pop (uint32_t *buf, struct aarch64_register rt) 2633 { 2634 return emit_ldr (buf, rt, sp, postindex_memory_operand (1 * 16)); 2635 } 2636 2637 /* Push a register on the stack. */ 2638 2639 static int 2640 emit_push (uint32_t *buf, struct aarch64_register rt) 2641 { 2642 return emit_str (buf, rt, sp, preindex_memory_operand (-1 * 16)); 2643 } 2644 2645 /* Implementation of emit_ops method "emit_prologue". */ 2646 2647 static void 2648 aarch64_emit_prologue (void) 2649 { 2650 uint32_t buf[16]; 2651 uint32_t *p = buf; 2652 2653 /* This function emit a prologue for the following function prototype: 2654 2655 enum eval_result_type f (unsigned char *regs, 2656 ULONGEST *value); 2657 2658 The first argument is a buffer of raw registers. The second 2659 argument is the result of 2660 evaluating the expression, which will be set to whatever is on top of 2661 the stack at the end. 2662 2663 The stack set up by the prologue is as such: 2664 2665 High *------------------------------------------------------* 2666 | LR | 2667 | FP | <- FP 2668 | x1 (ULONGEST *value) | 2669 | x0 (unsigned char *regs) | 2670 Low *------------------------------------------------------* 2671 2672 As we are implementing a stack machine, each opcode can expand the 2673 stack so we never know how far we are from the data saved by this 2674 prologue. In order to be able refer to value and regs later, we save 2675 the current stack pointer in the frame pointer. This way, it is not 2676 clobbered when calling C functions. 2677 2678 Finally, throughout every operation, we are using register x0 as the 2679 top of the stack, and x1 as a scratch register. */ 2680 2681 p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16)); 2682 p += emit_str (p, lr, sp, offset_memory_operand (3 * 8)); 2683 p += emit_str (p, fp, sp, offset_memory_operand (2 * 8)); 2684 2685 p += emit_add (p, fp, sp, immediate_operand (2 * 8)); 2686 2687 2688 emit_ops_insns (buf, p - buf); 2689 } 2690 2691 /* Implementation of emit_ops method "emit_epilogue". */ 2692 2693 static void 2694 aarch64_emit_epilogue (void) 2695 { 2696 uint32_t buf[16]; 2697 uint32_t *p = buf; 2698 2699 /* Store the result of the expression (x0) in *value. */ 2700 p += emit_sub (p, x1, fp, immediate_operand (1 * 8)); 2701 p += emit_ldr (p, x1, x1, offset_memory_operand (0)); 2702 p += emit_str (p, x0, x1, offset_memory_operand (0)); 2703 2704 /* Restore the previous state. */ 2705 p += emit_add (p, sp, fp, immediate_operand (2 * 8)); 2706 p += emit_ldp (p, fp, lr, fp, offset_memory_operand (0)); 2707 2708 /* Return expr_eval_no_error. */ 2709 p += emit_mov (p, x0, immediate_operand (expr_eval_no_error)); 2710 p += emit_ret (p, lr); 2711 2712 emit_ops_insns (buf, p - buf); 2713 } 2714 2715 /* Implementation of emit_ops method "emit_add". */ 2716 2717 static void 2718 aarch64_emit_add (void) 2719 { 2720 uint32_t buf[16]; 2721 uint32_t *p = buf; 2722 2723 p += emit_pop (p, x1); 2724 p += emit_add (p, x0, x1, register_operand (x0)); 2725 2726 emit_ops_insns (buf, p - buf); 2727 } 2728 2729 /* Implementation of emit_ops method "emit_sub". */ 2730 2731 static void 2732 aarch64_emit_sub (void) 2733 { 2734 uint32_t buf[16]; 2735 uint32_t *p = buf; 2736 2737 p += emit_pop (p, x1); 2738 p += emit_sub (p, x0, x1, register_operand (x0)); 2739 2740 emit_ops_insns (buf, p - buf); 2741 } 2742 2743 /* Implementation of emit_ops method "emit_mul". */ 2744 2745 static void 2746 aarch64_emit_mul (void) 2747 { 2748 uint32_t buf[16]; 2749 uint32_t *p = buf; 2750 2751 p += emit_pop (p, x1); 2752 p += emit_mul (p, x0, x1, x0); 2753 2754 emit_ops_insns (buf, p - buf); 2755 } 2756 2757 /* Implementation of emit_ops method "emit_lsh". */ 2758 2759 static void 2760 aarch64_emit_lsh (void) 2761 { 2762 uint32_t buf[16]; 2763 uint32_t *p = buf; 2764 2765 p += emit_pop (p, x1); 2766 p += emit_lslv (p, x0, x1, x0); 2767 2768 emit_ops_insns (buf, p - buf); 2769 } 2770 2771 /* Implementation of emit_ops method "emit_rsh_signed". */ 2772 2773 static void 2774 aarch64_emit_rsh_signed (void) 2775 { 2776 uint32_t buf[16]; 2777 uint32_t *p = buf; 2778 2779 p += emit_pop (p, x1); 2780 p += emit_asrv (p, x0, x1, x0); 2781 2782 emit_ops_insns (buf, p - buf); 2783 } 2784 2785 /* Implementation of emit_ops method "emit_rsh_unsigned". */ 2786 2787 static void 2788 aarch64_emit_rsh_unsigned (void) 2789 { 2790 uint32_t buf[16]; 2791 uint32_t *p = buf; 2792 2793 p += emit_pop (p, x1); 2794 p += emit_lsrv (p, x0, x1, x0); 2795 2796 emit_ops_insns (buf, p - buf); 2797 } 2798 2799 /* Implementation of emit_ops method "emit_ext". */ 2800 2801 static void 2802 aarch64_emit_ext (int arg) 2803 { 2804 uint32_t buf[16]; 2805 uint32_t *p = buf; 2806 2807 p += emit_sbfx (p, x0, x0, 0, arg); 2808 2809 emit_ops_insns (buf, p - buf); 2810 } 2811 2812 /* Implementation of emit_ops method "emit_log_not". */ 2813 2814 static void 2815 aarch64_emit_log_not (void) 2816 { 2817 uint32_t buf[16]; 2818 uint32_t *p = buf; 2819 2820 /* If the top of the stack is 0, replace it with 1. Else replace it with 2821 0. */ 2822 2823 p += emit_cmp (p, x0, immediate_operand (0)); 2824 p += emit_cset (p, x0, EQ); 2825 2826 emit_ops_insns (buf, p - buf); 2827 } 2828 2829 /* Implementation of emit_ops method "emit_bit_and". */ 2830 2831 static void 2832 aarch64_emit_bit_and (void) 2833 { 2834 uint32_t buf[16]; 2835 uint32_t *p = buf; 2836 2837 p += emit_pop (p, x1); 2838 p += emit_and (p, x0, x0, x1); 2839 2840 emit_ops_insns (buf, p - buf); 2841 } 2842 2843 /* Implementation of emit_ops method "emit_bit_or". */ 2844 2845 static void 2846 aarch64_emit_bit_or (void) 2847 { 2848 uint32_t buf[16]; 2849 uint32_t *p = buf; 2850 2851 p += emit_pop (p, x1); 2852 p += emit_orr (p, x0, x0, x1); 2853 2854 emit_ops_insns (buf, p - buf); 2855 } 2856 2857 /* Implementation of emit_ops method "emit_bit_xor". */ 2858 2859 static void 2860 aarch64_emit_bit_xor (void) 2861 { 2862 uint32_t buf[16]; 2863 uint32_t *p = buf; 2864 2865 p += emit_pop (p, x1); 2866 p += emit_eor (p, x0, x0, x1); 2867 2868 emit_ops_insns (buf, p - buf); 2869 } 2870 2871 /* Implementation of emit_ops method "emit_bit_not". */ 2872 2873 static void 2874 aarch64_emit_bit_not (void) 2875 { 2876 uint32_t buf[16]; 2877 uint32_t *p = buf; 2878 2879 p += emit_mvn (p, x0, x0); 2880 2881 emit_ops_insns (buf, p - buf); 2882 } 2883 2884 /* Implementation of emit_ops method "emit_equal". */ 2885 2886 static void 2887 aarch64_emit_equal (void) 2888 { 2889 uint32_t buf[16]; 2890 uint32_t *p = buf; 2891 2892 p += emit_pop (p, x1); 2893 p += emit_cmp (p, x0, register_operand (x1)); 2894 p += emit_cset (p, x0, EQ); 2895 2896 emit_ops_insns (buf, p - buf); 2897 } 2898 2899 /* Implementation of emit_ops method "emit_less_signed". */ 2900 2901 static void 2902 aarch64_emit_less_signed (void) 2903 { 2904 uint32_t buf[16]; 2905 uint32_t *p = buf; 2906 2907 p += emit_pop (p, x1); 2908 p += emit_cmp (p, x1, register_operand (x0)); 2909 p += emit_cset (p, x0, LT); 2910 2911 emit_ops_insns (buf, p - buf); 2912 } 2913 2914 /* Implementation of emit_ops method "emit_less_unsigned". */ 2915 2916 static void 2917 aarch64_emit_less_unsigned (void) 2918 { 2919 uint32_t buf[16]; 2920 uint32_t *p = buf; 2921 2922 p += emit_pop (p, x1); 2923 p += emit_cmp (p, x1, register_operand (x0)); 2924 p += emit_cset (p, x0, LO); 2925 2926 emit_ops_insns (buf, p - buf); 2927 } 2928 2929 /* Implementation of emit_ops method "emit_ref". */ 2930 2931 static void 2932 aarch64_emit_ref (int size) 2933 { 2934 uint32_t buf[16]; 2935 uint32_t *p = buf; 2936 2937 switch (size) 2938 { 2939 case 1: 2940 p += emit_ldrb (p, w0, x0, offset_memory_operand (0)); 2941 break; 2942 case 2: 2943 p += emit_ldrh (p, w0, x0, offset_memory_operand (0)); 2944 break; 2945 case 4: 2946 p += emit_ldr (p, w0, x0, offset_memory_operand (0)); 2947 break; 2948 case 8: 2949 p += emit_ldr (p, x0, x0, offset_memory_operand (0)); 2950 break; 2951 default: 2952 /* Unknown size, bail on compilation. */ 2953 emit_error = 1; 2954 break; 2955 } 2956 2957 emit_ops_insns (buf, p - buf); 2958 } 2959 2960 /* Implementation of emit_ops method "emit_if_goto". */ 2961 2962 static void 2963 aarch64_emit_if_goto (int *offset_p, int *size_p) 2964 { 2965 uint32_t buf[16]; 2966 uint32_t *p = buf; 2967 2968 /* The Z flag is set or cleared here. */ 2969 p += emit_cmp (p, x0, immediate_operand (0)); 2970 /* This instruction must not change the Z flag. */ 2971 p += emit_pop (p, x0); 2972 /* Branch over the next instruction if x0 == 0. */ 2973 p += emit_bcond (p, EQ, 8); 2974 2975 /* The NOP instruction will be patched with an unconditional branch. */ 2976 if (offset_p) 2977 *offset_p = (p - buf) * 4; 2978 if (size_p) 2979 *size_p = 4; 2980 p += emit_nop (p); 2981 2982 emit_ops_insns (buf, p - buf); 2983 } 2984 2985 /* Implementation of emit_ops method "emit_goto". */ 2986 2987 static void 2988 aarch64_emit_goto (int *offset_p, int *size_p) 2989 { 2990 uint32_t buf[16]; 2991 uint32_t *p = buf; 2992 2993 /* The NOP instruction will be patched with an unconditional branch. */ 2994 if (offset_p) 2995 *offset_p = 0; 2996 if (size_p) 2997 *size_p = 4; 2998 p += emit_nop (p); 2999 3000 emit_ops_insns (buf, p - buf); 3001 } 3002 3003 /* Implementation of emit_ops method "write_goto_address". */ 3004 3005 static void 3006 aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) 3007 { 3008 uint32_t insn; 3009 3010 emit_b (&insn, 0, to - from); 3011 append_insns (&from, 1, &insn); 3012 } 3013 3014 /* Implementation of emit_ops method "emit_const". */ 3015 3016 static void 3017 aarch64_emit_const (LONGEST num) 3018 { 3019 uint32_t buf[16]; 3020 uint32_t *p = buf; 3021 3022 p += emit_mov_addr (p, x0, num); 3023 3024 emit_ops_insns (buf, p - buf); 3025 } 3026 3027 /* Implementation of emit_ops method "emit_call". */ 3028 3029 static void 3030 aarch64_emit_call (CORE_ADDR fn) 3031 { 3032 uint32_t buf[16]; 3033 uint32_t *p = buf; 3034 3035 p += emit_mov_addr (p, ip0, fn); 3036 p += emit_blr (p, ip0); 3037 3038 emit_ops_insns (buf, p - buf); 3039 } 3040 3041 /* Implementation of emit_ops method "emit_reg". */ 3042 3043 static void 3044 aarch64_emit_reg (int reg) 3045 { 3046 uint32_t buf[16]; 3047 uint32_t *p = buf; 3048 3049 /* Set x0 to unsigned char *regs. */ 3050 p += emit_sub (p, x0, fp, immediate_operand (2 * 8)); 3051 p += emit_ldr (p, x0, x0, offset_memory_operand (0)); 3052 p += emit_mov (p, x1, immediate_operand (reg)); 3053 3054 emit_ops_insns (buf, p - buf); 3055 3056 aarch64_emit_call (get_raw_reg_func_addr ()); 3057 } 3058 3059 /* Implementation of emit_ops method "emit_pop". */ 3060 3061 static void 3062 aarch64_emit_pop (void) 3063 { 3064 uint32_t buf[16]; 3065 uint32_t *p = buf; 3066 3067 p += emit_pop (p, x0); 3068 3069 emit_ops_insns (buf, p - buf); 3070 } 3071 3072 /* Implementation of emit_ops method "emit_stack_flush". */ 3073 3074 static void 3075 aarch64_emit_stack_flush (void) 3076 { 3077 uint32_t buf[16]; 3078 uint32_t *p = buf; 3079 3080 p += emit_push (p, x0); 3081 3082 emit_ops_insns (buf, p - buf); 3083 } 3084 3085 /* Implementation of emit_ops method "emit_zero_ext". */ 3086 3087 static void 3088 aarch64_emit_zero_ext (int arg) 3089 { 3090 uint32_t buf[16]; 3091 uint32_t *p = buf; 3092 3093 p += emit_ubfx (p, x0, x0, 0, arg); 3094 3095 emit_ops_insns (buf, p - buf); 3096 } 3097 3098 /* Implementation of emit_ops method "emit_swap". */ 3099 3100 static void 3101 aarch64_emit_swap (void) 3102 { 3103 uint32_t buf[16]; 3104 uint32_t *p = buf; 3105 3106 p += emit_ldr (p, x1, sp, offset_memory_operand (0 * 16)); 3107 p += emit_str (p, x0, sp, offset_memory_operand (0 * 16)); 3108 p += emit_mov (p, x0, register_operand (x1)); 3109 3110 emit_ops_insns (buf, p - buf); 3111 } 3112 3113 /* Implementation of emit_ops method "emit_stack_adjust". */ 3114 3115 static void 3116 aarch64_emit_stack_adjust (int n) 3117 { 3118 /* This is not needed with our design. */ 3119 uint32_t buf[16]; 3120 uint32_t *p = buf; 3121 3122 p += emit_add (p, sp, sp, immediate_operand (n * 16)); 3123 3124 emit_ops_insns (buf, p - buf); 3125 } 3126 3127 /* Implementation of emit_ops method "emit_int_call_1". */ 3128 3129 static void 3130 aarch64_emit_int_call_1 (CORE_ADDR fn, int arg1) 3131 { 3132 uint32_t buf[16]; 3133 uint32_t *p = buf; 3134 3135 p += emit_mov (p, x0, immediate_operand (arg1)); 3136 3137 emit_ops_insns (buf, p - buf); 3138 3139 aarch64_emit_call (fn); 3140 } 3141 3142 /* Implementation of emit_ops method "emit_void_call_2". */ 3143 3144 static void 3145 aarch64_emit_void_call_2 (CORE_ADDR fn, int arg1) 3146 { 3147 uint32_t buf[16]; 3148 uint32_t *p = buf; 3149 3150 /* Push x0 on the stack. */ 3151 aarch64_emit_stack_flush (); 3152 3153 /* Setup arguments for the function call: 3154 3155 x0: arg1 3156 x1: top of the stack 3157 3158 MOV x1, x0 3159 MOV x0, #arg1 */ 3160 3161 p += emit_mov (p, x1, register_operand (x0)); 3162 p += emit_mov (p, x0, immediate_operand (arg1)); 3163 3164 emit_ops_insns (buf, p - buf); 3165 3166 aarch64_emit_call (fn); 3167 3168 /* Restore x0. */ 3169 aarch64_emit_pop (); 3170 } 3171 3172 /* Implementation of emit_ops method "emit_eq_goto". */ 3173 3174 static void 3175 aarch64_emit_eq_goto (int *offset_p, int *size_p) 3176 { 3177 uint32_t buf[16]; 3178 uint32_t *p = buf; 3179 3180 p += emit_pop (p, x1); 3181 p += emit_cmp (p, x1, register_operand (x0)); 3182 /* Branch over the next instruction if x0 != x1. */ 3183 p += emit_bcond (p, NE, 8); 3184 /* The NOP instruction will be patched with an unconditional branch. */ 3185 if (offset_p) 3186 *offset_p = (p - buf) * 4; 3187 if (size_p) 3188 *size_p = 4; 3189 p += emit_nop (p); 3190 3191 emit_ops_insns (buf, p - buf); 3192 } 3193 3194 /* Implementation of emit_ops method "emit_ne_goto". */ 3195 3196 static void 3197 aarch64_emit_ne_goto (int *offset_p, int *size_p) 3198 { 3199 uint32_t buf[16]; 3200 uint32_t *p = buf; 3201 3202 p += emit_pop (p, x1); 3203 p += emit_cmp (p, x1, register_operand (x0)); 3204 /* Branch over the next instruction if x0 == x1. */ 3205 p += emit_bcond (p, EQ, 8); 3206 /* The NOP instruction will be patched with an unconditional branch. */ 3207 if (offset_p) 3208 *offset_p = (p - buf) * 4; 3209 if (size_p) 3210 *size_p = 4; 3211 p += emit_nop (p); 3212 3213 emit_ops_insns (buf, p - buf); 3214 } 3215 3216 /* Implementation of emit_ops method "emit_lt_goto". */ 3217 3218 static void 3219 aarch64_emit_lt_goto (int *offset_p, int *size_p) 3220 { 3221 uint32_t buf[16]; 3222 uint32_t *p = buf; 3223 3224 p += emit_pop (p, x1); 3225 p += emit_cmp (p, x1, register_operand (x0)); 3226 /* Branch over the next instruction if x0 >= x1. */ 3227 p += emit_bcond (p, GE, 8); 3228 /* The NOP instruction will be patched with an unconditional branch. */ 3229 if (offset_p) 3230 *offset_p = (p - buf) * 4; 3231 if (size_p) 3232 *size_p = 4; 3233 p += emit_nop (p); 3234 3235 emit_ops_insns (buf, p - buf); 3236 } 3237 3238 /* Implementation of emit_ops method "emit_le_goto". */ 3239 3240 static void 3241 aarch64_emit_le_goto (int *offset_p, int *size_p) 3242 { 3243 uint32_t buf[16]; 3244 uint32_t *p = buf; 3245 3246 p += emit_pop (p, x1); 3247 p += emit_cmp (p, x1, register_operand (x0)); 3248 /* Branch over the next instruction if x0 > x1. */ 3249 p += emit_bcond (p, GT, 8); 3250 /* The NOP instruction will be patched with an unconditional branch. */ 3251 if (offset_p) 3252 *offset_p = (p - buf) * 4; 3253 if (size_p) 3254 *size_p = 4; 3255 p += emit_nop (p); 3256 3257 emit_ops_insns (buf, p - buf); 3258 } 3259 3260 /* Implementation of emit_ops method "emit_gt_goto". */ 3261 3262 static void 3263 aarch64_emit_gt_goto (int *offset_p, int *size_p) 3264 { 3265 uint32_t buf[16]; 3266 uint32_t *p = buf; 3267 3268 p += emit_pop (p, x1); 3269 p += emit_cmp (p, x1, register_operand (x0)); 3270 /* Branch over the next instruction if x0 <= x1. */ 3271 p += emit_bcond (p, LE, 8); 3272 /* The NOP instruction will be patched with an unconditional branch. */ 3273 if (offset_p) 3274 *offset_p = (p - buf) * 4; 3275 if (size_p) 3276 *size_p = 4; 3277 p += emit_nop (p); 3278 3279 emit_ops_insns (buf, p - buf); 3280 } 3281 3282 /* Implementation of emit_ops method "emit_ge_got". */ 3283 3284 static void 3285 aarch64_emit_ge_got (int *offset_p, int *size_p) 3286 { 3287 uint32_t buf[16]; 3288 uint32_t *p = buf; 3289 3290 p += emit_pop (p, x1); 3291 p += emit_cmp (p, x1, register_operand (x0)); 3292 /* Branch over the next instruction if x0 <= x1. */ 3293 p += emit_bcond (p, LT, 8); 3294 /* The NOP instruction will be patched with an unconditional branch. */ 3295 if (offset_p) 3296 *offset_p = (p - buf) * 4; 3297 if (size_p) 3298 *size_p = 4; 3299 p += emit_nop (p); 3300 3301 emit_ops_insns (buf, p - buf); 3302 } 3303 3304 static struct emit_ops aarch64_emit_ops_impl = 3305 { 3306 aarch64_emit_prologue, 3307 aarch64_emit_epilogue, 3308 aarch64_emit_add, 3309 aarch64_emit_sub, 3310 aarch64_emit_mul, 3311 aarch64_emit_lsh, 3312 aarch64_emit_rsh_signed, 3313 aarch64_emit_rsh_unsigned, 3314 aarch64_emit_ext, 3315 aarch64_emit_log_not, 3316 aarch64_emit_bit_and, 3317 aarch64_emit_bit_or, 3318 aarch64_emit_bit_xor, 3319 aarch64_emit_bit_not, 3320 aarch64_emit_equal, 3321 aarch64_emit_less_signed, 3322 aarch64_emit_less_unsigned, 3323 aarch64_emit_ref, 3324 aarch64_emit_if_goto, 3325 aarch64_emit_goto, 3326 aarch64_write_goto_address, 3327 aarch64_emit_const, 3328 aarch64_emit_call, 3329 aarch64_emit_reg, 3330 aarch64_emit_pop, 3331 aarch64_emit_stack_flush, 3332 aarch64_emit_zero_ext, 3333 aarch64_emit_swap, 3334 aarch64_emit_stack_adjust, 3335 aarch64_emit_int_call_1, 3336 aarch64_emit_void_call_2, 3337 aarch64_emit_eq_goto, 3338 aarch64_emit_ne_goto, 3339 aarch64_emit_lt_goto, 3340 aarch64_emit_le_goto, 3341 aarch64_emit_gt_goto, 3342 aarch64_emit_ge_got, 3343 }; 3344 3345 /* Implementation of target ops method "emit_ops". */ 3346 3347 emit_ops * 3348 aarch64_target::emit_ops () 3349 { 3350 return &aarch64_emit_ops_impl; 3351 } 3352 3353 /* Implementation of target ops method 3354 "get_min_fast_tracepoint_insn_len". */ 3355 3356 int 3357 aarch64_target::get_min_fast_tracepoint_insn_len () 3358 { 3359 return 4; 3360 } 3361 3362 /* Implementation of linux target ops method "low_supports_range_stepping". */ 3363 3364 bool 3365 aarch64_target::low_supports_range_stepping () 3366 { 3367 return true; 3368 } 3369 3370 /* Implementation of target ops method "sw_breakpoint_from_kind". */ 3371 3372 const gdb_byte * 3373 aarch64_target::sw_breakpoint_from_kind (int kind, int *size) 3374 { 3375 if (is_64bit_tdesc ()) 3376 { 3377 *size = aarch64_breakpoint_len; 3378 return aarch64_breakpoint; 3379 } 3380 else 3381 return arm_sw_breakpoint_from_kind (kind, size); 3382 } 3383 3384 /* Implementation of target ops method "breakpoint_kind_from_pc". */ 3385 3386 int 3387 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) 3388 { 3389 if (is_64bit_tdesc ()) 3390 return aarch64_breakpoint_len; 3391 else 3392 return arm_breakpoint_kind_from_pc (pcptr); 3393 } 3394 3395 /* Implementation of the target ops method 3396 "breakpoint_kind_from_current_state". */ 3397 3398 int 3399 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) 3400 { 3401 if (is_64bit_tdesc ()) 3402 return aarch64_breakpoint_len; 3403 else 3404 return arm_breakpoint_kind_from_current_state (pcptr); 3405 } 3406 3407 /* Returns true if memory tagging is supported. */ 3408 bool 3409 aarch64_target::supports_memory_tagging () 3410 { 3411 if (current_thread == NULL) 3412 { 3413 /* We don't have any processes running, so don't attempt to 3414 use linux_get_hwcap2 as it will try to fetch the current 3415 thread id. Instead, just fetch the auxv from the self 3416 PID. */ 3417 #ifdef HAVE_GETAUXVAL 3418 return (getauxval (AT_HWCAP2) & HWCAP2_MTE) != 0; 3419 #else 3420 return true; 3421 #endif 3422 } 3423 3424 return (linux_get_hwcap2 (current_thread->id.pid (), 8) & HWCAP2_MTE) != 0; 3425 } 3426 3427 bool 3428 aarch64_target::fetch_memtags (CORE_ADDR address, size_t len, 3429 gdb::byte_vector &tags, int type) 3430 { 3431 /* Allocation tags are per-process, so any tid is fine. */ 3432 int tid = current_thread->id.lwp (); 3433 3434 /* Allocation tag? */ 3435 if (type == static_cast <int> (aarch64_memtag_type::mte_allocation)) 3436 return aarch64_mte_fetch_memtags (tid, address, len, tags); 3437 3438 return false; 3439 } 3440 3441 bool 3442 aarch64_target::store_memtags (CORE_ADDR address, size_t len, 3443 const gdb::byte_vector &tags, int type) 3444 { 3445 /* Allocation tags are per-process, so any tid is fine. */ 3446 int tid = current_thread->id.lwp (); 3447 3448 /* Allocation tag? */ 3449 if (type == static_cast <int> (aarch64_memtag_type::mte_allocation)) 3450 return aarch64_mte_store_memtags (tid, address, len, tags); 3451 3452 return false; 3453 } 3454 3455 /* The linux target ops object. */ 3456 3457 linux_process_target *the_linux_target = &the_aarch64_target; 3458 3459 void 3460 initialize_low_arch (void) 3461 { 3462 initialize_low_arch_aarch32 (); 3463 3464 initialize_regsets_info (&aarch64_regsets_info); 3465 } 3466
Indexes created Sun Mar 01 05:31:48 UTC 2026