aarch64.h revision 1.1.1.1
1 /* AArch64 assembler/disassembler support. 2 3 Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 /* The offset for pc-relative addressing is currently defined to be 0. */ 31 #define AARCH64_PCREL_OFFSET 0 32 33 typedef uint32_t aarch64_insn; 34 35 /* The following bitmasks control CPU features. */ 36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 40 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 41 42 /* Architectures are the sum of the base and extensions. */ 43 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 44 AARCH64_FEATURE_FP \ 45 | AARCH64_FEATURE_SIMD) 46 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 47 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 48 49 /* CPU-specific features. */ 50 typedef unsigned long aarch64_feature_set; 51 52 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 53 (((CPU) & (FEAT)) != 0) 54 55 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 56 do \ 57 { \ 58 (TARG) = (F1) | (F2); \ 59 } \ 60 while (0) 61 62 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 63 do \ 64 { \ 65 (TARG) = (F1) &~ (F2); \ 66 } \ 67 while (0) 68 69 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 70 71 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ 72 (((OPC) & (FEAT)) != 0) 73 74 enum aarch64_operand_class 75 { 76 AARCH64_OPND_CLASS_NIL, 77 AARCH64_OPND_CLASS_INT_REG, 78 AARCH64_OPND_CLASS_MODIFIED_REG, 79 AARCH64_OPND_CLASS_FP_REG, 80 AARCH64_OPND_CLASS_SIMD_REG, 81 AARCH64_OPND_CLASS_SIMD_ELEMENT, 82 AARCH64_OPND_CLASS_SISD_REG, 83 AARCH64_OPND_CLASS_SIMD_REGLIST, 84 AARCH64_OPND_CLASS_CP_REG, 85 AARCH64_OPND_CLASS_ADDRESS, 86 AARCH64_OPND_CLASS_IMMEDIATE, 87 AARCH64_OPND_CLASS_SYSTEM, 88 }; 89 90 /* Operand code that helps both parsing and coding. 91 Keep AARCH64_OPERANDS synced. */ 92 93 enum aarch64_opnd 94 { 95 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 96 97 AARCH64_OPND_Rd, /* Integer register as destination. */ 98 AARCH64_OPND_Rn, /* Integer register as source. */ 99 AARCH64_OPND_Rm, /* Integer register as source. */ 100 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 101 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 102 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 103 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 104 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 105 106 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 107 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 108 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 109 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 110 111 AARCH64_OPND_Fd, /* Floating-point Fd. */ 112 AARCH64_OPND_Fn, /* Floating-point Fn. */ 113 AARCH64_OPND_Fm, /* Floating-point Fm. */ 114 AARCH64_OPND_Fa, /* Floating-point Fa. */ 115 AARCH64_OPND_Ft, /* Floating-point Ft. */ 116 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 117 118 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 119 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 120 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 121 122 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 123 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 124 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 125 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 126 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 127 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 128 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 129 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 130 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 131 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 132 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 133 structure to all lanes. */ 134 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 135 136 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 137 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 138 139 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 140 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 141 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 142 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 143 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 144 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 145 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 146 (no encoding). */ 147 AARCH64_OPND_IMM0, /* Immediate for #0. */ 148 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 149 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 150 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 151 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 152 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 153 AARCH64_OPND_IMM, /* Immediate. */ 154 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 155 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 156 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 157 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 158 AARCH64_OPND_BIT_NUM, /* Immediate. */ 159 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 160 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 161 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 162 each condition flag. */ 163 164 AARCH64_OPND_LIMM, /* Logical Immediate. */ 165 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 166 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 167 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 168 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 169 170 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 171 172 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 173 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 174 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 175 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 176 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 177 178 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 179 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 180 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 181 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 182 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 183 negative or unaligned and there is 184 no writeback allowed. This operand code 185 is only used to support the programmer- 186 friendly feature of using LDR/STR as the 187 the mnemonic name for LDUR/STUR instructions 188 wherever there is no ambiguity. */ 189 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 190 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 191 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 192 193 AARCH64_OPND_SYSREG, /* System register operand. */ 194 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 195 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 196 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 197 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 198 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 199 AARCH64_OPND_BARRIER, /* Barrier operand. */ 200 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 201 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 202 }; 203 204 /* Qualifier constrains an operand. It either specifies a variant of an 205 operand type or limits values available to an operand type. 206 207 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 208 209 enum aarch64_opnd_qualifier 210 { 211 /* Indicating no further qualification on an operand. */ 212 AARCH64_OPND_QLF_NIL, 213 214 /* Qualifying an operand which is a general purpose (integer) register; 215 indicating the operand data size or a specific register. */ 216 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 217 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 218 AARCH64_OPND_QLF_WSP, /* WSP. */ 219 AARCH64_OPND_QLF_SP, /* SP. */ 220 221 /* Qualifying an operand which is a floating-point register, a SIMD 222 vector element or a SIMD vector element list; indicating operand data 223 size or the size of each SIMD vector element in the case of a SIMD 224 vector element list. 225 These qualifiers are also used to qualify an address operand to 226 indicate the size of data element a load/store instruction is 227 accessing. 228 They are also used for the immediate shift operand in e.g. SSHR. Such 229 a use is only for the ease of operand encoding/decoding and qualifier 230 sequence matching; such a use should not be applied widely; use the value 231 constraint qualifiers for immediate operands wherever possible. */ 232 AARCH64_OPND_QLF_S_B, 233 AARCH64_OPND_QLF_S_H, 234 AARCH64_OPND_QLF_S_S, 235 AARCH64_OPND_QLF_S_D, 236 AARCH64_OPND_QLF_S_Q, 237 238 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 239 register list; indicating register shape. 240 They are also used for the immediate shift operand in e.g. SSHR. Such 241 a use is only for the ease of operand encoding/decoding and qualifier 242 sequence matching; such a use should not be applied widely; use the value 243 constraint qualifiers for immediate operands wherever possible. */ 244 AARCH64_OPND_QLF_V_8B, 245 AARCH64_OPND_QLF_V_16B, 246 AARCH64_OPND_QLF_V_4H, 247 AARCH64_OPND_QLF_V_8H, 248 AARCH64_OPND_QLF_V_2S, 249 AARCH64_OPND_QLF_V_4S, 250 AARCH64_OPND_QLF_V_1D, 251 AARCH64_OPND_QLF_V_2D, 252 AARCH64_OPND_QLF_V_1Q, 253 254 /* Constraint on value. */ 255 AARCH64_OPND_QLF_imm_0_7, 256 AARCH64_OPND_QLF_imm_0_15, 257 AARCH64_OPND_QLF_imm_0_31, 258 AARCH64_OPND_QLF_imm_0_63, 259 AARCH64_OPND_QLF_imm_1_32, 260 AARCH64_OPND_QLF_imm_1_64, 261 262 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 263 or shift-ones. */ 264 AARCH64_OPND_QLF_LSL, 265 AARCH64_OPND_QLF_MSL, 266 267 /* Special qualifier helping retrieve qualifier information during the 268 decoding time (currently not in use). */ 269 AARCH64_OPND_QLF_RETRIEVE, 270 }; 271 272 /* Instruction class. */ 274 275 enum aarch64_insn_class 276 { 277 addsub_carry, 278 addsub_ext, 279 addsub_imm, 280 addsub_shift, 281 asimdall, 282 asimddiff, 283 asimdelem, 284 asimdext, 285 asimdimm, 286 asimdins, 287 asimdmisc, 288 asimdperm, 289 asimdsame, 290 asimdshf, 291 asimdtbl, 292 asisddiff, 293 asisdelem, 294 asisdlse, 295 asisdlsep, 296 asisdlso, 297 asisdlsop, 298 asisdmisc, 299 asisdone, 300 asisdpair, 301 asisdsame, 302 asisdshf, 303 bitfield, 304 branch_imm, 305 branch_reg, 306 compbranch, 307 condbranch, 308 condcmp_imm, 309 condcmp_reg, 310 condsel, 311 cryptoaes, 312 cryptosha2, 313 cryptosha3, 314 dp_1src, 315 dp_2src, 316 dp_3src, 317 exception, 318 extract, 319 float2fix, 320 float2int, 321 floatccmp, 322 floatcmp, 323 floatdp1, 324 floatdp2, 325 floatdp3, 326 floatimm, 327 floatsel, 328 ldst_immpost, 329 ldst_immpre, 330 ldst_imm9, /* immpost or immpre */ 331 ldst_pos, 332 ldst_regoff, 333 ldst_unpriv, 334 ldst_unscaled, 335 ldstexcl, 336 ldstnapair_offs, 337 ldstpair_off, 338 ldstpair_indexed, 339 loadlit, 340 log_imm, 341 log_shift, 342 movewide, 343 pcreladdr, 344 ic_system, 345 testbranch, 346 }; 347 348 /* Opcode enumerators. */ 349 350 enum aarch64_op 351 { 352 OP_NIL, 353 OP_STRB_POS, 354 OP_LDRB_POS, 355 OP_LDRSB_POS, 356 OP_STRH_POS, 357 OP_LDRH_POS, 358 OP_LDRSH_POS, 359 OP_STR_POS, 360 OP_LDR_POS, 361 OP_STRF_POS, 362 OP_LDRF_POS, 363 OP_LDRSW_POS, 364 OP_PRFM_POS, 365 366 OP_STURB, 367 OP_LDURB, 368 OP_LDURSB, 369 OP_STURH, 370 OP_LDURH, 371 OP_LDURSH, 372 OP_STUR, 373 OP_LDUR, 374 OP_STURV, 375 OP_LDURV, 376 OP_LDURSW, 377 OP_PRFUM, 378 379 OP_LDR_LIT, 380 OP_LDRV_LIT, 381 OP_LDRSW_LIT, 382 OP_PRFM_LIT, 383 384 OP_ADD, 385 OP_B, 386 OP_BL, 387 388 OP_MOVN, 389 OP_MOVZ, 390 OP_MOVK, 391 392 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 393 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 394 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 395 396 OP_MOV_V, /* MOV alias for moving vector register. */ 397 398 OP_ASR_IMM, 399 OP_LSR_IMM, 400 OP_LSL_IMM, 401 402 OP_BIC, 403 404 OP_UBFX, 405 OP_BFXIL, 406 OP_SBFX, 407 OP_SBFIZ, 408 OP_BFI, 409 OP_UBFIZ, 410 OP_UXTB, 411 OP_UXTH, 412 OP_UXTW, 413 414 OP_CINC, 415 OP_CINV, 416 OP_CNEG, 417 OP_CSET, 418 OP_CSETM, 419 420 OP_FCVT, 421 OP_FCVTN, 422 OP_FCVTN2, 423 OP_FCVTL, 424 OP_FCVTL2, 425 OP_FCVTXN_S, /* Scalar version. */ 426 427 OP_ROR_IMM, 428 429 OP_SXTL, 430 OP_SXTL2, 431 OP_UXTL, 432 OP_UXTL2, 433 434 OP_TOTAL_NUM, /* Pseudo. */ 435 }; 436 437 /* Maximum number of operands an instruction can have. */ 438 #define AARCH64_MAX_OPND_NUM 6 439 /* Maximum number of qualifier sequences an instruction can have. */ 440 #define AARCH64_MAX_QLF_SEQ_NUM 10 441 /* Operand qualifier typedef; optimized for the size. */ 442 typedef unsigned char aarch64_opnd_qualifier_t; 443 /* Operand qualifier sequence typedef. */ 444 typedef aarch64_opnd_qualifier_t \ 445 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 446 447 /* FIXME: improve the efficiency. */ 448 static inline bfd_boolean 449 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 450 { 451 int i; 452 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 453 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 454 return FALSE; 455 return TRUE; 456 } 457 458 /* This structure holds information for a particular opcode. */ 459 460 struct aarch64_opcode 461 { 462 /* The name of the mnemonic. */ 463 const char *name; 464 465 /* The opcode itself. Those bits which will be filled in with 466 operands are zeroes. */ 467 aarch64_insn opcode; 468 469 /* The opcode mask. This is used by the disassembler. This is a 470 mask containing ones indicating those bits which must match the 471 opcode field, and zeroes indicating those bits which need not 472 match (and are presumably filled in by operands). */ 473 aarch64_insn mask; 474 475 /* Instruction class. */ 476 enum aarch64_insn_class iclass; 477 478 /* Enumerator identifier. */ 479 enum aarch64_op op; 480 481 /* Which architecture variant provides this instruction. */ 482 const aarch64_feature_set *avariant; 483 484 /* An array of operand codes. Each code is an index into the 485 operand table. They appear in the order which the operands must 486 appear in assembly code, and are terminated by a zero. */ 487 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 488 489 /* A list of operand qualifier code sequence. Each operand qualifier 490 code qualifies the corresponding operand code. Each operand 491 qualifier sequence specifies a valid opcode variant and related 492 constraint on operands. */ 493 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 494 495 /* Flags providing information about this instruction */ 496 uint32_t flags; 497 }; 498 499 typedef struct aarch64_opcode aarch64_opcode; 500 501 /* Table describing all the AArch64 opcodes. */ 502 extern aarch64_opcode aarch64_opcode_table[]; 503 504 /* Opcode flags. */ 505 #define F_ALIAS (1 << 0) 506 #define F_HAS_ALIAS (1 << 1) 507 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 508 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 509 #define F_P1 (1 << 2) 510 #define F_P2 (2 << 2) 511 #define F_P3 (3 << 2) 512 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 513 #define F_COND (1 << 4) 514 /* Instruction has the field of 'sf'. */ 515 #define F_SF (1 << 5) 516 /* Instruction has the field of 'size:Q'. */ 517 #define F_SIZEQ (1 << 6) 518 /* Floating-point instruction has the field of 'type'. */ 519 #define F_FPTYPE (1 << 7) 520 /* AdvSIMD scalar instruction has the field of 'size'. */ 521 #define F_SSIZE (1 << 8) 522 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 523 #define F_T (1 << 9) 524 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 525 #define F_GPRSIZE_IN_Q (1 << 10) 526 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 527 #define F_LDS_SIZE (1 << 11) 528 /* Optional operand; assume maximum of 1 operand can be optional. */ 529 #define F_OPD0_OPT (1 << 12) 530 #define F_OPD1_OPT (2 << 12) 531 #define F_OPD2_OPT (3 << 12) 532 #define F_OPD3_OPT (4 << 12) 533 #define F_OPD4_OPT (5 << 12) 534 /* Default value for the optional operand when omitted from the assembly. */ 535 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 536 /* Instruction that is an alias of another instruction needs to be 537 encoded/decoded by converting it to/from the real form, followed by 538 the encoding/decoding according to the rules of the real opcode. 539 This compares to the direct coding using the alias's information. 540 N.B. this flag requires F_ALIAS to be used together. */ 541 #define F_CONV (1 << 20) 542 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 543 friendly pseudo instruction available only in the assembly code (thus will 544 not show up in the disassembly). */ 545 #define F_PSEUDO (1 << 21) 546 /* Instruction has miscellaneous encoding/decoding rules. */ 547 #define F_MISC (1 << 22) 548 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 549 #define F_N (1 << 23) 550 /* Opcode dependent field. */ 551 #define F_OD(X) (((X) & 0x7) << 24) 552 /* Next bit is 27. */ 553 554 static inline bfd_boolean 555 alias_opcode_p (const aarch64_opcode *opcode) 556 { 557 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 558 } 559 560 static inline bfd_boolean 561 opcode_has_alias (const aarch64_opcode *opcode) 562 { 563 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 564 } 565 566 /* Priority for disassembling preference. */ 567 static inline int 568 opcode_priority (const aarch64_opcode *opcode) 569 { 570 return (opcode->flags >> 2) & 0x3; 571 } 572 573 static inline bfd_boolean 574 pseudo_opcode_p (const aarch64_opcode *opcode) 575 { 576 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 577 } 578 579 static inline bfd_boolean 580 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 581 { 582 return (((opcode->flags >> 12) & 0x7) == idx + 1) 583 ? TRUE : FALSE; 584 } 585 586 static inline aarch64_insn 587 get_optional_operand_default_value (const aarch64_opcode *opcode) 588 { 589 return (opcode->flags >> 15) & 0x1f; 590 } 591 592 static inline unsigned int 593 get_opcode_dependent_value (const aarch64_opcode *opcode) 594 { 595 return (opcode->flags >> 24) & 0x7; 596 } 597 598 static inline bfd_boolean 599 opcode_has_special_coder (const aarch64_opcode *opcode) 600 { 601 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 602 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 603 : FALSE; 604 } 605 606 struct aarch64_name_value_pair 608 { 609 const char * name; 610 aarch64_insn value; 611 }; 612 613 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 614 extern const struct aarch64_name_value_pair aarch64_sys_regs []; 615 extern const struct aarch64_name_value_pair aarch64_pstatefields []; 616 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 617 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 618 619 typedef struct 620 { 621 const char *template; 622 uint32_t value; 623 int has_xt; 624 } aarch64_sys_ins_reg; 625 626 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 627 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 628 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 629 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 630 631 /* Shift/extending operator kinds. 632 N.B. order is important; keep aarch64_operand_modifiers synced. */ 633 enum aarch64_modifier_kind 634 { 635 AARCH64_MOD_NONE, 636 AARCH64_MOD_MSL, 637 AARCH64_MOD_ROR, 638 AARCH64_MOD_ASR, 639 AARCH64_MOD_LSR, 640 AARCH64_MOD_LSL, 641 AARCH64_MOD_UXTB, 642 AARCH64_MOD_UXTH, 643 AARCH64_MOD_UXTW, 644 AARCH64_MOD_UXTX, 645 AARCH64_MOD_SXTB, 646 AARCH64_MOD_SXTH, 647 AARCH64_MOD_SXTW, 648 AARCH64_MOD_SXTX, 649 }; 650 651 bfd_boolean 652 aarch64_extend_operator_p (enum aarch64_modifier_kind); 653 654 enum aarch64_modifier_kind 655 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 656 /* Condition. */ 657 658 typedef struct 659 { 660 /* A list of names with the first one as the disassembly preference; 661 terminated by NULL if fewer than 3. */ 662 const char *names[3]; 663 aarch64_insn value; 664 } aarch64_cond; 665 666 extern const aarch64_cond aarch64_conds[16]; 667 668 const aarch64_cond* get_cond_from_value (aarch64_insn value); 669 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 670 671 /* Structure representing an operand. */ 673 674 struct aarch64_opnd_info 675 { 676 enum aarch64_opnd type; 677 aarch64_opnd_qualifier_t qualifier; 678 int idx; 679 680 union 681 { 682 struct 683 { 684 unsigned regno; 685 } reg; 686 struct 687 { 688 unsigned regno : 5; 689 unsigned index : 4; 690 } reglane; 691 /* e.g. LVn. */ 692 struct 693 { 694 unsigned first_regno : 5; 695 unsigned num_regs : 3; 696 /* 1 if it is a list of reg element. */ 697 unsigned has_index : 1; 698 /* Lane index; valid only when has_index is 1. */ 699 unsigned index : 4; 700 } reglist; 701 /* e.g. immediate or pc relative address offset. */ 702 struct 703 { 704 int64_t value; 705 unsigned is_fp : 1; 706 } imm; 707 /* e.g. address in STR (register offset). */ 708 struct 709 { 710 unsigned base_regno; 711 struct 712 { 713 union 714 { 715 int imm; 716 unsigned regno; 717 }; 718 unsigned is_reg; 719 } offset; 720 unsigned pcrel : 1; /* PC-relative. */ 721 unsigned writeback : 1; 722 unsigned preind : 1; /* Pre-indexed. */ 723 unsigned postind : 1; /* Post-indexed. */ 724 } addr; 725 const aarch64_cond *cond; 726 /* The encoding of the system register. */ 727 aarch64_insn sysreg; 728 /* The encoding of the PSTATE field. */ 729 aarch64_insn pstatefield; 730 const aarch64_sys_ins_reg *sysins_op; 731 const struct aarch64_name_value_pair *barrier; 732 const struct aarch64_name_value_pair *prfop; 733 }; 734 735 /* Operand shifter; in use when the operand is a register offset address, 736 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 737 struct 738 { 739 enum aarch64_modifier_kind kind; 740 int amount; 741 unsigned operator_present: 1; /* Only valid during encoding. */ 742 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 743 unsigned amount_present: 1; 744 } shifter; 745 746 unsigned skip:1; /* Operand is not completed if there is a fixup needed 747 to be done on it. In some (but not all) of these 748 cases, we need to tell libopcodes to skip the 749 constraint checking and the encoding for this 750 operand, so that the libopcodes can pick up the 751 right opcode before the operand is fixed-up. This 752 flag should only be used during the 753 assembling/encoding. */ 754 unsigned present:1; /* Whether this operand is present in the assembly 755 line; not used during the disassembly. */ 756 }; 757 758 typedef struct aarch64_opnd_info aarch64_opnd_info; 759 760 /* Structure representing an instruction. 761 762 It is used during both the assembling and disassembling. The assembler 763 fills an aarch64_inst after a successful parsing and then passes it to the 764 encoding routine to do the encoding. During the disassembling, the 765 disassembler calls the decoding routine to decode a binary instruction; on a 766 successful return, such a structure will be filled with information of the 767 instruction; then the disassembler uses the information to print out the 768 instruction. */ 769 770 struct aarch64_inst 771 { 772 /* The value of the binary instruction. */ 773 aarch64_insn value; 774 775 /* Corresponding opcode entry. */ 776 const aarch64_opcode *opcode; 777 778 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 779 const aarch64_cond *cond; 780 781 /* Operands information. */ 782 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 783 }; 784 785 typedef struct aarch64_inst aarch64_inst; 786 787 /* Diagnosis related declaration and interface. */ 789 790 /* Operand error kind enumerators. 791 792 AARCH64_OPDE_RECOVERABLE 793 Less severe error found during the parsing, very possibly because that 794 GAS has picked up a wrong instruction template for the parsing. 795 796 AARCH64_OPDE_SYNTAX_ERROR 797 General syntax error; it can be either a user error, or simply because 798 that GAS is trying a wrong instruction template. 799 800 AARCH64_OPDE_FATAL_SYNTAX_ERROR 801 Definitely a user syntax error. 802 803 AARCH64_OPDE_INVALID_VARIANT 804 No syntax error, but the operands are not a valid combination, e.g. 805 FMOV D0,S0 806 807 AARCH64_OPDE_OUT_OF_RANGE 808 Error about some immediate value out of a valid range. 809 810 AARCH64_OPDE_UNALIGNED 811 Error about some immediate value not properly aligned (i.e. not being a 812 multiple times of a certain value). 813 814 AARCH64_OPDE_REG_LIST 815 Error about the register list operand having unexpected number of 816 registers. 817 818 AARCH64_OPDE_OTHER_ERROR 819 Error of the highest severity and used for any severe issue that does not 820 fall into any of the above categories. 821 822 The enumerators are only interesting to GAS. They are declared here (in 823 libopcodes) because that some errors are detected (and then notified to GAS) 824 by libopcodes (rather than by GAS solely). 825 826 The first three errors are only deteced by GAS while the 827 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 828 only libopcodes has the information about the valid variants of each 829 instruction. 830 831 The enumerators have an increasing severity. This is helpful when there are 832 multiple instruction templates available for a given mnemonic name (e.g. 833 FMOV); this mechanism will help choose the most suitable template from which 834 the generated diagnostics can most closely describe the issues, if any. */ 835 836 enum aarch64_operand_error_kind 837 { 838 AARCH64_OPDE_NIL, 839 AARCH64_OPDE_RECOVERABLE, 840 AARCH64_OPDE_SYNTAX_ERROR, 841 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 842 AARCH64_OPDE_INVALID_VARIANT, 843 AARCH64_OPDE_OUT_OF_RANGE, 844 AARCH64_OPDE_UNALIGNED, 845 AARCH64_OPDE_REG_LIST, 846 AARCH64_OPDE_OTHER_ERROR 847 }; 848 849 /* N.B. GAS assumes that this structure work well with shallow copy. */ 850 struct aarch64_operand_error 851 { 852 enum aarch64_operand_error_kind kind; 853 int index; 854 const char *error; 855 int data[3]; /* Some data for extra information. */ 856 }; 857 858 typedef struct aarch64_operand_error aarch64_operand_error; 859 860 /* Encoding entrypoint. */ 861 862 extern int 863 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 864 aarch64_insn *, aarch64_opnd_qualifier_t *, 865 aarch64_operand_error *); 866 867 extern const aarch64_opcode * 868 aarch64_replace_opcode (struct aarch64_inst *, 869 const aarch64_opcode *); 870 871 /* Given the opcode enumerator OP, return the pointer to the corresponding 872 opcode entry. */ 873 874 extern const aarch64_opcode * 875 aarch64_get_opcode (enum aarch64_op); 876 877 /* Generate the string representation of an operand. */ 878 extern void 879 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 880 const aarch64_opnd_info *, int, int *, bfd_vma *); 881 882 /* Miscellaneous interface. */ 883 884 extern int 885 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 886 887 extern aarch64_opnd_qualifier_t 888 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 889 const aarch64_opnd_qualifier_t, int); 890 891 extern int 892 aarch64_num_of_operands (const aarch64_opcode *); 893 894 extern int 895 aarch64_stack_pointer_p (const aarch64_opnd_info *); 896 897 extern 898 int aarch64_zero_register_p (const aarch64_opnd_info *); 899 900 /* Given an operand qualifier, return the expected data element size 901 of a qualified operand. */ 902 extern unsigned char 903 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 904 905 extern enum aarch64_operand_class 906 aarch64_get_operand_class (enum aarch64_opnd); 907 908 extern const char * 909 aarch64_get_operand_name (enum aarch64_opnd); 910 911 extern const char * 912 aarch64_get_operand_desc (enum aarch64_opnd); 913 914 #ifdef DEBUG_AARCH64 915 extern int debug_dump; 916 917 extern void 918 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 919 920 #define DEBUG_TRACE(M, ...) \ 921 { \ 922 if (debug_dump) \ 923 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 924 } 925 926 #define DEBUG_TRACE_IF(C, M, ...) \ 927 { \ 928 if (debug_dump && (C)) \ 929 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 930 } 931 #else /* !DEBUG_AARCH64 */ 932 #define DEBUG_TRACE(M, ...) ; 933 #define DEBUG_TRACE_IF(C, M, ...) ; 934 #endif /* DEBUG_AARCH64 */ 935 936 #endif /* OPCODE_AARCH64_H */ 937
Indexes created Sat Mar 28 00:23:22 UTC 2026