aarch64.h revision 1.1.1.2
1 /* AArch64 assembler/disassembler support. 2 3 Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 /* The offset for pc-relative addressing is currently defined to be 0. */ 31 #define AARCH64_PCREL_OFFSET 0 32 33 typedef uint32_t aarch64_insn; 34 35 /* The following bitmasks control CPU features. */ 36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 40 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 41 42 /* Architectures are the sum of the base and extensions. */ 43 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 44 AARCH64_FEATURE_FP \ 45 | AARCH64_FEATURE_SIMD) 46 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 47 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 48 49 /* CPU-specific features. */ 50 typedef unsigned long aarch64_feature_set; 51 52 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 53 (((CPU) & (FEAT)) != 0) 54 55 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 56 do \ 57 { \ 58 (TARG) = (F1) | (F2); \ 59 } \ 60 while (0) 61 62 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 63 do \ 64 { \ 65 (TARG) = (F1) &~ (F2); \ 66 } \ 67 while (0) 68 69 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 70 71 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ 72 (((OPC) & (FEAT)) != 0) 73 74 enum aarch64_operand_class 75 { 76 AARCH64_OPND_CLASS_NIL, 77 AARCH64_OPND_CLASS_INT_REG, 78 AARCH64_OPND_CLASS_MODIFIED_REG, 79 AARCH64_OPND_CLASS_FP_REG, 80 AARCH64_OPND_CLASS_SIMD_REG, 81 AARCH64_OPND_CLASS_SIMD_ELEMENT, 82 AARCH64_OPND_CLASS_SISD_REG, 83 AARCH64_OPND_CLASS_SIMD_REGLIST, 84 AARCH64_OPND_CLASS_CP_REG, 85 AARCH64_OPND_CLASS_ADDRESS, 86 AARCH64_OPND_CLASS_IMMEDIATE, 87 AARCH64_OPND_CLASS_SYSTEM, 88 AARCH64_OPND_CLASS_COND, 89 }; 90 91 /* Operand code that helps both parsing and coding. 92 Keep AARCH64_OPERANDS synced. */ 93 94 enum aarch64_opnd 95 { 96 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 97 98 AARCH64_OPND_Rd, /* Integer register as destination. */ 99 AARCH64_OPND_Rn, /* Integer register as source. */ 100 AARCH64_OPND_Rm, /* Integer register as source. */ 101 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 102 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 103 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 104 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 105 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 106 107 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 108 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 109 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 110 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 111 112 AARCH64_OPND_Fd, /* Floating-point Fd. */ 113 AARCH64_OPND_Fn, /* Floating-point Fn. */ 114 AARCH64_OPND_Fm, /* Floating-point Fm. */ 115 AARCH64_OPND_Fa, /* Floating-point Fa. */ 116 AARCH64_OPND_Ft, /* Floating-point Ft. */ 117 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 118 119 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 120 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 121 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 122 123 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 124 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 125 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 126 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 127 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 128 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 129 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 130 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 131 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 132 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 133 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 134 structure to all lanes. */ 135 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 136 137 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 138 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 139 140 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 141 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 142 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 143 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 144 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 145 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 146 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 147 (no encoding). */ 148 AARCH64_OPND_IMM0, /* Immediate for #0. */ 149 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 150 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 151 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 152 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 153 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 154 AARCH64_OPND_IMM, /* Immediate. */ 155 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 156 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 157 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 158 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 159 AARCH64_OPND_BIT_NUM, /* Immediate. */ 160 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 161 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 162 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 163 each condition flag. */ 164 165 AARCH64_OPND_LIMM, /* Logical Immediate. */ 166 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 167 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 168 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 169 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 170 171 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 172 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 173 174 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 175 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 176 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 177 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 178 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 179 180 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 181 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 182 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 183 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 184 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 185 negative or unaligned and there is 186 no writeback allowed. This operand code 187 is only used to support the programmer- 188 friendly feature of using LDR/STR as the 189 the mnemonic name for LDUR/STUR instructions 190 wherever there is no ambiguity. */ 191 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 192 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 193 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 194 195 AARCH64_OPND_SYSREG, /* System register operand. */ 196 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 197 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 198 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 199 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 200 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 201 AARCH64_OPND_BARRIER, /* Barrier operand. */ 202 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 203 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 204 }; 205 206 /* Qualifier constrains an operand. It either specifies a variant of an 207 operand type or limits values available to an operand type. 208 209 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 210 211 enum aarch64_opnd_qualifier 212 { 213 /* Indicating no further qualification on an operand. */ 214 AARCH64_OPND_QLF_NIL, 215 216 /* Qualifying an operand which is a general purpose (integer) register; 217 indicating the operand data size or a specific register. */ 218 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 219 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 220 AARCH64_OPND_QLF_WSP, /* WSP. */ 221 AARCH64_OPND_QLF_SP, /* SP. */ 222 223 /* Qualifying an operand which is a floating-point register, a SIMD 224 vector element or a SIMD vector element list; indicating operand data 225 size or the size of each SIMD vector element in the case of a SIMD 226 vector element list. 227 These qualifiers are also used to qualify an address operand to 228 indicate the size of data element a load/store instruction is 229 accessing. 230 They are also used for the immediate shift operand in e.g. SSHR. Such 231 a use is only for the ease of operand encoding/decoding and qualifier 232 sequence matching; such a use should not be applied widely; use the value 233 constraint qualifiers for immediate operands wherever possible. */ 234 AARCH64_OPND_QLF_S_B, 235 AARCH64_OPND_QLF_S_H, 236 AARCH64_OPND_QLF_S_S, 237 AARCH64_OPND_QLF_S_D, 238 AARCH64_OPND_QLF_S_Q, 239 240 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 241 register list; indicating register shape. 242 They are also used for the immediate shift operand in e.g. SSHR. Such 243 a use is only for the ease of operand encoding/decoding and qualifier 244 sequence matching; such a use should not be applied widely; use the value 245 constraint qualifiers for immediate operands wherever possible. */ 246 AARCH64_OPND_QLF_V_8B, 247 AARCH64_OPND_QLF_V_16B, 248 AARCH64_OPND_QLF_V_4H, 249 AARCH64_OPND_QLF_V_8H, 250 AARCH64_OPND_QLF_V_2S, 251 AARCH64_OPND_QLF_V_4S, 252 AARCH64_OPND_QLF_V_1D, 253 AARCH64_OPND_QLF_V_2D, 254 AARCH64_OPND_QLF_V_1Q, 255 256 /* Constraint on value. */ 257 AARCH64_OPND_QLF_imm_0_7, 258 AARCH64_OPND_QLF_imm_0_15, 259 AARCH64_OPND_QLF_imm_0_31, 260 AARCH64_OPND_QLF_imm_0_63, 261 AARCH64_OPND_QLF_imm_1_32, 262 AARCH64_OPND_QLF_imm_1_64, 263 264 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 265 or shift-ones. */ 266 AARCH64_OPND_QLF_LSL, 267 AARCH64_OPND_QLF_MSL, 268 269 /* Special qualifier helping retrieve qualifier information during the 270 decoding time (currently not in use). */ 271 AARCH64_OPND_QLF_RETRIEVE, 272 }; 273 274 /* Instruction class. */ 276 277 enum aarch64_insn_class 278 { 279 addsub_carry, 280 addsub_ext, 281 addsub_imm, 282 addsub_shift, 283 asimdall, 284 asimddiff, 285 asimdelem, 286 asimdext, 287 asimdimm, 288 asimdins, 289 asimdmisc, 290 asimdperm, 291 asimdsame, 292 asimdshf, 293 asimdtbl, 294 asisddiff, 295 asisdelem, 296 asisdlse, 297 asisdlsep, 298 asisdlso, 299 asisdlsop, 300 asisdmisc, 301 asisdone, 302 asisdpair, 303 asisdsame, 304 asisdshf, 305 bitfield, 306 branch_imm, 307 branch_reg, 308 compbranch, 309 condbranch, 310 condcmp_imm, 311 condcmp_reg, 312 condsel, 313 cryptoaes, 314 cryptosha2, 315 cryptosha3, 316 dp_1src, 317 dp_2src, 318 dp_3src, 319 exception, 320 extract, 321 float2fix, 322 float2int, 323 floatccmp, 324 floatcmp, 325 floatdp1, 326 floatdp2, 327 floatdp3, 328 floatimm, 329 floatsel, 330 ldst_immpost, 331 ldst_immpre, 332 ldst_imm9, /* immpost or immpre */ 333 ldst_pos, 334 ldst_regoff, 335 ldst_unpriv, 336 ldst_unscaled, 337 ldstexcl, 338 ldstnapair_offs, 339 ldstpair_off, 340 ldstpair_indexed, 341 loadlit, 342 log_imm, 343 log_shift, 344 movewide, 345 pcreladdr, 346 ic_system, 347 testbranch, 348 }; 349 350 /* Opcode enumerators. */ 351 352 enum aarch64_op 353 { 354 OP_NIL, 355 OP_STRB_POS, 356 OP_LDRB_POS, 357 OP_LDRSB_POS, 358 OP_STRH_POS, 359 OP_LDRH_POS, 360 OP_LDRSH_POS, 361 OP_STR_POS, 362 OP_LDR_POS, 363 OP_STRF_POS, 364 OP_LDRF_POS, 365 OP_LDRSW_POS, 366 OP_PRFM_POS, 367 368 OP_STURB, 369 OP_LDURB, 370 OP_LDURSB, 371 OP_STURH, 372 OP_LDURH, 373 OP_LDURSH, 374 OP_STUR, 375 OP_LDUR, 376 OP_STURV, 377 OP_LDURV, 378 OP_LDURSW, 379 OP_PRFUM, 380 381 OP_LDR_LIT, 382 OP_LDRV_LIT, 383 OP_LDRSW_LIT, 384 OP_PRFM_LIT, 385 386 OP_ADD, 387 OP_B, 388 OP_BL, 389 390 OP_MOVN, 391 OP_MOVZ, 392 OP_MOVK, 393 394 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 395 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 396 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 397 398 OP_MOV_V, /* MOV alias for moving vector register. */ 399 400 OP_ASR_IMM, 401 OP_LSR_IMM, 402 OP_LSL_IMM, 403 404 OP_BIC, 405 406 OP_UBFX, 407 OP_BFXIL, 408 OP_SBFX, 409 OP_SBFIZ, 410 OP_BFI, 411 OP_UBFIZ, 412 OP_UXTB, 413 OP_UXTH, 414 OP_UXTW, 415 416 OP_CINC, 417 OP_CINV, 418 OP_CNEG, 419 OP_CSET, 420 OP_CSETM, 421 422 OP_FCVT, 423 OP_FCVTN, 424 OP_FCVTN2, 425 OP_FCVTL, 426 OP_FCVTL2, 427 OP_FCVTXN_S, /* Scalar version. */ 428 429 OP_ROR_IMM, 430 431 OP_SXTL, 432 OP_SXTL2, 433 OP_UXTL, 434 OP_UXTL2, 435 436 OP_TOTAL_NUM, /* Pseudo. */ 437 }; 438 439 /* Maximum number of operands an instruction can have. */ 440 #define AARCH64_MAX_OPND_NUM 6 441 /* Maximum number of qualifier sequences an instruction can have. */ 442 #define AARCH64_MAX_QLF_SEQ_NUM 10 443 /* Operand qualifier typedef; optimized for the size. */ 444 typedef unsigned char aarch64_opnd_qualifier_t; 445 /* Operand qualifier sequence typedef. */ 446 typedef aarch64_opnd_qualifier_t \ 447 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 448 449 /* FIXME: improve the efficiency. */ 450 static inline bfd_boolean 451 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 452 { 453 int i; 454 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 455 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 456 return FALSE; 457 return TRUE; 458 } 459 460 /* This structure holds information for a particular opcode. */ 461 462 struct aarch64_opcode 463 { 464 /* The name of the mnemonic. */ 465 const char *name; 466 467 /* The opcode itself. Those bits which will be filled in with 468 operands are zeroes. */ 469 aarch64_insn opcode; 470 471 /* The opcode mask. This is used by the disassembler. This is a 472 mask containing ones indicating those bits which must match the 473 opcode field, and zeroes indicating those bits which need not 474 match (and are presumably filled in by operands). */ 475 aarch64_insn mask; 476 477 /* Instruction class. */ 478 enum aarch64_insn_class iclass; 479 480 /* Enumerator identifier. */ 481 enum aarch64_op op; 482 483 /* Which architecture variant provides this instruction. */ 484 const aarch64_feature_set *avariant; 485 486 /* An array of operand codes. Each code is an index into the 487 operand table. They appear in the order which the operands must 488 appear in assembly code, and are terminated by a zero. */ 489 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 490 491 /* A list of operand qualifier code sequence. Each operand qualifier 492 code qualifies the corresponding operand code. Each operand 493 qualifier sequence specifies a valid opcode variant and related 494 constraint on operands. */ 495 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 496 497 /* Flags providing information about this instruction */ 498 uint32_t flags; 499 }; 500 501 typedef struct aarch64_opcode aarch64_opcode; 502 503 /* Table describing all the AArch64 opcodes. */ 504 extern aarch64_opcode aarch64_opcode_table[]; 505 506 /* Opcode flags. */ 507 #define F_ALIAS (1 << 0) 508 #define F_HAS_ALIAS (1 << 1) 509 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 510 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 511 #define F_P1 (1 << 2) 512 #define F_P2 (2 << 2) 513 #define F_P3 (3 << 2) 514 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 515 #define F_COND (1 << 4) 516 /* Instruction has the field of 'sf'. */ 517 #define F_SF (1 << 5) 518 /* Instruction has the field of 'size:Q'. */ 519 #define F_SIZEQ (1 << 6) 520 /* Floating-point instruction has the field of 'type'. */ 521 #define F_FPTYPE (1 << 7) 522 /* AdvSIMD scalar instruction has the field of 'size'. */ 523 #define F_SSIZE (1 << 8) 524 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 525 #define F_T (1 << 9) 526 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 527 #define F_GPRSIZE_IN_Q (1 << 10) 528 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 529 #define F_LDS_SIZE (1 << 11) 530 /* Optional operand; assume maximum of 1 operand can be optional. */ 531 #define F_OPD0_OPT (1 << 12) 532 #define F_OPD1_OPT (2 << 12) 533 #define F_OPD2_OPT (3 << 12) 534 #define F_OPD3_OPT (4 << 12) 535 #define F_OPD4_OPT (5 << 12) 536 /* Default value for the optional operand when omitted from the assembly. */ 537 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 538 /* Instruction that is an alias of another instruction needs to be 539 encoded/decoded by converting it to/from the real form, followed by 540 the encoding/decoding according to the rules of the real opcode. 541 This compares to the direct coding using the alias's information. 542 N.B. this flag requires F_ALIAS to be used together. */ 543 #define F_CONV (1 << 20) 544 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 545 friendly pseudo instruction available only in the assembly code (thus will 546 not show up in the disassembly). */ 547 #define F_PSEUDO (1 << 21) 548 /* Instruction has miscellaneous encoding/decoding rules. */ 549 #define F_MISC (1 << 22) 550 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 551 #define F_N (1 << 23) 552 /* Opcode dependent field. */ 553 #define F_OD(X) (((X) & 0x7) << 24) 554 /* Next bit is 27. */ 555 556 static inline bfd_boolean 557 alias_opcode_p (const aarch64_opcode *opcode) 558 { 559 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 560 } 561 562 static inline bfd_boolean 563 opcode_has_alias (const aarch64_opcode *opcode) 564 { 565 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 566 } 567 568 /* Priority for disassembling preference. */ 569 static inline int 570 opcode_priority (const aarch64_opcode *opcode) 571 { 572 return (opcode->flags >> 2) & 0x3; 573 } 574 575 static inline bfd_boolean 576 pseudo_opcode_p (const aarch64_opcode *opcode) 577 { 578 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 579 } 580 581 static inline bfd_boolean 582 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 583 { 584 return (((opcode->flags >> 12) & 0x7) == idx + 1) 585 ? TRUE : FALSE; 586 } 587 588 static inline aarch64_insn 589 get_optional_operand_default_value (const aarch64_opcode *opcode) 590 { 591 return (opcode->flags >> 15) & 0x1f; 592 } 593 594 static inline unsigned int 595 get_opcode_dependent_value (const aarch64_opcode *opcode) 596 { 597 return (opcode->flags >> 24) & 0x7; 598 } 599 600 static inline bfd_boolean 601 opcode_has_special_coder (const aarch64_opcode *opcode) 602 { 603 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 604 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 605 : FALSE; 606 } 607 608 struct aarch64_name_value_pair 610 { 611 const char * name; 612 aarch64_insn value; 613 }; 614 615 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 616 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 617 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 618 619 typedef struct 620 { 621 const char * name; 622 aarch64_insn value; 623 uint32_t flags; 624 } aarch64_sys_reg; 625 626 extern const aarch64_sys_reg aarch64_sys_regs []; 627 extern const aarch64_sys_reg aarch64_pstatefields []; 628 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 629 630 typedef struct 631 { 632 const char *template; 633 uint32_t value; 634 int has_xt; 635 } aarch64_sys_ins_reg; 636 637 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 638 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 639 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 640 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 641 642 /* Shift/extending operator kinds. 643 N.B. order is important; keep aarch64_operand_modifiers synced. */ 644 enum aarch64_modifier_kind 645 { 646 AARCH64_MOD_NONE, 647 AARCH64_MOD_MSL, 648 AARCH64_MOD_ROR, 649 AARCH64_MOD_ASR, 650 AARCH64_MOD_LSR, 651 AARCH64_MOD_LSL, 652 AARCH64_MOD_UXTB, 653 AARCH64_MOD_UXTH, 654 AARCH64_MOD_UXTW, 655 AARCH64_MOD_UXTX, 656 AARCH64_MOD_SXTB, 657 AARCH64_MOD_SXTH, 658 AARCH64_MOD_SXTW, 659 AARCH64_MOD_SXTX, 660 }; 661 662 bfd_boolean 663 aarch64_extend_operator_p (enum aarch64_modifier_kind); 664 665 enum aarch64_modifier_kind 666 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 667 /* Condition. */ 668 669 typedef struct 670 { 671 /* A list of names with the first one as the disassembly preference; 672 terminated by NULL if fewer than 3. */ 673 const char *names[3]; 674 aarch64_insn value; 675 } aarch64_cond; 676 677 extern const aarch64_cond aarch64_conds[16]; 678 679 const aarch64_cond* get_cond_from_value (aarch64_insn value); 680 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 681 682 /* Structure representing an operand. */ 684 685 struct aarch64_opnd_info 686 { 687 enum aarch64_opnd type; 688 aarch64_opnd_qualifier_t qualifier; 689 int idx; 690 691 union 692 { 693 struct 694 { 695 unsigned regno; 696 } reg; 697 struct 698 { 699 unsigned regno : 5; 700 unsigned index : 4; 701 } reglane; 702 /* e.g. LVn. */ 703 struct 704 { 705 unsigned first_regno : 5; 706 unsigned num_regs : 3; 707 /* 1 if it is a list of reg element. */ 708 unsigned has_index : 1; 709 /* Lane index; valid only when has_index is 1. */ 710 unsigned index : 4; 711 } reglist; 712 /* e.g. immediate or pc relative address offset. */ 713 struct 714 { 715 int64_t value; 716 unsigned is_fp : 1; 717 } imm; 718 /* e.g. address in STR (register offset). */ 719 struct 720 { 721 unsigned base_regno; 722 struct 723 { 724 union 725 { 726 int imm; 727 unsigned regno; 728 }; 729 unsigned is_reg; 730 } offset; 731 unsigned pcrel : 1; /* PC-relative. */ 732 unsigned writeback : 1; 733 unsigned preind : 1; /* Pre-indexed. */ 734 unsigned postind : 1; /* Post-indexed. */ 735 } addr; 736 const aarch64_cond *cond; 737 /* The encoding of the system register. */ 738 aarch64_insn sysreg; 739 /* The encoding of the PSTATE field. */ 740 aarch64_insn pstatefield; 741 const aarch64_sys_ins_reg *sysins_op; 742 const struct aarch64_name_value_pair *barrier; 743 const struct aarch64_name_value_pair *prfop; 744 }; 745 746 /* Operand shifter; in use when the operand is a register offset address, 747 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 748 struct 749 { 750 enum aarch64_modifier_kind kind; 751 int amount; 752 unsigned operator_present: 1; /* Only valid during encoding. */ 753 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 754 unsigned amount_present: 1; 755 } shifter; 756 757 unsigned skip:1; /* Operand is not completed if there is a fixup needed 758 to be done on it. In some (but not all) of these 759 cases, we need to tell libopcodes to skip the 760 constraint checking and the encoding for this 761 operand, so that the libopcodes can pick up the 762 right opcode before the operand is fixed-up. This 763 flag should only be used during the 764 assembling/encoding. */ 765 unsigned present:1; /* Whether this operand is present in the assembly 766 line; not used during the disassembly. */ 767 }; 768 769 typedef struct aarch64_opnd_info aarch64_opnd_info; 770 771 /* Structure representing an instruction. 772 773 It is used during both the assembling and disassembling. The assembler 774 fills an aarch64_inst after a successful parsing and then passes it to the 775 encoding routine to do the encoding. During the disassembling, the 776 disassembler calls the decoding routine to decode a binary instruction; on a 777 successful return, such a structure will be filled with information of the 778 instruction; then the disassembler uses the information to print out the 779 instruction. */ 780 781 struct aarch64_inst 782 { 783 /* The value of the binary instruction. */ 784 aarch64_insn value; 785 786 /* Corresponding opcode entry. */ 787 const aarch64_opcode *opcode; 788 789 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 790 const aarch64_cond *cond; 791 792 /* Operands information. */ 793 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 794 }; 795 796 typedef struct aarch64_inst aarch64_inst; 797 798 /* Diagnosis related declaration and interface. */ 800 801 /* Operand error kind enumerators. 802 803 AARCH64_OPDE_RECOVERABLE 804 Less severe error found during the parsing, very possibly because that 805 GAS has picked up a wrong instruction template for the parsing. 806 807 AARCH64_OPDE_SYNTAX_ERROR 808 General syntax error; it can be either a user error, or simply because 809 that GAS is trying a wrong instruction template. 810 811 AARCH64_OPDE_FATAL_SYNTAX_ERROR 812 Definitely a user syntax error. 813 814 AARCH64_OPDE_INVALID_VARIANT 815 No syntax error, but the operands are not a valid combination, e.g. 816 FMOV D0,S0 817 818 AARCH64_OPDE_OUT_OF_RANGE 819 Error about some immediate value out of a valid range. 820 821 AARCH64_OPDE_UNALIGNED 822 Error about some immediate value not properly aligned (i.e. not being a 823 multiple times of a certain value). 824 825 AARCH64_OPDE_REG_LIST 826 Error about the register list operand having unexpected number of 827 registers. 828 829 AARCH64_OPDE_OTHER_ERROR 830 Error of the highest severity and used for any severe issue that does not 831 fall into any of the above categories. 832 833 The enumerators are only interesting to GAS. They are declared here (in 834 libopcodes) because that some errors are detected (and then notified to GAS) 835 by libopcodes (rather than by GAS solely). 836 837 The first three errors are only deteced by GAS while the 838 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 839 only libopcodes has the information about the valid variants of each 840 instruction. 841 842 The enumerators have an increasing severity. This is helpful when there are 843 multiple instruction templates available for a given mnemonic name (e.g. 844 FMOV); this mechanism will help choose the most suitable template from which 845 the generated diagnostics can most closely describe the issues, if any. */ 846 847 enum aarch64_operand_error_kind 848 { 849 AARCH64_OPDE_NIL, 850 AARCH64_OPDE_RECOVERABLE, 851 AARCH64_OPDE_SYNTAX_ERROR, 852 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 853 AARCH64_OPDE_INVALID_VARIANT, 854 AARCH64_OPDE_OUT_OF_RANGE, 855 AARCH64_OPDE_UNALIGNED, 856 AARCH64_OPDE_REG_LIST, 857 AARCH64_OPDE_OTHER_ERROR 858 }; 859 860 /* N.B. GAS assumes that this structure work well with shallow copy. */ 861 struct aarch64_operand_error 862 { 863 enum aarch64_operand_error_kind kind; 864 int index; 865 const char *error; 866 int data[3]; /* Some data for extra information. */ 867 }; 868 869 typedef struct aarch64_operand_error aarch64_operand_error; 870 871 /* Encoding entrypoint. */ 872 873 extern int 874 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 875 aarch64_insn *, aarch64_opnd_qualifier_t *, 876 aarch64_operand_error *); 877 878 extern const aarch64_opcode * 879 aarch64_replace_opcode (struct aarch64_inst *, 880 const aarch64_opcode *); 881 882 /* Given the opcode enumerator OP, return the pointer to the corresponding 883 opcode entry. */ 884 885 extern const aarch64_opcode * 886 aarch64_get_opcode (enum aarch64_op); 887 888 /* Generate the string representation of an operand. */ 889 extern void 890 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 891 const aarch64_opnd_info *, int, int *, bfd_vma *); 892 893 /* Miscellaneous interface. */ 894 895 extern int 896 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 897 898 extern aarch64_opnd_qualifier_t 899 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 900 const aarch64_opnd_qualifier_t, int); 901 902 extern int 903 aarch64_num_of_operands (const aarch64_opcode *); 904 905 extern int 906 aarch64_stack_pointer_p (const aarch64_opnd_info *); 907 908 extern 909 int aarch64_zero_register_p (const aarch64_opnd_info *); 910 911 /* Given an operand qualifier, return the expected data element size 912 of a qualified operand. */ 913 extern unsigned char 914 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 915 916 extern enum aarch64_operand_class 917 aarch64_get_operand_class (enum aarch64_opnd); 918 919 extern const char * 920 aarch64_get_operand_name (enum aarch64_opnd); 921 922 extern const char * 923 aarch64_get_operand_desc (enum aarch64_opnd); 924 925 #ifdef DEBUG_AARCH64 926 extern int debug_dump; 927 928 extern void 929 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 930 931 #define DEBUG_TRACE(M, ...) \ 932 { \ 933 if (debug_dump) \ 934 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 935 } 936 937 #define DEBUG_TRACE_IF(C, M, ...) \ 938 { \ 939 if (debug_dump && (C)) \ 940 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 941 } 942 #else /* !DEBUG_AARCH64 */ 943 #define DEBUG_TRACE(M, ...) ; 944 #define DEBUG_TRACE_IF(C, M, ...) ; 945 #endif /* DEBUG_AARCH64 */ 946 947 #endif /* OPCODE_AARCH64_H */ 948
Indexes created Sat Mar 28 00:23:22 UTC 2026