aarch64.h revision 1.1.1.3
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2015 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 /* The offset for pc-relative addressing is currently defined to be 0. */ 31 #define AARCH64_PCREL_OFFSET 0 32 33 typedef uint32_t aarch64_insn; 34 35 /* The following bitmasks control CPU features. */ 36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 40 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 41 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ 42 43 /* Architectures are the sum of the base and extensions. */ 44 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 45 AARCH64_FEATURE_FP \ 46 | AARCH64_FEATURE_SIMD) 47 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 48 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 49 50 /* CPU-specific features. */ 51 typedef unsigned long aarch64_feature_set; 52 53 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 54 (((CPU) & (FEAT)) != 0) 55 56 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 57 do \ 58 { \ 59 (TARG) = (F1) | (F2); \ 60 } \ 61 while (0) 62 63 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 64 do \ 65 { \ 66 (TARG) = (F1) &~ (F2); \ 67 } \ 68 while (0) 69 70 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 71 72 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ 73 (((OPC) & (FEAT)) != 0) 74 75 enum aarch64_operand_class 76 { 77 AARCH64_OPND_CLASS_NIL, 78 AARCH64_OPND_CLASS_INT_REG, 79 AARCH64_OPND_CLASS_MODIFIED_REG, 80 AARCH64_OPND_CLASS_FP_REG, 81 AARCH64_OPND_CLASS_SIMD_REG, 82 AARCH64_OPND_CLASS_SIMD_ELEMENT, 83 AARCH64_OPND_CLASS_SISD_REG, 84 AARCH64_OPND_CLASS_SIMD_REGLIST, 85 AARCH64_OPND_CLASS_CP_REG, 86 AARCH64_OPND_CLASS_ADDRESS, 87 AARCH64_OPND_CLASS_IMMEDIATE, 88 AARCH64_OPND_CLASS_SYSTEM, 89 AARCH64_OPND_CLASS_COND, 90 }; 91 92 /* Operand code that helps both parsing and coding. 93 Keep AARCH64_OPERANDS synced. */ 94 95 enum aarch64_opnd 96 { 97 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 98 99 AARCH64_OPND_Rd, /* Integer register as destination. */ 100 AARCH64_OPND_Rn, /* Integer register as source. */ 101 AARCH64_OPND_Rm, /* Integer register as source. */ 102 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 103 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 104 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 105 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 106 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 107 108 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 109 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 110 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 111 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 112 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 113 114 AARCH64_OPND_Fd, /* Floating-point Fd. */ 115 AARCH64_OPND_Fn, /* Floating-point Fn. */ 116 AARCH64_OPND_Fm, /* Floating-point Fm. */ 117 AARCH64_OPND_Fa, /* Floating-point Fa. */ 118 AARCH64_OPND_Ft, /* Floating-point Ft. */ 119 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 120 121 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 122 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 123 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 124 125 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 126 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 127 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 128 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 129 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 130 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 131 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 132 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 133 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 134 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 135 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 136 structure to all lanes. */ 137 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 138 139 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 140 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 141 142 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 143 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 144 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 145 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 146 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 147 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 148 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 149 (no encoding). */ 150 AARCH64_OPND_IMM0, /* Immediate for #0. */ 151 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 152 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 153 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 154 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 155 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 156 AARCH64_OPND_IMM, /* Immediate. */ 157 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 158 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 159 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 160 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 161 AARCH64_OPND_BIT_NUM, /* Immediate. */ 162 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 163 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 164 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 165 each condition flag. */ 166 167 AARCH64_OPND_LIMM, /* Logical Immediate. */ 168 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 169 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 170 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 171 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 172 173 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 174 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 175 176 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 177 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 178 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 179 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 180 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 181 182 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 183 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 184 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 185 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 186 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 187 negative or unaligned and there is 188 no writeback allowed. This operand code 189 is only used to support the programmer- 190 friendly feature of using LDR/STR as the 191 the mnemonic name for LDUR/STUR instructions 192 wherever there is no ambiguity. */ 193 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 194 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 195 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 196 197 AARCH64_OPND_SYSREG, /* System register operand. */ 198 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 199 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 200 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 201 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 202 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 203 AARCH64_OPND_BARRIER, /* Barrier operand. */ 204 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 205 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 206 }; 207 208 /* Qualifier constrains an operand. It either specifies a variant of an 209 operand type or limits values available to an operand type. 210 211 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 212 213 enum aarch64_opnd_qualifier 214 { 215 /* Indicating no further qualification on an operand. */ 216 AARCH64_OPND_QLF_NIL, 217 218 /* Qualifying an operand which is a general purpose (integer) register; 219 indicating the operand data size or a specific register. */ 220 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 221 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 222 AARCH64_OPND_QLF_WSP, /* WSP. */ 223 AARCH64_OPND_QLF_SP, /* SP. */ 224 225 /* Qualifying an operand which is a floating-point register, a SIMD 226 vector element or a SIMD vector element list; indicating operand data 227 size or the size of each SIMD vector element in the case of a SIMD 228 vector element list. 229 These qualifiers are also used to qualify an address operand to 230 indicate the size of data element a load/store instruction is 231 accessing. 232 They are also used for the immediate shift operand in e.g. SSHR. Such 233 a use is only for the ease of operand encoding/decoding and qualifier 234 sequence matching; such a use should not be applied widely; use the value 235 constraint qualifiers for immediate operands wherever possible. */ 236 AARCH64_OPND_QLF_S_B, 237 AARCH64_OPND_QLF_S_H, 238 AARCH64_OPND_QLF_S_S, 239 AARCH64_OPND_QLF_S_D, 240 AARCH64_OPND_QLF_S_Q, 241 242 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 243 register list; indicating register shape. 244 They are also used for the immediate shift operand in e.g. SSHR. Such 245 a use is only for the ease of operand encoding/decoding and qualifier 246 sequence matching; such a use should not be applied widely; use the value 247 constraint qualifiers for immediate operands wherever possible. */ 248 AARCH64_OPND_QLF_V_8B, 249 AARCH64_OPND_QLF_V_16B, 250 AARCH64_OPND_QLF_V_4H, 251 AARCH64_OPND_QLF_V_8H, 252 AARCH64_OPND_QLF_V_2S, 253 AARCH64_OPND_QLF_V_4S, 254 AARCH64_OPND_QLF_V_1D, 255 AARCH64_OPND_QLF_V_2D, 256 AARCH64_OPND_QLF_V_1Q, 257 258 /* Constraint on value. */ 259 AARCH64_OPND_QLF_imm_0_7, 260 AARCH64_OPND_QLF_imm_0_15, 261 AARCH64_OPND_QLF_imm_0_31, 262 AARCH64_OPND_QLF_imm_0_63, 263 AARCH64_OPND_QLF_imm_1_32, 264 AARCH64_OPND_QLF_imm_1_64, 265 266 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 267 or shift-ones. */ 268 AARCH64_OPND_QLF_LSL, 269 AARCH64_OPND_QLF_MSL, 270 271 /* Special qualifier helping retrieve qualifier information during the 272 decoding time (currently not in use). */ 273 AARCH64_OPND_QLF_RETRIEVE, 274 }; 275 276 /* Instruction class. */ 278 279 enum aarch64_insn_class 280 { 281 addsub_carry, 282 addsub_ext, 283 addsub_imm, 284 addsub_shift, 285 asimdall, 286 asimddiff, 287 asimdelem, 288 asimdext, 289 asimdimm, 290 asimdins, 291 asimdmisc, 292 asimdperm, 293 asimdsame, 294 asimdshf, 295 asimdtbl, 296 asisddiff, 297 asisdelem, 298 asisdlse, 299 asisdlsep, 300 asisdlso, 301 asisdlsop, 302 asisdmisc, 303 asisdone, 304 asisdpair, 305 asisdsame, 306 asisdshf, 307 bitfield, 308 branch_imm, 309 branch_reg, 310 compbranch, 311 condbranch, 312 condcmp_imm, 313 condcmp_reg, 314 condsel, 315 cryptoaes, 316 cryptosha2, 317 cryptosha3, 318 dp_1src, 319 dp_2src, 320 dp_3src, 321 exception, 322 extract, 323 float2fix, 324 float2int, 325 floatccmp, 326 floatcmp, 327 floatdp1, 328 floatdp2, 329 floatdp3, 330 floatimm, 331 floatsel, 332 ldst_immpost, 333 ldst_immpre, 334 ldst_imm9, /* immpost or immpre */ 335 ldst_pos, 336 ldst_regoff, 337 ldst_unpriv, 338 ldst_unscaled, 339 ldstexcl, 340 ldstnapair_offs, 341 ldstpair_off, 342 ldstpair_indexed, 343 loadlit, 344 log_imm, 345 log_shift, 346 lse_atomic, 347 movewide, 348 pcreladdr, 349 ic_system, 350 testbranch, 351 }; 352 353 /* Opcode enumerators. */ 354 355 enum aarch64_op 356 { 357 OP_NIL, 358 OP_STRB_POS, 359 OP_LDRB_POS, 360 OP_LDRSB_POS, 361 OP_STRH_POS, 362 OP_LDRH_POS, 363 OP_LDRSH_POS, 364 OP_STR_POS, 365 OP_LDR_POS, 366 OP_STRF_POS, 367 OP_LDRF_POS, 368 OP_LDRSW_POS, 369 OP_PRFM_POS, 370 371 OP_STURB, 372 OP_LDURB, 373 OP_LDURSB, 374 OP_STURH, 375 OP_LDURH, 376 OP_LDURSH, 377 OP_STUR, 378 OP_LDUR, 379 OP_STURV, 380 OP_LDURV, 381 OP_LDURSW, 382 OP_PRFUM, 383 384 OP_LDR_LIT, 385 OP_LDRV_LIT, 386 OP_LDRSW_LIT, 387 OP_PRFM_LIT, 388 389 OP_ADD, 390 OP_B, 391 OP_BL, 392 393 OP_MOVN, 394 OP_MOVZ, 395 OP_MOVK, 396 397 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 398 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 399 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 400 401 OP_MOV_V, /* MOV alias for moving vector register. */ 402 403 OP_ASR_IMM, 404 OP_LSR_IMM, 405 OP_LSL_IMM, 406 407 OP_BIC, 408 409 OP_UBFX, 410 OP_BFXIL, 411 OP_SBFX, 412 OP_SBFIZ, 413 OP_BFI, 414 OP_UBFIZ, 415 OP_UXTB, 416 OP_UXTH, 417 OP_UXTW, 418 419 OP_CINC, 420 OP_CINV, 421 OP_CNEG, 422 OP_CSET, 423 OP_CSETM, 424 425 OP_FCVT, 426 OP_FCVTN, 427 OP_FCVTN2, 428 OP_FCVTL, 429 OP_FCVTL2, 430 OP_FCVTXN_S, /* Scalar version. */ 431 432 OP_ROR_IMM, 433 434 OP_SXTL, 435 OP_SXTL2, 436 OP_UXTL, 437 OP_UXTL2, 438 439 OP_TOTAL_NUM, /* Pseudo. */ 440 }; 441 442 /* Maximum number of operands an instruction can have. */ 443 #define AARCH64_MAX_OPND_NUM 6 444 /* Maximum number of qualifier sequences an instruction can have. */ 445 #define AARCH64_MAX_QLF_SEQ_NUM 10 446 /* Operand qualifier typedef; optimized for the size. */ 447 typedef unsigned char aarch64_opnd_qualifier_t; 448 /* Operand qualifier sequence typedef. */ 449 typedef aarch64_opnd_qualifier_t \ 450 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 451 452 /* FIXME: improve the efficiency. */ 453 static inline bfd_boolean 454 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 455 { 456 int i; 457 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 458 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 459 return FALSE; 460 return TRUE; 461 } 462 463 /* This structure holds information for a particular opcode. */ 464 465 struct aarch64_opcode 466 { 467 /* The name of the mnemonic. */ 468 const char *name; 469 470 /* The opcode itself. Those bits which will be filled in with 471 operands are zeroes. */ 472 aarch64_insn opcode; 473 474 /* The opcode mask. This is used by the disassembler. This is a 475 mask containing ones indicating those bits which must match the 476 opcode field, and zeroes indicating those bits which need not 477 match (and are presumably filled in by operands). */ 478 aarch64_insn mask; 479 480 /* Instruction class. */ 481 enum aarch64_insn_class iclass; 482 483 /* Enumerator identifier. */ 484 enum aarch64_op op; 485 486 /* Which architecture variant provides this instruction. */ 487 const aarch64_feature_set *avariant; 488 489 /* An array of operand codes. Each code is an index into the 490 operand table. They appear in the order which the operands must 491 appear in assembly code, and are terminated by a zero. */ 492 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 493 494 /* A list of operand qualifier code sequence. Each operand qualifier 495 code qualifies the corresponding operand code. Each operand 496 qualifier sequence specifies a valid opcode variant and related 497 constraint on operands. */ 498 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 499 500 /* Flags providing information about this instruction */ 501 uint32_t flags; 502 }; 503 504 typedef struct aarch64_opcode aarch64_opcode; 505 506 /* Table describing all the AArch64 opcodes. */ 507 extern aarch64_opcode aarch64_opcode_table[]; 508 509 /* Opcode flags. */ 510 #define F_ALIAS (1 << 0) 511 #define F_HAS_ALIAS (1 << 1) 512 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 513 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 514 #define F_P1 (1 << 2) 515 #define F_P2 (2 << 2) 516 #define F_P3 (3 << 2) 517 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 518 #define F_COND (1 << 4) 519 /* Instruction has the field of 'sf'. */ 520 #define F_SF (1 << 5) 521 /* Instruction has the field of 'size:Q'. */ 522 #define F_SIZEQ (1 << 6) 523 /* Floating-point instruction has the field of 'type'. */ 524 #define F_FPTYPE (1 << 7) 525 /* AdvSIMD scalar instruction has the field of 'size'. */ 526 #define F_SSIZE (1 << 8) 527 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 528 #define F_T (1 << 9) 529 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 530 #define F_GPRSIZE_IN_Q (1 << 10) 531 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 532 #define F_LDS_SIZE (1 << 11) 533 /* Optional operand; assume maximum of 1 operand can be optional. */ 534 #define F_OPD0_OPT (1 << 12) 535 #define F_OPD1_OPT (2 << 12) 536 #define F_OPD2_OPT (3 << 12) 537 #define F_OPD3_OPT (4 << 12) 538 #define F_OPD4_OPT (5 << 12) 539 /* Default value for the optional operand when omitted from the assembly. */ 540 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 541 /* Instruction that is an alias of another instruction needs to be 542 encoded/decoded by converting it to/from the real form, followed by 543 the encoding/decoding according to the rules of the real opcode. 544 This compares to the direct coding using the alias's information. 545 N.B. this flag requires F_ALIAS to be used together. */ 546 #define F_CONV (1 << 20) 547 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 548 friendly pseudo instruction available only in the assembly code (thus will 549 not show up in the disassembly). */ 550 #define F_PSEUDO (1 << 21) 551 /* Instruction has miscellaneous encoding/decoding rules. */ 552 #define F_MISC (1 << 22) 553 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 554 #define F_N (1 << 23) 555 /* Opcode dependent field. */ 556 #define F_OD(X) (((X) & 0x7) << 24) 557 /* Instruction has the field of 'sz'. */ 558 #define F_LSE_SZ (1 << 27) 559 /* Next bit is 28. */ 560 561 static inline bfd_boolean 562 alias_opcode_p (const aarch64_opcode *opcode) 563 { 564 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 565 } 566 567 static inline bfd_boolean 568 opcode_has_alias (const aarch64_opcode *opcode) 569 { 570 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 571 } 572 573 /* Priority for disassembling preference. */ 574 static inline int 575 opcode_priority (const aarch64_opcode *opcode) 576 { 577 return (opcode->flags >> 2) & 0x3; 578 } 579 580 static inline bfd_boolean 581 pseudo_opcode_p (const aarch64_opcode *opcode) 582 { 583 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 584 } 585 586 static inline bfd_boolean 587 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 588 { 589 return (((opcode->flags >> 12) & 0x7) == idx + 1) 590 ? TRUE : FALSE; 591 } 592 593 static inline aarch64_insn 594 get_optional_operand_default_value (const aarch64_opcode *opcode) 595 { 596 return (opcode->flags >> 15) & 0x1f; 597 } 598 599 static inline unsigned int 600 get_opcode_dependent_value (const aarch64_opcode *opcode) 601 { 602 return (opcode->flags >> 24) & 0x7; 603 } 604 605 static inline bfd_boolean 606 opcode_has_special_coder (const aarch64_opcode *opcode) 607 { 608 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 609 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 610 : FALSE; 611 } 612 613 struct aarch64_name_value_pair 615 { 616 const char * name; 617 aarch64_insn value; 618 }; 619 620 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 621 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 622 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 623 624 typedef struct 625 { 626 const char * name; 627 aarch64_insn value; 628 uint32_t flags; 629 } aarch64_sys_reg; 630 631 extern const aarch64_sys_reg aarch64_sys_regs []; 632 extern const aarch64_sys_reg aarch64_pstatefields []; 633 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 634 635 typedef struct 636 { 637 const char *template; 638 uint32_t value; 639 int has_xt; 640 } aarch64_sys_ins_reg; 641 642 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 643 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 644 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 645 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 646 647 /* Shift/extending operator kinds. 648 N.B. order is important; keep aarch64_operand_modifiers synced. */ 649 enum aarch64_modifier_kind 650 { 651 AARCH64_MOD_NONE, 652 AARCH64_MOD_MSL, 653 AARCH64_MOD_ROR, 654 AARCH64_MOD_ASR, 655 AARCH64_MOD_LSR, 656 AARCH64_MOD_LSL, 657 AARCH64_MOD_UXTB, 658 AARCH64_MOD_UXTH, 659 AARCH64_MOD_UXTW, 660 AARCH64_MOD_UXTX, 661 AARCH64_MOD_SXTB, 662 AARCH64_MOD_SXTH, 663 AARCH64_MOD_SXTW, 664 AARCH64_MOD_SXTX, 665 }; 666 667 bfd_boolean 668 aarch64_extend_operator_p (enum aarch64_modifier_kind); 669 670 enum aarch64_modifier_kind 671 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 672 /* Condition. */ 673 674 typedef struct 675 { 676 /* A list of names with the first one as the disassembly preference; 677 terminated by NULL if fewer than 3. */ 678 const char *names[3]; 679 aarch64_insn value; 680 } aarch64_cond; 681 682 extern const aarch64_cond aarch64_conds[16]; 683 684 const aarch64_cond* get_cond_from_value (aarch64_insn value); 685 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 686 687 /* Structure representing an operand. */ 689 690 struct aarch64_opnd_info 691 { 692 enum aarch64_opnd type; 693 aarch64_opnd_qualifier_t qualifier; 694 int idx; 695 696 union 697 { 698 struct 699 { 700 unsigned regno; 701 } reg; 702 struct 703 { 704 unsigned regno : 5; 705 unsigned index : 4; 706 } reglane; 707 /* e.g. LVn. */ 708 struct 709 { 710 unsigned first_regno : 5; 711 unsigned num_regs : 3; 712 /* 1 if it is a list of reg element. */ 713 unsigned has_index : 1; 714 /* Lane index; valid only when has_index is 1. */ 715 unsigned index : 4; 716 } reglist; 717 /* e.g. immediate or pc relative address offset. */ 718 struct 719 { 720 int64_t value; 721 unsigned is_fp : 1; 722 } imm; 723 /* e.g. address in STR (register offset). */ 724 struct 725 { 726 unsigned base_regno; 727 struct 728 { 729 union 730 { 731 int imm; 732 unsigned regno; 733 }; 734 unsigned is_reg; 735 } offset; 736 unsigned pcrel : 1; /* PC-relative. */ 737 unsigned writeback : 1; 738 unsigned preind : 1; /* Pre-indexed. */ 739 unsigned postind : 1; /* Post-indexed. */ 740 } addr; 741 const aarch64_cond *cond; 742 /* The encoding of the system register. */ 743 aarch64_insn sysreg; 744 /* The encoding of the PSTATE field. */ 745 aarch64_insn pstatefield; 746 const aarch64_sys_ins_reg *sysins_op; 747 const struct aarch64_name_value_pair *barrier; 748 const struct aarch64_name_value_pair *prfop; 749 }; 750 751 /* Operand shifter; in use when the operand is a register offset address, 752 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 753 struct 754 { 755 enum aarch64_modifier_kind kind; 756 int amount; 757 unsigned operator_present: 1; /* Only valid during encoding. */ 758 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 759 unsigned amount_present: 1; 760 } shifter; 761 762 unsigned skip:1; /* Operand is not completed if there is a fixup needed 763 to be done on it. In some (but not all) of these 764 cases, we need to tell libopcodes to skip the 765 constraint checking and the encoding for this 766 operand, so that the libopcodes can pick up the 767 right opcode before the operand is fixed-up. This 768 flag should only be used during the 769 assembling/encoding. */ 770 unsigned present:1; /* Whether this operand is present in the assembly 771 line; not used during the disassembly. */ 772 }; 773 774 typedef struct aarch64_opnd_info aarch64_opnd_info; 775 776 /* Structure representing an instruction. 777 778 It is used during both the assembling and disassembling. The assembler 779 fills an aarch64_inst after a successful parsing and then passes it to the 780 encoding routine to do the encoding. During the disassembling, the 781 disassembler calls the decoding routine to decode a binary instruction; on a 782 successful return, such a structure will be filled with information of the 783 instruction; then the disassembler uses the information to print out the 784 instruction. */ 785 786 struct aarch64_inst 787 { 788 /* The value of the binary instruction. */ 789 aarch64_insn value; 790 791 /* Corresponding opcode entry. */ 792 const aarch64_opcode *opcode; 793 794 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 795 const aarch64_cond *cond; 796 797 /* Operands information. */ 798 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 799 }; 800 801 typedef struct aarch64_inst aarch64_inst; 802 803 /* Diagnosis related declaration and interface. */ 805 806 /* Operand error kind enumerators. 807 808 AARCH64_OPDE_RECOVERABLE 809 Less severe error found during the parsing, very possibly because that 810 GAS has picked up a wrong instruction template for the parsing. 811 812 AARCH64_OPDE_SYNTAX_ERROR 813 General syntax error; it can be either a user error, or simply because 814 that GAS is trying a wrong instruction template. 815 816 AARCH64_OPDE_FATAL_SYNTAX_ERROR 817 Definitely a user syntax error. 818 819 AARCH64_OPDE_INVALID_VARIANT 820 No syntax error, but the operands are not a valid combination, e.g. 821 FMOV D0,S0 822 823 AARCH64_OPDE_OUT_OF_RANGE 824 Error about some immediate value out of a valid range. 825 826 AARCH64_OPDE_UNALIGNED 827 Error about some immediate value not properly aligned (i.e. not being a 828 multiple times of a certain value). 829 830 AARCH64_OPDE_REG_LIST 831 Error about the register list operand having unexpected number of 832 registers. 833 834 AARCH64_OPDE_OTHER_ERROR 835 Error of the highest severity and used for any severe issue that does not 836 fall into any of the above categories. 837 838 The enumerators are only interesting to GAS. They are declared here (in 839 libopcodes) because that some errors are detected (and then notified to GAS) 840 by libopcodes (rather than by GAS solely). 841 842 The first three errors are only deteced by GAS while the 843 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 844 only libopcodes has the information about the valid variants of each 845 instruction. 846 847 The enumerators have an increasing severity. This is helpful when there are 848 multiple instruction templates available for a given mnemonic name (e.g. 849 FMOV); this mechanism will help choose the most suitable template from which 850 the generated diagnostics can most closely describe the issues, if any. */ 851 852 enum aarch64_operand_error_kind 853 { 854 AARCH64_OPDE_NIL, 855 AARCH64_OPDE_RECOVERABLE, 856 AARCH64_OPDE_SYNTAX_ERROR, 857 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 858 AARCH64_OPDE_INVALID_VARIANT, 859 AARCH64_OPDE_OUT_OF_RANGE, 860 AARCH64_OPDE_UNALIGNED, 861 AARCH64_OPDE_REG_LIST, 862 AARCH64_OPDE_OTHER_ERROR 863 }; 864 865 /* N.B. GAS assumes that this structure work well with shallow copy. */ 866 struct aarch64_operand_error 867 { 868 enum aarch64_operand_error_kind kind; 869 int index; 870 const char *error; 871 int data[3]; /* Some data for extra information. */ 872 }; 873 874 typedef struct aarch64_operand_error aarch64_operand_error; 875 876 /* Encoding entrypoint. */ 877 878 extern int 879 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 880 aarch64_insn *, aarch64_opnd_qualifier_t *, 881 aarch64_operand_error *); 882 883 extern const aarch64_opcode * 884 aarch64_replace_opcode (struct aarch64_inst *, 885 const aarch64_opcode *); 886 887 /* Given the opcode enumerator OP, return the pointer to the corresponding 888 opcode entry. */ 889 890 extern const aarch64_opcode * 891 aarch64_get_opcode (enum aarch64_op); 892 893 /* Generate the string representation of an operand. */ 894 extern void 895 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 896 const aarch64_opnd_info *, int, int *, bfd_vma *); 897 898 /* Miscellaneous interface. */ 899 900 extern int 901 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 902 903 extern aarch64_opnd_qualifier_t 904 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 905 const aarch64_opnd_qualifier_t, int); 906 907 extern int 908 aarch64_num_of_operands (const aarch64_opcode *); 909 910 extern int 911 aarch64_stack_pointer_p (const aarch64_opnd_info *); 912 913 extern 914 int aarch64_zero_register_p (const aarch64_opnd_info *); 915 916 /* Given an operand qualifier, return the expected data element size 917 of a qualified operand. */ 918 extern unsigned char 919 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 920 921 extern enum aarch64_operand_class 922 aarch64_get_operand_class (enum aarch64_opnd); 923 924 extern const char * 925 aarch64_get_operand_name (enum aarch64_opnd); 926 927 extern const char * 928 aarch64_get_operand_desc (enum aarch64_opnd); 929 930 #ifdef DEBUG_AARCH64 931 extern int debug_dump; 932 933 extern void 934 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 935 936 #define DEBUG_TRACE(M, ...) \ 937 { \ 938 if (debug_dump) \ 939 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 940 } 941 942 #define DEBUG_TRACE_IF(C, M, ...) \ 943 { \ 944 if (debug_dump && (C)) \ 945 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 946 } 947 #else /* !DEBUG_AARCH64 */ 948 #define DEBUG_TRACE(M, ...) ; 949 #define DEBUG_TRACE_IF(C, M, ...) ; 950 #endif /* DEBUG_AARCH64 */ 951 952 #endif /* OPCODE_AARCH64_H */ 953
Indexes created Sat Mar 28 00:23:22 UTC 2026