aarch64.h revision 1.1.1.5
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2016 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* The offset for pc-relative addressing is currently defined to be 0. */ 35 #define AARCH64_PCREL_OFFSET 0 36 37 typedef uint32_t aarch64_insn; 38 39 /* The following bitmasks control CPU features. */ 40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ 42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ 47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ 48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ 49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ 50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ 51 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ 52 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ 53 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ 54 55 /* Architectures are the sum of the base and extensions. */ 56 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 57 AARCH64_FEATURE_FP \ 58 | AARCH64_FEATURE_SIMD) 59 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 60 AARCH64_FEATURE_FP \ 61 | AARCH64_FEATURE_SIMD \ 62 | AARCH64_FEATURE_CRC \ 63 | AARCH64_FEATURE_V8_1 \ 64 | AARCH64_FEATURE_LSE \ 65 | AARCH64_FEATURE_PAN \ 66 | AARCH64_FEATURE_LOR \ 67 | AARCH64_FEATURE_RDMA) 68 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 69 AARCH64_FEATURE_V8_2 \ 70 | AARCH64_FEATURE_F16 \ 71 | AARCH64_FEATURE_RAS \ 72 | AARCH64_FEATURE_FP \ 73 | AARCH64_FEATURE_SIMD \ 74 | AARCH64_FEATURE_CRC \ 75 | AARCH64_FEATURE_V8_1 \ 76 | AARCH64_FEATURE_LSE \ 77 | AARCH64_FEATURE_PAN \ 78 | AARCH64_FEATURE_LOR \ 79 | AARCH64_FEATURE_RDMA) 80 81 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 82 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 83 84 /* CPU-specific features. */ 85 typedef unsigned long aarch64_feature_set; 86 87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 88 ((~(CPU) & (FEAT)) == 0) 89 90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 91 (((CPU) & (FEAT)) != 0) 92 93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 94 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 95 96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 97 do \ 98 { \ 99 (TARG) = (F1) | (F2); \ 100 } \ 101 while (0) 102 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 104 do \ 105 { \ 106 (TARG) = (F1) &~ (F2); \ 107 } \ 108 while (0) 109 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 111 112 enum aarch64_operand_class 113 { 114 AARCH64_OPND_CLASS_NIL, 115 AARCH64_OPND_CLASS_INT_REG, 116 AARCH64_OPND_CLASS_MODIFIED_REG, 117 AARCH64_OPND_CLASS_FP_REG, 118 AARCH64_OPND_CLASS_SIMD_REG, 119 AARCH64_OPND_CLASS_SIMD_ELEMENT, 120 AARCH64_OPND_CLASS_SISD_REG, 121 AARCH64_OPND_CLASS_SIMD_REGLIST, 122 AARCH64_OPND_CLASS_CP_REG, 123 AARCH64_OPND_CLASS_ADDRESS, 124 AARCH64_OPND_CLASS_IMMEDIATE, 125 AARCH64_OPND_CLASS_SYSTEM, 126 AARCH64_OPND_CLASS_COND, 127 }; 128 129 /* Operand code that helps both parsing and coding. 130 Keep AARCH64_OPERANDS synced. */ 131 132 enum aarch64_opnd 133 { 134 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 135 136 AARCH64_OPND_Rd, /* Integer register as destination. */ 137 AARCH64_OPND_Rn, /* Integer register as source. */ 138 AARCH64_OPND_Rm, /* Integer register as source. */ 139 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 140 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 141 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 142 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 143 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 144 145 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 146 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 147 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 148 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 149 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 150 151 AARCH64_OPND_Fd, /* Floating-point Fd. */ 152 AARCH64_OPND_Fn, /* Floating-point Fn. */ 153 AARCH64_OPND_Fm, /* Floating-point Fm. */ 154 AARCH64_OPND_Fa, /* Floating-point Fa. */ 155 AARCH64_OPND_Ft, /* Floating-point Ft. */ 156 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 157 158 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 159 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 160 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 161 162 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 163 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 164 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 165 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 166 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 167 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 168 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 169 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 170 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 171 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 172 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 173 structure to all lanes. */ 174 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 175 176 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 177 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 178 179 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 180 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 181 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 182 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 183 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 184 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 185 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 186 (no encoding). */ 187 AARCH64_OPND_IMM0, /* Immediate for #0. */ 188 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 189 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 190 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 191 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 192 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 193 AARCH64_OPND_IMM, /* Immediate. */ 194 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 195 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 196 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 197 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 198 AARCH64_OPND_BIT_NUM, /* Immediate. */ 199 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 200 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 201 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 202 each condition flag. */ 203 204 AARCH64_OPND_LIMM, /* Logical Immediate. */ 205 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 206 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 207 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 208 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 209 210 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 211 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 212 213 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 214 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 215 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 216 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 217 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 218 219 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 220 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 221 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 222 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 223 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 224 negative or unaligned and there is 225 no writeback allowed. This operand code 226 is only used to support the programmer- 227 friendly feature of using LDR/STR as the 228 the mnemonic name for LDUR/STUR instructions 229 wherever there is no ambiguity. */ 230 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 231 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 232 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 233 234 AARCH64_OPND_SYSREG, /* System register operand. */ 235 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 236 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 237 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 238 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 239 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 240 AARCH64_OPND_BARRIER, /* Barrier operand. */ 241 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 242 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 243 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 244 }; 245 246 /* Qualifier constrains an operand. It either specifies a variant of an 247 operand type or limits values available to an operand type. 248 249 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 250 251 enum aarch64_opnd_qualifier 252 { 253 /* Indicating no further qualification on an operand. */ 254 AARCH64_OPND_QLF_NIL, 255 256 /* Qualifying an operand which is a general purpose (integer) register; 257 indicating the operand data size or a specific register. */ 258 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 259 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 260 AARCH64_OPND_QLF_WSP, /* WSP. */ 261 AARCH64_OPND_QLF_SP, /* SP. */ 262 263 /* Qualifying an operand which is a floating-point register, a SIMD 264 vector element or a SIMD vector element list; indicating operand data 265 size or the size of each SIMD vector element in the case of a SIMD 266 vector element list. 267 These qualifiers are also used to qualify an address operand to 268 indicate the size of data element a load/store instruction is 269 accessing. 270 They are also used for the immediate shift operand in e.g. SSHR. Such 271 a use is only for the ease of operand encoding/decoding and qualifier 272 sequence matching; such a use should not be applied widely; use the value 273 constraint qualifiers for immediate operands wherever possible. */ 274 AARCH64_OPND_QLF_S_B, 275 AARCH64_OPND_QLF_S_H, 276 AARCH64_OPND_QLF_S_S, 277 AARCH64_OPND_QLF_S_D, 278 AARCH64_OPND_QLF_S_Q, 279 280 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 281 register list; indicating register shape. 282 They are also used for the immediate shift operand in e.g. SSHR. Such 283 a use is only for the ease of operand encoding/decoding and qualifier 284 sequence matching; such a use should not be applied widely; use the value 285 constraint qualifiers for immediate operands wherever possible. */ 286 AARCH64_OPND_QLF_V_8B, 287 AARCH64_OPND_QLF_V_16B, 288 AARCH64_OPND_QLF_V_2H, 289 AARCH64_OPND_QLF_V_4H, 290 AARCH64_OPND_QLF_V_8H, 291 AARCH64_OPND_QLF_V_2S, 292 AARCH64_OPND_QLF_V_4S, 293 AARCH64_OPND_QLF_V_1D, 294 AARCH64_OPND_QLF_V_2D, 295 AARCH64_OPND_QLF_V_1Q, 296 297 /* Constraint on value. */ 298 AARCH64_OPND_QLF_imm_0_7, 299 AARCH64_OPND_QLF_imm_0_15, 300 AARCH64_OPND_QLF_imm_0_31, 301 AARCH64_OPND_QLF_imm_0_63, 302 AARCH64_OPND_QLF_imm_1_32, 303 AARCH64_OPND_QLF_imm_1_64, 304 305 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 306 or shift-ones. */ 307 AARCH64_OPND_QLF_LSL, 308 AARCH64_OPND_QLF_MSL, 309 310 /* Special qualifier helping retrieve qualifier information during the 311 decoding time (currently not in use). */ 312 AARCH64_OPND_QLF_RETRIEVE, 313 }; 314 315 /* Instruction class. */ 317 318 enum aarch64_insn_class 319 { 320 addsub_carry, 321 addsub_ext, 322 addsub_imm, 323 addsub_shift, 324 asimdall, 325 asimddiff, 326 asimdelem, 327 asimdext, 328 asimdimm, 329 asimdins, 330 asimdmisc, 331 asimdperm, 332 asimdsame, 333 asimdshf, 334 asimdtbl, 335 asisddiff, 336 asisdelem, 337 asisdlse, 338 asisdlsep, 339 asisdlso, 340 asisdlsop, 341 asisdmisc, 342 asisdone, 343 asisdpair, 344 asisdsame, 345 asisdshf, 346 bitfield, 347 branch_imm, 348 branch_reg, 349 compbranch, 350 condbranch, 351 condcmp_imm, 352 condcmp_reg, 353 condsel, 354 cryptoaes, 355 cryptosha2, 356 cryptosha3, 357 dp_1src, 358 dp_2src, 359 dp_3src, 360 exception, 361 extract, 362 float2fix, 363 float2int, 364 floatccmp, 365 floatcmp, 366 floatdp1, 367 floatdp2, 368 floatdp3, 369 floatimm, 370 floatsel, 371 ldst_immpost, 372 ldst_immpre, 373 ldst_imm9, /* immpost or immpre */ 374 ldst_pos, 375 ldst_regoff, 376 ldst_unpriv, 377 ldst_unscaled, 378 ldstexcl, 379 ldstnapair_offs, 380 ldstpair_off, 381 ldstpair_indexed, 382 loadlit, 383 log_imm, 384 log_shift, 385 lse_atomic, 386 movewide, 387 pcreladdr, 388 ic_system, 389 testbranch, 390 }; 391 392 /* Opcode enumerators. */ 393 394 enum aarch64_op 395 { 396 OP_NIL, 397 OP_STRB_POS, 398 OP_LDRB_POS, 399 OP_LDRSB_POS, 400 OP_STRH_POS, 401 OP_LDRH_POS, 402 OP_LDRSH_POS, 403 OP_STR_POS, 404 OP_LDR_POS, 405 OP_STRF_POS, 406 OP_LDRF_POS, 407 OP_LDRSW_POS, 408 OP_PRFM_POS, 409 410 OP_STURB, 411 OP_LDURB, 412 OP_LDURSB, 413 OP_STURH, 414 OP_LDURH, 415 OP_LDURSH, 416 OP_STUR, 417 OP_LDUR, 418 OP_STURV, 419 OP_LDURV, 420 OP_LDURSW, 421 OP_PRFUM, 422 423 OP_LDR_LIT, 424 OP_LDRV_LIT, 425 OP_LDRSW_LIT, 426 OP_PRFM_LIT, 427 428 OP_ADD, 429 OP_B, 430 OP_BL, 431 432 OP_MOVN, 433 OP_MOVZ, 434 OP_MOVK, 435 436 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 437 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 438 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 439 440 OP_MOV_V, /* MOV alias for moving vector register. */ 441 442 OP_ASR_IMM, 443 OP_LSR_IMM, 444 OP_LSL_IMM, 445 446 OP_BIC, 447 448 OP_UBFX, 449 OP_BFXIL, 450 OP_SBFX, 451 OP_SBFIZ, 452 OP_BFI, 453 OP_BFC, /* ARMv8.2. */ 454 OP_UBFIZ, 455 OP_UXTB, 456 OP_UXTH, 457 OP_UXTW, 458 459 OP_CINC, 460 OP_CINV, 461 OP_CNEG, 462 OP_CSET, 463 OP_CSETM, 464 465 OP_FCVT, 466 OP_FCVTN, 467 OP_FCVTN2, 468 OP_FCVTL, 469 OP_FCVTL2, 470 OP_FCVTXN_S, /* Scalar version. */ 471 472 OP_ROR_IMM, 473 474 OP_SXTL, 475 OP_SXTL2, 476 OP_UXTL, 477 OP_UXTL2, 478 479 OP_TOTAL_NUM, /* Pseudo. */ 480 }; 481 482 /* Maximum number of operands an instruction can have. */ 483 #define AARCH64_MAX_OPND_NUM 6 484 /* Maximum number of qualifier sequences an instruction can have. */ 485 #define AARCH64_MAX_QLF_SEQ_NUM 10 486 /* Operand qualifier typedef; optimized for the size. */ 487 typedef unsigned char aarch64_opnd_qualifier_t; 488 /* Operand qualifier sequence typedef. */ 489 typedef aarch64_opnd_qualifier_t \ 490 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 491 492 /* FIXME: improve the efficiency. */ 493 static inline bfd_boolean 494 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 495 { 496 int i; 497 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 498 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 499 return FALSE; 500 return TRUE; 501 } 502 503 /* This structure holds information for a particular opcode. */ 504 505 struct aarch64_opcode 506 { 507 /* The name of the mnemonic. */ 508 const char *name; 509 510 /* The opcode itself. Those bits which will be filled in with 511 operands are zeroes. */ 512 aarch64_insn opcode; 513 514 /* The opcode mask. This is used by the disassembler. This is a 515 mask containing ones indicating those bits which must match the 516 opcode field, and zeroes indicating those bits which need not 517 match (and are presumably filled in by operands). */ 518 aarch64_insn mask; 519 520 /* Instruction class. */ 521 enum aarch64_insn_class iclass; 522 523 /* Enumerator identifier. */ 524 enum aarch64_op op; 525 526 /* Which architecture variant provides this instruction. */ 527 const aarch64_feature_set *avariant; 528 529 /* An array of operand codes. Each code is an index into the 530 operand table. They appear in the order which the operands must 531 appear in assembly code, and are terminated by a zero. */ 532 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 533 534 /* A list of operand qualifier code sequence. Each operand qualifier 535 code qualifies the corresponding operand code. Each operand 536 qualifier sequence specifies a valid opcode variant and related 537 constraint on operands. */ 538 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 539 540 /* Flags providing information about this instruction */ 541 uint32_t flags; 542 543 /* If non-NULL, a function to verify that a given instruction is valid. */ 544 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); 545 }; 546 547 typedef struct aarch64_opcode aarch64_opcode; 548 549 /* Table describing all the AArch64 opcodes. */ 550 extern aarch64_opcode aarch64_opcode_table[]; 551 552 /* Opcode flags. */ 553 #define F_ALIAS (1 << 0) 554 #define F_HAS_ALIAS (1 << 1) 555 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 556 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 557 #define F_P1 (1 << 2) 558 #define F_P2 (2 << 2) 559 #define F_P3 (3 << 2) 560 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 561 #define F_COND (1 << 4) 562 /* Instruction has the field of 'sf'. */ 563 #define F_SF (1 << 5) 564 /* Instruction has the field of 'size:Q'. */ 565 #define F_SIZEQ (1 << 6) 566 /* Floating-point instruction has the field of 'type'. */ 567 #define F_FPTYPE (1 << 7) 568 /* AdvSIMD scalar instruction has the field of 'size'. */ 569 #define F_SSIZE (1 << 8) 570 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 571 #define F_T (1 << 9) 572 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 573 #define F_GPRSIZE_IN_Q (1 << 10) 574 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 575 #define F_LDS_SIZE (1 << 11) 576 /* Optional operand; assume maximum of 1 operand can be optional. */ 577 #define F_OPD0_OPT (1 << 12) 578 #define F_OPD1_OPT (2 << 12) 579 #define F_OPD2_OPT (3 << 12) 580 #define F_OPD3_OPT (4 << 12) 581 #define F_OPD4_OPT (5 << 12) 582 /* Default value for the optional operand when omitted from the assembly. */ 583 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 584 /* Instruction that is an alias of another instruction needs to be 585 encoded/decoded by converting it to/from the real form, followed by 586 the encoding/decoding according to the rules of the real opcode. 587 This compares to the direct coding using the alias's information. 588 N.B. this flag requires F_ALIAS to be used together. */ 589 #define F_CONV (1 << 20) 590 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 591 friendly pseudo instruction available only in the assembly code (thus will 592 not show up in the disassembly). */ 593 #define F_PSEUDO (1 << 21) 594 /* Instruction has miscellaneous encoding/decoding rules. */ 595 #define F_MISC (1 << 22) 596 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 597 #define F_N (1 << 23) 598 /* Opcode dependent field. */ 599 #define F_OD(X) (((X) & 0x7) << 24) 600 /* Instruction has the field of 'sz'. */ 601 #define F_LSE_SZ (1 << 27) 602 /* Next bit is 28. */ 603 604 static inline bfd_boolean 605 alias_opcode_p (const aarch64_opcode *opcode) 606 { 607 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 608 } 609 610 static inline bfd_boolean 611 opcode_has_alias (const aarch64_opcode *opcode) 612 { 613 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 614 } 615 616 /* Priority for disassembling preference. */ 617 static inline int 618 opcode_priority (const aarch64_opcode *opcode) 619 { 620 return (opcode->flags >> 2) & 0x3; 621 } 622 623 static inline bfd_boolean 624 pseudo_opcode_p (const aarch64_opcode *opcode) 625 { 626 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 627 } 628 629 static inline bfd_boolean 630 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 631 { 632 return (((opcode->flags >> 12) & 0x7) == idx + 1) 633 ? TRUE : FALSE; 634 } 635 636 static inline aarch64_insn 637 get_optional_operand_default_value (const aarch64_opcode *opcode) 638 { 639 return (opcode->flags >> 15) & 0x1f; 640 } 641 642 static inline unsigned int 643 get_opcode_dependent_value (const aarch64_opcode *opcode) 644 { 645 return (opcode->flags >> 24) & 0x7; 646 } 647 648 static inline bfd_boolean 649 opcode_has_special_coder (const aarch64_opcode *opcode) 650 { 651 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 652 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 653 : FALSE; 654 } 655 656 struct aarch64_name_value_pair 658 { 659 const char * name; 660 aarch64_insn value; 661 }; 662 663 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 664 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 665 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 666 extern const struct aarch64_name_value_pair aarch64_hint_options []; 667 668 typedef struct 669 { 670 const char * name; 671 aarch64_insn value; 672 uint32_t flags; 673 } aarch64_sys_reg; 674 675 extern const aarch64_sys_reg aarch64_sys_regs []; 676 extern const aarch64_sys_reg aarch64_pstatefields []; 677 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 678 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, 679 const aarch64_sys_reg *); 680 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, 681 const aarch64_sys_reg *); 682 683 typedef struct 684 { 685 const char *name; 686 uint32_t value; 687 uint32_t flags ; 688 } aarch64_sys_ins_reg; 689 690 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 691 extern bfd_boolean 692 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 693 const aarch64_sys_ins_reg *); 694 695 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 696 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 697 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 698 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 699 700 /* Shift/extending operator kinds. 701 N.B. order is important; keep aarch64_operand_modifiers synced. */ 702 enum aarch64_modifier_kind 703 { 704 AARCH64_MOD_NONE, 705 AARCH64_MOD_MSL, 706 AARCH64_MOD_ROR, 707 AARCH64_MOD_ASR, 708 AARCH64_MOD_LSR, 709 AARCH64_MOD_LSL, 710 AARCH64_MOD_UXTB, 711 AARCH64_MOD_UXTH, 712 AARCH64_MOD_UXTW, 713 AARCH64_MOD_UXTX, 714 AARCH64_MOD_SXTB, 715 AARCH64_MOD_SXTH, 716 AARCH64_MOD_SXTW, 717 AARCH64_MOD_SXTX, 718 }; 719 720 bfd_boolean 721 aarch64_extend_operator_p (enum aarch64_modifier_kind); 722 723 enum aarch64_modifier_kind 724 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 725 /* Condition. */ 726 727 typedef struct 728 { 729 /* A list of names with the first one as the disassembly preference; 730 terminated by NULL if fewer than 3. */ 731 const char *names[3]; 732 aarch64_insn value; 733 } aarch64_cond; 734 735 extern const aarch64_cond aarch64_conds[16]; 736 737 const aarch64_cond* get_cond_from_value (aarch64_insn value); 738 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 739 740 /* Structure representing an operand. */ 742 743 struct aarch64_opnd_info 744 { 745 enum aarch64_opnd type; 746 aarch64_opnd_qualifier_t qualifier; 747 int idx; 748 749 union 750 { 751 struct 752 { 753 unsigned regno; 754 } reg; 755 struct 756 { 757 unsigned int regno; 758 int64_t index; 759 } reglane; 760 /* e.g. LVn. */ 761 struct 762 { 763 unsigned first_regno : 5; 764 unsigned num_regs : 3; 765 /* 1 if it is a list of reg element. */ 766 unsigned has_index : 1; 767 /* Lane index; valid only when has_index is 1. */ 768 int64_t index; 769 } reglist; 770 /* e.g. immediate or pc relative address offset. */ 771 struct 772 { 773 int64_t value; 774 unsigned is_fp : 1; 775 } imm; 776 /* e.g. address in STR (register offset). */ 777 struct 778 { 779 unsigned base_regno; 780 struct 781 { 782 union 783 { 784 int imm; 785 unsigned regno; 786 }; 787 unsigned is_reg; 788 } offset; 789 unsigned pcrel : 1; /* PC-relative. */ 790 unsigned writeback : 1; 791 unsigned preind : 1; /* Pre-indexed. */ 792 unsigned postind : 1; /* Post-indexed. */ 793 } addr; 794 const aarch64_cond *cond; 795 /* The encoding of the system register. */ 796 aarch64_insn sysreg; 797 /* The encoding of the PSTATE field. */ 798 aarch64_insn pstatefield; 799 const aarch64_sys_ins_reg *sysins_op; 800 const struct aarch64_name_value_pair *barrier; 801 const struct aarch64_name_value_pair *hint_option; 802 const struct aarch64_name_value_pair *prfop; 803 }; 804 805 /* Operand shifter; in use when the operand is a register offset address, 806 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 807 struct 808 { 809 enum aarch64_modifier_kind kind; 810 int amount; 811 unsigned operator_present: 1; /* Only valid during encoding. */ 812 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 813 unsigned amount_present: 1; 814 } shifter; 815 816 unsigned skip:1; /* Operand is not completed if there is a fixup needed 817 to be done on it. In some (but not all) of these 818 cases, we need to tell libopcodes to skip the 819 constraint checking and the encoding for this 820 operand, so that the libopcodes can pick up the 821 right opcode before the operand is fixed-up. This 822 flag should only be used during the 823 assembling/encoding. */ 824 unsigned present:1; /* Whether this operand is present in the assembly 825 line; not used during the disassembly. */ 826 }; 827 828 typedef struct aarch64_opnd_info aarch64_opnd_info; 829 830 /* Structure representing an instruction. 831 832 It is used during both the assembling and disassembling. The assembler 833 fills an aarch64_inst after a successful parsing and then passes it to the 834 encoding routine to do the encoding. During the disassembling, the 835 disassembler calls the decoding routine to decode a binary instruction; on a 836 successful return, such a structure will be filled with information of the 837 instruction; then the disassembler uses the information to print out the 838 instruction. */ 839 840 struct aarch64_inst 841 { 842 /* The value of the binary instruction. */ 843 aarch64_insn value; 844 845 /* Corresponding opcode entry. */ 846 const aarch64_opcode *opcode; 847 848 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 849 const aarch64_cond *cond; 850 851 /* Operands information. */ 852 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 853 }; 854 855 typedef struct aarch64_inst aarch64_inst; 856 857 /* Diagnosis related declaration and interface. */ 859 860 /* Operand error kind enumerators. 861 862 AARCH64_OPDE_RECOVERABLE 863 Less severe error found during the parsing, very possibly because that 864 GAS has picked up a wrong instruction template for the parsing. 865 866 AARCH64_OPDE_SYNTAX_ERROR 867 General syntax error; it can be either a user error, or simply because 868 that GAS is trying a wrong instruction template. 869 870 AARCH64_OPDE_FATAL_SYNTAX_ERROR 871 Definitely a user syntax error. 872 873 AARCH64_OPDE_INVALID_VARIANT 874 No syntax error, but the operands are not a valid combination, e.g. 875 FMOV D0,S0 876 877 AARCH64_OPDE_OUT_OF_RANGE 878 Error about some immediate value out of a valid range. 879 880 AARCH64_OPDE_UNALIGNED 881 Error about some immediate value not properly aligned (i.e. not being a 882 multiple times of a certain value). 883 884 AARCH64_OPDE_REG_LIST 885 Error about the register list operand having unexpected number of 886 registers. 887 888 AARCH64_OPDE_OTHER_ERROR 889 Error of the highest severity and used for any severe issue that does not 890 fall into any of the above categories. 891 892 The enumerators are only interesting to GAS. They are declared here (in 893 libopcodes) because that some errors are detected (and then notified to GAS) 894 by libopcodes (rather than by GAS solely). 895 896 The first three errors are only deteced by GAS while the 897 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 898 only libopcodes has the information about the valid variants of each 899 instruction. 900 901 The enumerators have an increasing severity. This is helpful when there are 902 multiple instruction templates available for a given mnemonic name (e.g. 903 FMOV); this mechanism will help choose the most suitable template from which 904 the generated diagnostics can most closely describe the issues, if any. */ 905 906 enum aarch64_operand_error_kind 907 { 908 AARCH64_OPDE_NIL, 909 AARCH64_OPDE_RECOVERABLE, 910 AARCH64_OPDE_SYNTAX_ERROR, 911 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 912 AARCH64_OPDE_INVALID_VARIANT, 913 AARCH64_OPDE_OUT_OF_RANGE, 914 AARCH64_OPDE_UNALIGNED, 915 AARCH64_OPDE_REG_LIST, 916 AARCH64_OPDE_OTHER_ERROR 917 }; 918 919 /* N.B. GAS assumes that this structure work well with shallow copy. */ 920 struct aarch64_operand_error 921 { 922 enum aarch64_operand_error_kind kind; 923 int index; 924 const char *error; 925 int data[3]; /* Some data for extra information. */ 926 }; 927 928 typedef struct aarch64_operand_error aarch64_operand_error; 929 930 /* Encoding entrypoint. */ 931 932 extern int 933 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 934 aarch64_insn *, aarch64_opnd_qualifier_t *, 935 aarch64_operand_error *); 936 937 extern const aarch64_opcode * 938 aarch64_replace_opcode (struct aarch64_inst *, 939 const aarch64_opcode *); 940 941 /* Given the opcode enumerator OP, return the pointer to the corresponding 942 opcode entry. */ 943 944 extern const aarch64_opcode * 945 aarch64_get_opcode (enum aarch64_op); 946 947 /* Generate the string representation of an operand. */ 948 extern void 949 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 950 const aarch64_opnd_info *, int, int *, bfd_vma *); 951 952 /* Miscellaneous interface. */ 953 954 extern int 955 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 956 957 extern aarch64_opnd_qualifier_t 958 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 959 const aarch64_opnd_qualifier_t, int); 960 961 extern int 962 aarch64_num_of_operands (const aarch64_opcode *); 963 964 extern int 965 aarch64_stack_pointer_p (const aarch64_opnd_info *); 966 967 extern int 968 aarch64_zero_register_p (const aarch64_opnd_info *); 969 970 extern int 971 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); 972 973 /* Given an operand qualifier, return the expected data element size 974 of a qualified operand. */ 975 extern unsigned char 976 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 977 978 extern enum aarch64_operand_class 979 aarch64_get_operand_class (enum aarch64_opnd); 980 981 extern const char * 982 aarch64_get_operand_name (enum aarch64_opnd); 983 984 extern const char * 985 aarch64_get_operand_desc (enum aarch64_opnd); 986 987 #ifdef DEBUG_AARCH64 988 extern int debug_dump; 989 990 extern void 991 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 992 993 #define DEBUG_TRACE(M, ...) \ 994 { \ 995 if (debug_dump) \ 996 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 997 } 998 999 #define DEBUG_TRACE_IF(C, M, ...) \ 1000 { \ 1001 if (debug_dump && (C)) \ 1002 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1003 } 1004 #else /* !DEBUG_AARCH64 */ 1005 #define DEBUG_TRACE(M, ...) ; 1006 #define DEBUG_TRACE_IF(C, M, ...) ; 1007 #endif /* DEBUG_AARCH64 */ 1008 1009 #ifdef __cplusplus 1010 } 1011 #endif 1012 1013 #endif /* OPCODE_AARCH64_H */ 1014
Indexes created Sat Mar 28 00:23:22 UTC 2026