aarch64.h revision 1.1.1.6
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2017 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* The offset for pc-relative addressing is currently defined to be 0. */ 35 #define AARCH64_PCREL_OFFSET 0 36 37 typedef uint32_t aarch64_insn; 38 39 /* The following bitmasks control CPU features. */ 40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ 42 #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ 43 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 44 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 45 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 46 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 47 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ 48 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ 49 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ 50 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ 51 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ 52 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ 53 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ 54 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ 55 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ 56 #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ 57 #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ 58 59 /* Architectures are the sum of the base and extensions. */ 60 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 61 AARCH64_FEATURE_FP \ 62 | AARCH64_FEATURE_SIMD) 63 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ 64 AARCH64_FEATURE_CRC \ 65 | AARCH64_FEATURE_V8_1 \ 66 | AARCH64_FEATURE_LSE \ 67 | AARCH64_FEATURE_PAN \ 68 | AARCH64_FEATURE_LOR \ 69 | AARCH64_FEATURE_RDMA) 70 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ 71 AARCH64_FEATURE_V8_2 \ 72 | AARCH64_FEATURE_F16 \ 73 | AARCH64_FEATURE_RAS) 74 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ 75 AARCH64_FEATURE_V8_3 \ 76 | AARCH64_FEATURE_RCPC \ 77 | AARCH64_FEATURE_COMPNUM) 78 79 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 80 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 81 82 /* CPU-specific features. */ 83 typedef unsigned long aarch64_feature_set; 84 85 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 86 ((~(CPU) & (FEAT)) == 0) 87 88 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 89 (((CPU) & (FEAT)) != 0) 90 91 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 92 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 93 94 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 95 do \ 96 { \ 97 (TARG) = (F1) | (F2); \ 98 } \ 99 while (0) 100 101 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 102 do \ 103 { \ 104 (TARG) = (F1) &~ (F2); \ 105 } \ 106 while (0) 107 108 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 109 110 enum aarch64_operand_class 111 { 112 AARCH64_OPND_CLASS_NIL, 113 AARCH64_OPND_CLASS_INT_REG, 114 AARCH64_OPND_CLASS_MODIFIED_REG, 115 AARCH64_OPND_CLASS_FP_REG, 116 AARCH64_OPND_CLASS_SIMD_REG, 117 AARCH64_OPND_CLASS_SIMD_ELEMENT, 118 AARCH64_OPND_CLASS_SISD_REG, 119 AARCH64_OPND_CLASS_SIMD_REGLIST, 120 AARCH64_OPND_CLASS_SVE_REG, 121 AARCH64_OPND_CLASS_PRED_REG, 122 AARCH64_OPND_CLASS_ADDRESS, 123 AARCH64_OPND_CLASS_IMMEDIATE, 124 AARCH64_OPND_CLASS_SYSTEM, 125 AARCH64_OPND_CLASS_COND, 126 }; 127 128 /* Operand code that helps both parsing and coding. 129 Keep AARCH64_OPERANDS synced. */ 130 131 enum aarch64_opnd 132 { 133 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 134 135 AARCH64_OPND_Rd, /* Integer register as destination. */ 136 AARCH64_OPND_Rn, /* Integer register as source. */ 137 AARCH64_OPND_Rm, /* Integer register as source. */ 138 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 139 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 140 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 141 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 142 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 143 144 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 145 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 146 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ 147 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 148 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 149 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 150 151 AARCH64_OPND_Fd, /* Floating-point Fd. */ 152 AARCH64_OPND_Fn, /* Floating-point Fn. */ 153 AARCH64_OPND_Fm, /* Floating-point Fm. */ 154 AARCH64_OPND_Fa, /* Floating-point Fa. */ 155 AARCH64_OPND_Ft, /* Floating-point Ft. */ 156 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 157 158 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 159 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 160 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 161 162 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 163 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 164 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 165 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 166 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 167 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 168 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 169 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 170 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 171 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 172 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 173 structure to all lanes. */ 174 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 175 176 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ 177 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ 178 179 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 180 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 181 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 182 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 183 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 184 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 185 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 186 (no encoding). */ 187 AARCH64_OPND_IMM0, /* Immediate for #0. */ 188 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 189 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 190 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 191 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 192 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 193 AARCH64_OPND_IMM, /* Immediate. */ 194 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 195 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 196 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 197 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 198 AARCH64_OPND_BIT_NUM, /* Immediate. */ 199 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 200 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 201 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ 202 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 203 each condition flag. */ 204 205 AARCH64_OPND_LIMM, /* Logical Immediate. */ 206 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 207 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 208 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 209 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 210 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ 211 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ 212 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ 213 214 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 215 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 216 217 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 218 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 219 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 220 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 221 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 222 223 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 224 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 225 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 226 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 227 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 228 negative or unaligned and there is 229 no writeback allowed. This operand code 230 is only used to support the programmer- 231 friendly feature of using LDR/STR as the 232 the mnemonic name for LDUR/STUR instructions 233 wherever there is no ambiguity. */ 234 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ 235 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 236 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 237 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 238 239 AARCH64_OPND_SYSREG, /* System register operand. */ 240 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 241 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 242 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 243 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 244 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 245 AARCH64_OPND_BARRIER, /* Barrier operand. */ 246 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 247 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 248 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 249 250 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ 251 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ 252 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ 253 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ 254 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ 255 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ 256 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ 257 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ 258 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ 259 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ 260 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ 261 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ 262 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ 263 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ 264 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ 265 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ 266 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ 267 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ 268 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ 269 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ 270 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ 271 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ 272 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ 273 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 274 Bit 14 controls S/U choice. */ 275 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 276 Bit 22 controls S/U choice. */ 277 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 278 Bit 14 controls S/U choice. */ 279 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 280 Bit 22 controls S/U choice. */ 281 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 282 Bit 14 controls S/U choice. */ 283 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 284 Bit 22 controls S/U choice. */ 285 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 286 Bit 14 controls S/U choice. */ 287 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 288 Bit 22 controls S/U choice. */ 289 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ 290 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ 291 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ 292 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ 293 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ 294 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ 295 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ 296 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ 297 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ 298 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ 299 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ 300 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ 301 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ 302 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ 303 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ 304 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ 305 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ 306 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ 307 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ 308 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ 309 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ 310 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ 311 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ 312 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ 313 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ 314 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ 315 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ 316 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ 317 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ 318 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ 319 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ 320 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ 321 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ 322 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ 323 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ 324 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ 325 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ 326 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ 327 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ 328 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ 329 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ 330 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ 331 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ 332 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ 333 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ 334 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ 335 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ 336 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ 337 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ 338 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ 339 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ 340 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ 341 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ 342 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ 343 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ 344 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ 345 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ 346 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ 347 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ 348 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ 349 }; 350 351 /* Qualifier constrains an operand. It either specifies a variant of an 352 operand type or limits values available to an operand type. 353 354 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 355 356 enum aarch64_opnd_qualifier 357 { 358 /* Indicating no further qualification on an operand. */ 359 AARCH64_OPND_QLF_NIL, 360 361 /* Qualifying an operand which is a general purpose (integer) register; 362 indicating the operand data size or a specific register. */ 363 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 364 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 365 AARCH64_OPND_QLF_WSP, /* WSP. */ 366 AARCH64_OPND_QLF_SP, /* SP. */ 367 368 /* Qualifying an operand which is a floating-point register, a SIMD 369 vector element or a SIMD vector element list; indicating operand data 370 size or the size of each SIMD vector element in the case of a SIMD 371 vector element list. 372 These qualifiers are also used to qualify an address operand to 373 indicate the size of data element a load/store instruction is 374 accessing. 375 They are also used for the immediate shift operand in e.g. SSHR. Such 376 a use is only for the ease of operand encoding/decoding and qualifier 377 sequence matching; such a use should not be applied widely; use the value 378 constraint qualifiers for immediate operands wherever possible. */ 379 AARCH64_OPND_QLF_S_B, 380 AARCH64_OPND_QLF_S_H, 381 AARCH64_OPND_QLF_S_S, 382 AARCH64_OPND_QLF_S_D, 383 AARCH64_OPND_QLF_S_Q, 384 385 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 386 register list; indicating register shape. 387 They are also used for the immediate shift operand in e.g. SSHR. Such 388 a use is only for the ease of operand encoding/decoding and qualifier 389 sequence matching; such a use should not be applied widely; use the value 390 constraint qualifiers for immediate operands wherever possible. */ 391 AARCH64_OPND_QLF_V_8B, 392 AARCH64_OPND_QLF_V_16B, 393 AARCH64_OPND_QLF_V_2H, 394 AARCH64_OPND_QLF_V_4H, 395 AARCH64_OPND_QLF_V_8H, 396 AARCH64_OPND_QLF_V_2S, 397 AARCH64_OPND_QLF_V_4S, 398 AARCH64_OPND_QLF_V_1D, 399 AARCH64_OPND_QLF_V_2D, 400 AARCH64_OPND_QLF_V_1Q, 401 402 AARCH64_OPND_QLF_P_Z, 403 AARCH64_OPND_QLF_P_M, 404 405 /* Constraint on value. */ 406 AARCH64_OPND_QLF_CR, /* CRn, CRm. */ 407 AARCH64_OPND_QLF_imm_0_7, 408 AARCH64_OPND_QLF_imm_0_15, 409 AARCH64_OPND_QLF_imm_0_31, 410 AARCH64_OPND_QLF_imm_0_63, 411 AARCH64_OPND_QLF_imm_1_32, 412 AARCH64_OPND_QLF_imm_1_64, 413 414 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 415 or shift-ones. */ 416 AARCH64_OPND_QLF_LSL, 417 AARCH64_OPND_QLF_MSL, 418 419 /* Special qualifier helping retrieve qualifier information during the 420 decoding time (currently not in use). */ 421 AARCH64_OPND_QLF_RETRIEVE, 422 }; 423 424 /* Instruction class. */ 426 427 enum aarch64_insn_class 428 { 429 addsub_carry, 430 addsub_ext, 431 addsub_imm, 432 addsub_shift, 433 asimdall, 434 asimddiff, 435 asimdelem, 436 asimdext, 437 asimdimm, 438 asimdins, 439 asimdmisc, 440 asimdperm, 441 asimdsame, 442 asimdshf, 443 asimdtbl, 444 asisddiff, 445 asisdelem, 446 asisdlse, 447 asisdlsep, 448 asisdlso, 449 asisdlsop, 450 asisdmisc, 451 asisdone, 452 asisdpair, 453 asisdsame, 454 asisdshf, 455 bitfield, 456 branch_imm, 457 branch_reg, 458 compbranch, 459 condbranch, 460 condcmp_imm, 461 condcmp_reg, 462 condsel, 463 cryptoaes, 464 cryptosha2, 465 cryptosha3, 466 dp_1src, 467 dp_2src, 468 dp_3src, 469 exception, 470 extract, 471 float2fix, 472 float2int, 473 floatccmp, 474 floatcmp, 475 floatdp1, 476 floatdp2, 477 floatdp3, 478 floatimm, 479 floatsel, 480 ldst_immpost, 481 ldst_immpre, 482 ldst_imm9, /* immpost or immpre */ 483 ldst_imm10, /* LDRAA/LDRAB */ 484 ldst_pos, 485 ldst_regoff, 486 ldst_unpriv, 487 ldst_unscaled, 488 ldstexcl, 489 ldstnapair_offs, 490 ldstpair_off, 491 ldstpair_indexed, 492 loadlit, 493 log_imm, 494 log_shift, 495 lse_atomic, 496 movewide, 497 pcreladdr, 498 ic_system, 499 sve_cpy, 500 sve_index, 501 sve_limm, 502 sve_misc, 503 sve_movprfx, 504 sve_pred_zm, 505 sve_shift_pred, 506 sve_shift_unpred, 507 sve_size_bhs, 508 sve_size_bhsd, 509 sve_size_hsd, 510 sve_size_sd, 511 testbranch, 512 }; 513 514 /* Opcode enumerators. */ 515 516 enum aarch64_op 517 { 518 OP_NIL, 519 OP_STRB_POS, 520 OP_LDRB_POS, 521 OP_LDRSB_POS, 522 OP_STRH_POS, 523 OP_LDRH_POS, 524 OP_LDRSH_POS, 525 OP_STR_POS, 526 OP_LDR_POS, 527 OP_STRF_POS, 528 OP_LDRF_POS, 529 OP_LDRSW_POS, 530 OP_PRFM_POS, 531 532 OP_STURB, 533 OP_LDURB, 534 OP_LDURSB, 535 OP_STURH, 536 OP_LDURH, 537 OP_LDURSH, 538 OP_STUR, 539 OP_LDUR, 540 OP_STURV, 541 OP_LDURV, 542 OP_LDURSW, 543 OP_PRFUM, 544 545 OP_LDR_LIT, 546 OP_LDRV_LIT, 547 OP_LDRSW_LIT, 548 OP_PRFM_LIT, 549 550 OP_ADD, 551 OP_B, 552 OP_BL, 553 554 OP_MOVN, 555 OP_MOVZ, 556 OP_MOVK, 557 558 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 559 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 560 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 561 562 OP_MOV_V, /* MOV alias for moving vector register. */ 563 564 OP_ASR_IMM, 565 OP_LSR_IMM, 566 OP_LSL_IMM, 567 568 OP_BIC, 569 570 OP_UBFX, 571 OP_BFXIL, 572 OP_SBFX, 573 OP_SBFIZ, 574 OP_BFI, 575 OP_BFC, /* ARMv8.2. */ 576 OP_UBFIZ, 577 OP_UXTB, 578 OP_UXTH, 579 OP_UXTW, 580 581 OP_CINC, 582 OP_CINV, 583 OP_CNEG, 584 OP_CSET, 585 OP_CSETM, 586 587 OP_FCVT, 588 OP_FCVTN, 589 OP_FCVTN2, 590 OP_FCVTL, 591 OP_FCVTL2, 592 OP_FCVTXN_S, /* Scalar version. */ 593 594 OP_ROR_IMM, 595 596 OP_SXTL, 597 OP_SXTL2, 598 OP_UXTL, 599 OP_UXTL2, 600 601 OP_MOV_P_P, 602 OP_MOV_Z_P_Z, 603 OP_MOV_Z_V, 604 OP_MOV_Z_Z, 605 OP_MOV_Z_Zi, 606 OP_MOVM_P_P_P, 607 OP_MOVS_P_P, 608 OP_MOVZS_P_P_P, 609 OP_MOVZ_P_P_P, 610 OP_NOTS_P_P_P_Z, 611 OP_NOT_P_P_P_Z, 612 613 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ 614 615 OP_TOTAL_NUM, /* Pseudo. */ 616 }; 617 618 /* Maximum number of operands an instruction can have. */ 619 #define AARCH64_MAX_OPND_NUM 6 620 /* Maximum number of qualifier sequences an instruction can have. */ 621 #define AARCH64_MAX_QLF_SEQ_NUM 10 622 /* Operand qualifier typedef; optimized for the size. */ 623 typedef unsigned char aarch64_opnd_qualifier_t; 624 /* Operand qualifier sequence typedef. */ 625 typedef aarch64_opnd_qualifier_t \ 626 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 627 628 /* FIXME: improve the efficiency. */ 629 static inline bfd_boolean 630 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 631 { 632 int i; 633 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 634 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 635 return FALSE; 636 return TRUE; 637 } 638 639 /* This structure holds information for a particular opcode. */ 640 641 struct aarch64_opcode 642 { 643 /* The name of the mnemonic. */ 644 const char *name; 645 646 /* The opcode itself. Those bits which will be filled in with 647 operands are zeroes. */ 648 aarch64_insn opcode; 649 650 /* The opcode mask. This is used by the disassembler. This is a 651 mask containing ones indicating those bits which must match the 652 opcode field, and zeroes indicating those bits which need not 653 match (and are presumably filled in by operands). */ 654 aarch64_insn mask; 655 656 /* Instruction class. */ 657 enum aarch64_insn_class iclass; 658 659 /* Enumerator identifier. */ 660 enum aarch64_op op; 661 662 /* Which architecture variant provides this instruction. */ 663 const aarch64_feature_set *avariant; 664 665 /* An array of operand codes. Each code is an index into the 666 operand table. They appear in the order which the operands must 667 appear in assembly code, and are terminated by a zero. */ 668 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 669 670 /* A list of operand qualifier code sequence. Each operand qualifier 671 code qualifies the corresponding operand code. Each operand 672 qualifier sequence specifies a valid opcode variant and related 673 constraint on operands. */ 674 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 675 676 /* Flags providing information about this instruction */ 677 uint32_t flags; 678 679 /* If nonzero, this operand and operand 0 are both registers and 680 are required to have the same register number. */ 681 unsigned char tied_operand; 682 683 /* If non-NULL, a function to verify that a given instruction is valid. */ 684 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); 685 }; 686 687 typedef struct aarch64_opcode aarch64_opcode; 688 689 /* Table describing all the AArch64 opcodes. */ 690 extern aarch64_opcode aarch64_opcode_table[]; 691 692 /* Opcode flags. */ 693 #define F_ALIAS (1 << 0) 694 #define F_HAS_ALIAS (1 << 1) 695 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 696 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 697 #define F_P1 (1 << 2) 698 #define F_P2 (2 << 2) 699 #define F_P3 (3 << 2) 700 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 701 #define F_COND (1 << 4) 702 /* Instruction has the field of 'sf'. */ 703 #define F_SF (1 << 5) 704 /* Instruction has the field of 'size:Q'. */ 705 #define F_SIZEQ (1 << 6) 706 /* Floating-point instruction has the field of 'type'. */ 707 #define F_FPTYPE (1 << 7) 708 /* AdvSIMD scalar instruction has the field of 'size'. */ 709 #define F_SSIZE (1 << 8) 710 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 711 #define F_T (1 << 9) 712 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 713 #define F_GPRSIZE_IN_Q (1 << 10) 714 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 715 #define F_LDS_SIZE (1 << 11) 716 /* Optional operand; assume maximum of 1 operand can be optional. */ 717 #define F_OPD0_OPT (1 << 12) 718 #define F_OPD1_OPT (2 << 12) 719 #define F_OPD2_OPT (3 << 12) 720 #define F_OPD3_OPT (4 << 12) 721 #define F_OPD4_OPT (5 << 12) 722 /* Default value for the optional operand when omitted from the assembly. */ 723 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 724 /* Instruction that is an alias of another instruction needs to be 725 encoded/decoded by converting it to/from the real form, followed by 726 the encoding/decoding according to the rules of the real opcode. 727 This compares to the direct coding using the alias's information. 728 N.B. this flag requires F_ALIAS to be used together. */ 729 #define F_CONV (1 << 20) 730 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 731 friendly pseudo instruction available only in the assembly code (thus will 732 not show up in the disassembly). */ 733 #define F_PSEUDO (1 << 21) 734 /* Instruction has miscellaneous encoding/decoding rules. */ 735 #define F_MISC (1 << 22) 736 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 737 #define F_N (1 << 23) 738 /* Opcode dependent field. */ 739 #define F_OD(X) (((X) & 0x7) << 24) 740 /* Instruction has the field of 'sz'. */ 741 #define F_LSE_SZ (1 << 27) 742 /* Require an exact qualifier match, even for NIL qualifiers. */ 743 #define F_STRICT (1ULL << 28) 744 /* Next bit is 29. */ 745 746 static inline bfd_boolean 747 alias_opcode_p (const aarch64_opcode *opcode) 748 { 749 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 750 } 751 752 static inline bfd_boolean 753 opcode_has_alias (const aarch64_opcode *opcode) 754 { 755 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 756 } 757 758 /* Priority for disassembling preference. */ 759 static inline int 760 opcode_priority (const aarch64_opcode *opcode) 761 { 762 return (opcode->flags >> 2) & 0x3; 763 } 764 765 static inline bfd_boolean 766 pseudo_opcode_p (const aarch64_opcode *opcode) 767 { 768 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 769 } 770 771 static inline bfd_boolean 772 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 773 { 774 return (((opcode->flags >> 12) & 0x7) == idx + 1) 775 ? TRUE : FALSE; 776 } 777 778 static inline aarch64_insn 779 get_optional_operand_default_value (const aarch64_opcode *opcode) 780 { 781 return (opcode->flags >> 15) & 0x1f; 782 } 783 784 static inline unsigned int 785 get_opcode_dependent_value (const aarch64_opcode *opcode) 786 { 787 return (opcode->flags >> 24) & 0x7; 788 } 789 790 static inline bfd_boolean 791 opcode_has_special_coder (const aarch64_opcode *opcode) 792 { 793 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 794 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 795 : FALSE; 796 } 797 798 struct aarch64_name_value_pair 800 { 801 const char * name; 802 aarch64_insn value; 803 }; 804 805 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 806 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 807 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 808 extern const struct aarch64_name_value_pair aarch64_hint_options []; 809 810 typedef struct 811 { 812 const char * name; 813 aarch64_insn value; 814 uint32_t flags; 815 } aarch64_sys_reg; 816 817 extern const aarch64_sys_reg aarch64_sys_regs []; 818 extern const aarch64_sys_reg aarch64_pstatefields []; 819 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 820 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, 821 const aarch64_sys_reg *); 822 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, 823 const aarch64_sys_reg *); 824 825 typedef struct 826 { 827 const char *name; 828 uint32_t value; 829 uint32_t flags ; 830 } aarch64_sys_ins_reg; 831 832 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 833 extern bfd_boolean 834 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 835 const aarch64_sys_ins_reg *); 836 837 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 838 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 839 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 840 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 841 842 /* Shift/extending operator kinds. 843 N.B. order is important; keep aarch64_operand_modifiers synced. */ 844 enum aarch64_modifier_kind 845 { 846 AARCH64_MOD_NONE, 847 AARCH64_MOD_MSL, 848 AARCH64_MOD_ROR, 849 AARCH64_MOD_ASR, 850 AARCH64_MOD_LSR, 851 AARCH64_MOD_LSL, 852 AARCH64_MOD_UXTB, 853 AARCH64_MOD_UXTH, 854 AARCH64_MOD_UXTW, 855 AARCH64_MOD_UXTX, 856 AARCH64_MOD_SXTB, 857 AARCH64_MOD_SXTH, 858 AARCH64_MOD_SXTW, 859 AARCH64_MOD_SXTX, 860 AARCH64_MOD_MUL, 861 AARCH64_MOD_MUL_VL, 862 }; 863 864 bfd_boolean 865 aarch64_extend_operator_p (enum aarch64_modifier_kind); 866 867 enum aarch64_modifier_kind 868 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 869 /* Condition. */ 870 871 typedef struct 872 { 873 /* A list of names with the first one as the disassembly preference; 874 terminated by NULL if fewer than 3. */ 875 const char *names[4]; 876 aarch64_insn value; 877 } aarch64_cond; 878 879 extern const aarch64_cond aarch64_conds[16]; 880 881 const aarch64_cond* get_cond_from_value (aarch64_insn value); 882 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 883 884 /* Structure representing an operand. */ 886 887 struct aarch64_opnd_info 888 { 889 enum aarch64_opnd type; 890 aarch64_opnd_qualifier_t qualifier; 891 int idx; 892 893 union 894 { 895 struct 896 { 897 unsigned regno; 898 } reg; 899 struct 900 { 901 unsigned int regno; 902 int64_t index; 903 } reglane; 904 /* e.g. LVn. */ 905 struct 906 { 907 unsigned first_regno : 5; 908 unsigned num_regs : 3; 909 /* 1 if it is a list of reg element. */ 910 unsigned has_index : 1; 911 /* Lane index; valid only when has_index is 1. */ 912 int64_t index; 913 } reglist; 914 /* e.g. immediate or pc relative address offset. */ 915 struct 916 { 917 int64_t value; 918 unsigned is_fp : 1; 919 } imm; 920 /* e.g. address in STR (register offset). */ 921 struct 922 { 923 unsigned base_regno; 924 struct 925 { 926 union 927 { 928 int imm; 929 unsigned regno; 930 }; 931 unsigned is_reg; 932 } offset; 933 unsigned pcrel : 1; /* PC-relative. */ 934 unsigned writeback : 1; 935 unsigned preind : 1; /* Pre-indexed. */ 936 unsigned postind : 1; /* Post-indexed. */ 937 } addr; 938 const aarch64_cond *cond; 939 /* The encoding of the system register. */ 940 aarch64_insn sysreg; 941 /* The encoding of the PSTATE field. */ 942 aarch64_insn pstatefield; 943 const aarch64_sys_ins_reg *sysins_op; 944 const struct aarch64_name_value_pair *barrier; 945 const struct aarch64_name_value_pair *hint_option; 946 const struct aarch64_name_value_pair *prfop; 947 }; 948 949 /* Operand shifter; in use when the operand is a register offset address, 950 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 951 struct 952 { 953 enum aarch64_modifier_kind kind; 954 unsigned operator_present: 1; /* Only valid during encoding. */ 955 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 956 unsigned amount_present: 1; 957 int64_t amount; 958 } shifter; 959 960 unsigned skip:1; /* Operand is not completed if there is a fixup needed 961 to be done on it. In some (but not all) of these 962 cases, we need to tell libopcodes to skip the 963 constraint checking and the encoding for this 964 operand, so that the libopcodes can pick up the 965 right opcode before the operand is fixed-up. This 966 flag should only be used during the 967 assembling/encoding. */ 968 unsigned present:1; /* Whether this operand is present in the assembly 969 line; not used during the disassembly. */ 970 }; 971 972 typedef struct aarch64_opnd_info aarch64_opnd_info; 973 974 /* Structure representing an instruction. 975 976 It is used during both the assembling and disassembling. The assembler 977 fills an aarch64_inst after a successful parsing and then passes it to the 978 encoding routine to do the encoding. During the disassembling, the 979 disassembler calls the decoding routine to decode a binary instruction; on a 980 successful return, such a structure will be filled with information of the 981 instruction; then the disassembler uses the information to print out the 982 instruction. */ 983 984 struct aarch64_inst 985 { 986 /* The value of the binary instruction. */ 987 aarch64_insn value; 988 989 /* Corresponding opcode entry. */ 990 const aarch64_opcode *opcode; 991 992 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 993 const aarch64_cond *cond; 994 995 /* Operands information. */ 996 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 997 }; 998 999 typedef struct aarch64_inst aarch64_inst; 1000 1001 /* Diagnosis related declaration and interface. */ 1003 1004 /* Operand error kind enumerators. 1005 1006 AARCH64_OPDE_RECOVERABLE 1007 Less severe error found during the parsing, very possibly because that 1008 GAS has picked up a wrong instruction template for the parsing. 1009 1010 AARCH64_OPDE_SYNTAX_ERROR 1011 General syntax error; it can be either a user error, or simply because 1012 that GAS is trying a wrong instruction template. 1013 1014 AARCH64_OPDE_FATAL_SYNTAX_ERROR 1015 Definitely a user syntax error. 1016 1017 AARCH64_OPDE_INVALID_VARIANT 1018 No syntax error, but the operands are not a valid combination, e.g. 1019 FMOV D0,S0 1020 1021 AARCH64_OPDE_UNTIED_OPERAND 1022 The asm failed to use the same register for a destination operand 1023 and a tied source operand. 1024 1025 AARCH64_OPDE_OUT_OF_RANGE 1026 Error about some immediate value out of a valid range. 1027 1028 AARCH64_OPDE_UNALIGNED 1029 Error about some immediate value not properly aligned (i.e. not being a 1030 multiple times of a certain value). 1031 1032 AARCH64_OPDE_REG_LIST 1033 Error about the register list operand having unexpected number of 1034 registers. 1035 1036 AARCH64_OPDE_OTHER_ERROR 1037 Error of the highest severity and used for any severe issue that does not 1038 fall into any of the above categories. 1039 1040 The enumerators are only interesting to GAS. They are declared here (in 1041 libopcodes) because that some errors are detected (and then notified to GAS) 1042 by libopcodes (rather than by GAS solely). 1043 1044 The first three errors are only deteced by GAS while the 1045 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 1046 only libopcodes has the information about the valid variants of each 1047 instruction. 1048 1049 The enumerators have an increasing severity. This is helpful when there are 1050 multiple instruction templates available for a given mnemonic name (e.g. 1051 FMOV); this mechanism will help choose the most suitable template from which 1052 the generated diagnostics can most closely describe the issues, if any. */ 1053 1054 enum aarch64_operand_error_kind 1055 { 1056 AARCH64_OPDE_NIL, 1057 AARCH64_OPDE_RECOVERABLE, 1058 AARCH64_OPDE_SYNTAX_ERROR, 1059 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 1060 AARCH64_OPDE_INVALID_VARIANT, 1061 AARCH64_OPDE_UNTIED_OPERAND, 1062 AARCH64_OPDE_OUT_OF_RANGE, 1063 AARCH64_OPDE_UNALIGNED, 1064 AARCH64_OPDE_REG_LIST, 1065 AARCH64_OPDE_OTHER_ERROR 1066 }; 1067 1068 /* N.B. GAS assumes that this structure work well with shallow copy. */ 1069 struct aarch64_operand_error 1070 { 1071 enum aarch64_operand_error_kind kind; 1072 int index; 1073 const char *error; 1074 int data[3]; /* Some data for extra information. */ 1075 }; 1076 1077 typedef struct aarch64_operand_error aarch64_operand_error; 1078 1079 /* Encoding entrypoint. */ 1080 1081 extern int 1082 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 1083 aarch64_insn *, aarch64_opnd_qualifier_t *, 1084 aarch64_operand_error *); 1085 1086 extern const aarch64_opcode * 1087 aarch64_replace_opcode (struct aarch64_inst *, 1088 const aarch64_opcode *); 1089 1090 /* Given the opcode enumerator OP, return the pointer to the corresponding 1091 opcode entry. */ 1092 1093 extern const aarch64_opcode * 1094 aarch64_get_opcode (enum aarch64_op); 1095 1096 /* Generate the string representation of an operand. */ 1097 extern void 1098 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 1099 const aarch64_opnd_info *, int, int *, bfd_vma *); 1100 1101 /* Miscellaneous interface. */ 1102 1103 extern int 1104 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 1105 1106 extern aarch64_opnd_qualifier_t 1107 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 1108 const aarch64_opnd_qualifier_t, int); 1109 1110 extern int 1111 aarch64_num_of_operands (const aarch64_opcode *); 1112 1113 extern int 1114 aarch64_stack_pointer_p (const aarch64_opnd_info *); 1115 1116 extern int 1117 aarch64_zero_register_p (const aarch64_opnd_info *); 1118 1119 extern int 1120 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); 1121 1122 /* Given an operand qualifier, return the expected data element size 1123 of a qualified operand. */ 1124 extern unsigned char 1125 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 1126 1127 extern enum aarch64_operand_class 1128 aarch64_get_operand_class (enum aarch64_opnd); 1129 1130 extern const char * 1131 aarch64_get_operand_name (enum aarch64_opnd); 1132 1133 extern const char * 1134 aarch64_get_operand_desc (enum aarch64_opnd); 1135 1136 extern bfd_boolean 1137 aarch64_sve_dupm_mov_immediate_p (uint64_t, int); 1138 1139 #ifdef DEBUG_AARCH64 1140 extern int debug_dump; 1141 1142 extern void 1143 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 1144 1145 #define DEBUG_TRACE(M, ...) \ 1146 { \ 1147 if (debug_dump) \ 1148 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1149 } 1150 1151 #define DEBUG_TRACE_IF(C, M, ...) \ 1152 { \ 1153 if (debug_dump && (C)) \ 1154 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1155 } 1156 #else /* !DEBUG_AARCH64 */ 1157 #define DEBUG_TRACE(M, ...) ; 1158 #define DEBUG_TRACE_IF(C, M, ...) ; 1159 #endif /* DEBUG_AARCH64 */ 1160 1161 extern const char *const aarch64_sve_pattern_array[32]; 1162 extern const char *const aarch64_sve_prfop_array[16]; 1163 1164 #ifdef __cplusplus 1165 } 1166 #endif 1167 1168 #endif /* OPCODE_AARCH64_H */ 1169
Indexes created Sat Mar 28 00:23:22 UTC 2026