aarch64.h revision 1.1.1.8
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2020 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* The offset for pc-relative addressing is currently defined to be 0. */ 35 #define AARCH64_PCREL_OFFSET 0 36 37 typedef uint32_t aarch64_insn; 38 39 /* The following bitmasks control CPU features. */ 40 #define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */ 41 #define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */ 42 #define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */ 43 #define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */ 44 #define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */ 45 #define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */ 46 #define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */ 47 #define AARCH64_FEATURE_SVE2_AES (1ULL << 7) 48 #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8) 49 #define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9) 50 #define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) 51 #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ 52 #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ 53 #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ 54 #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ 55 #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ 56 #define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */ 57 #define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */ 58 #define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */ 59 #define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */ 60 #define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */ 61 #define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */ 62 #define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */ 63 #define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */ 64 #define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */ 65 #define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */ 66 #define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */ 67 #define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */ 68 #define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */ 69 #define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */ 70 #define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */ 71 #define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */ 72 #define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */ 73 #define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */ 74 #define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */ 75 #define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */ 76 #define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */ 77 #define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */ 78 #define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */ 79 #define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */ 80 #define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */ 81 #define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */ 82 #define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */ 83 #define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */ 84 #define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */ 85 #define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */ 86 #define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */ 87 #define AARCH64_FEATURE_F32MM (1ULL << 53) 88 #define AARCH64_FEATURE_F64MM (1ULL << 54) 89 90 /* Crypto instructions are the combination of AES and SHA2. */ 91 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) 92 93 /* Architectures are the sum of the base and extensions. */ 94 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 95 AARCH64_FEATURE_V8_A \ 96 | AARCH64_FEATURE_FP \ 97 | AARCH64_FEATURE_SIMD) 98 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ 99 AARCH64_FEATURE_CRC \ 100 | AARCH64_FEATURE_V8_1 \ 101 | AARCH64_FEATURE_LSE \ 102 | AARCH64_FEATURE_PAN \ 103 | AARCH64_FEATURE_LOR \ 104 | AARCH64_FEATURE_RDMA) 105 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ 106 AARCH64_FEATURE_V8_2 \ 107 | AARCH64_FEATURE_RAS) 108 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ 109 AARCH64_FEATURE_V8_3 \ 110 | AARCH64_FEATURE_RCPC \ 111 | AARCH64_FEATURE_COMPNUM) 112 #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ 113 AARCH64_FEATURE_V8_4 \ 114 | AARCH64_FEATURE_DOTPROD \ 115 | AARCH64_FEATURE_F16_FML) 116 #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ 117 AARCH64_FEATURE_V8_5 \ 118 | AARCH64_FEATURE_FLAGMANIP \ 119 | AARCH64_FEATURE_FRINTTS \ 120 | AARCH64_FEATURE_SB \ 121 | AARCH64_FEATURE_PREDRES \ 122 | AARCH64_FEATURE_CVADP \ 123 | AARCH64_FEATURE_BTI \ 124 | AARCH64_FEATURE_SCXTNUM \ 125 | AARCH64_FEATURE_ID_PFR2 \ 126 | AARCH64_FEATURE_SSBS) 127 #define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ 128 AARCH64_FEATURE_V8_6 \ 129 | AARCH64_FEATURE_BFLOAT16 \ 130 | AARCH64_FEATURE_I8MM) 131 #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ 132 AARCH64_FEATURE_V8_R) \ 133 & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) 134 135 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 136 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 137 138 /* CPU-specific features. */ 139 typedef unsigned long long aarch64_feature_set; 140 141 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 142 ((~(CPU) & (FEAT)) == 0) 143 144 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 145 (((CPU) & (FEAT)) != 0) 146 147 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 148 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 149 150 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 151 do \ 152 { \ 153 (TARG) = (F1) | (F2); \ 154 } \ 155 while (0) 156 157 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 158 do \ 159 { \ 160 (TARG) = (F1) &~ (F2); \ 161 } \ 162 while (0) 163 164 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 165 166 enum aarch64_operand_class 167 { 168 AARCH64_OPND_CLASS_NIL, 169 AARCH64_OPND_CLASS_INT_REG, 170 AARCH64_OPND_CLASS_MODIFIED_REG, 171 AARCH64_OPND_CLASS_FP_REG, 172 AARCH64_OPND_CLASS_SIMD_REG, 173 AARCH64_OPND_CLASS_SIMD_ELEMENT, 174 AARCH64_OPND_CLASS_SISD_REG, 175 AARCH64_OPND_CLASS_SIMD_REGLIST, 176 AARCH64_OPND_CLASS_SVE_REG, 177 AARCH64_OPND_CLASS_PRED_REG, 178 AARCH64_OPND_CLASS_ADDRESS, 179 AARCH64_OPND_CLASS_IMMEDIATE, 180 AARCH64_OPND_CLASS_SYSTEM, 181 AARCH64_OPND_CLASS_COND, 182 }; 183 184 /* Operand code that helps both parsing and coding. 185 Keep AARCH64_OPERANDS synced. */ 186 187 enum aarch64_opnd 188 { 189 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 190 191 AARCH64_OPND_Rd, /* Integer register as destination. */ 192 AARCH64_OPND_Rn, /* Integer register as source. */ 193 AARCH64_OPND_Rm, /* Integer register as source. */ 194 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 195 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 196 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ 197 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 198 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 199 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 200 201 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 202 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 203 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ 204 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 205 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 206 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 207 208 AARCH64_OPND_Fd, /* Floating-point Fd. */ 209 AARCH64_OPND_Fn, /* Floating-point Fn. */ 210 AARCH64_OPND_Fm, /* Floating-point Fm. */ 211 AARCH64_OPND_Fa, /* Floating-point Fa. */ 212 AARCH64_OPND_Ft, /* Floating-point Ft. */ 213 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 214 215 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 216 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 217 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 218 219 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ 220 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 221 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 222 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 223 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 224 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 225 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 226 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 227 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 228 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when 229 qualifier is S_H. */ 230 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 231 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 232 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 233 structure to all lanes. */ 234 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 235 236 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ 237 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ 238 239 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 240 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ 241 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 242 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 243 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 244 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 245 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 246 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 247 (no encoding). */ 248 AARCH64_OPND_IMM0, /* Immediate for #0. */ 249 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 250 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 251 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 252 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 253 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 254 AARCH64_OPND_IMM, /* Immediate. */ 255 AARCH64_OPND_IMM_2, /* Immediate. */ 256 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 257 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 258 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 259 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ 260 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 261 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ 262 AARCH64_OPND_BIT_NUM, /* Immediate. */ 263 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 264 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ 265 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 266 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ 267 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 268 each condition flag. */ 269 270 AARCH64_OPND_LIMM, /* Logical Immediate. */ 271 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 272 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 273 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 274 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 275 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ 276 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ 277 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ 278 279 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 280 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 281 282 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 283 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 284 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 285 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 286 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 287 288 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 289 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 290 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 291 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 292 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 293 negative or unaligned and there is 294 no writeback allowed. This operand code 295 is only used to support the programmer- 296 friendly feature of using LDR/STR as the 297 the mnemonic name for LDUR/STUR instructions 298 wherever there is no ambiguity. */ 299 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ 300 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of 301 16) immediate. */ 302 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 303 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of 304 16) immediate. */ 305 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 306 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ 307 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 308 309 AARCH64_OPND_SYSREG, /* System register operand. */ 310 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 311 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 312 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 313 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 314 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 315 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ 316 AARCH64_OPND_BARRIER, /* Barrier operand. */ 317 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 318 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 319 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 320 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ 321 322 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ 323 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ 324 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ 325 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ 326 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ 327 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ 328 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ 329 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ 330 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ 331 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ 332 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ 333 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ 334 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ 335 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ 336 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ 337 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ 338 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ 339 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ 340 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ 341 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ 342 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ 343 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */ 344 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ 345 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ 346 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ 347 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ 348 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 349 Bit 14 controls S/U choice. */ 350 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 351 Bit 22 controls S/U choice. */ 352 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 353 Bit 14 controls S/U choice. */ 354 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 355 Bit 22 controls S/U choice. */ 356 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 357 Bit 14 controls S/U choice. */ 358 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 359 Bit 22 controls S/U choice. */ 360 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 361 Bit 14 controls S/U choice. */ 362 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 363 Bit 22 controls S/U choice. */ 364 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ 365 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ 366 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ 367 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ 368 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ 369 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ 370 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ 371 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ 372 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ 373 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ 374 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ 375 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ 376 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ 377 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ 378 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ 379 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */ 380 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ 381 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ 382 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ 383 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ 384 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ 385 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ 386 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ 387 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ 388 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ 389 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ 390 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ 391 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ 392 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ 393 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ 394 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ 395 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ 396 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ 397 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ 398 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */ 399 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ 400 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ 401 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ 402 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ 403 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ 404 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ 405 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ 406 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ 407 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ 408 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ 409 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ 410 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ 411 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ 412 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ 413 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ 414 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ 415 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ 416 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ 417 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ 418 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ 419 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ 420 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ 421 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ 422 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ 423 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ 424 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ 425 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ 426 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ 427 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ 428 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ 429 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ 430 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ 431 }; 432 433 /* Qualifier constrains an operand. It either specifies a variant of an 434 operand type or limits values available to an operand type. 435 436 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 437 438 enum aarch64_opnd_qualifier 439 { 440 /* Indicating no further qualification on an operand. */ 441 AARCH64_OPND_QLF_NIL, 442 443 /* Qualifying an operand which is a general purpose (integer) register; 444 indicating the operand data size or a specific register. */ 445 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 446 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 447 AARCH64_OPND_QLF_WSP, /* WSP. */ 448 AARCH64_OPND_QLF_SP, /* SP. */ 449 450 /* Qualifying an operand which is a floating-point register, a SIMD 451 vector element or a SIMD vector element list; indicating operand data 452 size or the size of each SIMD vector element in the case of a SIMD 453 vector element list. 454 These qualifiers are also used to qualify an address operand to 455 indicate the size of data element a load/store instruction is 456 accessing. 457 They are also used for the immediate shift operand in e.g. SSHR. Such 458 a use is only for the ease of operand encoding/decoding and qualifier 459 sequence matching; such a use should not be applied widely; use the value 460 constraint qualifiers for immediate operands wherever possible. */ 461 AARCH64_OPND_QLF_S_B, 462 AARCH64_OPND_QLF_S_H, 463 AARCH64_OPND_QLF_S_S, 464 AARCH64_OPND_QLF_S_D, 465 AARCH64_OPND_QLF_S_Q, 466 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte 467 or 2 x 2 byte are selected by the instruction. Other than that they have 468 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely 469 for syntactical reasons and is an exception from normal AArch64 470 disassembly scheme. */ 471 AARCH64_OPND_QLF_S_4B, 472 AARCH64_OPND_QLF_S_2H, 473 474 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 475 register list; indicating register shape. 476 They are also used for the immediate shift operand in e.g. SSHR. Such 477 a use is only for the ease of operand encoding/decoding and qualifier 478 sequence matching; such a use should not be applied widely; use the value 479 constraint qualifiers for immediate operands wherever possible. */ 480 AARCH64_OPND_QLF_V_4B, 481 AARCH64_OPND_QLF_V_8B, 482 AARCH64_OPND_QLF_V_16B, 483 AARCH64_OPND_QLF_V_2H, 484 AARCH64_OPND_QLF_V_4H, 485 AARCH64_OPND_QLF_V_8H, 486 AARCH64_OPND_QLF_V_2S, 487 AARCH64_OPND_QLF_V_4S, 488 AARCH64_OPND_QLF_V_1D, 489 AARCH64_OPND_QLF_V_2D, 490 AARCH64_OPND_QLF_V_1Q, 491 492 AARCH64_OPND_QLF_P_Z, 493 AARCH64_OPND_QLF_P_M, 494 495 /* Used in scaled signed immediate that are scaled by a Tag granule 496 like in stg, st2g, etc. */ 497 AARCH64_OPND_QLF_imm_tag, 498 499 /* Constraint on value. */ 500 AARCH64_OPND_QLF_CR, /* CRn, CRm. */ 501 AARCH64_OPND_QLF_imm_0_7, 502 AARCH64_OPND_QLF_imm_0_15, 503 AARCH64_OPND_QLF_imm_0_31, 504 AARCH64_OPND_QLF_imm_0_63, 505 AARCH64_OPND_QLF_imm_1_32, 506 AARCH64_OPND_QLF_imm_1_64, 507 508 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 509 or shift-ones. */ 510 AARCH64_OPND_QLF_LSL, 511 AARCH64_OPND_QLF_MSL, 512 513 /* Special qualifier helping retrieve qualifier information during the 514 decoding time (currently not in use). */ 515 AARCH64_OPND_QLF_RETRIEVE, 516 }; 517 518 /* Instruction class. */ 520 521 enum aarch64_insn_class 522 { 523 aarch64_misc, 524 addsub_carry, 525 addsub_ext, 526 addsub_imm, 527 addsub_shift, 528 asimdall, 529 asimddiff, 530 asimdelem, 531 asimdext, 532 asimdimm, 533 asimdins, 534 asimdmisc, 535 asimdperm, 536 asimdsame, 537 asimdshf, 538 asimdtbl, 539 asisddiff, 540 asisdelem, 541 asisdlse, 542 asisdlsep, 543 asisdlso, 544 asisdlsop, 545 asisdmisc, 546 asisdone, 547 asisdpair, 548 asisdsame, 549 asisdshf, 550 bitfield, 551 branch_imm, 552 branch_reg, 553 compbranch, 554 condbranch, 555 condcmp_imm, 556 condcmp_reg, 557 condsel, 558 cryptoaes, 559 cryptosha2, 560 cryptosha3, 561 dp_1src, 562 dp_2src, 563 dp_3src, 564 exception, 565 extract, 566 float2fix, 567 float2int, 568 floatccmp, 569 floatcmp, 570 floatdp1, 571 floatdp2, 572 floatdp3, 573 floatimm, 574 floatsel, 575 ldst_immpost, 576 ldst_immpre, 577 ldst_imm9, /* immpost or immpre */ 578 ldst_imm10, /* LDRAA/LDRAB */ 579 ldst_pos, 580 ldst_regoff, 581 ldst_unpriv, 582 ldst_unscaled, 583 ldstexcl, 584 ldstnapair_offs, 585 ldstpair_off, 586 ldstpair_indexed, 587 loadlit, 588 log_imm, 589 log_shift, 590 lse_atomic, 591 movewide, 592 pcreladdr, 593 ic_system, 594 sve_cpy, 595 sve_index, 596 sve_limm, 597 sve_misc, 598 sve_movprfx, 599 sve_pred_zm, 600 sve_shift_pred, 601 sve_shift_unpred, 602 sve_size_bhs, 603 sve_size_bhsd, 604 sve_size_hsd, 605 sve_size_hsd2, 606 sve_size_sd, 607 sve_size_bh, 608 sve_size_sd2, 609 sve_size_13, 610 sve_shift_tsz_hsd, 611 sve_shift_tsz_bhsd, 612 sve_size_tsz_bhs, 613 testbranch, 614 cryptosm3, 615 cryptosm4, 616 dotproduct, 617 bfloat16, 618 }; 619 620 /* Opcode enumerators. */ 621 622 enum aarch64_op 623 { 624 OP_NIL, 625 OP_STRB_POS, 626 OP_LDRB_POS, 627 OP_LDRSB_POS, 628 OP_STRH_POS, 629 OP_LDRH_POS, 630 OP_LDRSH_POS, 631 OP_STR_POS, 632 OP_LDR_POS, 633 OP_STRF_POS, 634 OP_LDRF_POS, 635 OP_LDRSW_POS, 636 OP_PRFM_POS, 637 638 OP_STURB, 639 OP_LDURB, 640 OP_LDURSB, 641 OP_STURH, 642 OP_LDURH, 643 OP_LDURSH, 644 OP_STUR, 645 OP_LDUR, 646 OP_STURV, 647 OP_LDURV, 648 OP_LDURSW, 649 OP_PRFUM, 650 651 OP_LDR_LIT, 652 OP_LDRV_LIT, 653 OP_LDRSW_LIT, 654 OP_PRFM_LIT, 655 656 OP_ADD, 657 OP_B, 658 OP_BL, 659 660 OP_MOVN, 661 OP_MOVZ, 662 OP_MOVK, 663 664 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 665 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 666 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 667 668 OP_MOV_V, /* MOV alias for moving vector register. */ 669 670 OP_ASR_IMM, 671 OP_LSR_IMM, 672 OP_LSL_IMM, 673 674 OP_BIC, 675 676 OP_UBFX, 677 OP_BFXIL, 678 OP_SBFX, 679 OP_SBFIZ, 680 OP_BFI, 681 OP_BFC, /* ARMv8.2. */ 682 OP_UBFIZ, 683 OP_UXTB, 684 OP_UXTH, 685 OP_UXTW, 686 687 OP_CINC, 688 OP_CINV, 689 OP_CNEG, 690 OP_CSET, 691 OP_CSETM, 692 693 OP_FCVT, 694 OP_FCVTN, 695 OP_FCVTN2, 696 OP_FCVTL, 697 OP_FCVTL2, 698 OP_FCVTXN_S, /* Scalar version. */ 699 700 OP_ROR_IMM, 701 702 OP_SXTL, 703 OP_SXTL2, 704 OP_UXTL, 705 OP_UXTL2, 706 707 OP_MOV_P_P, 708 OP_MOV_Z_P_Z, 709 OP_MOV_Z_V, 710 OP_MOV_Z_Z, 711 OP_MOV_Z_Zi, 712 OP_MOVM_P_P_P, 713 OP_MOVS_P_P, 714 OP_MOVZS_P_P_P, 715 OP_MOVZ_P_P_P, 716 OP_NOTS_P_P_P_Z, 717 OP_NOT_P_P_P_Z, 718 719 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ 720 721 OP_TOTAL_NUM, /* Pseudo. */ 722 }; 723 724 /* Error types. */ 725 enum err_type 726 { 727 ERR_OK, 728 ERR_UND, 729 ERR_UNP, 730 ERR_NYI, 731 ERR_VFI, 732 ERR_NR_ENTRIES 733 }; 734 735 /* Maximum number of operands an instruction can have. */ 736 #define AARCH64_MAX_OPND_NUM 6 737 /* Maximum number of qualifier sequences an instruction can have. */ 738 #define AARCH64_MAX_QLF_SEQ_NUM 10 739 /* Operand qualifier typedef; optimized for the size. */ 740 typedef unsigned char aarch64_opnd_qualifier_t; 741 /* Operand qualifier sequence typedef. */ 742 typedef aarch64_opnd_qualifier_t \ 743 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 744 745 /* FIXME: improve the efficiency. */ 746 static inline bfd_boolean 747 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 748 { 749 int i; 750 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 751 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 752 return FALSE; 753 return TRUE; 754 } 755 756 /* Forward declare error reporting type. */ 757 typedef struct aarch64_operand_error aarch64_operand_error; 758 /* Forward declare instruction sequence type. */ 759 typedef struct aarch64_instr_sequence aarch64_instr_sequence; 760 /* Forward declare instruction definition. */ 761 typedef struct aarch64_inst aarch64_inst; 762 763 /* This structure holds information for a particular opcode. */ 764 765 struct aarch64_opcode 766 { 767 /* The name of the mnemonic. */ 768 const char *name; 769 770 /* The opcode itself. Those bits which will be filled in with 771 operands are zeroes. */ 772 aarch64_insn opcode; 773 774 /* The opcode mask. This is used by the disassembler. This is a 775 mask containing ones indicating those bits which must match the 776 opcode field, and zeroes indicating those bits which need not 777 match (and are presumably filled in by operands). */ 778 aarch64_insn mask; 779 780 /* Instruction class. */ 781 enum aarch64_insn_class iclass; 782 783 /* Enumerator identifier. */ 784 enum aarch64_op op; 785 786 /* Which architecture variant provides this instruction. */ 787 const aarch64_feature_set *avariant; 788 789 /* An array of operand codes. Each code is an index into the 790 operand table. They appear in the order which the operands must 791 appear in assembly code, and are terminated by a zero. */ 792 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 793 794 /* A list of operand qualifier code sequence. Each operand qualifier 795 code qualifies the corresponding operand code. Each operand 796 qualifier sequence specifies a valid opcode variant and related 797 constraint on operands. */ 798 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 799 800 /* Flags providing information about this instruction */ 801 uint64_t flags; 802 803 /* Extra constraints on the instruction that the verifier checks. */ 804 uint32_t constraints; 805 806 /* If nonzero, this operand and operand 0 are both registers and 807 are required to have the same register number. */ 808 unsigned char tied_operand; 809 810 /* If non-NULL, a function to verify that a given instruction is valid. */ 811 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, 812 bfd_vma, bfd_boolean, aarch64_operand_error *, 813 struct aarch64_instr_sequence *); 814 }; 815 816 typedef struct aarch64_opcode aarch64_opcode; 817 818 /* Table describing all the AArch64 opcodes. */ 819 extern aarch64_opcode aarch64_opcode_table[]; 820 821 /* Opcode flags. */ 822 #define F_ALIAS (1 << 0) 823 #define F_HAS_ALIAS (1 << 1) 824 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 825 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 826 #define F_P1 (1 << 2) 827 #define F_P2 (2 << 2) 828 #define F_P3 (3 << 2) 829 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 830 #define F_COND (1 << 4) 831 /* Instruction has the field of 'sf'. */ 832 #define F_SF (1 << 5) 833 /* Instruction has the field of 'size:Q'. */ 834 #define F_SIZEQ (1 << 6) 835 /* Floating-point instruction has the field of 'type'. */ 836 #define F_FPTYPE (1 << 7) 837 /* AdvSIMD scalar instruction has the field of 'size'. */ 838 #define F_SSIZE (1 << 8) 839 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 840 #define F_T (1 << 9) 841 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 842 #define F_GPRSIZE_IN_Q (1 << 10) 843 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 844 #define F_LDS_SIZE (1 << 11) 845 /* Optional operand; assume maximum of 1 operand can be optional. */ 846 #define F_OPD0_OPT (1 << 12) 847 #define F_OPD1_OPT (2 << 12) 848 #define F_OPD2_OPT (3 << 12) 849 #define F_OPD3_OPT (4 << 12) 850 #define F_OPD4_OPT (5 << 12) 851 /* Default value for the optional operand when omitted from the assembly. */ 852 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 853 /* Instruction that is an alias of another instruction needs to be 854 encoded/decoded by converting it to/from the real form, followed by 855 the encoding/decoding according to the rules of the real opcode. 856 This compares to the direct coding using the alias's information. 857 N.B. this flag requires F_ALIAS to be used together. */ 858 #define F_CONV (1 << 20) 859 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 860 friendly pseudo instruction available only in the assembly code (thus will 861 not show up in the disassembly). */ 862 #define F_PSEUDO (1 << 21) 863 /* Instruction has miscellaneous encoding/decoding rules. */ 864 #define F_MISC (1 << 22) 865 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 866 #define F_N (1 << 23) 867 /* Opcode dependent field. */ 868 #define F_OD(X) (((X) & 0x7) << 24) 869 /* Instruction has the field of 'sz'. */ 870 #define F_LSE_SZ (1 << 27) 871 /* Require an exact qualifier match, even for NIL qualifiers. */ 872 #define F_STRICT (1ULL << 28) 873 /* This system instruction is used to read system registers. */ 874 #define F_SYS_READ (1ULL << 29) 875 /* This system instruction is used to write system registers. */ 876 #define F_SYS_WRITE (1ULL << 30) 877 /* This instruction has an extra constraint on it that imposes a requirement on 878 subsequent instructions. */ 879 #define F_SCAN (1ULL << 31) 880 /* Next bit is 32. */ 881 882 /* Instruction constraints. */ 883 /* This instruction has a predication constraint on the instruction at PC+4. */ 884 #define C_SCAN_MOVPRFX (1U << 0) 885 /* This instruction's operation width is determined by the operand with the 886 largest element size. */ 887 #define C_MAX_ELEM (1U << 1) 888 /* Next bit is 2. */ 889 890 static inline bfd_boolean 891 alias_opcode_p (const aarch64_opcode *opcode) 892 { 893 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 894 } 895 896 static inline bfd_boolean 897 opcode_has_alias (const aarch64_opcode *opcode) 898 { 899 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 900 } 901 902 /* Priority for disassembling preference. */ 903 static inline int 904 opcode_priority (const aarch64_opcode *opcode) 905 { 906 return (opcode->flags >> 2) & 0x3; 907 } 908 909 static inline bfd_boolean 910 pseudo_opcode_p (const aarch64_opcode *opcode) 911 { 912 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 913 } 914 915 static inline bfd_boolean 916 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 917 { 918 return (((opcode->flags >> 12) & 0x7) == idx + 1) 919 ? TRUE : FALSE; 920 } 921 922 static inline aarch64_insn 923 get_optional_operand_default_value (const aarch64_opcode *opcode) 924 { 925 return (opcode->flags >> 15) & 0x1f; 926 } 927 928 static inline unsigned int 929 get_opcode_dependent_value (const aarch64_opcode *opcode) 930 { 931 return (opcode->flags >> 24) & 0x7; 932 } 933 934 static inline bfd_boolean 935 opcode_has_special_coder (const aarch64_opcode *opcode) 936 { 937 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 938 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 939 : FALSE; 940 } 941 942 struct aarch64_name_value_pair 944 { 945 const char * name; 946 aarch64_insn value; 947 }; 948 949 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 950 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 951 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 952 extern const struct aarch64_name_value_pair aarch64_hint_options []; 953 954 #define AARCH64_MAX_SYSREG_NAME_LEN 32 955 956 typedef struct 957 { 958 const char * name; 959 aarch64_insn value; 960 uint32_t flags; 961 962 /* A set of features, all of which are required for this system register to be 963 available. */ 964 aarch64_feature_set features; 965 } aarch64_sys_reg; 966 967 extern const aarch64_sys_reg aarch64_sys_regs []; 968 extern const aarch64_sys_reg aarch64_pstatefields []; 969 extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t); 970 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, 971 const aarch64_sys_reg *); 972 973 typedef struct 974 { 975 const char *name; 976 uint32_t value; 977 uint32_t flags ; 978 } aarch64_sys_ins_reg; 979 980 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 981 extern bfd_boolean 982 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 983 const char *reg_name, aarch64_insn, 984 uint32_t, aarch64_feature_set); 985 986 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 987 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 988 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 989 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 990 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; 991 992 /* Shift/extending operator kinds. 993 N.B. order is important; keep aarch64_operand_modifiers synced. */ 994 enum aarch64_modifier_kind 995 { 996 AARCH64_MOD_NONE, 997 AARCH64_MOD_MSL, 998 AARCH64_MOD_ROR, 999 AARCH64_MOD_ASR, 1000 AARCH64_MOD_LSR, 1001 AARCH64_MOD_LSL, 1002 AARCH64_MOD_UXTB, 1003 AARCH64_MOD_UXTH, 1004 AARCH64_MOD_UXTW, 1005 AARCH64_MOD_UXTX, 1006 AARCH64_MOD_SXTB, 1007 AARCH64_MOD_SXTH, 1008 AARCH64_MOD_SXTW, 1009 AARCH64_MOD_SXTX, 1010 AARCH64_MOD_MUL, 1011 AARCH64_MOD_MUL_VL, 1012 }; 1013 1014 bfd_boolean 1015 aarch64_extend_operator_p (enum aarch64_modifier_kind); 1016 1017 enum aarch64_modifier_kind 1018 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 1019 /* Condition. */ 1020 1021 typedef struct 1022 { 1023 /* A list of names with the first one as the disassembly preference; 1024 terminated by NULL if fewer than 3. */ 1025 const char *names[4]; 1026 aarch64_insn value; 1027 } aarch64_cond; 1028 1029 extern const aarch64_cond aarch64_conds[16]; 1030 1031 const aarch64_cond* get_cond_from_value (aarch64_insn value); 1032 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 1033 1034 /* Structure representing an operand. */ 1036 1037 struct aarch64_opnd_info 1038 { 1039 enum aarch64_opnd type; 1040 aarch64_opnd_qualifier_t qualifier; 1041 int idx; 1042 1043 union 1044 { 1045 struct 1046 { 1047 unsigned regno; 1048 } reg; 1049 struct 1050 { 1051 unsigned int regno; 1052 int64_t index; 1053 } reglane; 1054 /* e.g. LVn. */ 1055 struct 1056 { 1057 unsigned first_regno : 5; 1058 unsigned num_regs : 3; 1059 /* 1 if it is a list of reg element. */ 1060 unsigned has_index : 1; 1061 /* Lane index; valid only when has_index is 1. */ 1062 int64_t index; 1063 } reglist; 1064 /* e.g. immediate or pc relative address offset. */ 1065 struct 1066 { 1067 int64_t value; 1068 unsigned is_fp : 1; 1069 } imm; 1070 /* e.g. address in STR (register offset). */ 1071 struct 1072 { 1073 unsigned base_regno; 1074 struct 1075 { 1076 union 1077 { 1078 int imm; 1079 unsigned regno; 1080 }; 1081 unsigned is_reg; 1082 } offset; 1083 unsigned pcrel : 1; /* PC-relative. */ 1084 unsigned writeback : 1; 1085 unsigned preind : 1; /* Pre-indexed. */ 1086 unsigned postind : 1; /* Post-indexed. */ 1087 } addr; 1088 1089 struct 1090 { 1091 /* The encoding of the system register. */ 1092 aarch64_insn value; 1093 1094 /* The system register flags. */ 1095 uint32_t flags; 1096 } sysreg; 1097 1098 const aarch64_cond *cond; 1099 /* The encoding of the PSTATE field. */ 1100 aarch64_insn pstatefield; 1101 const aarch64_sys_ins_reg *sysins_op; 1102 const struct aarch64_name_value_pair *barrier; 1103 const struct aarch64_name_value_pair *hint_option; 1104 const struct aarch64_name_value_pair *prfop; 1105 }; 1106 1107 /* Operand shifter; in use when the operand is a register offset address, 1108 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 1109 struct 1110 { 1111 enum aarch64_modifier_kind kind; 1112 unsigned operator_present: 1; /* Only valid during encoding. */ 1113 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 1114 unsigned amount_present: 1; 1115 int64_t amount; 1116 } shifter; 1117 1118 unsigned skip:1; /* Operand is not completed if there is a fixup needed 1119 to be done on it. In some (but not all) of these 1120 cases, we need to tell libopcodes to skip the 1121 constraint checking and the encoding for this 1122 operand, so that the libopcodes can pick up the 1123 right opcode before the operand is fixed-up. This 1124 flag should only be used during the 1125 assembling/encoding. */ 1126 unsigned present:1; /* Whether this operand is present in the assembly 1127 line; not used during the disassembly. */ 1128 }; 1129 1130 typedef struct aarch64_opnd_info aarch64_opnd_info; 1131 1132 /* Structure representing an instruction. 1133 1134 It is used during both the assembling and disassembling. The assembler 1135 fills an aarch64_inst after a successful parsing and then passes it to the 1136 encoding routine to do the encoding. During the disassembling, the 1137 disassembler calls the decoding routine to decode a binary instruction; on a 1138 successful return, such a structure will be filled with information of the 1139 instruction; then the disassembler uses the information to print out the 1140 instruction. */ 1141 1142 struct aarch64_inst 1143 { 1144 /* The value of the binary instruction. */ 1145 aarch64_insn value; 1146 1147 /* Corresponding opcode entry. */ 1148 const aarch64_opcode *opcode; 1149 1150 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 1151 const aarch64_cond *cond; 1152 1153 /* Operands information. */ 1154 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 1155 }; 1156 1157 /* Defining the HINT #imm values for the aarch64_hint_options. */ 1158 #define HINT_OPD_CSYNC 0x11 1159 #define HINT_OPD_C 0x22 1160 #define HINT_OPD_J 0x24 1161 #define HINT_OPD_JC 0x26 1162 #define HINT_OPD_NULL 0x00 1163 1164 1165 /* Diagnosis related declaration and interface. */ 1167 1168 /* Operand error kind enumerators. 1169 1170 AARCH64_OPDE_RECOVERABLE 1171 Less severe error found during the parsing, very possibly because that 1172 GAS has picked up a wrong instruction template for the parsing. 1173 1174 AARCH64_OPDE_SYNTAX_ERROR 1175 General syntax error; it can be either a user error, or simply because 1176 that GAS is trying a wrong instruction template. 1177 1178 AARCH64_OPDE_FATAL_SYNTAX_ERROR 1179 Definitely a user syntax error. 1180 1181 AARCH64_OPDE_INVALID_VARIANT 1182 No syntax error, but the operands are not a valid combination, e.g. 1183 FMOV D0,S0 1184 1185 AARCH64_OPDE_UNTIED_OPERAND 1186 The asm failed to use the same register for a destination operand 1187 and a tied source operand. 1188 1189 AARCH64_OPDE_OUT_OF_RANGE 1190 Error about some immediate value out of a valid range. 1191 1192 AARCH64_OPDE_UNALIGNED 1193 Error about some immediate value not properly aligned (i.e. not being a 1194 multiple times of a certain value). 1195 1196 AARCH64_OPDE_REG_LIST 1197 Error about the register list operand having unexpected number of 1198 registers. 1199 1200 AARCH64_OPDE_OTHER_ERROR 1201 Error of the highest severity and used for any severe issue that does not 1202 fall into any of the above categories. 1203 1204 The enumerators are only interesting to GAS. They are declared here (in 1205 libopcodes) because that some errors are detected (and then notified to GAS) 1206 by libopcodes (rather than by GAS solely). 1207 1208 The first three errors are only deteced by GAS while the 1209 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 1210 only libopcodes has the information about the valid variants of each 1211 instruction. 1212 1213 The enumerators have an increasing severity. This is helpful when there are 1214 multiple instruction templates available for a given mnemonic name (e.g. 1215 FMOV); this mechanism will help choose the most suitable template from which 1216 the generated diagnostics can most closely describe the issues, if any. */ 1217 1218 enum aarch64_operand_error_kind 1219 { 1220 AARCH64_OPDE_NIL, 1221 AARCH64_OPDE_RECOVERABLE, 1222 AARCH64_OPDE_SYNTAX_ERROR, 1223 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 1224 AARCH64_OPDE_INVALID_VARIANT, 1225 AARCH64_OPDE_UNTIED_OPERAND, 1226 AARCH64_OPDE_OUT_OF_RANGE, 1227 AARCH64_OPDE_UNALIGNED, 1228 AARCH64_OPDE_REG_LIST, 1229 AARCH64_OPDE_OTHER_ERROR 1230 }; 1231 1232 /* N.B. GAS assumes that this structure work well with shallow copy. */ 1233 struct aarch64_operand_error 1234 { 1235 enum aarch64_operand_error_kind kind; 1236 int index; 1237 const char *error; 1238 int data[3]; /* Some data for extra information. */ 1239 bfd_boolean non_fatal; 1240 }; 1241 1242 /* AArch64 sequence structure used to track instructions with F_SCAN 1243 dependencies for both assembler and disassembler. */ 1244 struct aarch64_instr_sequence 1245 { 1246 /* The instruction that caused this sequence to be opened. */ 1247 aarch64_inst *instr; 1248 /* The number of instructions the above instruction allows to be kept in the 1249 sequence before an automatic close is done. */ 1250 int num_insns; 1251 /* The instructions currently added to the sequence. */ 1252 aarch64_inst **current_insns; 1253 /* The number of instructions already in the sequence. */ 1254 int next_insn; 1255 }; 1256 1257 /* Encoding entrypoint. */ 1258 1259 extern int 1260 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 1261 aarch64_insn *, aarch64_opnd_qualifier_t *, 1262 aarch64_operand_error *, aarch64_instr_sequence *); 1263 1264 extern const aarch64_opcode * 1265 aarch64_replace_opcode (struct aarch64_inst *, 1266 const aarch64_opcode *); 1267 1268 /* Given the opcode enumerator OP, return the pointer to the corresponding 1269 opcode entry. */ 1270 1271 extern const aarch64_opcode * 1272 aarch64_get_opcode (enum aarch64_op); 1273 1274 /* Generate the string representation of an operand. */ 1275 extern void 1276 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 1277 const aarch64_opnd_info *, int, int *, bfd_vma *, 1278 char **, 1279 aarch64_feature_set features); 1280 1281 /* Miscellaneous interface. */ 1282 1283 extern int 1284 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 1285 1286 extern aarch64_opnd_qualifier_t 1287 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 1288 const aarch64_opnd_qualifier_t, int); 1289 1290 extern bfd_boolean 1291 aarch64_is_destructive_by_operands (const aarch64_opcode *); 1292 1293 extern int 1294 aarch64_num_of_operands (const aarch64_opcode *); 1295 1296 extern int 1297 aarch64_stack_pointer_p (const aarch64_opnd_info *); 1298 1299 extern int 1300 aarch64_zero_register_p (const aarch64_opnd_info *); 1301 1302 extern enum err_type 1303 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, 1304 aarch64_operand_error *); 1305 1306 extern void 1307 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *); 1308 1309 /* Given an operand qualifier, return the expected data element size 1310 of a qualified operand. */ 1311 extern unsigned char 1312 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 1313 1314 extern enum aarch64_operand_class 1315 aarch64_get_operand_class (enum aarch64_opnd); 1316 1317 extern const char * 1318 aarch64_get_operand_name (enum aarch64_opnd); 1319 1320 extern const char * 1321 aarch64_get_operand_desc (enum aarch64_opnd); 1322 1323 extern bfd_boolean 1324 aarch64_sve_dupm_mov_immediate_p (uint64_t, int); 1325 1326 #ifdef DEBUG_AARCH64 1327 extern int debug_dump; 1328 1329 extern void 1330 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 1331 1332 #define DEBUG_TRACE(M, ...) \ 1333 { \ 1334 if (debug_dump) \ 1335 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1336 } 1337 1338 #define DEBUG_TRACE_IF(C, M, ...) \ 1339 { \ 1340 if (debug_dump && (C)) \ 1341 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1342 } 1343 #else /* !DEBUG_AARCH64 */ 1344 #define DEBUG_TRACE(M, ...) ; 1345 #define DEBUG_TRACE_IF(C, M, ...) ; 1346 #endif /* DEBUG_AARCH64 */ 1347 1348 extern const char *const aarch64_sve_pattern_array[32]; 1349 extern const char *const aarch64_sve_prfop_array[16]; 1350 1351 #ifdef __cplusplus 1352 } 1353 #endif 1354 1355 #endif /* OPCODE_AARCH64_H */ 1356
Indexes created Sat Mar 28 00:23:22 UTC 2026