aarch64.h revision 1.1.1.9
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2022 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include <stdint.h> 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #include "dis-asm.h" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* The offset for pc-relative addressing is currently defined to be 0. */ 37 #define AARCH64_PCREL_OFFSET 0 38 39 typedef uint32_t aarch64_insn; 40 41 /* The following bitmasks control CPU features. */ 42 #define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */ 43 #define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */ 44 #define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */ 45 #define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */ 46 #define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */ 47 #define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */ 48 #define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */ 49 #define AARCH64_FEATURE_SVE2_AES (1ULL << 7) 50 #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8) 51 #define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9) 52 #define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) 53 #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ 54 #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ 55 #define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ 56 #define AARCH64_FEATURE_SME (1ULL << 14) /* Scalable Matrix Extension. */ 57 #define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ 58 #define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */ 59 #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ 60 #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ 61 #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ 62 #define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */ 63 #define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */ 64 #define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */ 65 #define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */ 66 #define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */ 67 #define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */ 68 #define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */ 69 #define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */ 70 #define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */ 71 #define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */ 72 #define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */ 73 #define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */ 74 #define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */ 75 #define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */ 76 #define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */ 77 #define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */ 78 #define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */ 79 #define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */ 80 #define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */ 81 #define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */ 82 #define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */ 83 #define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */ 84 #define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */ 85 #define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */ 86 #define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */ 87 #define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */ 88 #define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */ 89 #define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */ 90 #define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */ 91 #define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */ 92 #define AARCH64_FEATURE_MOPS (1ULL << 50) /* Standardization of memory operations. */ 93 #define AARCH64_FEATURE_HBC (1ULL << 51) /* Hinted conditional branches. */ 94 #define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */ 95 #define AARCH64_FEATURE_F32MM (1ULL << 53) 96 #define AARCH64_FEATURE_F64MM (1ULL << 54) 97 #define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */ 98 #define AARCH64_FEATURE_V9 (1ULL << 56) /* Armv9.0-A processors. */ 99 #define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */ 100 #define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */ 101 #define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ 102 #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ 103 104 /* Crypto instructions are the combination of AES and SHA2. */ 105 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) 106 107 #define AARCH64_ARCH_V8_FEATURES (AARCH64_FEATURE_V8_A \ 108 | AARCH64_FEATURE_FP \ 109 | AARCH64_FEATURE_RAS \ 110 | AARCH64_FEATURE_SIMD) 111 #define AARCH64_ARCH_V8_1_FEATURES (AARCH64_FEATURE_V8_1 \ 112 | AARCH64_FEATURE_CRC \ 113 | AARCH64_FEATURE_LSE \ 114 | AARCH64_FEATURE_PAN \ 115 | AARCH64_FEATURE_LOR \ 116 | AARCH64_FEATURE_RDMA) 117 #define AARCH64_ARCH_V8_2_FEATURES (AARCH64_FEATURE_V8_2) 118 #define AARCH64_ARCH_V8_3_FEATURES (AARCH64_FEATURE_V8_3 \ 119 | AARCH64_FEATURE_PAC \ 120 | AARCH64_FEATURE_RCPC \ 121 | AARCH64_FEATURE_COMPNUM) 122 #define AARCH64_ARCH_V8_4_FEATURES (AARCH64_FEATURE_V8_4 \ 123 | AARCH64_FEATURE_DOTPROD \ 124 | AARCH64_FEATURE_FLAGM \ 125 | AARCH64_FEATURE_F16_FML) 126 #define AARCH64_ARCH_V8_5_FEATURES (AARCH64_FEATURE_V8_5 \ 127 | AARCH64_FEATURE_FLAGMANIP \ 128 | AARCH64_FEATURE_FRINTTS \ 129 | AARCH64_FEATURE_SB \ 130 | AARCH64_FEATURE_PREDRES \ 131 | AARCH64_FEATURE_CVADP \ 132 | AARCH64_FEATURE_BTI \ 133 | AARCH64_FEATURE_SCXTNUM \ 134 | AARCH64_FEATURE_ID_PFR2 \ 135 | AARCH64_FEATURE_SSBS) 136 #define AARCH64_ARCH_V8_6_FEATURES (AARCH64_FEATURE_V8_6 \ 137 | AARCH64_FEATURE_BFLOAT16 \ 138 | AARCH64_FEATURE_I8MM) 139 #define AARCH64_ARCH_V8_7_FEATURES (AARCH64_FEATURE_V8_7 \ 140 | AARCH64_FEATURE_LS64) 141 #define AARCH64_ARCH_V8_8_FEATURES (AARCH64_FEATURE_V8_8 \ 142 | AARCH64_FEATURE_MOPS \ 143 | AARCH64_FEATURE_HBC) 144 145 #define AARCH64_ARCH_V9_FEATURES (AARCH64_FEATURE_V9 \ 146 | AARCH64_FEATURE_F16 \ 147 | AARCH64_FEATURE_SVE \ 148 | AARCH64_FEATURE_SVE2) 149 #define AARCH64_ARCH_V9_1_FEATURES (AARCH64_ARCH_V8_6_FEATURES) 150 #define AARCH64_ARCH_V9_2_FEATURES (AARCH64_ARCH_V8_7_FEATURES) 151 #define AARCH64_ARCH_V9_3_FEATURES (AARCH64_ARCH_V8_8_FEATURES) 152 153 /* Architectures are the sum of the base and extensions. */ 154 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 155 AARCH64_ARCH_V8_FEATURES) 156 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ 157 AARCH64_ARCH_V8_1_FEATURES) 158 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ 159 AARCH64_ARCH_V8_2_FEATURES) 160 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ 161 AARCH64_ARCH_V8_3_FEATURES) 162 #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ 163 AARCH64_ARCH_V8_4_FEATURES) 164 #define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ 165 AARCH64_ARCH_V8_5_FEATURES) 166 #define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ 167 AARCH64_ARCH_V8_6_FEATURES) 168 #define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ 169 AARCH64_ARCH_V8_7_FEATURES) 170 #define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \ 171 AARCH64_ARCH_V8_8_FEATURES) 172 #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ 173 AARCH64_FEATURE_V8_R) \ 174 & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) 175 176 #define AARCH64_ARCH_V9 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ 177 AARCH64_ARCH_V9_FEATURES) 178 #define AARCH64_ARCH_V9_1 AARCH64_FEATURE (AARCH64_ARCH_V9, \ 179 AARCH64_ARCH_V9_1_FEATURES) 180 #define AARCH64_ARCH_V9_2 AARCH64_FEATURE (AARCH64_ARCH_V9_1, \ 181 AARCH64_ARCH_V9_2_FEATURES) 182 #define AARCH64_ARCH_V9_3 AARCH64_FEATURE (AARCH64_ARCH_V9_2, \ 183 AARCH64_ARCH_V9_3_FEATURES) 184 185 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 186 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 187 188 /* CPU-specific features. */ 189 typedef unsigned long long aarch64_feature_set; 190 191 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 192 ((~(CPU) & (FEAT)) == 0) 193 194 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 195 (((CPU) & (FEAT)) != 0) 196 197 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 198 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 199 200 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 201 do \ 202 { \ 203 (TARG) = (F1) | (F2); \ 204 } \ 205 while (0) 206 207 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 208 do \ 209 { \ 210 (TARG) = (F1) &~ (F2); \ 211 } \ 212 while (0) 213 214 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 215 216 enum aarch64_operand_class 217 { 218 AARCH64_OPND_CLASS_NIL, 219 AARCH64_OPND_CLASS_INT_REG, 220 AARCH64_OPND_CLASS_MODIFIED_REG, 221 AARCH64_OPND_CLASS_FP_REG, 222 AARCH64_OPND_CLASS_SIMD_REG, 223 AARCH64_OPND_CLASS_SIMD_ELEMENT, 224 AARCH64_OPND_CLASS_SISD_REG, 225 AARCH64_OPND_CLASS_SIMD_REGLIST, 226 AARCH64_OPND_CLASS_SVE_REG, 227 AARCH64_OPND_CLASS_PRED_REG, 228 AARCH64_OPND_CLASS_ADDRESS, 229 AARCH64_OPND_CLASS_IMMEDIATE, 230 AARCH64_OPND_CLASS_SYSTEM, 231 AARCH64_OPND_CLASS_COND, 232 }; 233 234 /* Operand code that helps both parsing and coding. 235 Keep AARCH64_OPERANDS synced. */ 236 237 enum aarch64_opnd 238 { 239 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 240 241 AARCH64_OPND_Rd, /* Integer register as destination. */ 242 AARCH64_OPND_Rn, /* Integer register as source. */ 243 AARCH64_OPND_Rm, /* Integer register as source. */ 244 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 245 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 246 AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ 247 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ 248 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 249 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 250 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 251 252 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 253 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 254 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ 255 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 256 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 257 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 258 259 AARCH64_OPND_Fd, /* Floating-point Fd. */ 260 AARCH64_OPND_Fn, /* Floating-point Fn. */ 261 AARCH64_OPND_Fm, /* Floating-point Fm. */ 262 AARCH64_OPND_Fa, /* Floating-point Fa. */ 263 AARCH64_OPND_Ft, /* Floating-point Ft. */ 264 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 265 266 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 267 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 268 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 269 270 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ 271 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 272 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 273 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 274 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 275 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 276 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 277 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 278 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 279 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when 280 qualifier is S_H. */ 281 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 282 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 283 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 284 structure to all lanes. */ 285 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 286 287 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ 288 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ 289 290 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 291 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ 292 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 293 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 294 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 295 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 296 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 297 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 298 (no encoding). */ 299 AARCH64_OPND_IMM0, /* Immediate for #0. */ 300 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 301 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 302 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 303 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 304 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 305 AARCH64_OPND_IMM, /* Immediate. */ 306 AARCH64_OPND_IMM_2, /* Immediate. */ 307 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 308 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 309 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 310 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ 311 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 312 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ 313 AARCH64_OPND_BIT_NUM, /* Immediate. */ 314 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 315 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ 316 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 317 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ 318 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 319 each condition flag. */ 320 321 AARCH64_OPND_LIMM, /* Logical Immediate. */ 322 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 323 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 324 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 325 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 326 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ 327 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ 328 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ 329 330 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 331 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 332 333 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 334 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 335 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 336 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 337 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 338 339 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 340 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 341 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 342 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 343 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 344 negative or unaligned and there is 345 no writeback allowed. This operand code 346 is only used to support the programmer- 347 friendly feature of using LDR/STR as the 348 the mnemonic name for LDUR/STUR instructions 349 wherever there is no ambiguity. */ 350 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ 351 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of 352 16) immediate. */ 353 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 354 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of 355 16) immediate. */ 356 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 357 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ 358 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 359 360 AARCH64_OPND_SYSREG, /* System register operand. */ 361 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 362 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 363 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 364 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 365 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 366 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ 367 AARCH64_OPND_BARRIER, /* Barrier operand. */ 368 AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ 369 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 370 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 371 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 372 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ 373 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ 374 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ 375 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ 376 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ 377 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ 378 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ 379 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ 380 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ 381 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ 382 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ 383 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ 384 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ 385 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ 386 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ 387 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ 388 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ 389 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ 390 AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ 391 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ 392 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ 393 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ 394 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ 395 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */ 396 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ 397 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ 398 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ 399 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ 400 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 401 Bit 14 controls S/U choice. */ 402 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 403 Bit 22 controls S/U choice. */ 404 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 405 Bit 14 controls S/U choice. */ 406 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 407 Bit 22 controls S/U choice. */ 408 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 409 Bit 14 controls S/U choice. */ 410 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 411 Bit 22 controls S/U choice. */ 412 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 413 Bit 14 controls S/U choice. */ 414 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 415 Bit 22 controls S/U choice. */ 416 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ 417 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ 418 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ 419 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ 420 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ 421 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ 422 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ 423 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ 424 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ 425 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ 426 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ 427 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ 428 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ 429 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ 430 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ 431 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */ 432 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ 433 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ 434 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ 435 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ 436 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ 437 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ 438 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ 439 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ 440 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ 441 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ 442 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ 443 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ 444 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ 445 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ 446 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ 447 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ 448 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ 449 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ 450 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */ 451 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ 452 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ 453 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ 454 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ 455 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ 456 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ 457 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ 458 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ 459 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ 460 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ 461 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ 462 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ 463 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ 464 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ 465 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ 466 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ 467 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ 468 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ 469 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ 470 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ 471 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ 472 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ 473 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ 474 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ 475 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ 476 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ 477 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ 478 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ 479 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ 480 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ 481 AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ 482 AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ 483 AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ 484 AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ 485 AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ 486 AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ 487 AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ 488 AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */ 489 AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ 490 AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ 491 AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ 492 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ 493 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ 494 AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ 495 AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ 496 AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ 497 AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ 498 AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ 499 }; 500 501 /* Qualifier constrains an operand. It either specifies a variant of an 502 operand type or limits values available to an operand type. 503 504 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 505 506 enum aarch64_opnd_qualifier 507 { 508 /* Indicating no further qualification on an operand. */ 509 AARCH64_OPND_QLF_NIL, 510 511 /* Qualifying an operand which is a general purpose (integer) register; 512 indicating the operand data size or a specific register. */ 513 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 514 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 515 AARCH64_OPND_QLF_WSP, /* WSP. */ 516 AARCH64_OPND_QLF_SP, /* SP. */ 517 518 /* Qualifying an operand which is a floating-point register, a SIMD 519 vector element or a SIMD vector element list; indicating operand data 520 size or the size of each SIMD vector element in the case of a SIMD 521 vector element list. 522 These qualifiers are also used to qualify an address operand to 523 indicate the size of data element a load/store instruction is 524 accessing. 525 They are also used for the immediate shift operand in e.g. SSHR. Such 526 a use is only for the ease of operand encoding/decoding and qualifier 527 sequence matching; such a use should not be applied widely; use the value 528 constraint qualifiers for immediate operands wherever possible. */ 529 AARCH64_OPND_QLF_S_B, 530 AARCH64_OPND_QLF_S_H, 531 AARCH64_OPND_QLF_S_S, 532 AARCH64_OPND_QLF_S_D, 533 AARCH64_OPND_QLF_S_Q, 534 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte 535 or 2 x 2 byte are selected by the instruction. Other than that they have 536 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely 537 for syntactical reasons and is an exception from normal AArch64 538 disassembly scheme. */ 539 AARCH64_OPND_QLF_S_4B, 540 AARCH64_OPND_QLF_S_2H, 541 542 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 543 register list; indicating register shape. 544 They are also used for the immediate shift operand in e.g. SSHR. Such 545 a use is only for the ease of operand encoding/decoding and qualifier 546 sequence matching; such a use should not be applied widely; use the value 547 constraint qualifiers for immediate operands wherever possible. */ 548 AARCH64_OPND_QLF_V_4B, 549 AARCH64_OPND_QLF_V_8B, 550 AARCH64_OPND_QLF_V_16B, 551 AARCH64_OPND_QLF_V_2H, 552 AARCH64_OPND_QLF_V_4H, 553 AARCH64_OPND_QLF_V_8H, 554 AARCH64_OPND_QLF_V_2S, 555 AARCH64_OPND_QLF_V_4S, 556 AARCH64_OPND_QLF_V_1D, 557 AARCH64_OPND_QLF_V_2D, 558 AARCH64_OPND_QLF_V_1Q, 559 560 AARCH64_OPND_QLF_P_Z, 561 AARCH64_OPND_QLF_P_M, 562 563 /* Used in scaled signed immediate that are scaled by a Tag granule 564 like in stg, st2g, etc. */ 565 AARCH64_OPND_QLF_imm_tag, 566 567 /* Constraint on value. */ 568 AARCH64_OPND_QLF_CR, /* CRn, CRm. */ 569 AARCH64_OPND_QLF_imm_0_7, 570 AARCH64_OPND_QLF_imm_0_15, 571 AARCH64_OPND_QLF_imm_0_31, 572 AARCH64_OPND_QLF_imm_0_63, 573 AARCH64_OPND_QLF_imm_1_32, 574 AARCH64_OPND_QLF_imm_1_64, 575 576 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 577 or shift-ones. */ 578 AARCH64_OPND_QLF_LSL, 579 AARCH64_OPND_QLF_MSL, 580 581 /* Special qualifier helping retrieve qualifier information during the 582 decoding time (currently not in use). */ 583 AARCH64_OPND_QLF_RETRIEVE, 584 }; 585 586 /* Instruction class. */ 588 589 enum aarch64_insn_class 590 { 591 aarch64_misc, 592 addsub_carry, 593 addsub_ext, 594 addsub_imm, 595 addsub_shift, 596 asimdall, 597 asimddiff, 598 asimdelem, 599 asimdext, 600 asimdimm, 601 asimdins, 602 asimdmisc, 603 asimdperm, 604 asimdsame, 605 asimdshf, 606 asimdtbl, 607 asisddiff, 608 asisdelem, 609 asisdlse, 610 asisdlsep, 611 asisdlso, 612 asisdlsop, 613 asisdmisc, 614 asisdone, 615 asisdpair, 616 asisdsame, 617 asisdshf, 618 bitfield, 619 branch_imm, 620 branch_reg, 621 compbranch, 622 condbranch, 623 condcmp_imm, 624 condcmp_reg, 625 condsel, 626 cryptoaes, 627 cryptosha2, 628 cryptosha3, 629 dp_1src, 630 dp_2src, 631 dp_3src, 632 exception, 633 extract, 634 float2fix, 635 float2int, 636 floatccmp, 637 floatcmp, 638 floatdp1, 639 floatdp2, 640 floatdp3, 641 floatimm, 642 floatsel, 643 ldst_immpost, 644 ldst_immpre, 645 ldst_imm9, /* immpost or immpre */ 646 ldst_imm10, /* LDRAA/LDRAB */ 647 ldst_pos, 648 ldst_regoff, 649 ldst_unpriv, 650 ldst_unscaled, 651 ldstexcl, 652 ldstnapair_offs, 653 ldstpair_off, 654 ldstpair_indexed, 655 loadlit, 656 log_imm, 657 log_shift, 658 lse_atomic, 659 movewide, 660 pcreladdr, 661 ic_system, 662 sme_misc, 663 sme_ldr, 664 sme_str, 665 sme_start, 666 sme_stop, 667 sve_cpy, 668 sve_index, 669 sve_limm, 670 sve_misc, 671 sve_movprfx, 672 sve_pred_zm, 673 sve_shift_pred, 674 sve_shift_unpred, 675 sve_size_bhs, 676 sve_size_bhsd, 677 sve_size_hsd, 678 sve_size_hsd2, 679 sve_size_sd, 680 sve_size_bh, 681 sve_size_sd2, 682 sve_size_13, 683 sve_shift_tsz_hsd, 684 sve_shift_tsz_bhsd, 685 sve_size_tsz_bhs, 686 testbranch, 687 cryptosm3, 688 cryptosm4, 689 dotproduct, 690 bfloat16, 691 cssc, 692 }; 693 694 /* Opcode enumerators. */ 695 696 enum aarch64_op 697 { 698 OP_NIL, 699 OP_STRB_POS, 700 OP_LDRB_POS, 701 OP_LDRSB_POS, 702 OP_STRH_POS, 703 OP_LDRH_POS, 704 OP_LDRSH_POS, 705 OP_STR_POS, 706 OP_LDR_POS, 707 OP_STRF_POS, 708 OP_LDRF_POS, 709 OP_LDRSW_POS, 710 OP_PRFM_POS, 711 712 OP_STURB, 713 OP_LDURB, 714 OP_LDURSB, 715 OP_STURH, 716 OP_LDURH, 717 OP_LDURSH, 718 OP_STUR, 719 OP_LDUR, 720 OP_STURV, 721 OP_LDURV, 722 OP_LDURSW, 723 OP_PRFUM, 724 725 OP_LDR_LIT, 726 OP_LDRV_LIT, 727 OP_LDRSW_LIT, 728 OP_PRFM_LIT, 729 730 OP_ADD, 731 OP_B, 732 OP_BL, 733 734 OP_MOVN, 735 OP_MOVZ, 736 OP_MOVK, 737 738 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 739 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 740 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 741 742 OP_MOV_V, /* MOV alias for moving vector register. */ 743 744 OP_ASR_IMM, 745 OP_LSR_IMM, 746 OP_LSL_IMM, 747 748 OP_BIC, 749 750 OP_UBFX, 751 OP_BFXIL, 752 OP_SBFX, 753 OP_SBFIZ, 754 OP_BFI, 755 OP_BFC, /* ARMv8.2. */ 756 OP_UBFIZ, 757 OP_UXTB, 758 OP_UXTH, 759 OP_UXTW, 760 761 OP_CINC, 762 OP_CINV, 763 OP_CNEG, 764 OP_CSET, 765 OP_CSETM, 766 767 OP_FCVT, 768 OP_FCVTN, 769 OP_FCVTN2, 770 OP_FCVTL, 771 OP_FCVTL2, 772 OP_FCVTXN_S, /* Scalar version. */ 773 774 OP_ROR_IMM, 775 776 OP_SXTL, 777 OP_SXTL2, 778 OP_UXTL, 779 OP_UXTL2, 780 781 OP_MOV_P_P, 782 OP_MOV_Z_P_Z, 783 OP_MOV_Z_V, 784 OP_MOV_Z_Z, 785 OP_MOV_Z_Zi, 786 OP_MOVM_P_P_P, 787 OP_MOVS_P_P, 788 OP_MOVZS_P_P_P, 789 OP_MOVZ_P_P_P, 790 OP_NOTS_P_P_P_Z, 791 OP_NOT_P_P_P_Z, 792 793 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ 794 795 OP_TOTAL_NUM, /* Pseudo. */ 796 }; 797 798 /* Error types. */ 799 enum err_type 800 { 801 ERR_OK, 802 ERR_UND, 803 ERR_UNP, 804 ERR_NYI, 805 ERR_VFI, 806 ERR_NR_ENTRIES 807 }; 808 809 /* Maximum number of operands an instruction can have. */ 810 #define AARCH64_MAX_OPND_NUM 6 811 /* Maximum number of qualifier sequences an instruction can have. */ 812 #define AARCH64_MAX_QLF_SEQ_NUM 10 813 /* Operand qualifier typedef; optimized for the size. */ 814 typedef unsigned char aarch64_opnd_qualifier_t; 815 /* Operand qualifier sequence typedef. */ 816 typedef aarch64_opnd_qualifier_t \ 817 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 818 819 /* FIXME: improve the efficiency. */ 820 static inline bool 821 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 822 { 823 int i; 824 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 825 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 826 return false; 827 return true; 828 } 829 830 /* Forward declare error reporting type. */ 831 typedef struct aarch64_operand_error aarch64_operand_error; 832 /* Forward declare instruction sequence type. */ 833 typedef struct aarch64_instr_sequence aarch64_instr_sequence; 834 /* Forward declare instruction definition. */ 835 typedef struct aarch64_inst aarch64_inst; 836 837 /* This structure holds information for a particular opcode. */ 838 839 struct aarch64_opcode 840 { 841 /* The name of the mnemonic. */ 842 const char *name; 843 844 /* The opcode itself. Those bits which will be filled in with 845 operands are zeroes. */ 846 aarch64_insn opcode; 847 848 /* The opcode mask. This is used by the disassembler. This is a 849 mask containing ones indicating those bits which must match the 850 opcode field, and zeroes indicating those bits which need not 851 match (and are presumably filled in by operands). */ 852 aarch64_insn mask; 853 854 /* Instruction class. */ 855 enum aarch64_insn_class iclass; 856 857 /* Enumerator identifier. */ 858 enum aarch64_op op; 859 860 /* Which architecture variant provides this instruction. */ 861 const aarch64_feature_set *avariant; 862 863 /* An array of operand codes. Each code is an index into the 864 operand table. They appear in the order which the operands must 865 appear in assembly code, and are terminated by a zero. */ 866 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 867 868 /* A list of operand qualifier code sequence. Each operand qualifier 869 code qualifies the corresponding operand code. Each operand 870 qualifier sequence specifies a valid opcode variant and related 871 constraint on operands. */ 872 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 873 874 /* Flags providing information about this instruction */ 875 uint64_t flags; 876 877 /* Extra constraints on the instruction that the verifier checks. */ 878 uint32_t constraints; 879 880 /* If nonzero, this operand and operand 0 are both registers and 881 are required to have the same register number. */ 882 unsigned char tied_operand; 883 884 /* If non-NULL, a function to verify that a given instruction is valid. */ 885 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, 886 bfd_vma, bool, aarch64_operand_error *, 887 struct aarch64_instr_sequence *); 888 }; 889 890 typedef struct aarch64_opcode aarch64_opcode; 891 892 /* Table describing all the AArch64 opcodes. */ 893 extern const aarch64_opcode aarch64_opcode_table[]; 894 895 /* Opcode flags. */ 896 #define F_ALIAS (1 << 0) 897 #define F_HAS_ALIAS (1 << 1) 898 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 899 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 900 #define F_P1 (1 << 2) 901 #define F_P2 (2 << 2) 902 #define F_P3 (3 << 2) 903 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 904 #define F_COND (1 << 4) 905 /* Instruction has the field of 'sf'. */ 906 #define F_SF (1 << 5) 907 /* Instruction has the field of 'size:Q'. */ 908 #define F_SIZEQ (1 << 6) 909 /* Floating-point instruction has the field of 'type'. */ 910 #define F_FPTYPE (1 << 7) 911 /* AdvSIMD scalar instruction has the field of 'size'. */ 912 #define F_SSIZE (1 << 8) 913 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 914 #define F_T (1 << 9) 915 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 916 #define F_GPRSIZE_IN_Q (1 << 10) 917 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 918 #define F_LDS_SIZE (1 << 11) 919 /* Optional operand; assume maximum of 1 operand can be optional. */ 920 #define F_OPD0_OPT (1 << 12) 921 #define F_OPD1_OPT (2 << 12) 922 #define F_OPD2_OPT (3 << 12) 923 #define F_OPD3_OPT (4 << 12) 924 #define F_OPD4_OPT (5 << 12) 925 /* Default value for the optional operand when omitted from the assembly. */ 926 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 927 /* Instruction that is an alias of another instruction needs to be 928 encoded/decoded by converting it to/from the real form, followed by 929 the encoding/decoding according to the rules of the real opcode. 930 This compares to the direct coding using the alias's information. 931 N.B. this flag requires F_ALIAS to be used together. */ 932 #define F_CONV (1 << 20) 933 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 934 friendly pseudo instruction available only in the assembly code (thus will 935 not show up in the disassembly). */ 936 #define F_PSEUDO (1 << 21) 937 /* Instruction has miscellaneous encoding/decoding rules. */ 938 #define F_MISC (1 << 22) 939 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 940 #define F_N (1 << 23) 941 /* Opcode dependent field. */ 942 #define F_OD(X) (((X) & 0x7) << 24) 943 /* Instruction has the field of 'sz'. */ 944 #define F_LSE_SZ (1 << 27) 945 /* Require an exact qualifier match, even for NIL qualifiers. */ 946 #define F_STRICT (1ULL << 28) 947 /* This system instruction is used to read system registers. */ 948 #define F_SYS_READ (1ULL << 29) 949 /* This system instruction is used to write system registers. */ 950 #define F_SYS_WRITE (1ULL << 30) 951 /* This instruction has an extra constraint on it that imposes a requirement on 952 subsequent instructions. */ 953 #define F_SCAN (1ULL << 31) 954 /* Next bit is 32. */ 955 956 /* Instruction constraints. */ 957 /* This instruction has a predication constraint on the instruction at PC+4. */ 958 #define C_SCAN_MOVPRFX (1U << 0) 959 /* This instruction's operation width is determined by the operand with the 960 largest element size. */ 961 #define C_MAX_ELEM (1U << 1) 962 #define C_SCAN_MOPS_P (1U << 2) 963 #define C_SCAN_MOPS_M (2U << 2) 964 #define C_SCAN_MOPS_E (3U << 2) 965 #define C_SCAN_MOPS_PME (3U << 2) 966 /* Next bit is 4. */ 967 968 static inline bool 969 alias_opcode_p (const aarch64_opcode *opcode) 970 { 971 return (opcode->flags & F_ALIAS) != 0; 972 } 973 974 static inline bool 975 opcode_has_alias (const aarch64_opcode *opcode) 976 { 977 return (opcode->flags & F_HAS_ALIAS) != 0; 978 } 979 980 /* Priority for disassembling preference. */ 981 static inline int 982 opcode_priority (const aarch64_opcode *opcode) 983 { 984 return (opcode->flags >> 2) & 0x3; 985 } 986 987 static inline bool 988 pseudo_opcode_p (const aarch64_opcode *opcode) 989 { 990 return (opcode->flags & F_PSEUDO) != 0lu; 991 } 992 993 static inline bool 994 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 995 { 996 return ((opcode->flags >> 12) & 0x7) == idx + 1; 997 } 998 999 static inline aarch64_insn 1000 get_optional_operand_default_value (const aarch64_opcode *opcode) 1001 { 1002 return (opcode->flags >> 15) & 0x1f; 1003 } 1004 1005 static inline unsigned int 1006 get_opcode_dependent_value (const aarch64_opcode *opcode) 1007 { 1008 return (opcode->flags >> 24) & 0x7; 1009 } 1010 1011 static inline bool 1012 opcode_has_special_coder (const aarch64_opcode *opcode) 1013 { 1014 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 1015 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; 1016 } 1017 1018 struct aarch64_name_value_pair 1020 { 1021 const char * name; 1022 aarch64_insn value; 1023 }; 1024 1025 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 1026 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 1027 extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4]; 1028 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 1029 extern const struct aarch64_name_value_pair aarch64_hint_options []; 1030 1031 #define AARCH64_MAX_SYSREG_NAME_LEN 32 1032 1033 typedef struct 1034 { 1035 const char * name; 1036 aarch64_insn value; 1037 uint32_t flags; 1038 1039 /* A set of features, all of which are required for this system register to be 1040 available. */ 1041 aarch64_feature_set features; 1042 } aarch64_sys_reg; 1043 1044 extern const aarch64_sys_reg aarch64_sys_regs []; 1045 extern const aarch64_sys_reg aarch64_pstatefields []; 1046 extern bool aarch64_sys_reg_deprecated_p (const uint32_t); 1047 extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set, 1048 const aarch64_sys_reg *); 1049 1050 typedef struct 1051 { 1052 const char *name; 1053 uint32_t value; 1054 uint32_t flags ; 1055 } aarch64_sys_ins_reg; 1056 1057 extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 1058 extern bool 1059 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 1060 const char *reg_name, aarch64_insn, 1061 uint32_t, aarch64_feature_set); 1062 1063 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 1064 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 1065 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 1066 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 1067 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; 1068 1069 /* Shift/extending operator kinds. 1070 N.B. order is important; keep aarch64_operand_modifiers synced. */ 1071 enum aarch64_modifier_kind 1072 { 1073 AARCH64_MOD_NONE, 1074 AARCH64_MOD_MSL, 1075 AARCH64_MOD_ROR, 1076 AARCH64_MOD_ASR, 1077 AARCH64_MOD_LSR, 1078 AARCH64_MOD_LSL, 1079 AARCH64_MOD_UXTB, 1080 AARCH64_MOD_UXTH, 1081 AARCH64_MOD_UXTW, 1082 AARCH64_MOD_UXTX, 1083 AARCH64_MOD_SXTB, 1084 AARCH64_MOD_SXTH, 1085 AARCH64_MOD_SXTW, 1086 AARCH64_MOD_SXTX, 1087 AARCH64_MOD_MUL, 1088 AARCH64_MOD_MUL_VL, 1089 }; 1090 1091 bool 1092 aarch64_extend_operator_p (enum aarch64_modifier_kind); 1093 1094 enum aarch64_modifier_kind 1095 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 1096 /* Condition. */ 1097 1098 typedef struct 1099 { 1100 /* A list of names with the first one as the disassembly preference; 1101 terminated by NULL if fewer than 3. */ 1102 const char *names[4]; 1103 aarch64_insn value; 1104 } aarch64_cond; 1105 1106 extern const aarch64_cond aarch64_conds[16]; 1107 1108 const aarch64_cond* get_cond_from_value (aarch64_insn value); 1109 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 1110 1111 /* Structure representing an operand. */ 1113 1114 struct aarch64_opnd_info 1115 { 1116 enum aarch64_opnd type; 1117 aarch64_opnd_qualifier_t qualifier; 1118 int idx; 1119 1120 union 1121 { 1122 struct 1123 { 1124 unsigned regno; 1125 } reg; 1126 struct 1127 { 1128 unsigned int regno; 1129 int64_t index; 1130 } reglane; 1131 /* e.g. LVn. */ 1132 struct 1133 { 1134 unsigned first_regno : 5; 1135 unsigned num_regs : 3; 1136 /* 1 if it is a list of reg element. */ 1137 unsigned has_index : 1; 1138 /* Lane index; valid only when has_index is 1. */ 1139 int64_t index; 1140 } reglist; 1141 /* e.g. immediate or pc relative address offset. */ 1142 struct 1143 { 1144 int64_t value; 1145 unsigned is_fp : 1; 1146 } imm; 1147 /* e.g. address in STR (register offset). */ 1148 struct 1149 { 1150 unsigned base_regno; 1151 struct 1152 { 1153 union 1154 { 1155 int imm; 1156 unsigned regno; 1157 }; 1158 unsigned is_reg; 1159 } offset; 1160 unsigned pcrel : 1; /* PC-relative. */ 1161 unsigned writeback : 1; 1162 unsigned preind : 1; /* Pre-indexed. */ 1163 unsigned postind : 1; /* Post-indexed. */ 1164 } addr; 1165 1166 struct 1167 { 1168 /* The encoding of the system register. */ 1169 aarch64_insn value; 1170 1171 /* The system register flags. */ 1172 uint32_t flags; 1173 } sysreg; 1174 1175 /* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */ 1176 struct 1177 { 1178 int regno; /* <ZAn> */ 1179 struct 1180 { 1181 int regno; /* <Wv> */ 1182 int imm; /* <imm> */ 1183 } index; 1184 unsigned v : 1; /* <HV> horizontal or vertical vector indicator. */ 1185 } za_tile_vector; 1186 1187 const aarch64_cond *cond; 1188 /* The encoding of the PSTATE field. */ 1189 aarch64_insn pstatefield; 1190 const aarch64_sys_ins_reg *sysins_op; 1191 const struct aarch64_name_value_pair *barrier; 1192 const struct aarch64_name_value_pair *hint_option; 1193 const struct aarch64_name_value_pair *prfop; 1194 }; 1195 1196 /* Operand shifter; in use when the operand is a register offset address, 1197 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 1198 struct 1199 { 1200 enum aarch64_modifier_kind kind; 1201 unsigned operator_present: 1; /* Only valid during encoding. */ 1202 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 1203 unsigned amount_present: 1; 1204 int64_t amount; 1205 } shifter; 1206 1207 unsigned skip:1; /* Operand is not completed if there is a fixup needed 1208 to be done on it. In some (but not all) of these 1209 cases, we need to tell libopcodes to skip the 1210 constraint checking and the encoding for this 1211 operand, so that the libopcodes can pick up the 1212 right opcode before the operand is fixed-up. This 1213 flag should only be used during the 1214 assembling/encoding. */ 1215 unsigned present:1; /* Whether this operand is present in the assembly 1216 line; not used during the disassembly. */ 1217 }; 1218 1219 typedef struct aarch64_opnd_info aarch64_opnd_info; 1220 1221 /* Structure representing an instruction. 1222 1223 It is used during both the assembling and disassembling. The assembler 1224 fills an aarch64_inst after a successful parsing and then passes it to the 1225 encoding routine to do the encoding. During the disassembling, the 1226 disassembler calls the decoding routine to decode a binary instruction; on a 1227 successful return, such a structure will be filled with information of the 1228 instruction; then the disassembler uses the information to print out the 1229 instruction. */ 1230 1231 struct aarch64_inst 1232 { 1233 /* The value of the binary instruction. */ 1234 aarch64_insn value; 1235 1236 /* Corresponding opcode entry. */ 1237 const aarch64_opcode *opcode; 1238 1239 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 1240 const aarch64_cond *cond; 1241 1242 /* Operands information. */ 1243 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 1244 }; 1245 1246 /* Defining the HINT #imm values for the aarch64_hint_options. */ 1247 #define HINT_OPD_CSYNC 0x11 1248 #define HINT_OPD_C 0x22 1249 #define HINT_OPD_J 0x24 1250 #define HINT_OPD_JC 0x26 1251 #define HINT_OPD_NULL 0x00 1252 1253 1254 /* Diagnosis related declaration and interface. */ 1256 1257 /* Operand error kind enumerators. 1258 1259 AARCH64_OPDE_RECOVERABLE 1260 Less severe error found during the parsing, very possibly because that 1261 GAS has picked up a wrong instruction template for the parsing. 1262 1263 AARCH64_OPDE_A_SHOULD_FOLLOW_B 1264 The instruction forms (or is expected to form) part of a sequence, 1265 but the preceding instruction in the sequence wasn't the expected one. 1266 The message refers to two strings: the name of the current instruction, 1267 followed by the name of the expected preceding instruction. 1268 1269 AARCH64_OPDE_EXPECTED_A_AFTER_B 1270 Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus 1271 so that the current instruction is assumed to be the incorrect one: 1272 "since the previous instruction was B, the current one should be A". 1273 1274 AARCH64_OPDE_SYNTAX_ERROR 1275 General syntax error; it can be either a user error, or simply because 1276 that GAS is trying a wrong instruction template. 1277 1278 AARCH64_OPDE_FATAL_SYNTAX_ERROR 1279 Definitely a user syntax error. 1280 1281 AARCH64_OPDE_INVALID_VARIANT 1282 No syntax error, but the operands are not a valid combination, e.g. 1283 FMOV D0,S0 1284 1285 AARCH64_OPDE_UNTIED_IMMS 1286 The asm failed to use the same immediate for a destination operand 1287 and a tied source operand. 1288 1289 AARCH64_OPDE_UNTIED_OPERAND 1290 The asm failed to use the same register for a destination operand 1291 and a tied source operand. 1292 1293 AARCH64_OPDE_OUT_OF_RANGE 1294 Error about some immediate value out of a valid range. 1295 1296 AARCH64_OPDE_UNALIGNED 1297 Error about some immediate value not properly aligned (i.e. not being a 1298 multiple times of a certain value). 1299 1300 AARCH64_OPDE_REG_LIST 1301 Error about the register list operand having unexpected number of 1302 registers. 1303 1304 AARCH64_OPDE_OTHER_ERROR 1305 Error of the highest severity and used for any severe issue that does not 1306 fall into any of the above categories. 1307 1308 AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and 1309 AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the 1310 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 1311 only libopcodes has the information about the valid variants of each 1312 instruction. 1313 1314 The enumerators have an increasing severity. This is helpful when there are 1315 multiple instruction templates available for a given mnemonic name (e.g. 1316 FMOV); this mechanism will help choose the most suitable template from which 1317 the generated diagnostics can most closely describe the issues, if any. */ 1318 1319 enum aarch64_operand_error_kind 1320 { 1321 AARCH64_OPDE_NIL, 1322 AARCH64_OPDE_RECOVERABLE, 1323 AARCH64_OPDE_A_SHOULD_FOLLOW_B, 1324 AARCH64_OPDE_EXPECTED_A_AFTER_B, 1325 AARCH64_OPDE_SYNTAX_ERROR, 1326 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 1327 AARCH64_OPDE_INVALID_VARIANT, 1328 AARCH64_OPDE_UNTIED_IMMS, 1329 AARCH64_OPDE_UNTIED_OPERAND, 1330 AARCH64_OPDE_OUT_OF_RANGE, 1331 AARCH64_OPDE_UNALIGNED, 1332 AARCH64_OPDE_REG_LIST, 1333 AARCH64_OPDE_OTHER_ERROR 1334 }; 1335 1336 /* N.B. GAS assumes that this structure work well with shallow copy. */ 1337 struct aarch64_operand_error 1338 { 1339 enum aarch64_operand_error_kind kind; 1340 int index; 1341 const char *error; 1342 /* Some data for extra information. */ 1343 union { 1344 int i; 1345 const char *s; 1346 } data[3]; 1347 bool non_fatal; 1348 }; 1349 1350 /* AArch64 sequence structure used to track instructions with F_SCAN 1351 dependencies for both assembler and disassembler. */ 1352 struct aarch64_instr_sequence 1353 { 1354 /* The instructions in the sequence, starting with the one that 1355 caused it to be opened. */ 1356 aarch64_inst *instr; 1357 /* The number of instructions already in the sequence. */ 1358 int num_added_insns; 1359 /* The number of instructions allocated to the sequence. */ 1360 int num_allocated_insns; 1361 }; 1362 1363 /* Encoding entrypoint. */ 1364 1365 extern bool 1366 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 1367 aarch64_insn *, aarch64_opnd_qualifier_t *, 1368 aarch64_operand_error *, aarch64_instr_sequence *); 1369 1370 extern const aarch64_opcode * 1371 aarch64_replace_opcode (struct aarch64_inst *, 1372 const aarch64_opcode *); 1373 1374 /* Given the opcode enumerator OP, return the pointer to the corresponding 1375 opcode entry. */ 1376 1377 extern const aarch64_opcode * 1378 aarch64_get_opcode (enum aarch64_op); 1379 1380 /* An instance of this structure is passed to aarch64_print_operand, and 1381 the callback within this structure is used to apply styling to the 1382 disassembler output. This structure encapsulates the callback and a 1383 state pointer. */ 1384 1385 struct aarch64_styler 1386 { 1387 /* The callback used to apply styling. Returns a string created from FMT 1388 and ARGS with STYLE applied to the string. STYLER is a pointer back 1389 to this object so that the callback can access the state member. 1390 1391 The string returned from this callback must remain valid until the 1392 call to aarch64_print_operand has completed. */ 1393 const char *(*apply_style) (struct aarch64_styler *styler, 1394 enum disassembler_style style, 1395 const char *fmt, 1396 va_list args); 1397 1398 /* A pointer to a state object which can be used by the apply_style 1399 callback function. */ 1400 void *state; 1401 }; 1402 1403 /* Generate the string representation of an operand. */ 1404 extern void 1405 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 1406 const aarch64_opnd_info *, int, int *, bfd_vma *, 1407 char **, char *, size_t, 1408 aarch64_feature_set features, 1409 struct aarch64_styler *styler); 1410 1411 /* Miscellaneous interface. */ 1412 1413 extern int 1414 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 1415 1416 extern aarch64_opnd_qualifier_t 1417 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 1418 const aarch64_opnd_qualifier_t, int); 1419 1420 extern bool 1421 aarch64_is_destructive_by_operands (const aarch64_opcode *); 1422 1423 extern int 1424 aarch64_num_of_operands (const aarch64_opcode *); 1425 1426 extern int 1427 aarch64_stack_pointer_p (const aarch64_opnd_info *); 1428 1429 extern int 1430 aarch64_zero_register_p (const aarch64_opnd_info *); 1431 1432 extern enum err_type 1433 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool, 1434 aarch64_operand_error *); 1435 1436 extern void 1437 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *); 1438 1439 /* Given an operand qualifier, return the expected data element size 1440 of a qualified operand. */ 1441 extern unsigned char 1442 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 1443 1444 extern enum aarch64_operand_class 1445 aarch64_get_operand_class (enum aarch64_opnd); 1446 1447 extern const char * 1448 aarch64_get_operand_name (enum aarch64_opnd); 1449 1450 extern const char * 1451 aarch64_get_operand_desc (enum aarch64_opnd); 1452 1453 extern bool 1454 aarch64_sve_dupm_mov_immediate_p (uint64_t, int); 1455 1456 #ifdef DEBUG_AARCH64 1457 extern int debug_dump; 1458 1459 extern void 1460 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 1461 1462 #define DEBUG_TRACE(M, ...) \ 1463 { \ 1464 if (debug_dump) \ 1465 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1466 } 1467 1468 #define DEBUG_TRACE_IF(C, M, ...) \ 1469 { \ 1470 if (debug_dump && (C)) \ 1471 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1472 } 1473 #else /* !DEBUG_AARCH64 */ 1474 #define DEBUG_TRACE(M, ...) ; 1475 #define DEBUG_TRACE_IF(C, M, ...) ; 1476 #endif /* DEBUG_AARCH64 */ 1477 1478 extern const char *const aarch64_sve_pattern_array[32]; 1479 extern const char *const aarch64_sve_prfop_array[16]; 1480 1481 #ifdef __cplusplus 1482 } 1483 #endif 1484 1485 #endif /* OPCODE_AARCH64_H */ 1486
Indexes created Sat Mar 28 00:23:22 UTC 2026