arm-dis.c revision 1.1.1.11
1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2024 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <assert.h> 25 26 #include "disassemble.h" 27 #include "opcode/arm.h" 28 #include "opintl.h" 29 #include "safe-ctype.h" 30 #include "libiberty.h" 31 #include "floatformat.h" 32 33 /* FIXME: This shouldn't be done here. */ 34 #include "coff/internal.h" 35 #include "libcoff.h" 36 #include "bfd.h" 37 #include "elf-bfd.h" 38 #include "elf/internal.h" 39 #include "elf/arm.h" 40 #include "mach-o.h" 41 42 /* Cached mapping symbol state. */ 43 enum map_type 44 { 45 MAP_ARM, 46 MAP_THUMB, 47 MAP_DATA 48 }; 49 50 struct arm_private_data 51 { 52 /* The features to use when disassembling optional instructions. */ 53 arm_feature_set features; 54 55 /* Track the last type (although this doesn't seem to be useful) */ 56 enum map_type last_type; 57 58 /* Tracking symbol table information */ 59 int last_mapping_sym; 60 61 /* The end range of the current range being disassembled. */ 62 bfd_vma last_stop_offset; 63 bfd_vma last_mapping_addr; 64 }; 65 66 enum mve_instructions 67 { 68 MVE_VPST, 69 MVE_VPT_FP_T1, 70 MVE_VPT_FP_T2, 71 MVE_VPT_VEC_T1, 72 MVE_VPT_VEC_T2, 73 MVE_VPT_VEC_T3, 74 MVE_VPT_VEC_T4, 75 MVE_VPT_VEC_T5, 76 MVE_VPT_VEC_T6, 77 MVE_VCMP_FP_T1, 78 MVE_VCMP_FP_T2, 79 MVE_VCMP_VEC_T1, 80 MVE_VCMP_VEC_T2, 81 MVE_VCMP_VEC_T3, 82 MVE_VCMP_VEC_T4, 83 MVE_VCMP_VEC_T5, 84 MVE_VCMP_VEC_T6, 85 MVE_VDUP, 86 MVE_VEOR, 87 MVE_VFMAS_FP_SCALAR, 88 MVE_VFMA_FP_SCALAR, 89 MVE_VFMA_FP, 90 MVE_VFMS_FP, 91 MVE_VHADD_T1, 92 MVE_VHADD_T2, 93 MVE_VHSUB_T1, 94 MVE_VHSUB_T2, 95 MVE_VRHADD, 96 MVE_VLD2, 97 MVE_VLD4, 98 MVE_VST2, 99 MVE_VST4, 100 MVE_VLDRB_T1, 101 MVE_VLDRH_T2, 102 MVE_VLDRB_T5, 103 MVE_VLDRH_T6, 104 MVE_VLDRW_T7, 105 MVE_VSTRB_T1, 106 MVE_VSTRH_T2, 107 MVE_VSTRB_T5, 108 MVE_VSTRH_T6, 109 MVE_VSTRW_T7, 110 MVE_VLDRB_GATHER_T1, 111 MVE_VLDRH_GATHER_T2, 112 MVE_VLDRW_GATHER_T3, 113 MVE_VLDRD_GATHER_T4, 114 MVE_VLDRW_GATHER_T5, 115 MVE_VLDRD_GATHER_T6, 116 MVE_VSTRB_SCATTER_T1, 117 MVE_VSTRH_SCATTER_T2, 118 MVE_VSTRW_SCATTER_T3, 119 MVE_VSTRD_SCATTER_T4, 120 MVE_VSTRW_SCATTER_T5, 121 MVE_VSTRD_SCATTER_T6, 122 MVE_VCVT_FP_FIX_VEC, 123 MVE_VCVT_BETWEEN_FP_INT, 124 MVE_VCVT_FP_HALF_FP, 125 MVE_VCVT_FROM_FP_TO_INT, 126 MVE_VRINT_FP, 127 MVE_VMOV_HFP_TO_GP, 128 MVE_VMOV_GP_TO_VEC_LANE, 129 MVE_VMOV_IMM_TO_VEC, 130 MVE_VMOV_VEC_TO_VEC, 131 MVE_VMOV2_VEC_LANE_TO_GP, 132 MVE_VMOV2_GP_TO_VEC_LANE, 133 MVE_VMOV_VEC_LANE_TO_GP, 134 MVE_VMVN_IMM, 135 MVE_VMVN_REG, 136 MVE_VORR_IMM, 137 MVE_VORR_REG, 138 MVE_VORN, 139 MVE_VBIC_IMM, 140 MVE_VBIC_REG, 141 MVE_VMOVX, 142 MVE_VMOVL, 143 MVE_VMOVN, 144 MVE_VMULL_INT, 145 MVE_VMULL_POLY, 146 MVE_VQDMULL_T1, 147 MVE_VQDMULL_T2, 148 MVE_VQMOVN, 149 MVE_VQMOVUN, 150 MVE_VADDV, 151 MVE_VMLADAV_T1, 152 MVE_VMLADAV_T2, 153 MVE_VMLALDAV, 154 MVE_VMLAS, 155 MVE_VADDLV, 156 MVE_VMLSDAV_T1, 157 MVE_VMLSDAV_T2, 158 MVE_VMLSLDAV, 159 MVE_VRMLALDAVH, 160 MVE_VRMLSLDAVH, 161 MVE_VQDMLADH, 162 MVE_VQRDMLADH, 163 MVE_VQDMLAH, 164 MVE_VQRDMLAH, 165 MVE_VQDMLASH, 166 MVE_VQRDMLASH, 167 MVE_VQDMLSDH, 168 MVE_VQRDMLSDH, 169 MVE_VQDMULH_T1, 170 MVE_VQRDMULH_T2, 171 MVE_VQDMULH_T3, 172 MVE_VQRDMULH_T4, 173 MVE_VDDUP, 174 MVE_VDWDUP, 175 MVE_VIWDUP, 176 MVE_VIDUP, 177 MVE_VCADD_FP, 178 MVE_VCADD_VEC, 179 MVE_VHCADD, 180 MVE_VCMLA_FP, 181 MVE_VCMUL_FP, 182 MVE_VQRSHL_T1, 183 MVE_VQRSHL_T2, 184 MVE_VQRSHRN, 185 MVE_VQRSHRUN, 186 MVE_VQSHL_T1, 187 MVE_VQSHL_T2, 188 MVE_VQSHLU_T3, 189 MVE_VQSHL_T4, 190 MVE_VQSHRN, 191 MVE_VQSHRUN, 192 MVE_VRSHL_T1, 193 MVE_VRSHL_T2, 194 MVE_VRSHR, 195 MVE_VRSHRN, 196 MVE_VSHL_T1, 197 MVE_VSHL_T2, 198 MVE_VSHL_T3, 199 MVE_VSHLC, 200 MVE_VSHLL_T1, 201 MVE_VSHLL_T2, 202 MVE_VSHR, 203 MVE_VSHRN, 204 MVE_VSLI, 205 MVE_VSRI, 206 MVE_VADC, 207 MVE_VABAV, 208 MVE_VABD_FP, 209 MVE_VABD_VEC, 210 MVE_VABS_FP, 211 MVE_VABS_VEC, 212 MVE_VADD_FP_T1, 213 MVE_VADD_FP_T2, 214 MVE_VADD_VEC_T1, 215 MVE_VADD_VEC_T2, 216 MVE_VSBC, 217 MVE_VSUB_FP_T1, 218 MVE_VSUB_FP_T2, 219 MVE_VSUB_VEC_T1, 220 MVE_VSUB_VEC_T2, 221 MVE_VAND, 222 MVE_VBRSR, 223 MVE_VCLS, 224 MVE_VCLZ, 225 MVE_VCTP, 226 MVE_VMAX, 227 MVE_VMAXA, 228 MVE_VMAXNM_FP, 229 MVE_VMAXNMA_FP, 230 MVE_VMAXNMV_FP, 231 MVE_VMAXNMAV_FP, 232 MVE_VMAXV, 233 MVE_VMAXAV, 234 MVE_VMIN, 235 MVE_VMINA, 236 MVE_VMINNM_FP, 237 MVE_VMINNMA_FP, 238 MVE_VMINNMV_FP, 239 MVE_VMINNMAV_FP, 240 MVE_VMINV, 241 MVE_VMINAV, 242 MVE_VMLA, 243 MVE_VMUL_FP_T1, 244 MVE_VMUL_FP_T2, 245 MVE_VMUL_VEC_T1, 246 MVE_VMUL_VEC_T2, 247 MVE_VMULH, 248 MVE_VRMULH, 249 MVE_VNEG_FP, 250 MVE_VNEG_VEC, 251 MVE_VPNOT, 252 MVE_VPSEL, 253 MVE_VQABS, 254 MVE_VQADD_T1, 255 MVE_VQADD_T2, 256 MVE_VQSUB_T1, 257 MVE_VQSUB_T2, 258 MVE_VQNEG, 259 MVE_VREV16, 260 MVE_VREV32, 261 MVE_VREV64, 262 MVE_LSLL, 263 MVE_LSLLI, 264 MVE_LSRL, 265 MVE_ASRL, 266 MVE_ASRLI, 267 MVE_SQRSHRL, 268 MVE_SQRSHR, 269 MVE_UQRSHL, 270 MVE_UQRSHLL, 271 MVE_UQSHL, 272 MVE_UQSHLL, 273 MVE_URSHRL, 274 MVE_URSHR, 275 MVE_SRSHRL, 276 MVE_SRSHR, 277 MVE_SQSHLL, 278 MVE_SQSHL, 279 MVE_CINC, 280 MVE_CINV, 281 MVE_CNEG, 282 MVE_CSINC, 283 MVE_CSINV, 284 MVE_CSET, 285 MVE_CSETM, 286 MVE_CSNEG, 287 MVE_CSEL, 288 MVE_NONE 289 }; 290 291 enum mve_unpredictable 292 { 293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. 294 */ 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and 296 fcB = 1 (vpt). */ 297 UNPRED_R13, /* Unpredictable because r13 (sp) or 298 r15 (sp) used. */ 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ 300 UNPRED_Q_GT_4, /* Unpredictable because 301 vec reg start > 4 (vld4/st4). */ 302 UNPRED_Q_GT_6, /* Unpredictable because 303 vec reg start > 6 (vld2/st2). */ 304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 305 and WB bit = 1. */ 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are 307 equal. */ 308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */ 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the 310 same. */ 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and 312 size = 1. */ 313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and 314 size = 2. */ 315 UNPRED_NONE /* No unpredictable behavior. */ 316 }; 317 318 enum mve_undefined 319 { 320 UNDEF_SIZE, /* undefined size. */ 321 UNDEF_SIZE_0, /* undefined because size == 0. */ 322 UNDEF_SIZE_2, /* undefined because size == 2. */ 323 UNDEF_SIZE_3, /* undefined because size == 3. */ 324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ 327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ 328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and 329 size == 0. */ 330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and 331 size == 1. */ 332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */ 334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and 336 op1 == (0 or 1). */ 337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and 338 op2 == 0 and op1 == (0 or 1). */ 339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode 340 in {0xx1, x0x1}. */ 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ 342 UNDEF_NONE /* no undefined behavior. */ 343 }; 344 345 struct opcode32 346 { 347 arm_feature_set arch; /* Architecture defining this insn. */ 348 unsigned long value; /* If arch is 0 then value is a sentinel. */ 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 350 const char * assembler; /* How to disassemble this insn. */ 351 }; 352 353 struct cdeopcode32 354 { 355 arm_feature_set arch; /* Architecture defining this insn. */ 356 uint8_t coproc_shift; /* coproc is this far into op. */ 357 uint16_t coproc_mask; /* Length of coproc field in op. */ 358 unsigned long value; /* If arch is 0 then value is a sentinel. */ 359 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 360 const char * assembler; /* How to disassemble this insn. */ 361 }; 362 363 /* MVE opcodes. */ 364 365 struct mopcode32 366 { 367 arm_feature_set arch; /* Architecture defining this insn. */ 368 enum mve_instructions mve_op; /* Specific mve instruction for faster 369 decoding. */ 370 unsigned long value; /* If arch is 0 then value is a sentinel. */ 371 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 372 const char * assembler; /* How to disassemble this insn. */ 373 }; 374 375 enum isa { 376 ANY, 377 T32, 378 ARM 379 }; 380 381 382 /* Shared (between Arm and Thumb mode) opcode. */ 383 struct sopcode32 384 { 385 enum isa isa; /* Execution mode instruction availability. */ 386 arm_feature_set arch; /* Architecture defining this insn. */ 387 unsigned long value; /* If arch is 0 then value is a sentinel. */ 388 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 389 const char * assembler; /* How to disassemble this insn. */ 390 }; 391 392 struct opcode16 393 { 394 arm_feature_set arch; /* Architecture defining this insn. */ 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 396 const char *assembler; /* How to disassemble this insn. */ 397 }; 398 399 /* print_insn_coprocessor recognizes the following format control codes: 400 401 %% % 402 403 %c print condition code (always bits 28-31 in ARM mode) 404 %b print condition code allowing cp_num == 9 405 %q print shifter argument 406 %u print condition code (unconditional in ARM mode, 407 UNPREDICTABLE if not AL in Thumb) 408 %A print address for ldc/stc/ldf/stf instruction 409 %B print vstm/vldm register list 410 %C print vscclrm register list 411 %I print cirrus signed shift immediate: bits 0..3|4..6 412 %J print register for VLDR instruction 413 %K print address for VLDR instruction 414 %F print the COUNT field of a LFM/SFM instruction. 415 %P print floating point precision in arithmetic insn 416 %Q print floating point precision in ldf/stf insn 417 %R print floating point rounding mode 418 419 %<bitfield>c print as a condition code (for vsel) 420 %<bitfield>r print as an ARM register 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 422 %<bitfield>ru as %<>r but each u register must be unique. 423 %<bitfield>d print the bitfield in decimal 424 %<bitfield>k print immediate for VFPv3 conversion instruction 425 %<bitfield>x print the bitfield in hex 426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 427 %<bitfield>f print a floating point constant if >7 else a 428 floating point register 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 430 %<bitfield>g print as an iWMMXt 64-bit register 431 %<bitfield>G print as an iWMMXt general purpose or control register 432 %<bitfield>D print as a NEON D register 433 %<bitfield>Q print as a NEON Q register 434 %<bitfield>V print as a NEON D or Q register 435 %<bitfield>E print a quarter-float immediate value 436 437 %y<code> print a single precision VFP reg. 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 439 %z<code> print a double precision VFP reg 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 441 442 %<bitfield>'c print specified char iff bitfield is all ones 443 %<bitfield>`c print specified char iff bitfield is all zeroes 444 %<bitfield>?ab... select from array of values in big endian order 445 446 %L print as an iWMMXt N/M width field. 447 %Z print the Immediate of a WSHUFH instruction. 448 %l like 'A' except use byte offsets for 'B' & 'H' 449 versions. 450 %i print 5-bit immediate in bits 8,3..0 451 (print "32" when 0) 452 %r print register offset address for wldt/wstr instruction. */ 453 454 enum opcode_sentinel_enum 455 { 456 SENTINEL_IWMMXT_START = 1, 457 SENTINEL_IWMMXT_END, 458 SENTINEL_GENERIC_START 459 } opcode_sentinels; 460 461 #define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x" 462 #define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x" 463 #define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x" 464 #define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>" 465 466 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 467 468 /* print_insn_cde recognizes the following format control codes: 469 470 %% % 471 472 %a print 'a' iff bit 28 is 1 473 %p print bits 8-10 as coprocessor 474 %<bitfield>d print as decimal 475 %<bitfield>r print as an ARM register 476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv 477 %<bitfield>T print as an ARM register + 1 478 %<bitfield>R as %r but r13 is UNPREDICTABLE 479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE 480 %j print immediate taken from bits (16..21,7,0..5) 481 %k print immediate taken from bits (20..21,7,0..5). 482 %l print immediate taken from bits (20..22,7,4..5). */ 483 484 /* At the moment there is only one valid position for the coprocessor number, 485 and hence that's encoded in the macro below. */ 486 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ 487 { ARCH, 8, 7, VALUE, MASK, ASM } 488 static const struct cdeopcode32 cde_opcodes[] = 489 { 490 /* Custom Datapath Extension instructions. */ 491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 492 0xee000000, 0xefc00840, 493 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"), 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 495 0xee000040, 0xefc00840, 496 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"), 497 498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 499 0xee400000, 0xefc00840, 500 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"), 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 502 0xee400040, 0xefc00840, 503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"), 504 505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 506 0xee800000, 0xef800840, 507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 509 0xee800040, 0xef800840, 510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), 511 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 513 0xec200000, 0xeeb00840, 514 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"), 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 516 0xec200040, 0xeeb00840, 517 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"), 518 519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 520 0xec300000, 0xeeb00840, 521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"), 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 523 0xec300040, 0xeeb00840, 524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"), 525 526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 527 0xec800000, 0xee800840, 528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"), 529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 530 0xec800040, 0xee800840, 531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"), 532 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) 534 535 }; 536 537 static const struct sopcode32 coprocessor_opcodes[] = 538 { 539 /* XScale instructions. */ 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 541 0x0e200010, 0x0fff0ff0, 542 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"}, 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 544 0x0e280010, 0x0fff0ff0, 545 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"}, 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"}, 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 549 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"}, 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"}, 552 553 /* Intel Wireless MMX technology instructions. */ 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"}, 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"}, 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"}, 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"}, 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"}, 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 628 0x0e800120, 0x0f800ff0, 629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 643 0x0e8000a0, 0x0f800ff0, 644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"}, 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 707 {ANY, ARM_FEATURE_CORE_LOW (0), 708 SENTINEL_IWMMXT_END, 0, "" }, 709 710 /* Floating point coprocessor (FPA) instructions. */ 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 797 798 /* Armv8.1-M Mainline instructions. */ 799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, 801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, 803 804 /* ARMv8-M Mainline Security Extensions instructions. */ 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 809 810 /* Register load/store. */ 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, 845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, 847 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, 856 857 /* Data transfer between ARM and NEON registers. */ 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"}, 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"}, 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"}, 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"}, 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"}, 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"}, 874 /* Half-precision conversion instructions. */ 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 883 884 /* Floating point coprocessor (VFP) instructions. */ 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"}, 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"}, 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 890 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"}, 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"}, 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"}, 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"}, 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"}, 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"}, 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"}, 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"}, 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"}, 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 908 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"}, 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 910 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"}, 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"}, 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"}, 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"}, 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"}, 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"}, 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"}, 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"}, 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"}, 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"}, 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"}, 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"}, 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"}, 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"}, 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"}, 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"}, 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"}, 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"}, 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"}, 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"}, 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"}, 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"}, 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"}, 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"}, 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 1043 1044 /* VFP Fused multiply add instructions. */ 1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1046 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1048 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 1049 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1050 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 1051 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1052 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 1053 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1054 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 1055 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1056 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 1057 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1058 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 1059 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1060 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 1061 1062 /* FP v5. */ 1063 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1064 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 1065 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1066 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 1067 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1068 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 1069 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1070 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 1071 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1072 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 1073 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1074 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 1075 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1076 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 1077 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1078 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 1079 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1080 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 1081 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1082 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 1083 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1084 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 1085 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1086 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 1087 1088 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 1089 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 1090 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1091 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, 1092 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1093 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, 1094 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1095 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, 1096 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1097 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, 1098 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1099 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, 1100 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1101 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, 1102 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1103 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"}, 1104 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1105 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"}, 1106 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1107 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"}, 1108 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1109 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"}, 1110 1111 /* BFloat16 instructions. */ 1112 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1113 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, 1114 1115 /* Dot Product instructions in the space of coprocessor 13. */ 1116 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1117 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 1118 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1119 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"}, 1120 1121 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 1122 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1123 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, 1124 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1125 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, 1126 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1127 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, 1128 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1129 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, 1130 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1131 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, 1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1133 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, 1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1135 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, 1136 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1137 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, 1138 1139 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 1140 cp_num: bit <11:8> == 0b1001. 1141 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 1142 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1143 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 1144 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1145 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1147 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1149 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"}, 1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1151 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, 1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1153 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"}, 1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1155 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1157 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1159 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1161 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1163 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1165 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1167 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1169 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1171 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1173 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1175 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1177 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1179 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1181 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1183 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1185 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1187 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1189 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1191 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"}, 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1193 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1195 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1197 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1199 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1201 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1203 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1205 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1207 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1209 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1211 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1212 1213 /* ARMv8.3 javascript conversion instruction. */ 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1215 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1216 1217 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1218 }; 1219 1220 /* Generic coprocessor instructions. These are only matched if a more specific 1221 SIMD or co-processor instruction does not match first. */ 1222 1223 static const struct sopcode32 generic_coprocessor_opcodes[] = 1224 { 1225 /* Generic coprocessor instructions. */ 1226 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1227 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"}, 1228 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1229 0x0c500000, 0x0ff00000, 1230 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, 1231 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1232 0x0e000000, 0x0f000010, 1233 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1234 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1235 0x0e10f010, 0x0f10f010, 1236 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1237 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1238 0x0e100010, 0x0f100010, 1239 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1240 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1241 0x0e000010, 0x0f100010, 1242 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1243 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1244 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1245 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1246 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1247 1248 /* V6 coprocessor instructions. */ 1249 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1250 0xfc500000, 0xfff00000, 1251 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, 1252 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1253 0xfc400000, 0xfff00000, 1254 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"}, 1255 1256 /* V5 coprocessor instructions. */ 1257 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1258 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1259 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1260 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1261 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1262 0xfe000000, 0xff000010, 1263 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1264 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1265 0xfe000010, 0xff100010, 1266 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1267 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1268 0xfe100010, 0xff100010, 1269 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1270 1271 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1272 }; 1273 1274 /* Neon opcode table: This does not encode the top byte -- that is 1275 checked by the print_insn_neon routine, as it depends on whether we are 1276 doing thumb32 or arm32 disassembly. */ 1277 1278 /* print_insn_neon recognizes the following format control codes: 1279 1280 %% % 1281 1282 %c print condition code 1283 %u print condition code (unconditional in ARM mode, 1284 UNPREDICTABLE if not AL in Thumb) 1285 %A print v{st,ld}[1234] operands 1286 %B print v{st,ld}[1234] any one operands 1287 %C print v{st,ld}[1234] single->all operands 1288 %D print scalar 1289 %E print vmov, vmvn, vorr, vbic encoded constant 1290 %F print vtbl,vtbx register list 1291 1292 %<bitfield>r print as an ARM register 1293 %<bitfield>d print the bitfield in decimal 1294 %<bitfield>e print the 2^N - bitfield in decimal 1295 %<bitfield>D print as a NEON D register 1296 %<bitfield>Q print as a NEON Q register 1297 %<bitfield>R print as a NEON D or Q register 1298 %<bitfield>Sn print byte scaled width limited by n 1299 %<bitfield>Tn print short scaled width limited by n 1300 %<bitfield>Un print long scaled width limited by n 1301 1302 %<bitfield>'c print specified char iff bitfield is all ones 1303 %<bitfield>`c print specified char iff bitfield is all zeroes 1304 %<bitfield>?ab... select from array of values in big endian order. */ 1305 1306 static const struct opcode32 neon_opcodes[] = 1307 { 1308 /* Extract. */ 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1310 0xf2b00840, 0xffb00850, 1311 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, 1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1313 0xf2b00000, 0xffb00810, 1314 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, 1315 1316 /* Data transfer between ARM and NEON registers. */ 1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1318 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1320 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1322 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1324 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1326 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1328 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 1329 1330 /* Move data element to all lanes. */ 1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1332 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"}, 1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1334 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"}, 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1336 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"}, 1337 1338 /* Table lookup. */ 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1340 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1342 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1343 1344 /* Half-precision conversions. */ 1345 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1346 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1347 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1348 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1349 1350 /* NEON fused multiply add instructions. */ 1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1352 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1354 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1356 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1358 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1359 1360 /* BFloat16 instructions. */ 1361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1362 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1364 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1366 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1368 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, 1369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1370 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1372 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"}, 1373 1374 /* Matrix Multiply instructions. */ 1375 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1376 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1378 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1380 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1382 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1384 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1386 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1387 1388 /* Two registers, miscellaneous. */ 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1390 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1392 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1394 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1396 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1397 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1398 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1399 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1400 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1401 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1402 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1403 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1404 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1405 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1406 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1407 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1408 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1409 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1410 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1412 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1414 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1416 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1418 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1420 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1422 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1424 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1426 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1428 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1430 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1432 0xf3b20300, 0xffb30fd0, 1433 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"}, 1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1435 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1436 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1437 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1439 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1441 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1443 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1445 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1447 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1449 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1451 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1453 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1455 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1457 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1459 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1461 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1463 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1465 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1467 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1469 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1471 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1473 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1475 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1477 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1479 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1481 0xf3bb0600, 0xffbf0e10, 1482 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1484 0xf3b70600, 0xffbf0e10, 1485 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1486 1487 /* Three registers of the same length. */ 1488 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1489 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1490 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1491 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1492 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1493 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1494 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1495 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1496 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1497 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1498 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1499 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1500 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1501 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1503 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1505 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1507 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1509 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1511 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1517 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1519 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1521 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1523 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1525 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1527 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1529 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1531 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1533 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1535 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1537 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1539 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1541 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1543 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1545 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1547 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1549 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1551 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1553 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1557 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1559 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1561 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1563 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1565 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1569 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1571 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1573 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1575 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1577 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1579 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1581 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1583 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1585 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1587 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1589 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1592 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1593 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1595 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1597 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1599 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1601 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1603 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf2000b00, 0xff800f10, 1606 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1608 0xf2000b10, 0xff800f10, 1609 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1613 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1615 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1617 0xf3000b00, 0xff800f10, 1618 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1620 0xf2000000, 0xfe800f10, 1621 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf2000010, 0xfe800f10, 1624 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1626 0xf2000100, 0xfe800f10, 1627 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1629 0xf2000200, 0xfe800f10, 1630 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1632 0xf2000210, 0xfe800f10, 1633 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1635 0xf2000300, 0xfe800f10, 1636 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1638 0xf2000310, 0xfe800f10, 1639 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1641 0xf2000400, 0xfe800f10, 1642 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1644 0xf2000410, 0xfe800f10, 1645 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1647 0xf2000500, 0xfe800f10, 1648 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1650 0xf2000510, 0xfe800f10, 1651 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1653 0xf2000600, 0xfe800f10, 1654 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1656 0xf2000610, 0xfe800f10, 1657 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1659 0xf2000700, 0xfe800f10, 1660 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1662 0xf2000710, 0xfe800f10, 1663 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1665 0xf2000910, 0xfe800f10, 1666 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1668 0xf2000a00, 0xfe800f10, 1669 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1671 0xf2000a10, 0xfe800f10, 1672 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1674 0xf3000b10, 0xff800f10, 1675 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1677 0xf3000c10, 0xff800f10, 1678 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1679 1680 /* One register and an immediate value. */ 1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1682 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1684 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1686 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1688 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1690 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1692 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1694 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1696 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1698 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1700 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1702 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1704 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1706 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1707 1708 /* Two registers and a shift amount. */ 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1710 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1712 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1714 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1716 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1718 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1720 0xf2880950, 0xfeb80fd0, 1721 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1723 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"}, 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1725 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1727 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1729 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1731 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1733 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1735 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1737 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1739 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1741 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1743 0xf2900950, 0xfeb00fd0, 1744 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1746 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"}, 1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1748 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1750 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1752 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1754 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1756 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1758 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1759 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1760 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1762 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1764 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1766 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1768 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1770 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"}, 1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1772 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1774 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1776 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1778 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1780 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1782 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1784 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1786 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1788 0xf2a00950, 0xfea00fd0, 1789 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1791 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1793 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1795 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1797 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1799 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1801 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1803 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1805 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1807 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1809 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1811 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1813 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1815 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1817 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1819 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1821 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1823 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1825 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1827 0xf2a00e10, 0xfea00e90, 1828 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1830 0xf2a00c10, 0xfea00e90, 1831 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1832 1833 /* Three registers of different lengths. */ 1834 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1835 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1837 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1839 0xf2800400, 0xff800f50, 1840 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1842 0xf2800600, 0xff800f50, 1843 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1845 0xf2800900, 0xff800f50, 1846 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1848 0xf2800b00, 0xff800f50, 1849 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1851 0xf2800d00, 0xff800f50, 1852 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1854 0xf3800400, 0xff800f50, 1855 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1857 0xf3800600, 0xff800f50, 1858 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1860 0xf2800000, 0xfe800f50, 1861 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1863 0xf2800100, 0xfe800f50, 1864 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1866 0xf2800200, 0xfe800f50, 1867 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1869 0xf2800300, 0xfe800f50, 1870 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1872 0xf2800500, 0xfe800f50, 1873 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1875 0xf2800700, 0xfe800f50, 1876 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1878 0xf2800800, 0xfe800f50, 1879 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1881 0xf2800a00, 0xfe800f50, 1882 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1884 0xf2800c00, 0xfe800f50, 1885 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1886 1887 /* Two registers and a scalar. */ 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1889 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1891 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1892 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1893 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1895 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1897 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1899 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1900 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1901 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1903 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1905 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1907 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1908 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1909 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1911 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1913 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1915 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1917 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1919 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1920 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1921 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1923 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1925 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1926 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1927 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1929 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1931 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1932 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1933 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1935 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1937 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1939 0xf2800240, 0xfe800f50, 1940 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1942 0xf2800640, 0xfe800f50, 1943 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1945 0xf2800a40, 0xfe800f50, 1946 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1948 0xf2800e40, 0xff800f50, 1949 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1951 0xf2800f40, 0xff800f50, 1952 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1954 0xf3800e40, 0xff800f50, 1955 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1957 0xf3800f40, 0xff800f50, 1958 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1959 }, 1960 1961 /* Element and structure load/store. */ 1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1963 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1965 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1967 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1969 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1971 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1973 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1975 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1977 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1979 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1981 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1983 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1985 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1987 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1989 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1991 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1993 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1995 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1997 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1999 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 2000 2001 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 2002 }; 2003 2004 /* mve opcode table. */ 2005 2006 /* print_insn_mve recognizes the following format control codes: 2007 2008 %% % 2009 2010 %a print '+' or '-' or imm offset in vldr[bhwd] and 2011 vstr[bhwd] 2012 %c print condition code 2013 %d print addr mode of MVE vldr[bhw] and vstr[bhw] 2014 %u print 'U' (unsigned) or 'S' for various mve instructions 2015 %i print MVE predicate(s) for vpt and vpst 2016 %j print a 5-bit immediate from hw2[14:12,7:6] 2017 %k print 48 if the 7th position bit is set else print 64. 2018 %m print rounding mode for vcvt and vrint 2019 %n print vector comparison code for predicated instruction 2020 %s print size for various vcvt instructions 2021 %v print vector predicate for instruction in predicated 2022 block 2023 %o print offset scaled for vldr[hwd] and vstr[hwd] 2024 %w print writeback mode for MVE v{st,ld}[24] 2025 %B print v{st,ld}[24] any one operands 2026 %E print vmov, vmvn, vorr, vbic encoded constant 2027 %N print generic index for vmov 2028 %T print bottom ('b') or top ('t') of source register 2029 %X print exchange field in vmla* instructions 2030 2031 %<bitfield>r print as an ARM register 2032 %<bitfield>d print the bitfield in decimal 2033 %<bitfield>A print accumulate or not 2034 %<bitfield>c print bitfield as a condition code 2035 %<bitfield>C print bitfield as an inverted condition code 2036 %<bitfield>Q print as a MVE Q register 2037 %<bitfield>F print as a MVE S register 2038 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is 2039 UNPREDICTABLE 2040 2041 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE 2042 %<bitfield>s print size for vector predicate & non VMOV instructions 2043 %<bitfield>I print carry flag or not 2044 %<bitfield>i print immediate for vstr/vldr reg +/- imm 2045 %<bitfield>h print high half of 64-bit destination reg 2046 %<bitfield>k print immediate for vector conversion instruction 2047 %<bitfield>l print low half of 64-bit destination reg 2048 %<bitfield>o print rotate value for vcmul 2049 %<bitfield>u print immediate value for vddup/vdwdup 2050 %<bitfield>x print the bitfield in hex. 2051 */ 2052 2053 static const struct mopcode32 mve_opcodes[] = 2054 { 2055 /* MVE. */ 2056 2057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2058 MVE_VPST, 2059 0xfe310f4d, 0xffbf1fff, 2060 "vpst%i" 2061 }, 2062 2063 /* Floating point VPT T1. */ 2064 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2065 MVE_VPT_FP_T1, 2066 0xee310f00, 0xefb10f50, 2067 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2068 /* Floating point VPT T2. */ 2069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2070 MVE_VPT_FP_T2, 2071 0xee310f40, 0xefb10f50, 2072 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, 2073 2074 /* Vector VPT T1. */ 2075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2076 MVE_VPT_VEC_T1, 2077 0xfe010f00, 0xff811f51, 2078 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2079 /* Vector VPT T2. */ 2080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2081 MVE_VPT_VEC_T2, 2082 0xfe010f01, 0xff811f51, 2083 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2084 /* Vector VPT T3. */ 2085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2086 MVE_VPT_VEC_T3, 2087 0xfe011f00, 0xff811f50, 2088 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2089 /* Vector VPT T4. */ 2090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2091 MVE_VPT_VEC_T4, 2092 0xfe010f40, 0xff811f70, 2093 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2094 /* Vector VPT T5. */ 2095 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2096 MVE_VPT_VEC_T5, 2097 0xfe010f60, 0xff811f70, 2098 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2099 /* Vector VPT T6. */ 2100 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2101 MVE_VPT_VEC_T6, 2102 0xfe011f40, 0xff811f50, 2103 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2104 2105 /* Vector VBIC immediate. */ 2106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2107 MVE_VBIC_IMM, 2108 0xef800070, 0xefb81070, 2109 "vbic%v.i%8-11s\t%13-15,22Q, %E"}, 2110 2111 /* Vector VBIC register. */ 2112 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2113 MVE_VBIC_REG, 2114 0xef100150, 0xffb11f51, 2115 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2116 2117 /* Vector VABAV. */ 2118 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2119 MVE_VABAV, 2120 0xee800f01, 0xefc10f51, 2121 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, 2122 2123 /* Vector VABD floating point. */ 2124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2125 MVE_VABD_FP, 2126 0xff200d40, 0xffa11f51, 2127 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2128 2129 /* Vector VABD. */ 2130 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2131 MVE_VABD_VEC, 2132 0xef000740, 0xef811f51, 2133 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2134 2135 /* Vector VABS floating point. */ 2136 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2137 MVE_VABS_FP, 2138 0xFFB10740, 0xFFB31FD1, 2139 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2140 /* Vector VABS. */ 2141 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2142 MVE_VABS_VEC, 2143 0xffb10340, 0xffb31fd1, 2144 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2145 2146 /* Vector VADD floating point T1. */ 2147 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2148 MVE_VADD_FP_T1, 2149 0xef000d40, 0xffa11f51, 2150 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2151 /* Vector VADD floating point T2. */ 2152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2153 MVE_VADD_FP_T2, 2154 0xee300f40, 0xefb11f70, 2155 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2156 /* Vector VADD T1. */ 2157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2158 MVE_VADD_VEC_T1, 2159 0xef000840, 0xff811f51, 2160 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2161 /* Vector VADD T2. */ 2162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2163 MVE_VADD_VEC_T2, 2164 0xee010f40, 0xff811f70, 2165 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2166 2167 /* Vector VADDLV. */ 2168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2169 MVE_VADDLV, 2170 0xee890f00, 0xef8f1fd1, 2171 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, 2172 2173 /* Vector VADDV. */ 2174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2175 MVE_VADDV, 2176 0xeef10f00, 0xeff31fd1, 2177 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, 2178 2179 /* Vector VADC. */ 2180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2181 MVE_VADC, 2182 0xee300f00, 0xffb10f51, 2183 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2184 2185 /* Vector VAND. */ 2186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2187 MVE_VAND, 2188 0xef000150, 0xffb11f51, 2189 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2190 2191 /* Vector VBRSR register. */ 2192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2193 MVE_VBRSR, 2194 0xfe011e60, 0xff811f70, 2195 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2196 2197 /* Vector VCADD floating point. */ 2198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2199 MVE_VCADD_FP, 2200 0xfc800840, 0xfea11f51, 2201 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"}, 2202 2203 /* Vector VCADD. */ 2204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2205 MVE_VCADD_VEC, 2206 0xfe000f00, 0xff810f51, 2207 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, 2208 2209 /* Vector VCLS. */ 2210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2211 MVE_VCLS, 2212 0xffb00440, 0xffb31fd1, 2213 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2214 2215 /* Vector VCLZ. */ 2216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2217 MVE_VCLZ, 2218 0xffb004c0, 0xffb31fd1, 2219 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2220 2221 /* Vector VCMLA. */ 2222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2223 MVE_VCMLA_FP, 2224 0xfc200840, 0xfe211f51, 2225 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"}, 2226 2227 /* Vector VCMP floating point T1. */ 2228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2229 MVE_VCMP_FP_T1, 2230 0xee310f00, 0xeff1ef50, 2231 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2232 2233 /* Vector VCMP floating point T2. */ 2234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2235 MVE_VCMP_FP_T2, 2236 0xee310f40, 0xeff1ef50, 2237 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, 2238 2239 /* Vector VCMP T1. */ 2240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2241 MVE_VCMP_VEC_T1, 2242 0xfe010f00, 0xffc1ff51, 2243 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2244 /* Vector VCMP T2. */ 2245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2246 MVE_VCMP_VEC_T2, 2247 0xfe010f01, 0xffc1ff51, 2248 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2249 /* Vector VCMP T3. */ 2250 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2251 MVE_VCMP_VEC_T3, 2252 0xfe011f00, 0xffc1ff50, 2253 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2254 /* Vector VCMP T4. */ 2255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2256 MVE_VCMP_VEC_T4, 2257 0xfe010f40, 0xffc1ff70, 2258 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2259 /* Vector VCMP T5. */ 2260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2261 MVE_VCMP_VEC_T5, 2262 0xfe010f60, 0xffc1ff70, 2263 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2264 /* Vector VCMP T6. */ 2265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2266 MVE_VCMP_VEC_T6, 2267 0xfe011f40, 0xffc1ff50, 2268 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2269 2270 /* Vector VDUP. */ 2271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2272 MVE_VDUP, 2273 0xeea00b10, 0xffb10f5f, 2274 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2275 2276 /* Vector VEOR. */ 2277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2278 MVE_VEOR, 2279 0xff000150, 0xffd11f51, 2280 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2281 2282 /* Vector VFMA, vector * scalar. */ 2283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2284 MVE_VFMA_FP_SCALAR, 2285 0xee310e40, 0xefb11f70, 2286 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2287 2288 /* Vector VFMA floating point. */ 2289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2290 MVE_VFMA_FP, 2291 0xef000c50, 0xffa11f51, 2292 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2293 2294 /* Vector VFMS floating point. */ 2295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2296 MVE_VFMS_FP, 2297 0xef200c50, 0xffa11f51, 2298 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2299 2300 /* Vector VFMAS, vector * scalar. */ 2301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2302 MVE_VFMAS_FP_SCALAR, 2303 0xee311e40, 0xefb11f70, 2304 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2305 2306 /* Vector VHADD T1. */ 2307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2308 MVE_VHADD_T1, 2309 0xef000040, 0xef811f51, 2310 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2311 2312 /* Vector VHADD T2. */ 2313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2314 MVE_VHADD_T2, 2315 0xee000f40, 0xef811f70, 2316 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2317 2318 /* Vector VHSUB T1. */ 2319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2320 MVE_VHSUB_T1, 2321 0xef000240, 0xef811f51, 2322 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2323 2324 /* Vector VHSUB T2. */ 2325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2326 MVE_VHSUB_T2, 2327 0xee001f40, 0xef811f70, 2328 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2329 2330 /* Vector VCMUL. */ 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2332 MVE_VCMUL_FP, 2333 0xee300e00, 0xefb10f50, 2334 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"}, 2335 2336 /* Vector VCTP. */ 2337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2338 MVE_VCTP, 2339 0xf000e801, 0xffc0ffff, 2340 "vctp%v.%20-21s\t%16-19r"}, 2341 2342 /* Vector VDUP. */ 2343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2344 MVE_VDUP, 2345 0xeea00b10, 0xffb10f5f, 2346 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2347 2348 /* Vector VRHADD. */ 2349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2350 MVE_VRHADD, 2351 0xef000140, 0xef811f51, 2352 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2353 2354 /* Vector VCVT. */ 2355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2356 MVE_VCVT_FP_FIX_VEC, 2357 0xef800c50, 0xef801cd1, 2358 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"}, 2359 2360 /* Vector VCVT. */ 2361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2362 MVE_VCVT_BETWEEN_FP_INT, 2363 0xffb30640, 0xffb31e51, 2364 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2365 2366 /* Vector VCVT between single and half-precision float, bottom half. */ 2367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2368 MVE_VCVT_FP_HALF_FP, 2369 0xee3f0e01, 0xefbf1fd1, 2370 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, 2371 2372 /* Vector VCVT between single and half-precision float, top half. */ 2373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2374 MVE_VCVT_FP_HALF_FP, 2375 0xee3f1e01, 0xefbf1fd1, 2376 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2377 2378 /* Vector VCVT. */ 2379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2380 MVE_VCVT_FROM_FP_TO_INT, 2381 0xffb30040, 0xffb31c51, 2382 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, 2383 2384 /* Vector VDDUP. */ 2385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2386 MVE_VDDUP, 2387 0xee011f6e, 0xff811f7e, 2388 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, 2389 2390 /* Vector VDWDUP. */ 2391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2392 MVE_VDWDUP, 2393 0xee011f60, 0xff811f70, 2394 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, 2395 2396 /* Vector VHCADD. */ 2397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2398 MVE_VHCADD, 2399 0xee000f00, 0xff810f51, 2400 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, 2401 2402 /* Vector VIWDUP. */ 2403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2404 MVE_VIWDUP, 2405 0xee010f60, 0xff811f70, 2406 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, 2407 2408 /* Vector VIDUP. */ 2409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2410 MVE_VIDUP, 2411 0xee010f6e, 0xff811f7e, 2412 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, 2413 2414 /* Vector VLD2. */ 2415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2416 MVE_VLD2, 2417 0xfc901e00, 0xff901e5f, 2418 "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, 2419 2420 /* Vector VLD4. */ 2421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2422 MVE_VLD4, 2423 0xfc901e01, 0xff901e1f, 2424 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, 2425 2426 /* Vector VLDRB gather load. */ 2427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2428 MVE_VLDRB_GATHER_T1, 2429 0xec900e00, 0xefb01e50, 2430 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 2431 2432 /* Vector VLDRH gather load. */ 2433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2434 MVE_VLDRH_GATHER_T2, 2435 0xec900e10, 0xefb01e50, 2436 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2437 2438 /* Vector VLDRW gather load. */ 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2440 MVE_VLDRW_GATHER_T3, 2441 0xfc900f40, 0xffb01fd0, 2442 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2443 2444 /* Vector VLDRD gather load. */ 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2446 MVE_VLDRD_GATHER_T4, 2447 0xec900fd0, 0xefb01fd0, 2448 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2449 2450 /* Vector VLDRW gather load. */ 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2452 MVE_VLDRW_GATHER_T5, 2453 0xfd101e00, 0xff111f00, 2454 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 2455 2456 /* Vector VLDRD gather load, variant T6. */ 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2458 MVE_VLDRD_GATHER_T6, 2459 0xfd101f00, 0xff111f00, 2460 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 2461 2462 /* Vector VLDRB. */ 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2464 MVE_VLDRB_T1, 2465 0xec100e00, 0xee581e00, 2466 "vldrb%v.%u%7-8s\t%13-15Q, %d"}, 2467 2468 /* Vector VLDRH. */ 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2470 MVE_VLDRH_T2, 2471 0xec180e00, 0xee581e00, 2472 "vldrh%v.%u%7-8s\t%13-15Q, %d"}, 2473 2474 /* Vector VLDRB unsigned, variant T5. */ 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2476 MVE_VLDRB_T5, 2477 0xec101e00, 0xfe101f80, 2478 "vldrb%v.u8\t%13-15,22Q, %d"}, 2479 2480 /* Vector VLDRH unsigned, variant T6. */ 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2482 MVE_VLDRH_T6, 2483 0xec101e80, 0xfe101f80, 2484 "vldrh%v.u16\t%13-15,22Q, %d"}, 2485 2486 /* Vector VLDRW unsigned, variant T7. */ 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2488 MVE_VLDRW_T7, 2489 0xec101f00, 0xfe101f80, 2490 "vldrw%v.u32\t%13-15,22Q, %d"}, 2491 2492 /* Vector VMAX. */ 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2494 MVE_VMAX, 2495 0xef000640, 0xef811f51, 2496 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2497 2498 /* Vector VMAXA. */ 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2500 MVE_VMAXA, 2501 0xee330e81, 0xffb31fd1, 2502 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2503 2504 /* Vector VMAXNM floating point. */ 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2506 MVE_VMAXNM_FP, 2507 0xff000f50, 0xffa11f51, 2508 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2509 2510 /* Vector VMAXNMA floating point. */ 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2512 MVE_VMAXNMA_FP, 2513 0xee3f0e81, 0xefbf1fd1, 2514 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2515 2516 /* Vector VMAXNMV floating point. */ 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2518 MVE_VMAXNMV_FP, 2519 0xeeee0f00, 0xefff0fd1, 2520 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2521 2522 /* Vector VMAXNMAV floating point. */ 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2524 MVE_VMAXNMAV_FP, 2525 0xeeec0f00, 0xefff0fd1, 2526 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2527 2528 /* Vector VMAXV. */ 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2530 MVE_VMAXV, 2531 0xeee20f00, 0xeff30fd1, 2532 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2533 2534 /* Vector VMAXAV. */ 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2536 MVE_VMAXAV, 2537 0xeee00f00, 0xfff30fd1, 2538 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2539 2540 /* Vector VMIN. */ 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2542 MVE_VMIN, 2543 0xef000650, 0xef811f51, 2544 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2545 2546 /* Vector VMINA. */ 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2548 MVE_VMINA, 2549 0xee331e81, 0xffb31fd1, 2550 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2551 2552 /* Vector VMINNM floating point. */ 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2554 MVE_VMINNM_FP, 2555 0xff200f50, 0xffa11f51, 2556 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2557 2558 /* Vector VMINNMA floating point. */ 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2560 MVE_VMINNMA_FP, 2561 0xee3f1e81, 0xefbf1fd1, 2562 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2563 2564 /* Vector VMINNMV floating point. */ 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2566 MVE_VMINNMV_FP, 2567 0xeeee0f80, 0xefff0fd1, 2568 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2569 2570 /* Vector VMINNMAV floating point. */ 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2572 MVE_VMINNMAV_FP, 2573 0xeeec0f80, 0xefff0fd1, 2574 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2575 2576 /* Vector VMINV. */ 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2578 MVE_VMINV, 2579 0xeee20f80, 0xeff30fd1, 2580 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2581 2582 /* Vector VMINAV. */ 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2584 MVE_VMINAV, 2585 0xeee00f80, 0xfff30fd1, 2586 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2587 2588 /* Vector VMLA. */ 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2590 MVE_VMLA, 2591 0xee010e40, 0xef811f70, 2592 "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2593 2594 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction 2595 opcode aliasing. */ 2596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2597 MVE_VMLALDAV, 2598 0xee801e00, 0xef801f51, 2599 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2600 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2602 MVE_VMLALDAV, 2603 0xee800e00, 0xef801f51, 2604 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2605 2606 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2608 MVE_VMLADAV_T1, 2609 0xeef00e00, 0xeff01f51, 2610 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2611 2612 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2614 MVE_VMLADAV_T2, 2615 0xeef00f00, 0xeff11f51, 2616 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2617 2618 /* Vector VMLADAV T1 variant. */ 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2620 MVE_VMLADAV_T1, 2621 0xeef01e00, 0xeff01f51, 2622 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2623 2624 /* Vector VMLADAV T2 variant. */ 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2626 MVE_VMLADAV_T2, 2627 0xeef01f00, 0xeff11f51, 2628 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2629 2630 /* Vector VMLAS. */ 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2632 MVE_VMLAS, 2633 0xee011e40, 0xef811f70, 2634 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2635 2636 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction 2637 opcode aliasing. */ 2638 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2639 MVE_VRMLSLDAVH, 2640 0xfe800e01, 0xff810f51, 2641 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2642 2643 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction 2644 opcdoe aliasing. */ 2645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2646 MVE_VMLSLDAV, 2647 0xee800e01, 0xff800f51, 2648 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2649 2650 /* Vector VMLSDAV T1 Variant. */ 2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2652 MVE_VMLSDAV_T1, 2653 0xeef00e01, 0xfff00f51, 2654 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2655 2656 /* Vector VMLSDAV T2 Variant. */ 2657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2658 MVE_VMLSDAV_T2, 2659 0xfef00e01, 0xfff10f51, 2660 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, 2661 2662 /* Vector VMOV between gpr and half precision register, op == 0. */ 2663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2664 MVE_VMOV_HFP_TO_GP, 2665 0xee000910, 0xfff00f7f, 2666 "vmov.f16\t%7,16-19F, %12-15r"}, 2667 2668 /* Vector VMOV between gpr and half precision register, op == 1. */ 2669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2670 MVE_VMOV_HFP_TO_GP, 2671 0xee100910, 0xfff00f7f, 2672 "vmov.f16\t%12-15r, %7,16-19F"}, 2673 2674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2675 MVE_VMOV_GP_TO_VEC_LANE, 2676 0xee000b10, 0xff900f1f, 2677 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"}, 2678 2679 /* Vector VORR immediate to vector. 2680 NOTE: MVE_VORR_IMM must appear in the table 2681 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2683 MVE_VORR_IMM, 2684 0xef800050, 0xefb810f0, 2685 "vorr%v.i%8-11s\t%13-15,22Q, %E"}, 2686 2687 /* Vector VQSHL T2 Variant. 2688 NOTE: MVE_VQSHL_T2 must appear in the table before 2689 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2691 MVE_VQSHL_T2, 2692 0xef800750, 0xef801fd1, 2693 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2694 2695 /* Vector VQSHLU T3 Variant 2696 NOTE: MVE_VQSHL_T2 must appear in the table before 2697 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2698 2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2700 MVE_VQSHLU_T3, 2701 0xff800650, 0xff801fd1, 2702 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2703 2704 /* Vector VRSHR 2705 NOTE: MVE_VRSHR must appear in the table before 2706 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2708 MVE_VRSHR, 2709 0xef800250, 0xef801fd1, 2710 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2711 2712 /* Vector VSHL. 2713 NOTE: MVE_VSHL must appear in the table before 2714 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2716 MVE_VSHL_T1, 2717 0xef800550, 0xff801fd1, 2718 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2719 2720 /* Vector VSHR 2721 NOTE: MVE_VSHR must appear in the table before 2722 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2724 MVE_VSHR, 2725 0xef800050, 0xef801fd1, 2726 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2727 2728 /* Vector VSLI 2729 NOTE: MVE_VSLI must appear in the table before 2730 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2732 MVE_VSLI, 2733 0xff800550, 0xff801fd1, 2734 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2735 2736 /* Vector VSRI 2737 NOTE: MVE_VSRI must appear in the table before 2738 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2740 MVE_VSRI, 2741 0xff800450, 0xff801fd1, 2742 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2743 2744 /* Vector VMOV immediate to vector, 2745 undefinded for cmode == 1111 */ 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2747 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, 2748 2749 /* Vector VMOV immediate to vector, 2750 cmode == 1101 */ 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2752 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, 2753 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2754 2755 /* Vector VMOV immediate to vector. */ 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2757 MVE_VMOV_IMM_TO_VEC, 2758 0xef800050, 0xefb810d0, 2759 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2760 2761 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2763 MVE_VMOV2_VEC_LANE_TO_GP, 2764 0xec000f00, 0xffb01ff0, 2765 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"}, 2766 2767 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ 2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2769 MVE_VMOV2_VEC_LANE_TO_GP, 2770 0xec000f10, 0xffb01ff0, 2771 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"}, 2772 2773 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ 2774 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2775 MVE_VMOV2_GP_TO_VEC_LANE, 2776 0xec100f00, 0xffb01ff0, 2777 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"}, 2778 2779 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2781 MVE_VMOV2_GP_TO_VEC_LANE, 2782 0xec100f10, 0xffb01ff0, 2783 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"}, 2784 2785 /* Vector VMOV Vector lane to gpr. */ 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2787 MVE_VMOV_VEC_LANE_TO_GP, 2788 0xee100b10, 0xff100f1f, 2789 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"}, 2790 2791 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due 2792 to instruction opcode aliasing. */ 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2794 MVE_VSHLL_T1, 2795 0xeea00f40, 0xefa00fd1, 2796 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2797 2798 /* Vector VMOVL long. */ 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2800 MVE_VMOVL, 2801 0xeea00f40, 0xefa70fd1, 2802 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, 2803 2804 /* Vector VMOV and narrow. */ 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2806 MVE_VMOVN, 2807 0xfe310e81, 0xffb30fd1, 2808 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2809 2810 /* Floating point move extract. */ 2811 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2812 MVE_VMOVX, 2813 0xfeb00a40, 0xffbf0fd0, 2814 "vmovx.f16\t%22,12-15F, %5,0-3F"}, 2815 2816 /* Vector VMUL floating-point T1 variant. */ 2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2818 MVE_VMUL_FP_T1, 2819 0xff000d50, 0xffa11f51, 2820 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2821 2822 /* Vector VMUL floating-point T2 variant. */ 2823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2824 MVE_VMUL_FP_T2, 2825 0xee310e60, 0xefb11f70, 2826 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2827 2828 /* Vector VMUL T1 variant. */ 2829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2830 MVE_VMUL_VEC_T1, 2831 0xef000950, 0xff811f51, 2832 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2833 2834 /* Vector VMUL T2 variant. */ 2835 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2836 MVE_VMUL_VEC_T2, 2837 0xee011e60, 0xff811f70, 2838 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2839 2840 /* Vector VMULH. */ 2841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2842 MVE_VMULH, 2843 0xee010e01, 0xef811f51, 2844 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2845 2846 /* Vector VRMULH. */ 2847 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2848 MVE_VRMULH, 2849 0xee011e01, 0xef811f51, 2850 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2851 2852 /* Vector VMULL integer. */ 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2854 MVE_VMULL_INT, 2855 0xee010e00, 0xef810f51, 2856 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2857 2858 /* Vector VMULL polynomial. */ 2859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2860 MVE_VMULL_POLY, 2861 0xee310e00, 0xefb10f51, 2862 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2863 2864 /* Vector VMVN immediate to vector. */ 2865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2866 MVE_VMVN_IMM, 2867 0xef800070, 0xefb810f0, 2868 "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, 2869 2870 /* Vector VMVN register. */ 2871 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2872 MVE_VMVN_REG, 2873 0xffb005c0, 0xffbf1fd1, 2874 "vmvn%v\t%13-15,22Q, %1-3,5Q"}, 2875 2876 /* Vector VNEG floating point. */ 2877 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2878 MVE_VNEG_FP, 2879 0xffb107c0, 0xffb31fd1, 2880 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2881 2882 /* Vector VNEG. */ 2883 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2884 MVE_VNEG_VEC, 2885 0xffb103c0, 0xffb31fd1, 2886 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2887 2888 /* Vector VORN, vector bitwise or not. */ 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2890 MVE_VORN, 2891 0xef300150, 0xffb11f51, 2892 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2893 2894 /* Vector VORR register. */ 2895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2896 MVE_VORR_REG, 2897 0xef200150, 0xffb11f51, 2898 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2899 2900 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if 2901 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen 2902 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes 2903 array. */ 2904 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2906 MVE_VMOV_VEC_TO_VEC, 2907 0xef200150, 0xffb11f51, 2908 "vmov%v\t%13-15,22Q, %17-19,7Q"}, 2909 2910 /* Vector VQDMULL T1 variant. */ 2911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2912 MVE_VQDMULL_T1, 2913 0xee300f01, 0xefb10f51, 2914 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2915 2916 /* Vector VPNOT. */ 2917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2918 MVE_VPNOT, 2919 0xfe310f4d, 0xffffffff, 2920 "vpnot%v"}, 2921 2922 /* Vector VPSEL. */ 2923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2924 MVE_VPSEL, 2925 0xfe310f01, 0xffb11f51, 2926 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2927 2928 /* Vector VQABS. */ 2929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2930 MVE_VQABS, 2931 0xffb00740, 0xffb31fd1, 2932 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2933 2934 /* Vector VQADD T1 variant. */ 2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2936 MVE_VQADD_T1, 2937 0xef000050, 0xef811f51, 2938 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2939 2940 /* Vector VQADD T2 variant. */ 2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2942 MVE_VQADD_T2, 2943 0xee000f60, 0xef811f70, 2944 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2945 2946 /* Vector VQDMULL T2 variant. */ 2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2948 MVE_VQDMULL_T2, 2949 0xee300f60, 0xefb10f70, 2950 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2951 2952 /* Vector VQMOVN. */ 2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2954 MVE_VQMOVN, 2955 0xee330e01, 0xefb30fd1, 2956 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, 2957 2958 /* Vector VQMOVUN. */ 2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2960 MVE_VQMOVUN, 2961 0xee310e81, 0xffb30fd1, 2962 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2963 2964 /* Vector VQDMLADH. */ 2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2966 MVE_VQDMLADH, 2967 0xee000e00, 0xff810f51, 2968 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2969 2970 /* Vector VQRDMLADH. */ 2971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2972 MVE_VQRDMLADH, 2973 0xee000e01, 0xff810f51, 2974 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2975 2976 /* Vector VQDMLAH. */ 2977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2978 MVE_VQDMLAH, 2979 0xee000e60, 0xff811f70, 2980 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2981 2982 /* Vector VQRDMLAH. */ 2983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2984 MVE_VQRDMLAH, 2985 0xee000e40, 0xff811f70, 2986 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2987 2988 /* Vector VQDMLASH. */ 2989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2990 MVE_VQDMLASH, 2991 0xee001e60, 0xff811f70, 2992 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2993 2994 /* Vector VQRDMLASH. */ 2995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2996 MVE_VQRDMLASH, 2997 0xee001e40, 0xff811f70, 2998 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2999 3000 /* Vector VQDMLSDH. */ 3001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3002 MVE_VQDMLSDH, 3003 0xfe000e00, 0xff810f51, 3004 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3005 3006 /* Vector VQRDMLSDH. */ 3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3008 MVE_VQRDMLSDH, 3009 0xfe000e01, 0xff810f51, 3010 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3011 3012 /* Vector VQDMULH T1 variant. */ 3013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3014 MVE_VQDMULH_T1, 3015 0xef000b40, 0xff811f51, 3016 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3017 3018 /* Vector VQRDMULH T2 variant. */ 3019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3020 MVE_VQRDMULH_T2, 3021 0xff000b40, 0xff811f51, 3022 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3023 3024 /* Vector VQDMULH T3 variant. */ 3025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3026 MVE_VQDMULH_T3, 3027 0xee010e60, 0xff811f70, 3028 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3029 3030 /* Vector VQRDMULH T4 variant. */ 3031 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3032 MVE_VQRDMULH_T4, 3033 0xfe010e60, 0xff811f70, 3034 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3035 3036 /* Vector VQNEG. */ 3037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3038 MVE_VQNEG, 3039 0xffb007c0, 0xffb31fd1, 3040 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3041 3042 /* Vector VQRSHL T1 variant. */ 3043 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3044 MVE_VQRSHL_T1, 3045 0xef000550, 0xef811f51, 3046 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3047 3048 /* Vector VQRSHL T2 variant. */ 3049 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3050 MVE_VQRSHL_T2, 3051 0xee331ee0, 0xefb31ff0, 3052 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3053 3054 /* Vector VQRSHRN. */ 3055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3056 MVE_VQRSHRN, 3057 0xee800f41, 0xefa00fd1, 3058 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3059 3060 /* Vector VQRSHRUN. */ 3061 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3062 MVE_VQRSHRUN, 3063 0xfe800fc0, 0xffa00fd1, 3064 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3065 3066 /* Vector VQSHL T1 Variant. */ 3067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3068 MVE_VQSHL_T1, 3069 0xee311ee0, 0xefb31ff0, 3070 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3071 3072 /* Vector VQSHL T4 Variant. */ 3073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3074 MVE_VQSHL_T4, 3075 0xef000450, 0xef811f51, 3076 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3077 3078 /* Vector VQSHRN. */ 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3080 MVE_VQSHRN, 3081 0xee800f40, 0xefa00fd1, 3082 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3083 3084 /* Vector VQSHRUN. */ 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3086 MVE_VQSHRUN, 3087 0xee800fc0, 0xffa00fd1, 3088 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3089 3090 /* Vector VQSUB T1 Variant. */ 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3092 MVE_VQSUB_T1, 3093 0xef000250, 0xef811f51, 3094 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3095 3096 /* Vector VQSUB T2 Variant. */ 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3098 MVE_VQSUB_T2, 3099 0xee001f60, 0xef811f70, 3100 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3101 3102 /* Vector VREV16. */ 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3104 MVE_VREV16, 3105 0xffb00140, 0xffb31fd1, 3106 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"}, 3107 3108 /* Vector VREV32. */ 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3110 MVE_VREV32, 3111 0xffb000c0, 0xffb31fd1, 3112 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3113 3114 /* Vector VREV64. */ 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3116 MVE_VREV64, 3117 0xffb00040, 0xffb31fd1, 3118 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3119 3120 /* Vector VRINT floating point. */ 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3122 MVE_VRINT_FP, 3123 0xffb20440, 0xffb31c51, 3124 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3125 3126 /* Vector VRMLALDAVH. */ 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3128 MVE_VRMLALDAVH, 3129 0xee800f00, 0xef811f51, 3130 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3131 3132 /* Vector VRMLALDAVH. */ 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3134 MVE_VRMLALDAVH, 3135 0xee801f00, 0xef811f51, 3136 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3137 3138 /* Vector VRSHL T1 Variant. */ 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3140 MVE_VRSHL_T1, 3141 0xef000540, 0xef811f51, 3142 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3143 3144 /* Vector VRSHL T2 Variant. */ 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3146 MVE_VRSHL_T2, 3147 0xee331e60, 0xefb31ff0, 3148 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3149 3150 /* Vector VRSHRN. */ 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3152 MVE_VRSHRN, 3153 0xfe800fc1, 0xffa00fd1, 3154 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3155 3156 /* Vector VSBC. */ 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3158 MVE_VSBC, 3159 0xfe300f00, 0xffb10f51, 3160 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3161 3162 /* Vector VSHL T2 Variant. */ 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3164 MVE_VSHL_T2, 3165 0xee311e60, 0xefb31ff0, 3166 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3167 3168 /* Vector VSHL T3 Variant. */ 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3170 MVE_VSHL_T3, 3171 0xef000440, 0xef811f51, 3172 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3173 3174 /* Vector VSHLC. */ 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3176 MVE_VSHLC, 3177 0xeea00fc0, 0xffa01ff0, 3178 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"}, 3179 3180 /* Vector VSHLL T2 Variant. */ 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3182 MVE_VSHLL_T2, 3183 0xee310e01, 0xefb30fd1, 3184 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"}, 3185 3186 /* Vector VSHRN. */ 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3188 MVE_VSHRN, 3189 0xee800fc1, 0xffa00fd1, 3190 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3191 3192 /* Vector VST2 no writeback. */ 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3194 MVE_VST2, 3195 0xfc801e00, 0xffb01e5f, 3196 "vst2%5d.%7-8s\t%B, [%16-19r]"}, 3197 3198 /* Vector VST2 writeback. */ 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3200 MVE_VST2, 3201 0xfca01e00, 0xffb01e5f, 3202 "vst2%5d.%7-8s\t%B, [%16-19r]!"}, 3203 3204 /* Vector VST4 no writeback. */ 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3206 MVE_VST4, 3207 0xfc801e01, 0xffb01e1f, 3208 "vst4%5-6d.%7-8s\t%B, [%16-19r]"}, 3209 3210 /* Vector VST4 writeback. */ 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3212 MVE_VST4, 3213 0xfca01e01, 0xffb01e1f, 3214 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"}, 3215 3216 /* Vector VSTRB scatter store, T1 variant. */ 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3218 MVE_VSTRB_SCATTER_T1, 3219 0xec800e00, 0xffb01e50, 3220 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 3221 3222 /* Vector VSTRH scatter store, T2 variant. */ 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3224 MVE_VSTRH_SCATTER_T2, 3225 0xec800e10, 0xffb01e50, 3226 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3227 3228 /* Vector VSTRW scatter store, T3 variant. */ 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3230 MVE_VSTRW_SCATTER_T3, 3231 0xec800e40, 0xffb01e50, 3232 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3233 3234 /* Vector VSTRD scatter store, T4 variant. */ 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3236 MVE_VSTRD_SCATTER_T4, 3237 0xec800fd0, 0xffb01fd0, 3238 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3239 3240 /* Vector VSTRW scatter store, T5 variant. */ 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3242 MVE_VSTRW_SCATTER_T5, 3243 0xfd001e00, 0xff111f00, 3244 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 3245 3246 /* Vector VSTRD scatter store, T6 variant. */ 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3248 MVE_VSTRD_SCATTER_T6, 3249 0xfd001f00, 0xff111f00, 3250 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 3251 3252 /* Vector VSTRB. */ 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3254 MVE_VSTRB_T1, 3255 0xec000e00, 0xfe581e00, 3256 "vstrb%v.%7-8s\t%13-15Q, %d"}, 3257 3258 /* Vector VSTRH. */ 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3260 MVE_VSTRH_T2, 3261 0xec080e00, 0xfe581e00, 3262 "vstrh%v.%7-8s\t%13-15Q, %d"}, 3263 3264 /* Vector VSTRB variant T5. */ 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3266 MVE_VSTRB_T5, 3267 0xec001e00, 0xfe101f80, 3268 "vstrb%v.8\t%13-15,22Q, %d"}, 3269 3270 /* Vector VSTRH variant T6. */ 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3272 MVE_VSTRH_T6, 3273 0xec001e80, 0xfe101f80, 3274 "vstrh%v.16\t%13-15,22Q, %d"}, 3275 3276 /* Vector VSTRW variant T7. */ 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3278 MVE_VSTRW_T7, 3279 0xec001f00, 0xfe101f80, 3280 "vstrw%v.32\t%13-15,22Q, %d"}, 3281 3282 /* Vector VSUB floating point T1 variant. */ 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3284 MVE_VSUB_FP_T1, 3285 0xef200d40, 0xffa11f51, 3286 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3287 3288 /* Vector VSUB floating point T2 variant. */ 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3290 MVE_VSUB_FP_T2, 3291 0xee301f40, 0xefb11f70, 3292 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3293 3294 /* Vector VSUB T1 variant. */ 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3296 MVE_VSUB_VEC_T1, 3297 0xff000840, 0xff811f51, 3298 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3299 3300 /* Vector VSUB T2 variant. */ 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3302 MVE_VSUB_VEC_T2, 3303 0xee011f40, 0xff811f70, 3304 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3305 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3307 MVE_ASRLI, 3308 0xea50012f, 0xfff1813f, 3309 "asrl%c\t%17-19l, %9-11h, %j"}, 3310 3311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3312 MVE_ASRL, 3313 0xea50012d, 0xfff101ff, 3314 "asrl%c\t%17-19l, %9-11h, %12-15S"}, 3315 3316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3317 MVE_LSLLI, 3318 0xea50010f, 0xfff1813f, 3319 "lsll%c\t%17-19l, %9-11h, %j"}, 3320 3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3322 MVE_LSLL, 3323 0xea50010d, 0xfff101ff, 3324 "lsll%c\t%17-19l, %9-11h, %12-15S"}, 3325 3326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3327 MVE_LSRL, 3328 0xea50011f, 0xfff1813f, 3329 "lsrl%c\t%17-19l, %9-11h, %j"}, 3330 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3332 MVE_SQRSHRL, 3333 0xea51012d, 0xfff1017f, 3334 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, 3335 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3337 MVE_SQRSHR, 3338 0xea500f2d, 0xfff00fff, 3339 "sqrshr%c\t%16-19S, %12-15S"}, 3340 3341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3342 MVE_SQSHLL, 3343 0xea51013f, 0xfff1813f, 3344 "sqshll%c\t%17-19l, %9-11h, %j"}, 3345 3346 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3347 MVE_SQSHL, 3348 0xea500f3f, 0xfff08f3f, 3349 "sqshl%c\t%16-19S, %j"}, 3350 3351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3352 MVE_SRSHRL, 3353 0xea51012f, 0xfff1813f, 3354 "srshrl%c\t%17-19l, %9-11h, %j"}, 3355 3356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3357 MVE_SRSHR, 3358 0xea500f2f, 0xfff08f3f, 3359 "srshr%c\t%16-19S, %j"}, 3360 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3362 MVE_UQRSHLL, 3363 0xea51010d, 0xfff1017f, 3364 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, 3365 3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3367 MVE_UQRSHL, 3368 0xea500f0d, 0xfff00fff, 3369 "uqrshl%c\t%16-19S, %12-15S"}, 3370 3371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3372 MVE_UQSHLL, 3373 0xea51010f, 0xfff1813f, 3374 "uqshll%c\t%17-19l, %9-11h, %j"}, 3375 3376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3377 MVE_UQSHL, 3378 0xea500f0f, 0xfff08f3f, 3379 "uqshl%c\t%16-19S, %j"}, 3380 3381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3382 MVE_URSHRL, 3383 0xea51011f, 0xfff1813f, 3384 "urshrl%c\t%17-19l, %9-11h, %j"}, 3385 3386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3387 MVE_URSHR, 3388 0xea500f1f, 0xfff08f3f, 3389 "urshr%c\t%16-19S, %j"}, 3390 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3392 MVE_CSINC, 3393 0xea509000, 0xfff0f000, 3394 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3395 3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3397 MVE_CSINV, 3398 0xea50a000, 0xfff0f000, 3399 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3400 3401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3402 MVE_CSET, 3403 0xea5f900f, 0xfffff00f, 3404 "cset\t%8-11S, %4-7C"}, 3405 3406 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3407 MVE_CSETM, 3408 0xea5fa00f, 0xfffff00f, 3409 "csetm\t%8-11S, %4-7C"}, 3410 3411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3412 MVE_CSEL, 3413 0xea508000, 0xfff0f000, 3414 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3415 3416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3417 MVE_CSNEG, 3418 0xea50b000, 0xfff0f000, 3419 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3420 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3422 MVE_CINC, 3423 0xea509000, 0xfff0f000, 3424 "cinc\t%8-11S, %16-19Z, %4-7C"}, 3425 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3427 MVE_CINV, 3428 0xea50a000, 0xfff0f000, 3429 "cinv\t%8-11S, %16-19Z, %4-7C"}, 3430 3431 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3432 MVE_CNEG, 3433 0xea50b000, 0xfff0f000, 3434 "cneg\t%8-11S, %16-19Z, %4-7C"}, 3435 3436 {ARM_FEATURE_CORE_LOW (0), 3437 MVE_NONE, 3438 0x00000000, 0x00000000, 0} 3439 }; 3440 3441 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 3442 ordered: they must be searched linearly from the top to obtain a correct 3443 match. */ 3444 3445 /* print_insn_arm recognizes the following format control codes: 3446 3447 %% % 3448 3449 %a print address for ldr/str instruction 3450 %s print address for ldr/str halfword/signextend instruction 3451 %S like %s but allow UNPREDICTABLE addressing 3452 %b print branch destination 3453 %c print condition code (always bits 28-31) 3454 %m print register mask for ldm/stm instruction 3455 %o print operand2 (immediate or register + shift) 3456 %p print 'p' iff bits 12-15 are 15 3457 %t print 't' iff bit 21 set and bit 24 clear 3458 %B print arm BLX(1) destination 3459 %C print the PSR sub type. 3460 %U print barrier type. 3461 %P print address for pli instruction. 3462 3463 %<bitfield>r print as an ARM register 3464 %<bitfield>T print as an ARM register + 1 3465 %<bitfield>R as %r but r15 is UNPREDICTABLE 3466 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 3467 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 3468 %<bitfield>d print the bitfield in decimal 3469 %<bitfield>W print the bitfield plus one in decimal 3470 %<bitfield>x print the bitfield in hex 3471 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 3472 3473 %<bitfield>'c print specified char iff bitfield is all ones 3474 %<bitfield>`c print specified char iff bitfield is all zeroes 3475 %<bitfield>?ab... select from array of values in big endian order 3476 3477 %e print arm SMI operand (bits 0..7,8..19). 3478 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 3479 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 3480 %R print the SPSR/CPSR or banked register of an MRS. */ 3481 3482 static const struct opcode32 arm_opcodes[] = 3483 { 3484 /* ARM instructions. */ 3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3486 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"}, 3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3488 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"}, 3489 3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 3491 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3493 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3495 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 3497 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3499 0x00800090, 0x0fa000f0, 3500 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3502 0x00a00090, 0x0fa000f0, 3503 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3504 3505 /* V8.2 RAS extension instructions. */ 3506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 3507 0xe320f010, 0xffffffff, "esb"}, 3508 3509 /* V8-R instructions. */ 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 3511 0xf57ff04c, 0xffffffff, "dfb"}, 3512 3513 /* V8 instructions. */ 3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3515 0x0320f005, 0x0fffffff, "sevl"}, 3516 /* Defined in V8 but is in NOP space so available to all arch. */ 3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3518 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"}, 3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 3520 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 3521 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3522 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3524 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3526 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 3527 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3528 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 3529 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3530 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 3531 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3532 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 3533 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3534 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 3535 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3536 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 3537 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3538 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 3539 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3540 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 3541 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3542 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 3543 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3544 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 3545 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3546 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 3547 /* CRC32 instructions. */ 3548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3549 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3551 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 3552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3553 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 3554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3555 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 3556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3557 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 3558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3559 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 3560 3561 /* Privileged Access Never extension instructions. */ 3562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 3563 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"}, 3564 3565 /* Virtualization Extension instructions. */ 3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 3568 3569 /* Integer Divide Extension instructions. */ 3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3571 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3573 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 3574 3575 /* MP Extension instructions. */ 3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 3577 3578 /* Speculation Barriers. */ 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 3582 3583 /* V7 instructions. */ 3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"}, 3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 3592 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"}, 3593 3594 /* ARM V6T2 instructions. */ 3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3596 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3598 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3600 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3602 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 3603 3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3605 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3607 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 3608 3609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3610 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 3611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3612 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3614 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3616 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"}, 3617 3618 /* ARM Security extension instructions. */ 3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 3620 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 3621 3622 /* ARM V6K instructions. */ 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3624 0xf57ff01f, 0xffffffff, "clrex"}, 3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3626 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3628 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3630 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3632 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3634 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3636 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 3637 3638 /* ARMv8.5-A instructions. */ 3639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 3640 3641 /* ARM V6K NOP hints. */ 3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3643 0x0320f001, 0x0fffffff, "yield%c"}, 3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3645 0x0320f002, 0x0fffffff, "wfe%c"}, 3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3647 0x0320f003, 0x0fffffff, "wfi%c"}, 3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3649 0x0320f004, 0x0fffffff, "sev%c"}, 3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3651 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"}, 3652 3653 /* ARM V6 instructions. */ 3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3655 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"}, 3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3657 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"}, 3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3659 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"}, 3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3661 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"}, 3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3663 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"}, 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3665 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3667 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3669 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"}, 3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3671 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3673 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"}, 3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3675 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3677 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3679 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3681 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3683 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3685 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3687 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3689 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3691 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3693 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3695 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3697 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3699 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3701 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3703 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3705 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3707 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3709 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3711 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3713 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3715 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3717 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3719 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3721 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3723 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3725 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3727 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3729 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3731 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3733 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3735 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3737 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3739 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3741 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3743 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3745 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3747 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3749 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3751 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3753 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3755 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3757 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3759 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3761 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3763 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3765 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3767 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3769 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3771 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3773 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3775 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3777 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3779 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3781 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3783 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3785 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3787 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3789 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3791 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3793 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3795 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3797 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3799 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3801 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3803 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3805 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3807 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3809 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3811 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3813 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3815 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3817 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3819 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3821 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3823 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3825 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3827 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3829 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3831 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3833 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3835 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3837 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3839 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3841 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"}, 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3843 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3845 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3847 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3849 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3851 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3853 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"}, 3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3855 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3857 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3859 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3861 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3863 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3865 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3867 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3869 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3871 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3873 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"}, 3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3875 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"}, 3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3877 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3879 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3881 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"}, 3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3883 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3885 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3887 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3889 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3891 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"}, 3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3893 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3895 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3897 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"}, 3898 3899 /* V5J instruction. */ 3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 3901 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 3902 3903 /* V5 Instructions. */ 3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3905 0xe1200070, 0xfff000f0, 3906 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"}, 3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3908 0xfa000000, 0xfe000000, "blx\t%B"}, 3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3910 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3912 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 3913 3914 /* V5E "El Segundo" Instructions. */ 3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3916 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3918 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3920 0xf450f000, 0xfc70f000, "pld\t%a"}, 3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3922 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3924 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3926 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3928 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 3929 3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3931 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3933 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 3934 3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3936 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3938 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3940 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3942 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3943 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3945 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3947 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3949 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3951 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 3952 3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3954 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3956 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 3957 3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3959 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3961 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3963 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3965 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 3966 3967 /* ARM Instructions. */ 3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3969 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"}, 3970 3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3972 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3974 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3976 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3978 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3980 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3982 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 3983 3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3985 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3987 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3989 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3991 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 3992 3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3994 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3996 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3998 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4000 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 4001 4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4003 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4005 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4007 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 4008 4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4010 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4012 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4014 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 4015 4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4017 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4019 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4021 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 4022 4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4024 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4026 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4028 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 4029 4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4031 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4033 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4035 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 4036 4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4038 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4040 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4042 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 4043 4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4045 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4047 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4049 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 4050 4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4052 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4054 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4056 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 4057 4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 4059 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4061 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4063 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 4064 4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4066 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4068 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4070 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 4071 4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4073 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4075 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4077 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 4078 4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4080 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4082 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4084 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 4085 4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4087 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4089 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4091 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 4092 4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4094 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4096 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4098 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 4099 4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4101 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4103 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4105 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4107 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4109 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4111 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4113 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 4114 4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4116 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4118 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4120 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 4121 4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4123 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4125 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4127 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 4128 4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4130 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4132 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"}, 4133 4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4135 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 4136 4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4138 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4140 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 4141 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4143 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4145 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4147 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4149 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4151 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4153 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4155 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4157 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4159 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4161 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4163 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4165 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4167 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4169 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4171 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4173 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4175 0x092d0000, 0x0fff0000, "push%c\t%m"}, 4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4177 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4179 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4180 4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4182 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4184 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4186 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4188 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4190 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4192 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4194 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4196 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4198 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4200 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4202 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4204 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4206 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4208 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4210 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4212 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4214 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4216 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4218 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4219 4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4221 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4223 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 4224 4225 /* The rest. */ 4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 4227 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION}, 4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4229 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 4230 {ARM_FEATURE_CORE_LOW (0), 4231 0x00000000, 0x00000000, 0} 4232 }; 4233 4234 /* print_insn_thumb16 recognizes the following format control codes: 4235 4236 %S print Thumb register (bits 3..5 as high number if bit 6 set) 4237 %D print Thumb register (bits 0..2 as high number if bit 7 set) 4238 %<bitfield>I print bitfield as a signed decimal 4239 (top bit of range being the sign bit) 4240 %N print Thumb register mask (with LR) 4241 %O print Thumb register mask (with PC) 4242 %M print Thumb register mask 4243 %b print CZB's 6-bit unsigned branch destination 4244 %s print Thumb right-shift immediate (6..10; 0 == 32). 4245 %c print the condition code 4246 %C print the condition code, or "s" if not conditional 4247 %x print warning if conditional an not at end of IT block" 4248 %X print "\t@ unpredictable <IT:code>" if conditional 4249 %I print IT instruction suffix and operands 4250 %W print Thumb Writeback indicator for LDMIA 4251 %<bitfield>r print bitfield as an ARM register 4252 %<bitfield>d print bitfield as a decimal 4253 %<bitfield>H print (bitfield * 2) as a decimal 4254 %<bitfield>W print (bitfield * 4) as a decimal 4255 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 4256 %<bitfield>B print Thumb branch destination (signed displacement) 4257 %<bitfield>c print bitfield as a condition code 4258 %<bitnum>'c print specified char iff bit is one 4259 %<bitnum>?ab print a if bit is one else print b. */ 4260 4261 static const struct opcode16 thumb_opcodes[] = 4262 { 4263 /* Thumb instructions. */ 4264 4265 /* ARMv8-M Security Extensions instructions. */ 4266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 4267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 4268 4269 /* ARM V8 instructions. */ 4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 4272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"}, 4273 4274 /* ARM V6K no-argument instructions. */ 4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 4281 4282 /* ARM V6T2 instructions. */ 4283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4284 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 4285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4286 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 4288 4289 /* ARM V6. */ 4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"}, 4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"}, 4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"}, 4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 4301 4302 /* ARM V5 ISA extends Thumb. */ 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4304 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 4305 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4307 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 4308 /* ARM V4T ISA (Thumb v1). */ 4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4310 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"}, 4311 /* Format 4. */ 4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 4328 /* format 13 */ 4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"}, 4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"}, 4331 /* format 5 */ 4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 4336 /* format 14 */ 4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 4339 /* format 2 */ 4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4341 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4343 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4345 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"}, 4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4347 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"}, 4348 /* format 8 */ 4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4350 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4352 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4354 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 4355 /* format 7 */ 4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4357 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4359 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4360 /* format 1 */ 4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4363 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"}, 4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 4366 /* format 3 */ 4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"}, 4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"}, 4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"}, 4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"}, 4371 /* format 6 */ 4372 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4374 0x4800, 0xF800, 4375 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"}, 4376 /* format 9 */ 4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4378 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"}, 4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4380 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"}, 4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4382 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"}, 4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4384 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"}, 4385 /* format 10 */ 4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4387 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"}, 4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4389 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"}, 4390 /* format 11 */ 4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4392 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"}, 4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4394 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"}, 4395 /* format 12 */ 4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4397 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"}, 4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4399 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"}, 4400 /* format 15 */ 4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 4403 /* format 17 */ 4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 4405 /* format 16 */ 4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"}, 4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 4409 /* format 18 */ 4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 4411 4412 /* The E800 .. FFFF range is unconditionally redirected to the 4413 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 4414 are processed via that table. Thus, we can never encounter a 4415 bare "second half of BL/BLX(1)" instruction here. */ 4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 4417 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 4418 }; 4419 4420 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 4421 We adopt the convention that hw1 is the high 16 bits of .value and 4422 .mask, hw2 the low 16 bits. 4423 4424 print_insn_thumb32 recognizes the following format control codes: 4425 4426 %% % 4427 4428 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 4429 %M print a modified 12-bit immediate (same location) 4430 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 4431 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 4432 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 4433 %S print a possibly-shifted Rm 4434 4435 %L print address for a ldrd/strd instruction 4436 %a print the address of a plain load/store 4437 %w print the width and signedness of a core load/store 4438 %m print register mask for ldm/stm 4439 %n print register mask for clrm 4440 4441 %E print the lsb and width fields of a bfc/bfi instruction 4442 %F print the lsb and width fields of a sbfx/ubfx instruction 4443 %G print a fallback offset for Branch Future instructions 4444 %W print an offset for BF instruction 4445 %Y print an offset for BFL instruction 4446 %Z print an offset for BFCSEL instruction 4447 %Q print an offset for Low Overhead Loop instructions 4448 %P print an offset for Low Overhead Loop end instructions 4449 %b print a conditional branch offset 4450 %B print an unconditional branch offset 4451 %s print the shift field of an SSAT instruction 4452 %R print the rotation field of an SXT instruction 4453 %U print barrier type. 4454 %P print address for pli instruction. 4455 %c print the condition code 4456 %x print warning if conditional an not at end of IT block" 4457 %X print "\t@ unpredictable <IT:code>" if conditional 4458 4459 %<bitfield>d print bitfield in decimal 4460 %<bitfield>D print bitfield plus one in decimal 4461 %<bitfield>W print bitfield*4 in decimal 4462 %<bitfield>r print bitfield as an ARM register 4463 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 4464 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE 4465 %<bitfield>c print bitfield as a condition code 4466 4467 %<bitfield>'c print specified char iff bitfield is all ones 4468 %<bitfield>`c print specified char iff bitfield is all zeroes 4469 %<bitfield>?ab... select from array of values in big endian order 4470 4471 With one exception at the bottom (done because BL and BLX(1) need 4472 to come dead last), this table was machine-sorted first in 4473 decreasing order of number of bits set in the mask, then in 4474 increasing numeric order of mask, then in increasing numeric order 4475 of opcode. This order is not the clearest for a human reader, but 4476 is guaranteed never to catch a special-case bit pattern with a more 4477 general mask, which is important, because this instruction encoding 4478 makes heavy use of special-case bit patterns. */ 4479 static const struct opcode32 thumb32_opcodes[] = 4480 { 4481 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target 4482 Identification Extension. */ 4483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4484 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4485 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4486 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"}, 4487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4488 0xf3af800f, 0xffffffff, "bti"}, 4489 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4490 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"}, 4491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4492 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4494 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4495 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4496 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"}, 4497 4498 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions 4499 instructions. */ 4500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4501 0xf00fe001, 0xffffffff, "lctp%c"}, 4502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4503 0xf02fc001, 0xfffff001, "le\t%P"}, 4504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4505 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"}, 4506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4507 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"}, 4508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4509 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"}, 4510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4511 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"}, 4512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4513 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"}, 4514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4515 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"}, 4516 4517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4518 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, 4519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4520 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, 4521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4522 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"}, 4523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4524 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, 4525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4526 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"}, 4527 4528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4529 0xe89f0000, 0xffff2000, "clrm%c\t%n"}, 4530 4531 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 4532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 4533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4534 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4536 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4538 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4540 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 4541 4542 /* ARM V8.2 RAS extension instructions. */ 4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 4544 0xf3af8010, 0xffffffff, "esb"}, 4545 4546 /* V8 instructions. */ 4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4548 0xf3af8005, 0xffffffff, "sevl%c.w"}, 4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4550 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4552 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4554 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4556 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4558 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 4559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4560 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4562 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4564 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4566 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4568 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 4569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4570 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4572 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4574 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4576 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4578 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 4579 4580 /* V8-R instructions. */ 4581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 4582 0xf3bf8f4c, 0xffffffff, "dfb%c"}, 4583 4584 /* CRC32 instructions. */ 4585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4586 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 4587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4588 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 4589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4590 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 4591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4592 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4594 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 4595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4596 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 4597 4598 /* Speculation Barriers. */ 4599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 4601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 4602 4603 /* V7 instructions. */ 4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 4605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"}, 4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 4607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 4609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 4611 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4612 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 4613 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4614 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 4615 4616 /* Virtualization Extension instructions. */ 4617 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 4618 /* We skip ERET as that is SUBS pc, lr, #0. */ 4619 4620 /* MP Extension instructions. */ 4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 4622 4623 /* Security extension instructions. */ 4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 4625 4626 /* ARMv8.5-A instructions. */ 4627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 4628 4629 /* Instructions defined in the basic V6T2 set. */ 4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4636 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"}, 4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 4638 4639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4640 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4642 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"}, 4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4644 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"}, 4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4646 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4648 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4650 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4652 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4654 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"}, 4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4656 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 4657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4658 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"}, 4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4660 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"}, 4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4662 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"}, 4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4664 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"}, 4665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4666 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4668 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4670 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4672 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"}, 4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4674 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"}, 4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4676 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4678 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4680 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4682 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4684 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 4685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4686 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 4687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4688 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4690 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4692 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4694 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 4695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4696 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4698 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4700 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4702 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4704 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4706 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4708 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4710 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4712 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4714 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4716 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4718 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4720 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4722 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4724 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4726 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4728 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4730 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4732 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4734 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4736 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4738 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4740 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4742 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4744 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4746 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4748 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4750 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4752 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4754 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4756 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4758 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4760 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4762 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4764 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4766 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4768 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4770 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4772 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4774 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4776 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4778 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4780 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4782 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4784 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4786 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4788 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4790 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4792 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4794 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 4795 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4796 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4798 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"}, 4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4800 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"}, 4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4802 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4804 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4806 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4808 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4810 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4812 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4814 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4816 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4818 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4820 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4822 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4824 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4826 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4828 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4830 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4832 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4834 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4836 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4838 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4840 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4842 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4844 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4846 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4848 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4850 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4852 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4854 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4856 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4858 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4860 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4862 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4863 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4864 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"}, 4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4866 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4868 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4870 0xf810f000, 0xff70f000, "pld%c\t%a"}, 4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4872 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4874 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4876 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4878 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4880 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4882 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4884 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4886 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4888 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4890 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4892 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4894 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4896 0xfb100000, 0xfff000c0, 4897 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4899 0xfbc00080, 0xfff000c0, 4900 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4902 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4904 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4906 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"}, 4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4908 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"}, 4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4910 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 4911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4912 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4914 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 4915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4916 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4918 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4920 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4922 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4924 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4926 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4928 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4930 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4932 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4934 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4936 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 4937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4938 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"}, 4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4940 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4942 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4944 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4946 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4948 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4950 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4952 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4954 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4956 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4958 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4960 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4962 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4964 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4966 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4968 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4970 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4972 0xe9400000, 0xff500000, 4973 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"}, 4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4975 0xe9500000, 0xff500000, 4976 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"}, 4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4978 0xe8600000, 0xff700000, 4979 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"}, 4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4981 0xe8700000, 0xff700000, 4982 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"}, 4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4984 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4986 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 4987 4988 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4990 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4992 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4994 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4996 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 4997 4998 /* These have been 32-bit since the invention of Thumb. */ 4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5000 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5002 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 5003 5004 /* Fallback. */ 5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 5006 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 5007 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 5008 }; 5009 5010 static const char *const arm_conditional[] = 5011 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 5012 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 5013 5014 static const char *const arm_fp_const[] = 5015 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 5016 5017 static const char *const arm_shift[] = 5018 {"lsl", "lsr", "asr", "ror"}; 5019 5020 typedef struct 5021 { 5022 const char *name; 5023 const char *description; 5024 const char *reg_names[16]; 5025 } 5026 arm_regname; 5027 5028 static const arm_regname regnames[] = 5029 { 5030 { "reg-names-raw", N_("Select raw register names"), 5031 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 5032 { "reg-names-gcc", N_("Select register names used by GCC"), 5033 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5034 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 5035 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 5036 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 5037 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 5038 { "reg-names-apcs", N_("Select register names used in the APCS"), 5039 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5040 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 5041 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 5042 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 5043 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 5044 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } } 5045 }; 5046 5047 static const char *const iwmmxt_wwnames[] = 5048 {"b", "h", "w", "d"}; 5049 5050 static const char *const iwmmxt_wwssnames[] = 5051 {"b", "bus", "bc", "bss", 5052 "h", "hus", "hc", "hss", 5053 "w", "wus", "wc", "wss", 5054 "d", "dus", "dc", "dss" 5055 }; 5056 5057 static const char *const iwmmxt_regnames[] = 5058 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 5059 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 5060 }; 5061 5062 static const char *const iwmmxt_cregnames[] = 5063 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 5064 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 5065 }; 5066 5067 static const char *const vec_condnames[] = 5068 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le" 5069 }; 5070 5071 static const char *const mve_predicatenames[] = 5072 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "", 5073 "eee", "ee", "eet", "e", "ett", "et", "ete" 5074 }; 5075 5076 /* Names for 2-bit size field for mve vector isntructions. */ 5077 static const char *const mve_vec_sizename[] = 5078 { "8", "16", "32", "64"}; 5079 5080 /* Indicates whether we are processing a then predicate, 5081 else predicate or none at all. */ 5082 enum vpt_pred_state 5083 { 5084 PRED_NONE, 5085 PRED_THEN, 5086 PRED_ELSE 5087 }; 5088 5089 /* Information used to process a vpt block and subsequent instructions. */ 5090 struct vpt_block 5091 { 5092 /* Are we in a vpt block. */ 5093 bool in_vpt_block; 5094 5095 /* Next predicate state if in vpt block. */ 5096 enum vpt_pred_state next_pred_state; 5097 5098 /* Mask from vpt/vpst instruction. */ 5099 long predicate_mask; 5100 5101 /* Instruction number in vpt block. */ 5102 long current_insn_num; 5103 5104 /* Number of instructions in vpt block.. */ 5105 long num_pred_insn; 5106 }; 5107 5108 static struct vpt_block vpt_block_state = 5109 { 5110 false, 5111 PRED_NONE, 5112 0, 5113 0, 5114 0 5115 }; 5116 5117 /* Default to GCC register name set. */ 5118 static unsigned int regname_selected = 1; 5119 5120 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 5121 #define arm_regnames regnames[regname_selected].reg_names 5122 5123 static bool force_thumb = false; 5124 static uint16_t cde_coprocs = 0; 5125 5126 /* Current IT instruction state. This contains the same state as the IT 5127 bits in the CPSR. */ 5128 static unsigned int ifthen_state; 5129 /* IT state for the next instruction. */ 5130 static unsigned int ifthen_next_state; 5131 /* The address of the insn for which the IT state is valid. */ 5132 static bfd_vma ifthen_address; 5133 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 5134 /* Indicates that the current Conditional state is unconditional or outside 5135 an IT block. */ 5136 #define COND_UNCOND 16 5137 5138 5139 /* Functions. */ 5141 /* Extract the predicate mask for a VPT or VPST instruction. 5142 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */ 5143 5144 static long 5145 mve_extract_pred_mask (long given) 5146 { 5147 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13); 5148 } 5149 5150 /* Return the number of instructions in a MVE predicate block. */ 5151 static long 5152 num_instructions_vpt_block (long given) 5153 { 5154 long mask = mve_extract_pred_mask (given); 5155 if (mask == 0) 5156 return 0; 5157 5158 if (mask == 8) 5159 return 1; 5160 5161 if ((mask & 7) == 4) 5162 return 2; 5163 5164 if ((mask & 3) == 2) 5165 return 3; 5166 5167 if ((mask & 1) == 1) 5168 return 4; 5169 5170 return 0; 5171 } 5172 5173 static void 5174 mark_outside_vpt_block (void) 5175 { 5176 vpt_block_state.in_vpt_block = false; 5177 vpt_block_state.next_pred_state = PRED_NONE; 5178 vpt_block_state.predicate_mask = 0; 5179 vpt_block_state.current_insn_num = 0; 5180 vpt_block_state.num_pred_insn = 0; 5181 } 5182 5183 static void 5184 mark_inside_vpt_block (long given) 5185 { 5186 vpt_block_state.in_vpt_block = true; 5187 vpt_block_state.next_pred_state = PRED_THEN; 5188 vpt_block_state.predicate_mask = mve_extract_pred_mask (given); 5189 vpt_block_state.current_insn_num = 0; 5190 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given); 5191 assert (vpt_block_state.num_pred_insn >= 1); 5192 } 5193 5194 static enum vpt_pred_state 5195 invert_next_predicate_state (enum vpt_pred_state astate) 5196 { 5197 if (astate == PRED_THEN) 5198 return PRED_ELSE; 5199 else if (astate == PRED_ELSE) 5200 return PRED_THEN; 5201 else 5202 return PRED_NONE; 5203 } 5204 5205 static enum vpt_pred_state 5206 update_next_predicate_state (void) 5207 { 5208 long pred_mask = vpt_block_state.predicate_mask; 5209 long mask_for_insn = 0; 5210 5211 switch (vpt_block_state.current_insn_num) 5212 { 5213 case 1: 5214 mask_for_insn = 8; 5215 break; 5216 5217 case 2: 5218 mask_for_insn = 4; 5219 break; 5220 5221 case 3: 5222 mask_for_insn = 2; 5223 break; 5224 5225 case 4: 5226 return PRED_NONE; 5227 } 5228 5229 if (pred_mask & mask_for_insn) 5230 return invert_next_predicate_state (vpt_block_state.next_pred_state); 5231 else 5232 return vpt_block_state.next_pred_state; 5233 } 5234 5235 static void 5236 update_vpt_block_state (void) 5237 { 5238 vpt_block_state.current_insn_num++; 5239 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn) 5240 { 5241 /* No more instructions to process in vpt block. */ 5242 mark_outside_vpt_block (); 5243 return; 5244 } 5245 5246 vpt_block_state.next_pred_state = update_next_predicate_state (); 5247 } 5248 5249 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 5250 Returns pointer to following character of the format string and 5251 fills in *VALUEP and *WIDTHP with the extracted value and number of 5252 bits extracted. WIDTHP can be NULL. */ 5253 5254 static const char * 5255 arm_decode_bitfield (const char *ptr, 5256 unsigned long insn, 5257 unsigned long *valuep, 5258 int *widthp) 5259 { 5260 unsigned long value = 0; 5261 int width = 0; 5262 5263 do 5264 { 5265 int start, end; 5266 int bits; 5267 5268 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 5269 start = start * 10 + *ptr - '0'; 5270 if (*ptr == '-') 5271 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 5272 end = end * 10 + *ptr - '0'; 5273 else 5274 end = start; 5275 bits = end - start; 5276 if (bits < 0) 5277 abort (); 5278 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 5279 width += bits + 1; 5280 } 5281 while (*ptr++ == ','); 5282 *valuep = value; 5283 if (widthp) 5284 *widthp = width; 5285 return ptr - 1; 5286 } 5287 5288 static void 5289 arm_decode_shift (long given, fprintf_styled_ftype func, void *stream, 5290 bool print_shift) 5291 { 5292 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]); 5293 5294 if ((given & 0xff0) != 0) 5295 { 5296 if ((given & 0x10) == 0) 5297 { 5298 int amount = (given & 0xf80) >> 7; 5299 int shift = (given & 0x60) >> 5; 5300 5301 if (amount == 0) 5302 { 5303 if (shift == 3) 5304 { 5305 func (stream, dis_style_text, ", "); 5306 func (stream, dis_style_sub_mnemonic, "rrx"); 5307 return; 5308 } 5309 5310 amount = 32; 5311 } 5312 5313 if (print_shift) 5314 { 5315 func (stream, dis_style_text, ", "); 5316 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]); 5317 func (stream, dis_style_immediate, "#%d", amount); 5318 } 5319 else 5320 { 5321 func (stream, dis_style_text, ", "); 5322 func (stream, dis_style_immediate, "#%d", amount); 5323 } 5324 } 5325 else if ((given & 0x80) == 0x80) 5326 func (stream, dis_style_comment_start, 5327 "\t@ <illegal shifter operand>"); 5328 else if (print_shift) 5329 { 5330 func (stream, dis_style_text, ", "); 5331 func (stream, dis_style_sub_mnemonic, "%s ", 5332 arm_shift[(given & 0x60) >> 5]); 5333 func (stream, dis_style_register, "%s", 5334 arm_regnames[(given & 0xf00) >> 8]); 5335 } 5336 else 5337 { 5338 func (stream, dis_style_text, ", "); 5339 func (stream, dis_style_register, "%s", 5340 arm_regnames[(given & 0xf00) >> 8]); 5341 } 5342 } 5343 } 5344 5345 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */ 5346 5347 static bool 5348 is_mve_okay_in_it (enum mve_instructions matched_insn) 5349 { 5350 switch (matched_insn) 5351 { 5352 case MVE_VMOV_GP_TO_VEC_LANE: 5353 case MVE_VMOV2_VEC_LANE_TO_GP: 5354 case MVE_VMOV2_GP_TO_VEC_LANE: 5355 case MVE_VMOV_VEC_LANE_TO_GP: 5356 case MVE_LSLL: 5357 case MVE_LSLLI: 5358 case MVE_LSRL: 5359 case MVE_ASRL: 5360 case MVE_ASRLI: 5361 case MVE_SQRSHRL: 5362 case MVE_SQRSHR: 5363 case MVE_UQRSHL: 5364 case MVE_UQRSHLL: 5365 case MVE_UQSHL: 5366 case MVE_UQSHLL: 5367 case MVE_URSHRL: 5368 case MVE_URSHR: 5369 case MVE_SRSHRL: 5370 case MVE_SRSHR: 5371 case MVE_SQSHLL: 5372 case MVE_SQSHL: 5373 return true; 5374 default: 5375 return false; 5376 } 5377 } 5378 5379 static bool 5380 is_mve_architecture (struct disassemble_info *info) 5381 { 5382 struct arm_private_data *private_data = info->private_data; 5383 arm_feature_set allowed_arches = private_data->features; 5384 5385 arm_feature_set arm_ext_v8_1m_main 5386 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 5387 5388 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 5389 && !ARM_CPU_IS_ANY (allowed_arches)) 5390 return true; 5391 else 5392 return false; 5393 } 5394 5395 static bool 5396 is_vpt_instruction (long given) 5397 { 5398 5399 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */ 5400 if ((given & 0x0040e000) == 0) 5401 return false; 5402 5403 /* VPT floating point T1 variant. */ 5404 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1)) 5405 /* VPT floating point T2 variant. */ 5406 || ((given & 0xefb10f50) == 0xee310f40) 5407 /* VPT vector T1 variant. */ 5408 || ((given & 0xff811f51) == 0xfe010f00) 5409 /* VPT vector T2 variant. */ 5410 || ((given & 0xff811f51) == 0xfe010f01 5411 && ((given & 0x300000) != 0x300000)) 5412 /* VPT vector T3 variant. */ 5413 || ((given & 0xff811f50) == 0xfe011f00) 5414 /* VPT vector T4 variant. */ 5415 || ((given & 0xff811f70) == 0xfe010f40) 5416 /* VPT vector T5 variant. */ 5417 || ((given & 0xff811f70) == 0xfe010f60) 5418 /* VPT vector T6 variant. */ 5419 || ((given & 0xff811f50) == 0xfe011f40) 5420 /* VPST vector T variant. */ 5421 || ((given & 0xffbf1fff) == 0xfe310f4d)) 5422 return true; 5423 else 5424 return false; 5425 } 5426 5427 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START 5428 and ending bitfield = END. END must be greater than START. */ 5429 5430 static unsigned long 5431 arm_decode_field (unsigned long given, unsigned int start, unsigned int end) 5432 { 5433 int bits = end - start; 5434 5435 if (bits < 0) 5436 abort (); 5437 5438 return ((given >> start) & ((2ul << bits) - 1)); 5439 } 5440 5441 /* Decode a bitfield from opcode GIVEN, with multiple bitfields: 5442 START:END and START2:END2. END/END2 must be greater than 5443 START/START2. */ 5444 5445 static unsigned long 5446 arm_decode_field_multiple (unsigned long given, unsigned int start, 5447 unsigned int end, unsigned int start2, 5448 unsigned int end2) 5449 { 5450 int bits = end - start; 5451 int bits2 = end2 - start2; 5452 unsigned long value = 0; 5453 int width = 0; 5454 5455 if (bits2 < 0) 5456 abort (); 5457 5458 value = arm_decode_field (given, start, end); 5459 width += bits + 1; 5460 5461 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width; 5462 return value; 5463 } 5464 5465 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN. 5466 This helps us decode instructions that change mnemonic depending on specific 5467 operand values/encodings. */ 5468 5469 static bool 5470 is_mve_encoding_conflict (unsigned long given, 5471 enum mve_instructions matched_insn) 5472 { 5473 switch (matched_insn) 5474 { 5475 case MVE_VPST: 5476 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5477 return true; 5478 else 5479 return false; 5480 5481 case MVE_VPT_FP_T1: 5482 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5483 return true; 5484 if ((arm_decode_field (given, 12, 12) == 0) 5485 && (arm_decode_field (given, 0, 0) == 1)) 5486 return true; 5487 return false; 5488 5489 case MVE_VPT_FP_T2: 5490 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5491 return true; 5492 if (arm_decode_field (given, 0, 3) == 0xd) 5493 return true; 5494 return false; 5495 5496 case MVE_VPT_VEC_T1: 5497 case MVE_VPT_VEC_T2: 5498 case MVE_VPT_VEC_T3: 5499 case MVE_VPT_VEC_T4: 5500 case MVE_VPT_VEC_T5: 5501 case MVE_VPT_VEC_T6: 5502 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5503 return true; 5504 if (arm_decode_field (given, 20, 21) == 3) 5505 return true; 5506 return false; 5507 5508 case MVE_VCMP_FP_T1: 5509 if ((arm_decode_field (given, 12, 12) == 0) 5510 && (arm_decode_field (given, 0, 0) == 1)) 5511 return true; 5512 else 5513 return false; 5514 5515 case MVE_VCMP_FP_T2: 5516 if (arm_decode_field (given, 0, 3) == 0xd) 5517 return true; 5518 else 5519 return false; 5520 5521 case MVE_VQADD_T2: 5522 case MVE_VQSUB_T2: 5523 case MVE_VMUL_VEC_T2: 5524 case MVE_VMULH: 5525 case MVE_VRMULH: 5526 case MVE_VMLA: 5527 case MVE_VMAX: 5528 case MVE_VMIN: 5529 case MVE_VBRSR: 5530 case MVE_VADD_VEC_T2: 5531 case MVE_VSUB_VEC_T2: 5532 case MVE_VABAV: 5533 case MVE_VQRSHL_T1: 5534 case MVE_VQSHL_T4: 5535 case MVE_VRSHL_T1: 5536 case MVE_VSHL_T3: 5537 case MVE_VCADD_VEC: 5538 case MVE_VHCADD: 5539 case MVE_VDDUP: 5540 case MVE_VIDUP: 5541 case MVE_VQRDMLADH: 5542 case MVE_VQDMLAH: 5543 case MVE_VQRDMLAH: 5544 case MVE_VQDMLASH: 5545 case MVE_VQRDMLASH: 5546 case MVE_VQDMLSDH: 5547 case MVE_VQRDMLSDH: 5548 case MVE_VQDMULH_T3: 5549 case MVE_VQRDMULH_T4: 5550 case MVE_VQDMLADH: 5551 case MVE_VMLAS: 5552 case MVE_VMULL_INT: 5553 case MVE_VHADD_T2: 5554 case MVE_VHSUB_T2: 5555 case MVE_VCMP_VEC_T1: 5556 case MVE_VCMP_VEC_T2: 5557 case MVE_VCMP_VEC_T3: 5558 case MVE_VCMP_VEC_T4: 5559 case MVE_VCMP_VEC_T5: 5560 case MVE_VCMP_VEC_T6: 5561 if (arm_decode_field (given, 20, 21) == 3) 5562 return true; 5563 else 5564 return false; 5565 5566 case MVE_VLD2: 5567 case MVE_VLD4: 5568 case MVE_VST2: 5569 case MVE_VST4: 5570 if (arm_decode_field (given, 7, 8) == 3) 5571 return true; 5572 else 5573 return false; 5574 5575 case MVE_VSTRB_T1: 5576 case MVE_VSTRH_T2: 5577 if ((arm_decode_field (given, 24, 24) == 0) 5578 && (arm_decode_field (given, 21, 21) == 0)) 5579 { 5580 return true; 5581 } 5582 else if ((arm_decode_field (given, 7, 8) == 3)) 5583 return true; 5584 else 5585 return false; 5586 5587 case MVE_VLDRB_T1: 5588 case MVE_VLDRH_T2: 5589 case MVE_VLDRW_T7: 5590 case MVE_VSTRB_T5: 5591 case MVE_VSTRH_T6: 5592 case MVE_VSTRW_T7: 5593 if ((arm_decode_field (given, 24, 24) == 0) 5594 && (arm_decode_field (given, 21, 21) == 0)) 5595 { 5596 return true; 5597 } 5598 else 5599 return false; 5600 5601 case MVE_VCVT_FP_FIX_VEC: 5602 return (arm_decode_field (given, 16, 21) & 0x38) == 0; 5603 5604 case MVE_VBIC_IMM: 5605 case MVE_VORR_IMM: 5606 { 5607 unsigned long cmode = arm_decode_field (given, 8, 11); 5608 5609 if ((cmode & 1) == 0) 5610 return true; 5611 else if ((cmode & 0xc) == 0xc) 5612 return true; 5613 else 5614 return false; 5615 } 5616 5617 case MVE_VMVN_IMM: 5618 { 5619 unsigned long cmode = arm_decode_field (given, 8, 11); 5620 5621 if (cmode == 0xe) 5622 return true; 5623 else if ((cmode & 0x9) == 1) 5624 return true; 5625 else if ((cmode & 0xd) == 9) 5626 return true; 5627 else 5628 return false; 5629 } 5630 5631 case MVE_VMOV_IMM_TO_VEC: 5632 if ((arm_decode_field (given, 5, 5) == 1) 5633 && (arm_decode_field (given, 8, 11) != 0xe)) 5634 return true; 5635 else 5636 return false; 5637 5638 case MVE_VMOVL: 5639 { 5640 unsigned long size = arm_decode_field (given, 19, 20); 5641 if ((size == 0) || (size == 3)) 5642 return true; 5643 else 5644 return false; 5645 } 5646 5647 case MVE_VMAXA: 5648 case MVE_VMINA: 5649 case MVE_VMAXV: 5650 case MVE_VMAXAV: 5651 case MVE_VMINV: 5652 case MVE_VMINAV: 5653 case MVE_VQRSHL_T2: 5654 case MVE_VQSHL_T1: 5655 case MVE_VRSHL_T2: 5656 case MVE_VSHL_T2: 5657 case MVE_VSHLL_T2: 5658 case MVE_VADDV: 5659 case MVE_VMOVN: 5660 case MVE_VQMOVUN: 5661 case MVE_VQMOVN: 5662 if (arm_decode_field (given, 18, 19) == 3) 5663 return true; 5664 else 5665 return false; 5666 5667 case MVE_VMLSLDAV: 5668 case MVE_VRMLSLDAVH: 5669 case MVE_VMLALDAV: 5670 case MVE_VADDLV: 5671 if (arm_decode_field (given, 20, 22) == 7) 5672 return true; 5673 else 5674 return false; 5675 5676 case MVE_VRMLALDAVH: 5677 if ((arm_decode_field (given, 20, 22) & 6) == 6) 5678 return true; 5679 else 5680 return false; 5681 5682 case MVE_VDWDUP: 5683 case MVE_VIWDUP: 5684 if ((arm_decode_field (given, 20, 21) == 3) 5685 || (arm_decode_field (given, 1, 3) == 7)) 5686 return true; 5687 else 5688 return false; 5689 5690 5691 case MVE_VSHLL_T1: 5692 if (arm_decode_field (given, 16, 18) == 0) 5693 { 5694 unsigned long sz = arm_decode_field (given, 19, 20); 5695 5696 if ((sz == 1) || (sz == 2)) 5697 return true; 5698 else 5699 return false; 5700 } 5701 else 5702 return false; 5703 5704 case MVE_VQSHL_T2: 5705 case MVE_VQSHLU_T3: 5706 case MVE_VRSHR: 5707 case MVE_VSHL_T1: 5708 case MVE_VSHR: 5709 case MVE_VSLI: 5710 case MVE_VSRI: 5711 if (arm_decode_field (given, 19, 21) == 0) 5712 return true; 5713 else 5714 return false; 5715 5716 case MVE_VCTP: 5717 if (arm_decode_field (given, 16, 19) == 0xf) 5718 return true; 5719 else 5720 return false; 5721 5722 case MVE_ASRLI: 5723 case MVE_ASRL: 5724 case MVE_LSLLI: 5725 case MVE_LSLL: 5726 case MVE_LSRL: 5727 case MVE_SQRSHRL: 5728 case MVE_SQSHLL: 5729 case MVE_SRSHRL: 5730 case MVE_UQRSHLL: 5731 case MVE_UQSHLL: 5732 case MVE_URSHRL: 5733 if (arm_decode_field (given, 9, 11) == 0x7) 5734 return true; 5735 else 5736 return false; 5737 5738 case MVE_CSINC: 5739 case MVE_CSINV: 5740 { 5741 unsigned long rm, rn; 5742 rm = arm_decode_field (given, 0, 3); 5743 rn = arm_decode_field (given, 16, 19); 5744 /* CSET/CSETM. */ 5745 if (rm == 0xf && rn == 0xf) 5746 return true; 5747 /* CINC/CINV. */ 5748 else if (rn == rm && rn != 0xf) 5749 return true; 5750 } 5751 /* Fall through. */ 5752 case MVE_CSEL: 5753 case MVE_CSNEG: 5754 if (arm_decode_field (given, 0, 3) == 0xd) 5755 return true; 5756 /* CNEG. */ 5757 else if (matched_insn == MVE_CSNEG) 5758 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19)) 5759 return true; 5760 return false; 5761 5762 default: 5763 case MVE_VADD_FP_T1: 5764 case MVE_VADD_FP_T2: 5765 case MVE_VADD_VEC_T1: 5766 return false; 5767 5768 } 5769 } 5770 5771 static void 5772 print_mve_vld_str_addr (struct disassemble_info *info, 5773 unsigned long given, 5774 enum mve_instructions matched_insn) 5775 { 5776 void *stream = info->stream; 5777 fprintf_styled_ftype func = info->fprintf_styled_func; 5778 5779 unsigned long p, w, gpr, imm, add, mod_imm; 5780 5781 imm = arm_decode_field (given, 0, 6); 5782 mod_imm = imm; 5783 5784 switch (matched_insn) 5785 { 5786 case MVE_VLDRB_T1: 5787 case MVE_VSTRB_T1: 5788 gpr = arm_decode_field (given, 16, 18); 5789 break; 5790 5791 case MVE_VLDRH_T2: 5792 case MVE_VSTRH_T2: 5793 gpr = arm_decode_field (given, 16, 18); 5794 mod_imm = imm << 1; 5795 break; 5796 5797 case MVE_VLDRH_T6: 5798 case MVE_VSTRH_T6: 5799 gpr = arm_decode_field (given, 16, 19); 5800 mod_imm = imm << 1; 5801 break; 5802 5803 case MVE_VLDRW_T7: 5804 case MVE_VSTRW_T7: 5805 gpr = arm_decode_field (given, 16, 19); 5806 mod_imm = imm << 2; 5807 break; 5808 5809 case MVE_VLDRB_T5: 5810 case MVE_VSTRB_T5: 5811 gpr = arm_decode_field (given, 16, 19); 5812 break; 5813 5814 default: 5815 return; 5816 } 5817 5818 p = arm_decode_field (given, 24, 24); 5819 w = arm_decode_field (given, 21, 21); 5820 5821 add = arm_decode_field (given, 23, 23); 5822 5823 char * add_sub; 5824 5825 /* Don't print anything for '+' as it is implied. */ 5826 if (add == 1) 5827 add_sub = ""; 5828 else 5829 add_sub = "-"; 5830 5831 func (stream, dis_style_text, "["); 5832 func (stream, dis_style_register, "%s", arm_regnames[gpr]); 5833 if (p == 1) 5834 { 5835 func (stream, dis_style_text, ", "); 5836 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm); 5837 /* Offset mode. */ 5838 if (w == 0) 5839 func (stream, dis_style_text, "]"); 5840 /* Pre-indexed mode. */ 5841 else 5842 func (stream, dis_style_text, "]!"); 5843 } 5844 else if ((p == 0) && (w == 1)) 5845 { 5846 /* Post-index mode. */ 5847 func (stream, dis_style_text, "], "); 5848 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm); 5849 } 5850 } 5851 5852 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN. 5853 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why 5854 this encoding is undefined. */ 5855 5856 static bool 5857 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn, 5858 enum mve_undefined *undefined_code) 5859 { 5860 *undefined_code = UNDEF_NONE; 5861 5862 switch (matched_insn) 5863 { 5864 case MVE_VDUP: 5865 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3) 5866 { 5867 *undefined_code = UNDEF_SIZE_3; 5868 return true; 5869 } 5870 else 5871 return false; 5872 5873 case MVE_VQADD_T1: 5874 case MVE_VQSUB_T1: 5875 case MVE_VMUL_VEC_T1: 5876 case MVE_VABD_VEC: 5877 case MVE_VADD_VEC_T1: 5878 case MVE_VSUB_VEC_T1: 5879 case MVE_VQDMULH_T1: 5880 case MVE_VQRDMULH_T2: 5881 case MVE_VRHADD: 5882 case MVE_VHADD_T1: 5883 case MVE_VHSUB_T1: 5884 if (arm_decode_field (given, 20, 21) == 3) 5885 { 5886 *undefined_code = UNDEF_SIZE_3; 5887 return true; 5888 } 5889 else 5890 return false; 5891 5892 case MVE_VLDRB_T1: 5893 if (arm_decode_field (given, 7, 8) == 3) 5894 { 5895 *undefined_code = UNDEF_SIZE_3; 5896 return true; 5897 } 5898 else 5899 return false; 5900 5901 case MVE_VLDRH_T2: 5902 if (arm_decode_field (given, 7, 8) <= 1) 5903 { 5904 *undefined_code = UNDEF_SIZE_LE_1; 5905 return true; 5906 } 5907 else 5908 return false; 5909 5910 case MVE_VSTRB_T1: 5911 if ((arm_decode_field (given, 7, 8) == 0)) 5912 { 5913 *undefined_code = UNDEF_SIZE_0; 5914 return true; 5915 } 5916 else 5917 return false; 5918 5919 case MVE_VSTRH_T2: 5920 if ((arm_decode_field (given, 7, 8) <= 1)) 5921 { 5922 *undefined_code = UNDEF_SIZE_LE_1; 5923 return true; 5924 } 5925 else 5926 return false; 5927 5928 case MVE_VLDRB_GATHER_T1: 5929 if (arm_decode_field (given, 7, 8) == 3) 5930 { 5931 *undefined_code = UNDEF_SIZE_3; 5932 return true; 5933 } 5934 else if ((arm_decode_field (given, 28, 28) == 0) 5935 && (arm_decode_field (given, 7, 8) == 0)) 5936 { 5937 *undefined_code = UNDEF_NOT_UNS_SIZE_0; 5938 return true; 5939 } 5940 else 5941 return false; 5942 5943 case MVE_VLDRH_GATHER_T2: 5944 if (arm_decode_field (given, 7, 8) == 3) 5945 { 5946 *undefined_code = UNDEF_SIZE_3; 5947 return true; 5948 } 5949 else if ((arm_decode_field (given, 28, 28) == 0) 5950 && (arm_decode_field (given, 7, 8) == 1)) 5951 { 5952 *undefined_code = UNDEF_NOT_UNS_SIZE_1; 5953 return true; 5954 } 5955 else if (arm_decode_field (given, 7, 8) == 0) 5956 { 5957 *undefined_code = UNDEF_SIZE_0; 5958 return true; 5959 } 5960 else 5961 return false; 5962 5963 case MVE_VLDRW_GATHER_T3: 5964 if (arm_decode_field (given, 7, 8) != 2) 5965 { 5966 *undefined_code = UNDEF_SIZE_NOT_2; 5967 return true; 5968 } 5969 else if (arm_decode_field (given, 28, 28) == 0) 5970 { 5971 *undefined_code = UNDEF_NOT_UNSIGNED; 5972 return true; 5973 } 5974 else 5975 return false; 5976 5977 case MVE_VLDRD_GATHER_T4: 5978 if (arm_decode_field (given, 7, 8) != 3) 5979 { 5980 *undefined_code = UNDEF_SIZE_NOT_3; 5981 return true; 5982 } 5983 else if (arm_decode_field (given, 28, 28) == 0) 5984 { 5985 *undefined_code = UNDEF_NOT_UNSIGNED; 5986 return true; 5987 } 5988 else 5989 return false; 5990 5991 case MVE_VSTRB_SCATTER_T1: 5992 if (arm_decode_field (given, 7, 8) == 3) 5993 { 5994 *undefined_code = UNDEF_SIZE_3; 5995 return true; 5996 } 5997 else 5998 return false; 5999 6000 case MVE_VSTRH_SCATTER_T2: 6001 { 6002 unsigned long size = arm_decode_field (given, 7, 8); 6003 if (size == 3) 6004 { 6005 *undefined_code = UNDEF_SIZE_3; 6006 return true; 6007 } 6008 else if (size == 0) 6009 { 6010 *undefined_code = UNDEF_SIZE_0; 6011 return true; 6012 } 6013 else 6014 return false; 6015 } 6016 6017 case MVE_VSTRW_SCATTER_T3: 6018 if (arm_decode_field (given, 7, 8) != 2) 6019 { 6020 *undefined_code = UNDEF_SIZE_NOT_2; 6021 return true; 6022 } 6023 else 6024 return false; 6025 6026 case MVE_VSTRD_SCATTER_T4: 6027 if (arm_decode_field (given, 7, 8) != 3) 6028 { 6029 *undefined_code = UNDEF_SIZE_NOT_3; 6030 return true; 6031 } 6032 else 6033 return false; 6034 6035 case MVE_VCVT_FP_FIX_VEC: 6036 { 6037 unsigned long imm6 = arm_decode_field (given, 16, 21); 6038 if ((imm6 & 0x20) == 0) 6039 { 6040 *undefined_code = UNDEF_VCVT_IMM6; 6041 return true; 6042 } 6043 6044 if ((arm_decode_field (given, 9, 9) == 0) 6045 && ((imm6 & 0x30) == 0x20)) 6046 { 6047 *undefined_code = UNDEF_VCVT_FSI_IMM6; 6048 return true; 6049 } 6050 6051 return false; 6052 } 6053 6054 case MVE_VNEG_FP: 6055 case MVE_VABS_FP: 6056 case MVE_VCVT_BETWEEN_FP_INT: 6057 case MVE_VCVT_FROM_FP_TO_INT: 6058 { 6059 unsigned long size = arm_decode_field (given, 18, 19); 6060 if (size == 0) 6061 { 6062 *undefined_code = UNDEF_SIZE_0; 6063 return true; 6064 } 6065 else if (size == 3) 6066 { 6067 *undefined_code = UNDEF_SIZE_3; 6068 return true; 6069 } 6070 else 6071 return false; 6072 } 6073 6074 case MVE_VMOV_VEC_LANE_TO_GP: 6075 { 6076 unsigned long op1 = arm_decode_field (given, 21, 22); 6077 unsigned long op2 = arm_decode_field (given, 5, 6); 6078 unsigned long u = arm_decode_field (given, 23, 23); 6079 6080 if ((op2 == 0) && (u == 1)) 6081 { 6082 if ((op1 == 0) || (op1 == 1)) 6083 { 6084 *undefined_code = UNDEF_BAD_U_OP1_OP2; 6085 return true; 6086 } 6087 else 6088 return false; 6089 } 6090 else if (op2 == 2) 6091 { 6092 if ((op1 == 0) || (op1 == 1)) 6093 { 6094 *undefined_code = UNDEF_BAD_OP1_OP2; 6095 return true; 6096 } 6097 else 6098 return false; 6099 } 6100 6101 return false; 6102 } 6103 6104 case MVE_VMOV_GP_TO_VEC_LANE: 6105 if (arm_decode_field (given, 5, 6) == 2) 6106 { 6107 unsigned long op1 = arm_decode_field (given, 21, 22); 6108 if ((op1 == 0) || (op1 == 1)) 6109 { 6110 *undefined_code = UNDEF_BAD_OP1_OP2; 6111 return true; 6112 } 6113 else 6114 return false; 6115 } 6116 else 6117 return false; 6118 6119 case MVE_VMOV_VEC_TO_VEC: 6120 if ((arm_decode_field (given, 5, 5) == 1) 6121 || (arm_decode_field (given, 22, 22) == 1)) 6122 return true; 6123 return false; 6124 6125 case MVE_VMOV_IMM_TO_VEC: 6126 if (arm_decode_field (given, 5, 5) == 0) 6127 { 6128 unsigned long cmode = arm_decode_field (given, 8, 11); 6129 6130 if (((cmode & 9) == 1) || ((cmode & 5) == 1)) 6131 { 6132 *undefined_code = UNDEF_OP_0_BAD_CMODE; 6133 return true; 6134 } 6135 else 6136 return false; 6137 } 6138 else 6139 return false; 6140 6141 case MVE_VSHLL_T2: 6142 case MVE_VMOVN: 6143 if (arm_decode_field (given, 18, 19) == 2) 6144 { 6145 *undefined_code = UNDEF_SIZE_2; 6146 return true; 6147 } 6148 else 6149 return false; 6150 6151 case MVE_VRMLALDAVH: 6152 case MVE_VMLADAV_T1: 6153 case MVE_VMLADAV_T2: 6154 case MVE_VMLALDAV: 6155 if ((arm_decode_field (given, 28, 28) == 1) 6156 && (arm_decode_field (given, 12, 12) == 1)) 6157 { 6158 *undefined_code = UNDEF_XCHG_UNS; 6159 return true; 6160 } 6161 else 6162 return false; 6163 6164 case MVE_VQSHRN: 6165 case MVE_VQSHRUN: 6166 case MVE_VSHLL_T1: 6167 case MVE_VSHRN: 6168 { 6169 unsigned long sz = arm_decode_field (given, 19, 20); 6170 if (sz == 1) 6171 return false; 6172 else if ((sz & 2) == 2) 6173 return false; 6174 else 6175 { 6176 *undefined_code = UNDEF_SIZE; 6177 return true; 6178 } 6179 } 6180 break; 6181 6182 case MVE_VQSHL_T2: 6183 case MVE_VQSHLU_T3: 6184 case MVE_VRSHR: 6185 case MVE_VSHL_T1: 6186 case MVE_VSHR: 6187 case MVE_VSLI: 6188 case MVE_VSRI: 6189 { 6190 unsigned long sz = arm_decode_field (given, 19, 21); 6191 if ((sz & 7) == 1) 6192 return false; 6193 else if ((sz & 6) == 2) 6194 return false; 6195 else if ((sz & 4) == 4) 6196 return false; 6197 else 6198 { 6199 *undefined_code = UNDEF_SIZE; 6200 return true; 6201 } 6202 } 6203 6204 case MVE_VQRSHRN: 6205 case MVE_VQRSHRUN: 6206 if (arm_decode_field (given, 19, 20) == 0) 6207 { 6208 *undefined_code = UNDEF_SIZE_0; 6209 return true; 6210 } 6211 else 6212 return false; 6213 6214 case MVE_VABS_VEC: 6215 if (arm_decode_field (given, 18, 19) == 3) 6216 { 6217 *undefined_code = UNDEF_SIZE_3; 6218 return true; 6219 } 6220 else 6221 return false; 6222 6223 case MVE_VQNEG: 6224 case MVE_VQABS: 6225 case MVE_VNEG_VEC: 6226 case MVE_VCLS: 6227 case MVE_VCLZ: 6228 if (arm_decode_field (given, 18, 19) == 3) 6229 { 6230 *undefined_code = UNDEF_SIZE_3; 6231 return true; 6232 } 6233 else 6234 return false; 6235 6236 case MVE_VREV16: 6237 if (arm_decode_field (given, 18, 19) == 0) 6238 return false; 6239 else 6240 { 6241 *undefined_code = UNDEF_SIZE_NOT_0; 6242 return true; 6243 } 6244 6245 case MVE_VREV32: 6246 { 6247 unsigned long size = arm_decode_field (given, 18, 19); 6248 if ((size & 2) == 2) 6249 { 6250 *undefined_code = UNDEF_SIZE_2; 6251 return true; 6252 } 6253 else 6254 return false; 6255 } 6256 6257 case MVE_VREV64: 6258 if (arm_decode_field (given, 18, 19) != 3) 6259 return false; 6260 else 6261 { 6262 *undefined_code = UNDEF_SIZE_3; 6263 return true; 6264 } 6265 6266 default: 6267 return false; 6268 } 6269 } 6270 6271 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN. 6272 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to 6273 why this encoding is unpredictable. */ 6274 6275 static bool 6276 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, 6277 enum mve_unpredictable *unpredictable_code) 6278 { 6279 *unpredictable_code = UNPRED_NONE; 6280 6281 switch (matched_insn) 6282 { 6283 case MVE_VCMP_FP_T2: 6284 case MVE_VPT_FP_T2: 6285 if ((arm_decode_field (given, 12, 12) == 0) 6286 && (arm_decode_field (given, 5, 5) == 1)) 6287 { 6288 *unpredictable_code = UNPRED_FCA_0_FCB_1; 6289 return true; 6290 } 6291 else 6292 return false; 6293 6294 case MVE_VPT_VEC_T4: 6295 case MVE_VPT_VEC_T5: 6296 case MVE_VPT_VEC_T6: 6297 case MVE_VCMP_VEC_T4: 6298 case MVE_VCMP_VEC_T5: 6299 case MVE_VCMP_VEC_T6: 6300 if (arm_decode_field (given, 0, 3) == 0xd) 6301 { 6302 *unpredictable_code = UNPRED_R13; 6303 return true; 6304 } 6305 else 6306 return false; 6307 6308 case MVE_VDUP: 6309 { 6310 unsigned long gpr = arm_decode_field (given, 12, 15); 6311 if (gpr == 0xd) 6312 { 6313 *unpredictable_code = UNPRED_R13; 6314 return true; 6315 } 6316 else if (gpr == 0xf) 6317 { 6318 *unpredictable_code = UNPRED_R15; 6319 return true; 6320 } 6321 6322 return false; 6323 } 6324 6325 case MVE_VQADD_T2: 6326 case MVE_VQSUB_T2: 6327 case MVE_VMUL_FP_T2: 6328 case MVE_VMUL_VEC_T2: 6329 case MVE_VMLA: 6330 case MVE_VBRSR: 6331 case MVE_VADD_FP_T2: 6332 case MVE_VSUB_FP_T2: 6333 case MVE_VADD_VEC_T2: 6334 case MVE_VSUB_VEC_T2: 6335 case MVE_VQRSHL_T2: 6336 case MVE_VQSHL_T1: 6337 case MVE_VRSHL_T2: 6338 case MVE_VSHL_T2: 6339 case MVE_VSHLC: 6340 case MVE_VQDMLAH: 6341 case MVE_VQRDMLAH: 6342 case MVE_VQDMLASH: 6343 case MVE_VQRDMLASH: 6344 case MVE_VQDMULH_T3: 6345 case MVE_VQRDMULH_T4: 6346 case MVE_VMLAS: 6347 case MVE_VFMA_FP_SCALAR: 6348 case MVE_VFMAS_FP_SCALAR: 6349 case MVE_VHADD_T2: 6350 case MVE_VHSUB_T2: 6351 { 6352 unsigned long gpr = arm_decode_field (given, 0, 3); 6353 if (gpr == 0xd) 6354 { 6355 *unpredictable_code = UNPRED_R13; 6356 return true; 6357 } 6358 else if (gpr == 0xf) 6359 { 6360 *unpredictable_code = UNPRED_R15; 6361 return true; 6362 } 6363 6364 return false; 6365 } 6366 6367 case MVE_VLD2: 6368 case MVE_VST2: 6369 { 6370 unsigned long rn = arm_decode_field (given, 16, 19); 6371 6372 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6373 { 6374 *unpredictable_code = UNPRED_R13_AND_WB; 6375 return true; 6376 } 6377 6378 if (rn == 0xf) 6379 { 6380 *unpredictable_code = UNPRED_R15; 6381 return true; 6382 } 6383 6384 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6) 6385 { 6386 *unpredictable_code = UNPRED_Q_GT_6; 6387 return true; 6388 } 6389 else 6390 return false; 6391 } 6392 6393 case MVE_VLD4: 6394 case MVE_VST4: 6395 { 6396 unsigned long rn = arm_decode_field (given, 16, 19); 6397 6398 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6399 { 6400 *unpredictable_code = UNPRED_R13_AND_WB; 6401 return true; 6402 } 6403 6404 if (rn == 0xf) 6405 { 6406 *unpredictable_code = UNPRED_R15; 6407 return true; 6408 } 6409 6410 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4) 6411 { 6412 *unpredictable_code = UNPRED_Q_GT_4; 6413 return true; 6414 } 6415 else 6416 return false; 6417 } 6418 6419 case MVE_VLDRB_T5: 6420 case MVE_VLDRH_T6: 6421 case MVE_VLDRW_T7: 6422 case MVE_VSTRB_T5: 6423 case MVE_VSTRH_T6: 6424 case MVE_VSTRW_T7: 6425 { 6426 unsigned long rn = arm_decode_field (given, 16, 19); 6427 6428 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6429 { 6430 *unpredictable_code = UNPRED_R13_AND_WB; 6431 return true; 6432 } 6433 else if (rn == 0xf) 6434 { 6435 *unpredictable_code = UNPRED_R15; 6436 return true; 6437 } 6438 else 6439 return false; 6440 } 6441 6442 case MVE_VLDRB_GATHER_T1: 6443 if (arm_decode_field (given, 0, 0) == 1) 6444 { 6445 *unpredictable_code = UNPRED_OS; 6446 return true; 6447 } 6448 6449 /* fall through. */ 6450 /* To handle common code with T2-T4 variants. */ 6451 case MVE_VLDRH_GATHER_T2: 6452 case MVE_VLDRW_GATHER_T3: 6453 case MVE_VLDRD_GATHER_T4: 6454 { 6455 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6456 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6457 6458 if (qd == qm) 6459 { 6460 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6461 return true; 6462 } 6463 6464 if (arm_decode_field (given, 16, 19) == 0xf) 6465 { 6466 *unpredictable_code = UNPRED_R15; 6467 return true; 6468 } 6469 6470 return false; 6471 } 6472 6473 case MVE_VLDRW_GATHER_T5: 6474 case MVE_VLDRD_GATHER_T6: 6475 { 6476 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6477 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7); 6478 6479 if (qd == qm) 6480 { 6481 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6482 return true; 6483 } 6484 else 6485 return false; 6486 } 6487 6488 case MVE_VSTRB_SCATTER_T1: 6489 if (arm_decode_field (given, 16, 19) == 0xf) 6490 { 6491 *unpredictable_code = UNPRED_R15; 6492 return true; 6493 } 6494 else if (arm_decode_field (given, 0, 0) == 1) 6495 { 6496 *unpredictable_code = UNPRED_OS; 6497 return true; 6498 } 6499 else 6500 return false; 6501 6502 case MVE_VSTRH_SCATTER_T2: 6503 case MVE_VSTRW_SCATTER_T3: 6504 case MVE_VSTRD_SCATTER_T4: 6505 if (arm_decode_field (given, 16, 19) == 0xf) 6506 { 6507 *unpredictable_code = UNPRED_R15; 6508 return true; 6509 } 6510 else 6511 return false; 6512 6513 case MVE_VMOV2_VEC_LANE_TO_GP: 6514 case MVE_VMOV2_GP_TO_VEC_LANE: 6515 case MVE_VCVT_BETWEEN_FP_INT: 6516 case MVE_VCVT_FROM_FP_TO_INT: 6517 { 6518 unsigned long rt = arm_decode_field (given, 0, 3); 6519 unsigned long rt2 = arm_decode_field (given, 16, 19); 6520 6521 if ((rt == 0xd) || (rt2 == 0xd)) 6522 { 6523 *unpredictable_code = UNPRED_R13; 6524 return true; 6525 } 6526 else if ((rt == 0xf) || (rt2 == 0xf)) 6527 { 6528 *unpredictable_code = UNPRED_R15; 6529 return true; 6530 } 6531 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE) 6532 { 6533 *unpredictable_code = UNPRED_GP_REGS_EQUAL; 6534 return true; 6535 } 6536 6537 return false; 6538 } 6539 6540 case MVE_VMAXV: 6541 case MVE_VMAXAV: 6542 case MVE_VMAXNMV_FP: 6543 case MVE_VMAXNMAV_FP: 6544 case MVE_VMINNMV_FP: 6545 case MVE_VMINNMAV_FP: 6546 case MVE_VMINV: 6547 case MVE_VMINAV: 6548 case MVE_VABAV: 6549 case MVE_VMOV_HFP_TO_GP: 6550 case MVE_VMOV_GP_TO_VEC_LANE: 6551 case MVE_VMOV_VEC_LANE_TO_GP: 6552 { 6553 unsigned long rda = arm_decode_field (given, 12, 15); 6554 if (rda == 0xd) 6555 { 6556 *unpredictable_code = UNPRED_R13; 6557 return true; 6558 } 6559 else if (rda == 0xf) 6560 { 6561 *unpredictable_code = UNPRED_R15; 6562 return true; 6563 } 6564 6565 return false; 6566 } 6567 6568 case MVE_VMULL_INT: 6569 { 6570 unsigned long Qd; 6571 unsigned long Qm; 6572 unsigned long Qn; 6573 6574 if (arm_decode_field (given, 20, 21) == 2) 6575 { 6576 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6577 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6578 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6579 6580 if ((Qd == Qn) || (Qd == Qm)) 6581 { 6582 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6583 return true; 6584 } 6585 else 6586 return false; 6587 } 6588 else 6589 return false; 6590 } 6591 6592 case MVE_VCMUL_FP: 6593 case MVE_VQDMULL_T1: 6594 { 6595 unsigned long Qd; 6596 unsigned long Qm; 6597 unsigned long Qn; 6598 6599 if (arm_decode_field (given, 28, 28) == 1) 6600 { 6601 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6602 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6603 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6604 6605 if ((Qd == Qn) || (Qd == Qm)) 6606 { 6607 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6608 return true; 6609 } 6610 else 6611 return false; 6612 } 6613 else 6614 return false; 6615 } 6616 6617 case MVE_VQDMULL_T2: 6618 { 6619 unsigned long gpr = arm_decode_field (given, 0, 3); 6620 if (gpr == 0xd) 6621 { 6622 *unpredictable_code = UNPRED_R13; 6623 return true; 6624 } 6625 else if (gpr == 0xf) 6626 { 6627 *unpredictable_code = UNPRED_R15; 6628 return true; 6629 } 6630 6631 if (arm_decode_field (given, 28, 28) == 1) 6632 { 6633 unsigned long Qd 6634 = arm_decode_field_multiple (given, 13, 15, 22, 22); 6635 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6636 6637 if (Qd == Qn) 6638 { 6639 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6640 return true; 6641 } 6642 else 6643 return false; 6644 } 6645 6646 return false; 6647 } 6648 6649 case MVE_VMLSLDAV: 6650 case MVE_VRMLSLDAVH: 6651 case MVE_VMLALDAV: 6652 case MVE_VADDLV: 6653 if (arm_decode_field (given, 20, 22) == 6) 6654 { 6655 *unpredictable_code = UNPRED_R13; 6656 return true; 6657 } 6658 else 6659 return false; 6660 6661 case MVE_VDWDUP: 6662 case MVE_VIWDUP: 6663 if (arm_decode_field (given, 1, 3) == 6) 6664 { 6665 *unpredictable_code = UNPRED_R13; 6666 return true; 6667 } 6668 else 6669 return false; 6670 6671 case MVE_VCADD_VEC: 6672 case MVE_VHCADD: 6673 { 6674 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6675 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6676 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2) 6677 { 6678 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6679 return true; 6680 } 6681 else 6682 return false; 6683 } 6684 6685 case MVE_VCADD_FP: 6686 { 6687 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6688 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6689 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1) 6690 { 6691 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6692 return true; 6693 } 6694 else 6695 return false; 6696 } 6697 6698 case MVE_VCMLA_FP: 6699 { 6700 unsigned long Qda; 6701 unsigned long Qm; 6702 unsigned long Qn; 6703 6704 if (arm_decode_field (given, 20, 20) == 1) 6705 { 6706 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22); 6707 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6708 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6709 6710 if ((Qda == Qn) || (Qda == Qm)) 6711 { 6712 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6713 return true; 6714 } 6715 else 6716 return false; 6717 } 6718 else 6719 return false; 6720 6721 } 6722 6723 case MVE_VCTP: 6724 if (arm_decode_field (given, 16, 19) == 0xd) 6725 { 6726 *unpredictable_code = UNPRED_R13; 6727 return true; 6728 } 6729 else 6730 return false; 6731 6732 case MVE_VREV64: 6733 { 6734 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6735 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6); 6736 6737 if (qd == qm) 6738 { 6739 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6740 return true; 6741 } 6742 else 6743 return false; 6744 } 6745 6746 case MVE_LSLL: 6747 case MVE_LSLLI: 6748 case MVE_LSRL: 6749 case MVE_ASRL: 6750 case MVE_ASRLI: 6751 case MVE_UQSHLL: 6752 case MVE_UQRSHLL: 6753 case MVE_URSHRL: 6754 case MVE_SRSHRL: 6755 case MVE_SQSHLL: 6756 case MVE_SQRSHRL: 6757 { 6758 unsigned long gpr = arm_decode_field (given, 9, 11); 6759 gpr = ((gpr << 1) | 1); 6760 if (gpr == 0xd) 6761 { 6762 *unpredictable_code = UNPRED_R13; 6763 return true; 6764 } 6765 else if (gpr == 0xf) 6766 { 6767 *unpredictable_code = UNPRED_R15; 6768 return true; 6769 } 6770 6771 return false; 6772 } 6773 6774 default: 6775 return false; 6776 } 6777 } 6778 6779 static void 6780 print_mve_vmov_index (struct disassemble_info *info, unsigned long given) 6781 { 6782 unsigned long op1 = arm_decode_field (given, 21, 22); 6783 unsigned long op2 = arm_decode_field (given, 5, 6); 6784 unsigned long h = arm_decode_field (given, 16, 16); 6785 unsigned long index_operand, esize, targetBeat, idx; 6786 void *stream = info->stream; 6787 fprintf_styled_ftype func = info->fprintf_styled_func; 6788 6789 if ((op1 & 0x2) == 0x2) 6790 { 6791 index_operand = op2; 6792 esize = 8; 6793 } 6794 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) 6795 { 6796 index_operand = op2 >> 1; 6797 esize = 16; 6798 } 6799 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) 6800 { 6801 index_operand = 0; 6802 esize = 32; 6803 } 6804 else 6805 { 6806 func (stream, dis_style_text, "<undefined index>"); 6807 return; 6808 } 6809 6810 targetBeat = (op1 & 0x1) | (h << 1); 6811 idx = index_operand + targetBeat * (32/esize); 6812 6813 func (stream, dis_style_immediate, "%lu", idx); 6814 } 6815 6816 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits 6817 in length and integer of floating-point type. */ 6818 static void 6819 print_simd_imm8 (struct disassemble_info *info, unsigned long given, 6820 unsigned int ibit_loc, const struct mopcode32 *insn) 6821 { 6822 int bits = 0; 6823 int cmode = (given >> 8) & 0xf; 6824 int op = (given >> 5) & 0x1; 6825 unsigned long value = 0, hival = 0; 6826 unsigned shift; 6827 int size = 0; 6828 int isfloat = 0; 6829 void *stream = info->stream; 6830 fprintf_styled_ftype func = info->fprintf_styled_func; 6831 6832 /* On Neon the 'i' bit is at bit 24, on mve it is 6833 at bit 28. */ 6834 bits |= ((given >> ibit_loc) & 1) << 7; 6835 bits |= ((given >> 16) & 7) << 4; 6836 bits |= ((given >> 0) & 15) << 0; 6837 6838 if (cmode < 8) 6839 { 6840 shift = (cmode >> 1) & 3; 6841 value = (unsigned long) bits << (8 * shift); 6842 size = 32; 6843 } 6844 else if (cmode < 12) 6845 { 6846 shift = (cmode >> 1) & 1; 6847 value = (unsigned long) bits << (8 * shift); 6848 size = 16; 6849 } 6850 else if (cmode < 14) 6851 { 6852 shift = (cmode & 1) + 1; 6853 value = (unsigned long) bits << (8 * shift); 6854 value |= (1ul << (8 * shift)) - 1; 6855 size = 32; 6856 } 6857 else if (cmode == 14) 6858 { 6859 if (op) 6860 { 6861 /* Bit replication into bytes. */ 6862 int ix; 6863 unsigned long mask; 6864 6865 value = 0; 6866 hival = 0; 6867 for (ix = 7; ix >= 0; ix--) 6868 { 6869 mask = ((bits >> ix) & 1) ? 0xff : 0; 6870 if (ix <= 3) 6871 value = (value << 8) | mask; 6872 else 6873 hival = (hival << 8) | mask; 6874 } 6875 size = 64; 6876 } 6877 else 6878 { 6879 /* Byte replication. */ 6880 value = (unsigned long) bits; 6881 size = 8; 6882 } 6883 } 6884 else if (!op) 6885 { 6886 /* Floating point encoding. */ 6887 int tmp; 6888 6889 value = (unsigned long) (bits & 0x7f) << 19; 6890 value |= (unsigned long) (bits & 0x80) << 24; 6891 tmp = bits & 0x40 ? 0x3c : 0x40; 6892 value |= (unsigned long) tmp << 24; 6893 size = 32; 6894 isfloat = 1; 6895 } 6896 else 6897 { 6898 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>", 6899 bits, cmode, op); 6900 size = 32; 6901 return; 6902 } 6903 6904 /* printU determines whether the immediate value should be printed as 6905 unsigned. */ 6906 unsigned printU = 0; 6907 switch (insn->mve_op) 6908 { 6909 default: 6910 break; 6911 /* We want this for instructions that don't have a 'signed' type. */ 6912 case MVE_VBIC_IMM: 6913 case MVE_VORR_IMM: 6914 case MVE_VMVN_IMM: 6915 case MVE_VMOV_IMM_TO_VEC: 6916 printU = 1; 6917 break; 6918 } 6919 switch (size) 6920 { 6921 case 8: 6922 func (stream, dis_style_immediate, "#%ld", value); 6923 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value); 6924 break; 6925 6926 case 16: 6927 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value); 6928 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value); 6929 break; 6930 6931 case 32: 6932 if (isfloat) 6933 { 6934 unsigned char valbytes[4]; 6935 double fvalue; 6936 6937 /* Do this a byte at a time so we don't have to 6938 worry about the host's endianness. */ 6939 valbytes[0] = value & 0xff; 6940 valbytes[1] = (value >> 8) & 0xff; 6941 valbytes[2] = (value >> 16) & 0xff; 6942 valbytes[3] = (value >> 24) & 0xff; 6943 6944 floatformat_to_double 6945 (& floatformat_ieee_single_little, valbytes, 6946 & fvalue); 6947 6948 func (stream, dis_style_immediate, "#%.7g", fvalue); 6949 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value); 6950 } 6951 else 6952 { 6953 func (stream, dis_style_immediate, 6954 printU ? "#%lu" : "#%ld", 6955 (long) (((value & 0x80000000L) != 0) 6956 && !printU 6957 ? value | ~0xffffffffL : value)); 6958 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value); 6959 } 6960 break; 6961 6962 case 64: 6963 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value); 6964 break; 6965 6966 default: 6967 abort (); 6968 } 6969 6970 } 6971 6972 static void 6973 print_mve_undefined (struct disassemble_info *info, 6974 enum mve_undefined undefined_code) 6975 { 6976 void *stream = info->stream; 6977 fprintf_styled_ftype func = info->fprintf_styled_func; 6978 /* Initialize REASON to avoid compiler warning about uninitialized 6979 usage, though such usage should be impossible. */ 6980 const char *reason = "??"; 6981 6982 switch (undefined_code) 6983 { 6984 case UNDEF_SIZE: 6985 reason = "illegal size"; 6986 break; 6987 6988 case UNDEF_SIZE_0: 6989 reason = "size equals zero"; 6990 break; 6991 6992 case UNDEF_SIZE_2: 6993 reason = "size equals two"; 6994 break; 6995 6996 case UNDEF_SIZE_3: 6997 reason = "size equals three"; 6998 break; 6999 7000 case UNDEF_SIZE_LE_1: 7001 reason = "size <= 1"; 7002 break; 7003 7004 case UNDEF_SIZE_NOT_0: 7005 reason = "size not equal to 0"; 7006 break; 7007 7008 case UNDEF_SIZE_NOT_2: 7009 reason = "size not equal to 2"; 7010 break; 7011 7012 case UNDEF_SIZE_NOT_3: 7013 reason = "size not equal to 3"; 7014 break; 7015 7016 case UNDEF_NOT_UNS_SIZE_0: 7017 reason = "not unsigned and size = zero"; 7018 break; 7019 7020 case UNDEF_NOT_UNS_SIZE_1: 7021 reason = "not unsigned and size = one"; 7022 break; 7023 7024 case UNDEF_NOT_UNSIGNED: 7025 reason = "not unsigned"; 7026 break; 7027 7028 case UNDEF_VCVT_IMM6: 7029 reason = "invalid imm6"; 7030 break; 7031 7032 case UNDEF_VCVT_FSI_IMM6: 7033 reason = "fsi = 0 and invalid imm6"; 7034 break; 7035 7036 case UNDEF_BAD_OP1_OP2: 7037 reason = "bad size with op2 = 2 and op1 = 0 or 1"; 7038 break; 7039 7040 case UNDEF_BAD_U_OP1_OP2: 7041 reason = "unsigned with op2 = 0 and op1 = 0 or 1"; 7042 break; 7043 7044 case UNDEF_OP_0_BAD_CMODE: 7045 reason = "op field equal 0 and bad cmode"; 7046 break; 7047 7048 case UNDEF_XCHG_UNS: 7049 reason = "exchange and unsigned together"; 7050 break; 7051 7052 case UNDEF_NONE: 7053 reason = ""; 7054 break; 7055 } 7056 7057 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason); 7058 } 7059 7060 static void 7061 print_mve_unpredictable (struct disassemble_info *info, 7062 enum mve_unpredictable unpredict_code) 7063 { 7064 void *stream = info->stream; 7065 fprintf_styled_ftype func = info->fprintf_styled_func; 7066 /* Initialize REASON to avoid compiler warning about uninitialized 7067 usage, though such usage should be impossible. */ 7068 const char *reason = "??"; 7069 7070 switch (unpredict_code) 7071 { 7072 case UNPRED_IT_BLOCK: 7073 reason = "mve instruction in it block"; 7074 break; 7075 7076 case UNPRED_FCA_0_FCB_1: 7077 reason = "condition bits, fca = 0 and fcb = 1"; 7078 break; 7079 7080 case UNPRED_R13: 7081 reason = "use of r13 (sp)"; 7082 break; 7083 7084 case UNPRED_R15: 7085 reason = "use of r15 (pc)"; 7086 break; 7087 7088 case UNPRED_Q_GT_4: 7089 reason = "start register block > r4"; 7090 break; 7091 7092 case UNPRED_Q_GT_6: 7093 reason = "start register block > r6"; 7094 break; 7095 7096 case UNPRED_R13_AND_WB: 7097 reason = "use of r13 and write back"; 7098 break; 7099 7100 case UNPRED_Q_REGS_EQUAL: 7101 reason = "same vector register used for destination and other operand"; 7102 break; 7103 7104 case UNPRED_OS: 7105 reason = "use of offset scaled"; 7106 break; 7107 7108 case UNPRED_GP_REGS_EQUAL: 7109 reason = "same general-purpose register used for both operands"; 7110 break; 7111 7112 case UNPRED_Q_REGS_EQ_AND_SIZE_1: 7113 reason = "use of identical q registers and size = 1"; 7114 break; 7115 7116 case UNPRED_Q_REGS_EQ_AND_SIZE_2: 7117 reason = "use of identical q registers and size = 1"; 7118 break; 7119 7120 case UNPRED_NONE: 7121 reason = ""; 7122 break; 7123 } 7124 7125 func (stream, dis_style_comment_start, "%s: %s", 7126 UNPREDICTABLE_INSTRUCTION, reason); 7127 } 7128 7129 /* Print register block operand for mve vld2/vld4/vst2/vld4. */ 7130 7131 static void 7132 print_mve_register_blocks (struct disassemble_info *info, 7133 unsigned long given, 7134 enum mve_instructions matched_insn) 7135 { 7136 void *stream = info->stream; 7137 fprintf_styled_ftype func = info->fprintf_styled_func; 7138 7139 unsigned long q_reg_start = arm_decode_field_multiple (given, 7140 13, 15, 7141 22, 22); 7142 switch (matched_insn) 7143 { 7144 case MVE_VLD2: 7145 case MVE_VST2: 7146 if (q_reg_start <= 6) 7147 { 7148 func (stream, dis_style_text, "{"); 7149 func (stream, dis_style_register, "q%ld", q_reg_start); 7150 func (stream, dis_style_text, ", "); 7151 func (stream, dis_style_register, "q%ld", q_reg_start + 1); 7152 func (stream, dis_style_text, "}"); 7153 } 7154 else 7155 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start); 7156 break; 7157 7158 case MVE_VLD4: 7159 case MVE_VST4: 7160 if (q_reg_start <= 4) 7161 { 7162 func (stream, dis_style_text, "{"); 7163 func (stream, dis_style_register, "q%ld", q_reg_start); 7164 func (stream, dis_style_text, ", "); 7165 func (stream, dis_style_register, "q%ld", q_reg_start + 1); 7166 func (stream, dis_style_text, ", "); 7167 func (stream, dis_style_register, "q%ld", q_reg_start + 2); 7168 func (stream, dis_style_text, ", "); 7169 func (stream, dis_style_register, "q%ld", q_reg_start + 3); 7170 func (stream, dis_style_text, "}"); 7171 } 7172 else 7173 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start); 7174 break; 7175 7176 default: 7177 break; 7178 } 7179 } 7180 7181 static void 7182 print_mve_rounding_mode (struct disassemble_info *info, 7183 unsigned long given, 7184 enum mve_instructions matched_insn) 7185 { 7186 void *stream = info->stream; 7187 fprintf_styled_ftype func = info->fprintf_styled_func; 7188 7189 switch (matched_insn) 7190 { 7191 case MVE_VCVT_FROM_FP_TO_INT: 7192 { 7193 switch (arm_decode_field (given, 8, 9)) 7194 { 7195 case 0: 7196 func (stream, dis_style_mnemonic, "a"); 7197 break; 7198 7199 case 1: 7200 func (stream, dis_style_mnemonic, "n"); 7201 break; 7202 7203 case 2: 7204 func (stream, dis_style_mnemonic, "p"); 7205 break; 7206 7207 case 3: 7208 func (stream, dis_style_mnemonic, "m"); 7209 break; 7210 7211 default: 7212 break; 7213 } 7214 } 7215 break; 7216 7217 case MVE_VRINT_FP: 7218 { 7219 switch (arm_decode_field (given, 7, 9)) 7220 { 7221 case 0: 7222 func (stream, dis_style_mnemonic, "n"); 7223 break; 7224 7225 case 1: 7226 func (stream, dis_style_mnemonic, "x"); 7227 break; 7228 7229 case 2: 7230 func (stream, dis_style_mnemonic, "a"); 7231 break; 7232 7233 case 3: 7234 func (stream, dis_style_mnemonic, "z"); 7235 break; 7236 7237 case 5: 7238 func (stream, dis_style_mnemonic, "m"); 7239 break; 7240 7241 case 7: 7242 func (stream, dis_style_mnemonic, "p"); 7243 7244 case 4: 7245 case 6: 7246 default: 7247 break; 7248 } 7249 } 7250 break; 7251 7252 default: 7253 break; 7254 } 7255 } 7256 7257 static void 7258 print_mve_vcvt_size (struct disassemble_info *info, 7259 unsigned long given, 7260 enum mve_instructions matched_insn) 7261 { 7262 unsigned long mode = 0; 7263 void *stream = info->stream; 7264 fprintf_styled_ftype func = info->fprintf_styled_func; 7265 7266 switch (matched_insn) 7267 { 7268 case MVE_VCVT_FP_FIX_VEC: 7269 { 7270 mode = (((given & 0x200) >> 7) 7271 | ((given & 0x10000000) >> 27) 7272 | ((given & 0x100) >> 8)); 7273 7274 switch (mode) 7275 { 7276 case 0: 7277 func (stream, dis_style_mnemonic, "f16.s16"); 7278 break; 7279 7280 case 1: 7281 func (stream, dis_style_mnemonic, "s16.f16"); 7282 break; 7283 7284 case 2: 7285 func (stream, dis_style_mnemonic, "f16.u16"); 7286 break; 7287 7288 case 3: 7289 func (stream, dis_style_mnemonic, "u16.f16"); 7290 break; 7291 7292 case 4: 7293 func (stream, dis_style_mnemonic, "f32.s32"); 7294 break; 7295 7296 case 5: 7297 func (stream, dis_style_mnemonic, "s32.f32"); 7298 break; 7299 7300 case 6: 7301 func (stream, dis_style_mnemonic, "f32.u32"); 7302 break; 7303 7304 case 7: 7305 func (stream, dis_style_mnemonic, "u32.f32"); 7306 break; 7307 7308 default: 7309 break; 7310 } 7311 break; 7312 } 7313 case MVE_VCVT_BETWEEN_FP_INT: 7314 { 7315 unsigned long size = arm_decode_field (given, 18, 19); 7316 unsigned long op = arm_decode_field (given, 7, 8); 7317 7318 if (size == 1) 7319 { 7320 switch (op) 7321 { 7322 case 0: 7323 func (stream, dis_style_mnemonic, "f16.s16"); 7324 break; 7325 7326 case 1: 7327 func (stream, dis_style_mnemonic, "f16.u16"); 7328 break; 7329 7330 case 2: 7331 func (stream, dis_style_mnemonic, "s16.f16"); 7332 break; 7333 7334 case 3: 7335 func (stream, dis_style_mnemonic, "u16.f16"); 7336 break; 7337 7338 default: 7339 break; 7340 } 7341 } 7342 else if (size == 2) 7343 { 7344 switch (op) 7345 { 7346 case 0: 7347 func (stream, dis_style_mnemonic, "f32.s32"); 7348 break; 7349 7350 case 1: 7351 func (stream, dis_style_mnemonic, "f32.u32"); 7352 break; 7353 7354 case 2: 7355 func (stream, dis_style_mnemonic, "s32.f32"); 7356 break; 7357 7358 case 3: 7359 func (stream, dis_style_mnemonic, "u32.f32"); 7360 break; 7361 } 7362 } 7363 } 7364 break; 7365 7366 case MVE_VCVT_FP_HALF_FP: 7367 { 7368 unsigned long op = arm_decode_field (given, 28, 28); 7369 if (op == 0) 7370 func (stream, dis_style_mnemonic, "f16.f32"); 7371 else if (op == 1) 7372 func (stream, dis_style_mnemonic, "f32.f16"); 7373 } 7374 break; 7375 7376 case MVE_VCVT_FROM_FP_TO_INT: 7377 { 7378 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19); 7379 7380 switch (size) 7381 { 7382 case 2: 7383 func (stream, dis_style_mnemonic, "s16.f16"); 7384 break; 7385 7386 case 3: 7387 func (stream, dis_style_mnemonic, "u16.f16"); 7388 break; 7389 7390 case 4: 7391 func (stream, dis_style_mnemonic, "s32.f32"); 7392 break; 7393 7394 case 5: 7395 func (stream, dis_style_mnemonic, "u32.f32"); 7396 break; 7397 7398 default: 7399 break; 7400 } 7401 } 7402 break; 7403 7404 default: 7405 break; 7406 } 7407 } 7408 7409 static void 7410 print_mve_rotate (struct disassemble_info *info, unsigned long rot, 7411 unsigned long rot_width) 7412 { 7413 void *stream = info->stream; 7414 fprintf_styled_ftype func = info->fprintf_styled_func; 7415 7416 if (rot_width == 1) 7417 { 7418 switch (rot) 7419 { 7420 case 0: 7421 func (stream, dis_style_immediate, "90"); 7422 break; 7423 case 1: 7424 func (stream, dis_style_immediate, "270"); 7425 break; 7426 default: 7427 break; 7428 } 7429 } 7430 else if (rot_width == 2) 7431 { 7432 switch (rot) 7433 { 7434 case 0: 7435 func (stream, dis_style_immediate, "0"); 7436 break; 7437 case 1: 7438 func (stream, dis_style_immediate, "90"); 7439 break; 7440 case 2: 7441 func (stream, dis_style_immediate, "180"); 7442 break; 7443 case 3: 7444 func (stream, dis_style_immediate, "270"); 7445 break; 7446 default: 7447 break; 7448 } 7449 } 7450 } 7451 7452 static void 7453 print_instruction_predicate (struct disassemble_info *info) 7454 { 7455 void *stream = info->stream; 7456 fprintf_styled_ftype func = info->fprintf_styled_func; 7457 7458 if (vpt_block_state.next_pred_state == PRED_THEN) 7459 func (stream, dis_style_mnemonic, "t"); 7460 else if (vpt_block_state.next_pred_state == PRED_ELSE) 7461 func (stream, dis_style_mnemonic, "e"); 7462 } 7463 7464 static void 7465 print_mve_size (struct disassemble_info *info, 7466 unsigned long size, 7467 enum mve_instructions matched_insn) 7468 { 7469 void *stream = info->stream; 7470 fprintf_styled_ftype func = info->fprintf_styled_func; 7471 7472 switch (matched_insn) 7473 { 7474 case MVE_VABAV: 7475 case MVE_VABD_VEC: 7476 case MVE_VABS_FP: 7477 case MVE_VABS_VEC: 7478 case MVE_VADD_VEC_T1: 7479 case MVE_VADD_VEC_T2: 7480 case MVE_VADDV: 7481 case MVE_VBRSR: 7482 case MVE_VCADD_VEC: 7483 case MVE_VCLS: 7484 case MVE_VCLZ: 7485 case MVE_VCMP_VEC_T1: 7486 case MVE_VCMP_VEC_T2: 7487 case MVE_VCMP_VEC_T3: 7488 case MVE_VCMP_VEC_T4: 7489 case MVE_VCMP_VEC_T5: 7490 case MVE_VCMP_VEC_T6: 7491 case MVE_VCTP: 7492 case MVE_VDDUP: 7493 case MVE_VDWDUP: 7494 case MVE_VHADD_T1: 7495 case MVE_VHADD_T2: 7496 case MVE_VHCADD: 7497 case MVE_VHSUB_T1: 7498 case MVE_VHSUB_T2: 7499 case MVE_VIDUP: 7500 case MVE_VIWDUP: 7501 case MVE_VLD2: 7502 case MVE_VLD4: 7503 case MVE_VLDRB_GATHER_T1: 7504 case MVE_VLDRH_GATHER_T2: 7505 case MVE_VLDRW_GATHER_T3: 7506 case MVE_VLDRD_GATHER_T4: 7507 case MVE_VLDRB_T1: 7508 case MVE_VLDRH_T2: 7509 case MVE_VMAX: 7510 case MVE_VMAXA: 7511 case MVE_VMAXV: 7512 case MVE_VMAXAV: 7513 case MVE_VMIN: 7514 case MVE_VMINA: 7515 case MVE_VMINV: 7516 case MVE_VMINAV: 7517 case MVE_VMLA: 7518 case MVE_VMLAS: 7519 case MVE_VMUL_VEC_T1: 7520 case MVE_VMUL_VEC_T2: 7521 case MVE_VMULH: 7522 case MVE_VRMULH: 7523 case MVE_VMULL_INT: 7524 case MVE_VNEG_FP: 7525 case MVE_VNEG_VEC: 7526 case MVE_VPT_VEC_T1: 7527 case MVE_VPT_VEC_T2: 7528 case MVE_VPT_VEC_T3: 7529 case MVE_VPT_VEC_T4: 7530 case MVE_VPT_VEC_T5: 7531 case MVE_VPT_VEC_T6: 7532 case MVE_VQABS: 7533 case MVE_VQADD_T1: 7534 case MVE_VQADD_T2: 7535 case MVE_VQDMLADH: 7536 case MVE_VQRDMLADH: 7537 case MVE_VQDMLAH: 7538 case MVE_VQRDMLAH: 7539 case MVE_VQDMLASH: 7540 case MVE_VQRDMLASH: 7541 case MVE_VQDMLSDH: 7542 case MVE_VQRDMLSDH: 7543 case MVE_VQDMULH_T1: 7544 case MVE_VQRDMULH_T2: 7545 case MVE_VQDMULH_T3: 7546 case MVE_VQRDMULH_T4: 7547 case MVE_VQNEG: 7548 case MVE_VQRSHL_T1: 7549 case MVE_VQRSHL_T2: 7550 case MVE_VQSHL_T1: 7551 case MVE_VQSHL_T4: 7552 case MVE_VQSUB_T1: 7553 case MVE_VQSUB_T2: 7554 case MVE_VREV32: 7555 case MVE_VREV64: 7556 case MVE_VRHADD: 7557 case MVE_VRINT_FP: 7558 case MVE_VRSHL_T1: 7559 case MVE_VRSHL_T2: 7560 case MVE_VSHL_T2: 7561 case MVE_VSHL_T3: 7562 case MVE_VSHLL_T2: 7563 case MVE_VST2: 7564 case MVE_VST4: 7565 case MVE_VSTRB_SCATTER_T1: 7566 case MVE_VSTRH_SCATTER_T2: 7567 case MVE_VSTRW_SCATTER_T3: 7568 case MVE_VSTRB_T1: 7569 case MVE_VSTRH_T2: 7570 case MVE_VSUB_VEC_T1: 7571 case MVE_VSUB_VEC_T2: 7572 if (size <= 3) 7573 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]); 7574 else 7575 func (stream, dis_style_text, "<undef size>"); 7576 break; 7577 7578 case MVE_VABD_FP: 7579 case MVE_VADD_FP_T1: 7580 case MVE_VADD_FP_T2: 7581 case MVE_VSUB_FP_T1: 7582 case MVE_VSUB_FP_T2: 7583 case MVE_VCMP_FP_T1: 7584 case MVE_VCMP_FP_T2: 7585 case MVE_VFMA_FP_SCALAR: 7586 case MVE_VFMA_FP: 7587 case MVE_VFMS_FP: 7588 case MVE_VFMAS_FP_SCALAR: 7589 case MVE_VMAXNM_FP: 7590 case MVE_VMAXNMA_FP: 7591 case MVE_VMAXNMV_FP: 7592 case MVE_VMAXNMAV_FP: 7593 case MVE_VMINNM_FP: 7594 case MVE_VMINNMA_FP: 7595 case MVE_VMINNMV_FP: 7596 case MVE_VMINNMAV_FP: 7597 case MVE_VMUL_FP_T1: 7598 case MVE_VMUL_FP_T2: 7599 case MVE_VPT_FP_T1: 7600 case MVE_VPT_FP_T2: 7601 if (size == 0) 7602 func (stream, dis_style_mnemonic, "32"); 7603 else if (size == 1) 7604 func (stream, dis_style_mnemonic, "16"); 7605 break; 7606 7607 case MVE_VCADD_FP: 7608 case MVE_VCMLA_FP: 7609 case MVE_VCMUL_FP: 7610 case MVE_VMLADAV_T1: 7611 case MVE_VMLALDAV: 7612 case MVE_VMLSDAV_T1: 7613 case MVE_VMLSLDAV: 7614 case MVE_VMOVN: 7615 case MVE_VQDMULL_T1: 7616 case MVE_VQDMULL_T2: 7617 case MVE_VQMOVN: 7618 case MVE_VQMOVUN: 7619 if (size == 0) 7620 func (stream, dis_style_mnemonic, "16"); 7621 else if (size == 1) 7622 func (stream, dis_style_mnemonic, "32"); 7623 break; 7624 7625 case MVE_VMOVL: 7626 if (size == 1) 7627 func (stream, dis_style_mnemonic, "8"); 7628 else if (size == 2) 7629 func (stream, dis_style_mnemonic, "16"); 7630 break; 7631 7632 case MVE_VDUP: 7633 switch (size) 7634 { 7635 case 0: 7636 func (stream, dis_style_mnemonic, "32"); 7637 break; 7638 case 1: 7639 func (stream, dis_style_mnemonic, "16"); 7640 break; 7641 case 2: 7642 func (stream, dis_style_mnemonic, "8"); 7643 break; 7644 default: 7645 break; 7646 } 7647 break; 7648 7649 case MVE_VMOV_GP_TO_VEC_LANE: 7650 case MVE_VMOV_VEC_LANE_TO_GP: 7651 switch (size) 7652 { 7653 case 0: case 4: 7654 func (stream, dis_style_mnemonic, "32"); 7655 break; 7656 7657 case 1: case 3: 7658 case 5: case 7: 7659 func (stream, dis_style_mnemonic, "16"); 7660 break; 7661 7662 case 8: case 9: case 10: case 11: 7663 case 12: case 13: case 14: case 15: 7664 func (stream, dis_style_mnemonic, "8"); 7665 break; 7666 7667 default: 7668 break; 7669 } 7670 break; 7671 7672 case MVE_VMOV_IMM_TO_VEC: 7673 switch (size) 7674 { 7675 case 0: case 4: case 8: 7676 case 12: case 24: case 26: 7677 func (stream, dis_style_mnemonic, "i32"); 7678 break; 7679 case 16: case 20: 7680 func (stream, dis_style_mnemonic, "i16"); 7681 break; 7682 case 28: 7683 func (stream, dis_style_mnemonic, "i8"); 7684 break; 7685 case 29: 7686 func (stream, dis_style_mnemonic, "i64"); 7687 break; 7688 case 30: 7689 func (stream, dis_style_mnemonic, "f32"); 7690 break; 7691 default: 7692 break; 7693 } 7694 break; 7695 7696 case MVE_VMULL_POLY: 7697 if (size == 0) 7698 func (stream, dis_style_mnemonic, "p8"); 7699 else if (size == 1) 7700 func (stream, dis_style_mnemonic, "p16"); 7701 break; 7702 7703 case MVE_VMVN_IMM: 7704 switch (size) 7705 { 7706 case 0: case 2: case 4: 7707 case 6: case 12: case 13: 7708 func (stream, dis_style_mnemonic, "32"); 7709 break; 7710 7711 case 8: case 10: 7712 func (stream, dis_style_mnemonic, "16"); 7713 break; 7714 7715 default: 7716 break; 7717 } 7718 break; 7719 7720 case MVE_VBIC_IMM: 7721 case MVE_VORR_IMM: 7722 switch (size) 7723 { 7724 case 1: case 3: 7725 case 5: case 7: 7726 func (stream, dis_style_mnemonic, "32"); 7727 break; 7728 7729 case 9: case 11: 7730 func (stream, dis_style_mnemonic, "16"); 7731 break; 7732 7733 default: 7734 break; 7735 } 7736 break; 7737 7738 case MVE_VQSHRN: 7739 case MVE_VQSHRUN: 7740 case MVE_VQRSHRN: 7741 case MVE_VQRSHRUN: 7742 case MVE_VRSHRN: 7743 case MVE_VSHRN: 7744 { 7745 switch (size) 7746 { 7747 case 1: 7748 func (stream, dis_style_mnemonic, "16"); 7749 break; 7750 7751 case 2: case 3: 7752 func (stream, dis_style_mnemonic, "32"); 7753 break; 7754 7755 default: 7756 break; 7757 } 7758 } 7759 break; 7760 7761 case MVE_VQSHL_T2: 7762 case MVE_VQSHLU_T3: 7763 case MVE_VRSHR: 7764 case MVE_VSHL_T1: 7765 case MVE_VSHLL_T1: 7766 case MVE_VSHR: 7767 case MVE_VSLI: 7768 case MVE_VSRI: 7769 { 7770 switch (size) 7771 { 7772 case 1: 7773 func (stream, dis_style_mnemonic, "8"); 7774 break; 7775 7776 case 2: case 3: 7777 func (stream, dis_style_mnemonic, "16"); 7778 break; 7779 7780 case 4: case 5: case 6: case 7: 7781 func (stream, dis_style_mnemonic, "32"); 7782 break; 7783 7784 default: 7785 break; 7786 } 7787 } 7788 break; 7789 7790 default: 7791 break; 7792 } 7793 } 7794 7795 /* Return true if INSN is a shift insn with an immediate shift amount 7796 which needs decoding as per print_mve_shift_n. */ 7797 7798 static bool 7799 mve_shift_insn_p (enum mve_instructions insn) 7800 { 7801 switch (insn) 7802 { 7803 case MVE_VQSHL_T2: 7804 case MVE_VQSHLU_T3: 7805 case MVE_VQSHRN: 7806 case MVE_VQSHRUN: 7807 case MVE_VQRSHRN: 7808 case MVE_VQRSHRUN: 7809 case MVE_VRSHR: 7810 case MVE_VRSHRN: 7811 case MVE_VSHL_T1: 7812 case MVE_VSHLL_T1: 7813 case MVE_VSHR: 7814 case MVE_VSHRN: 7815 case MVE_VSLI: 7816 case MVE_VSRI: 7817 return true; 7818 default: 7819 return false; 7820 } 7821 } 7822 7823 static void 7824 print_mve_shift_n (struct disassemble_info *info, long given, 7825 enum mve_instructions matched_insn) 7826 { 7827 void *stream = info->stream; 7828 fprintf_styled_ftype func = info->fprintf_styled_func; 7829 7830 int startAt0 7831 = matched_insn == MVE_VQSHL_T2 7832 || matched_insn == MVE_VQSHLU_T3 7833 || matched_insn == MVE_VSHL_T1 7834 || matched_insn == MVE_VSHLL_T1 7835 || matched_insn == MVE_VSLI; 7836 7837 unsigned imm6 = (given & 0x3f0000) >> 16; 7838 7839 if (matched_insn == MVE_VSHLL_T1) 7840 imm6 &= 0x1f; 7841 7842 unsigned shiftAmount = 0; 7843 if ((imm6 & 0x20) != 0) 7844 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6; 7845 else if ((imm6 & 0x10) != 0) 7846 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6; 7847 else if ((imm6 & 0x08) != 0) 7848 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6; 7849 else 7850 print_mve_undefined (info, UNDEF_SIZE_0); 7851 7852 func (stream, dis_style_immediate, "%u", shiftAmount); 7853 } 7854 7855 static void 7856 print_vec_condition (struct disassemble_info *info, long given, 7857 enum mve_instructions matched_insn) 7858 { 7859 void *stream = info->stream; 7860 fprintf_styled_ftype func = info->fprintf_styled_func; 7861 long vec_cond = 0; 7862 7863 switch (matched_insn) 7864 { 7865 case MVE_VPT_FP_T1: 7866 case MVE_VCMP_FP_T1: 7867 vec_cond = (((given & 0x1000) >> 10) 7868 | ((given & 1) << 1) 7869 | ((given & 0x0080) >> 7)); 7870 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7871 break; 7872 7873 case MVE_VPT_FP_T2: 7874 case MVE_VCMP_FP_T2: 7875 vec_cond = (((given & 0x1000) >> 10) 7876 | ((given & 0x0020) >> 4) 7877 | ((given & 0x0080) >> 7)); 7878 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7879 break; 7880 7881 case MVE_VPT_VEC_T1: 7882 case MVE_VCMP_VEC_T1: 7883 vec_cond = (given & 0x0080) >> 7; 7884 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7885 break; 7886 7887 case MVE_VPT_VEC_T2: 7888 case MVE_VCMP_VEC_T2: 7889 vec_cond = 2 | ((given & 0x0080) >> 7); 7890 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7891 break; 7892 7893 case MVE_VPT_VEC_T3: 7894 case MVE_VCMP_VEC_T3: 7895 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7); 7896 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7897 break; 7898 7899 case MVE_VPT_VEC_T4: 7900 case MVE_VCMP_VEC_T4: 7901 vec_cond = (given & 0x0080) >> 7; 7902 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7903 break; 7904 7905 case MVE_VPT_VEC_T5: 7906 case MVE_VCMP_VEC_T5: 7907 vec_cond = 2 | ((given & 0x0080) >> 7); 7908 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7909 break; 7910 7911 case MVE_VPT_VEC_T6: 7912 case MVE_VCMP_VEC_T6: 7913 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7); 7914 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7915 break; 7916 7917 case MVE_NONE: 7918 case MVE_VPST: 7919 default: 7920 break; 7921 } 7922 } 7923 7924 #define W_BIT 21 7925 #define I_BIT 22 7926 #define U_BIT 23 7927 #define P_BIT 24 7928 7929 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 7930 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 7931 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 7932 #define PRE_BIT_SET (given & (1 << P_BIT)) 7933 7934 /* The assembler string for an instruction can include %{X:...%} patterns, 7935 where the 'X' is one of the characters understood by this function. 7936 7937 This function takes the X character, and returns a new style. This new 7938 style will be used by the caller to temporarily change the current base 7939 style. */ 7940 7941 static enum disassembler_style 7942 decode_base_style (const char x) 7943 { 7944 switch (x) 7945 { 7946 case 'A': return dis_style_address; 7947 case 'B': return dis_style_sub_mnemonic; 7948 case 'C': return dis_style_comment_start; 7949 case 'D': return dis_style_assembler_directive; 7950 case 'I': return dis_style_immediate; 7951 case 'M': return dis_style_mnemonic; 7952 case 'O': return dis_style_address_offset; 7953 case 'R': return dis_style_register; 7954 case 'S': return dis_style_symbol; 7955 case 'T': return dis_style_text; 7956 default: 7957 abort (); 7958 } 7959 } 7960 7961 /* Print one coprocessor instruction on INFO->STREAM. 7962 Return TRUE if the instuction matched, FALSE if this is not a 7963 recognised coprocessor instruction. */ 7964 7965 static bool 7966 print_insn_coprocessor_1 (const struct sopcode32 *opcodes, 7967 bfd_vma pc, 7968 struct disassemble_info *info, 7969 long given, 7970 bool thumb) 7971 { 7972 const struct sopcode32 *insn; 7973 void *stream = info->stream; 7974 fprintf_styled_ftype func = info->fprintf_styled_func; 7975 unsigned long mask; 7976 unsigned long value = 0; 7977 int cond; 7978 int cp_num; 7979 struct arm_private_data *private_data = info->private_data; 7980 arm_feature_set allowed_arches = ARM_ARCH_NONE; 7981 arm_feature_set arm_ext_v8_1m_main = 7982 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 7983 enum disassembler_style base_style = dis_style_mnemonic; 7984 enum disassembler_style old_base_style = base_style; 7985 7986 allowed_arches = private_data->features; 7987 7988 for (insn = opcodes; insn->assembler; insn++) 7989 { 7990 unsigned long u_reg = 16; 7991 bool is_unpredictable = false; 7992 signed long value_in_comment = 0; 7993 const char *c; 7994 7995 if (ARM_FEATURE_ZERO (insn->arch)) 7996 switch (insn->value) 7997 { 7998 case SENTINEL_IWMMXT_START: 7999 if (info->mach != bfd_mach_arm_XScale 8000 && info->mach != bfd_mach_arm_iWMMXt 8001 && info->mach != bfd_mach_arm_iWMMXt2) 8002 do 8003 insn++; 8004 while ((! ARM_FEATURE_ZERO (insn->arch)) 8005 && insn->value != SENTINEL_IWMMXT_END); 8006 continue; 8007 8008 case SENTINEL_IWMMXT_END: 8009 continue; 8010 8011 case SENTINEL_GENERIC_START: 8012 allowed_arches = private_data->features; 8013 continue; 8014 8015 default: 8016 abort (); 8017 } 8018 8019 mask = insn->mask; 8020 value = insn->value; 8021 cp_num = (given >> 8) & 0xf; 8022 8023 if (thumb) 8024 { 8025 /* The high 4 bits are 0xe for Arm conditional instructions, and 8026 0xe for arm unconditional instructions. The rest of the 8027 encoding is the same. */ 8028 mask |= 0xf0000000; 8029 value |= 0xe0000000; 8030 if (ifthen_state) 8031 cond = IFTHEN_COND; 8032 else 8033 cond = COND_UNCOND; 8034 } 8035 else 8036 { 8037 /* Only match unconditional instuctions against unconditional 8038 patterns. */ 8039 if ((given & 0xf0000000) == 0xf0000000) 8040 { 8041 mask |= 0xf0000000; 8042 cond = COND_UNCOND; 8043 } 8044 else 8045 { 8046 cond = (given >> 28) & 0xf; 8047 if (cond == 0xe) 8048 cond = COND_UNCOND; 8049 } 8050 } 8051 8052 if ((insn->isa == T32 && !thumb) 8053 || (insn->isa == ARM && thumb)) 8054 continue; 8055 8056 if ((given & mask) != value) 8057 continue; 8058 8059 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 8060 continue; 8061 8062 if (insn->value == 0xfe000010 /* mcr2 */ 8063 || insn->value == 0xfe100010 /* mrc2 */ 8064 || insn->value == 0xfc100000 /* ldc2 */ 8065 || insn->value == 0xfc000000) /* stc2 */ 8066 { 8067 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8068 is_unpredictable = true; 8069 8070 /* Armv8.1-M Mainline FP & MVE instructions. */ 8071 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8072 && !ARM_CPU_IS_ANY (allowed_arches) 8073 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8074 continue; 8075 8076 } 8077 else if (insn->value == 0x0e000000 /* cdp */ 8078 || insn->value == 0xfe000000 /* cdp2 */ 8079 || insn->value == 0x0e000010 /* mcr */ 8080 || insn->value == 0x0e100010 /* mrc */ 8081 || insn->value == 0x0c100000 /* ldc */ 8082 || insn->value == 0x0c000000) /* stc */ 8083 { 8084 /* Floating-point instructions. */ 8085 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8086 continue; 8087 8088 /* Armv8.1-M Mainline FP & MVE instructions. */ 8089 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8090 && !ARM_CPU_IS_ANY (allowed_arches) 8091 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8092 continue; 8093 } 8094 else if ((insn->value == 0xec100f80 /* vldr (system register) */ 8095 || insn->value == 0xec000f80) /* vstr (system register) */ 8096 && arm_decode_field (given, 24, 24) == 0 8097 && arm_decode_field (given, 21, 21) == 0) 8098 /* If the P and W bits are both 0 then these encodings match the MVE 8099 VLDR and VSTR instructions, these are in a different table, so we 8100 don't let it match here. */ 8101 continue; 8102 8103 for (c = insn->assembler; *c; c++) 8104 { 8105 if (*c == '%') 8106 { 8107 const char mod = *++c; 8108 8109 switch (mod) 8110 { 8111 case '{': 8112 ++c; 8113 if (*c == '\0') 8114 abort (); 8115 old_base_style = base_style; 8116 base_style = decode_base_style (*c); 8117 ++c; 8118 if (*c != ':') 8119 abort (); 8120 break; 8121 8122 case '}': 8123 base_style = old_base_style; 8124 break; 8125 8126 case '%': 8127 func (stream, base_style, "%%"); 8128 break; 8129 8130 case 'A': 8131 case 'K': 8132 { 8133 int rn = (given >> 16) & 0xf; 8134 bfd_vma offset = given & 0xff; 8135 8136 if (mod == 'K') 8137 offset = given & 0x7f; 8138 8139 func (stream, dis_style_text, "["); 8140 func (stream, dis_style_register, "%s", 8141 arm_regnames [(given >> 16) & 0xf]); 8142 8143 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 8144 { 8145 /* Not unindexed. The offset is scaled. */ 8146 if (cp_num == 9) 8147 /* vldr.16/vstr.16 will shift the address 8148 left by 1 bit only. */ 8149 offset = offset * 2; 8150 else 8151 offset = offset * 4; 8152 8153 if (NEGATIVE_BIT_SET) 8154 offset = - offset; 8155 if (rn != 15) 8156 value_in_comment = offset; 8157 } 8158 8159 if (PRE_BIT_SET) 8160 { 8161 if (offset) 8162 { 8163 func (stream, dis_style_text, ", "); 8164 func (stream, dis_style_immediate, "#%d", 8165 (int) offset); 8166 func (stream, dis_style_text, "]%s", 8167 WRITEBACK_BIT_SET ? "!" : ""); 8168 } 8169 else if (NEGATIVE_BIT_SET) 8170 { 8171 func (stream, dis_style_text, ", "); 8172 func (stream, dis_style_immediate, "#-0"); 8173 func (stream, dis_style_text, "]"); 8174 } 8175 else 8176 func (stream, dis_style_text, "]"); 8177 } 8178 else 8179 { 8180 func (stream, dis_style_text, "]"); 8181 8182 if (WRITEBACK_BIT_SET) 8183 { 8184 if (offset) 8185 { 8186 func (stream, dis_style_text, ", "); 8187 func (stream, dis_style_immediate, 8188 "#%d", (int) offset); 8189 } 8190 else if (NEGATIVE_BIT_SET) 8191 { 8192 func (stream, dis_style_text, ", "); 8193 func (stream, dis_style_immediate, "#-0"); 8194 } 8195 } 8196 else 8197 { 8198 func (stream, dis_style_text, ", {"); 8199 func (stream, dis_style_immediate, "%s%d", 8200 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 8201 (int) offset); 8202 func (stream, dis_style_text, "}"); 8203 value_in_comment = offset; 8204 } 8205 } 8206 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 8207 { 8208 func (stream, dis_style_comment_start, "\t@ "); 8209 /* For unaligned PCs, apply off-by-alignment 8210 correction. */ 8211 info->print_address_func (offset + pc 8212 + info->bytes_per_chunk * 2 8213 - (pc & 3), 8214 info); 8215 } 8216 } 8217 break; 8218 8219 case 'B': 8220 { 8221 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 8222 int offset = (given >> 1) & 0x3f; 8223 8224 func (stream, dis_style_text, "{"); 8225 if (offset == 1) 8226 func (stream, dis_style_register, "d%d", regno); 8227 else if (regno + offset > 32) 8228 { 8229 func (stream, dis_style_register, "d%d", regno); 8230 func (stream, dis_style_text, "-<overflow reg d%d>", 8231 regno + offset - 1); 8232 } 8233 else 8234 { 8235 func (stream, dis_style_register, "d%d", regno); 8236 func (stream, dis_style_text, "-"); 8237 func (stream, dis_style_register, "d%d", 8238 regno + offset - 1); 8239 } 8240 func (stream, dis_style_text, "}"); 8241 } 8242 break; 8243 8244 case 'C': 8245 { 8246 bool single = ((given >> 8) & 1) == 0; 8247 char reg_prefix = single ? 's' : 'd'; 8248 int Dreg = (given >> 22) & 0x1; 8249 int Vdreg = (given >> 12) & 0xf; 8250 int reg = single ? ((Vdreg << 1) | Dreg) 8251 : ((Dreg << 4) | Vdreg); 8252 int num = (given >> (single ? 0 : 1)) & 0x7f; 8253 int maxreg = single ? 31 : 15; 8254 int topreg = reg + num - 1; 8255 8256 func (stream, dis_style_text, "{"); 8257 if (!num) 8258 { 8259 /* Nothing. */ 8260 } 8261 else if (num == 1) 8262 { 8263 func (stream, dis_style_register, 8264 "%c%d", reg_prefix, reg); 8265 func (stream, dis_style_text, ", "); 8266 } 8267 else if (topreg > maxreg) 8268 { 8269 func (stream, dis_style_register, "%c%d", 8270 reg_prefix, reg); 8271 func (stream, dis_style_text, "-<overflow reg d%d, ", 8272 single ? topreg >> 1 : topreg); 8273 } 8274 else 8275 { 8276 func (stream, dis_style_register, 8277 "%c%d", reg_prefix, reg); 8278 func (stream, dis_style_text, "-"); 8279 func (stream, dis_style_register, "%c%d", 8280 reg_prefix, topreg); 8281 func (stream, dis_style_text, ", "); 8282 } 8283 func (stream, dis_style_register, "VPR"); 8284 func (stream, dis_style_text, "}"); 8285 } 8286 break; 8287 8288 case 'u': 8289 if (cond != COND_UNCOND) 8290 is_unpredictable = true; 8291 8292 /* Fall through. */ 8293 case 'c': 8294 if (cond != COND_UNCOND && cp_num == 9) 8295 is_unpredictable = true; 8296 8297 /* Fall through. */ 8298 case 'b': 8299 func (stream, dis_style_mnemonic, "%s", 8300 arm_conditional[cond]); 8301 break; 8302 8303 case 'I': 8304 /* Print a Cirrus/DSP shift immediate. */ 8305 /* Immediates are 7bit signed ints with bits 0..3 in 8306 bits 0..3 of opcode and bits 4..6 in bits 5..7 8307 of opcode. */ 8308 { 8309 int imm; 8310 8311 imm = (given & 0xf) | ((given & 0xe0) >> 1); 8312 8313 /* Is ``imm'' a negative number? */ 8314 if (imm & 0x40) 8315 imm -= 0x80; 8316 8317 func (stream, dis_style_immediate, "%d", imm); 8318 } 8319 8320 break; 8321 8322 case 'J': 8323 { 8324 unsigned long regno 8325 = arm_decode_field_multiple (given, 13, 15, 22, 22); 8326 8327 switch (regno) 8328 { 8329 case 0x1: 8330 func (stream, dis_style_register, "FPSCR"); 8331 break; 8332 case 0x2: 8333 func (stream, dis_style_register, "FPSCR_nzcvqc"); 8334 break; 8335 case 0xc: 8336 func (stream, dis_style_register, "VPR"); 8337 break; 8338 case 0xd: 8339 func (stream, dis_style_register, "P0"); 8340 break; 8341 case 0xe: 8342 func (stream, dis_style_register, "FPCXTNS"); 8343 break; 8344 case 0xf: 8345 func (stream, dis_style_register, "FPCXTS"); 8346 break; 8347 default: 8348 func (stream, dis_style_text, "<invalid reg %lu>", 8349 regno); 8350 break; 8351 } 8352 } 8353 break; 8354 8355 case 'F': 8356 switch (given & 0x00408000) 8357 { 8358 case 0: 8359 func (stream, dis_style_immediate, "4"); 8360 break; 8361 case 0x8000: 8362 func (stream, dis_style_immediate, "1"); 8363 break; 8364 case 0x00400000: 8365 func (stream, dis_style_immediate, "2"); 8366 break; 8367 default: 8368 func (stream, dis_style_immediate, "3"); 8369 } 8370 break; 8371 8372 case 'P': 8373 switch (given & 0x00080080) 8374 { 8375 case 0: 8376 func (stream, dis_style_mnemonic, "s"); 8377 break; 8378 case 0x80: 8379 func (stream, dis_style_mnemonic, "d"); 8380 break; 8381 case 0x00080000: 8382 func (stream, dis_style_mnemonic, "e"); 8383 break; 8384 default: 8385 func (stream, dis_style_text, _("<illegal precision>")); 8386 break; 8387 } 8388 break; 8389 8390 case 'Q': 8391 switch (given & 0x00408000) 8392 { 8393 case 0: 8394 func (stream, dis_style_mnemonic, "s"); 8395 break; 8396 case 0x8000: 8397 func (stream, dis_style_mnemonic, "d"); 8398 break; 8399 case 0x00400000: 8400 func (stream, dis_style_mnemonic, "e"); 8401 break; 8402 default: 8403 func (stream, dis_style_mnemonic, "p"); 8404 break; 8405 } 8406 break; 8407 8408 case 'R': 8409 switch (given & 0x60) 8410 { 8411 case 0: 8412 break; 8413 case 0x20: 8414 func (stream, dis_style_mnemonic, "p"); 8415 break; 8416 case 0x40: 8417 func (stream, dis_style_mnemonic, "m"); 8418 break; 8419 default: 8420 func (stream, dis_style_mnemonic, "z"); 8421 break; 8422 } 8423 break; 8424 8425 case '0': case '1': case '2': case '3': case '4': 8426 case '5': case '6': case '7': case '8': case '9': 8427 { 8428 int width; 8429 8430 c = arm_decode_bitfield (c, given, &value, &width); 8431 8432 switch (*c) 8433 { 8434 case 'R': 8435 if (value == 15) 8436 is_unpredictable = true; 8437 /* Fall through. */ 8438 case 'r': 8439 if (c[1] == 'u') 8440 { 8441 /* Eat the 'u' character. */ 8442 ++ c; 8443 8444 if (u_reg == value) 8445 is_unpredictable = true; 8446 u_reg = value; 8447 } 8448 func (stream, dis_style_register, "%s", 8449 arm_regnames[value]); 8450 break; 8451 case 'V': 8452 if (given & (1 << 6)) 8453 goto Q; 8454 /* FALLTHROUGH */ 8455 case 'D': 8456 func (stream, dis_style_register, "d%ld", value); 8457 break; 8458 case 'Q': 8459 Q: 8460 if (value & 1) 8461 func (stream, dis_style_text, 8462 "<illegal reg q%ld.5>", value >> 1); 8463 else 8464 func (stream, dis_style_register, 8465 "q%ld", value >> 1); 8466 break; 8467 case 'd': 8468 func (stream, base_style, "%ld", value); 8469 value_in_comment = value; 8470 break; 8471 case 'E': 8472 { 8473 /* Converts immediate 8 bit back to float value. */ 8474 unsigned floatVal = (value & 0x80) << 24 8475 | (value & 0x3F) << 19 8476 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 8477 8478 /* Quarter float have a maximum value of 31.0. 8479 Get floating point value multiplied by 1e7. 8480 The maximum value stays in limit of a 32-bit int. */ 8481 unsigned decVal = 8482 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 8483 (16 + (value & 0xF)); 8484 8485 if (!(decVal % 1000000)) 8486 { 8487 func (stream, dis_style_immediate, "%ld", value); 8488 func (stream, dis_style_comment_start, 8489 "\t@ 0x%08x %c%u.%01u", 8490 floatVal, value & 0x80 ? '-' : ' ', 8491 decVal / 10000000, 8492 decVal % 10000000 / 1000000); 8493 } 8494 else if (!(decVal % 10000)) 8495 { 8496 func (stream, dis_style_immediate, "%ld", value); 8497 func (stream, dis_style_comment_start, 8498 "\t@ 0x%08x %c%u.%03u", 8499 floatVal, value & 0x80 ? '-' : ' ', 8500 decVal / 10000000, 8501 decVal % 10000000 / 10000); 8502 } 8503 else 8504 { 8505 func (stream, dis_style_immediate, "%ld", value); 8506 func (stream, dis_style_comment_start, 8507 "\t@ 0x%08x %c%u.%07u", 8508 floatVal, value & 0x80 ? '-' : ' ', 8509 decVal / 10000000, decVal % 10000000); 8510 } 8511 break; 8512 } 8513 case 'k': 8514 { 8515 int from = (given & (1 << 7)) ? 32 : 16; 8516 func (stream, dis_style_immediate, "%ld", 8517 from - value); 8518 } 8519 break; 8520 8521 case 'f': 8522 if (value > 7) 8523 func (stream, dis_style_immediate, "#%s", 8524 arm_fp_const[value & 7]); 8525 else 8526 func (stream, dis_style_register, "f%ld", value); 8527 break; 8528 8529 case 'w': 8530 if (width == 2) 8531 func (stream, dis_style_mnemonic, "%s", 8532 iwmmxt_wwnames[value]); 8533 else 8534 func (stream, dis_style_mnemonic, "%s", 8535 iwmmxt_wwssnames[value]); 8536 break; 8537 8538 case 'g': 8539 func (stream, dis_style_register, "%s", 8540 iwmmxt_regnames[value]); 8541 break; 8542 case 'G': 8543 func (stream, dis_style_register, "%s", 8544 iwmmxt_cregnames[value]); 8545 break; 8546 8547 case 'x': 8548 func (stream, dis_style_immediate, "0x%lx", 8549 (value & 0xffffffffUL)); 8550 break; 8551 8552 case 'c': 8553 switch (value) 8554 { 8555 case 0: 8556 func (stream, dis_style_mnemonic, "eq"); 8557 break; 8558 8559 case 1: 8560 func (stream, dis_style_mnemonic, "vs"); 8561 break; 8562 8563 case 2: 8564 func (stream, dis_style_mnemonic, "ge"); 8565 break; 8566 8567 case 3: 8568 func (stream, dis_style_mnemonic, "gt"); 8569 break; 8570 8571 default: 8572 func (stream, dis_style_text, "??"); 8573 break; 8574 } 8575 break; 8576 8577 case '`': 8578 c++; 8579 if (value == 0) 8580 func (stream, dis_style_mnemonic, "%c", *c); 8581 break; 8582 case '\'': 8583 c++; 8584 if (value == ((1ul << width) - 1)) 8585 func (stream, base_style, "%c", *c); 8586 break; 8587 case '?': 8588 func (stream, base_style, "%c", 8589 c[(1 << width) - (int) value]); 8590 c += 1 << width; 8591 break; 8592 default: 8593 abort (); 8594 } 8595 } 8596 break; 8597 8598 case 'y': 8599 case 'z': 8600 { 8601 int single = *c++ == 'y'; 8602 int regno; 8603 8604 switch (*c) 8605 { 8606 case '4': /* Sm pair */ 8607 case '0': /* Sm, Dm */ 8608 regno = given & 0x0000000f; 8609 if (single) 8610 { 8611 regno <<= 1; 8612 regno += (given >> 5) & 1; 8613 } 8614 else 8615 regno += ((given >> 5) & 1) << 4; 8616 break; 8617 8618 case '1': /* Sd, Dd */ 8619 regno = (given >> 12) & 0x0000000f; 8620 if (single) 8621 { 8622 regno <<= 1; 8623 regno += (given >> 22) & 1; 8624 } 8625 else 8626 regno += ((given >> 22) & 1) << 4; 8627 break; 8628 8629 case '2': /* Sn, Dn */ 8630 regno = (given >> 16) & 0x0000000f; 8631 if (single) 8632 { 8633 regno <<= 1; 8634 regno += (given >> 7) & 1; 8635 } 8636 else 8637 regno += ((given >> 7) & 1) << 4; 8638 break; 8639 8640 case '3': /* List */ 8641 func (stream, dis_style_text, "{"); 8642 regno = (given >> 12) & 0x0000000f; 8643 if (single) 8644 { 8645 regno <<= 1; 8646 regno += (given >> 22) & 1; 8647 } 8648 else 8649 regno += ((given >> 22) & 1) << 4; 8650 break; 8651 8652 default: 8653 abort (); 8654 } 8655 8656 func (stream, dis_style_register, "%c%d", 8657 single ? 's' : 'd', regno); 8658 8659 if (*c == '3') 8660 { 8661 int count = given & 0xff; 8662 8663 if (single == 0) 8664 count >>= 1; 8665 8666 if (--count) 8667 { 8668 func (stream, dis_style_text, "-"); 8669 func (stream, dis_style_register, "%c%d", 8670 single ? 's' : 'd', 8671 regno + count); 8672 } 8673 8674 func (stream, dis_style_text, "}"); 8675 } 8676 else if (*c == '4') 8677 { 8678 func (stream, dis_style_text, ", "); 8679 func (stream, dis_style_register, "%c%d", 8680 single ? 's' : 'd', regno + 1); 8681 } 8682 } 8683 break; 8684 8685 case 'L': 8686 switch (given & 0x00400100) 8687 { 8688 case 0x00000000: 8689 func (stream, dis_style_mnemonic, "b"); 8690 break; 8691 case 0x00400000: 8692 func (stream, dis_style_mnemonic, "h"); 8693 break; 8694 case 0x00000100: 8695 func (stream, dis_style_mnemonic, "w"); 8696 break; 8697 case 0x00400100: 8698 func (stream, dis_style_mnemonic, "d"); 8699 break; 8700 default: 8701 break; 8702 } 8703 break; 8704 8705 case 'Z': 8706 { 8707 /* given (20, 23) | given (0, 3) */ 8708 value = ((given >> 16) & 0xf0) | (given & 0xf); 8709 func (stream, dis_style_immediate, "%d", (int) value); 8710 } 8711 break; 8712 8713 case 'l': 8714 /* This is like the 'A' operator, except that if 8715 the width field "M" is zero, then the offset is 8716 *not* multiplied by four. */ 8717 { 8718 int offset = given & 0xff; 8719 int multiplier = (given & 0x00000100) ? 4 : 1; 8720 8721 func (stream, dis_style_text, "["); 8722 func (stream, dis_style_register, "%s", 8723 arm_regnames [(given >> 16) & 0xf]); 8724 8725 if (multiplier > 1) 8726 { 8727 value_in_comment = offset * multiplier; 8728 if (NEGATIVE_BIT_SET) 8729 value_in_comment = - value_in_comment; 8730 } 8731 8732 if (offset) 8733 { 8734 if (PRE_BIT_SET) 8735 { 8736 func (stream, dis_style_text, ", "); 8737 func (stream, dis_style_immediate, "#%s%d", 8738 NEGATIVE_BIT_SET ? "-" : "", 8739 offset * multiplier); 8740 func (stream, dis_style_text, "]%s", 8741 WRITEBACK_BIT_SET ? "!" : ""); 8742 } 8743 else 8744 { 8745 func (stream, dis_style_text, "], "); 8746 func (stream, dis_style_immediate, "#%s%d", 8747 NEGATIVE_BIT_SET ? "-" : "", 8748 offset * multiplier); 8749 } 8750 } 8751 else 8752 func (stream, dis_style_text, "]"); 8753 } 8754 break; 8755 8756 case 'r': 8757 { 8758 int imm4 = (given >> 4) & 0xf; 8759 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 8760 int ubit = ! NEGATIVE_BIT_SET; 8761 const char *rm = arm_regnames [given & 0xf]; 8762 const char *rn = arm_regnames [(given >> 16) & 0xf]; 8763 8764 switch (puw_bits) 8765 { 8766 case 1: 8767 case 3: 8768 func (stream, dis_style_text, "["); 8769 func (stream, dis_style_register, "%s", rn); 8770 func (stream, dis_style_text, "], "); 8771 func (stream, dis_style_text, "%c", ubit ? '+' : '-'); 8772 func (stream, dis_style_register, "%s", rm); 8773 if (imm4) 8774 { 8775 func (stream, dis_style_text, ", "); 8776 func (stream, dis_style_sub_mnemonic, "lsl "); 8777 func (stream, dis_style_immediate, "#%d", imm4); 8778 } 8779 break; 8780 8781 case 4: 8782 case 5: 8783 case 6: 8784 case 7: 8785 func (stream, dis_style_text, "["); 8786 func (stream, dis_style_register, "%s", rn); 8787 func (stream, dis_style_text, ", "); 8788 func (stream, dis_style_text, "%c", ubit ? '+' : '-'); 8789 func (stream, dis_style_register, "%s", rm); 8790 if (imm4 > 0) 8791 { 8792 func (stream, dis_style_text, ", "); 8793 func (stream, dis_style_sub_mnemonic, "lsl "); 8794 func (stream, dis_style_immediate, "#%d", imm4); 8795 } 8796 func (stream, dis_style_text, "]"); 8797 if (puw_bits == 5 || puw_bits == 7) 8798 func (stream, dis_style_text, "!"); 8799 break; 8800 8801 default: 8802 func (stream, dis_style_text, "INVALID"); 8803 } 8804 } 8805 break; 8806 8807 case 'i': 8808 { 8809 long imm5; 8810 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 8811 func (stream, dis_style_immediate, "%ld", 8812 (imm5 == 0) ? 32 : imm5); 8813 } 8814 break; 8815 8816 default: 8817 abort (); 8818 } 8819 } 8820 else 8821 { 8822 if (*c == '@') 8823 base_style = dis_style_comment_start; 8824 8825 if (*c == '\t') 8826 base_style = dis_style_text; 8827 8828 func (stream, base_style, "%c", *c); 8829 } 8830 } 8831 8832 if (value_in_comment > 32 || value_in_comment < -16) 8833 func (stream, dis_style_comment_start, "\t@ 0x%lx", 8834 (value_in_comment & 0xffffffffUL)); 8835 8836 if (is_unpredictable) 8837 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 8838 8839 return true; 8840 } 8841 return false; 8842 } 8843 8844 static bool 8845 print_insn_coprocessor (bfd_vma pc, 8846 struct disassemble_info *info, 8847 long given, 8848 bool thumb) 8849 { 8850 return print_insn_coprocessor_1 (coprocessor_opcodes, 8851 pc, info, given, thumb); 8852 } 8853 8854 static bool 8855 print_insn_generic_coprocessor (bfd_vma pc, 8856 struct disassemble_info *info, 8857 long given, 8858 bool thumb) 8859 { 8860 return print_insn_coprocessor_1 (generic_coprocessor_opcodes, 8861 pc, info, given, thumb); 8862 } 8863 8864 /* Decodes and prints ARM addressing modes. Returns the offset 8865 used in the address, if any, if it is worthwhile printing the 8866 offset as a hexadecimal value in a comment at the end of the 8867 line of disassembly. */ 8868 8869 static signed long 8870 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 8871 { 8872 void *stream = info->stream; 8873 fprintf_styled_ftype func = info->fprintf_styled_func; 8874 bfd_vma offset = 0; 8875 8876 if (((given & 0x000f0000) == 0x000f0000) 8877 && ((given & 0x02000000) == 0)) 8878 { 8879 offset = given & 0xfff; 8880 8881 func (stream, dis_style_text, "["); 8882 func (stream, dis_style_register, "pc"); 8883 8884 if (PRE_BIT_SET) 8885 { 8886 /* Pre-indexed. Elide offset of positive zero when 8887 non-writeback. */ 8888 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8889 { 8890 func (stream, dis_style_text, ", "); 8891 func (stream, dis_style_immediate, "#%s%d", 8892 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8893 } 8894 8895 if (NEGATIVE_BIT_SET) 8896 offset = -offset; 8897 8898 offset += pc + 8; 8899 8900 /* Cope with the possibility of write-back 8901 being used. Probably a very dangerous thing 8902 for the programmer to do, but who are we to 8903 argue ? */ 8904 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 8905 } 8906 else /* Post indexed. */ 8907 { 8908 func (stream, dis_style_text, "], "); 8909 func (stream, dis_style_immediate, "#%s%d", 8910 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8911 8912 /* Ie ignore the offset. */ 8913 offset = pc + 8; 8914 } 8915 8916 func (stream, dis_style_comment_start, "\t@ "); 8917 info->print_address_func (offset, info); 8918 offset = 0; 8919 } 8920 else 8921 { 8922 func (stream, dis_style_text, "["); 8923 func (stream, dis_style_register, "%s", 8924 arm_regnames[(given >> 16) & 0xf]); 8925 8926 if (PRE_BIT_SET) 8927 { 8928 if ((given & 0x02000000) == 0) 8929 { 8930 /* Elide offset of positive zero when non-writeback. */ 8931 offset = given & 0xfff; 8932 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8933 { 8934 func (stream, dis_style_text, ", "); 8935 func (stream, dis_style_immediate, "#%s%d", 8936 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8937 } 8938 } 8939 else 8940 { 8941 func (stream, dis_style_text, ", %s", 8942 NEGATIVE_BIT_SET ? "-" : ""); 8943 arm_decode_shift (given, func, stream, true); 8944 } 8945 8946 func (stream, dis_style_text, "]%s", 8947 WRITEBACK_BIT_SET ? "!" : ""); 8948 } 8949 else 8950 { 8951 if ((given & 0x02000000) == 0) 8952 { 8953 /* Always show offset. */ 8954 offset = given & 0xfff; 8955 func (stream, dis_style_text, "], "); 8956 func (stream, dis_style_immediate, "#%s%d", 8957 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8958 } 8959 else 8960 { 8961 func (stream, dis_style_text, "], %s", 8962 NEGATIVE_BIT_SET ? "-" : ""); 8963 arm_decode_shift (given, func, stream, true); 8964 } 8965 } 8966 if (NEGATIVE_BIT_SET) 8967 offset = -offset; 8968 } 8969 8970 return (signed long) offset; 8971 } 8972 8973 8974 /* Print one cde instruction on INFO->STREAM. 8975 Return TRUE if the instuction matched, FALSE if this is not a 8976 recognised cde instruction. */ 8977 static bool 8978 print_insn_cde (struct disassemble_info *info, long given, bool thumb) 8979 { 8980 const struct cdeopcode32 *insn; 8981 void *stream = info->stream; 8982 fprintf_styled_ftype func = info->fprintf_styled_func; 8983 enum disassembler_style base_style = dis_style_mnemonic; 8984 enum disassembler_style old_base_style = base_style; 8985 8986 if (thumb) 8987 { 8988 /* Manually extract the coprocessor code from a known point. 8989 This position is the same across all CDE instructions. */ 8990 for (insn = cde_opcodes; insn->assembler; insn++) 8991 { 8992 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask; 8993 uint16_t coproc_mask = 1 << coproc; 8994 if (! (coproc_mask & cde_coprocs)) 8995 continue; 8996 8997 if ((given & insn->mask) == insn->value) 8998 { 8999 bool is_unpredictable = false; 9000 const char *c; 9001 9002 for (c = insn->assembler; *c; c++) 9003 { 9004 if (*c == '%') 9005 { 9006 switch (*++c) 9007 { 9008 case '{': 9009 ++c; 9010 if (*c == '\0') 9011 abort (); 9012 old_base_style = base_style; 9013 base_style = decode_base_style (*c); 9014 ++c; 9015 if (*c != ':') 9016 abort (); 9017 break; 9018 9019 case '}': 9020 base_style = old_base_style; 9021 break; 9022 9023 case '%': 9024 func (stream, base_style, "%%"); 9025 break; 9026 9027 case '0': case '1': case '2': case '3': case '4': 9028 case '5': case '6': case '7': case '8': case '9': 9029 { 9030 int width; 9031 unsigned long value; 9032 9033 c = arm_decode_bitfield (c, given, &value, &width); 9034 9035 switch (*c) 9036 { 9037 case 'S': 9038 if (value > 10) 9039 is_unpredictable = true; 9040 /* Fall through. */ 9041 case 'R': 9042 if (value == 13) 9043 is_unpredictable = true; 9044 /* Fall through. */ 9045 case 'r': 9046 func (stream, dis_style_register, "%s", 9047 arm_regnames[value]); 9048 break; 9049 9050 case 'n': 9051 if (value == 15) 9052 func (stream, dis_style_register, "%s", "APSR_nzcv"); 9053 else 9054 func (stream, dis_style_register, "%s", 9055 arm_regnames[value]); 9056 break; 9057 9058 case 'T': 9059 func (stream, dis_style_register, "%s", 9060 arm_regnames[(value + 1) & 15]); 9061 break; 9062 9063 case 'd': 9064 func (stream, dis_style_immediate, "%ld", value); 9065 break; 9066 9067 case 'V': 9068 if (given & (1 << 6)) 9069 func (stream, dis_style_register, "q%ld", value >> 1); 9070 else if (given & (1 << 24)) 9071 func (stream, dis_style_register, "d%ld", value); 9072 else 9073 { 9074 /* Encoding for S register is different than for D and 9075 Q registers. S registers are encoded using the top 9076 single bit in position 22 as the lowest bit of the 9077 register number, while for Q and D it represents the 9078 highest bit of the register number. */ 9079 uint8_t top_bit = (value >> 4) & 1; 9080 uint8_t tmp = (value << 1) & 0x1e; 9081 uint8_t res = tmp | top_bit; 9082 func (stream, dis_style_register, "s%u", res); 9083 } 9084 break; 9085 9086 default: 9087 abort (); 9088 } 9089 } 9090 break; 9091 9092 case 'p': 9093 { 9094 uint8_t proc_number = (given >> 8) & 0x7; 9095 func (stream, dis_style_register, "p%u", proc_number); 9096 break; 9097 } 9098 9099 case 'a': 9100 { 9101 uint8_t a_offset = 28; 9102 if (given & (1 << a_offset)) 9103 func (stream, dis_style_mnemonic, "a"); 9104 break; 9105 } 9106 default: 9107 abort (); 9108 } 9109 } 9110 else 9111 { 9112 if (*c == '@') 9113 base_style = dis_style_comment_start; 9114 if (*c == '\t') 9115 base_style = dis_style_text; 9116 9117 func (stream, base_style, "%c", *c); 9118 } 9119 } 9120 9121 if (is_unpredictable) 9122 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 9123 9124 return true; 9125 } 9126 } 9127 return false; 9128 } 9129 else 9130 return false; 9131 } 9132 9133 9134 /* Print one neon instruction on INFO->STREAM. 9135 Return TRUE if the instuction matched, FALSE if this is not a 9136 recognised neon instruction. */ 9137 9138 static bool 9139 print_insn_neon (struct disassemble_info *info, long given, bool thumb) 9140 { 9141 const struct opcode32 *insn; 9142 void *stream = info->stream; 9143 fprintf_styled_ftype func = info->fprintf_styled_func; 9144 enum disassembler_style base_style = dis_style_mnemonic; 9145 enum disassembler_style old_base_style = base_style; 9146 9147 if (thumb) 9148 { 9149 if ((given & 0xef000000) == 0xef000000) 9150 { 9151 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 9152 unsigned long bit28 = given & (1 << 28); 9153 9154 given &= 0x00ffffff; 9155 if (bit28) 9156 given |= 0xf3000000; 9157 else 9158 given |= 0xf2000000; 9159 } 9160 else if ((given & 0xff000000) == 0xf9000000) 9161 given ^= 0xf9000000 ^ 0xf4000000; 9162 /* BFloat16 neon instructions without special top byte handling. */ 9163 else if ((given & 0xff000000) == 0xfe000000 9164 || (given & 0xff000000) == 0xfc000000) 9165 ; 9166 /* vdup is also a valid neon instruction. */ 9167 else if ((given & 0xff900f5f) != 0xee800b10) 9168 return false; 9169 } 9170 9171 for (insn = neon_opcodes; insn->assembler; insn++) 9172 { 9173 unsigned long cond_mask = insn->mask; 9174 unsigned long cond_value = insn->value; 9175 int cond; 9176 9177 if (thumb) 9178 { 9179 if ((cond_mask & 0xf0000000) == 0) { 9180 /* For the entries in neon_opcodes, an opcode mask/value with 9181 the high 4 bits equal to 0 indicates a conditional 9182 instruction. For thumb however, we need to include those 9183 bits in the instruction matching. */ 9184 cond_mask |= 0xf0000000; 9185 /* Furthermore, the thumb encoding of a conditional instruction 9186 will have the high 4 bits equal to 0xe. */ 9187 cond_value |= 0xe0000000; 9188 } 9189 if (ifthen_state) 9190 cond = IFTHEN_COND; 9191 else 9192 cond = COND_UNCOND; 9193 } 9194 else 9195 { 9196 if ((given & 0xf0000000) == 0xf0000000) 9197 { 9198 /* If the instruction is unconditional, update the mask to only 9199 match against unconditional opcode values. */ 9200 cond_mask |= 0xf0000000; 9201 cond = COND_UNCOND; 9202 } 9203 else 9204 { 9205 cond = (given >> 28) & 0xf; 9206 if (cond == 0xe) 9207 cond = COND_UNCOND; 9208 } 9209 } 9210 9211 if ((given & cond_mask) == cond_value) 9212 { 9213 signed long value_in_comment = 0; 9214 bool is_unpredictable = false; 9215 const char *c; 9216 9217 for (c = insn->assembler; *c; c++) 9218 { 9219 if (*c == '%') 9220 { 9221 switch (*++c) 9222 { 9223 case '{': 9224 ++c; 9225 if (*c == '\0') 9226 abort (); 9227 old_base_style = base_style; 9228 base_style = decode_base_style (*c); 9229 ++c; 9230 if (*c != ':') 9231 abort (); 9232 break; 9233 9234 case '}': 9235 base_style = old_base_style; 9236 break; 9237 9238 case '%': 9239 func (stream, base_style, "%%"); 9240 break; 9241 9242 case 'u': 9243 if (thumb && ifthen_state) 9244 is_unpredictable = true; 9245 9246 /* Fall through. */ 9247 case 'c': 9248 func (stream, dis_style_mnemonic, "%s", 9249 arm_conditional[cond]); 9250 break; 9251 9252 case 'A': 9253 { 9254 static const unsigned char enc[16] = 9255 { 9256 0x4, 0x14, /* st4 0,1 */ 9257 0x4, /* st1 2 */ 9258 0x4, /* st2 3 */ 9259 0x3, /* st3 4 */ 9260 0x13, /* st3 5 */ 9261 0x3, /* st1 6 */ 9262 0x1, /* st1 7 */ 9263 0x2, /* st2 8 */ 9264 0x12, /* st2 9 */ 9265 0x2, /* st1 10 */ 9266 0, 0, 0, 0, 0 9267 }; 9268 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9269 int rn = ((given >> 16) & 0xf); 9270 int rm = ((given >> 0) & 0xf); 9271 int align = ((given >> 4) & 0x3); 9272 int type = ((given >> 8) & 0xf); 9273 int n = enc[type] & 0xf; 9274 int stride = (enc[type] >> 4) + 1; 9275 int ix; 9276 9277 func (stream, dis_style_text, "{"); 9278 if (stride > 1) 9279 for (ix = 0; ix != n; ix++) 9280 { 9281 if (ix > 0) 9282 func (stream, dis_style_text, ","); 9283 func (stream, dis_style_register, "d%d", 9284 rd + ix * stride); 9285 } 9286 else if (n == 1) 9287 func (stream, dis_style_register, "d%d", rd); 9288 else 9289 { 9290 func (stream, dis_style_register, "d%d", rd); 9291 func (stream, dis_style_text, "-"); 9292 func (stream, dis_style_register, "d%d", 9293 rd + n - 1); 9294 } 9295 func (stream, dis_style_text, "}, ["); 9296 func (stream, dis_style_register, "%s", 9297 arm_regnames[rn]); 9298 if (align) 9299 { 9300 func (stream, dis_style_text, " :"); 9301 func (stream, dis_style_immediate, "%d", 9302 32 << align); 9303 } 9304 func (stream, dis_style_text, "]"); 9305 if (rm == 0xd) 9306 func (stream, dis_style_text, "!"); 9307 else if (rm != 0xf) 9308 { 9309 func (stream, dis_style_text, ", "); 9310 func (stream, dis_style_register, "%s", 9311 arm_regnames[rm]); 9312 } 9313 } 9314 break; 9315 9316 case 'B': 9317 { 9318 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9319 int rn = ((given >> 16) & 0xf); 9320 int rm = ((given >> 0) & 0xf); 9321 int idx_align = ((given >> 4) & 0xf); 9322 int align = 0; 9323 int size = ((given >> 10) & 0x3); 9324 int idx = idx_align >> (size + 1); 9325 int length = ((given >> 8) & 3) + 1; 9326 int stride = 1; 9327 int i; 9328 9329 if (length > 1 && size > 0) 9330 stride = (idx_align & (1 << size)) ? 2 : 1; 9331 9332 switch (length) 9333 { 9334 case 1: 9335 { 9336 int amask = (1 << size) - 1; 9337 if ((idx_align & (1 << size)) != 0) 9338 return false; 9339 if (size > 0) 9340 { 9341 if ((idx_align & amask) == amask) 9342 align = 8 << size; 9343 else if ((idx_align & amask) != 0) 9344 return false; 9345 } 9346 } 9347 break; 9348 9349 case 2: 9350 if (size == 2 && (idx_align & 2) != 0) 9351 return false; 9352 align = (idx_align & 1) ? 16 << size : 0; 9353 break; 9354 9355 case 3: 9356 if ((size == 2 && (idx_align & 3) != 0) 9357 || (idx_align & 1) != 0) 9358 return false; 9359 break; 9360 9361 case 4: 9362 if (size == 2) 9363 { 9364 if ((idx_align & 3) == 3) 9365 return false; 9366 align = (idx_align & 3) * 64; 9367 } 9368 else 9369 align = (idx_align & 1) ? 32 << size : 0; 9370 break; 9371 9372 default: 9373 abort (); 9374 } 9375 9376 func (stream, dis_style_text, "{"); 9377 for (i = 0; i < length; i++) 9378 { 9379 if (i > 0) 9380 func (stream, dis_style_text, ","); 9381 func (stream, dis_style_register, "d%d[%d]", 9382 rd + i * stride, idx); 9383 } 9384 func (stream, dis_style_text, "}, ["); 9385 func (stream, dis_style_register, "%s", 9386 arm_regnames[rn]); 9387 if (align) 9388 { 9389 func (stream, dis_style_text, " :"); 9390 func (stream, dis_style_immediate, "%d", align); 9391 } 9392 func (stream, dis_style_text, "]"); 9393 if (rm == 0xd) 9394 func (stream, dis_style_text, "!"); 9395 else if (rm != 0xf) 9396 { 9397 func (stream, dis_style_text, ", "); 9398 func (stream, dis_style_register, "%s", 9399 arm_regnames[rm]); 9400 } 9401 } 9402 break; 9403 9404 case 'C': 9405 { 9406 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9407 int rn = ((given >> 16) & 0xf); 9408 int rm = ((given >> 0) & 0xf); 9409 int align = ((given >> 4) & 0x1); 9410 int size = ((given >> 6) & 0x3); 9411 int type = ((given >> 8) & 0x3); 9412 int n = type + 1; 9413 int stride = ((given >> 5) & 0x1); 9414 int ix; 9415 9416 if (stride && (n == 1)) 9417 n++; 9418 else 9419 stride++; 9420 9421 func (stream, dis_style_text, "{"); 9422 if (stride > 1) 9423 for (ix = 0; ix != n; ix++) 9424 { 9425 if (ix > 0) 9426 func (stream, dis_style_text, ","); 9427 func (stream, dis_style_register, "d%d[]", 9428 rd + ix * stride); 9429 } 9430 else if (n == 1) 9431 func (stream, dis_style_register, "d%d[]", rd); 9432 else 9433 { 9434 func (stream, dis_style_register, "d%d[]", rd); 9435 func (stream, dis_style_text, "-"); 9436 func (stream, dis_style_register, "d%d[]", 9437 rd + n - 1); 9438 } 9439 func (stream, dis_style_text, "}, ["); 9440 func (stream, dis_style_register, "%s", 9441 arm_regnames[rn]); 9442 if (align) 9443 { 9444 align = (8 * (type + 1)) << size; 9445 if (type == 3) 9446 align = (size > 1) ? align >> 1 : align; 9447 if (type == 2 || (type == 0 && !size)) 9448 func (stream, dis_style_text, 9449 " :<bad align %d>", align); 9450 else 9451 { 9452 func (stream, dis_style_text, " :"); 9453 func (stream, dis_style_immediate, 9454 "%d", align); 9455 } 9456 } 9457 func (stream, dis_style_text, "]"); 9458 if (rm == 0xd) 9459 func (stream, dis_style_text, "!"); 9460 else if (rm != 0xf) 9461 { 9462 func (stream, dis_style_text, ", "); 9463 func (stream, dis_style_register, "%s", 9464 arm_regnames[rm]); 9465 } 9466 } 9467 break; 9468 9469 case 'D': 9470 { 9471 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 9472 int size = (given >> 20) & 3; 9473 int reg = raw_reg & ((4 << size) - 1); 9474 int ix = raw_reg >> size >> 2; 9475 9476 func (stream, dis_style_register, "d%d[%d]", reg, ix); 9477 } 9478 break; 9479 9480 case 'E': 9481 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 9482 { 9483 int bits = 0; 9484 int cmode = (given >> 8) & 0xf; 9485 int op = (given >> 5) & 0x1; 9486 unsigned long value = 0, hival = 0; 9487 unsigned shift; 9488 int size = 0; 9489 int isfloat = 0; 9490 9491 bits |= ((given >> 24) & 1) << 7; 9492 bits |= ((given >> 16) & 7) << 4; 9493 bits |= ((given >> 0) & 15) << 0; 9494 9495 if (cmode < 8) 9496 { 9497 shift = (cmode >> 1) & 3; 9498 value = (unsigned long) bits << (8 * shift); 9499 size = 32; 9500 } 9501 else if (cmode < 12) 9502 { 9503 shift = (cmode >> 1) & 1; 9504 value = (unsigned long) bits << (8 * shift); 9505 size = 16; 9506 } 9507 else if (cmode < 14) 9508 { 9509 shift = (cmode & 1) + 1; 9510 value = (unsigned long) bits << (8 * shift); 9511 value |= (1ul << (8 * shift)) - 1; 9512 size = 32; 9513 } 9514 else if (cmode == 14) 9515 { 9516 if (op) 9517 { 9518 /* Bit replication into bytes. */ 9519 int ix; 9520 unsigned long mask; 9521 9522 value = 0; 9523 hival = 0; 9524 for (ix = 7; ix >= 0; ix--) 9525 { 9526 mask = ((bits >> ix) & 1) ? 0xff : 0; 9527 if (ix <= 3) 9528 value = (value << 8) | mask; 9529 else 9530 hival = (hival << 8) | mask; 9531 } 9532 size = 64; 9533 } 9534 else 9535 { 9536 /* Byte replication. */ 9537 value = (unsigned long) bits; 9538 size = 8; 9539 } 9540 } 9541 else if (!op) 9542 { 9543 /* Floating point encoding. */ 9544 int tmp; 9545 9546 value = (unsigned long) (bits & 0x7f) << 19; 9547 value |= (unsigned long) (bits & 0x80) << 24; 9548 tmp = bits & 0x40 ? 0x3c : 0x40; 9549 value |= (unsigned long) tmp << 24; 9550 size = 32; 9551 isfloat = 1; 9552 } 9553 else 9554 { 9555 func (stream, dis_style_text, 9556 "<illegal constant %.8x:%x:%x>", 9557 bits, cmode, op); 9558 size = 32; 9559 break; 9560 } 9561 switch (size) 9562 { 9563 case 8: 9564 func (stream, dis_style_immediate, "#%ld", value); 9565 func (stream, dis_style_comment_start, 9566 "\t@ 0x%.2lx", value); 9567 break; 9568 9569 case 16: 9570 func (stream, dis_style_immediate, "#%ld", value); 9571 func (stream, dis_style_comment_start, 9572 "\t@ 0x%.4lx", value); 9573 break; 9574 9575 case 32: 9576 if (isfloat) 9577 { 9578 unsigned char valbytes[4]; 9579 double fvalue; 9580 9581 /* Do this a byte at a time so we don't have to 9582 worry about the host's endianness. */ 9583 valbytes[0] = value & 0xff; 9584 valbytes[1] = (value >> 8) & 0xff; 9585 valbytes[2] = (value >> 16) & 0xff; 9586 valbytes[3] = (value >> 24) & 0xff; 9587 9588 floatformat_to_double 9589 (& floatformat_ieee_single_little, valbytes, 9590 & fvalue); 9591 9592 func (stream, dis_style_immediate, 9593 "#%.7g", fvalue); 9594 func (stream, dis_style_comment_start, 9595 "\t@ 0x%.8lx", value); 9596 } 9597 else 9598 { 9599 func (stream, dis_style_immediate, "#%ld", 9600 (long) (((value & 0x80000000L) != 0) 9601 ? value | ~0xffffffffL : value)); 9602 func (stream, dis_style_comment_start, 9603 "\t@ 0x%.8lx", value); 9604 } 9605 break; 9606 9607 case 64: 9608 func (stream, dis_style_immediate, 9609 "#0x%.8lx%.8lx", hival, value); 9610 break; 9611 9612 default: 9613 abort (); 9614 } 9615 } 9616 break; 9617 9618 case 'F': 9619 { 9620 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 9621 int num = (given >> 8) & 0x3; 9622 9623 func (stream, dis_style_text, "{"); 9624 if (!num) 9625 func (stream, dis_style_register, "d%d", regno); 9626 else if (num + regno >= 32) 9627 { 9628 func (stream, dis_style_register, "d%d", regno); 9629 func (stream, dis_style_text, "-<overflow reg d%d", 9630 regno + num); 9631 } 9632 else 9633 { 9634 func (stream, dis_style_register, "d%d", regno); 9635 func (stream, dis_style_text, "-"); 9636 func (stream, dis_style_register, "d%d", 9637 regno + num); 9638 } 9639 func (stream, dis_style_text, "}"); 9640 } 9641 break; 9642 9643 9644 case '0': case '1': case '2': case '3': case '4': 9645 case '5': case '6': case '7': case '8': case '9': 9646 { 9647 int width; 9648 unsigned long value; 9649 9650 c = arm_decode_bitfield (c, given, &value, &width); 9651 9652 switch (*c) 9653 { 9654 case 'r': 9655 func (stream, dis_style_register, "%s", 9656 arm_regnames[value]); 9657 break; 9658 case 'd': 9659 func (stream, base_style, "%ld", value); 9660 value_in_comment = value; 9661 break; 9662 case 'e': 9663 func (stream, dis_style_immediate, "%ld", 9664 (1ul << width) - value); 9665 break; 9666 9667 case 'S': 9668 case 'T': 9669 case 'U': 9670 /* Various width encodings. */ 9671 { 9672 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 9673 int limit; 9674 unsigned low, high; 9675 9676 c++; 9677 if (*c >= '0' && *c <= '9') 9678 limit = *c - '0'; 9679 else if (*c >= 'a' && *c <= 'f') 9680 limit = *c - 'a' + 10; 9681 else 9682 abort (); 9683 low = limit >> 2; 9684 high = limit & 3; 9685 9686 if (value < low || value > high) 9687 func (stream, dis_style_text, 9688 "<illegal width %d>", base << value); 9689 else 9690 func (stream, base_style, "%d", 9691 base << value); 9692 } 9693 break; 9694 case 'R': 9695 if (given & (1 << 6)) 9696 goto Q; 9697 /* FALLTHROUGH */ 9698 case 'D': 9699 func (stream, dis_style_register, "d%ld", value); 9700 break; 9701 case 'Q': 9702 Q: 9703 if (value & 1) 9704 func (stream, dis_style_text, 9705 "<illegal reg q%ld.5>", value >> 1); 9706 else 9707 func (stream, dis_style_register, 9708 "q%ld", value >> 1); 9709 break; 9710 9711 case '`': 9712 c++; 9713 if (value == 0) 9714 func (stream, dis_style_text, "%c", *c); 9715 break; 9716 case '\'': 9717 c++; 9718 if (value == ((1ul << width) - 1)) 9719 func (stream, dis_style_text, "%c", *c); 9720 break; 9721 case '?': 9722 func (stream, dis_style_mnemonic, "%c", 9723 c[(1 << width) - (int) value]); 9724 c += 1 << width; 9725 break; 9726 default: 9727 abort (); 9728 } 9729 } 9730 break; 9731 9732 default: 9733 abort (); 9734 } 9735 } 9736 else 9737 { 9738 if (*c == '@') 9739 base_style = dis_style_comment_start; 9740 9741 if (*c == '\t') 9742 base_style = dis_style_text; 9743 9744 func (stream, base_style, "%c", *c); 9745 9746 } 9747 } 9748 9749 if (value_in_comment > 32 || value_in_comment < -16) 9750 func (stream, dis_style_comment_start, "\t@ 0x%lx", 9751 value_in_comment); 9752 9753 if (is_unpredictable) 9754 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 9755 9756 return true; 9757 } 9758 } 9759 return false; 9760 } 9761 9762 /* Print one mve instruction on INFO->STREAM. 9763 Return TRUE if the instuction matched, FALSE if this is not a 9764 recognised mve instruction. */ 9765 9766 static bool 9767 print_insn_mve (struct disassemble_info *info, long given) 9768 { 9769 const struct mopcode32 *insn; 9770 void *stream = info->stream; 9771 fprintf_styled_ftype func = info->fprintf_styled_func; 9772 enum disassembler_style base_style = dis_style_mnemonic; 9773 enum disassembler_style old_base_style = base_style; 9774 9775 for (insn = mve_opcodes; insn->assembler; insn++) 9776 { 9777 if (((given & insn->mask) == insn->value) 9778 && !is_mve_encoding_conflict (given, insn->mve_op)) 9779 { 9780 signed long value_in_comment = 0; 9781 bool is_unpredictable = false; 9782 bool is_undefined = false; 9783 const char *c; 9784 enum mve_unpredictable unpredictable_cond = UNPRED_NONE; 9785 enum mve_undefined undefined_cond = UNDEF_NONE; 9786 9787 /* Most vector mve instruction are illegal in a it block. 9788 There are a few exceptions; check for them. */ 9789 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op)) 9790 { 9791 is_unpredictable = true; 9792 unpredictable_cond = UNPRED_IT_BLOCK; 9793 } 9794 else if (is_mve_unpredictable (given, insn->mve_op, 9795 &unpredictable_cond)) 9796 is_unpredictable = true; 9797 9798 if (is_mve_undefined (given, insn->mve_op, &undefined_cond)) 9799 is_undefined = true; 9800 9801 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV, 9802 i.e "VMOV Qd, Qm". */ 9803 if ((insn->mve_op == MVE_VORR_REG) 9804 && (arm_decode_field (given, 1, 3) 9805 == arm_decode_field (given, 17, 19))) 9806 continue; 9807 9808 for (c = insn->assembler; *c; c++) 9809 { 9810 if (*c == '%') 9811 { 9812 switch (*++c) 9813 { 9814 case '{': 9815 ++c; 9816 if (*c == '\0') 9817 abort (); 9818 old_base_style = base_style; 9819 base_style = decode_base_style (*c); 9820 ++c; 9821 if (*c != ':') 9822 abort (); 9823 break; 9824 9825 case '}': 9826 base_style = old_base_style; 9827 break; 9828 9829 case '%': 9830 func (stream, base_style, "%%"); 9831 break; 9832 9833 case 'a': 9834 /* Don't print anything for '+' as it is implied. */ 9835 if (arm_decode_field (given, 23, 23) == 0) 9836 func (stream, dis_style_immediate, "-"); 9837 break; 9838 9839 case 'c': 9840 if (ifthen_state) 9841 func (stream, dis_style_mnemonic, "%s", 9842 arm_conditional[IFTHEN_COND]); 9843 break; 9844 9845 case 'd': 9846 print_mve_vld_str_addr (info, given, insn->mve_op); 9847 break; 9848 9849 case 'i': 9850 { 9851 long mve_mask = mve_extract_pred_mask (given); 9852 func (stream, dis_style_mnemonic, "%s", 9853 mve_predicatenames[mve_mask]); 9854 } 9855 break; 9856 9857 case 'j': 9858 { 9859 unsigned int imm5 = 0; 9860 imm5 |= arm_decode_field (given, 6, 7); 9861 imm5 |= (arm_decode_field (given, 12, 14) << 2); 9862 func (stream, dis_style_immediate, "#%u", 9863 (imm5 == 0) ? 32 : imm5); 9864 } 9865 break; 9866 9867 case 'k': 9868 func (stream, dis_style_immediate, "#%u", 9869 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); 9870 break; 9871 9872 case 'n': 9873 print_vec_condition (info, given, insn->mve_op); 9874 break; 9875 9876 case 'o': 9877 if (arm_decode_field (given, 0, 0) == 1) 9878 { 9879 unsigned long size 9880 = arm_decode_field (given, 4, 4) 9881 | (arm_decode_field (given, 6, 6) << 1); 9882 9883 func (stream, dis_style_text, ", "); 9884 func (stream, dis_style_sub_mnemonic, "uxtw "); 9885 func (stream, dis_style_immediate, "#%lu", size); 9886 } 9887 break; 9888 9889 case 'm': 9890 print_mve_rounding_mode (info, given, insn->mve_op); 9891 break; 9892 9893 case 's': 9894 print_mve_vcvt_size (info, given, insn->mve_op); 9895 break; 9896 9897 case 'u': 9898 { 9899 unsigned long op1 = arm_decode_field (given, 21, 22); 9900 9901 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP)) 9902 { 9903 /* Check for signed. */ 9904 if (arm_decode_field (given, 23, 23) == 0) 9905 { 9906 /* We don't print 's' for S32. */ 9907 if ((arm_decode_field (given, 5, 6) == 0) 9908 && ((op1 == 0) || (op1 == 1))) 9909 ; 9910 else 9911 func (stream, dis_style_mnemonic, "s"); 9912 } 9913 else 9914 func (stream, dis_style_mnemonic, "u"); 9915 } 9916 else 9917 { 9918 if (arm_decode_field (given, 28, 28) == 0) 9919 func (stream, dis_style_mnemonic, "s"); 9920 else 9921 func (stream, dis_style_mnemonic, "u"); 9922 } 9923 } 9924 break; 9925 9926 case 'v': 9927 print_instruction_predicate (info); 9928 break; 9929 9930 case 'w': 9931 if (arm_decode_field (given, 21, 21) == 1) 9932 func (stream, dis_style_text, "!"); 9933 break; 9934 9935 case 'B': 9936 print_mve_register_blocks (info, given, insn->mve_op); 9937 break; 9938 9939 case 'E': 9940 /* SIMD encoded constant for mov, mvn, vorr, vbic. */ 9941 9942 print_simd_imm8 (info, given, 28, insn); 9943 break; 9944 9945 case 'N': 9946 print_mve_vmov_index (info, given); 9947 break; 9948 9949 case 'T': 9950 if (arm_decode_field (given, 12, 12) == 0) 9951 func (stream, dis_style_mnemonic, "b"); 9952 else 9953 func (stream, dis_style_mnemonic, "t"); 9954 break; 9955 9956 case 'X': 9957 if (arm_decode_field (given, 12, 12) == 1) 9958 func (stream, dis_style_mnemonic, "x"); 9959 break; 9960 9961 case '0': case '1': case '2': case '3': case '4': 9962 case '5': case '6': case '7': case '8': case '9': 9963 { 9964 int width; 9965 unsigned long value; 9966 9967 c = arm_decode_bitfield (c, given, &value, &width); 9968 9969 switch (*c) 9970 { 9971 case 'Z': 9972 if (value == 13) 9973 is_unpredictable = true; 9974 else if (value == 15) 9975 func (stream, dis_style_register, "zr"); 9976 else 9977 func (stream, dis_style_register, "%s", 9978 arm_regnames[value]); 9979 break; 9980 9981 case 'c': 9982 func (stream, dis_style_sub_mnemonic, "%s", 9983 arm_conditional[value]); 9984 break; 9985 9986 case 'C': 9987 value ^= 1; 9988 func (stream, dis_style_sub_mnemonic, "%s", 9989 arm_conditional[value]); 9990 break; 9991 9992 case 'S': 9993 if (value == 13 || value == 15) 9994 is_unpredictable = true; 9995 else 9996 func (stream, dis_style_register, "%s", 9997 arm_regnames[value]); 9998 break; 9999 10000 case 's': 10001 print_mve_size (info, 10002 value, 10003 insn->mve_op); 10004 break; 10005 case 'I': 10006 if (value == 1) 10007 func (stream, dis_style_mnemonic, "i"); 10008 break; 10009 case 'A': 10010 if (value == 1) 10011 func (stream, dis_style_mnemonic, "a"); 10012 break; 10013 case 'h': 10014 { 10015 unsigned int odd_reg = (value << 1) | 1; 10016 func (stream, dis_style_register, "%s", 10017 arm_regnames[odd_reg]); 10018 } 10019 break; 10020 case 'i': 10021 { 10022 unsigned long imm 10023 = arm_decode_field (given, 0, 6); 10024 unsigned long mod_imm = imm; 10025 10026 switch (insn->mve_op) 10027 { 10028 case MVE_VLDRW_GATHER_T5: 10029 case MVE_VSTRW_SCATTER_T5: 10030 mod_imm = mod_imm << 2; 10031 break; 10032 case MVE_VSTRD_SCATTER_T6: 10033 case MVE_VLDRD_GATHER_T6: 10034 mod_imm = mod_imm << 3; 10035 break; 10036 10037 default: 10038 break; 10039 } 10040 10041 func (stream, dis_style_immediate, "%lu", 10042 mod_imm); 10043 } 10044 break; 10045 case 'k': 10046 func (stream, dis_style_immediate, "%lu", 10047 64 - value); 10048 break; 10049 case 'l': 10050 { 10051 unsigned int even_reg = value << 1; 10052 func (stream, dis_style_register, "%s", 10053 arm_regnames[even_reg]); 10054 } 10055 break; 10056 case 'u': 10057 switch (value) 10058 { 10059 case 0: 10060 func (stream, dis_style_immediate, "1"); 10061 break; 10062 case 1: 10063 func (stream, dis_style_immediate, "2"); 10064 break; 10065 case 2: 10066 func (stream, dis_style_immediate, "4"); 10067 break; 10068 case 3: 10069 func (stream, dis_style_immediate, "8"); 10070 break; 10071 default: 10072 break; 10073 } 10074 break; 10075 case 'o': 10076 print_mve_rotate (info, value, width); 10077 break; 10078 case 'r': 10079 func (stream, dis_style_register, "%s", 10080 arm_regnames[value]); 10081 break; 10082 case 'd': 10083 if (mve_shift_insn_p (insn->mve_op)) 10084 print_mve_shift_n (info, given, insn->mve_op); 10085 else if (insn->mve_op == MVE_VSHLL_T2) 10086 { 10087 switch (value) 10088 { 10089 case 0x00: 10090 func (stream, dis_style_immediate, "8"); 10091 break; 10092 case 0x01: 10093 func (stream, dis_style_immediate, "16"); 10094 break; 10095 case 0x10: 10096 print_mve_undefined (info, UNDEF_SIZE_0); 10097 break; 10098 default: 10099 assert (0); 10100 break; 10101 } 10102 } 10103 else 10104 { 10105 if (insn->mve_op == MVE_VSHLC && value == 0) 10106 value = 32; 10107 func (stream, base_style, "%ld", value); 10108 value_in_comment = value; 10109 } 10110 break; 10111 case 'F': 10112 func (stream, dis_style_register, "s%ld", value); 10113 break; 10114 case 'Q': 10115 if (value & 0x8) 10116 func (stream, dis_style_text, 10117 "<illegal reg q%ld.5>", value); 10118 else 10119 func (stream, dis_style_register, "q%ld", value); 10120 break; 10121 case 'x': 10122 func (stream, dis_style_immediate, 10123 "0x%08lx", value); 10124 break; 10125 default: 10126 abort (); 10127 } 10128 break; 10129 default: 10130 abort (); 10131 } 10132 } 10133 } 10134 else 10135 { 10136 if (*c == '@') 10137 base_style = dis_style_comment_start; 10138 10139 if (*c == '\t') 10140 base_style = dis_style_text; 10141 10142 func (stream, base_style, "%c", *c); 10143 } 10144 } 10145 10146 if (value_in_comment > 32 || value_in_comment < -16) 10147 func (stream, dis_style_comment_start, "\t@ 0x%lx", 10148 value_in_comment); 10149 10150 if (is_unpredictable) 10151 print_mve_unpredictable (info, unpredictable_cond); 10152 10153 if (is_undefined) 10154 print_mve_undefined (info, undefined_cond); 10155 10156 if (!vpt_block_state.in_vpt_block 10157 && !ifthen_state 10158 && is_vpt_instruction (given)) 10159 mark_inside_vpt_block (given); 10160 else if (vpt_block_state.in_vpt_block) 10161 update_vpt_block_state (); 10162 10163 return true; 10164 } 10165 } 10166 return false; 10167 } 10168 10169 10170 /* Return the name of a v7A special register. */ 10171 10172 static const char * 10173 banked_regname (unsigned reg) 10174 { 10175 switch (reg) 10176 { 10177 case 15: return "CPSR"; 10178 case 32: return "R8_usr"; 10179 case 33: return "R9_usr"; 10180 case 34: return "R10_usr"; 10181 case 35: return "R11_usr"; 10182 case 36: return "R12_usr"; 10183 case 37: return "SP_usr"; 10184 case 38: return "LR_usr"; 10185 case 40: return "R8_fiq"; 10186 case 41: return "R9_fiq"; 10187 case 42: return "R10_fiq"; 10188 case 43: return "R11_fiq"; 10189 case 44: return "R12_fiq"; 10190 case 45: return "SP_fiq"; 10191 case 46: return "LR_fiq"; 10192 case 48: return "LR_irq"; 10193 case 49: return "SP_irq"; 10194 case 50: return "LR_svc"; 10195 case 51: return "SP_svc"; 10196 case 52: return "LR_abt"; 10197 case 53: return "SP_abt"; 10198 case 54: return "LR_und"; 10199 case 55: return "SP_und"; 10200 case 60: return "LR_mon"; 10201 case 61: return "SP_mon"; 10202 case 62: return "ELR_hyp"; 10203 case 63: return "SP_hyp"; 10204 case 79: return "SPSR"; 10205 case 110: return "SPSR_fiq"; 10206 case 112: return "SPSR_irq"; 10207 case 114: return "SPSR_svc"; 10208 case 116: return "SPSR_abt"; 10209 case 118: return "SPSR_und"; 10210 case 124: return "SPSR_mon"; 10211 case 126: return "SPSR_hyp"; 10212 default: return NULL; 10213 } 10214 } 10215 10216 /* Return the name of the DMB/DSB option. */ 10217 static const char * 10218 data_barrier_option (unsigned option) 10219 { 10220 switch (option & 0xf) 10221 { 10222 case 0xf: return "sy"; 10223 case 0xe: return "st"; 10224 case 0xd: return "ld"; 10225 case 0xb: return "ish"; 10226 case 0xa: return "ishst"; 10227 case 0x9: return "ishld"; 10228 case 0x7: return "un"; 10229 case 0x6: return "unst"; 10230 case 0x5: return "nshld"; 10231 case 0x3: return "osh"; 10232 case 0x2: return "oshst"; 10233 case 0x1: return "oshld"; 10234 default: return NULL; 10235 } 10236 } 10237 10238 /* Print one ARM instruction from PC on INFO->STREAM. */ 10239 10240 static void 10241 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 10242 { 10243 const struct opcode32 *insn; 10244 void *stream = info->stream; 10245 fprintf_styled_ftype func = info->fprintf_styled_func; 10246 struct arm_private_data *private_data = info->private_data; 10247 enum disassembler_style base_style = dis_style_mnemonic; 10248 enum disassembler_style old_base_style = base_style; 10249 10250 if (print_insn_coprocessor (pc, info, given, false)) 10251 return; 10252 10253 if (print_insn_neon (info, given, false)) 10254 return; 10255 10256 if (print_insn_generic_coprocessor (pc, info, given, false)) 10257 return; 10258 10259 for (insn = arm_opcodes; insn->assembler; insn++) 10260 { 10261 if ((given & insn->mask) != insn->value) 10262 continue; 10263 10264 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 10265 continue; 10266 10267 /* Special case: an instruction with all bits set in the condition field 10268 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 10269 or by the catchall at the end of the table. */ 10270 if ((given & 0xF0000000) != 0xF0000000 10271 || (insn->mask & 0xF0000000) == 0xF0000000 10272 || (insn->mask == 0 && insn->value == 0)) 10273 { 10274 unsigned long u_reg = 16; 10275 unsigned long U_reg = 16; 10276 bool is_unpredictable = false; 10277 signed long value_in_comment = 0; 10278 const char *c; 10279 10280 for (c = insn->assembler; *c; c++) 10281 { 10282 if (*c == '%') 10283 { 10284 bool allow_unpredictable = false; 10285 10286 switch (*++c) 10287 { 10288 case '{': 10289 ++c; 10290 if (*c == '\0') 10291 abort (); 10292 old_base_style = base_style; 10293 base_style = decode_base_style (*c); 10294 ++c; 10295 if (*c != ':') 10296 abort (); 10297 break; 10298 10299 case '}': 10300 base_style = old_base_style; 10301 break; 10302 10303 case '%': 10304 func (stream, base_style, "%%"); 10305 break; 10306 10307 case 'a': 10308 value_in_comment = print_arm_address (pc, info, given); 10309 break; 10310 10311 case 'P': 10312 /* Set P address bit and use normal address 10313 printing routine. */ 10314 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 10315 break; 10316 10317 case 'S': 10318 allow_unpredictable = true; 10319 /* Fall through. */ 10320 case 's': 10321 if ((given & 0x004f0000) == 0x004f0000) 10322 { 10323 /* PC relative with immediate offset. */ 10324 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 10325 10326 if (PRE_BIT_SET) 10327 { 10328 /* Elide positive zero offset. */ 10329 if (offset || NEGATIVE_BIT_SET) 10330 { 10331 func (stream, dis_style_text, "["); 10332 func (stream, dis_style_register, "pc"); 10333 func (stream, dis_style_text, ", "); 10334 func (stream, dis_style_immediate, "#%s%d", 10335 (NEGATIVE_BIT_SET ? "-" : ""), 10336 (int) offset); 10337 func (stream, dis_style_text, "]"); 10338 } 10339 else 10340 { 10341 func (stream, dis_style_text, "["); 10342 func (stream, dis_style_register, "pc"); 10343 func (stream, dis_style_text, "]"); 10344 } 10345 if (NEGATIVE_BIT_SET) 10346 offset = -offset; 10347 func (stream, dis_style_comment_start, "\t@ "); 10348 info->print_address_func (offset + pc + 8, info); 10349 } 10350 else 10351 { 10352 /* Always show the offset. */ 10353 func (stream, dis_style_text, "["); 10354 func (stream, dis_style_register, "pc"); 10355 func (stream, dis_style_text, "], "); 10356 func (stream, dis_style_immediate, "#%s%d", 10357 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10358 if (! allow_unpredictable) 10359 is_unpredictable = true; 10360 } 10361 } 10362 else 10363 { 10364 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 10365 10366 func (stream, dis_style_text, "["); 10367 func (stream, dis_style_register, "%s", 10368 arm_regnames[(given >> 16) & 0xf]); 10369 10370 if (PRE_BIT_SET) 10371 { 10372 if (IMMEDIATE_BIT_SET) 10373 { 10374 /* Elide offset for non-writeback 10375 positive zero. */ 10376 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 10377 || offset) 10378 { 10379 func (stream, dis_style_text, ", "); 10380 func (stream, dis_style_immediate, 10381 "#%s%d", 10382 (NEGATIVE_BIT_SET ? "-" : ""), 10383 offset); 10384 } 10385 10386 if (NEGATIVE_BIT_SET) 10387 offset = -offset; 10388 10389 value_in_comment = offset; 10390 } 10391 else 10392 { 10393 /* Register Offset or Register Pre-Indexed. */ 10394 func (stream, dis_style_text, ", %s", 10395 NEGATIVE_BIT_SET ? "-" : ""); 10396 func (stream, dis_style_register, "%s", 10397 arm_regnames[given & 0xf]); 10398 10399 /* Writing back to the register that is the source/ 10400 destination of the load/store is unpredictable. */ 10401 if (! allow_unpredictable 10402 && WRITEBACK_BIT_SET 10403 && ((given & 0xf) == ((given >> 12) & 0xf))) 10404 is_unpredictable = true; 10405 } 10406 10407 func (stream, dis_style_text, "]%s", 10408 WRITEBACK_BIT_SET ? "!" : ""); 10409 } 10410 else 10411 { 10412 if (IMMEDIATE_BIT_SET) 10413 { 10414 /* Immediate Post-indexed. */ 10415 /* PR 10924: Offset must be printed, even if it is zero. */ 10416 func (stream, dis_style_text, "], "); 10417 func (stream, dis_style_immediate, "#%s%d", 10418 NEGATIVE_BIT_SET ? "-" : "", offset); 10419 if (NEGATIVE_BIT_SET) 10420 offset = -offset; 10421 value_in_comment = offset; 10422 } 10423 else 10424 { 10425 /* Register Post-indexed. */ 10426 func (stream, dis_style_text, "], %s", 10427 NEGATIVE_BIT_SET ? "-" : ""); 10428 func (stream, dis_style_register, "%s", 10429 arm_regnames[given & 0xf]); 10430 10431 /* Writing back to the register that is the source/ 10432 destination of the load/store is unpredictable. */ 10433 if (! allow_unpredictable 10434 && (given & 0xf) == ((given >> 12) & 0xf)) 10435 is_unpredictable = true; 10436 } 10437 10438 if (! allow_unpredictable) 10439 { 10440 /* Writeback is automatically implied by post- addressing. 10441 Setting the W bit is unnecessary and ARM specify it as 10442 being unpredictable. */ 10443 if (WRITEBACK_BIT_SET 10444 /* Specifying the PC register as the post-indexed 10445 registers is also unpredictable. */ 10446 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 10447 is_unpredictable = true; 10448 } 10449 } 10450 } 10451 break; 10452 10453 case 'b': 10454 { 10455 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 10456 bfd_vma target = disp * 4 + pc + 8; 10457 info->print_address_func (target, info); 10458 10459 /* Fill in instruction information. */ 10460 info->insn_info_valid = 1; 10461 info->insn_type = dis_branch; 10462 info->target = target; 10463 } 10464 break; 10465 10466 case 'c': 10467 if (((given >> 28) & 0xf) != 0xe) 10468 func (stream, dis_style_mnemonic, "%s", 10469 arm_conditional [(given >> 28) & 0xf]); 10470 break; 10471 10472 case 'm': 10473 { 10474 int started = 0; 10475 int reg; 10476 10477 func (stream, dis_style_text, "{"); 10478 for (reg = 0; reg < 16; reg++) 10479 if ((given & (1 << reg)) != 0) 10480 { 10481 if (started) 10482 func (stream, dis_style_text, ", "); 10483 started = 1; 10484 func (stream, dis_style_register, "%s", 10485 arm_regnames[reg]); 10486 } 10487 func (stream, dis_style_text, "}"); 10488 if (! started) 10489 is_unpredictable = true; 10490 } 10491 break; 10492 10493 case 'q': 10494 arm_decode_shift (given, func, stream, false); 10495 break; 10496 10497 case 'o': 10498 if ((given & 0x02000000) != 0) 10499 { 10500 unsigned int rotate = (given & 0xf00) >> 7; 10501 unsigned int immed = (given & 0xff); 10502 unsigned int a, i; 10503 10504 a = (immed << ((32 - rotate) & 31) 10505 | immed >> rotate) & 0xffffffff; 10506 /* If there is another encoding with smaller rotate, 10507 the rotate should be specified directly. */ 10508 for (i = 0; i < 32; i += 2) 10509 if ((a << i | a >> ((32 - i) & 31)) <= 0xff) 10510 break; 10511 10512 if (i != rotate) 10513 { 10514 func (stream, dis_style_immediate, "#%d", immed); 10515 func (stream, dis_style_text, ", "); 10516 func (stream, dis_style_immediate, "%d", rotate); 10517 } 10518 else 10519 func (stream, dis_style_immediate, "#%d", a); 10520 value_in_comment = a; 10521 } 10522 else 10523 arm_decode_shift (given, func, stream, true); 10524 break; 10525 10526 case 'p': 10527 if ((given & 0x0000f000) == 0x0000f000) 10528 { 10529 arm_feature_set arm_ext_v6 = 10530 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 10531 10532 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 10533 mechanism for setting PSR flag bits. They are 10534 obsolete in V6 onwards. */ 10535 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 10536 arm_ext_v6)) 10537 func (stream, dis_style_mnemonic, "p"); 10538 else 10539 is_unpredictable = true; 10540 } 10541 break; 10542 10543 case 't': 10544 if ((given & 0x01200000) == 0x00200000) 10545 func (stream, dis_style_mnemonic, "t"); 10546 break; 10547 10548 case 'A': 10549 { 10550 int offset = given & 0xff; 10551 10552 value_in_comment = offset * 4; 10553 if (NEGATIVE_BIT_SET) 10554 value_in_comment = - value_in_comment; 10555 10556 func (stream, dis_style_text, "[%s", 10557 arm_regnames [(given >> 16) & 0xf]); 10558 10559 if (PRE_BIT_SET) 10560 { 10561 if (offset) 10562 func (stream, dis_style_text, ", #%d]%s", 10563 (int) value_in_comment, 10564 WRITEBACK_BIT_SET ? "!" : ""); 10565 else 10566 func (stream, dis_style_text, "]"); 10567 } 10568 else 10569 { 10570 func (stream, dis_style_text, "]"); 10571 10572 if (WRITEBACK_BIT_SET) 10573 { 10574 if (offset) 10575 func (stream, dis_style_text, 10576 ", #%d", (int) value_in_comment); 10577 } 10578 else 10579 { 10580 func (stream, dis_style_text, 10581 ", {%d}", (int) offset); 10582 value_in_comment = offset; 10583 } 10584 } 10585 } 10586 break; 10587 10588 case 'B': 10589 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 10590 { 10591 bfd_vma address; 10592 bfd_vma offset = 0; 10593 10594 if (! NEGATIVE_BIT_SET) 10595 /* Is signed, hi bits should be ones. */ 10596 offset = (-1) ^ 0x00ffffff; 10597 10598 /* Offset is (SignExtend(offset field)<<2). */ 10599 offset += given & 0x00ffffff; 10600 offset <<= 2; 10601 address = offset + pc + 8; 10602 10603 if (given & 0x01000000) 10604 /* H bit allows addressing to 2-byte boundaries. */ 10605 address += 2; 10606 10607 info->print_address_func (address, info); 10608 10609 /* Fill in instruction information. */ 10610 info->insn_info_valid = 1; 10611 info->insn_type = dis_branch; 10612 info->target = address; 10613 } 10614 break; 10615 10616 case 'C': 10617 if ((given & 0x02000200) == 0x200) 10618 { 10619 const char * name; 10620 unsigned sysm = (given & 0x004f0000) >> 16; 10621 10622 sysm |= (given & 0x300) >> 4; 10623 name = banked_regname (sysm); 10624 10625 if (name != NULL) 10626 func (stream, dis_style_register, "%s", name); 10627 else 10628 func (stream, dis_style_text, 10629 "(UNDEF: %lu)", (unsigned long) sysm); 10630 } 10631 else 10632 { 10633 func (stream, dis_style_register, "%cPSR_", 10634 (given & 0x00400000) ? 'S' : 'C'); 10635 10636 if (given & 0x80000) 10637 func (stream, dis_style_register, "f"); 10638 if (given & 0x40000) 10639 func (stream, dis_style_register, "s"); 10640 if (given & 0x20000) 10641 func (stream, dis_style_register, "x"); 10642 if (given & 0x10000) 10643 func (stream, dis_style_register, "c"); 10644 } 10645 break; 10646 10647 case 'U': 10648 if ((given & 0xf0) == 0x60) 10649 { 10650 switch (given & 0xf) 10651 { 10652 case 0xf: 10653 func (stream, dis_style_sub_mnemonic, "sy"); 10654 break; 10655 default: 10656 func (stream, dis_style_immediate, "#%d", 10657 (int) given & 0xf); 10658 break; 10659 } 10660 } 10661 else 10662 { 10663 const char * opt = data_barrier_option (given & 0xf); 10664 if (opt != NULL) 10665 func (stream, dis_style_sub_mnemonic, "%s", opt); 10666 else 10667 func (stream, dis_style_immediate, 10668 "#%d", (int) given & 0xf); 10669 } 10670 break; 10671 10672 case '0': case '1': case '2': case '3': case '4': 10673 case '5': case '6': case '7': case '8': case '9': 10674 { 10675 int width; 10676 unsigned long value; 10677 10678 c = arm_decode_bitfield (c, given, &value, &width); 10679 10680 switch (*c) 10681 { 10682 case 'R': 10683 if (value == 15) 10684 is_unpredictable = true; 10685 /* Fall through. */ 10686 case 'r': 10687 case 'T': 10688 /* We want register + 1 when decoding T. */ 10689 if (*c == 'T') 10690 value = (value + 1) & 0xf; 10691 10692 if (c[1] == 'u') 10693 { 10694 /* Eat the 'u' character. */ 10695 ++ c; 10696 10697 if (u_reg == value) 10698 is_unpredictable = true; 10699 u_reg = value; 10700 } 10701 if (c[1] == 'U') 10702 { 10703 /* Eat the 'U' character. */ 10704 ++ c; 10705 10706 if (U_reg == value) 10707 is_unpredictable = true; 10708 U_reg = value; 10709 } 10710 func (stream, dis_style_register, "%s", 10711 arm_regnames[value]); 10712 break; 10713 case 'd': 10714 func (stream, base_style, "%ld", value); 10715 value_in_comment = value; 10716 break; 10717 case 'b': 10718 func (stream, dis_style_immediate, 10719 "%ld", value * 8); 10720 value_in_comment = value * 8; 10721 break; 10722 case 'W': 10723 func (stream, dis_style_immediate, 10724 "%ld", value + 1); 10725 value_in_comment = value + 1; 10726 break; 10727 case 'x': 10728 func (stream, dis_style_immediate, 10729 "0x%08lx", value); 10730 10731 /* Some SWI instructions have special 10732 meanings. */ 10733 if ((given & 0x0fffffff) == 0x0FF00000) 10734 func (stream, dis_style_comment_start, 10735 "\t@ IMB"); 10736 else if ((given & 0x0fffffff) == 0x0FF00001) 10737 func (stream, dis_style_comment_start, 10738 "\t@ IMBRange"); 10739 break; 10740 case 'X': 10741 func (stream, dis_style_immediate, 10742 "%01lx", value & 0xf); 10743 value_in_comment = value; 10744 break; 10745 case '`': 10746 c++; 10747 if (value == 0) 10748 func (stream, dis_style_text, "%c", *c); 10749 break; 10750 case '\'': 10751 c++; 10752 if (value == ((1ul << width) - 1)) 10753 func (stream, base_style, "%c", *c); 10754 break; 10755 case '?': 10756 func (stream, base_style, "%c", 10757 c[(1 << width) - (int) value]); 10758 c += 1 << width; 10759 break; 10760 default: 10761 abort (); 10762 } 10763 } 10764 break; 10765 10766 case 'e': 10767 { 10768 int imm; 10769 10770 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 10771 func (stream, dis_style_immediate, "%d", imm); 10772 value_in_comment = imm; 10773 } 10774 break; 10775 10776 case 'E': 10777 /* LSB and WIDTH fields of BFI or BFC. The machine- 10778 language instruction encodes LSB and MSB. */ 10779 { 10780 long msb = (given & 0x001f0000) >> 16; 10781 long lsb = (given & 0x00000f80) >> 7; 10782 long w = msb - lsb + 1; 10783 10784 if (w > 0) 10785 { 10786 func (stream, dis_style_immediate, "#%lu", lsb); 10787 func (stream, dis_style_text, ", "); 10788 func (stream, dis_style_immediate, "#%lu", w); 10789 } 10790 else 10791 func (stream, dis_style_text, 10792 "(invalid: %lu:%lu)", lsb, msb); 10793 } 10794 break; 10795 10796 case 'R': 10797 /* Get the PSR/banked register name. */ 10798 { 10799 const char * name; 10800 unsigned sysm = (given & 0x004f0000) >> 16; 10801 10802 sysm |= (given & 0x300) >> 4; 10803 name = banked_regname (sysm); 10804 10805 if (name != NULL) 10806 func (stream, dis_style_register, "%s", name); 10807 else 10808 func (stream, dis_style_text, 10809 "(UNDEF: %lu)", (unsigned long) sysm); 10810 } 10811 break; 10812 10813 case 'V': 10814 /* 16-bit unsigned immediate from a MOVT or MOVW 10815 instruction, encoded in bits 0:11 and 15:19. */ 10816 { 10817 long hi = (given & 0x000f0000) >> 4; 10818 long lo = (given & 0x00000fff); 10819 long imm16 = hi | lo; 10820 10821 func (stream, dis_style_immediate, "#%lu", imm16); 10822 value_in_comment = imm16; 10823 } 10824 break; 10825 10826 default: 10827 abort (); 10828 } 10829 } 10830 else 10831 { 10832 10833 if (*c == '@') 10834 base_style = dis_style_comment_start; 10835 10836 if (*c == '\t') 10837 base_style = dis_style_text; 10838 10839 func (stream, base_style, "%c", *c); 10840 } 10841 } 10842 10843 if (value_in_comment > 32 || value_in_comment < -16) 10844 func (stream, dis_style_comment_start, "\t@ 0x%lx", 10845 (value_in_comment & 0xffffffffUL)); 10846 10847 if (is_unpredictable) 10848 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 10849 10850 return; 10851 } 10852 } 10853 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT, 10854 (unsigned) given); 10855 return; 10856 } 10857 10858 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 10859 10860 static void 10861 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 10862 { 10863 const struct opcode16 *insn; 10864 void *stream = info->stream; 10865 fprintf_styled_ftype func = info->fprintf_styled_func; 10866 enum disassembler_style base_style = dis_style_mnemonic; 10867 enum disassembler_style old_base_style = base_style; 10868 10869 for (insn = thumb_opcodes; insn->assembler; insn++) 10870 if ((given & insn->mask) == insn->value) 10871 { 10872 signed long value_in_comment = 0; 10873 const char *c = insn->assembler; 10874 10875 for (; *c; c++) 10876 { 10877 int domaskpc = 0; 10878 int domasklr = 0; 10879 10880 if (*c != '%') 10881 { 10882 if (*c == '@') 10883 base_style = dis_style_comment_start; 10884 10885 if (*c == '\t') 10886 base_style = dis_style_text; 10887 10888 func (stream, base_style, "%c", *c); 10889 10890 continue; 10891 } 10892 10893 switch (*++c) 10894 { 10895 case '{': 10896 ++c; 10897 if (*c == '\0') 10898 abort (); 10899 old_base_style = base_style; 10900 base_style = decode_base_style (*c); 10901 ++c; 10902 if (*c != ':') 10903 abort (); 10904 break; 10905 10906 case '}': 10907 base_style = old_base_style; 10908 break; 10909 10910 case '%': 10911 func (stream, base_style, "%%"); 10912 break; 10913 10914 case 'c': 10915 if (ifthen_state) 10916 func (stream, dis_style_mnemonic, "%s", 10917 arm_conditional[IFTHEN_COND]); 10918 break; 10919 10920 case 'C': 10921 if (ifthen_state) 10922 func (stream, dis_style_mnemonic, "%s", 10923 arm_conditional[IFTHEN_COND]); 10924 else 10925 func (stream, dis_style_mnemonic, "s"); 10926 break; 10927 10928 case 'I': 10929 { 10930 unsigned int tmp; 10931 10932 ifthen_next_state = given & 0xff; 10933 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 10934 func (stream, dis_style_mnemonic, 10935 ((given ^ tmp) & 0x10) ? "e" : "t"); 10936 func (stream, dis_style_text, "\t"); 10937 func (stream, dis_style_sub_mnemonic, "%s", 10938 arm_conditional[(given >> 4) & 0xf]); 10939 } 10940 break; 10941 10942 case 'x': 10943 if (ifthen_next_state) 10944 func (stream, dis_style_comment_start, 10945 "\t@ unpredictable branch in IT block\n"); 10946 break; 10947 10948 case 'X': 10949 if (ifthen_state) 10950 func (stream, dis_style_comment_start, 10951 "\t@ unpredictable <IT:%s>", 10952 arm_conditional[IFTHEN_COND]); 10953 break; 10954 10955 case 'S': 10956 { 10957 long reg; 10958 10959 reg = (given >> 3) & 0x7; 10960 if (given & (1 << 6)) 10961 reg += 8; 10962 10963 func (stream, dis_style_register, "%s", arm_regnames[reg]); 10964 } 10965 break; 10966 10967 case 'D': 10968 { 10969 long reg; 10970 10971 reg = given & 0x7; 10972 if (given & (1 << 7)) 10973 reg += 8; 10974 10975 func (stream, dis_style_register, "%s", arm_regnames[reg]); 10976 } 10977 break; 10978 10979 case 'N': 10980 if (given & (1 << 8)) 10981 domasklr = 1; 10982 /* Fall through. */ 10983 case 'O': 10984 if (*c == 'O' && (given & (1 << 8))) 10985 domaskpc = 1; 10986 /* Fall through. */ 10987 case 'M': 10988 { 10989 int started = 0; 10990 int reg; 10991 10992 func (stream, dis_style_text, "{"); 10993 10994 /* It would be nice if we could spot 10995 ranges, and generate the rS-rE format: */ 10996 for (reg = 0; (reg < 8); reg++) 10997 if ((given & (1 << reg)) != 0) 10998 { 10999 if (started) 11000 func (stream, dis_style_text, ", "); 11001 started = 1; 11002 func (stream, dis_style_register, "%s", 11003 arm_regnames[reg]); 11004 } 11005 11006 if (domasklr) 11007 { 11008 if (started) 11009 func (stream, dis_style_text, ", "); 11010 started = 1; 11011 func (stream, dis_style_register, "%s", 11012 arm_regnames[14] /* "lr" */); 11013 } 11014 11015 if (domaskpc) 11016 { 11017 if (started) 11018 func (stream, dis_style_text, ", "); 11019 func (stream, dis_style_register, "%s", 11020 arm_regnames[15] /* "pc" */); 11021 } 11022 11023 func (stream, dis_style_text, "}"); 11024 } 11025 break; 11026 11027 case 'W': 11028 /* Print writeback indicator for a LDMIA. We are doing a 11029 writeback if the base register is not in the register 11030 mask. */ 11031 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 11032 func (stream, dis_style_text, "!"); 11033 break; 11034 11035 case 'b': 11036 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 11037 { 11038 bfd_vma address = (pc + 4 11039 + ((given & 0x00f8) >> 2) 11040 + ((given & 0x0200) >> 3)); 11041 info->print_address_func (address, info); 11042 11043 /* Fill in instruction information. */ 11044 info->insn_info_valid = 1; 11045 info->insn_type = dis_branch; 11046 info->target = address; 11047 } 11048 break; 11049 11050 case 's': 11051 /* Right shift immediate -- bits 6..10; 1-31 print 11052 as themselves, 0 prints as 32. */ 11053 { 11054 long imm = (given & 0x07c0) >> 6; 11055 if (imm == 0) 11056 imm = 32; 11057 func (stream, dis_style_immediate, "#%ld", imm); 11058 } 11059 break; 11060 11061 case '0': case '1': case '2': case '3': case '4': 11062 case '5': case '6': case '7': case '8': case '9': 11063 { 11064 int bitstart = *c++ - '0'; 11065 int bitend = 0; 11066 11067 while (*c >= '0' && *c <= '9') 11068 bitstart = (bitstart * 10) + *c++ - '0'; 11069 11070 switch (*c) 11071 { 11072 case '-': 11073 { 11074 bfd_vma reg; 11075 11076 c++; 11077 while (*c >= '0' && *c <= '9') 11078 bitend = (bitend * 10) + *c++ - '0'; 11079 if (!bitend) 11080 abort (); 11081 reg = given >> bitstart; 11082 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1; 11083 11084 switch (*c) 11085 { 11086 case 'r': 11087 func (stream, dis_style_register, "%s", 11088 arm_regnames[reg]); 11089 break; 11090 11091 case 'd': 11092 func (stream, dis_style_immediate, "%ld", 11093 (long) reg); 11094 value_in_comment = reg; 11095 break; 11096 11097 case 'H': 11098 func (stream, dis_style_immediate, "%ld", 11099 (long) (reg << 1)); 11100 value_in_comment = reg << 1; 11101 break; 11102 11103 case 'W': 11104 func (stream, dis_style_immediate, "%ld", 11105 (long) (reg << 2)); 11106 value_in_comment = reg << 2; 11107 break; 11108 11109 case 'a': 11110 /* PC-relative address -- the bottom two 11111 bits of the address are dropped 11112 before the calculation. */ 11113 info->print_address_func 11114 (((pc + 4) & ~3) + (reg << 2), info); 11115 value_in_comment = 0; 11116 break; 11117 11118 case 'x': 11119 func (stream, dis_style_immediate, "0x%04lx", 11120 (long) reg); 11121 break; 11122 11123 case 'B': 11124 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 11125 bfd_vma target = reg * 2 + pc + 4; 11126 info->print_address_func (target, info); 11127 value_in_comment = 0; 11128 11129 /* Fill in instruction information. */ 11130 info->insn_info_valid = 1; 11131 info->insn_type = dis_branch; 11132 info->target = target; 11133 break; 11134 11135 case 'c': 11136 func (stream, dis_style_mnemonic, "%s", 11137 arm_conditional [reg]); 11138 break; 11139 11140 default: 11141 abort (); 11142 } 11143 } 11144 break; 11145 11146 case '\'': 11147 c++; 11148 if ((given & (1 << bitstart)) != 0) 11149 func (stream, base_style, "%c", *c); 11150 break; 11151 11152 case '?': 11153 ++c; 11154 if ((given & (1 << bitstart)) != 0) 11155 func (stream, base_style, "%c", *c++); 11156 else 11157 func (stream, base_style, "%c", *++c); 11158 break; 11159 11160 default: 11161 abort (); 11162 } 11163 } 11164 break; 11165 11166 default: 11167 abort (); 11168 } 11169 } 11170 11171 if (value_in_comment > 32 || value_in_comment < -16) 11172 func (stream, dis_style_comment_start, 11173 "\t@ 0x%lx", value_in_comment); 11174 return; 11175 } 11176 11177 /* No match. */ 11178 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT, 11179 (unsigned) given); 11180 return; 11181 } 11182 11183 /* Return the name of an V7M special register. */ 11184 11185 static const char * 11186 psr_name (int regno) 11187 { 11188 switch (regno) 11189 { 11190 case 0x0: return "APSR"; 11191 case 0x1: return "IAPSR"; 11192 case 0x2: return "EAPSR"; 11193 case 0x3: return "PSR"; 11194 case 0x5: return "IPSR"; 11195 case 0x6: return "EPSR"; 11196 case 0x7: return "IEPSR"; 11197 case 0x8: return "MSP"; 11198 case 0x9: return "PSP"; 11199 case 0xa: return "MSPLIM"; 11200 case 0xb: return "PSPLIM"; 11201 case 0x10: return "PRIMASK"; 11202 case 0x11: return "BASEPRI"; 11203 case 0x12: return "BASEPRI_MAX"; 11204 case 0x13: return "FAULTMASK"; 11205 case 0x14: return "CONTROL"; 11206 case 0x88: return "MSP_NS"; 11207 case 0x89: return "PSP_NS"; 11208 case 0x8a: return "MSPLIM_NS"; 11209 case 0x8b: return "PSPLIM_NS"; 11210 case 0x90: return "PRIMASK_NS"; 11211 case 0x91: return "BASEPRI_NS"; 11212 case 0x93: return "FAULTMASK_NS"; 11213 case 0x94: return "CONTROL_NS"; 11214 case 0x98: return "SP_NS"; 11215 default: return "<unknown>"; 11216 } 11217 } 11218 11219 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 11220 11221 static void 11222 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 11223 { 11224 const struct opcode32 *insn; 11225 void *stream = info->stream; 11226 fprintf_styled_ftype func = info->fprintf_styled_func; 11227 bool is_mve = is_mve_architecture (info); 11228 enum disassembler_style base_style = dis_style_mnemonic; 11229 enum disassembler_style old_base_style = base_style; 11230 11231 if (print_insn_coprocessor (pc, info, given, true)) 11232 return; 11233 11234 if (!is_mve && print_insn_neon (info, given, true)) 11235 return; 11236 11237 if (is_mve && print_insn_mve (info, given)) 11238 return; 11239 11240 if (print_insn_cde (info, given, true)) 11241 return; 11242 11243 if (print_insn_generic_coprocessor (pc, info, given, true)) 11244 return; 11245 11246 for (insn = thumb32_opcodes; insn->assembler; insn++) 11247 if ((given & insn->mask) == insn->value) 11248 { 11249 bool is_clrm = false; 11250 bool is_unpredictable = false; 11251 signed long value_in_comment = 0; 11252 const char *c = insn->assembler; 11253 11254 for (; *c; c++) 11255 { 11256 if (*c != '%') 11257 { 11258 if (*c == '@') 11259 base_style = dis_style_comment_start; 11260 if (*c == '\t') 11261 base_style = dis_style_text; 11262 func (stream, base_style, "%c", *c); 11263 continue; 11264 } 11265 11266 switch (*++c) 11267 { 11268 case '{': 11269 ++c; 11270 if (*c == '\0') 11271 abort (); 11272 old_base_style = base_style; 11273 base_style = decode_base_style (*c); 11274 ++c; 11275 if (*c != ':') 11276 abort (); 11277 break; 11278 11279 case '}': 11280 base_style = old_base_style; 11281 break; 11282 11283 case '%': 11284 func (stream, base_style, "%%"); 11285 break; 11286 11287 case 'c': 11288 if (ifthen_state) 11289 func (stream, dis_style_mnemonic, "%s", 11290 arm_conditional[IFTHEN_COND]); 11291 break; 11292 11293 case 'x': 11294 if (ifthen_next_state) 11295 func (stream, dis_style_comment_start, 11296 "\t@ unpredictable branch in IT block\n"); 11297 break; 11298 11299 case 'X': 11300 if (ifthen_state) 11301 func (stream, dis_style_comment_start, 11302 "\t@ unpredictable <IT:%s>", 11303 arm_conditional[IFTHEN_COND]); 11304 break; 11305 11306 case 'I': 11307 { 11308 unsigned int imm12 = 0; 11309 11310 imm12 |= (given & 0x000000ffu); 11311 imm12 |= (given & 0x00007000u) >> 4; 11312 imm12 |= (given & 0x04000000u) >> 15; 11313 func (stream, dis_style_immediate, "#%u", imm12); 11314 value_in_comment = imm12; 11315 } 11316 break; 11317 11318 case 'M': 11319 { 11320 unsigned int bits = 0, imm, imm8, mod; 11321 11322 bits |= (given & 0x000000ffu); 11323 bits |= (given & 0x00007000u) >> 4; 11324 bits |= (given & 0x04000000u) >> 15; 11325 imm8 = (bits & 0x0ff); 11326 mod = (bits & 0xf00) >> 8; 11327 switch (mod) 11328 { 11329 case 0: imm = imm8; break; 11330 case 1: imm = ((imm8 << 16) | imm8); break; 11331 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 11332 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 11333 default: 11334 mod = (bits & 0xf80) >> 7; 11335 imm8 = (bits & 0x07f) | 0x80; 11336 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 11337 } 11338 func (stream, dis_style_immediate, "#%u", imm); 11339 value_in_comment = imm; 11340 } 11341 break; 11342 11343 case 'J': 11344 { 11345 unsigned int imm = 0; 11346 11347 imm |= (given & 0x000000ffu); 11348 imm |= (given & 0x00007000u) >> 4; 11349 imm |= (given & 0x04000000u) >> 15; 11350 imm |= (given & 0x000f0000u) >> 4; 11351 func (stream, dis_style_immediate, "#%u", imm); 11352 value_in_comment = imm; 11353 } 11354 break; 11355 11356 case 'K': 11357 { 11358 unsigned int imm = 0; 11359 11360 imm |= (given & 0x000f0000u) >> 16; 11361 imm |= (given & 0x00000ff0u) >> 0; 11362 imm |= (given & 0x0000000fu) << 12; 11363 func (stream, dis_style_immediate, "#%u", imm); 11364 value_in_comment = imm; 11365 } 11366 break; 11367 11368 case 'H': 11369 { 11370 unsigned int imm = 0; 11371 11372 imm |= (given & 0x000f0000u) >> 4; 11373 imm |= (given & 0x00000fffu) >> 0; 11374 func (stream, dis_style_immediate, "#%u", imm); 11375 value_in_comment = imm; 11376 } 11377 break; 11378 11379 case 'V': 11380 { 11381 unsigned int imm = 0; 11382 11383 imm |= (given & 0x00000fffu); 11384 imm |= (given & 0x000f0000u) >> 4; 11385 func (stream, dis_style_immediate, "#%u", imm); 11386 value_in_comment = imm; 11387 } 11388 break; 11389 11390 case 'S': 11391 { 11392 unsigned int reg = (given & 0x0000000fu); 11393 unsigned int stp = (given & 0x00000030u) >> 4; 11394 unsigned int imm = 0; 11395 imm |= (given & 0x000000c0u) >> 6; 11396 imm |= (given & 0x00007000u) >> 10; 11397 11398 func (stream, dis_style_register, "%s", arm_regnames[reg]); 11399 switch (stp) 11400 { 11401 case 0: 11402 if (imm > 0) 11403 { 11404 func (stream, dis_style_text, ", "); 11405 func (stream, dis_style_sub_mnemonic, "lsl "); 11406 func (stream, dis_style_immediate, "#%u", imm); 11407 } 11408 break; 11409 11410 case 1: 11411 if (imm == 0) 11412 imm = 32; 11413 func (stream, dis_style_text, ", "); 11414 func (stream, dis_style_sub_mnemonic, "lsr "); 11415 func (stream, dis_style_immediate, "#%u", imm); 11416 break; 11417 11418 case 2: 11419 if (imm == 0) 11420 imm = 32; 11421 func (stream, dis_style_text, ", "); 11422 func (stream, dis_style_sub_mnemonic, "asr "); 11423 func (stream, dis_style_immediate, "#%u", imm); 11424 break; 11425 11426 case 3: 11427 if (imm == 0) 11428 { 11429 func (stream, dis_style_text, ", "); 11430 func (stream, dis_style_sub_mnemonic, "rrx"); 11431 } 11432 else 11433 { 11434 func (stream, dis_style_text, ", "); 11435 func (stream, dis_style_sub_mnemonic, "ror "); 11436 func (stream, dis_style_immediate, "#%u", imm); 11437 } 11438 } 11439 } 11440 break; 11441 11442 case 'a': 11443 { 11444 unsigned int Rn = (given & 0x000f0000) >> 16; 11445 unsigned int U = ! NEGATIVE_BIT_SET; 11446 unsigned int op = (given & 0x00000f00) >> 8; 11447 unsigned int i12 = (given & 0x00000fff); 11448 unsigned int i8 = (given & 0x000000ff); 11449 bool writeback = false, postind = false; 11450 bfd_vma offset = 0; 11451 11452 func (stream, dis_style_text, "["); 11453 func (stream, dis_style_register, "%s", arm_regnames[Rn]); 11454 if (U) /* 12-bit positive immediate offset. */ 11455 { 11456 offset = i12; 11457 if (Rn != 15) 11458 value_in_comment = offset; 11459 } 11460 else if (Rn == 15) /* 12-bit negative immediate offset. */ 11461 offset = - (int) i12; 11462 else if (op == 0x0) /* Shifted register offset. */ 11463 { 11464 unsigned int Rm = (i8 & 0x0f); 11465 unsigned int sh = (i8 & 0x30) >> 4; 11466 11467 func (stream, dis_style_text, ", "); 11468 func (stream, dis_style_register, "%s", 11469 arm_regnames[Rm]); 11470 if (sh) 11471 { 11472 func (stream, dis_style_text, ", "); 11473 func (stream, dis_style_sub_mnemonic, "lsl "); 11474 func (stream, dis_style_immediate, "#%u", sh); 11475 } 11476 func (stream, dis_style_text, "]"); 11477 break; 11478 } 11479 else switch (op) 11480 { 11481 case 0xE: /* 8-bit positive immediate offset. */ 11482 offset = i8; 11483 break; 11484 11485 case 0xC: /* 8-bit negative immediate offset. */ 11486 offset = -i8; 11487 break; 11488 11489 case 0xF: /* 8-bit + preindex with wb. */ 11490 offset = i8; 11491 writeback = true; 11492 break; 11493 11494 case 0xD: /* 8-bit - preindex with wb. */ 11495 offset = -i8; 11496 writeback = true; 11497 break; 11498 11499 case 0xB: /* 8-bit + postindex. */ 11500 offset = i8; 11501 postind = true; 11502 break; 11503 11504 case 0x9: /* 8-bit - postindex. */ 11505 offset = -i8; 11506 postind = true; 11507 break; 11508 11509 default: 11510 func (stream, dis_style_text, ", <undefined>]"); 11511 goto skip; 11512 } 11513 11514 if (postind) 11515 { 11516 func (stream, dis_style_text, "], "); 11517 func (stream, dis_style_immediate, "#%d", (int) offset); 11518 } 11519 else 11520 { 11521 if (offset) 11522 { 11523 func (stream, dis_style_text, ", "); 11524 func (stream, dis_style_immediate, "#%d", 11525 (int) offset); 11526 } 11527 func (stream, dis_style_text, writeback ? "]!" : "]"); 11528 } 11529 11530 if (Rn == 15) 11531 { 11532 func (stream, dis_style_comment_start, "\t@ "); 11533 info->print_address_func (((pc + 4) & ~3) + offset, info); 11534 } 11535 } 11536 skip: 11537 break; 11538 11539 case 'A': 11540 { 11541 unsigned int U = ! NEGATIVE_BIT_SET; 11542 unsigned int W = WRITEBACK_BIT_SET; 11543 unsigned int Rn = (given & 0x000f0000) >> 16; 11544 unsigned int off = (given & 0x000000ff); 11545 11546 func (stream, dis_style_text, "["); 11547 func (stream, dis_style_register, "%s", arm_regnames[Rn]); 11548 11549 if (PRE_BIT_SET) 11550 { 11551 if (off || !U) 11552 { 11553 func (stream, dis_style_text, ", "); 11554 func (stream, dis_style_immediate, "#%c%u", 11555 U ? '+' : '-', off * 4); 11556 value_in_comment = off * 4 * (U ? 1 : -1); 11557 } 11558 func (stream, dis_style_text, "]"); 11559 if (W) 11560 func (stream, dis_style_text, "!"); 11561 } 11562 else 11563 { 11564 func (stream, dis_style_text, "], "); 11565 if (W) 11566 { 11567 func (stream, dis_style_immediate, "#%c%u", 11568 U ? '+' : '-', off * 4); 11569 value_in_comment = off * 4 * (U ? 1 : -1); 11570 } 11571 else 11572 { 11573 func (stream, dis_style_text, "{"); 11574 func (stream, dis_style_immediate, "%u", off); 11575 func (stream, dis_style_text, "}"); 11576 value_in_comment = off; 11577 } 11578 } 11579 } 11580 break; 11581 11582 case 'w': 11583 { 11584 unsigned int Sbit = (given & 0x01000000) >> 24; 11585 unsigned int type = (given & 0x00600000) >> 21; 11586 11587 switch (type) 11588 { 11589 case 0: 11590 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b"); 11591 break; 11592 case 1: 11593 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h"); 11594 break; 11595 case 2: 11596 if (Sbit) 11597 func (stream, dis_style_text, "??"); 11598 break; 11599 case 3: 11600 func (stream, dis_style_text, "??"); 11601 break; 11602 } 11603 } 11604 break; 11605 11606 case 'n': 11607 is_clrm = true; 11608 /* Fall through. */ 11609 case 'm': 11610 { 11611 int started = 0; 11612 int reg; 11613 11614 func (stream, dis_style_text, "{"); 11615 for (reg = 0; reg < 16; reg++) 11616 if ((given & (1 << reg)) != 0) 11617 { 11618 if (started) 11619 func (stream, dis_style_text, ", "); 11620 started = 1; 11621 if (is_clrm && reg == 13) 11622 func (stream, dis_style_text, "(invalid: %s)", 11623 arm_regnames[reg]); 11624 else if (is_clrm && reg == 15) 11625 func (stream, dis_style_register, "%s", "APSR"); 11626 else 11627 func (stream, dis_style_register, "%s", 11628 arm_regnames[reg]); 11629 } 11630 func (stream, dis_style_text, "}"); 11631 } 11632 break; 11633 11634 case 'E': 11635 { 11636 unsigned int msb = (given & 0x0000001f); 11637 unsigned int lsb = 0; 11638 11639 lsb |= (given & 0x000000c0u) >> 6; 11640 lsb |= (given & 0x00007000u) >> 10; 11641 func (stream, dis_style_immediate, "#%u", lsb); 11642 func (stream, dis_style_text, ", "); 11643 func (stream, dis_style_immediate, "#%u", msb - lsb + 1); 11644 } 11645 break; 11646 11647 case 'F': 11648 { 11649 unsigned int width = (given & 0x0000001f) + 1; 11650 unsigned int lsb = 0; 11651 11652 lsb |= (given & 0x000000c0u) >> 6; 11653 lsb |= (given & 0x00007000u) >> 10; 11654 func (stream, dis_style_immediate, "#%u", lsb); 11655 func (stream, dis_style_text, ", "); 11656 func (stream, dis_style_immediate, "#%u", width); 11657 } 11658 break; 11659 11660 case 'G': 11661 { 11662 unsigned int boff = (((given & 0x07800000) >> 23) << 1); 11663 func (stream, dis_style_immediate, "%x", boff); 11664 } 11665 break; 11666 11667 case 'W': 11668 { 11669 unsigned int immA = (given & 0x001f0000u) >> 16; 11670 unsigned int immB = (given & 0x000007feu) >> 1; 11671 unsigned int immC = (given & 0x00000800u) >> 11; 11672 bfd_vma offset = 0; 11673 11674 offset |= immA << 12; 11675 offset |= immB << 2; 11676 offset |= immC << 1; 11677 /* Sign extend. */ 11678 offset = (offset & 0x10000) ? offset - (1 << 17) : offset; 11679 11680 info->print_address_func (pc + 4 + offset, info); 11681 } 11682 break; 11683 11684 case 'Y': 11685 { 11686 unsigned int immA = (given & 0x007f0000u) >> 16; 11687 unsigned int immB = (given & 0x000007feu) >> 1; 11688 unsigned int immC = (given & 0x00000800u) >> 11; 11689 bfd_vma offset = 0; 11690 11691 offset |= immA << 12; 11692 offset |= immB << 2; 11693 offset |= immC << 1; 11694 /* Sign extend. */ 11695 offset = (offset & 0x40000) ? offset - (1 << 19) : offset; 11696 11697 info->print_address_func (pc + 4 + offset, info); 11698 } 11699 break; 11700 11701 case 'Z': 11702 { 11703 unsigned int immA = (given & 0x00010000u) >> 16; 11704 unsigned int immB = (given & 0x000007feu) >> 1; 11705 unsigned int immC = (given & 0x00000800u) >> 11; 11706 bfd_vma offset = 0; 11707 11708 offset |= immA << 12; 11709 offset |= immB << 2; 11710 offset |= immC << 1; 11711 /* Sign extend. */ 11712 offset = (offset & 0x1000) ? offset - (1 << 13) : offset; 11713 11714 info->print_address_func (pc + 4 + offset, info); 11715 11716 unsigned int T = (given & 0x00020000u) >> 17; 11717 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1); 11718 unsigned int boffset = (T == 1) ? 4 : 2; 11719 func (stream, dis_style_text, ", "); 11720 func (stream, dis_style_immediate, "%x", 11721 endoffset + boffset); 11722 } 11723 break; 11724 11725 case 'Q': 11726 { 11727 unsigned int immh = (given & 0x000007feu) >> 1; 11728 unsigned int imml = (given & 0x00000800u) >> 11; 11729 bfd_vma imm32 = 0; 11730 11731 imm32 |= immh << 2; 11732 imm32 |= imml << 1; 11733 11734 info->print_address_func (pc + 4 + imm32, info); 11735 } 11736 break; 11737 11738 case 'P': 11739 { 11740 unsigned int immh = (given & 0x000007feu) >> 1; 11741 unsigned int imml = (given & 0x00000800u) >> 11; 11742 bfd_vma imm32 = 0; 11743 11744 imm32 |= immh << 2; 11745 imm32 |= imml << 1; 11746 11747 info->print_address_func (pc + 4 - imm32, info); 11748 } 11749 break; 11750 11751 case 'b': 11752 { 11753 unsigned int S = (given & 0x04000000u) >> 26; 11754 unsigned int J1 = (given & 0x00002000u) >> 13; 11755 unsigned int J2 = (given & 0x00000800u) >> 11; 11756 bfd_vma offset = 0; 11757 11758 offset |= !S << 20; 11759 offset |= J2 << 19; 11760 offset |= J1 << 18; 11761 offset |= (given & 0x003f0000) >> 4; 11762 offset |= (given & 0x000007ff) << 1; 11763 offset -= (1 << 20); 11764 11765 bfd_vma target = pc + 4 + offset; 11766 info->print_address_func (target, info); 11767 11768 /* Fill in instruction information. */ 11769 info->insn_info_valid = 1; 11770 info->insn_type = dis_branch; 11771 info->target = target; 11772 } 11773 break; 11774 11775 case 'B': 11776 { 11777 unsigned int S = (given & 0x04000000u) >> 26; 11778 unsigned int I1 = (given & 0x00002000u) >> 13; 11779 unsigned int I2 = (given & 0x00000800u) >> 11; 11780 bfd_vma offset = 0; 11781 11782 offset |= !S << 24; 11783 offset |= !(I1 ^ S) << 23; 11784 offset |= !(I2 ^ S) << 22; 11785 offset |= (given & 0x03ff0000u) >> 4; 11786 offset |= (given & 0x000007ffu) << 1; 11787 offset -= (1 << 24); 11788 offset += pc + 4; 11789 11790 /* BLX target addresses are always word aligned. */ 11791 if ((given & 0x00001000u) == 0) 11792 offset &= ~2u; 11793 11794 info->print_address_func (offset, info); 11795 11796 /* Fill in instruction information. */ 11797 info->insn_info_valid = 1; 11798 info->insn_type = dis_branch; 11799 info->target = offset; 11800 } 11801 break; 11802 11803 case 's': 11804 { 11805 unsigned int shift = 0; 11806 11807 shift |= (given & 0x000000c0u) >> 6; 11808 shift |= (given & 0x00007000u) >> 10; 11809 if (WRITEBACK_BIT_SET) 11810 { 11811 func (stream, dis_style_text, ", "); 11812 func (stream, dis_style_sub_mnemonic, "asr "); 11813 func (stream, dis_style_immediate, "#%u", shift); 11814 } 11815 else if (shift) 11816 { 11817 func (stream, dis_style_text, ", "); 11818 func (stream, dis_style_sub_mnemonic, "lsl "); 11819 func (stream, dis_style_immediate, "#%u", shift); 11820 } 11821 /* else print nothing - lsl #0 */ 11822 } 11823 break; 11824 11825 case 'R': 11826 { 11827 unsigned int rot = (given & 0x00000030) >> 4; 11828 11829 if (rot) 11830 { 11831 func (stream, dis_style_text, ", "); 11832 func (stream, dis_style_sub_mnemonic, "ror "); 11833 func (stream, dis_style_immediate, "#%u", rot * 8); 11834 } 11835 } 11836 break; 11837 11838 case 'U': 11839 if ((given & 0xf0) == 0x60) 11840 { 11841 switch (given & 0xf) 11842 { 11843 case 0xf: 11844 func (stream, dis_style_sub_mnemonic, "sy"); 11845 break; 11846 default: 11847 func (stream, dis_style_immediate, "#%d", 11848 (int) given & 0xf); 11849 break; 11850 } 11851 } 11852 else 11853 { 11854 const char * opt = data_barrier_option (given & 0xf); 11855 if (opt != NULL) 11856 func (stream, dis_style_sub_mnemonic, "%s", opt); 11857 else 11858 func (stream, dis_style_immediate, "#%d", 11859 (int) given & 0xf); 11860 } 11861 break; 11862 11863 case 'C': 11864 if ((given & 0xff) == 0) 11865 { 11866 func (stream, dis_style_register, "%cPSR_", 11867 (given & 0x100000) ? 'S' : 'C'); 11868 11869 if (given & 0x800) 11870 func (stream, dis_style_register, "f"); 11871 if (given & 0x400) 11872 func (stream, dis_style_register, "s"); 11873 if (given & 0x200) 11874 func (stream, dis_style_register, "x"); 11875 if (given & 0x100) 11876 func (stream, dis_style_register, "c"); 11877 } 11878 else if ((given & 0x20) == 0x20) 11879 { 11880 char const* name; 11881 unsigned sysm = (given & 0xf00) >> 8; 11882 11883 sysm |= (given & 0x30); 11884 sysm |= (given & 0x00100000) >> 14; 11885 name = banked_regname (sysm); 11886 11887 if (name != NULL) 11888 func (stream, dis_style_register, "%s", name); 11889 else 11890 func (stream, dis_style_text, 11891 "(UNDEF: %lu)", (unsigned long) sysm); 11892 } 11893 else 11894 { 11895 func (stream, dis_style_register, "%s", 11896 psr_name (given & 0xff)); 11897 } 11898 break; 11899 11900 case 'D': 11901 if (((given & 0xff) == 0) 11902 || ((given & 0x20) == 0x20)) 11903 { 11904 char const* name; 11905 unsigned sm = (given & 0xf0000) >> 16; 11906 11907 sm |= (given & 0x30); 11908 sm |= (given & 0x00100000) >> 14; 11909 name = banked_regname (sm); 11910 11911 if (name != NULL) 11912 func (stream, dis_style_register, "%s", name); 11913 else 11914 func (stream, dis_style_text, 11915 "(UNDEF: %lu)", (unsigned long) sm); 11916 } 11917 else 11918 func (stream, dis_style_register, "%s", 11919 psr_name (given & 0xff)); 11920 break; 11921 11922 case '0': case '1': case '2': case '3': case '4': 11923 case '5': case '6': case '7': case '8': case '9': 11924 { 11925 int width; 11926 unsigned long val; 11927 11928 c = arm_decode_bitfield (c, given, &val, &width); 11929 11930 switch (*c) 11931 { 11932 case 's': 11933 if (val <= 3) 11934 func (stream, dis_style_mnemonic, "%s", 11935 mve_vec_sizename[val]); 11936 else 11937 func (stream, dis_style_text, "<undef size>"); 11938 break; 11939 11940 case 'd': 11941 func (stream, base_style, "%lu", val); 11942 value_in_comment = val; 11943 break; 11944 11945 case 'D': 11946 func (stream, dis_style_immediate, "%lu", val + 1); 11947 value_in_comment = val + 1; 11948 break; 11949 11950 case 'W': 11951 func (stream, dis_style_immediate, "%lu", val * 4); 11952 value_in_comment = val * 4; 11953 break; 11954 11955 case 'S': 11956 if (val == 13) 11957 is_unpredictable = true; 11958 /* Fall through. */ 11959 case 'R': 11960 if (val == 15) 11961 is_unpredictable = true; 11962 /* Fall through. */ 11963 case 'r': 11964 func (stream, dis_style_register, "%s", 11965 arm_regnames[val]); 11966 break; 11967 11968 case 'c': 11969 func (stream, base_style, "%s", arm_conditional[val]); 11970 break; 11971 11972 case '\'': 11973 c++; 11974 if (val == ((1ul << width) - 1)) 11975 func (stream, base_style, "%c", *c); 11976 break; 11977 11978 case '`': 11979 c++; 11980 if (val == 0) 11981 func (stream, dis_style_immediate, "%c", *c); 11982 break; 11983 11984 case '?': 11985 func (stream, dis_style_mnemonic, "%c", 11986 c[(1 << width) - (int) val]); 11987 c += 1 << width; 11988 break; 11989 11990 case 'x': 11991 func (stream, dis_style_immediate, "0x%lx", 11992 val & 0xffffffffUL); 11993 break; 11994 11995 default: 11996 abort (); 11997 } 11998 } 11999 break; 12000 12001 case 'L': 12002 /* PR binutils/12534 12003 If we have a PC relative offset in an LDRD or STRD 12004 instructions then display the decoded address. */ 12005 if (((given >> 16) & 0xf) == 0xf) 12006 { 12007 bfd_vma offset = (given & 0xff) * 4; 12008 12009 if ((given & (1 << 23)) == 0) 12010 offset = - offset; 12011 func (stream, dis_style_comment_start, "\t@ "); 12012 info->print_address_func ((pc & ~3) + 4 + offset, info); 12013 } 12014 break; 12015 12016 default: 12017 abort (); 12018 } 12019 } 12020 12021 if (value_in_comment > 32 || value_in_comment < -16) 12022 func (stream, dis_style_comment_start, "\t@ 0x%lx", 12023 value_in_comment); 12024 12025 if (is_unpredictable) 12026 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 12027 12028 return; 12029 } 12030 12031 /* No match. */ 12032 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT, 12033 (unsigned) given); 12034 return; 12035 } 12036 12037 /* Print data bytes on INFO->STREAM. */ 12038 12039 static void 12040 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 12041 struct disassemble_info *info, 12042 long given) 12043 { 12044 fprintf_styled_ftype func = info->fprintf_styled_func; 12045 12046 switch (info->bytes_per_chunk) 12047 { 12048 case 1: 12049 func (info->stream, dis_style_assembler_directive, ".byte"); 12050 func (info->stream, dis_style_text, "\t"); 12051 func (info->stream, dis_style_immediate, "0x%02lx", given); 12052 break; 12053 case 2: 12054 func (info->stream, dis_style_assembler_directive, ".short"); 12055 func (info->stream, dis_style_text, "\t"); 12056 func (info->stream, dis_style_immediate, "0x%04lx", given); 12057 break; 12058 case 4: 12059 func (info->stream, dis_style_assembler_directive, ".word"); 12060 func (info->stream, dis_style_text, "\t"); 12061 func (info->stream, dis_style_immediate, "0x%08lx", given); 12062 break; 12063 default: 12064 abort (); 12065 } 12066 } 12067 12068 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 12069 being displayed in symbol relative addresses. 12070 12071 Also disallow private symbol, with __tagsym$$ prefix, 12072 from ARM RVCT toolchain being displayed. */ 12073 12074 bool 12075 arm_symbol_is_valid (asymbol * sym, 12076 struct disassemble_info * info ATTRIBUTE_UNUSED) 12077 { 12078 const char * name; 12079 12080 if (sym == NULL) 12081 return false; 12082 12083 name = bfd_asymbol_name (sym); 12084 12085 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 12086 } 12087 12088 /* Parse the string of disassembler options. */ 12089 12090 static void 12091 parse_arm_disassembler_options (const char *options) 12092 { 12093 const char *opt; 12094 12095 force_thumb = false; 12096 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 12097 { 12098 if (startswith (opt, "reg-names-")) 12099 { 12100 unsigned int i; 12101 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12102 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 12103 { 12104 regname_selected = i; 12105 break; 12106 } 12107 12108 if (i >= NUM_ARM_OPTIONS) 12109 /* xgettext: c-format */ 12110 opcodes_error_handler (_("unrecognised register name set: %s"), 12111 opt); 12112 } 12113 else if (startswith (opt, "force-thumb")) 12114 force_thumb = 1; 12115 else if (startswith (opt, "no-force-thumb")) 12116 force_thumb = 0; 12117 else if (startswith (opt, "coproc")) 12118 { 12119 const char *procptr = opt + sizeof ("coproc") - 1; 12120 char *endptr; 12121 uint8_t coproc_number = strtol (procptr, &endptr, 10); 12122 if (endptr != procptr + 1 || coproc_number > 7) 12123 { 12124 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"), 12125 opt); 12126 continue; 12127 } 12128 if (*endptr != '=') 12129 { 12130 opcodes_error_handler (_("coproc must have an argument: %s"), 12131 opt); 12132 continue; 12133 } 12134 endptr += 1; 12135 if (startswith (endptr, "generic")) 12136 cde_coprocs &= ~(1 << coproc_number); 12137 else if (startswith (endptr, "cde") 12138 || startswith (endptr, "CDE")) 12139 cde_coprocs |= (1 << coproc_number); 12140 else 12141 { 12142 opcodes_error_handler ( 12143 _("coprocN argument takes options \"generic\"," 12144 " \"cde\", or \"CDE\": %s"), opt); 12145 } 12146 } 12147 else 12148 /* xgettext: c-format */ 12149 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 12150 } 12151 12152 return; 12153 } 12154 12155 static bool 12156 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 12157 enum map_type *map_symbol); 12158 12159 /* Search back through the insn stream to determine if this instruction is 12160 conditionally executed. */ 12161 12162 static void 12163 find_ifthen_state (bfd_vma pc, 12164 struct disassemble_info *info, 12165 bool little) 12166 { 12167 unsigned char b[2]; 12168 unsigned int insn; 12169 int status; 12170 /* COUNT is twice the number of instructions seen. It will be odd if we 12171 just crossed an instruction boundary. */ 12172 int count; 12173 int it_count; 12174 unsigned int seen_it; 12175 bfd_vma addr; 12176 12177 ifthen_address = pc; 12178 ifthen_state = 0; 12179 12180 addr = pc; 12181 count = 1; 12182 it_count = 0; 12183 seen_it = 0; 12184 /* Scan backwards looking for IT instructions, keeping track of where 12185 instruction boundaries are. We don't know if something is actually an 12186 IT instruction until we find a definite instruction boundary. */ 12187 for (;;) 12188 { 12189 if (addr == 0 || info->symbol_at_address_func (addr, info)) 12190 { 12191 /* A symbol must be on an instruction boundary, and will not 12192 be within an IT block. */ 12193 if (seen_it && (count & 1)) 12194 break; 12195 12196 return; 12197 } 12198 addr -= 2; 12199 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 12200 if (status) 12201 return; 12202 12203 if (little) 12204 insn = (b[0]) | (b[1] << 8); 12205 else 12206 insn = (b[1]) | (b[0] << 8); 12207 if (seen_it) 12208 { 12209 if ((insn & 0xf800) < 0xe800) 12210 { 12211 /* Addr + 2 is an instruction boundary. See if this matches 12212 the expected boundary based on the position of the last 12213 IT candidate. */ 12214 if (count & 1) 12215 break; 12216 seen_it = 0; 12217 } 12218 } 12219 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 12220 { 12221 enum map_type type = MAP_ARM; 12222 bool found = mapping_symbol_for_insn (addr, info, &type); 12223 12224 if (!found || (found && type == MAP_THUMB)) 12225 { 12226 /* This could be an IT instruction. */ 12227 seen_it = insn; 12228 it_count = count >> 1; 12229 } 12230 } 12231 if ((insn & 0xf800) >= 0xe800) 12232 count++; 12233 else 12234 count = (count + 2) | 1; 12235 /* IT blocks contain at most 4 instructions. */ 12236 if (count >= 8 && !seen_it) 12237 return; 12238 } 12239 /* We found an IT instruction. */ 12240 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 12241 if ((ifthen_state & 0xf) == 0) 12242 ifthen_state = 0; 12243 } 12244 12245 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 12246 mapping symbol. */ 12247 12248 static int 12249 is_mapping_symbol (struct disassemble_info *info, 12250 int n, 12251 enum map_type *map_type) 12252 { 12253 const char *name = bfd_asymbol_name (info->symtab[n]); 12254 12255 if (name[0] == '$' 12256 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 12257 && (name[2] == 0 || name[2] == '.')) 12258 { 12259 *map_type = ((name[1] == 'a') ? MAP_ARM 12260 : (name[1] == 't') ? MAP_THUMB 12261 : MAP_DATA); 12262 return true; 12263 } 12264 12265 return false; 12266 } 12267 12268 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 12269 Returns nonzero if *MAP_TYPE was set. */ 12270 12271 static int 12272 get_map_sym_type (struct disassemble_info *info, 12273 int n, 12274 enum map_type *map_type) 12275 { 12276 /* If the symbol is in a different section, ignore it. */ 12277 if (info->section != NULL && info->section != info->symtab[n]->section) 12278 return false; 12279 12280 return is_mapping_symbol (info, n, map_type); 12281 } 12282 12283 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 12284 Returns nonzero if *MAP_TYPE was set. */ 12285 12286 static int 12287 get_sym_code_type (struct disassemble_info *info, 12288 int n, 12289 enum map_type *map_type) 12290 { 12291 elf_symbol_type *es; 12292 unsigned int type; 12293 asymbol * sym; 12294 12295 /* If the symbol is in a different section, ignore it. */ 12296 if (info->section != NULL && info->section != info->symtab[n]->section) 12297 return false; 12298 12299 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */ 12300 sym = info->symtab[n]; 12301 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour) 12302 return false; 12303 12304 es = (elf_symbol_type *) sym; 12305 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12306 12307 /* If the symbol has function type then use that. */ 12308 if (type == STT_FUNC || type == STT_GNU_IFUNC) 12309 { 12310 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12311 == ST_BRANCH_TO_THUMB) 12312 *map_type = MAP_THUMB; 12313 else 12314 *map_type = MAP_ARM; 12315 return true; 12316 } 12317 12318 return false; 12319 } 12320 12321 /* Search the mapping symbol state for instruction at pc. This is only 12322 applicable for elf target. 12323 12324 There is an assumption Here, info->private_data contains the correct AND 12325 up-to-date information about current scan process. The information will be 12326 used to speed this search process. 12327 12328 Return TRUE if the mapping state can be determined, and map_symbol 12329 will be updated accordingly. Otherwise, return FALSE. */ 12330 12331 static bool 12332 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 12333 enum map_type *map_symbol) 12334 { 12335 bfd_vma addr, section_vma = 0; 12336 int n, last_sym = -1; 12337 bool found = false; 12338 bool can_use_search_opt_p = false; 12339 12340 /* Sanity check. */ 12341 if (info == NULL) 12342 return false; 12343 12344 /* Default to DATA. A text section is required by the ABI to contain an 12345 INSN mapping symbol at the start. A data section has no such 12346 requirement, hence if no mapping symbol is found the section must 12347 contain only data. This however isn't very useful if the user has 12348 fully stripped the binaries. If this is the case use the section 12349 attributes to determine the default. If we have no section default to 12350 INSN as well, as we may be disassembling some raw bytes on a baremetal 12351 HEX file or similar. */ 12352 enum map_type type = MAP_DATA; 12353 if ((info->section && info->section->flags & SEC_CODE) || !info->section) 12354 type = MAP_ARM; 12355 struct arm_private_data *private_data; 12356 12357 if (info->private_data == NULL || info->symtab == NULL 12358 || info->symtab_size == 0 12359 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 12360 return false; 12361 12362 private_data = info->private_data; 12363 12364 /* First, look for mapping symbols. */ 12365 if (pc <= private_data->last_mapping_addr) 12366 private_data->last_mapping_sym = -1; 12367 12368 /* Start scanning at the start of the function, or wherever 12369 we finished last time. */ 12370 n = info->symtab_pos + 1; 12371 12372 /* If the last stop offset is different from the current one it means we 12373 are disassembling a different glob of bytes. As such the optimization 12374 would not be safe and we should start over. */ 12375 can_use_search_opt_p 12376 = (private_data->last_mapping_sym >= 0 12377 && info->stop_offset == private_data->last_stop_offset); 12378 12379 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 12380 n = private_data->last_mapping_sym; 12381 12382 /* Look down while we haven't passed the location being disassembled. 12383 The reason for this is that there's no defined order between a symbol 12384 and an mapping symbol that may be at the same address. We may have to 12385 look at least one position ahead. */ 12386 for (; n < info->symtab_size; n++) 12387 { 12388 addr = bfd_asymbol_value (info->symtab[n]); 12389 if (addr > pc) 12390 break; 12391 if (get_map_sym_type (info, n, &type)) 12392 { 12393 last_sym = n; 12394 found = true; 12395 } 12396 } 12397 12398 if (!found) 12399 { 12400 n = info->symtab_pos; 12401 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 12402 n = private_data->last_mapping_sym; 12403 12404 /* No mapping symbol found at this address. Look backwards 12405 for a preceeding one, but don't go pass the section start 12406 otherwise a data section with no mapping symbol can pick up 12407 a text mapping symbol of a preceeding section. The documentation 12408 says section can be NULL, in which case we will seek up all the 12409 way to the top. */ 12410 if (info->section) 12411 section_vma = info->section->vma; 12412 12413 for (; n >= 0; n--) 12414 { 12415 addr = bfd_asymbol_value (info->symtab[n]); 12416 if (addr < section_vma) 12417 break; 12418 12419 if (get_map_sym_type (info, n, &type)) 12420 { 12421 last_sym = n; 12422 found = true; 12423 break; 12424 } 12425 } 12426 } 12427 12428 /* If no mapping symbol was found, try looking up without a mapping 12429 symbol. This is done by walking up from the current PC to the nearest 12430 symbol. We don't actually have to loop here since symtab_pos will 12431 contain the nearest symbol already. */ 12432 if (!found) 12433 { 12434 n = info->symtab_pos; 12435 if (n >= 0 && get_sym_code_type (info, n, &type)) 12436 { 12437 last_sym = n; 12438 found = true; 12439 } 12440 } 12441 12442 private_data->last_mapping_sym = last_sym; 12443 private_data->last_type = type; 12444 private_data->last_stop_offset = info->stop_offset; 12445 12446 *map_symbol = type; 12447 return found; 12448 } 12449 12450 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 12451 of the supplied arm_feature_set structure with bitmasks indicating 12452 the supported base architectures and coprocessor extensions. 12453 12454 FIXME: This could more efficiently implemented as a constant array, 12455 although it would also be less robust. */ 12456 12457 static void 12458 select_arm_features (unsigned long mach, 12459 arm_feature_set * features) 12460 { 12461 arm_feature_set arch_fset; 12462 const arm_feature_set fpu_any = FPU_ANY; 12463 12464 #undef ARM_SET_FEATURES 12465 #define ARM_SET_FEATURES(FSET) \ 12466 { \ 12467 const arm_feature_set fset = FSET; \ 12468 arch_fset = fset; \ 12469 } 12470 12471 /* When several architecture versions share the same bfd_mach_arm_XXX value 12472 the most featureful is chosen. */ 12473 switch (mach) 12474 { 12475 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 12476 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 12477 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 12478 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 12479 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 12480 case bfd_mach_arm_ep9312: 12481 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 12482 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 12483 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 12484 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 12485 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 12486 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 12487 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 12488 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 12489 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 12490 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 12491 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 12492 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 12493 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 12494 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 12495 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 12496 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 12497 case bfd_mach_arm_8: 12498 { 12499 /* Add bits for extensions that Armv8.6-A recognizes. */ 12500 arm_feature_set armv8_6_ext_fset 12501 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 12502 ARM_SET_FEATURES (ARM_ARCH_V8_6A); 12503 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); 12504 break; 12505 } 12506 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; 12507 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 12508 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 12509 case bfd_mach_arm_8_1M_MAIN: 12510 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); 12511 arm_feature_set mve_all 12512 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP); 12513 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all); 12514 force_thumb = 1; 12515 break; 12516 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break; 12517 /* If the machine type is unknown allow all architecture types and all 12518 extensions, with the exception of MVE as that clashes with NEON. */ 12519 case bfd_mach_arm_unknown: 12520 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN); 12521 break; 12522 default: 12523 abort (); 12524 } 12525 #undef ARM_SET_FEATURES 12526 12527 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 12528 and thus on bfd_mach_arm_XXX value. Therefore for a given 12529 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 12530 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 12531 } 12532 12533 12534 /* NOTE: There are no checks in these routines that 12535 the relevant number of data bytes exist. */ 12536 12537 static int 12538 print_insn (bfd_vma pc, struct disassemble_info *info, bool little) 12539 { 12540 unsigned char b[4]; 12541 unsigned long given; 12542 int status; 12543 int is_thumb = false; 12544 int is_data = false; 12545 int little_code; 12546 unsigned int size = 4; 12547 void (*printer) (bfd_vma, struct disassemble_info *, long); 12548 bool found = false; 12549 struct arm_private_data *private_data; 12550 12551 /* Clear instruction information field. */ 12552 info->insn_info_valid = 0; 12553 info->branch_delay_insns = 0; 12554 info->data_size = 0; 12555 info->insn_type = dis_noninsn; 12556 info->target = 0; 12557 info->target2 = 0; 12558 12559 if (info->disassembler_options) 12560 { 12561 parse_arm_disassembler_options (info->disassembler_options); 12562 12563 /* To avoid repeated parsing of these options, we remove them here. */ 12564 info->disassembler_options = NULL; 12565 } 12566 12567 /* PR 10288: Control which instructions will be disassembled. */ 12568 if (info->private_data == NULL) 12569 { 12570 static struct arm_private_data private; 12571 12572 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 12573 /* If the user did not use the -m command line switch then default to 12574 disassembling all types of ARM instruction. 12575 12576 The info->mach value has to be ignored as this will be based on 12577 the default archictecture for the target and/or hints in the notes 12578 section, but it will never be greater than the current largest arm 12579 machine value (iWMMXt2), which is only equivalent to the V5TE 12580 architecture. ARM architectures have advanced beyond the machine 12581 value encoding, and these newer architectures would be ignored if 12582 the machine value was used. 12583 12584 Ie the -m switch is used to restrict which instructions will be 12585 disassembled. If it is necessary to use the -m switch to tell 12586 objdump that an ARM binary is being disassembled, eg because the 12587 input is a raw binary file, but it is also desired to disassemble 12588 all ARM instructions then use "-marm". This will select the 12589 "unknown" arm architecture which is compatible with any ARM 12590 instruction. */ 12591 info->mach = bfd_mach_arm_unknown; 12592 12593 /* Compute the architecture bitmask from the machine number. 12594 Note: This assumes that the machine number will not change 12595 during disassembly.... */ 12596 select_arm_features (info->mach, & private.features); 12597 12598 private.last_mapping_sym = -1; 12599 private.last_mapping_addr = 0; 12600 private.last_stop_offset = 0; 12601 12602 info->private_data = & private; 12603 } 12604 12605 private_data = info->private_data; 12606 12607 /* Decide if our code is going to be little-endian, despite what the 12608 function argument might say. */ 12609 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 12610 12611 /* For ELF, consult the symbol table to determine what kind of code 12612 or data we have. */ 12613 if (info->symtab_size != 0 12614 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 12615 { 12616 bfd_vma addr; 12617 int n; 12618 int last_sym = -1; 12619 enum map_type type = MAP_ARM; 12620 12621 found = mapping_symbol_for_insn (pc, info, &type); 12622 last_sym = private_data->last_mapping_sym; 12623 12624 is_thumb = (private_data->last_type == MAP_THUMB); 12625 is_data = (private_data->last_type == MAP_DATA); 12626 12627 /* Look a little bit ahead to see if we should print out 12628 two or four bytes of data. If there's a symbol, 12629 mapping or otherwise, after two bytes then don't 12630 print more. */ 12631 if (is_data) 12632 { 12633 size = 4 - (pc & 3); 12634 for (n = last_sym + 1; n < info->symtab_size; n++) 12635 { 12636 addr = bfd_asymbol_value (info->symtab[n]); 12637 if (addr > pc 12638 && (info->section == NULL 12639 || info->section == info->symtab[n]->section)) 12640 { 12641 if (addr - pc < size) 12642 size = addr - pc; 12643 break; 12644 } 12645 } 12646 /* If the next symbol is after three bytes, we need to 12647 print only part of the data, so that we can use either 12648 .byte or .short. */ 12649 if (size == 3) 12650 size = (pc & 1) ? 1 : 2; 12651 } 12652 } 12653 12654 if (info->symbols != NULL) 12655 { 12656 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 12657 { 12658 coff_symbol_type * cs; 12659 12660 cs = coffsymbol (*info->symbols); 12661 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 12662 || cs->native->u.syment.n_sclass == C_THUMBSTAT 12663 || cs->native->u.syment.n_sclass == C_THUMBLABEL 12664 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 12665 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 12666 } 12667 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 12668 && !found) 12669 { 12670 /* If no mapping symbol has been found then fall back to the type 12671 of the function symbol. */ 12672 elf_symbol_type * es; 12673 unsigned int type; 12674 12675 es = *(elf_symbol_type **)(info->symbols); 12676 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12677 12678 is_thumb = 12679 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12680 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 12681 } 12682 else if (bfd_asymbol_flavour (*info->symbols) 12683 == bfd_target_mach_o_flavour) 12684 { 12685 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 12686 12687 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 12688 } 12689 } 12690 12691 if (force_thumb) 12692 is_thumb = true; 12693 12694 if (is_data) 12695 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12696 else 12697 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12698 12699 info->bytes_per_line = 4; 12700 12701 /* PR 10263: Disassemble data if requested to do so by the user. */ 12702 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 12703 { 12704 int i; 12705 12706 /* Size was already set above. */ 12707 info->bytes_per_chunk = size; 12708 printer = print_insn_data; 12709 12710 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 12711 given = 0; 12712 if (little) 12713 for (i = size - 1; i >= 0; i--) 12714 given = b[i] | (given << 8); 12715 else 12716 for (i = 0; i < (int) size; i++) 12717 given = b[i] | (given << 8); 12718 } 12719 else if (!is_thumb) 12720 { 12721 /* In ARM mode endianness is a straightforward issue: the instruction 12722 is four bytes long and is either ordered 0123 or 3210. */ 12723 printer = print_insn_arm; 12724 info->bytes_per_chunk = 4; 12725 size = 4; 12726 12727 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 12728 if (little_code) 12729 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24); 12730 else 12731 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24); 12732 } 12733 else 12734 { 12735 /* In Thumb mode we have the additional wrinkle of two 12736 instruction lengths. Fortunately, the bits that determine 12737 the length of the current instruction are always to be found 12738 in the first two bytes. */ 12739 printer = print_insn_thumb16; 12740 info->bytes_per_chunk = 2; 12741 size = 2; 12742 12743 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 12744 if (little_code) 12745 given = (b[0]) | (b[1] << 8); 12746 else 12747 given = (b[1]) | (b[0] << 8); 12748 12749 if (!status) 12750 { 12751 /* These bit patterns signal a four-byte Thumb 12752 instruction. */ 12753 if ((given & 0xF800) == 0xF800 12754 || (given & 0xF800) == 0xF000 12755 || (given & 0xF800) == 0xE800) 12756 { 12757 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 12758 if (little_code) 12759 given = (b[0]) | (b[1] << 8) | (given << 16); 12760 else 12761 given = (b[1]) | (b[0] << 8) | (given << 16); 12762 12763 printer = print_insn_thumb32; 12764 size = 4; 12765 } 12766 } 12767 12768 if (ifthen_address != pc) 12769 find_ifthen_state (pc, info, little_code); 12770 12771 if (ifthen_state) 12772 { 12773 if ((ifthen_state & 0xf) == 0x8) 12774 ifthen_next_state = 0; 12775 else 12776 ifthen_next_state = (ifthen_state & 0xe0) 12777 | ((ifthen_state & 0xf) << 1); 12778 } 12779 } 12780 12781 if (status) 12782 { 12783 info->memory_error_func (status, pc, info); 12784 return -1; 12785 } 12786 if (info->flags & INSN_HAS_RELOC) 12787 /* If the instruction has a reloc associated with it, then 12788 the offset field in the instruction will actually be the 12789 addend for the reloc. (We are using REL type relocs). 12790 In such cases, we can ignore the pc when computing 12791 addresses, since the addend is not currently pc-relative. */ 12792 pc = 0; 12793 12794 printer (pc, info, given); 12795 12796 if (is_thumb) 12797 { 12798 ifthen_state = ifthen_next_state; 12799 ifthen_address += size; 12800 } 12801 return size; 12802 } 12803 12804 int 12805 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 12806 { 12807 /* Detect BE8-ness and record it in the disassembler info. */ 12808 if (info->flavour == bfd_target_elf_flavour 12809 && info->section != NULL 12810 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 12811 info->endian_code = BFD_ENDIAN_LITTLE; 12812 12813 return print_insn (pc, info, false); 12814 } 12815 12816 int 12817 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 12818 { 12819 return print_insn (pc, info, true); 12820 } 12821 12822 const disasm_options_and_args_t * 12823 disassembler_options_arm (void) 12824 { 12825 static disasm_options_and_args_t *opts_and_args; 12826 12827 if (opts_and_args == NULL) 12828 { 12829 disasm_options_t *opts; 12830 unsigned int i; 12831 12832 opts_and_args = XNEW (disasm_options_and_args_t); 12833 opts_and_args->args = NULL; 12834 12835 opts = &opts_and_args->options; 12836 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12837 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12838 opts->arg = NULL; 12839 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12840 { 12841 opts->name[i] = regnames[i].name; 12842 if (regnames[i].description != NULL) 12843 opts->description[i] = _(regnames[i].description); 12844 else 12845 opts->description[i] = NULL; 12846 } 12847 /* The array we return must be NULL terminated. */ 12848 opts->name[i] = NULL; 12849 opts->description[i] = NULL; 12850 } 12851 12852 return opts_and_args; 12853 } 12854 12855 void 12856 print_arm_disassembler_options (FILE *stream) 12857 { 12858 unsigned int i, max_len = 0; 12859 fprintf (stream, _("\n\ 12860 The following ARM specific disassembler options are supported for use with\n\ 12861 the -M switch:\n")); 12862 12863 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12864 { 12865 unsigned int len = strlen (regnames[i].name); 12866 if (max_len < len) 12867 max_len = len; 12868 } 12869 12870 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 12871 fprintf (stream, " %s%*c %s\n", 12872 regnames[i].name, 12873 (int)(max_len - strlen (regnames[i].name)), ' ', 12874 _(regnames[i].description)); 12875 } 12876
Indexes created Tue May 05 00:25:04 UTC 2026