arm-dis.c revision 1.1.1.9
1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2020 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <assert.h> 25 26 #include "disassemble.h" 27 #include "opcode/arm.h" 28 #include "opintl.h" 29 #include "safe-ctype.h" 30 #include "libiberty.h" 31 #include "floatformat.h" 32 33 /* FIXME: This shouldn't be done here. */ 34 #include "coff/internal.h" 35 #include "libcoff.h" 36 #include "bfd.h" 37 #include "elf-bfd.h" 38 #include "elf/internal.h" 39 #include "elf/arm.h" 40 #include "mach-o.h" 41 42 /* FIXME: Belongs in global header. */ 43 #ifndef strneq 44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 45 #endif 46 47 /* Cached mapping symbol state. */ 48 enum map_type 49 { 50 MAP_ARM, 51 MAP_THUMB, 52 MAP_DATA 53 }; 54 55 struct arm_private_data 56 { 57 /* The features to use when disassembling optional instructions. */ 58 arm_feature_set features; 59 60 /* Track the last type (although this doesn't seem to be useful) */ 61 enum map_type last_type; 62 63 /* Tracking symbol table information */ 64 int last_mapping_sym; 65 66 /* The end range of the current range being disassembled. */ 67 bfd_vma last_stop_offset; 68 bfd_vma last_mapping_addr; 69 }; 70 71 enum mve_instructions 72 { 73 MVE_VPST, 74 MVE_VPT_FP_T1, 75 MVE_VPT_FP_T2, 76 MVE_VPT_VEC_T1, 77 MVE_VPT_VEC_T2, 78 MVE_VPT_VEC_T3, 79 MVE_VPT_VEC_T4, 80 MVE_VPT_VEC_T5, 81 MVE_VPT_VEC_T6, 82 MVE_VCMP_FP_T1, 83 MVE_VCMP_FP_T2, 84 MVE_VCMP_VEC_T1, 85 MVE_VCMP_VEC_T2, 86 MVE_VCMP_VEC_T3, 87 MVE_VCMP_VEC_T4, 88 MVE_VCMP_VEC_T5, 89 MVE_VCMP_VEC_T6, 90 MVE_VDUP, 91 MVE_VEOR, 92 MVE_VFMAS_FP_SCALAR, 93 MVE_VFMA_FP_SCALAR, 94 MVE_VFMA_FP, 95 MVE_VFMS_FP, 96 MVE_VHADD_T1, 97 MVE_VHADD_T2, 98 MVE_VHSUB_T1, 99 MVE_VHSUB_T2, 100 MVE_VRHADD, 101 MVE_VLD2, 102 MVE_VLD4, 103 MVE_VST2, 104 MVE_VST4, 105 MVE_VLDRB_T1, 106 MVE_VLDRH_T2, 107 MVE_VLDRB_T5, 108 MVE_VLDRH_T6, 109 MVE_VLDRW_T7, 110 MVE_VSTRB_T1, 111 MVE_VSTRH_T2, 112 MVE_VSTRB_T5, 113 MVE_VSTRH_T6, 114 MVE_VSTRW_T7, 115 MVE_VLDRB_GATHER_T1, 116 MVE_VLDRH_GATHER_T2, 117 MVE_VLDRW_GATHER_T3, 118 MVE_VLDRD_GATHER_T4, 119 MVE_VLDRW_GATHER_T5, 120 MVE_VLDRD_GATHER_T6, 121 MVE_VSTRB_SCATTER_T1, 122 MVE_VSTRH_SCATTER_T2, 123 MVE_VSTRW_SCATTER_T3, 124 MVE_VSTRD_SCATTER_T4, 125 MVE_VSTRW_SCATTER_T5, 126 MVE_VSTRD_SCATTER_T6, 127 MVE_VCVT_FP_FIX_VEC, 128 MVE_VCVT_BETWEEN_FP_INT, 129 MVE_VCVT_FP_HALF_FP, 130 MVE_VCVT_FROM_FP_TO_INT, 131 MVE_VRINT_FP, 132 MVE_VMOV_HFP_TO_GP, 133 MVE_VMOV_GP_TO_VEC_LANE, 134 MVE_VMOV_IMM_TO_VEC, 135 MVE_VMOV_VEC_TO_VEC, 136 MVE_VMOV2_VEC_LANE_TO_GP, 137 MVE_VMOV2_GP_TO_VEC_LANE, 138 MVE_VMOV_VEC_LANE_TO_GP, 139 MVE_VMVN_IMM, 140 MVE_VMVN_REG, 141 MVE_VORR_IMM, 142 MVE_VORR_REG, 143 MVE_VORN, 144 MVE_VBIC_IMM, 145 MVE_VBIC_REG, 146 MVE_VMOVX, 147 MVE_VMOVL, 148 MVE_VMOVN, 149 MVE_VMULL_INT, 150 MVE_VMULL_POLY, 151 MVE_VQDMULL_T1, 152 MVE_VQDMULL_T2, 153 MVE_VQMOVN, 154 MVE_VQMOVUN, 155 MVE_VADDV, 156 MVE_VMLADAV_T1, 157 MVE_VMLADAV_T2, 158 MVE_VMLALDAV, 159 MVE_VMLAS, 160 MVE_VADDLV, 161 MVE_VMLSDAV_T1, 162 MVE_VMLSDAV_T2, 163 MVE_VMLSLDAV, 164 MVE_VRMLALDAVH, 165 MVE_VRMLSLDAVH, 166 MVE_VQDMLADH, 167 MVE_VQRDMLADH, 168 MVE_VQDMLAH, 169 MVE_VQRDMLAH, 170 MVE_VQDMLASH, 171 MVE_VQRDMLASH, 172 MVE_VQDMLSDH, 173 MVE_VQRDMLSDH, 174 MVE_VQDMULH_T1, 175 MVE_VQRDMULH_T2, 176 MVE_VQDMULH_T3, 177 MVE_VQRDMULH_T4, 178 MVE_VDDUP, 179 MVE_VDWDUP, 180 MVE_VIWDUP, 181 MVE_VIDUP, 182 MVE_VCADD_FP, 183 MVE_VCADD_VEC, 184 MVE_VHCADD, 185 MVE_VCMLA_FP, 186 MVE_VCMUL_FP, 187 MVE_VQRSHL_T1, 188 MVE_VQRSHL_T2, 189 MVE_VQRSHRN, 190 MVE_VQRSHRUN, 191 MVE_VQSHL_T1, 192 MVE_VQSHL_T2, 193 MVE_VQSHLU_T3, 194 MVE_VQSHL_T4, 195 MVE_VQSHRN, 196 MVE_VQSHRUN, 197 MVE_VRSHL_T1, 198 MVE_VRSHL_T2, 199 MVE_VRSHR, 200 MVE_VRSHRN, 201 MVE_VSHL_T1, 202 MVE_VSHL_T2, 203 MVE_VSHL_T3, 204 MVE_VSHLC, 205 MVE_VSHLL_T1, 206 MVE_VSHLL_T2, 207 MVE_VSHR, 208 MVE_VSHRN, 209 MVE_VSLI, 210 MVE_VSRI, 211 MVE_VADC, 212 MVE_VABAV, 213 MVE_VABD_FP, 214 MVE_VABD_VEC, 215 MVE_VABS_FP, 216 MVE_VABS_VEC, 217 MVE_VADD_FP_T1, 218 MVE_VADD_FP_T2, 219 MVE_VADD_VEC_T1, 220 MVE_VADD_VEC_T2, 221 MVE_VSBC, 222 MVE_VSUB_FP_T1, 223 MVE_VSUB_FP_T2, 224 MVE_VSUB_VEC_T1, 225 MVE_VSUB_VEC_T2, 226 MVE_VAND, 227 MVE_VBRSR, 228 MVE_VCLS, 229 MVE_VCLZ, 230 MVE_VCTP, 231 MVE_VMAX, 232 MVE_VMAXA, 233 MVE_VMAXNM_FP, 234 MVE_VMAXNMA_FP, 235 MVE_VMAXNMV_FP, 236 MVE_VMAXNMAV_FP, 237 MVE_VMAXV, 238 MVE_VMAXAV, 239 MVE_VMIN, 240 MVE_VMINA, 241 MVE_VMINNM_FP, 242 MVE_VMINNMA_FP, 243 MVE_VMINNMV_FP, 244 MVE_VMINNMAV_FP, 245 MVE_VMINV, 246 MVE_VMINAV, 247 MVE_VMLA, 248 MVE_VMUL_FP_T1, 249 MVE_VMUL_FP_T2, 250 MVE_VMUL_VEC_T1, 251 MVE_VMUL_VEC_T2, 252 MVE_VMULH, 253 MVE_VRMULH, 254 MVE_VNEG_FP, 255 MVE_VNEG_VEC, 256 MVE_VPNOT, 257 MVE_VPSEL, 258 MVE_VQABS, 259 MVE_VQADD_T1, 260 MVE_VQADD_T2, 261 MVE_VQSUB_T1, 262 MVE_VQSUB_T2, 263 MVE_VQNEG, 264 MVE_VREV16, 265 MVE_VREV32, 266 MVE_VREV64, 267 MVE_LSLL, 268 MVE_LSLLI, 269 MVE_LSRL, 270 MVE_ASRL, 271 MVE_ASRLI, 272 MVE_SQRSHRL, 273 MVE_SQRSHR, 274 MVE_UQRSHL, 275 MVE_UQRSHLL, 276 MVE_UQSHL, 277 MVE_UQSHLL, 278 MVE_URSHRL, 279 MVE_URSHR, 280 MVE_SRSHRL, 281 MVE_SRSHR, 282 MVE_SQSHLL, 283 MVE_SQSHL, 284 MVE_CINC, 285 MVE_CINV, 286 MVE_CNEG, 287 MVE_CSINC, 288 MVE_CSINV, 289 MVE_CSET, 290 MVE_CSETM, 291 MVE_CSNEG, 292 MVE_CSEL, 293 MVE_NONE 294 }; 295 296 enum mve_unpredictable 297 { 298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. 299 */ 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and 301 fcB = 1 (vpt). */ 302 UNPRED_R13, /* Unpredictable because r13 (sp) or 303 r15 (sp) used. */ 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ 305 UNPRED_Q_GT_4, /* Unpredictable because 306 vec reg start > 4 (vld4/st4). */ 307 UNPRED_Q_GT_6, /* Unpredictable because 308 vec reg start > 6 (vld2/st2). */ 309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 310 and WB bit = 1. */ 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are 312 equal. */ 313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */ 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the 315 same. */ 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and 317 size = 1. */ 318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and 319 size = 2. */ 320 UNPRED_NONE /* No unpredictable behavior. */ 321 }; 322 323 enum mve_undefined 324 { 325 UNDEF_SIZE, /* undefined size. */ 326 UNDEF_SIZE_0, /* undefined because size == 0. */ 327 UNDEF_SIZE_2, /* undefined because size == 2. */ 328 UNDEF_SIZE_3, /* undefined because size == 3. */ 329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ 332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ 333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and 334 size == 0. */ 335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and 336 size == 1. */ 337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */ 339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and 341 op1 == (0 or 1). */ 342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and 343 op2 == 0 and op1 == (0 or 1). */ 344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode 345 in {0xx1, x0x1}. */ 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ 347 UNDEF_NONE /* no undefined behavior. */ 348 }; 349 350 struct opcode32 351 { 352 arm_feature_set arch; /* Architecture defining this insn. */ 353 unsigned long value; /* If arch is 0 then value is a sentinel. */ 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 355 const char * assembler; /* How to disassemble this insn. */ 356 }; 357 358 struct cdeopcode32 359 { 360 arm_feature_set arch; /* Architecture defining this insn. */ 361 uint8_t coproc_shift; /* coproc is this far into op. */ 362 uint16_t coproc_mask; /* Length of coproc field in op. */ 363 unsigned long value; /* If arch is 0 then value is a sentinel. */ 364 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 365 const char * assembler; /* How to disassemble this insn. */ 366 }; 367 368 /* MVE opcodes. */ 369 370 struct mopcode32 371 { 372 arm_feature_set arch; /* Architecture defining this insn. */ 373 enum mve_instructions mve_op; /* Specific mve instruction for faster 374 decoding. */ 375 unsigned long value; /* If arch is 0 then value is a sentinel. */ 376 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 377 const char * assembler; /* How to disassemble this insn. */ 378 }; 379 380 enum isa { 381 ANY, 382 T32, 383 ARM 384 }; 385 386 387 /* Shared (between Arm and Thumb mode) opcode. */ 388 struct sopcode32 389 { 390 enum isa isa; /* Execution mode instruction availability. */ 391 arm_feature_set arch; /* Architecture defining this insn. */ 392 unsigned long value; /* If arch is 0 then value is a sentinel. */ 393 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 394 const char * assembler; /* How to disassemble this insn. */ 395 }; 396 397 struct opcode16 398 { 399 arm_feature_set arch; /* Architecture defining this insn. */ 400 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 401 const char *assembler; /* How to disassemble this insn. */ 402 }; 403 404 /* print_insn_coprocessor recognizes the following format control codes: 405 406 %% % 407 408 %c print condition code (always bits 28-31 in ARM mode) 409 %b print condition code allowing cp_num == 9 410 %q print shifter argument 411 %u print condition code (unconditional in ARM mode, 412 UNPREDICTABLE if not AL in Thumb) 413 %A print address for ldc/stc/ldf/stf instruction 414 %B print vstm/vldm register list 415 %C print vscclrm register list 416 %I print cirrus signed shift immediate: bits 0..3|4..6 417 %J print register for VLDR instruction 418 %K print address for VLDR instruction 419 %F print the COUNT field of a LFM/SFM instruction. 420 %P print floating point precision in arithmetic insn 421 %Q print floating point precision in ldf/stf insn 422 %R print floating point rounding mode 423 424 %<bitfield>c print as a condition code (for vsel) 425 %<bitfield>r print as an ARM register 426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 427 %<bitfield>ru as %<>r but each u register must be unique. 428 %<bitfield>d print the bitfield in decimal 429 %<bitfield>k print immediate for VFPv3 conversion instruction 430 %<bitfield>x print the bitfield in hex 431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 432 %<bitfield>f print a floating point constant if >7 else a 433 floating point register 434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 435 %<bitfield>g print as an iWMMXt 64-bit register 436 %<bitfield>G print as an iWMMXt general purpose or control register 437 %<bitfield>D print as a NEON D register 438 %<bitfield>Q print as a NEON Q register 439 %<bitfield>V print as a NEON D or Q register 440 %<bitfield>E print a quarter-float immediate value 441 442 %y<code> print a single precision VFP reg. 443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 444 %z<code> print a double precision VFP reg 445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 446 447 %<bitfield>'c print specified char iff bitfield is all ones 448 %<bitfield>`c print specified char iff bitfield is all zeroes 449 %<bitfield>?ab... select from array of values in big endian order 450 451 %L print as an iWMMXt N/M width field. 452 %Z print the Immediate of a WSHUFH instruction. 453 %l like 'A' except use byte offsets for 'B' & 'H' 454 versions. 455 %i print 5-bit immediate in bits 8,3..0 456 (print "32" when 0) 457 %r print register offset address for wldt/wstr instruction. */ 458 459 enum opcode_sentinel_enum 460 { 461 SENTINEL_IWMMXT_START = 1, 462 SENTINEL_IWMMXT_END, 463 SENTINEL_GENERIC_START 464 } opcode_sentinels; 465 466 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 467 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x" 468 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x" 469 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 470 471 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 472 473 /* print_insn_cde recognizes the following format control codes: 474 475 %% % 476 477 %a print 'a' iff bit 28 is 1 478 %p print bits 8-10 as coprocessor 479 %<bitfield>d print as decimal 480 %<bitfield>r print as an ARM register 481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv 482 %<bitfield>T print as an ARM register + 1 483 %<bitfield>R as %r but r13 is UNPREDICTABLE 484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE 485 %j print immediate taken from bits (16..21,7,0..5) 486 %k print immediate taken from bits (20..21,7,0..5). 487 %l print immediate taken from bits (20..22,7,4..5). */ 488 489 /* At the moment there is only one valid position for the coprocessor number, 490 and hence that's encoded in the macro below. */ 491 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ 492 { ARCH, 8, 7, VALUE, MASK, ASM } 493 static const struct cdeopcode32 cde_opcodes[] = 494 { 495 /* Custom Datapath Extension instructions. */ 496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 497 0xee000000, 0xefc00840, 498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"), 499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 500 0xee000040, 0xefc00840, 501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"), 502 503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 504 0xee400000, 0xefc00840, 505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"), 506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 507 0xee400040, 0xefc00840, 508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"), 509 510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 511 0xee800000, 0xef800840, 512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"), 513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 514 0xee800040, 0xef800840, 515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"), 516 517 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 518 0xec200000, 0xeeb00840, 519 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"), 520 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 521 0xec200040, 0xeeb00840, 522 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"), 523 524 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 525 0xec300000, 0xeeb00840, 526 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"), 527 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 528 0xec300040, 0xeeb00840, 529 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"), 530 531 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 532 0xec800000, 0xee800840, 533 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"), 534 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 535 0xec800040, 0xee800840, 536 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"), 537 538 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) 539 540 }; 541 542 static const struct sopcode32 coprocessor_opcodes[] = 543 { 544 /* XScale instructions. */ 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 546 0x0e200010, 0x0fff0ff0, 547 "mia%c\tacc0, %0-3r, %12-15r"}, 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 549 0x0e280010, 0x0fff0ff0, 550 "miaph%c\tacc0, %0-3r, %12-15r"}, 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 552 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 554 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 556 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 557 558 /* Intel Wireless MMX technology instructions. */ 559 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 561 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 563 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 565 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 567 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 569 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 571 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 573 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 575 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 577 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 579 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 581 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 583 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 585 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 587 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 589 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 591 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 593 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 595 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 597 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 599 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 601 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 603 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 605 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 607 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 609 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 611 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 613 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 615 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 617 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 619 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 621 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 623 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 625 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 627 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 629 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 631 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 633 0x0e800120, 0x0f800ff0, 634 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 636 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 637 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 638 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 639 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 640 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 641 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 642 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 643 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 644 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 646 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 648 0x0e8000a0, 0x0f800ff0, 649 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 650 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 651 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 652 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 653 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 654 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 655 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 656 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 657 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 658 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 659 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 660 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 661 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 662 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 663 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 665 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 667 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 669 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 671 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 673 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 675 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 677 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 679 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 681 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 683 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 685 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 687 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 689 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 691 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 693 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 695 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 697 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 699 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 700 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 701 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 702 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 703 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 704 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 705 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 706 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 707 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 708 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 709 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 710 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 711 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 712 {ANY, ARM_FEATURE_CORE_LOW (0), 713 SENTINEL_IWMMXT_END, 0, "" }, 714 715 /* Floating point coprocessor (FPA) instructions. */ 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 717 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 719 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 721 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 722 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 723 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 724 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 725 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 726 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 727 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 728 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 729 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 730 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 731 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 732 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 733 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 734 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 735 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 736 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 737 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 738 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 739 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 740 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 741 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 742 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 743 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 744 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 745 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 746 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 747 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 748 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 749 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 750 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 751 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 752 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 753 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 754 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 755 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 756 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 757 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 758 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 759 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 760 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 761 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 762 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 763 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 764 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 765 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 766 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 767 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 768 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 769 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 770 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 771 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 772 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 773 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 774 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 775 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 776 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 777 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 778 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 779 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 780 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 781 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 782 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 783 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 784 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 785 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 786 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 787 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 788 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 789 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 790 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 791 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 792 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 793 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 794 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 795 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 796 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 797 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 798 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 799 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 800 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 801 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 802 803 /* Armv8.1-M Mainline instructions. */ 804 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 805 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, 806 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 807 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, 808 809 /* ARMv8-M Mainline Security Extensions instructions. */ 810 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 811 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 812 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 813 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 814 815 /* Register load/store. */ 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 817 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 819 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 821 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 823 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 825 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 827 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 829 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 831 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 833 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 835 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 837 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 839 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 841 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 843 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 845 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 847 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 848 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 849 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, 850 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 851 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, 852 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 854 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 856 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 858 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 860 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 861 862 /* Data transfer between ARM and NEON registers. */ 863 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 864 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 865 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 866 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 867 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 868 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 869 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 870 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 871 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 872 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 873 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 874 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 875 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 876 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 877 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 878 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 879 /* Half-precision conversion instructions. */ 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 881 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 883 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 885 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 887 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 888 889 /* Floating point coprocessor (VFP) instructions. */ 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 891 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 892 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 893 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 894 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 895 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"}, 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 897 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 899 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 901 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 903 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 905 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 907 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 908 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 909 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"}, 910 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 911 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"}, 912 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 913 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"}, 914 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 915 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"}, 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 917 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 919 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 920 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 921 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 922 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 923 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"}, 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 925 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 927 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 929 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 931 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 933 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 935 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 936 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 937 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"}, 938 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 939 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"}, 940 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 941 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"}, 942 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 943 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"}, 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 945 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 947 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 949 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 951 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 953 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 955 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 957 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 959 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 961 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 963 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 965 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 967 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 968 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 969 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 970 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 971 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 972 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 973 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 974 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 975 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 976 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 977 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 978 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 979 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 980 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 981 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 982 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 983 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 984 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 985 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 986 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 987 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 988 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 989 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 990 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 991 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 992 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 993 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 994 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 995 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 996 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 997 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 998 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 999 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 1000 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1001 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 1002 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 1003 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 1004 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 1005 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 1006 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1007 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 1008 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1009 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 1010 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1011 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 1012 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1013 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 1014 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1015 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 1016 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1017 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 1018 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1019 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 1020 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1021 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 1022 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1023 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 1024 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1025 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 1026 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1027 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 1028 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1029 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 1030 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1031 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 1032 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1033 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 1034 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1035 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 1036 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1037 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 1038 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1039 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 1040 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1041 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 1042 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1043 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 1044 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1045 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 1046 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1047 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 1048 1049 /* Cirrus coprocessor instructions. */ 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1051 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1053 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1055 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1057 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1059 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1061 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1063 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1065 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1067 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1069 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1071 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1073 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1075 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1077 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1079 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1081 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1083 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1085 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1087 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1089 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1091 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1093 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1095 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1097 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1099 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1101 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1103 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1105 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1107 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1109 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1111 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1113 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1115 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1117 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1119 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1121 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1123 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1125 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1127 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1129 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1131 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 1132 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1133 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1135 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1137 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 1138 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1139 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1141 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 1142 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1143 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 1144 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1145 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 1146 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1147 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 1148 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1149 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 1150 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1151 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 1152 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1153 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 1154 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1155 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 1156 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1157 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 1158 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1159 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 1160 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1161 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 1162 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1163 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 1164 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1165 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 1166 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1167 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 1168 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1169 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 1170 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1171 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 1172 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1173 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 1174 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1175 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1176 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1177 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1178 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1179 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1180 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1181 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1182 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1183 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1184 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1185 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1186 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1187 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 1188 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1189 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 1190 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1191 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 1192 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1193 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 1194 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1195 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1196 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1197 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1198 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1199 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1200 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1201 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1202 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1203 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1204 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1205 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1206 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1207 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1209 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1210 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1211 0x0e000600, 0x0ff00f10, 1212 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1213 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1214 0x0e100600, 0x0ff00f10, 1215 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1216 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1217 0x0e200600, 0x0ff00f10, 1218 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1219 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1220 0x0e300600, 0x0ff00f10, 1221 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1222 1223 /* VFP Fused multiply add instructions. */ 1224 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1225 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 1226 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1227 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 1228 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1229 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 1230 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1231 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 1232 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1233 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 1234 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1235 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 1236 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1237 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 1238 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1239 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 1240 1241 /* FP v5. */ 1242 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1243 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 1244 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1245 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 1246 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1247 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 1248 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1249 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 1250 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1251 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 1252 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1253 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 1254 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1255 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 1256 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1257 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 1258 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1259 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 1260 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1261 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 1262 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1263 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 1264 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1265 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 1266 1267 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 1268 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1270 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1272 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1274 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1276 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1278 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1280 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1282 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1284 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1286 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1288 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, 1289 1290 /* BFloat16 instructions. */ 1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1292 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, 1293 1294 /* Dot Product instructions in the space of coprocessor 13. */ 1295 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1296 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 1297 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1298 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, 1299 1300 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1302 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1304 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1306 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1308 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1310 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1312 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1314 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1316 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 1317 1318 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 1319 cp_num: bit <11:8> == 0b1001. 1320 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1322 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1324 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1326 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1328 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1330 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1332 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1334 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1336 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1338 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1340 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1342 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1344 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1346 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1348 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1350 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1352 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 1353 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1354 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1356 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 1357 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1358 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 1359 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1360 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 1361 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1362 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 1363 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1364 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 1365 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1366 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1367 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1368 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1369 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1370 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 1371 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1372 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1373 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1374 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1375 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1376 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1377 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1378 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1379 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1380 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1381 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1382 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1383 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1384 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1385 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1386 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1387 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1388 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1389 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1390 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1391 1392 /* ARMv8.3 javascript conversion instruction. */ 1393 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1394 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1395 1396 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1397 }; 1398 1399 /* Generic coprocessor instructions. These are only matched if a more specific 1400 SIMD or co-processor instruction does not match first. */ 1401 1402 static const struct sopcode32 generic_coprocessor_opcodes[] = 1403 { 1404 /* Generic coprocessor instructions. */ 1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1406 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 1407 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1408 0x0c500000, 0x0ff00000, 1409 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 1410 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1411 0x0e000000, 0x0f000010, 1412 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 1413 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1414 0x0e10f010, 0x0f10f010, 1415 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 1416 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1417 0x0e100010, 0x0f100010, 1418 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1420 0x0e000010, 0x0f100010, 1421 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 1422 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1423 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 1424 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1425 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 1426 1427 /* V6 coprocessor instructions. */ 1428 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1429 0xfc500000, 0xfff00000, 1430 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1432 0xfc400000, 0xfff00000, 1433 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 1434 1435 /* V5 coprocessor instructions. */ 1436 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1437 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1439 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 1440 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1441 0xfe000000, 0xff000010, 1442 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 1443 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1444 0xfe000010, 0xff100010, 1445 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 1446 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1447 0xfe100010, 0xff100010, 1448 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 1449 1450 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1451 }; 1452 1453 /* Neon opcode table: This does not encode the top byte -- that is 1454 checked by the print_insn_neon routine, as it depends on whether we are 1455 doing thumb32 or arm32 disassembly. */ 1456 1457 /* print_insn_neon recognizes the following format control codes: 1458 1459 %% % 1460 1461 %c print condition code 1462 %u print condition code (unconditional in ARM mode, 1463 UNPREDICTABLE if not AL in Thumb) 1464 %A print v{st,ld}[1234] operands 1465 %B print v{st,ld}[1234] any one operands 1466 %C print v{st,ld}[1234] single->all operands 1467 %D print scalar 1468 %E print vmov, vmvn, vorr, vbic encoded constant 1469 %F print vtbl,vtbx register list 1470 1471 %<bitfield>r print as an ARM register 1472 %<bitfield>d print the bitfield in decimal 1473 %<bitfield>e print the 2^N - bitfield in decimal 1474 %<bitfield>D print as a NEON D register 1475 %<bitfield>Q print as a NEON Q register 1476 %<bitfield>R print as a NEON D or Q register 1477 %<bitfield>Sn print byte scaled width limited by n 1478 %<bitfield>Tn print short scaled width limited by n 1479 %<bitfield>Un print long scaled width limited by n 1480 1481 %<bitfield>'c print specified char iff bitfield is all ones 1482 %<bitfield>`c print specified char iff bitfield is all zeroes 1483 %<bitfield>?ab... select from array of values in big endian order. */ 1484 1485 static const struct opcode32 neon_opcodes[] = 1486 { 1487 /* Extract. */ 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1489 0xf2b00840, 0xffb00850, 1490 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1492 0xf2b00000, 0xffb00810, 1493 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1494 1495 /* Data transfer between ARM and NEON registers. */ 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1497 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1499 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1501 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1503 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1505 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1507 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 1508 1509 /* Move data element to all lanes. */ 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1511 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1516 1517 /* Table lookup. */ 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1519 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1521 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1522 1523 /* Half-precision conversions. */ 1524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1525 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1527 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1528 1529 /* NEON fused multiply add instructions. */ 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1531 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1533 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1535 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1537 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1538 1539 /* BFloat16 instructions. */ 1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1541 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1543 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1545 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1547 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, 1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1549 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1551 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"}, 1552 1553 /* Matrix Multiply instructions. */ 1554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1555 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1557 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1559 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1561 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1563 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1565 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1566 1567 /* Two registers, miscellaneous. */ 1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1569 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1571 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1573 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1575 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1576 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1577 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1578 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1579 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1580 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1581 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1582 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1583 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1584 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1585 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1586 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1587 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1589 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1593 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1595 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1599 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1601 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1603 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1607 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1609 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf3b20300, 0xffb30fd0, 1612 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1614 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1616 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1618 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1620 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1622 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1624 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1626 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1628 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1630 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1632 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1634 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1636 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1638 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1640 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1642 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1644 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1646 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1648 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1650 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1652 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1654 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1656 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1658 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1660 0xf3bb0600, 0xffbf0e10, 1661 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1663 0xf3b70600, 0xffbf0e10, 1664 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1665 1666 /* Three registers of the same length. */ 1667 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1668 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1669 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1670 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1671 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1672 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1673 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1674 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1675 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1676 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1677 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1678 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1679 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1680 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1682 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1684 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1686 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1688 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1690 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1692 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1694 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1696 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1698 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1700 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1702 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1704 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1706 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1708 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1710 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1712 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1714 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1716 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1718 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1720 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1722 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1724 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1726 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1728 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1730 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1732 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1734 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1736 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1738 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1740 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1742 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1744 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1746 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1748 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1750 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1752 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1754 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1756 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1758 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1760 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1762 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1764 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1766 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1768 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1770 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1772 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1774 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1776 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1778 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1780 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1782 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1784 0xf2000b00, 0xff800f10, 1785 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1787 0xf2000b10, 0xff800f10, 1788 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1790 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1792 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1794 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1796 0xf3000b00, 0xff800f10, 1797 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1799 0xf2000000, 0xfe800f10, 1800 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1802 0xf2000010, 0xfe800f10, 1803 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1805 0xf2000100, 0xfe800f10, 1806 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1808 0xf2000200, 0xfe800f10, 1809 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1811 0xf2000210, 0xfe800f10, 1812 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1814 0xf2000300, 0xfe800f10, 1815 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1817 0xf2000310, 0xfe800f10, 1818 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1820 0xf2000400, 0xfe800f10, 1821 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1823 0xf2000410, 0xfe800f10, 1824 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1826 0xf2000500, 0xfe800f10, 1827 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1829 0xf2000510, 0xfe800f10, 1830 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1832 0xf2000600, 0xfe800f10, 1833 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1835 0xf2000610, 0xfe800f10, 1836 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1838 0xf2000700, 0xfe800f10, 1839 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1841 0xf2000710, 0xfe800f10, 1842 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1844 0xf2000910, 0xfe800f10, 1845 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1847 0xf2000a00, 0xfe800f10, 1848 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1850 0xf2000a10, 0xfe800f10, 1851 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1853 0xf3000b10, 0xff800f10, 1854 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1856 0xf3000c10, 0xff800f10, 1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1858 1859 /* One register and an immediate value. */ 1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1861 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1863 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1865 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1867 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1869 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1871 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1873 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1875 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1877 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1879 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1881 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1883 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1885 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1886 1887 /* Two registers and a shift amount. */ 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1889 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1891 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1893 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1895 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1897 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1899 0xf2880950, 0xfeb80fd0, 1900 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1902 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1904 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1906 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1908 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1910 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1912 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1914 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1916 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1918 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1920 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1922 0xf2900950, 0xfeb00fd0, 1923 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1925 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1927 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1929 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1931 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1933 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1935 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1937 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1939 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1941 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1943 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1945 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1947 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1949 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1951 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1953 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1955 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1957 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1959 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1961 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1963 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1965 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1967 0xf2a00950, 0xfea00fd0, 1968 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1970 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1972 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1974 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1976 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1978 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1980 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1982 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1984 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1986 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1988 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1990 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1992 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1994 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1996 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1998 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2000 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2002 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2004 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2006 0xf2a00e10, 0xfea00e90, 2007 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 2008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 2009 0xf2a00c10, 0xfea00e90, 2010 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 2011 2012 /* Three registers of different lengths. */ 2013 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 2014 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2016 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2018 0xf2800400, 0xff800f50, 2019 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2021 0xf2800600, 0xff800f50, 2022 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2024 0xf2800900, 0xff800f50, 2025 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2027 0xf2800b00, 0xff800f50, 2028 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2030 0xf2800d00, 0xff800f50, 2031 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2033 0xf3800400, 0xff800f50, 2034 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2036 0xf3800600, 0xff800f50, 2037 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2039 0xf2800000, 0xfe800f50, 2040 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2042 0xf2800100, 0xfe800f50, 2043 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2045 0xf2800200, 0xfe800f50, 2046 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2048 0xf2800300, 0xfe800f50, 2049 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2051 0xf2800500, 0xfe800f50, 2052 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2054 0xf2800700, 0xfe800f50, 2055 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2057 0xf2800800, 0xfe800f50, 2058 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2060 0xf2800a00, 0xfe800f50, 2061 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2063 0xf2800c00, 0xfe800f50, 2064 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2065 2066 /* Two registers and a scalar. */ 2067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2068 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2070 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 2071 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2072 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2073 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2074 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2076 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2078 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2079 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2080 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2082 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2084 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2086 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 2087 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2088 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2090 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2092 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2094 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2096 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2098 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2099 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2100 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2102 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2104 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2105 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2106 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2108 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2110 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2111 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2112 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2114 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2116 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2118 0xf2800240, 0xfe800f50, 2119 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2121 0xf2800640, 0xfe800f50, 2122 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2124 0xf2800a40, 0xfe800f50, 2125 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2127 0xf2800e40, 0xff800f50, 2128 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2130 0xf2800f40, 0xff800f50, 2131 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2133 0xf3800e40, 0xff800f50, 2134 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2136 0xf3800f40, 0xff800f50, 2137 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 2138 }, 2139 2140 /* Element and structure load/store. */ 2141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2142 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 2143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2144 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 2145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2146 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 2147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2148 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 2149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2150 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 2151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2152 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2154 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2156 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 2157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2158 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 2159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2160 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2162 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2164 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2166 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2168 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2170 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 2171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2172 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 2173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2174 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 2175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2176 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 2177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2178 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 2179 2180 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 2181 }; 2182 2183 /* mve opcode table. */ 2184 2185 /* print_insn_mve recognizes the following format control codes: 2186 2187 %% % 2188 2189 %a print '+' or '-' or imm offset in vldr[bhwd] and 2190 vstr[bhwd] 2191 %c print condition code 2192 %d print addr mode of MVE vldr[bhw] and vstr[bhw] 2193 %u print 'U' (unsigned) or 'S' for various mve instructions 2194 %i print MVE predicate(s) for vpt and vpst 2195 %j print a 5-bit immediate from hw2[14:12,7:6] 2196 %k print 48 if the 7th position bit is set else print 64. 2197 %m print rounding mode for vcvt and vrint 2198 %n print vector comparison code for predicated instruction 2199 %s print size for various vcvt instructions 2200 %v print vector predicate for instruction in predicated 2201 block 2202 %o print offset scaled for vldr[hwd] and vstr[hwd] 2203 %w print writeback mode for MVE v{st,ld}[24] 2204 %B print v{st,ld}[24] any one operands 2205 %E print vmov, vmvn, vorr, vbic encoded constant 2206 %N print generic index for vmov 2207 %T print bottom ('b') or top ('t') of source register 2208 %X print exchange field in vmla* instructions 2209 2210 %<bitfield>r print as an ARM register 2211 %<bitfield>d print the bitfield in decimal 2212 %<bitfield>A print accumulate or not 2213 %<bitfield>c print bitfield as a condition code 2214 %<bitfield>C print bitfield as an inverted condition code 2215 %<bitfield>Q print as a MVE Q register 2216 %<bitfield>F print as a MVE S register 2217 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is 2218 UNPREDICTABLE 2219 2220 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE 2221 %<bitfield>s print size for vector predicate & non VMOV instructions 2222 %<bitfield>I print carry flag or not 2223 %<bitfield>i print immediate for vstr/vldr reg +/- imm 2224 %<bitfield>h print high half of 64-bit destination reg 2225 %<bitfield>k print immediate for vector conversion instruction 2226 %<bitfield>l print low half of 64-bit destination reg 2227 %<bitfield>o print rotate value for vcmul 2228 %<bitfield>u print immediate value for vddup/vdwdup 2229 %<bitfield>x print the bitfield in hex. 2230 */ 2231 2232 static const struct mopcode32 mve_opcodes[] = 2233 { 2234 /* MVE. */ 2235 2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2237 MVE_VPST, 2238 0xfe310f4d, 0xffbf1fff, 2239 "vpst%i" 2240 }, 2241 2242 /* Floating point VPT T1. */ 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2244 MVE_VPT_FP_T1, 2245 0xee310f00, 0xefb10f50, 2246 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2247 /* Floating point VPT T2. */ 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2249 MVE_VPT_FP_T2, 2250 0xee310f40, 0xefb10f50, 2251 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, 2252 2253 /* Vector VPT T1. */ 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2255 MVE_VPT_VEC_T1, 2256 0xfe010f00, 0xff811f51, 2257 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2258 /* Vector VPT T2. */ 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2260 MVE_VPT_VEC_T2, 2261 0xfe010f01, 0xff811f51, 2262 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2263 /* Vector VPT T3. */ 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2265 MVE_VPT_VEC_T3, 2266 0xfe011f00, 0xff811f50, 2267 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2268 /* Vector VPT T4. */ 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2270 MVE_VPT_VEC_T4, 2271 0xfe010f40, 0xff811f70, 2272 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2273 /* Vector VPT T5. */ 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2275 MVE_VPT_VEC_T5, 2276 0xfe010f60, 0xff811f70, 2277 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2278 /* Vector VPT T6. */ 2279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2280 MVE_VPT_VEC_T6, 2281 0xfe011f40, 0xff811f50, 2282 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2283 2284 /* Vector VBIC immediate. */ 2285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2286 MVE_VBIC_IMM, 2287 0xef800070, 0xefb81070, 2288 "vbic%v.i%8-11s\t%13-15,22Q, %E"}, 2289 2290 /* Vector VBIC register. */ 2291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2292 MVE_VBIC_REG, 2293 0xef100150, 0xffb11f51, 2294 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2295 2296 /* Vector VABAV. */ 2297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2298 MVE_VABAV, 2299 0xee800f01, 0xefc10f51, 2300 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, 2301 2302 /* Vector VABD floating point. */ 2303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2304 MVE_VABD_FP, 2305 0xff200d40, 0xffa11f51, 2306 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2307 2308 /* Vector VABD. */ 2309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2310 MVE_VABD_VEC, 2311 0xef000740, 0xef811f51, 2312 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2313 2314 /* Vector VABS floating point. */ 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2316 MVE_VABS_FP, 2317 0xFFB10740, 0xFFB31FD1, 2318 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2319 /* Vector VABS. */ 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2321 MVE_VABS_VEC, 2322 0xffb10340, 0xffb31fd1, 2323 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2324 2325 /* Vector VADD floating point T1. */ 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2327 MVE_VADD_FP_T1, 2328 0xef000d40, 0xffa11f51, 2329 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2330 /* Vector VADD floating point T2. */ 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2332 MVE_VADD_FP_T2, 2333 0xee300f40, 0xefb11f70, 2334 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2335 /* Vector VADD T1. */ 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2337 MVE_VADD_VEC_T1, 2338 0xef000840, 0xff811f51, 2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2340 /* Vector VADD T2. */ 2341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2342 MVE_VADD_VEC_T2, 2343 0xee010f40, 0xff811f70, 2344 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2345 2346 /* Vector VADDLV. */ 2347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2348 MVE_VADDLV, 2349 0xee890f00, 0xef8f1fd1, 2350 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, 2351 2352 /* Vector VADDV. */ 2353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2354 MVE_VADDV, 2355 0xeef10f00, 0xeff31fd1, 2356 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, 2357 2358 /* Vector VADC. */ 2359 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2360 MVE_VADC, 2361 0xee300f00, 0xffb10f51, 2362 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2363 2364 /* Vector VAND. */ 2365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2366 MVE_VAND, 2367 0xef000150, 0xffb11f51, 2368 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2369 2370 /* Vector VBRSR register. */ 2371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2372 MVE_VBRSR, 2373 0xfe011e60, 0xff811f70, 2374 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2375 2376 /* Vector VCADD floating point. */ 2377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2378 MVE_VCADD_FP, 2379 0xfc800840, 0xfea11f51, 2380 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"}, 2381 2382 /* Vector VCADD. */ 2383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2384 MVE_VCADD_VEC, 2385 0xfe000f00, 0xff810f51, 2386 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, 2387 2388 /* Vector VCLS. */ 2389 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2390 MVE_VCLS, 2391 0xffb00440, 0xffb31fd1, 2392 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2393 2394 /* Vector VCLZ. */ 2395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2396 MVE_VCLZ, 2397 0xffb004c0, 0xffb31fd1, 2398 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2399 2400 /* Vector VCMLA. */ 2401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2402 MVE_VCMLA_FP, 2403 0xfc200840, 0xfe211f51, 2404 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"}, 2405 2406 /* Vector VCMP floating point T1. */ 2407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2408 MVE_VCMP_FP_T1, 2409 0xee310f00, 0xeff1ef50, 2410 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2411 2412 /* Vector VCMP floating point T2. */ 2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2414 MVE_VCMP_FP_T2, 2415 0xee310f40, 0xeff1ef50, 2416 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, 2417 2418 /* Vector VCMP T1. */ 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2420 MVE_VCMP_VEC_T1, 2421 0xfe010f00, 0xffc1ff51, 2422 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2423 /* Vector VCMP T2. */ 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2425 MVE_VCMP_VEC_T2, 2426 0xfe010f01, 0xffc1ff51, 2427 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2428 /* Vector VCMP T3. */ 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2430 MVE_VCMP_VEC_T3, 2431 0xfe011f00, 0xffc1ff50, 2432 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2433 /* Vector VCMP T4. */ 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2435 MVE_VCMP_VEC_T4, 2436 0xfe010f40, 0xffc1ff70, 2437 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2438 /* Vector VCMP T5. */ 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2440 MVE_VCMP_VEC_T5, 2441 0xfe010f60, 0xffc1ff70, 2442 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2443 /* Vector VCMP T6. */ 2444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2445 MVE_VCMP_VEC_T6, 2446 0xfe011f40, 0xffc1ff50, 2447 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2448 2449 /* Vector VDUP. */ 2450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2451 MVE_VDUP, 2452 0xeea00b10, 0xffb10f5f, 2453 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2454 2455 /* Vector VEOR. */ 2456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2457 MVE_VEOR, 2458 0xff000150, 0xffd11f51, 2459 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2460 2461 /* Vector VFMA, vector * scalar. */ 2462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2463 MVE_VFMA_FP_SCALAR, 2464 0xee310e40, 0xefb11f70, 2465 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2466 2467 /* Vector VFMA floating point. */ 2468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2469 MVE_VFMA_FP, 2470 0xef000c50, 0xffa11f51, 2471 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2472 2473 /* Vector VFMS floating point. */ 2474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2475 MVE_VFMS_FP, 2476 0xef200c50, 0xffa11f51, 2477 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2478 2479 /* Vector VFMAS, vector * scalar. */ 2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2481 MVE_VFMAS_FP_SCALAR, 2482 0xee311e40, 0xefb11f70, 2483 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2484 2485 /* Vector VHADD T1. */ 2486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2487 MVE_VHADD_T1, 2488 0xef000040, 0xef811f51, 2489 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2490 2491 /* Vector VHADD T2. */ 2492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2493 MVE_VHADD_T2, 2494 0xee000f40, 0xef811f70, 2495 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2496 2497 /* Vector VHSUB T1. */ 2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2499 MVE_VHSUB_T1, 2500 0xef000240, 0xef811f51, 2501 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2502 2503 /* Vector VHSUB T2. */ 2504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2505 MVE_VHSUB_T2, 2506 0xee001f40, 0xef811f70, 2507 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2508 2509 /* Vector VCMUL. */ 2510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2511 MVE_VCMUL_FP, 2512 0xee300e00, 0xefb10f50, 2513 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"}, 2514 2515 /* Vector VCTP. */ 2516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2517 MVE_VCTP, 2518 0xf000e801, 0xffc0ffff, 2519 "vctp%v.%20-21s\t%16-19r"}, 2520 2521 /* Vector VDUP. */ 2522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2523 MVE_VDUP, 2524 0xeea00b10, 0xffb10f5f, 2525 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2526 2527 /* Vector VRHADD. */ 2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2529 MVE_VRHADD, 2530 0xef000140, 0xef811f51, 2531 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2532 2533 /* Vector VCVT. */ 2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2535 MVE_VCVT_FP_FIX_VEC, 2536 0xef800c50, 0xef801cd1, 2537 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"}, 2538 2539 /* Vector VCVT. */ 2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2541 MVE_VCVT_BETWEEN_FP_INT, 2542 0xffb30640, 0xffb31e51, 2543 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2544 2545 /* Vector VCVT between single and half-precision float, bottom half. */ 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2547 MVE_VCVT_FP_HALF_FP, 2548 0xee3f0e01, 0xefbf1fd1, 2549 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, 2550 2551 /* Vector VCVT between single and half-precision float, top half. */ 2552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2553 MVE_VCVT_FP_HALF_FP, 2554 0xee3f1e01, 0xefbf1fd1, 2555 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2556 2557 /* Vector VCVT. */ 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2559 MVE_VCVT_FROM_FP_TO_INT, 2560 0xffb30040, 0xffb31c51, 2561 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, 2562 2563 /* Vector VDDUP. */ 2564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2565 MVE_VDDUP, 2566 0xee011f6e, 0xff811f7e, 2567 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, 2568 2569 /* Vector VDWDUP. */ 2570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2571 MVE_VDWDUP, 2572 0xee011f60, 0xff811f70, 2573 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, 2574 2575 /* Vector VHCADD. */ 2576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2577 MVE_VHCADD, 2578 0xee000f00, 0xff810f51, 2579 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, 2580 2581 /* Vector VIWDUP. */ 2582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2583 MVE_VIWDUP, 2584 0xee010f60, 0xff811f70, 2585 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, 2586 2587 /* Vector VIDUP. */ 2588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2589 MVE_VIDUP, 2590 0xee010f6e, 0xff811f7e, 2591 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, 2592 2593 /* Vector VLD2. */ 2594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2595 MVE_VLD2, 2596 0xfc901e00, 0xff901e5f, 2597 "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, 2598 2599 /* Vector VLD4. */ 2600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2601 MVE_VLD4, 2602 0xfc901e01, 0xff901e1f, 2603 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, 2604 2605 /* Vector VLDRB gather load. */ 2606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2607 MVE_VLDRB_GATHER_T1, 2608 0xec900e00, 0xefb01e50, 2609 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 2610 2611 /* Vector VLDRH gather load. */ 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2613 MVE_VLDRH_GATHER_T2, 2614 0xec900e10, 0xefb01e50, 2615 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2616 2617 /* Vector VLDRW gather load. */ 2618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2619 MVE_VLDRW_GATHER_T3, 2620 0xfc900f40, 0xffb01fd0, 2621 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2622 2623 /* Vector VLDRD gather load. */ 2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2625 MVE_VLDRD_GATHER_T4, 2626 0xec900fd0, 0xefb01fd0, 2627 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2628 2629 /* Vector VLDRW gather load. */ 2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2631 MVE_VLDRW_GATHER_T5, 2632 0xfd101e00, 0xff111f00, 2633 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 2634 2635 /* Vector VLDRD gather load, variant T6. */ 2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2637 MVE_VLDRD_GATHER_T6, 2638 0xfd101f00, 0xff111f00, 2639 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 2640 2641 /* Vector VLDRB. */ 2642 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2643 MVE_VLDRB_T1, 2644 0xec100e00, 0xee581e00, 2645 "vldrb%v.%u%7-8s\t%13-15Q, %d"}, 2646 2647 /* Vector VLDRH. */ 2648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2649 MVE_VLDRH_T2, 2650 0xec180e00, 0xee581e00, 2651 "vldrh%v.%u%7-8s\t%13-15Q, %d"}, 2652 2653 /* Vector VLDRB unsigned, variant T5. */ 2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2655 MVE_VLDRB_T5, 2656 0xec101e00, 0xfe101f80, 2657 "vldrb%v.u8\t%13-15,22Q, %d"}, 2658 2659 /* Vector VLDRH unsigned, variant T6. */ 2660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2661 MVE_VLDRH_T6, 2662 0xec101e80, 0xfe101f80, 2663 "vldrh%v.u16\t%13-15,22Q, %d"}, 2664 2665 /* Vector VLDRW unsigned, variant T7. */ 2666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2667 MVE_VLDRW_T7, 2668 0xec101f00, 0xfe101f80, 2669 "vldrw%v.u32\t%13-15,22Q, %d"}, 2670 2671 /* Vector VMAX. */ 2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2673 MVE_VMAX, 2674 0xef000640, 0xef811f51, 2675 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2676 2677 /* Vector VMAXA. */ 2678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2679 MVE_VMAXA, 2680 0xee330e81, 0xffb31fd1, 2681 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2682 2683 /* Vector VMAXNM floating point. */ 2684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2685 MVE_VMAXNM_FP, 2686 0xff000f50, 0xffa11f51, 2687 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2688 2689 /* Vector VMAXNMA floating point. */ 2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2691 MVE_VMAXNMA_FP, 2692 0xee3f0e81, 0xefbf1fd1, 2693 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2694 2695 /* Vector VMAXNMV floating point. */ 2696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2697 MVE_VMAXNMV_FP, 2698 0xeeee0f00, 0xefff0fd1, 2699 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2700 2701 /* Vector VMAXNMAV floating point. */ 2702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2703 MVE_VMAXNMAV_FP, 2704 0xeeec0f00, 0xefff0fd1, 2705 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2706 2707 /* Vector VMAXV. */ 2708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2709 MVE_VMAXV, 2710 0xeee20f00, 0xeff30fd1, 2711 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2712 2713 /* Vector VMAXAV. */ 2714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2715 MVE_VMAXAV, 2716 0xeee00f00, 0xfff30fd1, 2717 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2718 2719 /* Vector VMIN. */ 2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2721 MVE_VMIN, 2722 0xef000650, 0xef811f51, 2723 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2724 2725 /* Vector VMINA. */ 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2727 MVE_VMINA, 2728 0xee331e81, 0xffb31fd1, 2729 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2730 2731 /* Vector VMINNM floating point. */ 2732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2733 MVE_VMINNM_FP, 2734 0xff200f50, 0xffa11f51, 2735 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2736 2737 /* Vector VMINNMA floating point. */ 2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2739 MVE_VMINNMA_FP, 2740 0xee3f1e81, 0xefbf1fd1, 2741 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2742 2743 /* Vector VMINNMV floating point. */ 2744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2745 MVE_VMINNMV_FP, 2746 0xeeee0f80, 0xefff0fd1, 2747 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2748 2749 /* Vector VMINNMAV floating point. */ 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2751 MVE_VMINNMAV_FP, 2752 0xeeec0f80, 0xefff0fd1, 2753 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2754 2755 /* Vector VMINV. */ 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2757 MVE_VMINV, 2758 0xeee20f80, 0xeff30fd1, 2759 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2760 2761 /* Vector VMINAV. */ 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2763 MVE_VMINAV, 2764 0xeee00f80, 0xfff30fd1, 2765 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2766 2767 /* Vector VMLA. */ 2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2769 MVE_VMLA, 2770 0xee010e40, 0xef811f70, 2771 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2772 2773 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction 2774 opcode aliasing. */ 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2776 MVE_VMLALDAV, 2777 0xee801e00, 0xef801f51, 2778 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2779 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2781 MVE_VMLALDAV, 2782 0xee800e00, 0xef801f51, 2783 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2784 2785 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2787 MVE_VMLADAV_T1, 2788 0xeef00e00, 0xeff01f51, 2789 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2790 2791 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ 2792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2793 MVE_VMLADAV_T2, 2794 0xeef00f00, 0xeff11f51, 2795 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2796 2797 /* Vector VMLADAV T1 variant. */ 2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2799 MVE_VMLADAV_T1, 2800 0xeef01e00, 0xeff01f51, 2801 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2802 2803 /* Vector VMLADAV T2 variant. */ 2804 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2805 MVE_VMLADAV_T2, 2806 0xeef01f00, 0xeff11f51, 2807 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2808 2809 /* Vector VMLAS. */ 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2811 MVE_VMLAS, 2812 0xee011e40, 0xef811f70, 2813 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2814 2815 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction 2816 opcode aliasing. */ 2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2818 MVE_VRMLSLDAVH, 2819 0xfe800e01, 0xff810f51, 2820 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2821 2822 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction 2823 opcdoe aliasing. */ 2824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2825 MVE_VMLSLDAV, 2826 0xee800e01, 0xff800f51, 2827 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2828 2829 /* Vector VMLSDAV T1 Variant. */ 2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2831 MVE_VMLSDAV_T1, 2832 0xeef00e01, 0xfff00f51, 2833 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2834 2835 /* Vector VMLSDAV T2 Variant. */ 2836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2837 MVE_VMLSDAV_T2, 2838 0xfef00e01, 0xfff10f51, 2839 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, 2840 2841 /* Vector VMOV between gpr and half precision register, op == 0. */ 2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2843 MVE_VMOV_HFP_TO_GP, 2844 0xee000910, 0xfff00f7f, 2845 "vmov.f16\t%7,16-19F, %12-15r"}, 2846 2847 /* Vector VMOV between gpr and half precision register, op == 1. */ 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2849 MVE_VMOV_HFP_TO_GP, 2850 0xee100910, 0xfff00f7f, 2851 "vmov.f16\t%12-15r, %7,16-19F"}, 2852 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2854 MVE_VMOV_GP_TO_VEC_LANE, 2855 0xee000b10, 0xff900f1f, 2856 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"}, 2857 2858 /* Vector VORR immediate to vector. 2859 NOTE: MVE_VORR_IMM must appear in the table 2860 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2862 MVE_VORR_IMM, 2863 0xef800050, 0xefb810f0, 2864 "vorr%v.i%8-11s\t%13-15,22Q, %E"}, 2865 2866 /* Vector VQSHL T2 Variant. 2867 NOTE: MVE_VQSHL_T2 must appear in the table before 2868 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2869 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2870 MVE_VQSHL_T2, 2871 0xef800750, 0xef801fd1, 2872 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2873 2874 /* Vector VQSHLU T3 Variant 2875 NOTE: MVE_VQSHL_T2 must appear in the table before 2876 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2877 2878 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2879 MVE_VQSHLU_T3, 2880 0xff800650, 0xff801fd1, 2881 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2882 2883 /* Vector VRSHR 2884 NOTE: MVE_VRSHR must appear in the table before 2885 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2887 MVE_VRSHR, 2888 0xef800250, 0xef801fd1, 2889 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2890 2891 /* Vector VSHL. 2892 NOTE: MVE_VSHL must appear in the table before 2893 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2895 MVE_VSHL_T1, 2896 0xef800550, 0xff801fd1, 2897 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2898 2899 /* Vector VSHR 2900 NOTE: MVE_VSHR must appear in the table before 2901 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2903 MVE_VSHR, 2904 0xef800050, 0xef801fd1, 2905 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2906 2907 /* Vector VSLI 2908 NOTE: MVE_VSLI must appear in the table before 2909 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2911 MVE_VSLI, 2912 0xff800550, 0xff801fd1, 2913 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2914 2915 /* Vector VSRI 2916 NOTE: MVE_VSRI must appear in the table before 2917 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2919 MVE_VSRI, 2920 0xff800450, 0xff801fd1, 2921 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2922 2923 /* Vector VMOV immediate to vector, 2924 undefinded for cmode == 1111 */ 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2926 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, 2927 2928 /* Vector VMOV immediate to vector, 2929 cmode == 1101 */ 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2931 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, 2932 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2933 2934 /* Vector VMOV immediate to vector. */ 2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2936 MVE_VMOV_IMM_TO_VEC, 2937 0xef800050, 0xefb810d0, 2938 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2939 2940 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ 2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2942 MVE_VMOV2_VEC_LANE_TO_GP, 2943 0xec000f00, 0xffb01ff0, 2944 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"}, 2945 2946 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ 2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2948 MVE_VMOV2_VEC_LANE_TO_GP, 2949 0xec000f10, 0xffb01ff0, 2950 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"}, 2951 2952 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ 2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2954 MVE_VMOV2_GP_TO_VEC_LANE, 2955 0xec100f00, 0xffb01ff0, 2956 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, 2957 2958 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ 2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2960 MVE_VMOV2_GP_TO_VEC_LANE, 2961 0xec100f10, 0xffb01ff0, 2962 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, 2963 2964 /* Vector VMOV Vector lane to gpr. */ 2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2966 MVE_VMOV_VEC_LANE_TO_GP, 2967 0xee100b10, 0xff100f1f, 2968 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"}, 2969 2970 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due 2971 to instruction opcode aliasing. */ 2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2973 MVE_VSHLL_T1, 2974 0xeea00f40, 0xefa00fd1, 2975 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2976 2977 /* Vector VMOVL long. */ 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2979 MVE_VMOVL, 2980 0xeea00f40, 0xefa70fd1, 2981 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, 2982 2983 /* Vector VMOV and narrow. */ 2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2985 MVE_VMOVN, 2986 0xfe310e81, 0xffb30fd1, 2987 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2988 2989 /* Floating point move extract. */ 2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2991 MVE_VMOVX, 2992 0xfeb00a40, 0xffbf0fd0, 2993 "vmovx.f16\t%22,12-15F, %5,0-3F"}, 2994 2995 /* Vector VMUL floating-point T1 variant. */ 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2997 MVE_VMUL_FP_T1, 2998 0xff000d50, 0xffa11f51, 2999 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3000 3001 /* Vector VMUL floating-point T2 variant. */ 3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3003 MVE_VMUL_FP_T2, 3004 0xee310e60, 0xefb11f70, 3005 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3006 3007 /* Vector VMUL T1 variant. */ 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3009 MVE_VMUL_VEC_T1, 3010 0xef000950, 0xff811f51, 3011 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3012 3013 /* Vector VMUL T2 variant. */ 3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3015 MVE_VMUL_VEC_T2, 3016 0xee011e60, 0xff811f70, 3017 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3018 3019 /* Vector VMULH. */ 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3021 MVE_VMULH, 3022 0xee010e01, 0xef811f51, 3023 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3024 3025 /* Vector VRMULH. */ 3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3027 MVE_VRMULH, 3028 0xee011e01, 0xef811f51, 3029 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3030 3031 /* Vector VMULL integer. */ 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3033 MVE_VMULL_INT, 3034 0xee010e00, 0xef810f51, 3035 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3036 3037 /* Vector VMULL polynomial. */ 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3039 MVE_VMULL_POLY, 3040 0xee310e00, 0xefb10f51, 3041 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3042 3043 /* Vector VMVN immediate to vector. */ 3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3045 MVE_VMVN_IMM, 3046 0xef800070, 0xefb810f0, 3047 "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, 3048 3049 /* Vector VMVN register. */ 3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3051 MVE_VMVN_REG, 3052 0xffb005c0, 0xffbf1fd1, 3053 "vmvn%v\t%13-15,22Q, %1-3,5Q"}, 3054 3055 /* Vector VNEG floating point. */ 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3057 MVE_VNEG_FP, 3058 0xffb107c0, 0xffb31fd1, 3059 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3060 3061 /* Vector VNEG. */ 3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3063 MVE_VNEG_VEC, 3064 0xffb103c0, 0xffb31fd1, 3065 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3066 3067 /* Vector VORN, vector bitwise or not. */ 3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3069 MVE_VORN, 3070 0xef300150, 0xffb11f51, 3071 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3072 3073 /* Vector VORR register. */ 3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3075 MVE_VORR_REG, 3076 0xef200150, 0xffb11f51, 3077 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3078 3079 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if 3080 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen 3081 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes 3082 array. */ 3083 3084 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3085 MVE_VMOV_VEC_TO_VEC, 3086 0xef200150, 0xffb11f51, 3087 "vmov%v\t%13-15,22Q, %17-19,7Q"}, 3088 3089 /* Vector VQDMULL T1 variant. */ 3090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3091 MVE_VQDMULL_T1, 3092 0xee300f01, 0xefb10f51, 3093 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3094 3095 /* Vector VPNOT. */ 3096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3097 MVE_VPNOT, 3098 0xfe310f4d, 0xffffffff, 3099 "vpnot%v"}, 3100 3101 /* Vector VPSEL. */ 3102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3103 MVE_VPSEL, 3104 0xfe310f01, 0xffb11f51, 3105 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3106 3107 /* Vector VQABS. */ 3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3109 MVE_VQABS, 3110 0xffb00740, 0xffb31fd1, 3111 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3112 3113 /* Vector VQADD T1 variant. */ 3114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3115 MVE_VQADD_T1, 3116 0xef000050, 0xef811f51, 3117 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3118 3119 /* Vector VQADD T2 variant. */ 3120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3121 MVE_VQADD_T2, 3122 0xee000f60, 0xef811f70, 3123 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3124 3125 /* Vector VQDMULL T2 variant. */ 3126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3127 MVE_VQDMULL_T2, 3128 0xee300f60, 0xefb10f70, 3129 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3130 3131 /* Vector VQMOVN. */ 3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3133 MVE_VQMOVN, 3134 0xee330e01, 0xefb30fd1, 3135 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, 3136 3137 /* Vector VQMOVUN. */ 3138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3139 MVE_VQMOVUN, 3140 0xee310e81, 0xffb30fd1, 3141 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3142 3143 /* Vector VQDMLADH. */ 3144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3145 MVE_VQDMLADH, 3146 0xee000e00, 0xff810f51, 3147 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3148 3149 /* Vector VQRDMLADH. */ 3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3151 MVE_VQRDMLADH, 3152 0xee000e01, 0xff810f51, 3153 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3154 3155 /* Vector VQDMLAH. */ 3156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3157 MVE_VQDMLAH, 3158 0xee000e60, 0xff811f70, 3159 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3160 3161 /* Vector VQRDMLAH. */ 3162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3163 MVE_VQRDMLAH, 3164 0xee000e40, 0xff811f70, 3165 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3166 3167 /* Vector VQDMLASH. */ 3168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3169 MVE_VQDMLASH, 3170 0xee001e60, 0xff811f70, 3171 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3172 3173 /* Vector VQRDMLASH. */ 3174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3175 MVE_VQRDMLASH, 3176 0xee001e40, 0xff811f70, 3177 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3178 3179 /* Vector VQDMLSDH. */ 3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3181 MVE_VQDMLSDH, 3182 0xfe000e00, 0xff810f51, 3183 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3184 3185 /* Vector VQRDMLSDH. */ 3186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3187 MVE_VQRDMLSDH, 3188 0xfe000e01, 0xff810f51, 3189 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3190 3191 /* Vector VQDMULH T1 variant. */ 3192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3193 MVE_VQDMULH_T1, 3194 0xef000b40, 0xff811f51, 3195 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3196 3197 /* Vector VQRDMULH T2 variant. */ 3198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3199 MVE_VQRDMULH_T2, 3200 0xff000b40, 0xff811f51, 3201 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3202 3203 /* Vector VQDMULH T3 variant. */ 3204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3205 MVE_VQDMULH_T3, 3206 0xee010e60, 0xff811f70, 3207 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3208 3209 /* Vector VQRDMULH T4 variant. */ 3210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3211 MVE_VQRDMULH_T4, 3212 0xfe010e60, 0xff811f70, 3213 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3214 3215 /* Vector VQNEG. */ 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3217 MVE_VQNEG, 3218 0xffb007c0, 0xffb31fd1, 3219 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3220 3221 /* Vector VQRSHL T1 variant. */ 3222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3223 MVE_VQRSHL_T1, 3224 0xef000550, 0xef811f51, 3225 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3226 3227 /* Vector VQRSHL T2 variant. */ 3228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3229 MVE_VQRSHL_T2, 3230 0xee331ee0, 0xefb31ff0, 3231 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3232 3233 /* Vector VQRSHRN. */ 3234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3235 MVE_VQRSHRN, 3236 0xee800f41, 0xefa00fd1, 3237 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3238 3239 /* Vector VQRSHRUN. */ 3240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3241 MVE_VQRSHRUN, 3242 0xfe800fc0, 0xffa00fd1, 3243 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3244 3245 /* Vector VQSHL T1 Variant. */ 3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3247 MVE_VQSHL_T1, 3248 0xee311ee0, 0xefb31ff0, 3249 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3250 3251 /* Vector VQSHL T4 Variant. */ 3252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3253 MVE_VQSHL_T4, 3254 0xef000450, 0xef811f51, 3255 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3256 3257 /* Vector VQSHRN. */ 3258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3259 MVE_VQSHRN, 3260 0xee800f40, 0xefa00fd1, 3261 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3262 3263 /* Vector VQSHRUN. */ 3264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3265 MVE_VQSHRUN, 3266 0xee800fc0, 0xffa00fd1, 3267 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3268 3269 /* Vector VQSUB T1 Variant. */ 3270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3271 MVE_VQSUB_T1, 3272 0xef000250, 0xef811f51, 3273 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3274 3275 /* Vector VQSUB T2 Variant. */ 3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3277 MVE_VQSUB_T2, 3278 0xee001f60, 0xef811f70, 3279 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3280 3281 /* Vector VREV16. */ 3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3283 MVE_VREV16, 3284 0xffb00140, 0xffb31fd1, 3285 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"}, 3286 3287 /* Vector VREV32. */ 3288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3289 MVE_VREV32, 3290 0xffb000c0, 0xffb31fd1, 3291 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3292 3293 /* Vector VREV64. */ 3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3295 MVE_VREV64, 3296 0xffb00040, 0xffb31fd1, 3297 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3298 3299 /* Vector VRINT floating point. */ 3300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3301 MVE_VRINT_FP, 3302 0xffb20440, 0xffb31c51, 3303 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3304 3305 /* Vector VRMLALDAVH. */ 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3307 MVE_VRMLALDAVH, 3308 0xee800f00, 0xef811f51, 3309 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3310 3311 /* Vector VRMLALDAVH. */ 3312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3313 MVE_VRMLALDAVH, 3314 0xee801f00, 0xef811f51, 3315 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3316 3317 /* Vector VRSHL T1 Variant. */ 3318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3319 MVE_VRSHL_T1, 3320 0xef000540, 0xef811f51, 3321 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3322 3323 /* Vector VRSHL T2 Variant. */ 3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3325 MVE_VRSHL_T2, 3326 0xee331e60, 0xefb31ff0, 3327 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3328 3329 /* Vector VRSHRN. */ 3330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3331 MVE_VRSHRN, 3332 0xfe800fc1, 0xffa00fd1, 3333 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3334 3335 /* Vector VSBC. */ 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3337 MVE_VSBC, 3338 0xfe300f00, 0xffb10f51, 3339 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3340 3341 /* Vector VSHL T2 Variant. */ 3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3343 MVE_VSHL_T2, 3344 0xee311e60, 0xefb31ff0, 3345 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3346 3347 /* Vector VSHL T3 Variant. */ 3348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3349 MVE_VSHL_T3, 3350 0xef000440, 0xef811f51, 3351 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3352 3353 /* Vector VSHLC. */ 3354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3355 MVE_VSHLC, 3356 0xeea00fc0, 0xffa01ff0, 3357 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"}, 3358 3359 /* Vector VSHLL T2 Variant. */ 3360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3361 MVE_VSHLL_T2, 3362 0xee310e01, 0xefb30fd1, 3363 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"}, 3364 3365 /* Vector VSHRN. */ 3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3367 MVE_VSHRN, 3368 0xee800fc1, 0xffa00fd1, 3369 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3370 3371 /* Vector VST2 no writeback. */ 3372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3373 MVE_VST2, 3374 0xfc801e00, 0xffb01e5f, 3375 "vst2%5d.%7-8s\t%B, [%16-19r]"}, 3376 3377 /* Vector VST2 writeback. */ 3378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3379 MVE_VST2, 3380 0xfca01e00, 0xffb01e5f, 3381 "vst2%5d.%7-8s\t%B, [%16-19r]!"}, 3382 3383 /* Vector VST4 no writeback. */ 3384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3385 MVE_VST4, 3386 0xfc801e01, 0xffb01e1f, 3387 "vst4%5-6d.%7-8s\t%B, [%16-19r]"}, 3388 3389 /* Vector VST4 writeback. */ 3390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3391 MVE_VST4, 3392 0xfca01e01, 0xffb01e1f, 3393 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"}, 3394 3395 /* Vector VSTRB scatter store, T1 variant. */ 3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3397 MVE_VSTRB_SCATTER_T1, 3398 0xec800e00, 0xffb01e50, 3399 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 3400 3401 /* Vector VSTRH scatter store, T2 variant. */ 3402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3403 MVE_VSTRH_SCATTER_T2, 3404 0xec800e10, 0xffb01e50, 3405 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3406 3407 /* Vector VSTRW scatter store, T3 variant. */ 3408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3409 MVE_VSTRW_SCATTER_T3, 3410 0xec800e40, 0xffb01e50, 3411 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3412 3413 /* Vector VSTRD scatter store, T4 variant. */ 3414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3415 MVE_VSTRD_SCATTER_T4, 3416 0xec800fd0, 0xffb01fd0, 3417 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3418 3419 /* Vector VSTRW scatter store, T5 variant. */ 3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3421 MVE_VSTRW_SCATTER_T5, 3422 0xfd001e00, 0xff111f00, 3423 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 3424 3425 /* Vector VSTRD scatter store, T6 variant. */ 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3427 MVE_VSTRD_SCATTER_T6, 3428 0xfd001f00, 0xff111f00, 3429 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 3430 3431 /* Vector VSTRB. */ 3432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3433 MVE_VSTRB_T1, 3434 0xec000e00, 0xfe581e00, 3435 "vstrb%v.%7-8s\t%13-15Q, %d"}, 3436 3437 /* Vector VSTRH. */ 3438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3439 MVE_VSTRH_T2, 3440 0xec080e00, 0xfe581e00, 3441 "vstrh%v.%7-8s\t%13-15Q, %d"}, 3442 3443 /* Vector VSTRB variant T5. */ 3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3445 MVE_VSTRB_T5, 3446 0xec001e00, 0xfe101f80, 3447 "vstrb%v.8\t%13-15,22Q, %d"}, 3448 3449 /* Vector VSTRH variant T6. */ 3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3451 MVE_VSTRH_T6, 3452 0xec001e80, 0xfe101f80, 3453 "vstrh%v.16\t%13-15,22Q, %d"}, 3454 3455 /* Vector VSTRW variant T7. */ 3456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3457 MVE_VSTRW_T7, 3458 0xec001f00, 0xfe101f80, 3459 "vstrw%v.32\t%13-15,22Q, %d"}, 3460 3461 /* Vector VSUB floating point T1 variant. */ 3462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3463 MVE_VSUB_FP_T1, 3464 0xef200d40, 0xffa11f51, 3465 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3466 3467 /* Vector VSUB floating point T2 variant. */ 3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3469 MVE_VSUB_FP_T2, 3470 0xee301f40, 0xefb11f70, 3471 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3472 3473 /* Vector VSUB T1 variant. */ 3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3475 MVE_VSUB_VEC_T1, 3476 0xff000840, 0xff811f51, 3477 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3478 3479 /* Vector VSUB T2 variant. */ 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3481 MVE_VSUB_VEC_T2, 3482 0xee011f40, 0xff811f70, 3483 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3484 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3486 MVE_ASRLI, 3487 0xea50012f, 0xfff1813f, 3488 "asrl%c\t%17-19l, %9-11h, %j"}, 3489 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3491 MVE_ASRL, 3492 0xea50012d, 0xfff101ff, 3493 "asrl%c\t%17-19l, %9-11h, %12-15S"}, 3494 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3496 MVE_LSLLI, 3497 0xea50010f, 0xfff1813f, 3498 "lsll%c\t%17-19l, %9-11h, %j"}, 3499 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3501 MVE_LSLL, 3502 0xea50010d, 0xfff101ff, 3503 "lsll%c\t%17-19l, %9-11h, %12-15S"}, 3504 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3506 MVE_LSRL, 3507 0xea50011f, 0xfff1813f, 3508 "lsrl%c\t%17-19l, %9-11h, %j"}, 3509 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3511 MVE_SQRSHRL, 3512 0xea51012d, 0xfff1017f, 3513 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, 3514 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3516 MVE_SQRSHR, 3517 0xea500f2d, 0xfff00fff, 3518 "sqrshr%c\t%16-19S, %12-15S"}, 3519 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3521 MVE_SQSHLL, 3522 0xea51013f, 0xfff1813f, 3523 "sqshll%c\t%17-19l, %9-11h, %j"}, 3524 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3526 MVE_SQSHL, 3527 0xea500f3f, 0xfff08f3f, 3528 "sqshl%c\t%16-19S, %j"}, 3529 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3531 MVE_SRSHRL, 3532 0xea51012f, 0xfff1813f, 3533 "srshrl%c\t%17-19l, %9-11h, %j"}, 3534 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3536 MVE_SRSHR, 3537 0xea500f2f, 0xfff08f3f, 3538 "srshr%c\t%16-19S, %j"}, 3539 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3541 MVE_UQRSHLL, 3542 0xea51010d, 0xfff1017f, 3543 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, 3544 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3546 MVE_UQRSHL, 3547 0xea500f0d, 0xfff00fff, 3548 "uqrshl%c\t%16-19S, %12-15S"}, 3549 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3551 MVE_UQSHLL, 3552 0xea51010f, 0xfff1813f, 3553 "uqshll%c\t%17-19l, %9-11h, %j"}, 3554 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3556 MVE_UQSHL, 3557 0xea500f0f, 0xfff08f3f, 3558 "uqshl%c\t%16-19S, %j"}, 3559 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3561 MVE_URSHRL, 3562 0xea51011f, 0xfff1813f, 3563 "urshrl%c\t%17-19l, %9-11h, %j"}, 3564 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3566 MVE_URSHR, 3567 0xea500f1f, 0xfff08f3f, 3568 "urshr%c\t%16-19S, %j"}, 3569 3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3571 MVE_CSINC, 3572 0xea509000, 0xfff0f000, 3573 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3574 3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3576 MVE_CSINV, 3577 0xea50a000, 0xfff0f000, 3578 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3579 3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3581 MVE_CSET, 3582 0xea5f900f, 0xfffff00f, 3583 "cset\t%8-11S, %4-7C"}, 3584 3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3586 MVE_CSETM, 3587 0xea5fa00f, 0xfffff00f, 3588 "csetm\t%8-11S, %4-7C"}, 3589 3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3591 MVE_CSEL, 3592 0xea508000, 0xfff0f000, 3593 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3594 3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3596 MVE_CSNEG, 3597 0xea50b000, 0xfff0f000, 3598 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3599 3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3601 MVE_CINC, 3602 0xea509000, 0xfff0f000, 3603 "cinc\t%8-11S, %16-19Z, %4-7C"}, 3604 3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3606 MVE_CINV, 3607 0xea50a000, 0xfff0f000, 3608 "cinv\t%8-11S, %16-19Z, %4-7C"}, 3609 3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3611 MVE_CNEG, 3612 0xea50b000, 0xfff0f000, 3613 "cneg\t%8-11S, %16-19Z, %4-7C"}, 3614 3615 {ARM_FEATURE_CORE_LOW (0), 3616 MVE_NONE, 3617 0x00000000, 0x00000000, 0} 3618 }; 3619 3620 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 3621 ordered: they must be searched linearly from the top to obtain a correct 3622 match. */ 3623 3624 /* print_insn_arm recognizes the following format control codes: 3625 3626 %% % 3627 3628 %a print address for ldr/str instruction 3629 %s print address for ldr/str halfword/signextend instruction 3630 %S like %s but allow UNPREDICTABLE addressing 3631 %b print branch destination 3632 %c print condition code (always bits 28-31) 3633 %m print register mask for ldm/stm instruction 3634 %o print operand2 (immediate or register + shift) 3635 %p print 'p' iff bits 12-15 are 15 3636 %t print 't' iff bit 21 set and bit 24 clear 3637 %B print arm BLX(1) destination 3638 %C print the PSR sub type. 3639 %U print barrier type. 3640 %P print address for pli instruction. 3641 3642 %<bitfield>r print as an ARM register 3643 %<bitfield>T print as an ARM register + 1 3644 %<bitfield>R as %r but r15 is UNPREDICTABLE 3645 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 3646 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 3647 %<bitfield>d print the bitfield in decimal 3648 %<bitfield>W print the bitfield plus one in decimal 3649 %<bitfield>x print the bitfield in hex 3650 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 3651 3652 %<bitfield>'c print specified char iff bitfield is all ones 3653 %<bitfield>`c print specified char iff bitfield is all zeroes 3654 %<bitfield>?ab... select from array of values in big endian order 3655 3656 %e print arm SMI operand (bits 0..7,8..19). 3657 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 3658 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 3659 %R print the SPSR/CPSR or banked register of an MRS. */ 3660 3661 static const struct opcode32 arm_opcodes[] = 3662 { 3663 /* ARM instructions. */ 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3665 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3667 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 3668 3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 3670 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3672 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3674 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 3676 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3678 0x00800090, 0x0fa000f0, 3679 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3681 0x00a00090, 0x0fa000f0, 3682 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3683 3684 /* V8.2 RAS extension instructions. */ 3685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 3686 0xe320f010, 0xffffffff, "esb"}, 3687 3688 /* V8-R instructions. */ 3689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 3690 0xf57ff04c, 0xffffffff, "dfb"}, 3691 3692 /* V8 instructions. */ 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3694 0x0320f005, 0x0fffffff, "sevl"}, 3695 /* Defined in V8 but is in NOP space so available to all arch. */ 3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3697 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 3698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 3699 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 3700 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3701 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3703 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3705 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 3706 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3707 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 3708 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3709 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 3710 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3711 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 3712 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3713 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 3714 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3715 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 3716 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3717 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 3718 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3719 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 3720 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3721 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 3722 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3723 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 3724 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3725 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 3726 /* CRC32 instructions. */ 3727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3728 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 3729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3730 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 3731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3732 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 3733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3734 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3736 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 3737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3738 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 3739 3740 /* Privileged Access Never extension instructions. */ 3741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 3742 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 3743 3744 /* Virtualization Extension instructions. */ 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 3747 3748 /* Integer Divide Extension instructions. */ 3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3750 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3752 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 3753 3754 /* MP Extension instructions. */ 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 3756 3757 /* Speculation Barriers. */ 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 3761 3762 /* V7 instructions. */ 3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 3771 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 3772 3773 /* ARM V6T2 instructions. */ 3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3775 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3777 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3779 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3781 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 3782 3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3784 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3786 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 3787 3788 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3789 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 3790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3791 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3793 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3795 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 3796 3797 /* ARM Security extension instructions. */ 3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 3799 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 3800 3801 /* ARM V6K instructions. */ 3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3803 0xf57ff01f, 0xffffffff, "clrex"}, 3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3805 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3807 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3809 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3811 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3813 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3815 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 3816 3817 /* ARMv8.5-A instructions. */ 3818 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 3819 3820 /* ARM V6K NOP hints. */ 3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3822 0x0320f001, 0x0fffffff, "yield%c"}, 3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3824 0x0320f002, 0x0fffffff, "wfe%c"}, 3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3826 0x0320f003, 0x0fffffff, "wfi%c"}, 3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3828 0x0320f004, 0x0fffffff, "sev%c"}, 3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3830 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 3831 3832 /* ARM V6 instructions. */ 3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3834 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3836 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3838 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3840 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3842 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3844 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3846 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3848 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3850 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3852 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3854 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3856 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3858 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3860 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3862 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3864 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3866 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3868 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3870 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3872 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3874 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3876 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3878 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3880 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3882 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3884 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3886 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3888 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3890 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3892 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3894 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3896 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3898 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3900 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3902 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3904 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3906 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3908 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3910 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3912 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3914 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3916 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3918 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3920 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3922 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3924 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3926 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3928 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3930 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3932 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3934 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3936 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3938 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3940 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3942 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3944 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3946 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3948 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3950 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3952 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3954 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3956 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3958 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3960 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3962 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3964 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3966 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3968 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3970 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3972 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3974 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3976 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3978 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3980 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3982 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3984 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3986 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3988 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3990 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3992 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3994 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3996 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3998 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4000 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4002 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4004 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4006 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4008 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4010 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4012 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4014 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4016 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4018 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4020 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4022 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4024 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4026 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4028 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4030 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4032 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4034 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4036 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4038 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4040 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4042 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4044 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4046 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4048 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4050 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4052 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4054 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4056 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4058 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4060 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4062 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4064 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4066 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4068 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4070 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4072 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4074 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4076 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 4077 4078 /* V5J instruction. */ 4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 4080 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 4081 4082 /* V5 Instructions. */ 4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4084 0xe1200070, 0xfff000f0, 4085 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4087 0xfa000000, 0xfe000000, "blx\t%B"}, 4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4089 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4091 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 4092 4093 /* V5E "El Segundo" Instructions. */ 4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4095 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4097 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4099 0xf450f000, 0xfc70f000, "pld\t%a"}, 4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4101 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4103 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4105 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4107 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 4108 4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4110 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4112 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 4113 4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4115 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4117 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4119 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4121 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4122 4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4124 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4126 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4128 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4130 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 4131 4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4133 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4135 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 4136 4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4138 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4140 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4142 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4144 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 4145 4146 /* ARM Instructions. */ 4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4148 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 4149 4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4151 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4153 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4155 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4157 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4159 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4161 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 4162 4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4164 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4166 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4168 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4170 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 4171 4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4173 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4175 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4177 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4179 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 4180 4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4182 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4184 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4186 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 4187 4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4189 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4191 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4193 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 4194 4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4196 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4198 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4200 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 4201 4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4203 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4205 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4207 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 4208 4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4210 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4212 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4214 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 4215 4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4217 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4219 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4221 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 4222 4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4224 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4226 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4228 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 4229 4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4231 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4233 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4235 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 4236 4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 4238 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4240 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4242 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 4243 4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4245 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4247 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4249 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 4250 4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4252 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4254 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4256 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 4257 4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4259 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4261 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4263 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 4264 4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4266 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4268 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4270 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 4271 4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4273 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4275 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4277 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 4278 4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4280 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4282 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4284 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4286 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4288 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4290 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4292 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 4293 4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4295 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4297 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4299 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 4300 4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4302 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4304 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4306 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 4307 4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4309 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4311 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 4312 4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4314 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 4315 4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4317 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4319 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 4320 4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4322 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4324 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4326 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4328 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4330 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4332 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4334 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4336 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4338 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4340 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4342 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4344 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4346 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4348 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4350 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4352 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4354 0x092d0000, 0x0fff0000, "push%c\t%m"}, 4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4356 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4358 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4359 4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4361 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4363 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4365 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4367 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4369 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4371 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4373 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4375 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4377 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4379 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4381 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4383 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4385 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4387 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4389 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4391 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4393 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4395 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4397 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4398 4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4400 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4402 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 4403 4404 /* The rest. */ 4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 4406 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4408 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 4409 {ARM_FEATURE_CORE_LOW (0), 4410 0x00000000, 0x00000000, 0} 4411 }; 4412 4413 /* print_insn_thumb16 recognizes the following format control codes: 4414 4415 %S print Thumb register (bits 3..5 as high number if bit 6 set) 4416 %D print Thumb register (bits 0..2 as high number if bit 7 set) 4417 %<bitfield>I print bitfield as a signed decimal 4418 (top bit of range being the sign bit) 4419 %N print Thumb register mask (with LR) 4420 %O print Thumb register mask (with PC) 4421 %M print Thumb register mask 4422 %b print CZB's 6-bit unsigned branch destination 4423 %s print Thumb right-shift immediate (6..10; 0 == 32). 4424 %c print the condition code 4425 %C print the condition code, or "s" if not conditional 4426 %x print warning if conditional an not at end of IT block" 4427 %X print "\t; unpredictable <IT:code>" if conditional 4428 %I print IT instruction suffix and operands 4429 %W print Thumb Writeback indicator for LDMIA 4430 %<bitfield>r print bitfield as an ARM register 4431 %<bitfield>d print bitfield as a decimal 4432 %<bitfield>H print (bitfield * 2) as a decimal 4433 %<bitfield>W print (bitfield * 4) as a decimal 4434 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 4435 %<bitfield>B print Thumb branch destination (signed displacement) 4436 %<bitfield>c print bitfield as a condition code 4437 %<bitnum>'c print specified char iff bit is one 4438 %<bitnum>?ab print a if bit is one else print b. */ 4439 4440 static const struct opcode16 thumb_opcodes[] = 4441 { 4442 /* Thumb instructions. */ 4443 4444 /* ARMv8-M Security Extensions instructions. */ 4445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 4447 4448 /* ARM V8 instructions. */ 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 4451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 4452 4453 /* ARM V6K no-argument instructions. */ 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 4460 4461 /* ARM V6T2 instructions. */ 4462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4463 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 4464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4465 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 4467 4468 /* ARM V6. */ 4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 4480 4481 /* ARM V5 ISA extends Thumb. */ 4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4483 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 4484 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 4485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4486 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 4487 /* ARM V4T ISA (Thumb v1). */ 4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4489 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 4490 /* Format 4. */ 4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 4507 /* format 13 */ 4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 4510 /* format 5 */ 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 4515 /* format 14 */ 4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 4518 /* format 2 */ 4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4520 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4522 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4524 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4526 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 4527 /* format 8 */ 4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4529 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4531 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4533 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 4534 /* format 7 */ 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4536 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4538 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4539 /* format 1 */ 4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4542 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 4545 /* format 3 */ 4546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 4550 /* format 6 */ 4551 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4553 0x4800, 0xF800, 4554 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 4555 /* format 9 */ 4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4557 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4559 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4561 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4563 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 4564 /* format 10 */ 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4566 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4568 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 4569 /* format 11 */ 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4571 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4573 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 4574 /* format 12 */ 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4576 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4578 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 4579 /* format 15 */ 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 4582 /* format 17 */ 4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 4584 /* format 16 */ 4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 4587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 4588 /* format 18 */ 4589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 4590 4591 /* The E800 .. FFFF range is unconditionally redirected to the 4592 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 4593 are processed via that table. Thus, we can never encounter a 4594 bare "second half of BL/BLX(1)" instruction here. */ 4595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 4596 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 4597 }; 4598 4599 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 4600 We adopt the convention that hw1 is the high 16 bits of .value and 4601 .mask, hw2 the low 16 bits. 4602 4603 print_insn_thumb32 recognizes the following format control codes: 4604 4605 %% % 4606 4607 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 4608 %M print a modified 12-bit immediate (same location) 4609 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 4610 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 4611 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 4612 %S print a possibly-shifted Rm 4613 4614 %L print address for a ldrd/strd instruction 4615 %a print the address of a plain load/store 4616 %w print the width and signedness of a core load/store 4617 %m print register mask for ldm/stm 4618 %n print register mask for clrm 4619 4620 %E print the lsb and width fields of a bfc/bfi instruction 4621 %F print the lsb and width fields of a sbfx/ubfx instruction 4622 %G print a fallback offset for Branch Future instructions 4623 %W print an offset for BF instruction 4624 %Y print an offset for BFL instruction 4625 %Z print an offset for BFCSEL instruction 4626 %Q print an offset for Low Overhead Loop instructions 4627 %P print an offset for Low Overhead Loop end instructions 4628 %b print a conditional branch offset 4629 %B print an unconditional branch offset 4630 %s print the shift field of an SSAT instruction 4631 %R print the rotation field of an SXT instruction 4632 %U print barrier type. 4633 %P print address for pli instruction. 4634 %c print the condition code 4635 %x print warning if conditional an not at end of IT block" 4636 %X print "\t; unpredictable <IT:code>" if conditional 4637 4638 %<bitfield>d print bitfield in decimal 4639 %<bitfield>D print bitfield plus one in decimal 4640 %<bitfield>W print bitfield*4 in decimal 4641 %<bitfield>r print bitfield as an ARM register 4642 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 4643 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE 4644 %<bitfield>c print bitfield as a condition code 4645 4646 %<bitfield>'c print specified char iff bitfield is all ones 4647 %<bitfield>`c print specified char iff bitfield is all zeroes 4648 %<bitfield>?ab... select from array of values in big endian order 4649 4650 With one exception at the bottom (done because BL and BLX(1) need 4651 to come dead last), this table was machine-sorted first in 4652 decreasing order of number of bits set in the mask, then in 4653 increasing numeric order of mask, then in increasing numeric order 4654 of opcode. This order is not the clearest for a human reader, but 4655 is guaranteed never to catch a special-case bit pattern with a more 4656 general mask, which is important, because this instruction encoding 4657 makes heavy use of special-case bit patterns. */ 4658 static const struct opcode32 thumb32_opcodes[] = 4659 { 4660 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions 4661 instructions. */ 4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4663 0xf00fe001, 0xffffffff, "lctp%c"}, 4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4665 0xf02fc001, 0xfffff001, "le\t%P"}, 4666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4667 0xf00fc001, 0xfffff001, "le\tlr, %P"}, 4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4669 0xf01fc001, 0xfffff001, "letp\tlr, %P"}, 4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4671 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, 4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4673 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"}, 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4675 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4677 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"}, 4678 4679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4680 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, 4681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4682 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, 4683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4684 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"}, 4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4686 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, 4687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4688 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"}, 4689 4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4691 0xe89f0000, 0xffff2000, "clrm%c\t%n"}, 4692 4693 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 4694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4696 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4698 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4700 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 4701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4702 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 4703 4704 /* ARM V8.2 RAS extension instructions. */ 4705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 4706 0xf3af8010, 0xffffffff, "esb"}, 4707 4708 /* V8 instructions. */ 4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4710 0xf3af8005, 0xffffffff, "sevl%c.w"}, 4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4712 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4714 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4716 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4718 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4720 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4722 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4724 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4726 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4728 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4730 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4732 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4734 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4736 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4738 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4740 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 4741 4742 /* V8-R instructions. */ 4743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 4744 0xf3bf8f4c, 0xffffffff, "dfb%c"}, 4745 4746 /* CRC32 instructions. */ 4747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4748 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 4749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4750 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 4751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4752 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 4753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4754 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4756 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 4757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4758 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 4759 4760 /* Speculation Barriers. */ 4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 4764 4765 /* V7 instructions. */ 4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4774 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4776 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 4777 4778 /* Virtualization Extension instructions. */ 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 4780 /* We skip ERET as that is SUBS pc, lr, #0. */ 4781 4782 /* MP Extension instructions. */ 4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 4784 4785 /* Security extension instructions. */ 4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 4787 4788 /* ARMv8.5-A instructions. */ 4789 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 4790 4791 /* Instructions defined in the basic V6T2 set. */ 4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4798 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 4800 4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4802 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4804 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4806 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4808 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4810 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4812 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4814 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4816 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4818 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4820 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4822 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4824 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4826 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4828 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 4829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4830 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 4831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4832 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4834 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4836 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4838 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4840 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4842 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4844 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4846 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4848 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 4849 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4850 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4852 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4854 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4856 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4858 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4860 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4862 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4864 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4866 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4868 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4870 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4872 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4874 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4876 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4878 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4880 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4882 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4884 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4886 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4888 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4890 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4892 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4894 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4896 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4898 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4900 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4902 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4904 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4906 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4908 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4910 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4912 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4914 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4916 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4918 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4920 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4922 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4924 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4926 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4928 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4930 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4932 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4934 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4936 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4938 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4940 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4942 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4944 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4946 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4948 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4950 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4952 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4954 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4956 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 4957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4958 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4960 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4962 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4964 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4966 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4968 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4970 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4972 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4974 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4976 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4978 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4980 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4982 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4984 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4986 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4988 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4990 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4992 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4994 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4996 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4998 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5000 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5002 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5004 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5006 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5008 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5010 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5012 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5014 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5016 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5018 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5020 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5022 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5024 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5026 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5028 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5030 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5032 0xf810f000, 0xff70f000, "pld%c\t%a"}, 5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5034 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5036 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5038 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5040 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5042 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5044 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5046 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5048 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5050 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5052 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5054 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5056 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5058 0xfb100000, 0xfff000c0, 5059 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5061 0xfbc00080, 0xfff000c0, 5062 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5064 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5066 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5068 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5070 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5072 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 5073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5074 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5076 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 5077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5078 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5080 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5082 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5084 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 5085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5086 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5088 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 5089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5090 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5092 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5094 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5096 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5098 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 5099 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5100 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5102 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5104 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5106 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5108 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5110 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 5111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5112 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5114 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5116 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5118 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5120 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5122 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5124 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5126 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5128 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5130 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5132 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5134 0xe9400000, 0xff500000, 5135 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 5136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5137 0xe9500000, 0xff500000, 5138 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5140 0xe8600000, 0xff700000, 5141 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 5142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5143 0xe8700000, 0xff700000, 5144 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5146 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 5147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5148 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 5149 5150 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5152 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 5153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5154 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 5155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5156 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5158 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 5159 5160 /* These have been 32-bit since the invention of Thumb. */ 5161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5162 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5164 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 5165 5166 /* Fallback. */ 5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 5168 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 5169 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 5170 }; 5171 5172 static const char *const arm_conditional[] = 5173 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 5174 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 5175 5176 static const char *const arm_fp_const[] = 5177 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 5178 5179 static const char *const arm_shift[] = 5180 {"lsl", "lsr", "asr", "ror"}; 5181 5182 typedef struct 5183 { 5184 const char *name; 5185 const char *description; 5186 const char *reg_names[16]; 5187 } 5188 arm_regname; 5189 5190 static const arm_regname regnames[] = 5191 { 5192 { "reg-names-raw", N_("Select raw register names"), 5193 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 5194 { "reg-names-gcc", N_("Select register names used by GCC"), 5195 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5196 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 5197 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 5198 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 5199 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 5200 { "reg-names-apcs", N_("Select register names used in the APCS"), 5201 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5202 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 5203 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 5204 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 5205 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 5206 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } } 5207 }; 5208 5209 static const char *const iwmmxt_wwnames[] = 5210 {"b", "h", "w", "d"}; 5211 5212 static const char *const iwmmxt_wwssnames[] = 5213 {"b", "bus", "bc", "bss", 5214 "h", "hus", "hc", "hss", 5215 "w", "wus", "wc", "wss", 5216 "d", "dus", "dc", "dss" 5217 }; 5218 5219 static const char *const iwmmxt_regnames[] = 5220 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 5221 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 5222 }; 5223 5224 static const char *const iwmmxt_cregnames[] = 5225 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 5226 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 5227 }; 5228 5229 static const char *const vec_condnames[] = 5230 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le" 5231 }; 5232 5233 static const char *const mve_predicatenames[] = 5234 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "", 5235 "eee", "ee", "eet", "e", "ett", "et", "ete" 5236 }; 5237 5238 /* Names for 2-bit size field for mve vector isntructions. */ 5239 static const char *const mve_vec_sizename[] = 5240 { "8", "16", "32", "64"}; 5241 5242 /* Indicates whether we are processing a then predicate, 5243 else predicate or none at all. */ 5244 enum vpt_pred_state 5245 { 5246 PRED_NONE, 5247 PRED_THEN, 5248 PRED_ELSE 5249 }; 5250 5251 /* Information used to process a vpt block and subsequent instructions. */ 5252 struct vpt_block 5253 { 5254 /* Are we in a vpt block. */ 5255 bfd_boolean in_vpt_block; 5256 5257 /* Next predicate state if in vpt block. */ 5258 enum vpt_pred_state next_pred_state; 5259 5260 /* Mask from vpt/vpst instruction. */ 5261 long predicate_mask; 5262 5263 /* Instruction number in vpt block. */ 5264 long current_insn_num; 5265 5266 /* Number of instructions in vpt block.. */ 5267 long num_pred_insn; 5268 }; 5269 5270 static struct vpt_block vpt_block_state = 5271 { 5272 FALSE, 5273 PRED_NONE, 5274 0, 5275 0, 5276 0 5277 }; 5278 5279 /* Default to GCC register name set. */ 5280 static unsigned int regname_selected = 1; 5281 5282 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 5283 #define arm_regnames regnames[regname_selected].reg_names 5284 5285 static bfd_boolean force_thumb = FALSE; 5286 static uint16_t cde_coprocs = 0; 5287 5288 /* Current IT instruction state. This contains the same state as the IT 5289 bits in the CPSR. */ 5290 static unsigned int ifthen_state; 5291 /* IT state for the next instruction. */ 5292 static unsigned int ifthen_next_state; 5293 /* The address of the insn for which the IT state is valid. */ 5294 static bfd_vma ifthen_address; 5295 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 5296 /* Indicates that the current Conditional state is unconditional or outside 5297 an IT block. */ 5298 #define COND_UNCOND 16 5299 5300 5301 /* Functions. */ 5303 /* Extract the predicate mask for a VPT or VPST instruction. 5304 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */ 5305 5306 static long 5307 mve_extract_pred_mask (long given) 5308 { 5309 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13); 5310 } 5311 5312 /* Return the number of instructions in a MVE predicate block. */ 5313 static long 5314 num_instructions_vpt_block (long given) 5315 { 5316 long mask = mve_extract_pred_mask (given); 5317 if (mask == 0) 5318 return 0; 5319 5320 if (mask == 8) 5321 return 1; 5322 5323 if ((mask & 7) == 4) 5324 return 2; 5325 5326 if ((mask & 3) == 2) 5327 return 3; 5328 5329 if ((mask & 1) == 1) 5330 return 4; 5331 5332 return 0; 5333 } 5334 5335 static void 5336 mark_outside_vpt_block (void) 5337 { 5338 vpt_block_state.in_vpt_block = FALSE; 5339 vpt_block_state.next_pred_state = PRED_NONE; 5340 vpt_block_state.predicate_mask = 0; 5341 vpt_block_state.current_insn_num = 0; 5342 vpt_block_state.num_pred_insn = 0; 5343 } 5344 5345 static void 5346 mark_inside_vpt_block (long given) 5347 { 5348 vpt_block_state.in_vpt_block = TRUE; 5349 vpt_block_state.next_pred_state = PRED_THEN; 5350 vpt_block_state.predicate_mask = mve_extract_pred_mask (given); 5351 vpt_block_state.current_insn_num = 0; 5352 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given); 5353 assert (vpt_block_state.num_pred_insn >= 1); 5354 } 5355 5356 static enum vpt_pred_state 5357 invert_next_predicate_state (enum vpt_pred_state astate) 5358 { 5359 if (astate == PRED_THEN) 5360 return PRED_ELSE; 5361 else if (astate == PRED_ELSE) 5362 return PRED_THEN; 5363 else 5364 return PRED_NONE; 5365 } 5366 5367 static enum vpt_pred_state 5368 update_next_predicate_state (void) 5369 { 5370 long pred_mask = vpt_block_state.predicate_mask; 5371 long mask_for_insn = 0; 5372 5373 switch (vpt_block_state.current_insn_num) 5374 { 5375 case 1: 5376 mask_for_insn = 8; 5377 break; 5378 5379 case 2: 5380 mask_for_insn = 4; 5381 break; 5382 5383 case 3: 5384 mask_for_insn = 2; 5385 break; 5386 5387 case 4: 5388 return PRED_NONE; 5389 } 5390 5391 if (pred_mask & mask_for_insn) 5392 return invert_next_predicate_state (vpt_block_state.next_pred_state); 5393 else 5394 return vpt_block_state.next_pred_state; 5395 } 5396 5397 static void 5398 update_vpt_block_state (void) 5399 { 5400 vpt_block_state.current_insn_num++; 5401 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn) 5402 { 5403 /* No more instructions to process in vpt block. */ 5404 mark_outside_vpt_block (); 5405 return; 5406 } 5407 5408 vpt_block_state.next_pred_state = update_next_predicate_state (); 5409 } 5410 5411 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 5412 Returns pointer to following character of the format string and 5413 fills in *VALUEP and *WIDTHP with the extracted value and number of 5414 bits extracted. WIDTHP can be NULL. */ 5415 5416 static const char * 5417 arm_decode_bitfield (const char *ptr, 5418 unsigned long insn, 5419 unsigned long *valuep, 5420 int *widthp) 5421 { 5422 unsigned long value = 0; 5423 int width = 0; 5424 5425 do 5426 { 5427 int start, end; 5428 int bits; 5429 5430 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 5431 start = start * 10 + *ptr - '0'; 5432 if (*ptr == '-') 5433 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 5434 end = end * 10 + *ptr - '0'; 5435 else 5436 end = start; 5437 bits = end - start; 5438 if (bits < 0) 5439 abort (); 5440 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 5441 width += bits + 1; 5442 } 5443 while (*ptr++ == ','); 5444 *valuep = value; 5445 if (widthp) 5446 *widthp = width; 5447 return ptr - 1; 5448 } 5449 5450 static void 5451 arm_decode_shift (long given, fprintf_ftype func, void *stream, 5452 bfd_boolean print_shift) 5453 { 5454 func (stream, "%s", arm_regnames[given & 0xf]); 5455 5456 if ((given & 0xff0) != 0) 5457 { 5458 if ((given & 0x10) == 0) 5459 { 5460 int amount = (given & 0xf80) >> 7; 5461 int shift = (given & 0x60) >> 5; 5462 5463 if (amount == 0) 5464 { 5465 if (shift == 3) 5466 { 5467 func (stream, ", rrx"); 5468 return; 5469 } 5470 5471 amount = 32; 5472 } 5473 5474 if (print_shift) 5475 func (stream, ", %s #%d", arm_shift[shift], amount); 5476 else 5477 func (stream, ", #%d", amount); 5478 } 5479 else if ((given & 0x80) == 0x80) 5480 func (stream, "\t; <illegal shifter operand>"); 5481 else if (print_shift) 5482 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 5483 arm_regnames[(given & 0xf00) >> 8]); 5484 else 5485 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 5486 } 5487 } 5488 5489 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */ 5490 5491 static bfd_boolean 5492 is_mve_okay_in_it (enum mve_instructions matched_insn) 5493 { 5494 switch (matched_insn) 5495 { 5496 case MVE_VMOV_GP_TO_VEC_LANE: 5497 case MVE_VMOV2_VEC_LANE_TO_GP: 5498 case MVE_VMOV2_GP_TO_VEC_LANE: 5499 case MVE_VMOV_VEC_LANE_TO_GP: 5500 case MVE_LSLL: 5501 case MVE_LSLLI: 5502 case MVE_LSRL: 5503 case MVE_ASRL: 5504 case MVE_ASRLI: 5505 case MVE_SQRSHRL: 5506 case MVE_SQRSHR: 5507 case MVE_UQRSHL: 5508 case MVE_UQRSHLL: 5509 case MVE_UQSHL: 5510 case MVE_UQSHLL: 5511 case MVE_URSHRL: 5512 case MVE_URSHR: 5513 case MVE_SRSHRL: 5514 case MVE_SRSHR: 5515 case MVE_SQSHLL: 5516 case MVE_SQSHL: 5517 return TRUE; 5518 default: 5519 return FALSE; 5520 } 5521 } 5522 5523 static bfd_boolean 5524 is_mve_architecture (struct disassemble_info *info) 5525 { 5526 struct arm_private_data *private_data = info->private_data; 5527 arm_feature_set allowed_arches = private_data->features; 5528 5529 arm_feature_set arm_ext_v8_1m_main 5530 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 5531 5532 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 5533 && !ARM_CPU_IS_ANY (allowed_arches)) 5534 return TRUE; 5535 else 5536 return FALSE; 5537 } 5538 5539 static bfd_boolean 5540 is_vpt_instruction (long given) 5541 { 5542 5543 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */ 5544 if ((given & 0x0040e000) == 0) 5545 return FALSE; 5546 5547 /* VPT floating point T1 variant. */ 5548 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1)) 5549 /* VPT floating point T2 variant. */ 5550 || ((given & 0xefb10f50) == 0xee310f40) 5551 /* VPT vector T1 variant. */ 5552 || ((given & 0xff811f51) == 0xfe010f00) 5553 /* VPT vector T2 variant. */ 5554 || ((given & 0xff811f51) == 0xfe010f01 5555 && ((given & 0x300000) != 0x300000)) 5556 /* VPT vector T3 variant. */ 5557 || ((given & 0xff811f50) == 0xfe011f00) 5558 /* VPT vector T4 variant. */ 5559 || ((given & 0xff811f70) == 0xfe010f40) 5560 /* VPT vector T5 variant. */ 5561 || ((given & 0xff811f70) == 0xfe010f60) 5562 /* VPT vector T6 variant. */ 5563 || ((given & 0xff811f50) == 0xfe011f40) 5564 /* VPST vector T variant. */ 5565 || ((given & 0xffbf1fff) == 0xfe310f4d)) 5566 return TRUE; 5567 else 5568 return FALSE; 5569 } 5570 5571 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START 5572 and ending bitfield = END. END must be greater than START. */ 5573 5574 static unsigned long 5575 arm_decode_field (unsigned long given, unsigned int start, unsigned int end) 5576 { 5577 int bits = end - start; 5578 5579 if (bits < 0) 5580 abort (); 5581 5582 return ((given >> start) & ((2ul << bits) - 1)); 5583 } 5584 5585 /* Decode a bitfield from opcode GIVEN, with multiple bitfields: 5586 START:END and START2:END2. END/END2 must be greater than 5587 START/START2. */ 5588 5589 static unsigned long 5590 arm_decode_field_multiple (unsigned long given, unsigned int start, 5591 unsigned int end, unsigned int start2, 5592 unsigned int end2) 5593 { 5594 int bits = end - start; 5595 int bits2 = end2 - start2; 5596 unsigned long value = 0; 5597 int width = 0; 5598 5599 if (bits2 < 0) 5600 abort (); 5601 5602 value = arm_decode_field (given, start, end); 5603 width += bits + 1; 5604 5605 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width; 5606 return value; 5607 } 5608 5609 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN. 5610 This helps us decode instructions that change mnemonic depending on specific 5611 operand values/encodings. */ 5612 5613 static bfd_boolean 5614 is_mve_encoding_conflict (unsigned long given, 5615 enum mve_instructions matched_insn) 5616 { 5617 switch (matched_insn) 5618 { 5619 case MVE_VPST: 5620 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5621 return TRUE; 5622 else 5623 return FALSE; 5624 5625 case MVE_VPT_FP_T1: 5626 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5627 return TRUE; 5628 if ((arm_decode_field (given, 12, 12) == 0) 5629 && (arm_decode_field (given, 0, 0) == 1)) 5630 return TRUE; 5631 return FALSE; 5632 5633 case MVE_VPT_FP_T2: 5634 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5635 return TRUE; 5636 if (arm_decode_field (given, 0, 3) == 0xd) 5637 return TRUE; 5638 return FALSE; 5639 5640 case MVE_VPT_VEC_T1: 5641 case MVE_VPT_VEC_T2: 5642 case MVE_VPT_VEC_T3: 5643 case MVE_VPT_VEC_T4: 5644 case MVE_VPT_VEC_T5: 5645 case MVE_VPT_VEC_T6: 5646 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5647 return TRUE; 5648 if (arm_decode_field (given, 20, 21) == 3) 5649 return TRUE; 5650 return FALSE; 5651 5652 case MVE_VCMP_FP_T1: 5653 if ((arm_decode_field (given, 12, 12) == 0) 5654 && (arm_decode_field (given, 0, 0) == 1)) 5655 return TRUE; 5656 else 5657 return FALSE; 5658 5659 case MVE_VCMP_FP_T2: 5660 if (arm_decode_field (given, 0, 3) == 0xd) 5661 return TRUE; 5662 else 5663 return FALSE; 5664 5665 case MVE_VQADD_T2: 5666 case MVE_VQSUB_T2: 5667 case MVE_VMUL_VEC_T2: 5668 case MVE_VMULH: 5669 case MVE_VRMULH: 5670 case MVE_VMLA: 5671 case MVE_VMAX: 5672 case MVE_VMIN: 5673 case MVE_VBRSR: 5674 case MVE_VADD_VEC_T2: 5675 case MVE_VSUB_VEC_T2: 5676 case MVE_VABAV: 5677 case MVE_VQRSHL_T1: 5678 case MVE_VQSHL_T4: 5679 case MVE_VRSHL_T1: 5680 case MVE_VSHL_T3: 5681 case MVE_VCADD_VEC: 5682 case MVE_VHCADD: 5683 case MVE_VDDUP: 5684 case MVE_VIDUP: 5685 case MVE_VQRDMLADH: 5686 case MVE_VQDMLAH: 5687 case MVE_VQRDMLAH: 5688 case MVE_VQDMLASH: 5689 case MVE_VQRDMLASH: 5690 case MVE_VQDMLSDH: 5691 case MVE_VQRDMLSDH: 5692 case MVE_VQDMULH_T3: 5693 case MVE_VQRDMULH_T4: 5694 case MVE_VQDMLADH: 5695 case MVE_VMLAS: 5696 case MVE_VMULL_INT: 5697 case MVE_VHADD_T2: 5698 case MVE_VHSUB_T2: 5699 case MVE_VCMP_VEC_T1: 5700 case MVE_VCMP_VEC_T2: 5701 case MVE_VCMP_VEC_T3: 5702 case MVE_VCMP_VEC_T4: 5703 case MVE_VCMP_VEC_T5: 5704 case MVE_VCMP_VEC_T6: 5705 if (arm_decode_field (given, 20, 21) == 3) 5706 return TRUE; 5707 else 5708 return FALSE; 5709 5710 case MVE_VLD2: 5711 case MVE_VLD4: 5712 case MVE_VST2: 5713 case MVE_VST4: 5714 if (arm_decode_field (given, 7, 8) == 3) 5715 return TRUE; 5716 else 5717 return FALSE; 5718 5719 case MVE_VSTRB_T1: 5720 case MVE_VSTRH_T2: 5721 if ((arm_decode_field (given, 24, 24) == 0) 5722 && (arm_decode_field (given, 21, 21) == 0)) 5723 { 5724 return TRUE; 5725 } 5726 else if ((arm_decode_field (given, 7, 8) == 3)) 5727 return TRUE; 5728 else 5729 return FALSE; 5730 5731 case MVE_VSTRB_T5: 5732 case MVE_VSTRH_T6: 5733 case MVE_VSTRW_T7: 5734 if ((arm_decode_field (given, 24, 24) == 0) 5735 && (arm_decode_field (given, 21, 21) == 0)) 5736 { 5737 return TRUE; 5738 } 5739 else 5740 return FALSE; 5741 5742 case MVE_VCVT_FP_FIX_VEC: 5743 return (arm_decode_field (given, 16, 21) & 0x38) == 0; 5744 5745 case MVE_VBIC_IMM: 5746 case MVE_VORR_IMM: 5747 { 5748 unsigned long cmode = arm_decode_field (given, 8, 11); 5749 5750 if ((cmode & 1) == 0) 5751 return TRUE; 5752 else if ((cmode & 0xc) == 0xc) 5753 return TRUE; 5754 else 5755 return FALSE; 5756 } 5757 5758 case MVE_VMVN_IMM: 5759 { 5760 unsigned long cmode = arm_decode_field (given, 8, 11); 5761 5762 if (cmode == 0xe) 5763 return TRUE; 5764 else if ((cmode & 0x9) == 1) 5765 return TRUE; 5766 else if ((cmode & 0xd) == 9) 5767 return TRUE; 5768 else 5769 return FALSE; 5770 } 5771 5772 case MVE_VMOV_IMM_TO_VEC: 5773 if ((arm_decode_field (given, 5, 5) == 1) 5774 && (arm_decode_field (given, 8, 11) != 0xe)) 5775 return TRUE; 5776 else 5777 return FALSE; 5778 5779 case MVE_VMOVL: 5780 { 5781 unsigned long size = arm_decode_field (given, 19, 20); 5782 if ((size == 0) || (size == 3)) 5783 return TRUE; 5784 else 5785 return FALSE; 5786 } 5787 5788 case MVE_VMAXA: 5789 case MVE_VMINA: 5790 case MVE_VMAXV: 5791 case MVE_VMAXAV: 5792 case MVE_VMINV: 5793 case MVE_VMINAV: 5794 case MVE_VQRSHL_T2: 5795 case MVE_VQSHL_T1: 5796 case MVE_VRSHL_T2: 5797 case MVE_VSHL_T2: 5798 case MVE_VSHLL_T2: 5799 case MVE_VADDV: 5800 case MVE_VMOVN: 5801 case MVE_VQMOVUN: 5802 case MVE_VQMOVN: 5803 if (arm_decode_field (given, 18, 19) == 3) 5804 return TRUE; 5805 else 5806 return FALSE; 5807 5808 case MVE_VMLSLDAV: 5809 case MVE_VRMLSLDAVH: 5810 case MVE_VMLALDAV: 5811 case MVE_VADDLV: 5812 if (arm_decode_field (given, 20, 22) == 7) 5813 return TRUE; 5814 else 5815 return FALSE; 5816 5817 case MVE_VRMLALDAVH: 5818 if ((arm_decode_field (given, 20, 22) & 6) == 6) 5819 return TRUE; 5820 else 5821 return FALSE; 5822 5823 case MVE_VDWDUP: 5824 case MVE_VIWDUP: 5825 if ((arm_decode_field (given, 20, 21) == 3) 5826 || (arm_decode_field (given, 1, 3) == 7)) 5827 return TRUE; 5828 else 5829 return FALSE; 5830 5831 5832 case MVE_VSHLL_T1: 5833 if (arm_decode_field (given, 16, 18) == 0) 5834 { 5835 unsigned long sz = arm_decode_field (given, 19, 20); 5836 5837 if ((sz == 1) || (sz == 2)) 5838 return TRUE; 5839 else 5840 return FALSE; 5841 } 5842 else 5843 return FALSE; 5844 5845 case MVE_VQSHL_T2: 5846 case MVE_VQSHLU_T3: 5847 case MVE_VRSHR: 5848 case MVE_VSHL_T1: 5849 case MVE_VSHR: 5850 case MVE_VSLI: 5851 case MVE_VSRI: 5852 if (arm_decode_field (given, 19, 21) == 0) 5853 return TRUE; 5854 else 5855 return FALSE; 5856 5857 case MVE_VCTP: 5858 if (arm_decode_field (given, 16, 19) == 0xf) 5859 return TRUE; 5860 else 5861 return FALSE; 5862 5863 case MVE_ASRLI: 5864 case MVE_ASRL: 5865 case MVE_LSLLI: 5866 case MVE_LSLL: 5867 case MVE_LSRL: 5868 case MVE_SQRSHRL: 5869 case MVE_SQSHLL: 5870 case MVE_SRSHRL: 5871 case MVE_UQRSHLL: 5872 case MVE_UQSHLL: 5873 case MVE_URSHRL: 5874 if (arm_decode_field (given, 9, 11) == 0x7) 5875 return TRUE; 5876 else 5877 return FALSE; 5878 5879 case MVE_CSINC: 5880 case MVE_CSINV: 5881 { 5882 unsigned long rm, rn; 5883 rm = arm_decode_field (given, 0, 3); 5884 rn = arm_decode_field (given, 16, 19); 5885 /* CSET/CSETM. */ 5886 if (rm == 0xf && rn == 0xf) 5887 return TRUE; 5888 /* CINC/CINV. */ 5889 else if (rn == rm && rn != 0xf) 5890 return TRUE; 5891 } 5892 /* Fall through. */ 5893 case MVE_CSEL: 5894 case MVE_CSNEG: 5895 if (arm_decode_field (given, 0, 3) == 0xd) 5896 return TRUE; 5897 /* CNEG. */ 5898 else if (matched_insn == MVE_CSNEG) 5899 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19)) 5900 return TRUE; 5901 return FALSE; 5902 5903 default: 5904 case MVE_VADD_FP_T1: 5905 case MVE_VADD_FP_T2: 5906 case MVE_VADD_VEC_T1: 5907 return FALSE; 5908 5909 } 5910 } 5911 5912 static void 5913 print_mve_vld_str_addr (struct disassemble_info *info, 5914 unsigned long given, 5915 enum mve_instructions matched_insn) 5916 { 5917 void *stream = info->stream; 5918 fprintf_ftype func = info->fprintf_func; 5919 5920 unsigned long p, w, gpr, imm, add, mod_imm; 5921 5922 imm = arm_decode_field (given, 0, 6); 5923 mod_imm = imm; 5924 5925 switch (matched_insn) 5926 { 5927 case MVE_VLDRB_T1: 5928 case MVE_VSTRB_T1: 5929 gpr = arm_decode_field (given, 16, 18); 5930 break; 5931 5932 case MVE_VLDRH_T2: 5933 case MVE_VSTRH_T2: 5934 gpr = arm_decode_field (given, 16, 18); 5935 mod_imm = imm << 1; 5936 break; 5937 5938 case MVE_VLDRH_T6: 5939 case MVE_VSTRH_T6: 5940 gpr = arm_decode_field (given, 16, 19); 5941 mod_imm = imm << 1; 5942 break; 5943 5944 case MVE_VLDRW_T7: 5945 case MVE_VSTRW_T7: 5946 gpr = arm_decode_field (given, 16, 19); 5947 mod_imm = imm << 2; 5948 break; 5949 5950 case MVE_VLDRB_T5: 5951 case MVE_VSTRB_T5: 5952 gpr = arm_decode_field (given, 16, 19); 5953 break; 5954 5955 default: 5956 return; 5957 } 5958 5959 p = arm_decode_field (given, 24, 24); 5960 w = arm_decode_field (given, 21, 21); 5961 5962 add = arm_decode_field (given, 23, 23); 5963 5964 char * add_sub; 5965 5966 /* Don't print anything for '+' as it is implied. */ 5967 if (add == 1) 5968 add_sub = ""; 5969 else 5970 add_sub = "-"; 5971 5972 if (p == 1) 5973 { 5974 /* Offset mode. */ 5975 if (w == 0) 5976 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm); 5977 /* Pre-indexed mode. */ 5978 else 5979 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm); 5980 } 5981 else if ((p == 0) && (w == 1)) 5982 /* Post-index mode. */ 5983 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm); 5984 } 5985 5986 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN. 5987 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why 5988 this encoding is undefined. */ 5989 5990 static bfd_boolean 5991 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn, 5992 enum mve_undefined *undefined_code) 5993 { 5994 *undefined_code = UNDEF_NONE; 5995 5996 switch (matched_insn) 5997 { 5998 case MVE_VDUP: 5999 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3) 6000 { 6001 *undefined_code = UNDEF_SIZE_3; 6002 return TRUE; 6003 } 6004 else 6005 return FALSE; 6006 6007 case MVE_VQADD_T1: 6008 case MVE_VQSUB_T1: 6009 case MVE_VMUL_VEC_T1: 6010 case MVE_VABD_VEC: 6011 case MVE_VADD_VEC_T1: 6012 case MVE_VSUB_VEC_T1: 6013 case MVE_VQDMULH_T1: 6014 case MVE_VQRDMULH_T2: 6015 case MVE_VRHADD: 6016 case MVE_VHADD_T1: 6017 case MVE_VHSUB_T1: 6018 if (arm_decode_field (given, 20, 21) == 3) 6019 { 6020 *undefined_code = UNDEF_SIZE_3; 6021 return TRUE; 6022 } 6023 else 6024 return FALSE; 6025 6026 case MVE_VLDRB_T1: 6027 if (arm_decode_field (given, 7, 8) == 3) 6028 { 6029 *undefined_code = UNDEF_SIZE_3; 6030 return TRUE; 6031 } 6032 else 6033 return FALSE; 6034 6035 case MVE_VLDRH_T2: 6036 if (arm_decode_field (given, 7, 8) <= 1) 6037 { 6038 *undefined_code = UNDEF_SIZE_LE_1; 6039 return TRUE; 6040 } 6041 else 6042 return FALSE; 6043 6044 case MVE_VSTRB_T1: 6045 if ((arm_decode_field (given, 7, 8) == 0)) 6046 { 6047 *undefined_code = UNDEF_SIZE_0; 6048 return TRUE; 6049 } 6050 else 6051 return FALSE; 6052 6053 case MVE_VSTRH_T2: 6054 if ((arm_decode_field (given, 7, 8) <= 1)) 6055 { 6056 *undefined_code = UNDEF_SIZE_LE_1; 6057 return TRUE; 6058 } 6059 else 6060 return FALSE; 6061 6062 case MVE_VLDRB_GATHER_T1: 6063 if (arm_decode_field (given, 7, 8) == 3) 6064 { 6065 *undefined_code = UNDEF_SIZE_3; 6066 return TRUE; 6067 } 6068 else if ((arm_decode_field (given, 28, 28) == 0) 6069 && (arm_decode_field (given, 7, 8) == 0)) 6070 { 6071 *undefined_code = UNDEF_NOT_UNS_SIZE_0; 6072 return TRUE; 6073 } 6074 else 6075 return FALSE; 6076 6077 case MVE_VLDRH_GATHER_T2: 6078 if (arm_decode_field (given, 7, 8) == 3) 6079 { 6080 *undefined_code = UNDEF_SIZE_3; 6081 return TRUE; 6082 } 6083 else if ((arm_decode_field (given, 28, 28) == 0) 6084 && (arm_decode_field (given, 7, 8) == 1)) 6085 { 6086 *undefined_code = UNDEF_NOT_UNS_SIZE_1; 6087 return TRUE; 6088 } 6089 else if (arm_decode_field (given, 7, 8) == 0) 6090 { 6091 *undefined_code = UNDEF_SIZE_0; 6092 return TRUE; 6093 } 6094 else 6095 return FALSE; 6096 6097 case MVE_VLDRW_GATHER_T3: 6098 if (arm_decode_field (given, 7, 8) != 2) 6099 { 6100 *undefined_code = UNDEF_SIZE_NOT_2; 6101 return TRUE; 6102 } 6103 else if (arm_decode_field (given, 28, 28) == 0) 6104 { 6105 *undefined_code = UNDEF_NOT_UNSIGNED; 6106 return TRUE; 6107 } 6108 else 6109 return FALSE; 6110 6111 case MVE_VLDRD_GATHER_T4: 6112 if (arm_decode_field (given, 7, 8) != 3) 6113 { 6114 *undefined_code = UNDEF_SIZE_NOT_3; 6115 return TRUE; 6116 } 6117 else if (arm_decode_field (given, 28, 28) == 0) 6118 { 6119 *undefined_code = UNDEF_NOT_UNSIGNED; 6120 return TRUE; 6121 } 6122 else 6123 return FALSE; 6124 6125 case MVE_VSTRB_SCATTER_T1: 6126 if (arm_decode_field (given, 7, 8) == 3) 6127 { 6128 *undefined_code = UNDEF_SIZE_3; 6129 return TRUE; 6130 } 6131 else 6132 return FALSE; 6133 6134 case MVE_VSTRH_SCATTER_T2: 6135 { 6136 unsigned long size = arm_decode_field (given, 7, 8); 6137 if (size == 3) 6138 { 6139 *undefined_code = UNDEF_SIZE_3; 6140 return TRUE; 6141 } 6142 else if (size == 0) 6143 { 6144 *undefined_code = UNDEF_SIZE_0; 6145 return TRUE; 6146 } 6147 else 6148 return FALSE; 6149 } 6150 6151 case MVE_VSTRW_SCATTER_T3: 6152 if (arm_decode_field (given, 7, 8) != 2) 6153 { 6154 *undefined_code = UNDEF_SIZE_NOT_2; 6155 return TRUE; 6156 } 6157 else 6158 return FALSE; 6159 6160 case MVE_VSTRD_SCATTER_T4: 6161 if (arm_decode_field (given, 7, 8) != 3) 6162 { 6163 *undefined_code = UNDEF_SIZE_NOT_3; 6164 return TRUE; 6165 } 6166 else 6167 return FALSE; 6168 6169 case MVE_VCVT_FP_FIX_VEC: 6170 { 6171 unsigned long imm6 = arm_decode_field (given, 16, 21); 6172 if ((imm6 & 0x20) == 0) 6173 { 6174 *undefined_code = UNDEF_VCVT_IMM6; 6175 return TRUE; 6176 } 6177 6178 if ((arm_decode_field (given, 9, 9) == 0) 6179 && ((imm6 & 0x30) == 0x20)) 6180 { 6181 *undefined_code = UNDEF_VCVT_FSI_IMM6; 6182 return TRUE; 6183 } 6184 6185 return FALSE; 6186 } 6187 6188 case MVE_VNEG_FP: 6189 case MVE_VABS_FP: 6190 case MVE_VCVT_BETWEEN_FP_INT: 6191 case MVE_VCVT_FROM_FP_TO_INT: 6192 { 6193 unsigned long size = arm_decode_field (given, 18, 19); 6194 if (size == 0) 6195 { 6196 *undefined_code = UNDEF_SIZE_0; 6197 return TRUE; 6198 } 6199 else if (size == 3) 6200 { 6201 *undefined_code = UNDEF_SIZE_3; 6202 return TRUE; 6203 } 6204 else 6205 return FALSE; 6206 } 6207 6208 case MVE_VMOV_VEC_LANE_TO_GP: 6209 { 6210 unsigned long op1 = arm_decode_field (given, 21, 22); 6211 unsigned long op2 = arm_decode_field (given, 5, 6); 6212 unsigned long u = arm_decode_field (given, 23, 23); 6213 6214 if ((op2 == 0) && (u == 1)) 6215 { 6216 if ((op1 == 0) || (op1 == 1)) 6217 { 6218 *undefined_code = UNDEF_BAD_U_OP1_OP2; 6219 return TRUE; 6220 } 6221 else 6222 return FALSE; 6223 } 6224 else if (op2 == 2) 6225 { 6226 if ((op1 == 0) || (op1 == 1)) 6227 { 6228 *undefined_code = UNDEF_BAD_OP1_OP2; 6229 return TRUE; 6230 } 6231 else 6232 return FALSE; 6233 } 6234 6235 return FALSE; 6236 } 6237 6238 case MVE_VMOV_GP_TO_VEC_LANE: 6239 if (arm_decode_field (given, 5, 6) == 2) 6240 { 6241 unsigned long op1 = arm_decode_field (given, 21, 22); 6242 if ((op1 == 0) || (op1 == 1)) 6243 { 6244 *undefined_code = UNDEF_BAD_OP1_OP2; 6245 return TRUE; 6246 } 6247 else 6248 return FALSE; 6249 } 6250 else 6251 return FALSE; 6252 6253 case MVE_VMOV_VEC_TO_VEC: 6254 if ((arm_decode_field (given, 5, 5) == 1) 6255 || (arm_decode_field (given, 22, 22) == 1)) 6256 return TRUE; 6257 return FALSE; 6258 6259 case MVE_VMOV_IMM_TO_VEC: 6260 if (arm_decode_field (given, 5, 5) == 0) 6261 { 6262 unsigned long cmode = arm_decode_field (given, 8, 11); 6263 6264 if (((cmode & 9) == 1) || ((cmode & 5) == 1)) 6265 { 6266 *undefined_code = UNDEF_OP_0_BAD_CMODE; 6267 return TRUE; 6268 } 6269 else 6270 return FALSE; 6271 } 6272 else 6273 return FALSE; 6274 6275 case MVE_VSHLL_T2: 6276 case MVE_VMOVN: 6277 if (arm_decode_field (given, 18, 19) == 2) 6278 { 6279 *undefined_code = UNDEF_SIZE_2; 6280 return TRUE; 6281 } 6282 else 6283 return FALSE; 6284 6285 case MVE_VRMLALDAVH: 6286 case MVE_VMLADAV_T1: 6287 case MVE_VMLADAV_T2: 6288 case MVE_VMLALDAV: 6289 if ((arm_decode_field (given, 28, 28) == 1) 6290 && (arm_decode_field (given, 12, 12) == 1)) 6291 { 6292 *undefined_code = UNDEF_XCHG_UNS; 6293 return TRUE; 6294 } 6295 else 6296 return FALSE; 6297 6298 case MVE_VQSHRN: 6299 case MVE_VQSHRUN: 6300 case MVE_VSHLL_T1: 6301 case MVE_VSHRN: 6302 { 6303 unsigned long sz = arm_decode_field (given, 19, 20); 6304 if (sz == 1) 6305 return FALSE; 6306 else if ((sz & 2) == 2) 6307 return FALSE; 6308 else 6309 { 6310 *undefined_code = UNDEF_SIZE; 6311 return TRUE; 6312 } 6313 } 6314 break; 6315 6316 case MVE_VQSHL_T2: 6317 case MVE_VQSHLU_T3: 6318 case MVE_VRSHR: 6319 case MVE_VSHL_T1: 6320 case MVE_VSHR: 6321 case MVE_VSLI: 6322 case MVE_VSRI: 6323 { 6324 unsigned long sz = arm_decode_field (given, 19, 21); 6325 if ((sz & 7) == 1) 6326 return FALSE; 6327 else if ((sz & 6) == 2) 6328 return FALSE; 6329 else if ((sz & 4) == 4) 6330 return FALSE; 6331 else 6332 { 6333 *undefined_code = UNDEF_SIZE; 6334 return TRUE; 6335 } 6336 } 6337 6338 case MVE_VQRSHRN: 6339 case MVE_VQRSHRUN: 6340 if (arm_decode_field (given, 19, 20) == 0) 6341 { 6342 *undefined_code = UNDEF_SIZE_0; 6343 return TRUE; 6344 } 6345 else 6346 return FALSE; 6347 6348 case MVE_VABS_VEC: 6349 if (arm_decode_field (given, 18, 19) == 3) 6350 { 6351 *undefined_code = UNDEF_SIZE_3; 6352 return TRUE; 6353 } 6354 else 6355 return FALSE; 6356 6357 case MVE_VQNEG: 6358 case MVE_VQABS: 6359 case MVE_VNEG_VEC: 6360 case MVE_VCLS: 6361 case MVE_VCLZ: 6362 if (arm_decode_field (given, 18, 19) == 3) 6363 { 6364 *undefined_code = UNDEF_SIZE_3; 6365 return TRUE; 6366 } 6367 else 6368 return FALSE; 6369 6370 case MVE_VREV16: 6371 if (arm_decode_field (given, 18, 19) == 0) 6372 return FALSE; 6373 else 6374 { 6375 *undefined_code = UNDEF_SIZE_NOT_0; 6376 return TRUE; 6377 } 6378 6379 case MVE_VREV32: 6380 { 6381 unsigned long size = arm_decode_field (given, 18, 19); 6382 if ((size & 2) == 2) 6383 { 6384 *undefined_code = UNDEF_SIZE_2; 6385 return TRUE; 6386 } 6387 else 6388 return FALSE; 6389 } 6390 6391 case MVE_VREV64: 6392 if (arm_decode_field (given, 18, 19) != 3) 6393 return FALSE; 6394 else 6395 { 6396 *undefined_code = UNDEF_SIZE_3; 6397 return TRUE; 6398 } 6399 6400 default: 6401 return FALSE; 6402 } 6403 } 6404 6405 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN. 6406 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to 6407 why this encoding is unpredictable. */ 6408 6409 static bfd_boolean 6410 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, 6411 enum mve_unpredictable *unpredictable_code) 6412 { 6413 *unpredictable_code = UNPRED_NONE; 6414 6415 switch (matched_insn) 6416 { 6417 case MVE_VCMP_FP_T2: 6418 case MVE_VPT_FP_T2: 6419 if ((arm_decode_field (given, 12, 12) == 0) 6420 && (arm_decode_field (given, 5, 5) == 1)) 6421 { 6422 *unpredictable_code = UNPRED_FCA_0_FCB_1; 6423 return TRUE; 6424 } 6425 else 6426 return FALSE; 6427 6428 case MVE_VPT_VEC_T4: 6429 case MVE_VPT_VEC_T5: 6430 case MVE_VPT_VEC_T6: 6431 case MVE_VCMP_VEC_T4: 6432 case MVE_VCMP_VEC_T5: 6433 case MVE_VCMP_VEC_T6: 6434 if (arm_decode_field (given, 0, 3) == 0xd) 6435 { 6436 *unpredictable_code = UNPRED_R13; 6437 return TRUE; 6438 } 6439 else 6440 return FALSE; 6441 6442 case MVE_VDUP: 6443 { 6444 unsigned long gpr = arm_decode_field (given, 12, 15); 6445 if (gpr == 0xd) 6446 { 6447 *unpredictable_code = UNPRED_R13; 6448 return TRUE; 6449 } 6450 else if (gpr == 0xf) 6451 { 6452 *unpredictable_code = UNPRED_R15; 6453 return TRUE; 6454 } 6455 6456 return FALSE; 6457 } 6458 6459 case MVE_VQADD_T2: 6460 case MVE_VQSUB_T2: 6461 case MVE_VMUL_FP_T2: 6462 case MVE_VMUL_VEC_T2: 6463 case MVE_VMLA: 6464 case MVE_VBRSR: 6465 case MVE_VADD_FP_T2: 6466 case MVE_VSUB_FP_T2: 6467 case MVE_VADD_VEC_T2: 6468 case MVE_VSUB_VEC_T2: 6469 case MVE_VQRSHL_T2: 6470 case MVE_VQSHL_T1: 6471 case MVE_VRSHL_T2: 6472 case MVE_VSHL_T2: 6473 case MVE_VSHLC: 6474 case MVE_VQDMLAH: 6475 case MVE_VQRDMLAH: 6476 case MVE_VQDMLASH: 6477 case MVE_VQRDMLASH: 6478 case MVE_VQDMULH_T3: 6479 case MVE_VQRDMULH_T4: 6480 case MVE_VMLAS: 6481 case MVE_VFMA_FP_SCALAR: 6482 case MVE_VFMAS_FP_SCALAR: 6483 case MVE_VHADD_T2: 6484 case MVE_VHSUB_T2: 6485 { 6486 unsigned long gpr = arm_decode_field (given, 0, 3); 6487 if (gpr == 0xd) 6488 { 6489 *unpredictable_code = UNPRED_R13; 6490 return TRUE; 6491 } 6492 else if (gpr == 0xf) 6493 { 6494 *unpredictable_code = UNPRED_R15; 6495 return TRUE; 6496 } 6497 6498 return FALSE; 6499 } 6500 6501 case MVE_VLD2: 6502 case MVE_VST2: 6503 { 6504 unsigned long rn = arm_decode_field (given, 16, 19); 6505 6506 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6507 { 6508 *unpredictable_code = UNPRED_R13_AND_WB; 6509 return TRUE; 6510 } 6511 6512 if (rn == 0xf) 6513 { 6514 *unpredictable_code = UNPRED_R15; 6515 return TRUE; 6516 } 6517 6518 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6) 6519 { 6520 *unpredictable_code = UNPRED_Q_GT_6; 6521 return TRUE; 6522 } 6523 else 6524 return FALSE; 6525 } 6526 6527 case MVE_VLD4: 6528 case MVE_VST4: 6529 { 6530 unsigned long rn = arm_decode_field (given, 16, 19); 6531 6532 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6533 { 6534 *unpredictable_code = UNPRED_R13_AND_WB; 6535 return TRUE; 6536 } 6537 6538 if (rn == 0xf) 6539 { 6540 *unpredictable_code = UNPRED_R15; 6541 return TRUE; 6542 } 6543 6544 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4) 6545 { 6546 *unpredictable_code = UNPRED_Q_GT_4; 6547 return TRUE; 6548 } 6549 else 6550 return FALSE; 6551 } 6552 6553 case MVE_VLDRB_T5: 6554 case MVE_VLDRH_T6: 6555 case MVE_VLDRW_T7: 6556 case MVE_VSTRB_T5: 6557 case MVE_VSTRH_T6: 6558 case MVE_VSTRW_T7: 6559 { 6560 unsigned long rn = arm_decode_field (given, 16, 19); 6561 6562 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6563 { 6564 *unpredictable_code = UNPRED_R13_AND_WB; 6565 return TRUE; 6566 } 6567 else if (rn == 0xf) 6568 { 6569 *unpredictable_code = UNPRED_R15; 6570 return TRUE; 6571 } 6572 else 6573 return FALSE; 6574 } 6575 6576 case MVE_VLDRB_GATHER_T1: 6577 if (arm_decode_field (given, 0, 0) == 1) 6578 { 6579 *unpredictable_code = UNPRED_OS; 6580 return TRUE; 6581 } 6582 6583 /* fall through. */ 6584 /* To handle common code with T2-T4 variants. */ 6585 case MVE_VLDRH_GATHER_T2: 6586 case MVE_VLDRW_GATHER_T3: 6587 case MVE_VLDRD_GATHER_T4: 6588 { 6589 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6590 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6591 6592 if (qd == qm) 6593 { 6594 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6595 return TRUE; 6596 } 6597 6598 if (arm_decode_field (given, 16, 19) == 0xf) 6599 { 6600 *unpredictable_code = UNPRED_R15; 6601 return TRUE; 6602 } 6603 6604 return FALSE; 6605 } 6606 6607 case MVE_VLDRW_GATHER_T5: 6608 case MVE_VLDRD_GATHER_T6: 6609 { 6610 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6611 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7); 6612 6613 if (qd == qm) 6614 { 6615 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6616 return TRUE; 6617 } 6618 else 6619 return FALSE; 6620 } 6621 6622 case MVE_VSTRB_SCATTER_T1: 6623 if (arm_decode_field (given, 16, 19) == 0xf) 6624 { 6625 *unpredictable_code = UNPRED_R15; 6626 return TRUE; 6627 } 6628 else if (arm_decode_field (given, 0, 0) == 1) 6629 { 6630 *unpredictable_code = UNPRED_OS; 6631 return TRUE; 6632 } 6633 else 6634 return FALSE; 6635 6636 case MVE_VSTRH_SCATTER_T2: 6637 case MVE_VSTRW_SCATTER_T3: 6638 case MVE_VSTRD_SCATTER_T4: 6639 if (arm_decode_field (given, 16, 19) == 0xf) 6640 { 6641 *unpredictable_code = UNPRED_R15; 6642 return TRUE; 6643 } 6644 else 6645 return FALSE; 6646 6647 case MVE_VMOV2_VEC_LANE_TO_GP: 6648 case MVE_VMOV2_GP_TO_VEC_LANE: 6649 case MVE_VCVT_BETWEEN_FP_INT: 6650 case MVE_VCVT_FROM_FP_TO_INT: 6651 { 6652 unsigned long rt = arm_decode_field (given, 0, 3); 6653 unsigned long rt2 = arm_decode_field (given, 16, 19); 6654 6655 if ((rt == 0xd) || (rt2 == 0xd)) 6656 { 6657 *unpredictable_code = UNPRED_R13; 6658 return TRUE; 6659 } 6660 else if ((rt == 0xf) || (rt2 == 0xf)) 6661 { 6662 *unpredictable_code = UNPRED_R15; 6663 return TRUE; 6664 } 6665 else if (rt == rt2) 6666 { 6667 *unpredictable_code = UNPRED_GP_REGS_EQUAL; 6668 return TRUE; 6669 } 6670 6671 return FALSE; 6672 } 6673 6674 case MVE_VMAXV: 6675 case MVE_VMAXAV: 6676 case MVE_VMAXNMV_FP: 6677 case MVE_VMAXNMAV_FP: 6678 case MVE_VMINNMV_FP: 6679 case MVE_VMINNMAV_FP: 6680 case MVE_VMINV: 6681 case MVE_VMINAV: 6682 case MVE_VABAV: 6683 case MVE_VMOV_HFP_TO_GP: 6684 case MVE_VMOV_GP_TO_VEC_LANE: 6685 case MVE_VMOV_VEC_LANE_TO_GP: 6686 { 6687 unsigned long rda = arm_decode_field (given, 12, 15); 6688 if (rda == 0xd) 6689 { 6690 *unpredictable_code = UNPRED_R13; 6691 return TRUE; 6692 } 6693 else if (rda == 0xf) 6694 { 6695 *unpredictable_code = UNPRED_R15; 6696 return TRUE; 6697 } 6698 6699 return FALSE; 6700 } 6701 6702 case MVE_VMULL_INT: 6703 { 6704 unsigned long Qd; 6705 unsigned long Qm; 6706 unsigned long Qn; 6707 6708 if (arm_decode_field (given, 20, 21) == 2) 6709 { 6710 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6711 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6712 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6713 6714 if ((Qd == Qn) || (Qd == Qm)) 6715 { 6716 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6717 return TRUE; 6718 } 6719 else 6720 return FALSE; 6721 } 6722 else 6723 return FALSE; 6724 } 6725 6726 case MVE_VCMUL_FP: 6727 case MVE_VQDMULL_T1: 6728 { 6729 unsigned long Qd; 6730 unsigned long Qm; 6731 unsigned long Qn; 6732 6733 if (arm_decode_field (given, 28, 28) == 1) 6734 { 6735 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6736 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6737 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6738 6739 if ((Qd == Qn) || (Qd == Qm)) 6740 { 6741 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6742 return TRUE; 6743 } 6744 else 6745 return FALSE; 6746 } 6747 else 6748 return FALSE; 6749 } 6750 6751 case MVE_VQDMULL_T2: 6752 { 6753 unsigned long gpr = arm_decode_field (given, 0, 3); 6754 if (gpr == 0xd) 6755 { 6756 *unpredictable_code = UNPRED_R13; 6757 return TRUE; 6758 } 6759 else if (gpr == 0xf) 6760 { 6761 *unpredictable_code = UNPRED_R15; 6762 return TRUE; 6763 } 6764 6765 if (arm_decode_field (given, 28, 28) == 1) 6766 { 6767 unsigned long Qd 6768 = arm_decode_field_multiple (given, 13, 15, 22, 22); 6769 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6770 6771 if (Qd == Qn) 6772 { 6773 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6774 return TRUE; 6775 } 6776 else 6777 return FALSE; 6778 } 6779 6780 return FALSE; 6781 } 6782 6783 case MVE_VMLSLDAV: 6784 case MVE_VRMLSLDAVH: 6785 case MVE_VMLALDAV: 6786 case MVE_VADDLV: 6787 if (arm_decode_field (given, 20, 22) == 6) 6788 { 6789 *unpredictable_code = UNPRED_R13; 6790 return TRUE; 6791 } 6792 else 6793 return FALSE; 6794 6795 case MVE_VDWDUP: 6796 case MVE_VIWDUP: 6797 if (arm_decode_field (given, 1, 3) == 6) 6798 { 6799 *unpredictable_code = UNPRED_R13; 6800 return TRUE; 6801 } 6802 else 6803 return FALSE; 6804 6805 case MVE_VCADD_VEC: 6806 case MVE_VHCADD: 6807 { 6808 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6809 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6810 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2) 6811 { 6812 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6813 return TRUE; 6814 } 6815 else 6816 return FALSE; 6817 } 6818 6819 case MVE_VCADD_FP: 6820 { 6821 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6822 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6823 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1) 6824 { 6825 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6826 return TRUE; 6827 } 6828 else 6829 return FALSE; 6830 } 6831 6832 case MVE_VCMLA_FP: 6833 { 6834 unsigned long Qda; 6835 unsigned long Qm; 6836 unsigned long Qn; 6837 6838 if (arm_decode_field (given, 20, 20) == 1) 6839 { 6840 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22); 6841 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6842 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6843 6844 if ((Qda == Qn) || (Qda == Qm)) 6845 { 6846 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6847 return TRUE; 6848 } 6849 else 6850 return FALSE; 6851 } 6852 else 6853 return FALSE; 6854 6855 } 6856 6857 case MVE_VCTP: 6858 if (arm_decode_field (given, 16, 19) == 0xd) 6859 { 6860 *unpredictable_code = UNPRED_R13; 6861 return TRUE; 6862 } 6863 else 6864 return FALSE; 6865 6866 case MVE_VREV64: 6867 { 6868 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6869 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6); 6870 6871 if (qd == qm) 6872 { 6873 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6874 return TRUE; 6875 } 6876 else 6877 return FALSE; 6878 } 6879 6880 case MVE_LSLL: 6881 case MVE_LSLLI: 6882 case MVE_LSRL: 6883 case MVE_ASRL: 6884 case MVE_ASRLI: 6885 case MVE_UQSHLL: 6886 case MVE_UQRSHLL: 6887 case MVE_URSHRL: 6888 case MVE_SRSHRL: 6889 case MVE_SQSHLL: 6890 case MVE_SQRSHRL: 6891 { 6892 unsigned long gpr = arm_decode_field (given, 9, 11); 6893 gpr = ((gpr << 1) | 1); 6894 if (gpr == 0xd) 6895 { 6896 *unpredictable_code = UNPRED_R13; 6897 return TRUE; 6898 } 6899 else if (gpr == 0xf) 6900 { 6901 *unpredictable_code = UNPRED_R15; 6902 return TRUE; 6903 } 6904 6905 return FALSE; 6906 } 6907 6908 default: 6909 return FALSE; 6910 } 6911 } 6912 6913 static void 6914 print_mve_vmov_index (struct disassemble_info *info, unsigned long given) 6915 { 6916 unsigned long op1 = arm_decode_field (given, 21, 22); 6917 unsigned long op2 = arm_decode_field (given, 5, 6); 6918 unsigned long h = arm_decode_field (given, 16, 16); 6919 unsigned long index_operand, esize, targetBeat, idx; 6920 void *stream = info->stream; 6921 fprintf_ftype func = info->fprintf_func; 6922 6923 if ((op1 & 0x2) == 0x2) 6924 { 6925 index_operand = op2; 6926 esize = 8; 6927 } 6928 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) 6929 { 6930 index_operand = op2 >> 1; 6931 esize = 16; 6932 } 6933 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) 6934 { 6935 index_operand = 0; 6936 esize = 32; 6937 } 6938 else 6939 { 6940 func (stream, "<undefined index>"); 6941 return; 6942 } 6943 6944 targetBeat = (op1 & 0x1) | (h << 1); 6945 idx = index_operand + targetBeat * (32/esize); 6946 6947 func (stream, "%lu", idx); 6948 } 6949 6950 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits 6951 in length and integer of floating-point type. */ 6952 static void 6953 print_simd_imm8 (struct disassemble_info *info, unsigned long given, 6954 unsigned int ibit_loc, const struct mopcode32 *insn) 6955 { 6956 int bits = 0; 6957 int cmode = (given >> 8) & 0xf; 6958 int op = (given >> 5) & 0x1; 6959 unsigned long value = 0, hival = 0; 6960 unsigned shift; 6961 int size = 0; 6962 int isfloat = 0; 6963 void *stream = info->stream; 6964 fprintf_ftype func = info->fprintf_func; 6965 6966 /* On Neon the 'i' bit is at bit 24, on mve it is 6967 at bit 28. */ 6968 bits |= ((given >> ibit_loc) & 1) << 7; 6969 bits |= ((given >> 16) & 7) << 4; 6970 bits |= ((given >> 0) & 15) << 0; 6971 6972 if (cmode < 8) 6973 { 6974 shift = (cmode >> 1) & 3; 6975 value = (unsigned long) bits << (8 * shift); 6976 size = 32; 6977 } 6978 else if (cmode < 12) 6979 { 6980 shift = (cmode >> 1) & 1; 6981 value = (unsigned long) bits << (8 * shift); 6982 size = 16; 6983 } 6984 else if (cmode < 14) 6985 { 6986 shift = (cmode & 1) + 1; 6987 value = (unsigned long) bits << (8 * shift); 6988 value |= (1ul << (8 * shift)) - 1; 6989 size = 32; 6990 } 6991 else if (cmode == 14) 6992 { 6993 if (op) 6994 { 6995 /* Bit replication into bytes. */ 6996 int ix; 6997 unsigned long mask; 6998 6999 value = 0; 7000 hival = 0; 7001 for (ix = 7; ix >= 0; ix--) 7002 { 7003 mask = ((bits >> ix) & 1) ? 0xff : 0; 7004 if (ix <= 3) 7005 value = (value << 8) | mask; 7006 else 7007 hival = (hival << 8) | mask; 7008 } 7009 size = 64; 7010 } 7011 else 7012 { 7013 /* Byte replication. */ 7014 value = (unsigned long) bits; 7015 size = 8; 7016 } 7017 } 7018 else if (!op) 7019 { 7020 /* Floating point encoding. */ 7021 int tmp; 7022 7023 value = (unsigned long) (bits & 0x7f) << 19; 7024 value |= (unsigned long) (bits & 0x80) << 24; 7025 tmp = bits & 0x40 ? 0x3c : 0x40; 7026 value |= (unsigned long) tmp << 24; 7027 size = 32; 7028 isfloat = 1; 7029 } 7030 else 7031 { 7032 func (stream, "<illegal constant %.8x:%x:%x>", 7033 bits, cmode, op); 7034 size = 32; 7035 return; 7036 } 7037 7038 /* printU determines whether the immediate value should be printed as 7039 unsigned. */ 7040 unsigned printU = 0; 7041 switch (insn->mve_op) 7042 { 7043 default: 7044 break; 7045 /* We want this for instructions that don't have a 'signed' type. */ 7046 case MVE_VBIC_IMM: 7047 case MVE_VORR_IMM: 7048 case MVE_VMVN_IMM: 7049 case MVE_VMOV_IMM_TO_VEC: 7050 printU = 1; 7051 break; 7052 } 7053 switch (size) 7054 { 7055 case 8: 7056 func (stream, "#%ld\t; 0x%.2lx", value, value); 7057 break; 7058 7059 case 16: 7060 func (stream, 7061 printU 7062 ? "#%lu\t; 0x%.4lx" 7063 : "#%ld\t; 0x%.4lx", value, value); 7064 break; 7065 7066 case 32: 7067 if (isfloat) 7068 { 7069 unsigned char valbytes[4]; 7070 double fvalue; 7071 7072 /* Do this a byte at a time so we don't have to 7073 worry about the host's endianness. */ 7074 valbytes[0] = value & 0xff; 7075 valbytes[1] = (value >> 8) & 0xff; 7076 valbytes[2] = (value >> 16) & 0xff; 7077 valbytes[3] = (value >> 24) & 0xff; 7078 7079 floatformat_to_double 7080 (& floatformat_ieee_single_little, valbytes, 7081 & fvalue); 7082 7083 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 7084 value); 7085 } 7086 else 7087 func (stream, 7088 printU 7089 ? "#%lu\t; 0x%.8lx" 7090 : "#%ld\t; 0x%.8lx", 7091 (long) (((value & 0x80000000L) != 0) 7092 && !printU 7093 ? value | ~0xffffffffL : value), 7094 value); 7095 break; 7096 7097 case 64: 7098 func (stream, "#0x%.8lx%.8lx", hival, value); 7099 break; 7100 7101 default: 7102 abort (); 7103 } 7104 7105 } 7106 7107 static void 7108 print_mve_undefined (struct disassemble_info *info, 7109 enum mve_undefined undefined_code) 7110 { 7111 void *stream = info->stream; 7112 fprintf_ftype func = info->fprintf_func; 7113 7114 func (stream, "\t\tundefined instruction: "); 7115 7116 switch (undefined_code) 7117 { 7118 case UNDEF_SIZE: 7119 func (stream, "illegal size"); 7120 break; 7121 7122 case UNDEF_SIZE_0: 7123 func (stream, "size equals zero"); 7124 break; 7125 7126 case UNDEF_SIZE_2: 7127 func (stream, "size equals two"); 7128 break; 7129 7130 case UNDEF_SIZE_3: 7131 func (stream, "size equals three"); 7132 break; 7133 7134 case UNDEF_SIZE_LE_1: 7135 func (stream, "size <= 1"); 7136 break; 7137 7138 case UNDEF_SIZE_NOT_0: 7139 func (stream, "size not equal to 0"); 7140 break; 7141 7142 case UNDEF_SIZE_NOT_2: 7143 func (stream, "size not equal to 2"); 7144 break; 7145 7146 case UNDEF_SIZE_NOT_3: 7147 func (stream, "size not equal to 3"); 7148 break; 7149 7150 case UNDEF_NOT_UNS_SIZE_0: 7151 func (stream, "not unsigned and size = zero"); 7152 break; 7153 7154 case UNDEF_NOT_UNS_SIZE_1: 7155 func (stream, "not unsigned and size = one"); 7156 break; 7157 7158 case UNDEF_NOT_UNSIGNED: 7159 func (stream, "not unsigned"); 7160 break; 7161 7162 case UNDEF_VCVT_IMM6: 7163 func (stream, "invalid imm6"); 7164 break; 7165 7166 case UNDEF_VCVT_FSI_IMM6: 7167 func (stream, "fsi = 0 and invalid imm6"); 7168 break; 7169 7170 case UNDEF_BAD_OP1_OP2: 7171 func (stream, "bad size with op2 = 2 and op1 = 0 or 1"); 7172 break; 7173 7174 case UNDEF_BAD_U_OP1_OP2: 7175 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1"); 7176 break; 7177 7178 case UNDEF_OP_0_BAD_CMODE: 7179 func (stream, "op field equal 0 and bad cmode"); 7180 break; 7181 7182 case UNDEF_XCHG_UNS: 7183 func (stream, "exchange and unsigned together"); 7184 break; 7185 7186 case UNDEF_NONE: 7187 break; 7188 } 7189 7190 } 7191 7192 static void 7193 print_mve_unpredictable (struct disassemble_info *info, 7194 enum mve_unpredictable unpredict_code) 7195 { 7196 void *stream = info->stream; 7197 fprintf_ftype func = info->fprintf_func; 7198 7199 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION); 7200 7201 switch (unpredict_code) 7202 { 7203 case UNPRED_IT_BLOCK: 7204 func (stream, "mve instruction in it block"); 7205 break; 7206 7207 case UNPRED_FCA_0_FCB_1: 7208 func (stream, "condition bits, fca = 0 and fcb = 1"); 7209 break; 7210 7211 case UNPRED_R13: 7212 func (stream, "use of r13 (sp)"); 7213 break; 7214 7215 case UNPRED_R15: 7216 func (stream, "use of r15 (pc)"); 7217 break; 7218 7219 case UNPRED_Q_GT_4: 7220 func (stream, "start register block > r4"); 7221 break; 7222 7223 case UNPRED_Q_GT_6: 7224 func (stream, "start register block > r6"); 7225 break; 7226 7227 case UNPRED_R13_AND_WB: 7228 func (stream, "use of r13 and write back"); 7229 break; 7230 7231 case UNPRED_Q_REGS_EQUAL: 7232 func (stream, 7233 "same vector register used for destination and other operand"); 7234 break; 7235 7236 case UNPRED_OS: 7237 func (stream, "use of offset scaled"); 7238 break; 7239 7240 case UNPRED_GP_REGS_EQUAL: 7241 func (stream, "same general-purpose register used for both operands"); 7242 break; 7243 7244 case UNPRED_Q_REGS_EQ_AND_SIZE_1: 7245 func (stream, "use of identical q registers and size = 1"); 7246 break; 7247 7248 case UNPRED_Q_REGS_EQ_AND_SIZE_2: 7249 func (stream, "use of identical q registers and size = 1"); 7250 break; 7251 7252 case UNPRED_NONE: 7253 break; 7254 } 7255 } 7256 7257 /* Print register block operand for mve vld2/vld4/vst2/vld4. */ 7258 7259 static void 7260 print_mve_register_blocks (struct disassemble_info *info, 7261 unsigned long given, 7262 enum mve_instructions matched_insn) 7263 { 7264 void *stream = info->stream; 7265 fprintf_ftype func = info->fprintf_func; 7266 7267 unsigned long q_reg_start = arm_decode_field_multiple (given, 7268 13, 15, 7269 22, 22); 7270 switch (matched_insn) 7271 { 7272 case MVE_VLD2: 7273 case MVE_VST2: 7274 if (q_reg_start <= 6) 7275 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1); 7276 else 7277 func (stream, "<illegal reg q%ld>", q_reg_start); 7278 break; 7279 7280 case MVE_VLD4: 7281 case MVE_VST4: 7282 if (q_reg_start <= 4) 7283 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start, 7284 q_reg_start + 1, q_reg_start + 2, 7285 q_reg_start + 3); 7286 else 7287 func (stream, "<illegal reg q%ld>", q_reg_start); 7288 break; 7289 7290 default: 7291 break; 7292 } 7293 } 7294 7295 static void 7296 print_mve_rounding_mode (struct disassemble_info *info, 7297 unsigned long given, 7298 enum mve_instructions matched_insn) 7299 { 7300 void *stream = info->stream; 7301 fprintf_ftype func = info->fprintf_func; 7302 7303 switch (matched_insn) 7304 { 7305 case MVE_VCVT_FROM_FP_TO_INT: 7306 { 7307 switch (arm_decode_field (given, 8, 9)) 7308 { 7309 case 0: 7310 func (stream, "a"); 7311 break; 7312 7313 case 1: 7314 func (stream, "n"); 7315 break; 7316 7317 case 2: 7318 func (stream, "p"); 7319 break; 7320 7321 case 3: 7322 func (stream, "m"); 7323 break; 7324 7325 default: 7326 break; 7327 } 7328 } 7329 break; 7330 7331 case MVE_VRINT_FP: 7332 { 7333 switch (arm_decode_field (given, 7, 9)) 7334 { 7335 case 0: 7336 func (stream, "n"); 7337 break; 7338 7339 case 1: 7340 func (stream, "x"); 7341 break; 7342 7343 case 2: 7344 func (stream, "a"); 7345 break; 7346 7347 case 3: 7348 func (stream, "z"); 7349 break; 7350 7351 case 5: 7352 func (stream, "m"); 7353 break; 7354 7355 case 7: 7356 func (stream, "p"); 7357 7358 case 4: 7359 case 6: 7360 default: 7361 break; 7362 } 7363 } 7364 break; 7365 7366 default: 7367 break; 7368 } 7369 } 7370 7371 static void 7372 print_mve_vcvt_size (struct disassemble_info *info, 7373 unsigned long given, 7374 enum mve_instructions matched_insn) 7375 { 7376 unsigned long mode = 0; 7377 void *stream = info->stream; 7378 fprintf_ftype func = info->fprintf_func; 7379 7380 switch (matched_insn) 7381 { 7382 case MVE_VCVT_FP_FIX_VEC: 7383 { 7384 mode = (((given & 0x200) >> 7) 7385 | ((given & 0x10000000) >> 27) 7386 | ((given & 0x100) >> 8)); 7387 7388 switch (mode) 7389 { 7390 case 0: 7391 func (stream, "f16.s16"); 7392 break; 7393 7394 case 1: 7395 func (stream, "s16.f16"); 7396 break; 7397 7398 case 2: 7399 func (stream, "f16.u16"); 7400 break; 7401 7402 case 3: 7403 func (stream, "u16.f16"); 7404 break; 7405 7406 case 4: 7407 func (stream, "f32.s32"); 7408 break; 7409 7410 case 5: 7411 func (stream, "s32.f32"); 7412 break; 7413 7414 case 6: 7415 func (stream, "f32.u32"); 7416 break; 7417 7418 case 7: 7419 func (stream, "u32.f32"); 7420 break; 7421 7422 default: 7423 break; 7424 } 7425 break; 7426 } 7427 case MVE_VCVT_BETWEEN_FP_INT: 7428 { 7429 unsigned long size = arm_decode_field (given, 18, 19); 7430 unsigned long op = arm_decode_field (given, 7, 8); 7431 7432 if (size == 1) 7433 { 7434 switch (op) 7435 { 7436 case 0: 7437 func (stream, "f16.s16"); 7438 break; 7439 7440 case 1: 7441 func (stream, "f16.u16"); 7442 break; 7443 7444 case 2: 7445 func (stream, "s16.f16"); 7446 break; 7447 7448 case 3: 7449 func (stream, "u16.f16"); 7450 break; 7451 7452 default: 7453 break; 7454 } 7455 } 7456 else if (size == 2) 7457 { 7458 switch (op) 7459 { 7460 case 0: 7461 func (stream, "f32.s32"); 7462 break; 7463 7464 case 1: 7465 func (stream, "f32.u32"); 7466 break; 7467 7468 case 2: 7469 func (stream, "s32.f32"); 7470 break; 7471 7472 case 3: 7473 func (stream, "u32.f32"); 7474 break; 7475 } 7476 } 7477 } 7478 break; 7479 7480 case MVE_VCVT_FP_HALF_FP: 7481 { 7482 unsigned long op = arm_decode_field (given, 28, 28); 7483 if (op == 0) 7484 func (stream, "f16.f32"); 7485 else if (op == 1) 7486 func (stream, "f32.f16"); 7487 } 7488 break; 7489 7490 case MVE_VCVT_FROM_FP_TO_INT: 7491 { 7492 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19); 7493 7494 switch (size) 7495 { 7496 case 2: 7497 func (stream, "s16.f16"); 7498 break; 7499 7500 case 3: 7501 func (stream, "u16.f16"); 7502 break; 7503 7504 case 4: 7505 func (stream, "s32.f32"); 7506 break; 7507 7508 case 5: 7509 func (stream, "u32.f32"); 7510 break; 7511 7512 default: 7513 break; 7514 } 7515 } 7516 break; 7517 7518 default: 7519 break; 7520 } 7521 } 7522 7523 static void 7524 print_mve_rotate (struct disassemble_info *info, unsigned long rot, 7525 unsigned long rot_width) 7526 { 7527 void *stream = info->stream; 7528 fprintf_ftype func = info->fprintf_func; 7529 7530 if (rot_width == 1) 7531 { 7532 switch (rot) 7533 { 7534 case 0: 7535 func (stream, "90"); 7536 break; 7537 case 1: 7538 func (stream, "270"); 7539 break; 7540 default: 7541 break; 7542 } 7543 } 7544 else if (rot_width == 2) 7545 { 7546 switch (rot) 7547 { 7548 case 0: 7549 func (stream, "0"); 7550 break; 7551 case 1: 7552 func (stream, "90"); 7553 break; 7554 case 2: 7555 func (stream, "180"); 7556 break; 7557 case 3: 7558 func (stream, "270"); 7559 break; 7560 default: 7561 break; 7562 } 7563 } 7564 } 7565 7566 static void 7567 print_instruction_predicate (struct disassemble_info *info) 7568 { 7569 void *stream = info->stream; 7570 fprintf_ftype func = info->fprintf_func; 7571 7572 if (vpt_block_state.next_pred_state == PRED_THEN) 7573 func (stream, "t"); 7574 else if (vpt_block_state.next_pred_state == PRED_ELSE) 7575 func (stream, "e"); 7576 } 7577 7578 static void 7579 print_mve_size (struct disassemble_info *info, 7580 unsigned long size, 7581 enum mve_instructions matched_insn) 7582 { 7583 void *stream = info->stream; 7584 fprintf_ftype func = info->fprintf_func; 7585 7586 switch (matched_insn) 7587 { 7588 case MVE_VABAV: 7589 case MVE_VABD_VEC: 7590 case MVE_VABS_FP: 7591 case MVE_VABS_VEC: 7592 case MVE_VADD_VEC_T1: 7593 case MVE_VADD_VEC_T2: 7594 case MVE_VADDV: 7595 case MVE_VBRSR: 7596 case MVE_VCADD_VEC: 7597 case MVE_VCLS: 7598 case MVE_VCLZ: 7599 case MVE_VCMP_VEC_T1: 7600 case MVE_VCMP_VEC_T2: 7601 case MVE_VCMP_VEC_T3: 7602 case MVE_VCMP_VEC_T4: 7603 case MVE_VCMP_VEC_T5: 7604 case MVE_VCMP_VEC_T6: 7605 case MVE_VCTP: 7606 case MVE_VDDUP: 7607 case MVE_VDWDUP: 7608 case MVE_VHADD_T1: 7609 case MVE_VHADD_T2: 7610 case MVE_VHCADD: 7611 case MVE_VHSUB_T1: 7612 case MVE_VHSUB_T2: 7613 case MVE_VIDUP: 7614 case MVE_VIWDUP: 7615 case MVE_VLD2: 7616 case MVE_VLD4: 7617 case MVE_VLDRB_GATHER_T1: 7618 case MVE_VLDRH_GATHER_T2: 7619 case MVE_VLDRW_GATHER_T3: 7620 case MVE_VLDRD_GATHER_T4: 7621 case MVE_VLDRB_T1: 7622 case MVE_VLDRH_T2: 7623 case MVE_VMAX: 7624 case MVE_VMAXA: 7625 case MVE_VMAXV: 7626 case MVE_VMAXAV: 7627 case MVE_VMIN: 7628 case MVE_VMINA: 7629 case MVE_VMINV: 7630 case MVE_VMINAV: 7631 case MVE_VMLA: 7632 case MVE_VMLAS: 7633 case MVE_VMUL_VEC_T1: 7634 case MVE_VMUL_VEC_T2: 7635 case MVE_VMULH: 7636 case MVE_VRMULH: 7637 case MVE_VMULL_INT: 7638 case MVE_VNEG_FP: 7639 case MVE_VNEG_VEC: 7640 case MVE_VPT_VEC_T1: 7641 case MVE_VPT_VEC_T2: 7642 case MVE_VPT_VEC_T3: 7643 case MVE_VPT_VEC_T4: 7644 case MVE_VPT_VEC_T5: 7645 case MVE_VPT_VEC_T6: 7646 case MVE_VQABS: 7647 case MVE_VQADD_T1: 7648 case MVE_VQADD_T2: 7649 case MVE_VQDMLADH: 7650 case MVE_VQRDMLADH: 7651 case MVE_VQDMLAH: 7652 case MVE_VQRDMLAH: 7653 case MVE_VQDMLASH: 7654 case MVE_VQRDMLASH: 7655 case MVE_VQDMLSDH: 7656 case MVE_VQRDMLSDH: 7657 case MVE_VQDMULH_T1: 7658 case MVE_VQRDMULH_T2: 7659 case MVE_VQDMULH_T3: 7660 case MVE_VQRDMULH_T4: 7661 case MVE_VQNEG: 7662 case MVE_VQRSHL_T1: 7663 case MVE_VQRSHL_T2: 7664 case MVE_VQSHL_T1: 7665 case MVE_VQSHL_T4: 7666 case MVE_VQSUB_T1: 7667 case MVE_VQSUB_T2: 7668 case MVE_VREV32: 7669 case MVE_VREV64: 7670 case MVE_VRHADD: 7671 case MVE_VRINT_FP: 7672 case MVE_VRSHL_T1: 7673 case MVE_VRSHL_T2: 7674 case MVE_VSHL_T2: 7675 case MVE_VSHL_T3: 7676 case MVE_VSHLL_T2: 7677 case MVE_VST2: 7678 case MVE_VST4: 7679 case MVE_VSTRB_SCATTER_T1: 7680 case MVE_VSTRH_SCATTER_T2: 7681 case MVE_VSTRW_SCATTER_T3: 7682 case MVE_VSTRB_T1: 7683 case MVE_VSTRH_T2: 7684 case MVE_VSUB_VEC_T1: 7685 case MVE_VSUB_VEC_T2: 7686 if (size <= 3) 7687 func (stream, "%s", mve_vec_sizename[size]); 7688 else 7689 func (stream, "<undef size>"); 7690 break; 7691 7692 case MVE_VABD_FP: 7693 case MVE_VADD_FP_T1: 7694 case MVE_VADD_FP_T2: 7695 case MVE_VSUB_FP_T1: 7696 case MVE_VSUB_FP_T2: 7697 case MVE_VCMP_FP_T1: 7698 case MVE_VCMP_FP_T2: 7699 case MVE_VFMA_FP_SCALAR: 7700 case MVE_VFMA_FP: 7701 case MVE_VFMS_FP: 7702 case MVE_VFMAS_FP_SCALAR: 7703 case MVE_VMAXNM_FP: 7704 case MVE_VMAXNMA_FP: 7705 case MVE_VMAXNMV_FP: 7706 case MVE_VMAXNMAV_FP: 7707 case MVE_VMINNM_FP: 7708 case MVE_VMINNMA_FP: 7709 case MVE_VMINNMV_FP: 7710 case MVE_VMINNMAV_FP: 7711 case MVE_VMUL_FP_T1: 7712 case MVE_VMUL_FP_T2: 7713 case MVE_VPT_FP_T1: 7714 case MVE_VPT_FP_T2: 7715 if (size == 0) 7716 func (stream, "32"); 7717 else if (size == 1) 7718 func (stream, "16"); 7719 break; 7720 7721 case MVE_VCADD_FP: 7722 case MVE_VCMLA_FP: 7723 case MVE_VCMUL_FP: 7724 case MVE_VMLADAV_T1: 7725 case MVE_VMLALDAV: 7726 case MVE_VMLSDAV_T1: 7727 case MVE_VMLSLDAV: 7728 case MVE_VMOVN: 7729 case MVE_VQDMULL_T1: 7730 case MVE_VQDMULL_T2: 7731 case MVE_VQMOVN: 7732 case MVE_VQMOVUN: 7733 if (size == 0) 7734 func (stream, "16"); 7735 else if (size == 1) 7736 func (stream, "32"); 7737 break; 7738 7739 case MVE_VMOVL: 7740 if (size == 1) 7741 func (stream, "8"); 7742 else if (size == 2) 7743 func (stream, "16"); 7744 break; 7745 7746 case MVE_VDUP: 7747 switch (size) 7748 { 7749 case 0: 7750 func (stream, "32"); 7751 break; 7752 case 1: 7753 func (stream, "16"); 7754 break; 7755 case 2: 7756 func (stream, "8"); 7757 break; 7758 default: 7759 break; 7760 } 7761 break; 7762 7763 case MVE_VMOV_GP_TO_VEC_LANE: 7764 case MVE_VMOV_VEC_LANE_TO_GP: 7765 switch (size) 7766 { 7767 case 0: case 4: 7768 func (stream, "32"); 7769 break; 7770 7771 case 1: case 3: 7772 case 5: case 7: 7773 func (stream, "16"); 7774 break; 7775 7776 case 8: case 9: case 10: case 11: 7777 case 12: case 13: case 14: case 15: 7778 func (stream, "8"); 7779 break; 7780 7781 default: 7782 break; 7783 } 7784 break; 7785 7786 case MVE_VMOV_IMM_TO_VEC: 7787 switch (size) 7788 { 7789 case 0: case 4: case 8: 7790 case 12: case 24: case 26: 7791 func (stream, "i32"); 7792 break; 7793 case 16: case 20: 7794 func (stream, "i16"); 7795 break; 7796 case 28: 7797 func (stream, "i8"); 7798 break; 7799 case 29: 7800 func (stream, "i64"); 7801 break; 7802 case 30: 7803 func (stream, "f32"); 7804 break; 7805 default: 7806 break; 7807 } 7808 break; 7809 7810 case MVE_VMULL_POLY: 7811 if (size == 0) 7812 func (stream, "p8"); 7813 else if (size == 1) 7814 func (stream, "p16"); 7815 break; 7816 7817 case MVE_VMVN_IMM: 7818 switch (size) 7819 { 7820 case 0: case 2: case 4: 7821 case 6: case 12: case 13: 7822 func (stream, "32"); 7823 break; 7824 7825 case 8: case 10: 7826 func (stream, "16"); 7827 break; 7828 7829 default: 7830 break; 7831 } 7832 break; 7833 7834 case MVE_VBIC_IMM: 7835 case MVE_VORR_IMM: 7836 switch (size) 7837 { 7838 case 1: case 3: 7839 case 5: case 7: 7840 func (stream, "32"); 7841 break; 7842 7843 case 9: case 11: 7844 func (stream, "16"); 7845 break; 7846 7847 default: 7848 break; 7849 } 7850 break; 7851 7852 case MVE_VQSHRN: 7853 case MVE_VQSHRUN: 7854 case MVE_VQRSHRN: 7855 case MVE_VQRSHRUN: 7856 case MVE_VRSHRN: 7857 case MVE_VSHRN: 7858 { 7859 switch (size) 7860 { 7861 case 1: 7862 func (stream, "16"); 7863 break; 7864 7865 case 2: case 3: 7866 func (stream, "32"); 7867 break; 7868 7869 default: 7870 break; 7871 } 7872 } 7873 break; 7874 7875 case MVE_VQSHL_T2: 7876 case MVE_VQSHLU_T3: 7877 case MVE_VRSHR: 7878 case MVE_VSHL_T1: 7879 case MVE_VSHLL_T1: 7880 case MVE_VSHR: 7881 case MVE_VSLI: 7882 case MVE_VSRI: 7883 { 7884 switch (size) 7885 { 7886 case 1: 7887 func (stream, "8"); 7888 break; 7889 7890 case 2: case 3: 7891 func (stream, "16"); 7892 break; 7893 7894 case 4: case 5: case 6: case 7: 7895 func (stream, "32"); 7896 break; 7897 7898 default: 7899 break; 7900 } 7901 } 7902 break; 7903 7904 default: 7905 break; 7906 } 7907 } 7908 7909 static void 7910 print_mve_shift_n (struct disassemble_info *info, long given, 7911 enum mve_instructions matched_insn) 7912 { 7913 void *stream = info->stream; 7914 fprintf_ftype func = info->fprintf_func; 7915 7916 int startAt0 7917 = matched_insn == MVE_VQSHL_T2 7918 || matched_insn == MVE_VQSHLU_T3 7919 || matched_insn == MVE_VSHL_T1 7920 || matched_insn == MVE_VSHLL_T1 7921 || matched_insn == MVE_VSLI; 7922 7923 unsigned imm6 = (given & 0x3f0000) >> 16; 7924 7925 if (matched_insn == MVE_VSHLL_T1) 7926 imm6 &= 0x1f; 7927 7928 unsigned shiftAmount = 0; 7929 if ((imm6 & 0x20) != 0) 7930 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6; 7931 else if ((imm6 & 0x10) != 0) 7932 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6; 7933 else if ((imm6 & 0x08) != 0) 7934 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6; 7935 else 7936 print_mve_undefined (info, UNDEF_SIZE_0); 7937 7938 func (stream, "%u", shiftAmount); 7939 } 7940 7941 static void 7942 print_vec_condition (struct disassemble_info *info, long given, 7943 enum mve_instructions matched_insn) 7944 { 7945 void *stream = info->stream; 7946 fprintf_ftype func = info->fprintf_func; 7947 long vec_cond = 0; 7948 7949 switch (matched_insn) 7950 { 7951 case MVE_VPT_FP_T1: 7952 case MVE_VCMP_FP_T1: 7953 vec_cond = (((given & 0x1000) >> 10) 7954 | ((given & 1) << 1) 7955 | ((given & 0x0080) >> 7)); 7956 func (stream, "%s",vec_condnames[vec_cond]); 7957 break; 7958 7959 case MVE_VPT_FP_T2: 7960 case MVE_VCMP_FP_T2: 7961 vec_cond = (((given & 0x1000) >> 10) 7962 | ((given & 0x0020) >> 4) 7963 | ((given & 0x0080) >> 7)); 7964 func (stream, "%s",vec_condnames[vec_cond]); 7965 break; 7966 7967 case MVE_VPT_VEC_T1: 7968 case MVE_VCMP_VEC_T1: 7969 vec_cond = (given & 0x0080) >> 7; 7970 func (stream, "%s",vec_condnames[vec_cond]); 7971 break; 7972 7973 case MVE_VPT_VEC_T2: 7974 case MVE_VCMP_VEC_T2: 7975 vec_cond = 2 | ((given & 0x0080) >> 7); 7976 func (stream, "%s",vec_condnames[vec_cond]); 7977 break; 7978 7979 case MVE_VPT_VEC_T3: 7980 case MVE_VCMP_VEC_T3: 7981 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7); 7982 func (stream, "%s",vec_condnames[vec_cond]); 7983 break; 7984 7985 case MVE_VPT_VEC_T4: 7986 case MVE_VCMP_VEC_T4: 7987 vec_cond = (given & 0x0080) >> 7; 7988 func (stream, "%s",vec_condnames[vec_cond]); 7989 break; 7990 7991 case MVE_VPT_VEC_T5: 7992 case MVE_VCMP_VEC_T5: 7993 vec_cond = 2 | ((given & 0x0080) >> 7); 7994 func (stream, "%s",vec_condnames[vec_cond]); 7995 break; 7996 7997 case MVE_VPT_VEC_T6: 7998 case MVE_VCMP_VEC_T6: 7999 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7); 8000 func (stream, "%s",vec_condnames[vec_cond]); 8001 break; 8002 8003 case MVE_NONE: 8004 case MVE_VPST: 8005 default: 8006 break; 8007 } 8008 } 8009 8010 #define W_BIT 21 8011 #define I_BIT 22 8012 #define U_BIT 23 8013 #define P_BIT 24 8014 8015 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 8016 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 8017 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 8018 #define PRE_BIT_SET (given & (1 << P_BIT)) 8019 8020 8021 /* Print one coprocessor instruction on INFO->STREAM. 8022 Return TRUE if the instuction matched, FALSE if this is not a 8023 recognised coprocessor instruction. */ 8024 8025 static bfd_boolean 8026 print_insn_coprocessor_1 (const struct sopcode32 *opcodes, 8027 bfd_vma pc, 8028 struct disassemble_info *info, 8029 long given, 8030 bfd_boolean thumb) 8031 { 8032 const struct sopcode32 *insn; 8033 void *stream = info->stream; 8034 fprintf_ftype func = info->fprintf_func; 8035 unsigned long mask; 8036 unsigned long value = 0; 8037 int cond; 8038 int cp_num; 8039 struct arm_private_data *private_data = info->private_data; 8040 arm_feature_set allowed_arches = ARM_ARCH_NONE; 8041 arm_feature_set arm_ext_v8_1m_main = 8042 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 8043 8044 allowed_arches = private_data->features; 8045 8046 for (insn = opcodes; insn->assembler; insn++) 8047 { 8048 unsigned long u_reg = 16; 8049 bfd_boolean is_unpredictable = FALSE; 8050 signed long value_in_comment = 0; 8051 const char *c; 8052 8053 if (ARM_FEATURE_ZERO (insn->arch)) 8054 switch (insn->value) 8055 { 8056 case SENTINEL_IWMMXT_START: 8057 if (info->mach != bfd_mach_arm_XScale 8058 && info->mach != bfd_mach_arm_iWMMXt 8059 && info->mach != bfd_mach_arm_iWMMXt2) 8060 do 8061 insn++; 8062 while ((! ARM_FEATURE_ZERO (insn->arch)) 8063 && insn->value != SENTINEL_IWMMXT_END); 8064 continue; 8065 8066 case SENTINEL_IWMMXT_END: 8067 continue; 8068 8069 case SENTINEL_GENERIC_START: 8070 allowed_arches = private_data->features; 8071 continue; 8072 8073 default: 8074 abort (); 8075 } 8076 8077 mask = insn->mask; 8078 value = insn->value; 8079 cp_num = (given >> 8) & 0xf; 8080 8081 if (thumb) 8082 { 8083 /* The high 4 bits are 0xe for Arm conditional instructions, and 8084 0xe for arm unconditional instructions. The rest of the 8085 encoding is the same. */ 8086 mask |= 0xf0000000; 8087 value |= 0xe0000000; 8088 if (ifthen_state) 8089 cond = IFTHEN_COND; 8090 else 8091 cond = COND_UNCOND; 8092 } 8093 else 8094 { 8095 /* Only match unconditional instuctions against unconditional 8096 patterns. */ 8097 if ((given & 0xf0000000) == 0xf0000000) 8098 { 8099 mask |= 0xf0000000; 8100 cond = COND_UNCOND; 8101 } 8102 else 8103 { 8104 cond = (given >> 28) & 0xf; 8105 if (cond == 0xe) 8106 cond = COND_UNCOND; 8107 } 8108 } 8109 8110 if ((insn->isa == T32 && !thumb) 8111 || (insn->isa == ARM && thumb)) 8112 continue; 8113 8114 if ((given & mask) != value) 8115 continue; 8116 8117 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 8118 continue; 8119 8120 if (insn->value == 0xfe000010 /* mcr2 */ 8121 || insn->value == 0xfe100010 /* mrc2 */ 8122 || insn->value == 0xfc100000 /* ldc2 */ 8123 || insn->value == 0xfc000000) /* stc2 */ 8124 { 8125 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8126 is_unpredictable = TRUE; 8127 8128 /* Armv8.1-M Mainline FP & MVE instructions. */ 8129 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8130 && !ARM_CPU_IS_ANY (allowed_arches) 8131 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8132 continue; 8133 8134 } 8135 else if (insn->value == 0x0e000000 /* cdp */ 8136 || insn->value == 0xfe000000 /* cdp2 */ 8137 || insn->value == 0x0e000010 /* mcr */ 8138 || insn->value == 0x0e100010 /* mrc */ 8139 || insn->value == 0x0c100000 /* ldc */ 8140 || insn->value == 0x0c000000) /* stc */ 8141 { 8142 /* Floating-point instructions. */ 8143 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8144 continue; 8145 8146 /* Armv8.1-M Mainline FP & MVE instructions. */ 8147 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8148 && !ARM_CPU_IS_ANY (allowed_arches) 8149 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8150 continue; 8151 } 8152 else if ((insn->value == 0xec100f80 /* vldr (system register) */ 8153 || insn->value == 0xec000f80) /* vstr (system register) */ 8154 && arm_decode_field (given, 24, 24) == 0 8155 && arm_decode_field (given, 21, 21) == 0) 8156 /* If the P and W bits are both 0 then these encodings match the MVE 8157 VLDR and VSTR instructions, these are in a different table, so we 8158 don't let it match here. */ 8159 continue; 8160 8161 for (c = insn->assembler; *c; c++) 8162 { 8163 if (*c == '%') 8164 { 8165 const char mod = *++c; 8166 switch (mod) 8167 { 8168 case '%': 8169 func (stream, "%%"); 8170 break; 8171 8172 case 'A': 8173 case 'K': 8174 { 8175 int rn = (given >> 16) & 0xf; 8176 bfd_vma offset = given & 0xff; 8177 8178 if (mod == 'K') 8179 offset = given & 0x7f; 8180 8181 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 8182 8183 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 8184 { 8185 /* Not unindexed. The offset is scaled. */ 8186 if (cp_num == 9) 8187 /* vldr.16/vstr.16 will shift the address 8188 left by 1 bit only. */ 8189 offset = offset * 2; 8190 else 8191 offset = offset * 4; 8192 8193 if (NEGATIVE_BIT_SET) 8194 offset = - offset; 8195 if (rn != 15) 8196 value_in_comment = offset; 8197 } 8198 8199 if (PRE_BIT_SET) 8200 { 8201 if (offset) 8202 func (stream, ", #%d]%s", 8203 (int) offset, 8204 WRITEBACK_BIT_SET ? "!" : ""); 8205 else if (NEGATIVE_BIT_SET) 8206 func (stream, ", #-0]"); 8207 else 8208 func (stream, "]"); 8209 } 8210 else 8211 { 8212 func (stream, "]"); 8213 8214 if (WRITEBACK_BIT_SET) 8215 { 8216 if (offset) 8217 func (stream, ", #%d", (int) offset); 8218 else if (NEGATIVE_BIT_SET) 8219 func (stream, ", #-0"); 8220 } 8221 else 8222 { 8223 func (stream, ", {%s%d}", 8224 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 8225 (int) offset); 8226 value_in_comment = offset; 8227 } 8228 } 8229 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 8230 { 8231 func (stream, "\t; "); 8232 /* For unaligned PCs, apply off-by-alignment 8233 correction. */ 8234 info->print_address_func (offset + pc 8235 + info->bytes_per_chunk * 2 8236 - (pc & 3), 8237 info); 8238 } 8239 } 8240 break; 8241 8242 case 'B': 8243 { 8244 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 8245 int offset = (given >> 1) & 0x3f; 8246 8247 if (offset == 1) 8248 func (stream, "{d%d}", regno); 8249 else if (regno + offset > 32) 8250 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 8251 else 8252 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 8253 } 8254 break; 8255 8256 case 'C': 8257 { 8258 bfd_boolean single = ((given >> 8) & 1) == 0; 8259 char reg_prefix = single ? 's' : 'd'; 8260 int Dreg = (given >> 22) & 0x1; 8261 int Vdreg = (given >> 12) & 0xf; 8262 int reg = single ? ((Vdreg << 1) | Dreg) 8263 : ((Dreg << 4) | Vdreg); 8264 int num = (given >> (single ? 0 : 1)) & 0x7f; 8265 int maxreg = single ? 31 : 15; 8266 int topreg = reg + num - 1; 8267 8268 if (!num) 8269 func (stream, "{VPR}"); 8270 else if (num == 1) 8271 func (stream, "{%c%d, VPR}", reg_prefix, reg); 8272 else if (topreg > maxreg) 8273 func (stream, "{%c%d-<overflow reg d%d, VPR}", 8274 reg_prefix, reg, single ? topreg >> 1 : topreg); 8275 else 8276 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg, 8277 reg_prefix, topreg); 8278 } 8279 break; 8280 8281 case 'u': 8282 if (cond != COND_UNCOND) 8283 is_unpredictable = TRUE; 8284 8285 /* Fall through. */ 8286 case 'c': 8287 if (cond != COND_UNCOND && cp_num == 9) 8288 is_unpredictable = TRUE; 8289 8290 /* Fall through. */ 8291 case 'b': 8292 func (stream, "%s", arm_conditional[cond]); 8293 break; 8294 8295 case 'I': 8296 /* Print a Cirrus/DSP shift immediate. */ 8297 /* Immediates are 7bit signed ints with bits 0..3 in 8298 bits 0..3 of opcode and bits 4..6 in bits 5..7 8299 of opcode. */ 8300 { 8301 int imm; 8302 8303 imm = (given & 0xf) | ((given & 0xe0) >> 1); 8304 8305 /* Is ``imm'' a negative number? */ 8306 if (imm & 0x40) 8307 imm -= 0x80; 8308 8309 func (stream, "%d", imm); 8310 } 8311 8312 break; 8313 8314 case 'J': 8315 { 8316 unsigned long regno 8317 = arm_decode_field_multiple (given, 13, 15, 22, 22); 8318 8319 switch (regno) 8320 { 8321 case 0x1: 8322 func (stream, "FPSCR"); 8323 break; 8324 case 0x2: 8325 func (stream, "FPSCR_nzcvqc"); 8326 break; 8327 case 0xc: 8328 func (stream, "VPR"); 8329 break; 8330 case 0xd: 8331 func (stream, "P0"); 8332 break; 8333 case 0xe: 8334 func (stream, "FPCXTNS"); 8335 break; 8336 case 0xf: 8337 func (stream, "FPCXTS"); 8338 break; 8339 default: 8340 func (stream, "<invalid reg %lu>", regno); 8341 break; 8342 } 8343 } 8344 break; 8345 8346 case 'F': 8347 switch (given & 0x00408000) 8348 { 8349 case 0: 8350 func (stream, "4"); 8351 break; 8352 case 0x8000: 8353 func (stream, "1"); 8354 break; 8355 case 0x00400000: 8356 func (stream, "2"); 8357 break; 8358 default: 8359 func (stream, "3"); 8360 } 8361 break; 8362 8363 case 'P': 8364 switch (given & 0x00080080) 8365 { 8366 case 0: 8367 func (stream, "s"); 8368 break; 8369 case 0x80: 8370 func (stream, "d"); 8371 break; 8372 case 0x00080000: 8373 func (stream, "e"); 8374 break; 8375 default: 8376 func (stream, _("<illegal precision>")); 8377 break; 8378 } 8379 break; 8380 8381 case 'Q': 8382 switch (given & 0x00408000) 8383 { 8384 case 0: 8385 func (stream, "s"); 8386 break; 8387 case 0x8000: 8388 func (stream, "d"); 8389 break; 8390 case 0x00400000: 8391 func (stream, "e"); 8392 break; 8393 default: 8394 func (stream, "p"); 8395 break; 8396 } 8397 break; 8398 8399 case 'R': 8400 switch (given & 0x60) 8401 { 8402 case 0: 8403 break; 8404 case 0x20: 8405 func (stream, "p"); 8406 break; 8407 case 0x40: 8408 func (stream, "m"); 8409 break; 8410 default: 8411 func (stream, "z"); 8412 break; 8413 } 8414 break; 8415 8416 case '0': case '1': case '2': case '3': case '4': 8417 case '5': case '6': case '7': case '8': case '9': 8418 { 8419 int width; 8420 8421 c = arm_decode_bitfield (c, given, &value, &width); 8422 8423 switch (*c) 8424 { 8425 case 'R': 8426 if (value == 15) 8427 is_unpredictable = TRUE; 8428 /* Fall through. */ 8429 case 'r': 8430 if (c[1] == 'u') 8431 { 8432 /* Eat the 'u' character. */ 8433 ++ c; 8434 8435 if (u_reg == value) 8436 is_unpredictable = TRUE; 8437 u_reg = value; 8438 } 8439 func (stream, "%s", arm_regnames[value]); 8440 break; 8441 case 'V': 8442 if (given & (1 << 6)) 8443 goto Q; 8444 /* FALLTHROUGH */ 8445 case 'D': 8446 func (stream, "d%ld", value); 8447 break; 8448 case 'Q': 8449 Q: 8450 if (value & 1) 8451 func (stream, "<illegal reg q%ld.5>", value >> 1); 8452 else 8453 func (stream, "q%ld", value >> 1); 8454 break; 8455 case 'd': 8456 func (stream, "%ld", value); 8457 value_in_comment = value; 8458 break; 8459 case 'E': 8460 { 8461 /* Converts immediate 8 bit back to float value. */ 8462 unsigned floatVal = (value & 0x80) << 24 8463 | (value & 0x3F) << 19 8464 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 8465 8466 /* Quarter float have a maximum value of 31.0. 8467 Get floating point value multiplied by 1e7. 8468 The maximum value stays in limit of a 32-bit int. */ 8469 unsigned decVal = 8470 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 8471 (16 + (value & 0xF)); 8472 8473 if (!(decVal % 1000000)) 8474 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 8475 floatVal, value & 0x80 ? '-' : ' ', 8476 decVal / 10000000, 8477 decVal % 10000000 / 1000000); 8478 else if (!(decVal % 10000)) 8479 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 8480 floatVal, value & 0x80 ? '-' : ' ', 8481 decVal / 10000000, 8482 decVal % 10000000 / 10000); 8483 else 8484 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 8485 floatVal, value & 0x80 ? '-' : ' ', 8486 decVal / 10000000, decVal % 10000000); 8487 break; 8488 } 8489 case 'k': 8490 { 8491 int from = (given & (1 << 7)) ? 32 : 16; 8492 func (stream, "%ld", from - value); 8493 } 8494 break; 8495 8496 case 'f': 8497 if (value > 7) 8498 func (stream, "#%s", arm_fp_const[value & 7]); 8499 else 8500 func (stream, "f%ld", value); 8501 break; 8502 8503 case 'w': 8504 if (width == 2) 8505 func (stream, "%s", iwmmxt_wwnames[value]); 8506 else 8507 func (stream, "%s", iwmmxt_wwssnames[value]); 8508 break; 8509 8510 case 'g': 8511 func (stream, "%s", iwmmxt_regnames[value]); 8512 break; 8513 case 'G': 8514 func (stream, "%s", iwmmxt_cregnames[value]); 8515 break; 8516 8517 case 'x': 8518 func (stream, "0x%lx", (value & 0xffffffffUL)); 8519 break; 8520 8521 case 'c': 8522 switch (value) 8523 { 8524 case 0: 8525 func (stream, "eq"); 8526 break; 8527 8528 case 1: 8529 func (stream, "vs"); 8530 break; 8531 8532 case 2: 8533 func (stream, "ge"); 8534 break; 8535 8536 case 3: 8537 func (stream, "gt"); 8538 break; 8539 8540 default: 8541 func (stream, "??"); 8542 break; 8543 } 8544 break; 8545 8546 case '`': 8547 c++; 8548 if (value == 0) 8549 func (stream, "%c", *c); 8550 break; 8551 case '\'': 8552 c++; 8553 if (value == ((1ul << width) - 1)) 8554 func (stream, "%c", *c); 8555 break; 8556 case '?': 8557 func (stream, "%c", c[(1 << width) - (int) value]); 8558 c += 1 << width; 8559 break; 8560 default: 8561 abort (); 8562 } 8563 } 8564 break; 8565 8566 case 'y': 8567 case 'z': 8568 { 8569 int single = *c++ == 'y'; 8570 int regno; 8571 8572 switch (*c) 8573 { 8574 case '4': /* Sm pair */ 8575 case '0': /* Sm, Dm */ 8576 regno = given & 0x0000000f; 8577 if (single) 8578 { 8579 regno <<= 1; 8580 regno += (given >> 5) & 1; 8581 } 8582 else 8583 regno += ((given >> 5) & 1) << 4; 8584 break; 8585 8586 case '1': /* Sd, Dd */ 8587 regno = (given >> 12) & 0x0000000f; 8588 if (single) 8589 { 8590 regno <<= 1; 8591 regno += (given >> 22) & 1; 8592 } 8593 else 8594 regno += ((given >> 22) & 1) << 4; 8595 break; 8596 8597 case '2': /* Sn, Dn */ 8598 regno = (given >> 16) & 0x0000000f; 8599 if (single) 8600 { 8601 regno <<= 1; 8602 regno += (given >> 7) & 1; 8603 } 8604 else 8605 regno += ((given >> 7) & 1) << 4; 8606 break; 8607 8608 case '3': /* List */ 8609 func (stream, "{"); 8610 regno = (given >> 12) & 0x0000000f; 8611 if (single) 8612 { 8613 regno <<= 1; 8614 regno += (given >> 22) & 1; 8615 } 8616 else 8617 regno += ((given >> 22) & 1) << 4; 8618 break; 8619 8620 default: 8621 abort (); 8622 } 8623 8624 func (stream, "%c%d", single ? 's' : 'd', regno); 8625 8626 if (*c == '3') 8627 { 8628 int count = given & 0xff; 8629 8630 if (single == 0) 8631 count >>= 1; 8632 8633 if (--count) 8634 { 8635 func (stream, "-%c%d", 8636 single ? 's' : 'd', 8637 regno + count); 8638 } 8639 8640 func (stream, "}"); 8641 } 8642 else if (*c == '4') 8643 func (stream, ", %c%d", single ? 's' : 'd', 8644 regno + 1); 8645 } 8646 break; 8647 8648 case 'L': 8649 switch (given & 0x00400100) 8650 { 8651 case 0x00000000: func (stream, "b"); break; 8652 case 0x00400000: func (stream, "h"); break; 8653 case 0x00000100: func (stream, "w"); break; 8654 case 0x00400100: func (stream, "d"); break; 8655 default: 8656 break; 8657 } 8658 break; 8659 8660 case 'Z': 8661 { 8662 /* given (20, 23) | given (0, 3) */ 8663 value = ((given >> 16) & 0xf0) | (given & 0xf); 8664 func (stream, "%d", (int) value); 8665 } 8666 break; 8667 8668 case 'l': 8669 /* This is like the 'A' operator, except that if 8670 the width field "M" is zero, then the offset is 8671 *not* multiplied by four. */ 8672 { 8673 int offset = given & 0xff; 8674 int multiplier = (given & 0x00000100) ? 4 : 1; 8675 8676 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 8677 8678 if (multiplier > 1) 8679 { 8680 value_in_comment = offset * multiplier; 8681 if (NEGATIVE_BIT_SET) 8682 value_in_comment = - value_in_comment; 8683 } 8684 8685 if (offset) 8686 { 8687 if (PRE_BIT_SET) 8688 func (stream, ", #%s%d]%s", 8689 NEGATIVE_BIT_SET ? "-" : "", 8690 offset * multiplier, 8691 WRITEBACK_BIT_SET ? "!" : ""); 8692 else 8693 func (stream, "], #%s%d", 8694 NEGATIVE_BIT_SET ? "-" : "", 8695 offset * multiplier); 8696 } 8697 else 8698 func (stream, "]"); 8699 } 8700 break; 8701 8702 case 'r': 8703 { 8704 int imm4 = (given >> 4) & 0xf; 8705 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 8706 int ubit = ! NEGATIVE_BIT_SET; 8707 const char *rm = arm_regnames [given & 0xf]; 8708 const char *rn = arm_regnames [(given >> 16) & 0xf]; 8709 8710 switch (puw_bits) 8711 { 8712 case 1: 8713 case 3: 8714 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 8715 if (imm4) 8716 func (stream, ", lsl #%d", imm4); 8717 break; 8718 8719 case 4: 8720 case 5: 8721 case 6: 8722 case 7: 8723 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 8724 if (imm4 > 0) 8725 func (stream, ", lsl #%d", imm4); 8726 func (stream, "]"); 8727 if (puw_bits == 5 || puw_bits == 7) 8728 func (stream, "!"); 8729 break; 8730 8731 default: 8732 func (stream, "INVALID"); 8733 } 8734 } 8735 break; 8736 8737 case 'i': 8738 { 8739 long imm5; 8740 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 8741 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 8742 } 8743 break; 8744 8745 default: 8746 abort (); 8747 } 8748 } 8749 else 8750 func (stream, "%c", *c); 8751 } 8752 8753 if (value_in_comment > 32 || value_in_comment < -16) 8754 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 8755 8756 if (is_unpredictable) 8757 func (stream, UNPREDICTABLE_INSTRUCTION); 8758 8759 return TRUE; 8760 } 8761 return FALSE; 8762 } 8763 8764 static bfd_boolean 8765 print_insn_coprocessor (bfd_vma pc, 8766 struct disassemble_info *info, 8767 long given, 8768 bfd_boolean thumb) 8769 { 8770 return print_insn_coprocessor_1 (coprocessor_opcodes, 8771 pc, info, given, thumb); 8772 } 8773 8774 static bfd_boolean 8775 print_insn_generic_coprocessor (bfd_vma pc, 8776 struct disassemble_info *info, 8777 long given, 8778 bfd_boolean thumb) 8779 { 8780 return print_insn_coprocessor_1 (generic_coprocessor_opcodes, 8781 pc, info, given, thumb); 8782 } 8783 8784 /* Decodes and prints ARM addressing modes. Returns the offset 8785 used in the address, if any, if it is worthwhile printing the 8786 offset as a hexadecimal value in a comment at the end of the 8787 line of disassembly. */ 8788 8789 static signed long 8790 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 8791 { 8792 void *stream = info->stream; 8793 fprintf_ftype func = info->fprintf_func; 8794 bfd_vma offset = 0; 8795 8796 if (((given & 0x000f0000) == 0x000f0000) 8797 && ((given & 0x02000000) == 0)) 8798 { 8799 offset = given & 0xfff; 8800 8801 func (stream, "[pc"); 8802 8803 if (PRE_BIT_SET) 8804 { 8805 /* Pre-indexed. Elide offset of positive zero when 8806 non-writeback. */ 8807 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8808 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8809 8810 if (NEGATIVE_BIT_SET) 8811 offset = -offset; 8812 8813 offset += pc + 8; 8814 8815 /* Cope with the possibility of write-back 8816 being used. Probably a very dangerous thing 8817 for the programmer to do, but who are we to 8818 argue ? */ 8819 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 8820 } 8821 else /* Post indexed. */ 8822 { 8823 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8824 8825 /* Ie ignore the offset. */ 8826 offset = pc + 8; 8827 } 8828 8829 func (stream, "\t; "); 8830 info->print_address_func (offset, info); 8831 offset = 0; 8832 } 8833 else 8834 { 8835 func (stream, "[%s", 8836 arm_regnames[(given >> 16) & 0xf]); 8837 8838 if (PRE_BIT_SET) 8839 { 8840 if ((given & 0x02000000) == 0) 8841 { 8842 /* Elide offset of positive zero when non-writeback. */ 8843 offset = given & 0xfff; 8844 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8845 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8846 } 8847 else 8848 { 8849 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 8850 arm_decode_shift (given, func, stream, TRUE); 8851 } 8852 8853 func (stream, "]%s", 8854 WRITEBACK_BIT_SET ? "!" : ""); 8855 } 8856 else 8857 { 8858 if ((given & 0x02000000) == 0) 8859 { 8860 /* Always show offset. */ 8861 offset = given & 0xfff; 8862 func (stream, "], #%s%d", 8863 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8864 } 8865 else 8866 { 8867 func (stream, "], %s", 8868 NEGATIVE_BIT_SET ? "-" : ""); 8869 arm_decode_shift (given, func, stream, TRUE); 8870 } 8871 } 8872 if (NEGATIVE_BIT_SET) 8873 offset = -offset; 8874 } 8875 8876 return (signed long) offset; 8877 } 8878 8879 8880 /* Print one cde instruction on INFO->STREAM. 8881 Return TRUE if the instuction matched, FALSE if this is not a 8882 recognised cde instruction. */ 8883 static bfd_boolean 8884 print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb) 8885 { 8886 const struct cdeopcode32 *insn; 8887 void *stream = info->stream; 8888 fprintf_ftype func = info->fprintf_func; 8889 8890 if (thumb) 8891 { 8892 /* Manually extract the coprocessor code from a known point. 8893 This position is the same across all CDE instructions. */ 8894 for (insn = cde_opcodes; insn->assembler; insn++) 8895 { 8896 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask; 8897 uint16_t coproc_mask = 1 << coproc; 8898 if (! (coproc_mask & cde_coprocs)) 8899 continue; 8900 8901 if ((given & insn->mask) == insn->value) 8902 { 8903 bfd_boolean is_unpredictable = FALSE; 8904 const char *c; 8905 8906 for (c = insn->assembler; *c; c++) 8907 { 8908 if (*c == '%') 8909 { 8910 switch (*++c) 8911 { 8912 case '%': 8913 func (stream, "%%"); 8914 break; 8915 8916 case '0': case '1': case '2': case '3': case '4': 8917 case '5': case '6': case '7': case '8': case '9': 8918 { 8919 int width; 8920 unsigned long value; 8921 8922 c = arm_decode_bitfield (c, given, &value, &width); 8923 8924 switch (*c) 8925 { 8926 case 'S': 8927 if (value > 10) 8928 is_unpredictable = TRUE; 8929 /* Fall through. */ 8930 case 'R': 8931 if (value == 13) 8932 is_unpredictable = TRUE; 8933 /* Fall through. */ 8934 case 'r': 8935 func (stream, "%s", arm_regnames[value]); 8936 break; 8937 8938 case 'n': 8939 if (value == 15) 8940 func (stream, "%s", "APSR_nzcv"); 8941 else 8942 func (stream, "%s", arm_regnames[value]); 8943 break; 8944 8945 case 'T': 8946 func (stream, "%s", arm_regnames[value + 1]); 8947 break; 8948 8949 case 'd': 8950 func (stream, "%ld", value); 8951 break; 8952 8953 case 'V': 8954 if (given & (1 << 6)) 8955 func (stream, "q%ld", value >> 1); 8956 else if (given & (1 << 24)) 8957 func (stream, "d%ld", value); 8958 else 8959 { 8960 /* Encoding for S register is different than for D and 8961 Q registers. S registers are encoded using the top 8962 single bit in position 22 as the lowest bit of the 8963 register number, while for Q and D it represents the 8964 highest bit of the register number. */ 8965 uint8_t top_bit = (value >> 4) & 1; 8966 uint8_t tmp = (value << 1) & 0x1e; 8967 uint8_t res = tmp | top_bit; 8968 func (stream, "s%u", res); 8969 } 8970 break; 8971 8972 default: 8973 abort (); 8974 } 8975 } 8976 break; 8977 8978 case 'p': 8979 { 8980 uint8_t proc_number = (given >> 8) & 0x7; 8981 func (stream, "p%u", proc_number); 8982 break; 8983 } 8984 8985 case 'a': 8986 { 8987 uint8_t a_offset = 28; 8988 if (given & (1 << a_offset)) 8989 func (stream, "a"); 8990 break; 8991 } 8992 default: 8993 abort (); 8994 } 8995 } 8996 else 8997 func (stream, "%c", *c); 8998 } 8999 9000 if (is_unpredictable) 9001 func (stream, UNPREDICTABLE_INSTRUCTION); 9002 9003 return TRUE; 9004 } 9005 } 9006 return FALSE; 9007 } 9008 else 9009 return FALSE; 9010 } 9011 9012 9013 /* Print one neon instruction on INFO->STREAM. 9014 Return TRUE if the instuction matched, FALSE if this is not a 9015 recognised neon instruction. */ 9016 9017 static bfd_boolean 9018 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 9019 { 9020 const struct opcode32 *insn; 9021 void *stream = info->stream; 9022 fprintf_ftype func = info->fprintf_func; 9023 9024 if (thumb) 9025 { 9026 if ((given & 0xef000000) == 0xef000000) 9027 { 9028 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 9029 unsigned long bit28 = given & (1 << 28); 9030 9031 given &= 0x00ffffff; 9032 if (bit28) 9033 given |= 0xf3000000; 9034 else 9035 given |= 0xf2000000; 9036 } 9037 else if ((given & 0xff000000) == 0xf9000000) 9038 given ^= 0xf9000000 ^ 0xf4000000; 9039 /* BFloat16 neon instructions without special top byte handling. */ 9040 else if ((given & 0xff000000) == 0xfe000000 9041 || (given & 0xff000000) == 0xfc000000) 9042 ; 9043 /* vdup is also a valid neon instruction. */ 9044 else if ((given & 0xff900f5f) != 0xee800b10) 9045 return FALSE; 9046 } 9047 9048 for (insn = neon_opcodes; insn->assembler; insn++) 9049 { 9050 unsigned long cond_mask = insn->mask; 9051 unsigned long cond_value = insn->value; 9052 int cond; 9053 9054 if (thumb) 9055 { 9056 if ((cond_mask & 0xf0000000) == 0) { 9057 /* For the entries in neon_opcodes, an opcode mask/value with 9058 the high 4 bits equal to 0 indicates a conditional 9059 instruction. For thumb however, we need to include those 9060 bits in the instruction matching. */ 9061 cond_mask |= 0xf0000000; 9062 /* Furthermore, the thumb encoding of a conditional instruction 9063 will have the high 4 bits equal to 0xe. */ 9064 cond_value |= 0xe0000000; 9065 } 9066 if (ifthen_state) 9067 cond = IFTHEN_COND; 9068 else 9069 cond = COND_UNCOND; 9070 } 9071 else 9072 { 9073 if ((given & 0xf0000000) == 0xf0000000) 9074 { 9075 /* If the instruction is unconditional, update the mask to only 9076 match against unconditional opcode values. */ 9077 cond_mask |= 0xf0000000; 9078 cond = COND_UNCOND; 9079 } 9080 else 9081 { 9082 cond = (given >> 28) & 0xf; 9083 if (cond == 0xe) 9084 cond = COND_UNCOND; 9085 } 9086 } 9087 9088 if ((given & cond_mask) == cond_value) 9089 { 9090 signed long value_in_comment = 0; 9091 bfd_boolean is_unpredictable = FALSE; 9092 const char *c; 9093 9094 for (c = insn->assembler; *c; c++) 9095 { 9096 if (*c == '%') 9097 { 9098 switch (*++c) 9099 { 9100 case '%': 9101 func (stream, "%%"); 9102 break; 9103 9104 case 'u': 9105 if (thumb && ifthen_state) 9106 is_unpredictable = TRUE; 9107 9108 /* Fall through. */ 9109 case 'c': 9110 func (stream, "%s", arm_conditional[cond]); 9111 break; 9112 9113 case 'A': 9114 { 9115 static const unsigned char enc[16] = 9116 { 9117 0x4, 0x14, /* st4 0,1 */ 9118 0x4, /* st1 2 */ 9119 0x4, /* st2 3 */ 9120 0x3, /* st3 4 */ 9121 0x13, /* st3 5 */ 9122 0x3, /* st1 6 */ 9123 0x1, /* st1 7 */ 9124 0x2, /* st2 8 */ 9125 0x12, /* st2 9 */ 9126 0x2, /* st1 10 */ 9127 0, 0, 0, 0, 0 9128 }; 9129 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9130 int rn = ((given >> 16) & 0xf); 9131 int rm = ((given >> 0) & 0xf); 9132 int align = ((given >> 4) & 0x3); 9133 int type = ((given >> 8) & 0xf); 9134 int n = enc[type] & 0xf; 9135 int stride = (enc[type] >> 4) + 1; 9136 int ix; 9137 9138 func (stream, "{"); 9139 if (stride > 1) 9140 for (ix = 0; ix != n; ix++) 9141 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 9142 else if (n == 1) 9143 func (stream, "d%d", rd); 9144 else 9145 func (stream, "d%d-d%d", rd, rd + n - 1); 9146 func (stream, "}, [%s", arm_regnames[rn]); 9147 if (align) 9148 func (stream, " :%d", 32 << align); 9149 func (stream, "]"); 9150 if (rm == 0xd) 9151 func (stream, "!"); 9152 else if (rm != 0xf) 9153 func (stream, ", %s", arm_regnames[rm]); 9154 } 9155 break; 9156 9157 case 'B': 9158 { 9159 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9160 int rn = ((given >> 16) & 0xf); 9161 int rm = ((given >> 0) & 0xf); 9162 int idx_align = ((given >> 4) & 0xf); 9163 int align = 0; 9164 int size = ((given >> 10) & 0x3); 9165 int idx = idx_align >> (size + 1); 9166 int length = ((given >> 8) & 3) + 1; 9167 int stride = 1; 9168 int i; 9169 9170 if (length > 1 && size > 0) 9171 stride = (idx_align & (1 << size)) ? 2 : 1; 9172 9173 switch (length) 9174 { 9175 case 1: 9176 { 9177 int amask = (1 << size) - 1; 9178 if ((idx_align & (1 << size)) != 0) 9179 return FALSE; 9180 if (size > 0) 9181 { 9182 if ((idx_align & amask) == amask) 9183 align = 8 << size; 9184 else if ((idx_align & amask) != 0) 9185 return FALSE; 9186 } 9187 } 9188 break; 9189 9190 case 2: 9191 if (size == 2 && (idx_align & 2) != 0) 9192 return FALSE; 9193 align = (idx_align & 1) ? 16 << size : 0; 9194 break; 9195 9196 case 3: 9197 if ((size == 2 && (idx_align & 3) != 0) 9198 || (idx_align & 1) != 0) 9199 return FALSE; 9200 break; 9201 9202 case 4: 9203 if (size == 2) 9204 { 9205 if ((idx_align & 3) == 3) 9206 return FALSE; 9207 align = (idx_align & 3) * 64; 9208 } 9209 else 9210 align = (idx_align & 1) ? 32 << size : 0; 9211 break; 9212 9213 default: 9214 abort (); 9215 } 9216 9217 func (stream, "{"); 9218 for (i = 0; i < length; i++) 9219 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 9220 rd + i * stride, idx); 9221 func (stream, "}, [%s", arm_regnames[rn]); 9222 if (align) 9223 func (stream, " :%d", align); 9224 func (stream, "]"); 9225 if (rm == 0xd) 9226 func (stream, "!"); 9227 else if (rm != 0xf) 9228 func (stream, ", %s", arm_regnames[rm]); 9229 } 9230 break; 9231 9232 case 'C': 9233 { 9234 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9235 int rn = ((given >> 16) & 0xf); 9236 int rm = ((given >> 0) & 0xf); 9237 int align = ((given >> 4) & 0x1); 9238 int size = ((given >> 6) & 0x3); 9239 int type = ((given >> 8) & 0x3); 9240 int n = type + 1; 9241 int stride = ((given >> 5) & 0x1); 9242 int ix; 9243 9244 if (stride && (n == 1)) 9245 n++; 9246 else 9247 stride++; 9248 9249 func (stream, "{"); 9250 if (stride > 1) 9251 for (ix = 0; ix != n; ix++) 9252 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 9253 else if (n == 1) 9254 func (stream, "d%d[]", rd); 9255 else 9256 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 9257 func (stream, "}, [%s", arm_regnames[rn]); 9258 if (align) 9259 { 9260 align = (8 * (type + 1)) << size; 9261 if (type == 3) 9262 align = (size > 1) ? align >> 1 : align; 9263 if (type == 2 || (type == 0 && !size)) 9264 func (stream, " :<bad align %d>", align); 9265 else 9266 func (stream, " :%d", align); 9267 } 9268 func (stream, "]"); 9269 if (rm == 0xd) 9270 func (stream, "!"); 9271 else if (rm != 0xf) 9272 func (stream, ", %s", arm_regnames[rm]); 9273 } 9274 break; 9275 9276 case 'D': 9277 { 9278 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 9279 int size = (given >> 20) & 3; 9280 int reg = raw_reg & ((4 << size) - 1); 9281 int ix = raw_reg >> size >> 2; 9282 9283 func (stream, "d%d[%d]", reg, ix); 9284 } 9285 break; 9286 9287 case 'E': 9288 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 9289 { 9290 int bits = 0; 9291 int cmode = (given >> 8) & 0xf; 9292 int op = (given >> 5) & 0x1; 9293 unsigned long value = 0, hival = 0; 9294 unsigned shift; 9295 int size = 0; 9296 int isfloat = 0; 9297 9298 bits |= ((given >> 24) & 1) << 7; 9299 bits |= ((given >> 16) & 7) << 4; 9300 bits |= ((given >> 0) & 15) << 0; 9301 9302 if (cmode < 8) 9303 { 9304 shift = (cmode >> 1) & 3; 9305 value = (unsigned long) bits << (8 * shift); 9306 size = 32; 9307 } 9308 else if (cmode < 12) 9309 { 9310 shift = (cmode >> 1) & 1; 9311 value = (unsigned long) bits << (8 * shift); 9312 size = 16; 9313 } 9314 else if (cmode < 14) 9315 { 9316 shift = (cmode & 1) + 1; 9317 value = (unsigned long) bits << (8 * shift); 9318 value |= (1ul << (8 * shift)) - 1; 9319 size = 32; 9320 } 9321 else if (cmode == 14) 9322 { 9323 if (op) 9324 { 9325 /* Bit replication into bytes. */ 9326 int ix; 9327 unsigned long mask; 9328 9329 value = 0; 9330 hival = 0; 9331 for (ix = 7; ix >= 0; ix--) 9332 { 9333 mask = ((bits >> ix) & 1) ? 0xff : 0; 9334 if (ix <= 3) 9335 value = (value << 8) | mask; 9336 else 9337 hival = (hival << 8) | mask; 9338 } 9339 size = 64; 9340 } 9341 else 9342 { 9343 /* Byte replication. */ 9344 value = (unsigned long) bits; 9345 size = 8; 9346 } 9347 } 9348 else if (!op) 9349 { 9350 /* Floating point encoding. */ 9351 int tmp; 9352 9353 value = (unsigned long) (bits & 0x7f) << 19; 9354 value |= (unsigned long) (bits & 0x80) << 24; 9355 tmp = bits & 0x40 ? 0x3c : 0x40; 9356 value |= (unsigned long) tmp << 24; 9357 size = 32; 9358 isfloat = 1; 9359 } 9360 else 9361 { 9362 func (stream, "<illegal constant %.8x:%x:%x>", 9363 bits, cmode, op); 9364 size = 32; 9365 break; 9366 } 9367 switch (size) 9368 { 9369 case 8: 9370 func (stream, "#%ld\t; 0x%.2lx", value, value); 9371 break; 9372 9373 case 16: 9374 func (stream, "#%ld\t; 0x%.4lx", value, value); 9375 break; 9376 9377 case 32: 9378 if (isfloat) 9379 { 9380 unsigned char valbytes[4]; 9381 double fvalue; 9382 9383 /* Do this a byte at a time so we don't have to 9384 worry about the host's endianness. */ 9385 valbytes[0] = value & 0xff; 9386 valbytes[1] = (value >> 8) & 0xff; 9387 valbytes[2] = (value >> 16) & 0xff; 9388 valbytes[3] = (value >> 24) & 0xff; 9389 9390 floatformat_to_double 9391 (& floatformat_ieee_single_little, valbytes, 9392 & fvalue); 9393 9394 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 9395 value); 9396 } 9397 else 9398 func (stream, "#%ld\t; 0x%.8lx", 9399 (long) (((value & 0x80000000L) != 0) 9400 ? value | ~0xffffffffL : value), 9401 value); 9402 break; 9403 9404 case 64: 9405 func (stream, "#0x%.8lx%.8lx", hival, value); 9406 break; 9407 9408 default: 9409 abort (); 9410 } 9411 } 9412 break; 9413 9414 case 'F': 9415 { 9416 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 9417 int num = (given >> 8) & 0x3; 9418 9419 if (!num) 9420 func (stream, "{d%d}", regno); 9421 else if (num + regno >= 32) 9422 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 9423 else 9424 func (stream, "{d%d-d%d}", regno, regno + num); 9425 } 9426 break; 9427 9428 9429 case '0': case '1': case '2': case '3': case '4': 9430 case '5': case '6': case '7': case '8': case '9': 9431 { 9432 int width; 9433 unsigned long value; 9434 9435 c = arm_decode_bitfield (c, given, &value, &width); 9436 9437 switch (*c) 9438 { 9439 case 'r': 9440 func (stream, "%s", arm_regnames[value]); 9441 break; 9442 case 'd': 9443 func (stream, "%ld", value); 9444 value_in_comment = value; 9445 break; 9446 case 'e': 9447 func (stream, "%ld", (1ul << width) - value); 9448 break; 9449 9450 case 'S': 9451 case 'T': 9452 case 'U': 9453 /* Various width encodings. */ 9454 { 9455 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 9456 int limit; 9457 unsigned low, high; 9458 9459 c++; 9460 if (*c >= '0' && *c <= '9') 9461 limit = *c - '0'; 9462 else if (*c >= 'a' && *c <= 'f') 9463 limit = *c - 'a' + 10; 9464 else 9465 abort (); 9466 low = limit >> 2; 9467 high = limit & 3; 9468 9469 if (value < low || value > high) 9470 func (stream, "<illegal width %d>", base << value); 9471 else 9472 func (stream, "%d", base << value); 9473 } 9474 break; 9475 case 'R': 9476 if (given & (1 << 6)) 9477 goto Q; 9478 /* FALLTHROUGH */ 9479 case 'D': 9480 func (stream, "d%ld", value); 9481 break; 9482 case 'Q': 9483 Q: 9484 if (value & 1) 9485 func (stream, "<illegal reg q%ld.5>", value >> 1); 9486 else 9487 func (stream, "q%ld", value >> 1); 9488 break; 9489 9490 case '`': 9491 c++; 9492 if (value == 0) 9493 func (stream, "%c", *c); 9494 break; 9495 case '\'': 9496 c++; 9497 if (value == ((1ul << width) - 1)) 9498 func (stream, "%c", *c); 9499 break; 9500 case '?': 9501 func (stream, "%c", c[(1 << width) - (int) value]); 9502 c += 1 << width; 9503 break; 9504 default: 9505 abort (); 9506 } 9507 } 9508 break; 9509 9510 default: 9511 abort (); 9512 } 9513 } 9514 else 9515 func (stream, "%c", *c); 9516 } 9517 9518 if (value_in_comment > 32 || value_in_comment < -16) 9519 func (stream, "\t; 0x%lx", value_in_comment); 9520 9521 if (is_unpredictable) 9522 func (stream, UNPREDICTABLE_INSTRUCTION); 9523 9524 return TRUE; 9525 } 9526 } 9527 return FALSE; 9528 } 9529 9530 /* Print one mve instruction on INFO->STREAM. 9531 Return TRUE if the instuction matched, FALSE if this is not a 9532 recognised mve instruction. */ 9533 9534 static bfd_boolean 9535 print_insn_mve (struct disassemble_info *info, long given) 9536 { 9537 const struct mopcode32 *insn; 9538 void *stream = info->stream; 9539 fprintf_ftype func = info->fprintf_func; 9540 9541 for (insn = mve_opcodes; insn->assembler; insn++) 9542 { 9543 if (((given & insn->mask) == insn->value) 9544 && !is_mve_encoding_conflict (given, insn->mve_op)) 9545 { 9546 signed long value_in_comment = 0; 9547 bfd_boolean is_unpredictable = FALSE; 9548 bfd_boolean is_undefined = FALSE; 9549 const char *c; 9550 enum mve_unpredictable unpredictable_cond = UNPRED_NONE; 9551 enum mve_undefined undefined_cond = UNDEF_NONE; 9552 9553 /* Most vector mve instruction are illegal in a it block. 9554 There are a few exceptions; check for them. */ 9555 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op)) 9556 { 9557 is_unpredictable = TRUE; 9558 unpredictable_cond = UNPRED_IT_BLOCK; 9559 } 9560 else if (is_mve_unpredictable (given, insn->mve_op, 9561 &unpredictable_cond)) 9562 is_unpredictable = TRUE; 9563 9564 if (is_mve_undefined (given, insn->mve_op, &undefined_cond)) 9565 is_undefined = TRUE; 9566 9567 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV, 9568 i.e "VMOV Qd, Qm". */ 9569 if ((insn->mve_op == MVE_VORR_REG) 9570 && (arm_decode_field (given, 1, 3) 9571 == arm_decode_field (given, 17, 19))) 9572 continue; 9573 9574 for (c = insn->assembler; *c; c++) 9575 { 9576 if (*c == '%') 9577 { 9578 switch (*++c) 9579 { 9580 case '%': 9581 func (stream, "%%"); 9582 break; 9583 9584 case 'a': 9585 /* Don't print anything for '+' as it is implied. */ 9586 if (arm_decode_field (given, 23, 23) == 0) 9587 func (stream, "-"); 9588 break; 9589 9590 case 'c': 9591 if (ifthen_state) 9592 func (stream, "%s", arm_conditional[IFTHEN_COND]); 9593 break; 9594 9595 case 'd': 9596 print_mve_vld_str_addr (info, given, insn->mve_op); 9597 break; 9598 9599 case 'i': 9600 { 9601 long mve_mask = mve_extract_pred_mask (given); 9602 func (stream, "%s", mve_predicatenames[mve_mask]); 9603 } 9604 break; 9605 9606 case 'j': 9607 { 9608 unsigned int imm5 = 0; 9609 imm5 |= arm_decode_field (given, 6, 7); 9610 imm5 |= (arm_decode_field (given, 12, 14) << 2); 9611 func (stream, "#%u", (imm5 == 0) ? 32 : imm5); 9612 } 9613 break; 9614 9615 case 'k': 9616 func (stream, "#%u", 9617 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); 9618 break; 9619 9620 case 'n': 9621 print_vec_condition (info, given, insn->mve_op); 9622 break; 9623 9624 case 'o': 9625 if (arm_decode_field (given, 0, 0) == 1) 9626 { 9627 unsigned long size 9628 = arm_decode_field (given, 4, 4) 9629 | (arm_decode_field (given, 6, 6) << 1); 9630 9631 func (stream, ", uxtw #%lu", size); 9632 } 9633 break; 9634 9635 case 'm': 9636 print_mve_rounding_mode (info, given, insn->mve_op); 9637 break; 9638 9639 case 's': 9640 print_mve_vcvt_size (info, given, insn->mve_op); 9641 break; 9642 9643 case 'u': 9644 { 9645 unsigned long op1 = arm_decode_field (given, 21, 22); 9646 9647 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP)) 9648 { 9649 /* Check for signed. */ 9650 if (arm_decode_field (given, 23, 23) == 0) 9651 { 9652 /* We don't print 's' for S32. */ 9653 if ((arm_decode_field (given, 5, 6) == 0) 9654 && ((op1 == 0) || (op1 == 1))) 9655 ; 9656 else 9657 func (stream, "s"); 9658 } 9659 else 9660 func (stream, "u"); 9661 } 9662 else 9663 { 9664 if (arm_decode_field (given, 28, 28) == 0) 9665 func (stream, "s"); 9666 else 9667 func (stream, "u"); 9668 } 9669 } 9670 break; 9671 9672 case 'v': 9673 print_instruction_predicate (info); 9674 break; 9675 9676 case 'w': 9677 if (arm_decode_field (given, 21, 21) == 1) 9678 func (stream, "!"); 9679 break; 9680 9681 case 'B': 9682 print_mve_register_blocks (info, given, insn->mve_op); 9683 break; 9684 9685 case 'E': 9686 /* SIMD encoded constant for mov, mvn, vorr, vbic. */ 9687 9688 print_simd_imm8 (info, given, 28, insn); 9689 break; 9690 9691 case 'N': 9692 print_mve_vmov_index (info, given); 9693 break; 9694 9695 case 'T': 9696 if (arm_decode_field (given, 12, 12) == 0) 9697 func (stream, "b"); 9698 else 9699 func (stream, "t"); 9700 break; 9701 9702 case 'X': 9703 if (arm_decode_field (given, 12, 12) == 1) 9704 func (stream, "x"); 9705 break; 9706 9707 case '0': case '1': case '2': case '3': case '4': 9708 case '5': case '6': case '7': case '8': case '9': 9709 { 9710 int width; 9711 unsigned long value; 9712 9713 c = arm_decode_bitfield (c, given, &value, &width); 9714 9715 switch (*c) 9716 { 9717 case 'Z': 9718 if (value == 13) 9719 is_unpredictable = TRUE; 9720 else if (value == 15) 9721 func (stream, "zr"); 9722 else 9723 func (stream, "%s", arm_regnames[value]); 9724 break; 9725 9726 case 'c': 9727 func (stream, "%s", arm_conditional[value]); 9728 break; 9729 9730 case 'C': 9731 value ^= 1; 9732 func (stream, "%s", arm_conditional[value]); 9733 break; 9734 9735 case 'S': 9736 if (value == 13 || value == 15) 9737 is_unpredictable = TRUE; 9738 else 9739 func (stream, "%s", arm_regnames[value]); 9740 break; 9741 9742 case 's': 9743 print_mve_size (info, 9744 value, 9745 insn->mve_op); 9746 break; 9747 case 'I': 9748 if (value == 1) 9749 func (stream, "i"); 9750 break; 9751 case 'A': 9752 if (value == 1) 9753 func (stream, "a"); 9754 break; 9755 case 'h': 9756 { 9757 unsigned int odd_reg = (value << 1) | 1; 9758 func (stream, "%s", arm_regnames[odd_reg]); 9759 } 9760 break; 9761 case 'i': 9762 { 9763 unsigned long imm 9764 = arm_decode_field (given, 0, 6); 9765 unsigned long mod_imm = imm; 9766 9767 switch (insn->mve_op) 9768 { 9769 case MVE_VLDRW_GATHER_T5: 9770 case MVE_VSTRW_SCATTER_T5: 9771 mod_imm = mod_imm << 2; 9772 break; 9773 case MVE_VSTRD_SCATTER_T6: 9774 case MVE_VLDRD_GATHER_T6: 9775 mod_imm = mod_imm << 3; 9776 break; 9777 9778 default: 9779 break; 9780 } 9781 9782 func (stream, "%lu", mod_imm); 9783 } 9784 break; 9785 case 'k': 9786 func (stream, "%lu", 64 - value); 9787 break; 9788 case 'l': 9789 { 9790 unsigned int even_reg = value << 1; 9791 func (stream, "%s", arm_regnames[even_reg]); 9792 } 9793 break; 9794 case 'u': 9795 switch (value) 9796 { 9797 case 0: 9798 func (stream, "1"); 9799 break; 9800 case 1: 9801 func (stream, "2"); 9802 break; 9803 case 2: 9804 func (stream, "4"); 9805 break; 9806 case 3: 9807 func (stream, "8"); 9808 break; 9809 default: 9810 break; 9811 } 9812 break; 9813 case 'o': 9814 print_mve_rotate (info, value, width); 9815 break; 9816 case 'r': 9817 func (stream, "%s", arm_regnames[value]); 9818 break; 9819 case 'd': 9820 if (insn->mve_op == MVE_VQSHL_T2 9821 || insn->mve_op == MVE_VQSHLU_T3 9822 || insn->mve_op == MVE_VRSHR 9823 || insn->mve_op == MVE_VRSHRN 9824 || insn->mve_op == MVE_VSHL_T1 9825 || insn->mve_op == MVE_VSHLL_T1 9826 || insn->mve_op == MVE_VSHR 9827 || insn->mve_op == MVE_VSHRN 9828 || insn->mve_op == MVE_VSLI 9829 || insn->mve_op == MVE_VSRI) 9830 print_mve_shift_n (info, given, insn->mve_op); 9831 else if (insn->mve_op == MVE_VSHLL_T2) 9832 { 9833 switch (value) 9834 { 9835 case 0x00: 9836 func (stream, "8"); 9837 break; 9838 case 0x01: 9839 func (stream, "16"); 9840 break; 9841 case 0x10: 9842 print_mve_undefined (info, UNDEF_SIZE_0); 9843 break; 9844 default: 9845 assert (0); 9846 break; 9847 } 9848 } 9849 else 9850 { 9851 if (insn->mve_op == MVE_VSHLC && value == 0) 9852 value = 32; 9853 func (stream, "%ld", value); 9854 value_in_comment = value; 9855 } 9856 break; 9857 case 'F': 9858 func (stream, "s%ld", value); 9859 break; 9860 case 'Q': 9861 if (value & 0x8) 9862 func (stream, "<illegal reg q%ld.5>", value); 9863 else 9864 func (stream, "q%ld", value); 9865 break; 9866 case 'x': 9867 func (stream, "0x%08lx", value); 9868 break; 9869 default: 9870 abort (); 9871 } 9872 break; 9873 default: 9874 abort (); 9875 } 9876 } 9877 } 9878 else 9879 func (stream, "%c", *c); 9880 } 9881 9882 if (value_in_comment > 32 || value_in_comment < -16) 9883 func (stream, "\t; 0x%lx", value_in_comment); 9884 9885 if (is_unpredictable) 9886 print_mve_unpredictable (info, unpredictable_cond); 9887 9888 if (is_undefined) 9889 print_mve_undefined (info, undefined_cond); 9890 9891 if ((vpt_block_state.in_vpt_block == FALSE) 9892 && !ifthen_state 9893 && (is_vpt_instruction (given) == TRUE)) 9894 mark_inside_vpt_block (given); 9895 else if (vpt_block_state.in_vpt_block == TRUE) 9896 update_vpt_block_state (); 9897 9898 return TRUE; 9899 } 9900 } 9901 return FALSE; 9902 } 9903 9904 9905 /* Return the name of a v7A special register. */ 9906 9907 static const char * 9908 banked_regname (unsigned reg) 9909 { 9910 switch (reg) 9911 { 9912 case 15: return "CPSR"; 9913 case 32: return "R8_usr"; 9914 case 33: return "R9_usr"; 9915 case 34: return "R10_usr"; 9916 case 35: return "R11_usr"; 9917 case 36: return "R12_usr"; 9918 case 37: return "SP_usr"; 9919 case 38: return "LR_usr"; 9920 case 40: return "R8_fiq"; 9921 case 41: return "R9_fiq"; 9922 case 42: return "R10_fiq"; 9923 case 43: return "R11_fiq"; 9924 case 44: return "R12_fiq"; 9925 case 45: return "SP_fiq"; 9926 case 46: return "LR_fiq"; 9927 case 48: return "LR_irq"; 9928 case 49: return "SP_irq"; 9929 case 50: return "LR_svc"; 9930 case 51: return "SP_svc"; 9931 case 52: return "LR_abt"; 9932 case 53: return "SP_abt"; 9933 case 54: return "LR_und"; 9934 case 55: return "SP_und"; 9935 case 60: return "LR_mon"; 9936 case 61: return "SP_mon"; 9937 case 62: return "ELR_hyp"; 9938 case 63: return "SP_hyp"; 9939 case 79: return "SPSR"; 9940 case 110: return "SPSR_fiq"; 9941 case 112: return "SPSR_irq"; 9942 case 114: return "SPSR_svc"; 9943 case 116: return "SPSR_abt"; 9944 case 118: return "SPSR_und"; 9945 case 124: return "SPSR_mon"; 9946 case 126: return "SPSR_hyp"; 9947 default: return NULL; 9948 } 9949 } 9950 9951 /* Return the name of the DMB/DSB option. */ 9952 static const char * 9953 data_barrier_option (unsigned option) 9954 { 9955 switch (option & 0xf) 9956 { 9957 case 0xf: return "sy"; 9958 case 0xe: return "st"; 9959 case 0xd: return "ld"; 9960 case 0xb: return "ish"; 9961 case 0xa: return "ishst"; 9962 case 0x9: return "ishld"; 9963 case 0x7: return "un"; 9964 case 0x6: return "unst"; 9965 case 0x5: return "nshld"; 9966 case 0x3: return "osh"; 9967 case 0x2: return "oshst"; 9968 case 0x1: return "oshld"; 9969 default: return NULL; 9970 } 9971 } 9972 9973 /* Print one ARM instruction from PC on INFO->STREAM. */ 9974 9975 static void 9976 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 9977 { 9978 const struct opcode32 *insn; 9979 void *stream = info->stream; 9980 fprintf_ftype func = info->fprintf_func; 9981 struct arm_private_data *private_data = info->private_data; 9982 9983 if (print_insn_coprocessor (pc, info, given, FALSE)) 9984 return; 9985 9986 if (print_insn_neon (info, given, FALSE)) 9987 return; 9988 9989 if (print_insn_generic_coprocessor (pc, info, given, FALSE)) 9990 return; 9991 9992 for (insn = arm_opcodes; insn->assembler; insn++) 9993 { 9994 if ((given & insn->mask) != insn->value) 9995 continue; 9996 9997 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 9998 continue; 9999 10000 /* Special case: an instruction with all bits set in the condition field 10001 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 10002 or by the catchall at the end of the table. */ 10003 if ((given & 0xF0000000) != 0xF0000000 10004 || (insn->mask & 0xF0000000) == 0xF0000000 10005 || (insn->mask == 0 && insn->value == 0)) 10006 { 10007 unsigned long u_reg = 16; 10008 unsigned long U_reg = 16; 10009 bfd_boolean is_unpredictable = FALSE; 10010 signed long value_in_comment = 0; 10011 const char *c; 10012 10013 for (c = insn->assembler; *c; c++) 10014 { 10015 if (*c == '%') 10016 { 10017 bfd_boolean allow_unpredictable = FALSE; 10018 10019 switch (*++c) 10020 { 10021 case '%': 10022 func (stream, "%%"); 10023 break; 10024 10025 case 'a': 10026 value_in_comment = print_arm_address (pc, info, given); 10027 break; 10028 10029 case 'P': 10030 /* Set P address bit and use normal address 10031 printing routine. */ 10032 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 10033 break; 10034 10035 case 'S': 10036 allow_unpredictable = TRUE; 10037 /* Fall through. */ 10038 case 's': 10039 if ((given & 0x004f0000) == 0x004f0000) 10040 { 10041 /* PC relative with immediate offset. */ 10042 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 10043 10044 if (PRE_BIT_SET) 10045 { 10046 /* Elide positive zero offset. */ 10047 if (offset || NEGATIVE_BIT_SET) 10048 func (stream, "[pc, #%s%d]\t; ", 10049 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10050 else 10051 func (stream, "[pc]\t; "); 10052 if (NEGATIVE_BIT_SET) 10053 offset = -offset; 10054 info->print_address_func (offset + pc + 8, info); 10055 } 10056 else 10057 { 10058 /* Always show the offset. */ 10059 func (stream, "[pc], #%s%d", 10060 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10061 if (! allow_unpredictable) 10062 is_unpredictable = TRUE; 10063 } 10064 } 10065 else 10066 { 10067 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 10068 10069 func (stream, "[%s", 10070 arm_regnames[(given >> 16) & 0xf]); 10071 10072 if (PRE_BIT_SET) 10073 { 10074 if (IMMEDIATE_BIT_SET) 10075 { 10076 /* Elide offset for non-writeback 10077 positive zero. */ 10078 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 10079 || offset) 10080 func (stream, ", #%s%d", 10081 NEGATIVE_BIT_SET ? "-" : "", offset); 10082 10083 if (NEGATIVE_BIT_SET) 10084 offset = -offset; 10085 10086 value_in_comment = offset; 10087 } 10088 else 10089 { 10090 /* Register Offset or Register Pre-Indexed. */ 10091 func (stream, ", %s%s", 10092 NEGATIVE_BIT_SET ? "-" : "", 10093 arm_regnames[given & 0xf]); 10094 10095 /* Writing back to the register that is the source/ 10096 destination of the load/store is unpredictable. */ 10097 if (! allow_unpredictable 10098 && WRITEBACK_BIT_SET 10099 && ((given & 0xf) == ((given >> 12) & 0xf))) 10100 is_unpredictable = TRUE; 10101 } 10102 10103 func (stream, "]%s", 10104 WRITEBACK_BIT_SET ? "!" : ""); 10105 } 10106 else 10107 { 10108 if (IMMEDIATE_BIT_SET) 10109 { 10110 /* Immediate Post-indexed. */ 10111 /* PR 10924: Offset must be printed, even if it is zero. */ 10112 func (stream, "], #%s%d", 10113 NEGATIVE_BIT_SET ? "-" : "", offset); 10114 if (NEGATIVE_BIT_SET) 10115 offset = -offset; 10116 value_in_comment = offset; 10117 } 10118 else 10119 { 10120 /* Register Post-indexed. */ 10121 func (stream, "], %s%s", 10122 NEGATIVE_BIT_SET ? "-" : "", 10123 arm_regnames[given & 0xf]); 10124 10125 /* Writing back to the register that is the source/ 10126 destination of the load/store is unpredictable. */ 10127 if (! allow_unpredictable 10128 && (given & 0xf) == ((given >> 12) & 0xf)) 10129 is_unpredictable = TRUE; 10130 } 10131 10132 if (! allow_unpredictable) 10133 { 10134 /* Writeback is automatically implied by post- addressing. 10135 Setting the W bit is unnecessary and ARM specify it as 10136 being unpredictable. */ 10137 if (WRITEBACK_BIT_SET 10138 /* Specifying the PC register as the post-indexed 10139 registers is also unpredictable. */ 10140 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 10141 is_unpredictable = TRUE; 10142 } 10143 } 10144 } 10145 break; 10146 10147 case 'b': 10148 { 10149 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 10150 bfd_vma target = disp * 4 + pc + 8; 10151 info->print_address_func (target, info); 10152 10153 /* Fill in instruction information. */ 10154 info->insn_info_valid = 1; 10155 info->insn_type = dis_branch; 10156 info->target = target; 10157 } 10158 break; 10159 10160 case 'c': 10161 if (((given >> 28) & 0xf) != 0xe) 10162 func (stream, "%s", 10163 arm_conditional [(given >> 28) & 0xf]); 10164 break; 10165 10166 case 'm': 10167 { 10168 int started = 0; 10169 int reg; 10170 10171 func (stream, "{"); 10172 for (reg = 0; reg < 16; reg++) 10173 if ((given & (1 << reg)) != 0) 10174 { 10175 if (started) 10176 func (stream, ", "); 10177 started = 1; 10178 func (stream, "%s", arm_regnames[reg]); 10179 } 10180 func (stream, "}"); 10181 if (! started) 10182 is_unpredictable = TRUE; 10183 } 10184 break; 10185 10186 case 'q': 10187 arm_decode_shift (given, func, stream, FALSE); 10188 break; 10189 10190 case 'o': 10191 if ((given & 0x02000000) != 0) 10192 { 10193 unsigned int rotate = (given & 0xf00) >> 7; 10194 unsigned int immed = (given & 0xff); 10195 unsigned int a, i; 10196 10197 a = (immed << ((32 - rotate) & 31) 10198 | immed >> rotate) & 0xffffffff; 10199 /* If there is another encoding with smaller rotate, 10200 the rotate should be specified directly. */ 10201 for (i = 0; i < 32; i += 2) 10202 if ((a << i | a >> ((32 - i) & 31)) <= 0xff) 10203 break; 10204 10205 if (i != rotate) 10206 func (stream, "#%d, %d", immed, rotate); 10207 else 10208 func (stream, "#%d", a); 10209 value_in_comment = a; 10210 } 10211 else 10212 arm_decode_shift (given, func, stream, TRUE); 10213 break; 10214 10215 case 'p': 10216 if ((given & 0x0000f000) == 0x0000f000) 10217 { 10218 arm_feature_set arm_ext_v6 = 10219 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 10220 10221 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 10222 mechanism for setting PSR flag bits. They are 10223 obsolete in V6 onwards. */ 10224 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 10225 arm_ext_v6)) 10226 func (stream, "p"); 10227 else 10228 is_unpredictable = TRUE; 10229 } 10230 break; 10231 10232 case 't': 10233 if ((given & 0x01200000) == 0x00200000) 10234 func (stream, "t"); 10235 break; 10236 10237 case 'A': 10238 { 10239 int offset = given & 0xff; 10240 10241 value_in_comment = offset * 4; 10242 if (NEGATIVE_BIT_SET) 10243 value_in_comment = - value_in_comment; 10244 10245 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 10246 10247 if (PRE_BIT_SET) 10248 { 10249 if (offset) 10250 func (stream, ", #%d]%s", 10251 (int) value_in_comment, 10252 WRITEBACK_BIT_SET ? "!" : ""); 10253 else 10254 func (stream, "]"); 10255 } 10256 else 10257 { 10258 func (stream, "]"); 10259 10260 if (WRITEBACK_BIT_SET) 10261 { 10262 if (offset) 10263 func (stream, ", #%d", (int) value_in_comment); 10264 } 10265 else 10266 { 10267 func (stream, ", {%d}", (int) offset); 10268 value_in_comment = offset; 10269 } 10270 } 10271 } 10272 break; 10273 10274 case 'B': 10275 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 10276 { 10277 bfd_vma address; 10278 bfd_vma offset = 0; 10279 10280 if (! NEGATIVE_BIT_SET) 10281 /* Is signed, hi bits should be ones. */ 10282 offset = (-1) ^ 0x00ffffff; 10283 10284 /* Offset is (SignExtend(offset field)<<2). */ 10285 offset += given & 0x00ffffff; 10286 offset <<= 2; 10287 address = offset + pc + 8; 10288 10289 if (given & 0x01000000) 10290 /* H bit allows addressing to 2-byte boundaries. */ 10291 address += 2; 10292 10293 info->print_address_func (address, info); 10294 10295 /* Fill in instruction information. */ 10296 info->insn_info_valid = 1; 10297 info->insn_type = dis_branch; 10298 info->target = address; 10299 } 10300 break; 10301 10302 case 'C': 10303 if ((given & 0x02000200) == 0x200) 10304 { 10305 const char * name; 10306 unsigned sysm = (given & 0x004f0000) >> 16; 10307 10308 sysm |= (given & 0x300) >> 4; 10309 name = banked_regname (sysm); 10310 10311 if (name != NULL) 10312 func (stream, "%s", name); 10313 else 10314 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 10315 } 10316 else 10317 { 10318 func (stream, "%cPSR_", 10319 (given & 0x00400000) ? 'S' : 'C'); 10320 if (given & 0x80000) 10321 func (stream, "f"); 10322 if (given & 0x40000) 10323 func (stream, "s"); 10324 if (given & 0x20000) 10325 func (stream, "x"); 10326 if (given & 0x10000) 10327 func (stream, "c"); 10328 } 10329 break; 10330 10331 case 'U': 10332 if ((given & 0xf0) == 0x60) 10333 { 10334 switch (given & 0xf) 10335 { 10336 case 0xf: func (stream, "sy"); break; 10337 default: 10338 func (stream, "#%d", (int) given & 0xf); 10339 break; 10340 } 10341 } 10342 else 10343 { 10344 const char * opt = data_barrier_option (given & 0xf); 10345 if (opt != NULL) 10346 func (stream, "%s", opt); 10347 else 10348 func (stream, "#%d", (int) given & 0xf); 10349 } 10350 break; 10351 10352 case '0': case '1': case '2': case '3': case '4': 10353 case '5': case '6': case '7': case '8': case '9': 10354 { 10355 int width; 10356 unsigned long value; 10357 10358 c = arm_decode_bitfield (c, given, &value, &width); 10359 10360 switch (*c) 10361 { 10362 case 'R': 10363 if (value == 15) 10364 is_unpredictable = TRUE; 10365 /* Fall through. */ 10366 case 'r': 10367 case 'T': 10368 /* We want register + 1 when decoding T. */ 10369 if (*c == 'T') 10370 value = (value + 1) & 0xf; 10371 10372 if (c[1] == 'u') 10373 { 10374 /* Eat the 'u' character. */ 10375 ++ c; 10376 10377 if (u_reg == value) 10378 is_unpredictable = TRUE; 10379 u_reg = value; 10380 } 10381 if (c[1] == 'U') 10382 { 10383 /* Eat the 'U' character. */ 10384 ++ c; 10385 10386 if (U_reg == value) 10387 is_unpredictable = TRUE; 10388 U_reg = value; 10389 } 10390 func (stream, "%s", arm_regnames[value]); 10391 break; 10392 case 'd': 10393 func (stream, "%ld", value); 10394 value_in_comment = value; 10395 break; 10396 case 'b': 10397 func (stream, "%ld", value * 8); 10398 value_in_comment = value * 8; 10399 break; 10400 case 'W': 10401 func (stream, "%ld", value + 1); 10402 value_in_comment = value + 1; 10403 break; 10404 case 'x': 10405 func (stream, "0x%08lx", value); 10406 10407 /* Some SWI instructions have special 10408 meanings. */ 10409 if ((given & 0x0fffffff) == 0x0FF00000) 10410 func (stream, "\t; IMB"); 10411 else if ((given & 0x0fffffff) == 0x0FF00001) 10412 func (stream, "\t; IMBRange"); 10413 break; 10414 case 'X': 10415 func (stream, "%01lx", value & 0xf); 10416 value_in_comment = value; 10417 break; 10418 case '`': 10419 c++; 10420 if (value == 0) 10421 func (stream, "%c", *c); 10422 break; 10423 case '\'': 10424 c++; 10425 if (value == ((1ul << width) - 1)) 10426 func (stream, "%c", *c); 10427 break; 10428 case '?': 10429 func (stream, "%c", c[(1 << width) - (int) value]); 10430 c += 1 << width; 10431 break; 10432 default: 10433 abort (); 10434 } 10435 } 10436 break; 10437 10438 case 'e': 10439 { 10440 int imm; 10441 10442 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 10443 func (stream, "%d", imm); 10444 value_in_comment = imm; 10445 } 10446 break; 10447 10448 case 'E': 10449 /* LSB and WIDTH fields of BFI or BFC. The machine- 10450 language instruction encodes LSB and MSB. */ 10451 { 10452 long msb = (given & 0x001f0000) >> 16; 10453 long lsb = (given & 0x00000f80) >> 7; 10454 long w = msb - lsb + 1; 10455 10456 if (w > 0) 10457 func (stream, "#%lu, #%lu", lsb, w); 10458 else 10459 func (stream, "(invalid: %lu:%lu)", lsb, msb); 10460 } 10461 break; 10462 10463 case 'R': 10464 /* Get the PSR/banked register name. */ 10465 { 10466 const char * name; 10467 unsigned sysm = (given & 0x004f0000) >> 16; 10468 10469 sysm |= (given & 0x300) >> 4; 10470 name = banked_regname (sysm); 10471 10472 if (name != NULL) 10473 func (stream, "%s", name); 10474 else 10475 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 10476 } 10477 break; 10478 10479 case 'V': 10480 /* 16-bit unsigned immediate from a MOVT or MOVW 10481 instruction, encoded in bits 0:11 and 15:19. */ 10482 { 10483 long hi = (given & 0x000f0000) >> 4; 10484 long lo = (given & 0x00000fff); 10485 long imm16 = hi | lo; 10486 10487 func (stream, "#%lu", imm16); 10488 value_in_comment = imm16; 10489 } 10490 break; 10491 10492 default: 10493 abort (); 10494 } 10495 } 10496 else 10497 func (stream, "%c", *c); 10498 } 10499 10500 if (value_in_comment > 32 || value_in_comment < -16) 10501 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 10502 10503 if (is_unpredictable) 10504 func (stream, UNPREDICTABLE_INSTRUCTION); 10505 10506 return; 10507 } 10508 } 10509 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 10510 return; 10511 } 10512 10513 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 10514 10515 static void 10516 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 10517 { 10518 const struct opcode16 *insn; 10519 void *stream = info->stream; 10520 fprintf_ftype func = info->fprintf_func; 10521 10522 for (insn = thumb_opcodes; insn->assembler; insn++) 10523 if ((given & insn->mask) == insn->value) 10524 { 10525 signed long value_in_comment = 0; 10526 const char *c = insn->assembler; 10527 10528 for (; *c; c++) 10529 { 10530 int domaskpc = 0; 10531 int domasklr = 0; 10532 10533 if (*c != '%') 10534 { 10535 func (stream, "%c", *c); 10536 continue; 10537 } 10538 10539 switch (*++c) 10540 { 10541 case '%': 10542 func (stream, "%%"); 10543 break; 10544 10545 case 'c': 10546 if (ifthen_state) 10547 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10548 break; 10549 10550 case 'C': 10551 if (ifthen_state) 10552 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10553 else 10554 func (stream, "s"); 10555 break; 10556 10557 case 'I': 10558 { 10559 unsigned int tmp; 10560 10561 ifthen_next_state = given & 0xff; 10562 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 10563 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 10564 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 10565 } 10566 break; 10567 10568 case 'x': 10569 if (ifthen_next_state) 10570 func (stream, "\t; unpredictable branch in IT block\n"); 10571 break; 10572 10573 case 'X': 10574 if (ifthen_state) 10575 func (stream, "\t; unpredictable <IT:%s>", 10576 arm_conditional[IFTHEN_COND]); 10577 break; 10578 10579 case 'S': 10580 { 10581 long reg; 10582 10583 reg = (given >> 3) & 0x7; 10584 if (given & (1 << 6)) 10585 reg += 8; 10586 10587 func (stream, "%s", arm_regnames[reg]); 10588 } 10589 break; 10590 10591 case 'D': 10592 { 10593 long reg; 10594 10595 reg = given & 0x7; 10596 if (given & (1 << 7)) 10597 reg += 8; 10598 10599 func (stream, "%s", arm_regnames[reg]); 10600 } 10601 break; 10602 10603 case 'N': 10604 if (given & (1 << 8)) 10605 domasklr = 1; 10606 /* Fall through. */ 10607 case 'O': 10608 if (*c == 'O' && (given & (1 << 8))) 10609 domaskpc = 1; 10610 /* Fall through. */ 10611 case 'M': 10612 { 10613 int started = 0; 10614 int reg; 10615 10616 func (stream, "{"); 10617 10618 /* It would be nice if we could spot 10619 ranges, and generate the rS-rE format: */ 10620 for (reg = 0; (reg < 8); reg++) 10621 if ((given & (1 << reg)) != 0) 10622 { 10623 if (started) 10624 func (stream, ", "); 10625 started = 1; 10626 func (stream, "%s", arm_regnames[reg]); 10627 } 10628 10629 if (domasklr) 10630 { 10631 if (started) 10632 func (stream, ", "); 10633 started = 1; 10634 func (stream, "%s", arm_regnames[14] /* "lr" */); 10635 } 10636 10637 if (domaskpc) 10638 { 10639 if (started) 10640 func (stream, ", "); 10641 func (stream, "%s", arm_regnames[15] /* "pc" */); 10642 } 10643 10644 func (stream, "}"); 10645 } 10646 break; 10647 10648 case 'W': 10649 /* Print writeback indicator for a LDMIA. We are doing a 10650 writeback if the base register is not in the register 10651 mask. */ 10652 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 10653 func (stream, "!"); 10654 break; 10655 10656 case 'b': 10657 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 10658 { 10659 bfd_vma address = (pc + 4 10660 + ((given & 0x00f8) >> 2) 10661 + ((given & 0x0200) >> 3)); 10662 info->print_address_func (address, info); 10663 10664 /* Fill in instruction information. */ 10665 info->insn_info_valid = 1; 10666 info->insn_type = dis_branch; 10667 info->target = address; 10668 } 10669 break; 10670 10671 case 's': 10672 /* Right shift immediate -- bits 6..10; 1-31 print 10673 as themselves, 0 prints as 32. */ 10674 { 10675 long imm = (given & 0x07c0) >> 6; 10676 if (imm == 0) 10677 imm = 32; 10678 func (stream, "#%ld", imm); 10679 } 10680 break; 10681 10682 case '0': case '1': case '2': case '3': case '4': 10683 case '5': case '6': case '7': case '8': case '9': 10684 { 10685 int bitstart = *c++ - '0'; 10686 int bitend = 0; 10687 10688 while (*c >= '0' && *c <= '9') 10689 bitstart = (bitstart * 10) + *c++ - '0'; 10690 10691 switch (*c) 10692 { 10693 case '-': 10694 { 10695 bfd_vma reg; 10696 10697 c++; 10698 while (*c >= '0' && *c <= '9') 10699 bitend = (bitend * 10) + *c++ - '0'; 10700 if (!bitend) 10701 abort (); 10702 reg = given >> bitstart; 10703 reg &= (2 << (bitend - bitstart)) - 1; 10704 10705 switch (*c) 10706 { 10707 case 'r': 10708 func (stream, "%s", arm_regnames[reg]); 10709 break; 10710 10711 case 'd': 10712 func (stream, "%ld", (long) reg); 10713 value_in_comment = reg; 10714 break; 10715 10716 case 'H': 10717 func (stream, "%ld", (long) (reg << 1)); 10718 value_in_comment = reg << 1; 10719 break; 10720 10721 case 'W': 10722 func (stream, "%ld", (long) (reg << 2)); 10723 value_in_comment = reg << 2; 10724 break; 10725 10726 case 'a': 10727 /* PC-relative address -- the bottom two 10728 bits of the address are dropped 10729 before the calculation. */ 10730 info->print_address_func 10731 (((pc + 4) & ~3) + (reg << 2), info); 10732 value_in_comment = 0; 10733 break; 10734 10735 case 'x': 10736 func (stream, "0x%04lx", (long) reg); 10737 break; 10738 10739 case 'B': 10740 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 10741 bfd_vma target = reg * 2 + pc + 4; 10742 info->print_address_func (target, info); 10743 value_in_comment = 0; 10744 10745 /* Fill in instruction information. */ 10746 info->insn_info_valid = 1; 10747 info->insn_type = dis_branch; 10748 info->target = target; 10749 break; 10750 10751 case 'c': 10752 func (stream, "%s", arm_conditional [reg]); 10753 break; 10754 10755 default: 10756 abort (); 10757 } 10758 } 10759 break; 10760 10761 case '\'': 10762 c++; 10763 if ((given & (1 << bitstart)) != 0) 10764 func (stream, "%c", *c); 10765 break; 10766 10767 case '?': 10768 ++c; 10769 if ((given & (1 << bitstart)) != 0) 10770 func (stream, "%c", *c++); 10771 else 10772 func (stream, "%c", *++c); 10773 break; 10774 10775 default: 10776 abort (); 10777 } 10778 } 10779 break; 10780 10781 default: 10782 abort (); 10783 } 10784 } 10785 10786 if (value_in_comment > 32 || value_in_comment < -16) 10787 func (stream, "\t; 0x%lx", value_in_comment); 10788 return; 10789 } 10790 10791 /* No match. */ 10792 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given); 10793 return; 10794 } 10795 10796 /* Return the name of an V7M special register. */ 10797 10798 static const char * 10799 psr_name (int regno) 10800 { 10801 switch (regno) 10802 { 10803 case 0x0: return "APSR"; 10804 case 0x1: return "IAPSR"; 10805 case 0x2: return "EAPSR"; 10806 case 0x3: return "PSR"; 10807 case 0x5: return "IPSR"; 10808 case 0x6: return "EPSR"; 10809 case 0x7: return "IEPSR"; 10810 case 0x8: return "MSP"; 10811 case 0x9: return "PSP"; 10812 case 0xa: return "MSPLIM"; 10813 case 0xb: return "PSPLIM"; 10814 case 0x10: return "PRIMASK"; 10815 case 0x11: return "BASEPRI"; 10816 case 0x12: return "BASEPRI_MAX"; 10817 case 0x13: return "FAULTMASK"; 10818 case 0x14: return "CONTROL"; 10819 case 0x88: return "MSP_NS"; 10820 case 0x89: return "PSP_NS"; 10821 case 0x8a: return "MSPLIM_NS"; 10822 case 0x8b: return "PSPLIM_NS"; 10823 case 0x90: return "PRIMASK_NS"; 10824 case 0x91: return "BASEPRI_NS"; 10825 case 0x93: return "FAULTMASK_NS"; 10826 case 0x94: return "CONTROL_NS"; 10827 case 0x98: return "SP_NS"; 10828 default: return "<unknown>"; 10829 } 10830 } 10831 10832 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 10833 10834 static void 10835 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 10836 { 10837 const struct opcode32 *insn; 10838 void *stream = info->stream; 10839 fprintf_ftype func = info->fprintf_func; 10840 bfd_boolean is_mve = is_mve_architecture (info); 10841 10842 if (print_insn_coprocessor (pc, info, given, TRUE)) 10843 return; 10844 10845 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE)) 10846 return; 10847 10848 if (is_mve && print_insn_mve (info, given)) 10849 return; 10850 10851 if (print_insn_cde (info, given, TRUE)) 10852 return; 10853 10854 if (print_insn_generic_coprocessor (pc, info, given, TRUE)) 10855 return; 10856 10857 for (insn = thumb32_opcodes; insn->assembler; insn++) 10858 if ((given & insn->mask) == insn->value) 10859 { 10860 bfd_boolean is_clrm = FALSE; 10861 bfd_boolean is_unpredictable = FALSE; 10862 signed long value_in_comment = 0; 10863 const char *c = insn->assembler; 10864 10865 for (; *c; c++) 10866 { 10867 if (*c != '%') 10868 { 10869 func (stream, "%c", *c); 10870 continue; 10871 } 10872 10873 switch (*++c) 10874 { 10875 case '%': 10876 func (stream, "%%"); 10877 break; 10878 10879 case 'c': 10880 if (ifthen_state) 10881 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10882 break; 10883 10884 case 'x': 10885 if (ifthen_next_state) 10886 func (stream, "\t; unpredictable branch in IT block\n"); 10887 break; 10888 10889 case 'X': 10890 if (ifthen_state) 10891 func (stream, "\t; unpredictable <IT:%s>", 10892 arm_conditional[IFTHEN_COND]); 10893 break; 10894 10895 case 'I': 10896 { 10897 unsigned int imm12 = 0; 10898 10899 imm12 |= (given & 0x000000ffu); 10900 imm12 |= (given & 0x00007000u) >> 4; 10901 imm12 |= (given & 0x04000000u) >> 15; 10902 func (stream, "#%u", imm12); 10903 value_in_comment = imm12; 10904 } 10905 break; 10906 10907 case 'M': 10908 { 10909 unsigned int bits = 0, imm, imm8, mod; 10910 10911 bits |= (given & 0x000000ffu); 10912 bits |= (given & 0x00007000u) >> 4; 10913 bits |= (given & 0x04000000u) >> 15; 10914 imm8 = (bits & 0x0ff); 10915 mod = (bits & 0xf00) >> 8; 10916 switch (mod) 10917 { 10918 case 0: imm = imm8; break; 10919 case 1: imm = ((imm8 << 16) | imm8); break; 10920 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 10921 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 10922 default: 10923 mod = (bits & 0xf80) >> 7; 10924 imm8 = (bits & 0x07f) | 0x80; 10925 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 10926 } 10927 func (stream, "#%u", imm); 10928 value_in_comment = imm; 10929 } 10930 break; 10931 10932 case 'J': 10933 { 10934 unsigned int imm = 0; 10935 10936 imm |= (given & 0x000000ffu); 10937 imm |= (given & 0x00007000u) >> 4; 10938 imm |= (given & 0x04000000u) >> 15; 10939 imm |= (given & 0x000f0000u) >> 4; 10940 func (stream, "#%u", imm); 10941 value_in_comment = imm; 10942 } 10943 break; 10944 10945 case 'K': 10946 { 10947 unsigned int imm = 0; 10948 10949 imm |= (given & 0x000f0000u) >> 16; 10950 imm |= (given & 0x00000ff0u) >> 0; 10951 imm |= (given & 0x0000000fu) << 12; 10952 func (stream, "#%u", imm); 10953 value_in_comment = imm; 10954 } 10955 break; 10956 10957 case 'H': 10958 { 10959 unsigned int imm = 0; 10960 10961 imm |= (given & 0x000f0000u) >> 4; 10962 imm |= (given & 0x00000fffu) >> 0; 10963 func (stream, "#%u", imm); 10964 value_in_comment = imm; 10965 } 10966 break; 10967 10968 case 'V': 10969 { 10970 unsigned int imm = 0; 10971 10972 imm |= (given & 0x00000fffu); 10973 imm |= (given & 0x000f0000u) >> 4; 10974 func (stream, "#%u", imm); 10975 value_in_comment = imm; 10976 } 10977 break; 10978 10979 case 'S': 10980 { 10981 unsigned int reg = (given & 0x0000000fu); 10982 unsigned int stp = (given & 0x00000030u) >> 4; 10983 unsigned int imm = 0; 10984 imm |= (given & 0x000000c0u) >> 6; 10985 imm |= (given & 0x00007000u) >> 10; 10986 10987 func (stream, "%s", arm_regnames[reg]); 10988 switch (stp) 10989 { 10990 case 0: 10991 if (imm > 0) 10992 func (stream, ", lsl #%u", imm); 10993 break; 10994 10995 case 1: 10996 if (imm == 0) 10997 imm = 32; 10998 func (stream, ", lsr #%u", imm); 10999 break; 11000 11001 case 2: 11002 if (imm == 0) 11003 imm = 32; 11004 func (stream, ", asr #%u", imm); 11005 break; 11006 11007 case 3: 11008 if (imm == 0) 11009 func (stream, ", rrx"); 11010 else 11011 func (stream, ", ror #%u", imm); 11012 } 11013 } 11014 break; 11015 11016 case 'a': 11017 { 11018 unsigned int Rn = (given & 0x000f0000) >> 16; 11019 unsigned int U = ! NEGATIVE_BIT_SET; 11020 unsigned int op = (given & 0x00000f00) >> 8; 11021 unsigned int i12 = (given & 0x00000fff); 11022 unsigned int i8 = (given & 0x000000ff); 11023 bfd_boolean writeback = FALSE, postind = FALSE; 11024 bfd_vma offset = 0; 11025 11026 func (stream, "[%s", arm_regnames[Rn]); 11027 if (U) /* 12-bit positive immediate offset. */ 11028 { 11029 offset = i12; 11030 if (Rn != 15) 11031 value_in_comment = offset; 11032 } 11033 else if (Rn == 15) /* 12-bit negative immediate offset. */ 11034 offset = - (int) i12; 11035 else if (op == 0x0) /* Shifted register offset. */ 11036 { 11037 unsigned int Rm = (i8 & 0x0f); 11038 unsigned int sh = (i8 & 0x30) >> 4; 11039 11040 func (stream, ", %s", arm_regnames[Rm]); 11041 if (sh) 11042 func (stream, ", lsl #%u", sh); 11043 func (stream, "]"); 11044 break; 11045 } 11046 else switch (op) 11047 { 11048 case 0xE: /* 8-bit positive immediate offset. */ 11049 offset = i8; 11050 break; 11051 11052 case 0xC: /* 8-bit negative immediate offset. */ 11053 offset = -i8; 11054 break; 11055 11056 case 0xF: /* 8-bit + preindex with wb. */ 11057 offset = i8; 11058 writeback = TRUE; 11059 break; 11060 11061 case 0xD: /* 8-bit - preindex with wb. */ 11062 offset = -i8; 11063 writeback = TRUE; 11064 break; 11065 11066 case 0xB: /* 8-bit + postindex. */ 11067 offset = i8; 11068 postind = TRUE; 11069 break; 11070 11071 case 0x9: /* 8-bit - postindex. */ 11072 offset = -i8; 11073 postind = TRUE; 11074 break; 11075 11076 default: 11077 func (stream, ", <undefined>]"); 11078 goto skip; 11079 } 11080 11081 if (postind) 11082 func (stream, "], #%d", (int) offset); 11083 else 11084 { 11085 if (offset) 11086 func (stream, ", #%d", (int) offset); 11087 func (stream, writeback ? "]!" : "]"); 11088 } 11089 11090 if (Rn == 15) 11091 { 11092 func (stream, "\t; "); 11093 info->print_address_func (((pc + 4) & ~3) + offset, info); 11094 } 11095 } 11096 skip: 11097 break; 11098 11099 case 'A': 11100 { 11101 unsigned int U = ! NEGATIVE_BIT_SET; 11102 unsigned int W = WRITEBACK_BIT_SET; 11103 unsigned int Rn = (given & 0x000f0000) >> 16; 11104 unsigned int off = (given & 0x000000ff); 11105 11106 func (stream, "[%s", arm_regnames[Rn]); 11107 11108 if (PRE_BIT_SET) 11109 { 11110 if (off || !U) 11111 { 11112 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 11113 value_in_comment = off * 4 * (U ? 1 : -1); 11114 } 11115 func (stream, "]"); 11116 if (W) 11117 func (stream, "!"); 11118 } 11119 else 11120 { 11121 func (stream, "], "); 11122 if (W) 11123 { 11124 func (stream, "#%c%u", U ? '+' : '-', off * 4); 11125 value_in_comment = off * 4 * (U ? 1 : -1); 11126 } 11127 else 11128 { 11129 func (stream, "{%u}", off); 11130 value_in_comment = off; 11131 } 11132 } 11133 } 11134 break; 11135 11136 case 'w': 11137 { 11138 unsigned int Sbit = (given & 0x01000000) >> 24; 11139 unsigned int type = (given & 0x00600000) >> 21; 11140 11141 switch (type) 11142 { 11143 case 0: func (stream, Sbit ? "sb" : "b"); break; 11144 case 1: func (stream, Sbit ? "sh" : "h"); break; 11145 case 2: 11146 if (Sbit) 11147 func (stream, "??"); 11148 break; 11149 case 3: 11150 func (stream, "??"); 11151 break; 11152 } 11153 } 11154 break; 11155 11156 case 'n': 11157 is_clrm = TRUE; 11158 /* Fall through. */ 11159 case 'm': 11160 { 11161 int started = 0; 11162 int reg; 11163 11164 func (stream, "{"); 11165 for (reg = 0; reg < 16; reg++) 11166 if ((given & (1 << reg)) != 0) 11167 { 11168 if (started) 11169 func (stream, ", "); 11170 started = 1; 11171 if (is_clrm && reg == 13) 11172 func (stream, "(invalid: %s)", arm_regnames[reg]); 11173 else if (is_clrm && reg == 15) 11174 func (stream, "%s", "APSR"); 11175 else 11176 func (stream, "%s", arm_regnames[reg]); 11177 } 11178 func (stream, "}"); 11179 } 11180 break; 11181 11182 case 'E': 11183 { 11184 unsigned int msb = (given & 0x0000001f); 11185 unsigned int lsb = 0; 11186 11187 lsb |= (given & 0x000000c0u) >> 6; 11188 lsb |= (given & 0x00007000u) >> 10; 11189 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 11190 } 11191 break; 11192 11193 case 'F': 11194 { 11195 unsigned int width = (given & 0x0000001f) + 1; 11196 unsigned int lsb = 0; 11197 11198 lsb |= (given & 0x000000c0u) >> 6; 11199 lsb |= (given & 0x00007000u) >> 10; 11200 func (stream, "#%u, #%u", lsb, width); 11201 } 11202 break; 11203 11204 case 'G': 11205 { 11206 unsigned int boff = (((given & 0x07800000) >> 23) << 1); 11207 func (stream, "%x", boff); 11208 } 11209 break; 11210 11211 case 'W': 11212 { 11213 unsigned int immA = (given & 0x001f0000u) >> 16; 11214 unsigned int immB = (given & 0x000007feu) >> 1; 11215 unsigned int immC = (given & 0x00000800u) >> 11; 11216 bfd_vma offset = 0; 11217 11218 offset |= immA << 12; 11219 offset |= immB << 2; 11220 offset |= immC << 1; 11221 /* Sign extend. */ 11222 offset = (offset & 0x10000) ? offset - (1 << 17) : offset; 11223 11224 info->print_address_func (pc + 4 + offset, info); 11225 } 11226 break; 11227 11228 case 'Y': 11229 { 11230 unsigned int immA = (given & 0x007f0000u) >> 16; 11231 unsigned int immB = (given & 0x000007feu) >> 1; 11232 unsigned int immC = (given & 0x00000800u) >> 11; 11233 bfd_vma offset = 0; 11234 11235 offset |= immA << 12; 11236 offset |= immB << 2; 11237 offset |= immC << 1; 11238 /* Sign extend. */ 11239 offset = (offset & 0x40000) ? offset - (1 << 19) : offset; 11240 11241 info->print_address_func (pc + 4 + offset, info); 11242 } 11243 break; 11244 11245 case 'Z': 11246 { 11247 unsigned int immA = (given & 0x00010000u) >> 16; 11248 unsigned int immB = (given & 0x000007feu) >> 1; 11249 unsigned int immC = (given & 0x00000800u) >> 11; 11250 bfd_vma offset = 0; 11251 11252 offset |= immA << 12; 11253 offset |= immB << 2; 11254 offset |= immC << 1; 11255 /* Sign extend. */ 11256 offset = (offset & 0x1000) ? offset - (1 << 13) : offset; 11257 11258 info->print_address_func (pc + 4 + offset, info); 11259 11260 unsigned int T = (given & 0x00020000u) >> 17; 11261 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1); 11262 unsigned int boffset = (T == 1) ? 4 : 2; 11263 func (stream, ", "); 11264 func (stream, "%x", endoffset + boffset); 11265 } 11266 break; 11267 11268 case 'Q': 11269 { 11270 unsigned int immh = (given & 0x000007feu) >> 1; 11271 unsigned int imml = (given & 0x00000800u) >> 11; 11272 bfd_vma imm32 = 0; 11273 11274 imm32 |= immh << 2; 11275 imm32 |= imml << 1; 11276 11277 info->print_address_func (pc + 4 + imm32, info); 11278 } 11279 break; 11280 11281 case 'P': 11282 { 11283 unsigned int immh = (given & 0x000007feu) >> 1; 11284 unsigned int imml = (given & 0x00000800u) >> 11; 11285 bfd_vma imm32 = 0; 11286 11287 imm32 |= immh << 2; 11288 imm32 |= imml << 1; 11289 11290 info->print_address_func (pc + 4 - imm32, info); 11291 } 11292 break; 11293 11294 case 'b': 11295 { 11296 unsigned int S = (given & 0x04000000u) >> 26; 11297 unsigned int J1 = (given & 0x00002000u) >> 13; 11298 unsigned int J2 = (given & 0x00000800u) >> 11; 11299 bfd_vma offset = 0; 11300 11301 offset |= !S << 20; 11302 offset |= J2 << 19; 11303 offset |= J1 << 18; 11304 offset |= (given & 0x003f0000) >> 4; 11305 offset |= (given & 0x000007ff) << 1; 11306 offset -= (1 << 20); 11307 11308 bfd_vma target = pc + 4 + offset; 11309 info->print_address_func (target, info); 11310 11311 /* Fill in instruction information. */ 11312 info->insn_info_valid = 1; 11313 info->insn_type = dis_branch; 11314 info->target = target; 11315 } 11316 break; 11317 11318 case 'B': 11319 { 11320 unsigned int S = (given & 0x04000000u) >> 26; 11321 unsigned int I1 = (given & 0x00002000u) >> 13; 11322 unsigned int I2 = (given & 0x00000800u) >> 11; 11323 bfd_vma offset = 0; 11324 11325 offset |= !S << 24; 11326 offset |= !(I1 ^ S) << 23; 11327 offset |= !(I2 ^ S) << 22; 11328 offset |= (given & 0x03ff0000u) >> 4; 11329 offset |= (given & 0x000007ffu) << 1; 11330 offset -= (1 << 24); 11331 offset += pc + 4; 11332 11333 /* BLX target addresses are always word aligned. */ 11334 if ((given & 0x00001000u) == 0) 11335 offset &= ~2u; 11336 11337 info->print_address_func (offset, info); 11338 11339 /* Fill in instruction information. */ 11340 info->insn_info_valid = 1; 11341 info->insn_type = dis_branch; 11342 info->target = offset; 11343 } 11344 break; 11345 11346 case 's': 11347 { 11348 unsigned int shift = 0; 11349 11350 shift |= (given & 0x000000c0u) >> 6; 11351 shift |= (given & 0x00007000u) >> 10; 11352 if (WRITEBACK_BIT_SET) 11353 func (stream, ", asr #%u", shift); 11354 else if (shift) 11355 func (stream, ", lsl #%u", shift); 11356 /* else print nothing - lsl #0 */ 11357 } 11358 break; 11359 11360 case 'R': 11361 { 11362 unsigned int rot = (given & 0x00000030) >> 4; 11363 11364 if (rot) 11365 func (stream, ", ror #%u", rot * 8); 11366 } 11367 break; 11368 11369 case 'U': 11370 if ((given & 0xf0) == 0x60) 11371 { 11372 switch (given & 0xf) 11373 { 11374 case 0xf: func (stream, "sy"); break; 11375 default: 11376 func (stream, "#%d", (int) given & 0xf); 11377 break; 11378 } 11379 } 11380 else 11381 { 11382 const char * opt = data_barrier_option (given & 0xf); 11383 if (opt != NULL) 11384 func (stream, "%s", opt); 11385 else 11386 func (stream, "#%d", (int) given & 0xf); 11387 } 11388 break; 11389 11390 case 'C': 11391 if ((given & 0xff) == 0) 11392 { 11393 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 11394 if (given & 0x800) 11395 func (stream, "f"); 11396 if (given & 0x400) 11397 func (stream, "s"); 11398 if (given & 0x200) 11399 func (stream, "x"); 11400 if (given & 0x100) 11401 func (stream, "c"); 11402 } 11403 else if ((given & 0x20) == 0x20) 11404 { 11405 char const* name; 11406 unsigned sysm = (given & 0xf00) >> 8; 11407 11408 sysm |= (given & 0x30); 11409 sysm |= (given & 0x00100000) >> 14; 11410 name = banked_regname (sysm); 11411 11412 if (name != NULL) 11413 func (stream, "%s", name); 11414 else 11415 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 11416 } 11417 else 11418 { 11419 func (stream, "%s", psr_name (given & 0xff)); 11420 } 11421 break; 11422 11423 case 'D': 11424 if (((given & 0xff) == 0) 11425 || ((given & 0x20) == 0x20)) 11426 { 11427 char const* name; 11428 unsigned sm = (given & 0xf0000) >> 16; 11429 11430 sm |= (given & 0x30); 11431 sm |= (given & 0x00100000) >> 14; 11432 name = banked_regname (sm); 11433 11434 if (name != NULL) 11435 func (stream, "%s", name); 11436 else 11437 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 11438 } 11439 else 11440 func (stream, "%s", psr_name (given & 0xff)); 11441 break; 11442 11443 case '0': case '1': case '2': case '3': case '4': 11444 case '5': case '6': case '7': case '8': case '9': 11445 { 11446 int width; 11447 unsigned long val; 11448 11449 c = arm_decode_bitfield (c, given, &val, &width); 11450 11451 switch (*c) 11452 { 11453 case 's': 11454 if (val <= 3) 11455 func (stream, "%s", mve_vec_sizename[val]); 11456 else 11457 func (stream, "<undef size>"); 11458 break; 11459 11460 case 'd': 11461 func (stream, "%lu", val); 11462 value_in_comment = val; 11463 break; 11464 11465 case 'D': 11466 func (stream, "%lu", val + 1); 11467 value_in_comment = val + 1; 11468 break; 11469 11470 case 'W': 11471 func (stream, "%lu", val * 4); 11472 value_in_comment = val * 4; 11473 break; 11474 11475 case 'S': 11476 if (val == 13) 11477 is_unpredictable = TRUE; 11478 /* Fall through. */ 11479 case 'R': 11480 if (val == 15) 11481 is_unpredictable = TRUE; 11482 /* Fall through. */ 11483 case 'r': 11484 func (stream, "%s", arm_regnames[val]); 11485 break; 11486 11487 case 'c': 11488 func (stream, "%s", arm_conditional[val]); 11489 break; 11490 11491 case '\'': 11492 c++; 11493 if (val == ((1ul << width) - 1)) 11494 func (stream, "%c", *c); 11495 break; 11496 11497 case '`': 11498 c++; 11499 if (val == 0) 11500 func (stream, "%c", *c); 11501 break; 11502 11503 case '?': 11504 func (stream, "%c", c[(1 << width) - (int) val]); 11505 c += 1 << width; 11506 break; 11507 11508 case 'x': 11509 func (stream, "0x%lx", val & 0xffffffffUL); 11510 break; 11511 11512 default: 11513 abort (); 11514 } 11515 } 11516 break; 11517 11518 case 'L': 11519 /* PR binutils/12534 11520 If we have a PC relative offset in an LDRD or STRD 11521 instructions then display the decoded address. */ 11522 if (((given >> 16) & 0xf) == 0xf) 11523 { 11524 bfd_vma offset = (given & 0xff) * 4; 11525 11526 if ((given & (1 << 23)) == 0) 11527 offset = - offset; 11528 func (stream, "\t; "); 11529 info->print_address_func ((pc & ~3) + 4 + offset, info); 11530 } 11531 break; 11532 11533 default: 11534 abort (); 11535 } 11536 } 11537 11538 if (value_in_comment > 32 || value_in_comment < -16) 11539 func (stream, "\t; 0x%lx", value_in_comment); 11540 11541 if (is_unpredictable) 11542 func (stream, UNPREDICTABLE_INSTRUCTION); 11543 11544 return; 11545 } 11546 11547 /* No match. */ 11548 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 11549 return; 11550 } 11551 11552 /* Print data bytes on INFO->STREAM. */ 11553 11554 static void 11555 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 11556 struct disassemble_info *info, 11557 long given) 11558 { 11559 switch (info->bytes_per_chunk) 11560 { 11561 case 1: 11562 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 11563 break; 11564 case 2: 11565 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 11566 break; 11567 case 4: 11568 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 11569 break; 11570 default: 11571 abort (); 11572 } 11573 } 11574 11575 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 11576 being displayed in symbol relative addresses. 11577 11578 Also disallow private symbol, with __tagsym$$ prefix, 11579 from ARM RVCT toolchain being displayed. */ 11580 11581 bfd_boolean 11582 arm_symbol_is_valid (asymbol * sym, 11583 struct disassemble_info * info ATTRIBUTE_UNUSED) 11584 { 11585 const char * name; 11586 11587 if (sym == NULL) 11588 return FALSE; 11589 11590 name = bfd_asymbol_name (sym); 11591 11592 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 11593 } 11594 11595 /* Parse the string of disassembler options. */ 11596 11597 static void 11598 parse_arm_disassembler_options (const char *options) 11599 { 11600 const char *opt; 11601 11602 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 11603 { 11604 if (CONST_STRNEQ (opt, "reg-names-")) 11605 { 11606 unsigned int i; 11607 for (i = 0; i < NUM_ARM_OPTIONS; i++) 11608 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 11609 { 11610 regname_selected = i; 11611 break; 11612 } 11613 11614 if (i >= NUM_ARM_OPTIONS) 11615 /* xgettext: c-format */ 11616 opcodes_error_handler (_("unrecognised register name set: %s"), 11617 opt); 11618 } 11619 else if (CONST_STRNEQ (opt, "force-thumb")) 11620 force_thumb = 1; 11621 else if (CONST_STRNEQ (opt, "no-force-thumb")) 11622 force_thumb = 0; 11623 else if (CONST_STRNEQ (opt, "coproc")) 11624 { 11625 const char *procptr = opt + sizeof ("coproc") - 1; 11626 char *endptr; 11627 uint8_t coproc_number = strtol (procptr, &endptr, 10); 11628 if (endptr != procptr + 1 || coproc_number > 7) 11629 { 11630 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"), 11631 opt); 11632 continue; 11633 } 11634 if (*endptr != '=') 11635 { 11636 opcodes_error_handler (_("coproc must have an argument: %s"), 11637 opt); 11638 continue; 11639 } 11640 endptr += 1; 11641 if (CONST_STRNEQ (endptr, "generic")) 11642 cde_coprocs &= ~(1 << coproc_number); 11643 else if (CONST_STRNEQ (endptr, "cde") 11644 || CONST_STRNEQ (endptr, "CDE")) 11645 cde_coprocs |= (1 << coproc_number); 11646 else 11647 { 11648 opcodes_error_handler ( 11649 _("coprocN argument takes options \"generic\"," 11650 " \"cde\", or \"CDE\": %s"), opt); 11651 } 11652 } 11653 else 11654 /* xgettext: c-format */ 11655 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 11656 } 11657 11658 return; 11659 } 11660 11661 static bfd_boolean 11662 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 11663 enum map_type *map_symbol); 11664 11665 /* Search back through the insn stream to determine if this instruction is 11666 conditionally executed. */ 11667 11668 static void 11669 find_ifthen_state (bfd_vma pc, 11670 struct disassemble_info *info, 11671 bfd_boolean little) 11672 { 11673 unsigned char b[2]; 11674 unsigned int insn; 11675 int status; 11676 /* COUNT is twice the number of instructions seen. It will be odd if we 11677 just crossed an instruction boundary. */ 11678 int count; 11679 int it_count; 11680 unsigned int seen_it; 11681 bfd_vma addr; 11682 11683 ifthen_address = pc; 11684 ifthen_state = 0; 11685 11686 addr = pc; 11687 count = 1; 11688 it_count = 0; 11689 seen_it = 0; 11690 /* Scan backwards looking for IT instructions, keeping track of where 11691 instruction boundaries are. We don't know if something is actually an 11692 IT instruction until we find a definite instruction boundary. */ 11693 for (;;) 11694 { 11695 if (addr == 0 || info->symbol_at_address_func (addr, info)) 11696 { 11697 /* A symbol must be on an instruction boundary, and will not 11698 be within an IT block. */ 11699 if (seen_it && (count & 1)) 11700 break; 11701 11702 return; 11703 } 11704 addr -= 2; 11705 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 11706 if (status) 11707 return; 11708 11709 if (little) 11710 insn = (b[0]) | (b[1] << 8); 11711 else 11712 insn = (b[1]) | (b[0] << 8); 11713 if (seen_it) 11714 { 11715 if ((insn & 0xf800) < 0xe800) 11716 { 11717 /* Addr + 2 is an instruction boundary. See if this matches 11718 the expected boundary based on the position of the last 11719 IT candidate. */ 11720 if (count & 1) 11721 break; 11722 seen_it = 0; 11723 } 11724 } 11725 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 11726 { 11727 enum map_type type = MAP_ARM; 11728 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 11729 11730 if (!found || (found && type == MAP_THUMB)) 11731 { 11732 /* This could be an IT instruction. */ 11733 seen_it = insn; 11734 it_count = count >> 1; 11735 } 11736 } 11737 if ((insn & 0xf800) >= 0xe800) 11738 count++; 11739 else 11740 count = (count + 2) | 1; 11741 /* IT blocks contain at most 4 instructions. */ 11742 if (count >= 8 && !seen_it) 11743 return; 11744 } 11745 /* We found an IT instruction. */ 11746 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 11747 if ((ifthen_state & 0xf) == 0) 11748 ifthen_state = 0; 11749 } 11750 11751 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 11752 mapping symbol. */ 11753 11754 static int 11755 is_mapping_symbol (struct disassemble_info *info, int n, 11756 enum map_type *map_type) 11757 { 11758 const char *name; 11759 11760 name = bfd_asymbol_name (info->symtab[n]); 11761 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 11762 && (name[2] == 0 || name[2] == '.')) 11763 { 11764 *map_type = ((name[1] == 'a') ? MAP_ARM 11765 : (name[1] == 't') ? MAP_THUMB 11766 : MAP_DATA); 11767 return TRUE; 11768 } 11769 11770 return FALSE; 11771 } 11772 11773 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 11774 Returns nonzero if *MAP_TYPE was set. */ 11775 11776 static int 11777 get_map_sym_type (struct disassemble_info *info, 11778 int n, 11779 enum map_type *map_type) 11780 { 11781 /* If the symbol is in a different section, ignore it. */ 11782 if (info->section != NULL && info->section != info->symtab[n]->section) 11783 return FALSE; 11784 11785 return is_mapping_symbol (info, n, map_type); 11786 } 11787 11788 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 11789 Returns nonzero if *MAP_TYPE was set. */ 11790 11791 static int 11792 get_sym_code_type (struct disassemble_info *info, 11793 int n, 11794 enum map_type *map_type) 11795 { 11796 elf_symbol_type *es; 11797 unsigned int type; 11798 11799 /* If the symbol is in a different section, ignore it. */ 11800 if (info->section != NULL && info->section != info->symtab[n]->section) 11801 return FALSE; 11802 11803 es = *(elf_symbol_type **)(info->symtab + n); 11804 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 11805 11806 /* If the symbol has function type then use that. */ 11807 if (type == STT_FUNC || type == STT_GNU_IFUNC) 11808 { 11809 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 11810 == ST_BRANCH_TO_THUMB) 11811 *map_type = MAP_THUMB; 11812 else 11813 *map_type = MAP_ARM; 11814 return TRUE; 11815 } 11816 11817 return FALSE; 11818 } 11819 11820 /* Search the mapping symbol state for instruction at pc. This is only 11821 applicable for elf target. 11822 11823 There is an assumption Here, info->private_data contains the correct AND 11824 up-to-date information about current scan process. The information will be 11825 used to speed this search process. 11826 11827 Return TRUE if the mapping state can be determined, and map_symbol 11828 will be updated accordingly. Otherwise, return FALSE. */ 11829 11830 static bfd_boolean 11831 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 11832 enum map_type *map_symbol) 11833 { 11834 bfd_vma addr, section_vma = 0; 11835 int n, last_sym = -1; 11836 bfd_boolean found = FALSE; 11837 bfd_boolean can_use_search_opt_p = FALSE; 11838 11839 /* Default to DATA. A text section is required by the ABI to contain an 11840 INSN mapping symbol at the start. A data section has no such 11841 requirement, hence if no mapping symbol is found the section must 11842 contain only data. This however isn't very useful if the user has 11843 fully stripped the binaries. If this is the case use the section 11844 attributes to determine the default. If we have no section default to 11845 INSN as well, as we may be disassembling some raw bytes on a baremetal 11846 HEX file or similar. */ 11847 enum map_type type = MAP_DATA; 11848 if ((info->section && info->section->flags & SEC_CODE) || !info->section) 11849 type = MAP_ARM; 11850 struct arm_private_data *private_data; 11851 11852 if (info->private_data == NULL 11853 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 11854 return FALSE; 11855 11856 private_data = info->private_data; 11857 11858 /* First, look for mapping symbols. */ 11859 if (info->symtab_size != 0) 11860 { 11861 if (pc <= private_data->last_mapping_addr) 11862 private_data->last_mapping_sym = -1; 11863 11864 /* Start scanning at the start of the function, or wherever 11865 we finished last time. */ 11866 n = info->symtab_pos + 1; 11867 11868 /* If the last stop offset is different from the current one it means we 11869 are disassembling a different glob of bytes. As such the optimization 11870 would not be safe and we should start over. */ 11871 can_use_search_opt_p 11872 = private_data->last_mapping_sym >= 0 11873 && info->stop_offset == private_data->last_stop_offset; 11874 11875 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 11876 n = private_data->last_mapping_sym; 11877 11878 /* Look down while we haven't passed the location being disassembled. 11879 The reason for this is that there's no defined order between a symbol 11880 and an mapping symbol that may be at the same address. We may have to 11881 look at least one position ahead. */ 11882 for (; n < info->symtab_size; n++) 11883 { 11884 addr = bfd_asymbol_value (info->symtab[n]); 11885 if (addr > pc) 11886 break; 11887 if (get_map_sym_type (info, n, &type)) 11888 { 11889 last_sym = n; 11890 found = TRUE; 11891 } 11892 } 11893 11894 if (!found) 11895 { 11896 n = info->symtab_pos; 11897 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 11898 n = private_data->last_mapping_sym; 11899 11900 /* No mapping symbol found at this address. Look backwards 11901 for a preceeding one, but don't go pass the section start 11902 otherwise a data section with no mapping symbol can pick up 11903 a text mapping symbol of a preceeding section. The documentation 11904 says section can be NULL, in which case we will seek up all the 11905 way to the top. */ 11906 if (info->section) 11907 section_vma = info->section->vma; 11908 11909 for (; n >= 0; n--) 11910 { 11911 addr = bfd_asymbol_value (info->symtab[n]); 11912 if (addr < section_vma) 11913 break; 11914 11915 if (get_map_sym_type (info, n, &type)) 11916 { 11917 last_sym = n; 11918 found = TRUE; 11919 break; 11920 } 11921 } 11922 } 11923 } 11924 11925 /* If no mapping symbol was found, try looking up without a mapping 11926 symbol. This is done by walking up from the current PC to the nearest 11927 symbol. We don't actually have to loop here since symtab_pos will 11928 contain the nearest symbol already. */ 11929 if (!found) 11930 { 11931 n = info->symtab_pos; 11932 if (n >= 0 && get_sym_code_type (info, n, &type)) 11933 { 11934 last_sym = n; 11935 found = TRUE; 11936 } 11937 } 11938 11939 private_data->last_mapping_sym = last_sym; 11940 private_data->last_type = type; 11941 private_data->last_stop_offset = info->stop_offset; 11942 11943 *map_symbol = type; 11944 return found; 11945 } 11946 11947 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 11948 of the supplied arm_feature_set structure with bitmasks indicating 11949 the supported base architectures and coprocessor extensions. 11950 11951 FIXME: This could more efficiently implemented as a constant array, 11952 although it would also be less robust. */ 11953 11954 static void 11955 select_arm_features (unsigned long mach, 11956 arm_feature_set * features) 11957 { 11958 arm_feature_set arch_fset; 11959 const arm_feature_set fpu_any = FPU_ANY; 11960 11961 #undef ARM_SET_FEATURES 11962 #define ARM_SET_FEATURES(FSET) \ 11963 { \ 11964 const arm_feature_set fset = FSET; \ 11965 arch_fset = fset; \ 11966 } 11967 11968 /* When several architecture versions share the same bfd_mach_arm_XXX value 11969 the most featureful is chosen. */ 11970 switch (mach) 11971 { 11972 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 11973 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 11974 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 11975 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 11976 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 11977 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 11978 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 11979 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 11980 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 11981 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 11982 case bfd_mach_arm_ep9312: 11983 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 11984 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 11985 break; 11986 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 11987 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 11988 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 11989 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 11990 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 11991 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 11992 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 11993 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 11994 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 11995 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 11996 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 11997 case bfd_mach_arm_8: 11998 { 11999 /* Add bits for extensions that Armv8.6-A recognizes. */ 12000 arm_feature_set armv8_6_ext_fset 12001 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 12002 ARM_SET_FEATURES (ARM_ARCH_V8_6A); 12003 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); 12004 break; 12005 } 12006 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; 12007 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 12008 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 12009 case bfd_mach_arm_8_1M_MAIN: 12010 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); 12011 arm_feature_set mve_all 12012 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP); 12013 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all); 12014 force_thumb = 1; 12015 break; 12016 /* If the machine type is unknown allow all architecture types and all 12017 extensions, with the exception of MVE as that clashes with NEON. */ 12018 case bfd_mach_arm_unknown: 12019 ARM_SET_FEATURES (ARM_FEATURE (-1, 12020 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), 12021 -1)); 12022 break; 12023 default: 12024 abort (); 12025 } 12026 #undef ARM_SET_FEATURES 12027 12028 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 12029 and thus on bfd_mach_arm_XXX value. Therefore for a given 12030 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 12031 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 12032 } 12033 12034 12035 /* NOTE: There are no checks in these routines that 12036 the relevant number of data bytes exist. */ 12037 12038 static int 12039 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 12040 { 12041 unsigned char b[4]; 12042 unsigned long given; 12043 int status; 12044 int is_thumb = FALSE; 12045 int is_data = FALSE; 12046 int little_code; 12047 unsigned int size = 4; 12048 void (*printer) (bfd_vma, struct disassemble_info *, long); 12049 bfd_boolean found = FALSE; 12050 struct arm_private_data *private_data; 12051 12052 /* Clear instruction information field. */ 12053 info->insn_info_valid = 0; 12054 info->branch_delay_insns = 0; 12055 info->data_size = 0; 12056 info->insn_type = dis_noninsn; 12057 info->target = 0; 12058 info->target2 = 0; 12059 12060 if (info->disassembler_options) 12061 { 12062 parse_arm_disassembler_options (info->disassembler_options); 12063 12064 /* To avoid repeated parsing of these options, we remove them here. */ 12065 info->disassembler_options = NULL; 12066 } 12067 12068 /* PR 10288: Control which instructions will be disassembled. */ 12069 if (info->private_data == NULL) 12070 { 12071 static struct arm_private_data private; 12072 12073 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 12074 /* If the user did not use the -m command line switch then default to 12075 disassembling all types of ARM instruction. 12076 12077 The info->mach value has to be ignored as this will be based on 12078 the default archictecture for the target and/or hints in the notes 12079 section, but it will never be greater than the current largest arm 12080 machine value (iWMMXt2), which is only equivalent to the V5TE 12081 architecture. ARM architectures have advanced beyond the machine 12082 value encoding, and these newer architectures would be ignored if 12083 the machine value was used. 12084 12085 Ie the -m switch is used to restrict which instructions will be 12086 disassembled. If it is necessary to use the -m switch to tell 12087 objdump that an ARM binary is being disassembled, eg because the 12088 input is a raw binary file, but it is also desired to disassemble 12089 all ARM instructions then use "-marm". This will select the 12090 "unknown" arm architecture which is compatible with any ARM 12091 instruction. */ 12092 info->mach = bfd_mach_arm_unknown; 12093 12094 /* Compute the architecture bitmask from the machine number. 12095 Note: This assumes that the machine number will not change 12096 during disassembly.... */ 12097 select_arm_features (info->mach, & private.features); 12098 12099 private.last_mapping_sym = -1; 12100 private.last_mapping_addr = 0; 12101 private.last_stop_offset = 0; 12102 12103 info->private_data = & private; 12104 } 12105 12106 private_data = info->private_data; 12107 12108 /* Decide if our code is going to be little-endian, despite what the 12109 function argument might say. */ 12110 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 12111 12112 /* For ELF, consult the symbol table to determine what kind of code 12113 or data we have. */ 12114 if (info->symtab_size != 0 12115 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 12116 { 12117 bfd_vma addr; 12118 int n; 12119 int last_sym = -1; 12120 enum map_type type = MAP_ARM; 12121 12122 found = mapping_symbol_for_insn (pc, info, &type); 12123 last_sym = private_data->last_mapping_sym; 12124 12125 is_thumb = (private_data->last_type == MAP_THUMB); 12126 is_data = (private_data->last_type == MAP_DATA); 12127 12128 /* Look a little bit ahead to see if we should print out 12129 two or four bytes of data. If there's a symbol, 12130 mapping or otherwise, after two bytes then don't 12131 print more. */ 12132 if (is_data) 12133 { 12134 size = 4 - (pc & 3); 12135 for (n = last_sym + 1; n < info->symtab_size; n++) 12136 { 12137 addr = bfd_asymbol_value (info->symtab[n]); 12138 if (addr > pc 12139 && (info->section == NULL 12140 || info->section == info->symtab[n]->section)) 12141 { 12142 if (addr - pc < size) 12143 size = addr - pc; 12144 break; 12145 } 12146 } 12147 /* If the next symbol is after three bytes, we need to 12148 print only part of the data, so that we can use either 12149 .byte or .short. */ 12150 if (size == 3) 12151 size = (pc & 1) ? 1 : 2; 12152 } 12153 } 12154 12155 if (info->symbols != NULL) 12156 { 12157 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 12158 { 12159 coff_symbol_type * cs; 12160 12161 cs = coffsymbol (*info->symbols); 12162 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 12163 || cs->native->u.syment.n_sclass == C_THUMBSTAT 12164 || cs->native->u.syment.n_sclass == C_THUMBLABEL 12165 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 12166 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 12167 } 12168 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 12169 && !found) 12170 { 12171 /* If no mapping symbol has been found then fall back to the type 12172 of the function symbol. */ 12173 elf_symbol_type * es; 12174 unsigned int type; 12175 12176 es = *(elf_symbol_type **)(info->symbols); 12177 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12178 12179 is_thumb = 12180 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12181 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 12182 } 12183 else if (bfd_asymbol_flavour (*info->symbols) 12184 == bfd_target_mach_o_flavour) 12185 { 12186 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 12187 12188 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 12189 } 12190 } 12191 12192 if (force_thumb) 12193 is_thumb = TRUE; 12194 12195 if (is_data) 12196 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12197 else 12198 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12199 12200 info->bytes_per_line = 4; 12201 12202 /* PR 10263: Disassemble data if requested to do so by the user. */ 12203 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 12204 { 12205 int i; 12206 12207 /* Size was already set above. */ 12208 info->bytes_per_chunk = size; 12209 printer = print_insn_data; 12210 12211 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 12212 given = 0; 12213 if (little) 12214 for (i = size - 1; i >= 0; i--) 12215 given = b[i] | (given << 8); 12216 else 12217 for (i = 0; i < (int) size; i++) 12218 given = b[i] | (given << 8); 12219 } 12220 else if (!is_thumb) 12221 { 12222 /* In ARM mode endianness is a straightforward issue: the instruction 12223 is four bytes long and is either ordered 0123 or 3210. */ 12224 printer = print_insn_arm; 12225 info->bytes_per_chunk = 4; 12226 size = 4; 12227 12228 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 12229 if (little_code) 12230 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24); 12231 else 12232 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24); 12233 } 12234 else 12235 { 12236 /* In Thumb mode we have the additional wrinkle of two 12237 instruction lengths. Fortunately, the bits that determine 12238 the length of the current instruction are always to be found 12239 in the first two bytes. */ 12240 printer = print_insn_thumb16; 12241 info->bytes_per_chunk = 2; 12242 size = 2; 12243 12244 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 12245 if (little_code) 12246 given = (b[0]) | (b[1] << 8); 12247 else 12248 given = (b[1]) | (b[0] << 8); 12249 12250 if (!status) 12251 { 12252 /* These bit patterns signal a four-byte Thumb 12253 instruction. */ 12254 if ((given & 0xF800) == 0xF800 12255 || (given & 0xF800) == 0xF000 12256 || (given & 0xF800) == 0xE800) 12257 { 12258 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 12259 if (little_code) 12260 given = (b[0]) | (b[1] << 8) | (given << 16); 12261 else 12262 given = (b[1]) | (b[0] << 8) | (given << 16); 12263 12264 printer = print_insn_thumb32; 12265 size = 4; 12266 } 12267 } 12268 12269 if (ifthen_address != pc) 12270 find_ifthen_state (pc, info, little_code); 12271 12272 if (ifthen_state) 12273 { 12274 if ((ifthen_state & 0xf) == 0x8) 12275 ifthen_next_state = 0; 12276 else 12277 ifthen_next_state = (ifthen_state & 0xe0) 12278 | ((ifthen_state & 0xf) << 1); 12279 } 12280 } 12281 12282 if (status) 12283 { 12284 info->memory_error_func (status, pc, info); 12285 return -1; 12286 } 12287 if (info->flags & INSN_HAS_RELOC) 12288 /* If the instruction has a reloc associated with it, then 12289 the offset field in the instruction will actually be the 12290 addend for the reloc. (We are using REL type relocs). 12291 In such cases, we can ignore the pc when computing 12292 addresses, since the addend is not currently pc-relative. */ 12293 pc = 0; 12294 12295 printer (pc, info, given); 12296 12297 if (is_thumb) 12298 { 12299 ifthen_state = ifthen_next_state; 12300 ifthen_address += size; 12301 } 12302 return size; 12303 } 12304 12305 int 12306 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 12307 { 12308 /* Detect BE8-ness and record it in the disassembler info. */ 12309 if (info->flavour == bfd_target_elf_flavour 12310 && info->section != NULL 12311 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 12312 info->endian_code = BFD_ENDIAN_LITTLE; 12313 12314 return print_insn (pc, info, FALSE); 12315 } 12316 12317 int 12318 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 12319 { 12320 return print_insn (pc, info, TRUE); 12321 } 12322 12323 const disasm_options_and_args_t * 12324 disassembler_options_arm (void) 12325 { 12326 static disasm_options_and_args_t *opts_and_args; 12327 12328 if (opts_and_args == NULL) 12329 { 12330 disasm_options_t *opts; 12331 unsigned int i; 12332 12333 opts_and_args = XNEW (disasm_options_and_args_t); 12334 opts_and_args->args = NULL; 12335 12336 opts = &opts_and_args->options; 12337 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12338 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12339 opts->arg = NULL; 12340 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12341 { 12342 opts->name[i] = regnames[i].name; 12343 if (regnames[i].description != NULL) 12344 opts->description[i] = _(regnames[i].description); 12345 else 12346 opts->description[i] = NULL; 12347 } 12348 /* The array we return must be NULL terminated. */ 12349 opts->name[i] = NULL; 12350 opts->description[i] = NULL; 12351 } 12352 12353 return opts_and_args; 12354 } 12355 12356 void 12357 print_arm_disassembler_options (FILE *stream) 12358 { 12359 unsigned int i, max_len = 0; 12360 fprintf (stream, _("\n\ 12361 The following ARM specific disassembler options are supported for use with\n\ 12362 the -M switch:\n")); 12363 12364 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12365 { 12366 unsigned int len = strlen (regnames[i].name); 12367 if (max_len < len) 12368 max_len = len; 12369 } 12370 12371 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 12372 fprintf (stream, " %s%*c %s\n", 12373 regnames[i].name, 12374 (int)(max_len - strlen (regnames[i].name)), ' ', 12375 _(regnames[i].description)); 12376 } 12377
Indexes created Sat May 02 00:23:24 UTC 2026