arm-dis.c revision 1.11
1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2025 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <assert.h> 25 26 #include "disassemble.h" 27 #include "opcode/arm.h" 28 #include "opintl.h" 29 #include "safe-ctype.h" 30 #include "libiberty.h" 31 #include "floatformat.h" 32 33 /* FIXME: This shouldn't be done here. */ 34 #include "coff/internal.h" 35 #include "libcoff.h" 36 #include "bfd.h" 37 #include "elf-bfd.h" 38 #include "elf/internal.h" 39 #include "elf/arm.h" 40 #include "mach-o.h" 41 42 /* Cached mapping symbol state. */ 43 enum map_type 44 { 45 MAP_ARM, 46 MAP_THUMB, 47 MAP_DATA 48 }; 49 50 struct arm_private_data 51 { 52 /* The features to use when disassembling optional instructions. */ 53 arm_feature_set features; 54 55 /* Track the last type (although this doesn't seem to be useful) */ 56 enum map_type last_type; 57 58 /* Tracking symbol table information */ 59 int last_mapping_sym; 60 61 /* The end range of the current range being disassembled. */ 62 bfd_vma last_stop_offset; 63 bfd_vma last_mapping_addr; 64 }; 65 66 enum mve_instructions 67 { 68 MVE_VPST, 69 MVE_VPT_FP_T1, 70 MVE_VPT_FP_T2, 71 MVE_VPT_VEC_T1, 72 MVE_VPT_VEC_T2, 73 MVE_VPT_VEC_T3, 74 MVE_VPT_VEC_T4, 75 MVE_VPT_VEC_T5, 76 MVE_VPT_VEC_T6, 77 MVE_VCMP_FP_T1, 78 MVE_VCMP_FP_T2, 79 MVE_VCMP_VEC_T1, 80 MVE_VCMP_VEC_T2, 81 MVE_VCMP_VEC_T3, 82 MVE_VCMP_VEC_T4, 83 MVE_VCMP_VEC_T5, 84 MVE_VCMP_VEC_T6, 85 MVE_VDUP, 86 MVE_VEOR, 87 MVE_VFMAS_FP_SCALAR, 88 MVE_VFMA_FP_SCALAR, 89 MVE_VFMA_FP, 90 MVE_VFMS_FP, 91 MVE_VHADD_T1, 92 MVE_VHADD_T2, 93 MVE_VHSUB_T1, 94 MVE_VHSUB_T2, 95 MVE_VRHADD, 96 MVE_VLD2, 97 MVE_VLD4, 98 MVE_VST2, 99 MVE_VST4, 100 MVE_VLDRB_T1, 101 MVE_VLDRH_T2, 102 MVE_VLDRB_T5, 103 MVE_VLDRH_T6, 104 MVE_VLDRW_T7, 105 MVE_VSTRB_T1, 106 MVE_VSTRH_T2, 107 MVE_VSTRB_T5, 108 MVE_VSTRH_T6, 109 MVE_VSTRW_T7, 110 MVE_VLDRB_GATHER_T1, 111 MVE_VLDRH_GATHER_T2, 112 MVE_VLDRW_GATHER_T3, 113 MVE_VLDRD_GATHER_T4, 114 MVE_VLDRW_GATHER_T5, 115 MVE_VLDRD_GATHER_T6, 116 MVE_VSTRB_SCATTER_T1, 117 MVE_VSTRH_SCATTER_T2, 118 MVE_VSTRW_SCATTER_T3, 119 MVE_VSTRD_SCATTER_T4, 120 MVE_VSTRW_SCATTER_T5, 121 MVE_VSTRD_SCATTER_T6, 122 MVE_VCVT_FP_FIX_VEC, 123 MVE_VCVT_BETWEEN_FP_INT, 124 MVE_VCVT_FP_HALF_FP, 125 MVE_VCVT_FROM_FP_TO_INT, 126 MVE_VRINT_FP, 127 MVE_VMOV_HFP_TO_GP, 128 MVE_VMOV_GP_TO_VEC_LANE, 129 MVE_VMOV_IMM_TO_VEC, 130 MVE_VMOV_VEC_TO_VEC, 131 MVE_VMOV2_VEC_LANE_TO_GP, 132 MVE_VMOV2_GP_TO_VEC_LANE, 133 MVE_VMOV_VEC_LANE_TO_GP, 134 MVE_VMVN_IMM, 135 MVE_VMVN_REG, 136 MVE_VORR_IMM, 137 MVE_VORR_REG, 138 MVE_VORN, 139 MVE_VBIC_IMM, 140 MVE_VBIC_REG, 141 MVE_VMOVX, 142 MVE_VMOVL, 143 MVE_VMOVN, 144 MVE_VMULL_INT, 145 MVE_VMULL_POLY, 146 MVE_VQDMULL_T1, 147 MVE_VQDMULL_T2, 148 MVE_VQMOVN, 149 MVE_VQMOVUN, 150 MVE_VADDV, 151 MVE_VMLADAV_T1, 152 MVE_VMLADAV_T2, 153 MVE_VMLALDAV, 154 MVE_VMLAS, 155 MVE_VADDLV, 156 MVE_VMLSDAV_T1, 157 MVE_VMLSDAV_T2, 158 MVE_VMLSLDAV, 159 MVE_VRMLALDAVH, 160 MVE_VRMLSLDAVH, 161 MVE_VQDMLADH, 162 MVE_VQRDMLADH, 163 MVE_VQDMLAH, 164 MVE_VQRDMLAH, 165 MVE_VQDMLASH, 166 MVE_VQRDMLASH, 167 MVE_VQDMLSDH, 168 MVE_VQRDMLSDH, 169 MVE_VQDMULH_T1, 170 MVE_VQRDMULH_T2, 171 MVE_VQDMULH_T3, 172 MVE_VQRDMULH_T4, 173 MVE_VDDUP, 174 MVE_VDWDUP, 175 MVE_VIWDUP, 176 MVE_VIDUP, 177 MVE_VCADD_FP, 178 MVE_VCADD_VEC, 179 MVE_VHCADD, 180 MVE_VCMLA_FP, 181 MVE_VCMUL_FP, 182 MVE_VQRSHL_T1, 183 MVE_VQRSHL_T2, 184 MVE_VQRSHRN, 185 MVE_VQRSHRUN, 186 MVE_VQSHL_T1, 187 MVE_VQSHL_T2, 188 MVE_VQSHLU_T3, 189 MVE_VQSHL_T4, 190 MVE_VQSHRN, 191 MVE_VQSHRUN, 192 MVE_VRSHL_T1, 193 MVE_VRSHL_T2, 194 MVE_VRSHR, 195 MVE_VRSHRN, 196 MVE_VSHL_T1, 197 MVE_VSHL_T2, 198 MVE_VSHL_T3, 199 MVE_VSHLC, 200 MVE_VSHLL_T1, 201 MVE_VSHLL_T2, 202 MVE_VSHR, 203 MVE_VSHRN, 204 MVE_VSLI, 205 MVE_VSRI, 206 MVE_VADC, 207 MVE_VABAV, 208 MVE_VABD_FP, 209 MVE_VABD_VEC, 210 MVE_VABS_FP, 211 MVE_VABS_VEC, 212 MVE_VADD_FP_T1, 213 MVE_VADD_FP_T2, 214 MVE_VADD_VEC_T1, 215 MVE_VADD_VEC_T2, 216 MVE_VSBC, 217 MVE_VSUB_FP_T1, 218 MVE_VSUB_FP_T2, 219 MVE_VSUB_VEC_T1, 220 MVE_VSUB_VEC_T2, 221 MVE_VAND, 222 MVE_VBRSR, 223 MVE_VCLS, 224 MVE_VCLZ, 225 MVE_VCTP, 226 MVE_VMAX, 227 MVE_VMAXA, 228 MVE_VMAXNM_FP, 229 MVE_VMAXNMA_FP, 230 MVE_VMAXNMV_FP, 231 MVE_VMAXNMAV_FP, 232 MVE_VMAXV, 233 MVE_VMAXAV, 234 MVE_VMIN, 235 MVE_VMINA, 236 MVE_VMINNM_FP, 237 MVE_VMINNMA_FP, 238 MVE_VMINNMV_FP, 239 MVE_VMINNMAV_FP, 240 MVE_VMINV, 241 MVE_VMINAV, 242 MVE_VMLA, 243 MVE_VMUL_FP_T1, 244 MVE_VMUL_FP_T2, 245 MVE_VMUL_VEC_T1, 246 MVE_VMUL_VEC_T2, 247 MVE_VMULH, 248 MVE_VRMULH, 249 MVE_VNEG_FP, 250 MVE_VNEG_VEC, 251 MVE_VPNOT, 252 MVE_VPSEL, 253 MVE_VQABS, 254 MVE_VQADD_T1, 255 MVE_VQADD_T2, 256 MVE_VQSUB_T1, 257 MVE_VQSUB_T2, 258 MVE_VQNEG, 259 MVE_VREV16, 260 MVE_VREV32, 261 MVE_VREV64, 262 MVE_LSLL, 263 MVE_LSLLI, 264 MVE_LSRL, 265 MVE_ASRL, 266 MVE_ASRLI, 267 MVE_SQRSHRL, 268 MVE_SQRSHR, 269 MVE_UQRSHL, 270 MVE_UQRSHLL, 271 MVE_UQSHL, 272 MVE_UQSHLL, 273 MVE_URSHRL, 274 MVE_URSHR, 275 MVE_SRSHRL, 276 MVE_SRSHR, 277 MVE_SQSHLL, 278 MVE_SQSHL, 279 MVE_CINC, 280 MVE_CINV, 281 MVE_CNEG, 282 MVE_CSINC, 283 MVE_CSINV, 284 MVE_CSET, 285 MVE_CSETM, 286 MVE_CSNEG, 287 MVE_CSEL, 288 MVE_NONE 289 }; 290 291 enum mve_unpredictable 292 { 293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. 294 */ 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and 296 fcB = 1 (vpt). */ 297 UNPRED_R13, /* Unpredictable because r13 (sp) or 298 r15 (sp) used. */ 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ 300 UNPRED_Q_GT_4, /* Unpredictable because 301 vec reg start > 4 (vld4/st4). */ 302 UNPRED_Q_GT_6, /* Unpredictable because 303 vec reg start > 6 (vld2/st2). */ 304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 305 and WB bit = 1. */ 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are 307 equal. */ 308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */ 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the 310 same. */ 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and 312 size = 1. */ 313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and 314 size = 2. */ 315 UNPRED_NONE /* No unpredictable behavior. */ 316 }; 317 318 enum mve_undefined 319 { 320 UNDEF_SIZE, /* undefined size. */ 321 UNDEF_SIZE_0, /* undefined because size == 0. */ 322 UNDEF_SIZE_2, /* undefined because size == 2. */ 323 UNDEF_SIZE_3, /* undefined because size == 3. */ 324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ 327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ 328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and 329 size == 0. */ 330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and 331 size == 1. */ 332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */ 334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and 336 op1 == (0 or 1). */ 337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and 338 op2 == 0 and op1 == (0 or 1). */ 339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode 340 in {0xx1, x0x1}. */ 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ 342 UNDEF_NONE /* no undefined behavior. */ 343 }; 344 345 struct opcode32 346 { 347 arm_feature_set arch; /* Architecture defining this insn. */ 348 unsigned long value; /* If arch is 0 then value is a sentinel. */ 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 350 const char * assembler; /* How to disassemble this insn. */ 351 }; 352 353 struct cdeopcode32 354 { 355 arm_feature_set arch; /* Architecture defining this insn. */ 356 uint8_t coproc_shift; /* coproc is this far into op. */ 357 uint16_t coproc_mask; /* Length of coproc field in op. */ 358 unsigned long value; /* If arch is 0 then value is a sentinel. */ 359 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 360 const char * assembler; /* How to disassemble this insn. */ 361 }; 362 363 /* MVE opcodes. */ 364 365 struct mopcode32 366 { 367 arm_feature_set arch; /* Architecture defining this insn. */ 368 enum mve_instructions mve_op; /* Specific mve instruction for faster 369 decoding. */ 370 unsigned long value; /* If arch is 0 then value is a sentinel. */ 371 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 372 const char * assembler; /* How to disassemble this insn. */ 373 }; 374 375 enum isa { 376 ANY, 377 T32, 378 ARM 379 }; 380 381 382 /* Shared (between Arm and Thumb mode) opcode. */ 383 struct sopcode32 384 { 385 enum isa isa; /* Execution mode instruction availability. */ 386 arm_feature_set arch; /* Architecture defining this insn. */ 387 unsigned long value; /* If arch is 0 then value is a sentinel. */ 388 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 389 const char * assembler; /* How to disassemble this insn. */ 390 }; 391 392 struct opcode16 393 { 394 arm_feature_set arch; /* Architecture defining this insn. */ 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 396 const char *assembler; /* How to disassemble this insn. */ 397 }; 398 399 /* print_insn_coprocessor recognizes the following format control codes: 400 401 %% % 402 403 %c print condition code (always bits 28-31 in ARM mode) 404 %b print condition code allowing cp_num == 9 405 %q print shifter argument 406 %u print condition code (unconditional in ARM mode, 407 UNPREDICTABLE if not AL in Thumb) 408 %A print address for ldc/stc instruction 409 %B print vstm/vldm register list 410 %C print vscclrm register list 411 %J print register for VLDR instruction 412 %K print address for VLDR instruction 413 414 %<bitfield>c print as a condition code (for vsel) 415 %<bitfield>r print as an ARM register 416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 417 %<bitfield>ru as %<>r but each u register must be unique. 418 %<bitfield>d print the bitfield in decimal 419 %<bitfield>k print immediate for VFPv3 conversion instruction 420 %<bitfield>x print the bitfield in hex 421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 422 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 423 %<bitfield>g print as an iWMMXt 64-bit register 424 %<bitfield>G print as an iWMMXt general purpose or control register 425 %<bitfield>D print as a NEON D register 426 %<bitfield>Q print as a NEON Q register 427 %<bitfield>V print as a NEON D or Q register 428 %<bitfield>E print a quarter-float immediate value 429 430 %y<code> print a single precision VFP reg. 431 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 432 %z<code> print a double precision VFP reg 433 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 434 435 %<bitfield>'c print specified char iff bitfield is all ones 436 %<bitfield>`c print specified char iff bitfield is all zeroes 437 %<bitfield>?ab... select from array of values in big endian order 438 439 %L print as an iWMMXt N/M width field. 440 %Z print the Immediate of a WSHUFH instruction. 441 %l like 'A' except use byte offsets for 'B' & 'H' 442 versions. 443 %i print 5-bit immediate in bits 8,3..0 444 (print "32" when 0) 445 %r print register offset address for wldt/wstr instruction. */ 446 447 enum opcode_sentinel_enum 448 { 449 SENTINEL_IWMMXT_START = 1, 450 SENTINEL_IWMMXT_END, 451 SENTINEL_GENERIC_START 452 } opcode_sentinels; 453 454 #define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x" 455 #define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x" 456 #define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x" 457 #define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>" 458 459 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 460 461 /* print_insn_cde recognizes the following format control codes: 462 463 %% % 464 465 %a print 'a' iff bit 28 is 1 466 %p print bits 8-10 as coprocessor 467 %<bitfield>d print as decimal 468 %<bitfield>r print as an ARM register 469 %<bitfield>n print as an ARM register but r15 is APSR_nzcv 470 %<bitfield>T print as an ARM register + 1 471 %<bitfield>R as %r but r13 is UNPREDICTABLE 472 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE 473 %j print immediate taken from bits (16..21,7,0..5) 474 %k print immediate taken from bits (20..21,7,0..5). 475 %l print immediate taken from bits (20..22,7,4..5). */ 476 477 /* At the moment there is only one valid position for the coprocessor number, 478 and hence that's encoded in the macro below. */ 479 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ 480 { ARCH, 8, 7, VALUE, MASK, ASM } 481 static const struct cdeopcode32 cde_opcodes[] = 482 { 483 /* Custom Datapath Extension instructions. */ 484 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 485 0xee000000, 0xefc00840, 486 "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"), 487 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 488 0xee000040, 0xefc00840, 489 "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"), 490 491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 492 0xee400000, 0xefc00840, 493 "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"), 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 495 0xee400040, 0xefc00840, 496 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"), 497 498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 499 0xee800000, 0xef800840, 500 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 502 0xee800040, 0xef800840, 503 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), 504 505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 506 0xec200000, 0xeeb00840, 507 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"), 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 509 0xec200040, 0xeeb00840, 510 "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"), 511 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 513 0xec300000, 0xeeb00840, 514 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"), 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 516 0xec300040, 0xeeb00840, 517 "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"), 518 519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 520 0xec800000, 0xee800840, 521 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"), 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 523 0xec800040, 0xee800840, 524 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"), 525 526 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) 527 528 }; 529 530 static const struct sopcode32 coprocessor_opcodes[] = 531 { 532 /* XScale instructions. */ 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 534 0x0e200010, 0x0fff0ff0, 535 "mia%c\t%{R:acc0%}, %0-3r, %12-15r"}, 536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 537 0x0e280010, 0x0fff0ff0, 538 "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"}, 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 540 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"}, 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 542 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"}, 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 544 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"}, 545 546 /* Intel Wireless MMX technology instructions. */ 547 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 549 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 551 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 553 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"}, 554 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 555 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"}, 556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 557 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"}, 558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 559 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 561 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 563 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 565 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 567 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 569 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 571 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 573 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 575 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 577 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 579 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 581 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 583 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 585 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 587 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 589 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"}, 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 591 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 593 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 595 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 597 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 599 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 601 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 603 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 605 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 607 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 609 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 611 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 613 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 615 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 617 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"}, 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 619 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 621 0x0e800120, 0x0f800ff0, 622 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 624 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 626 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 628 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 630 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 632 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 633 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 634 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 636 0x0e8000a0, 0x0f800ff0, 637 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 639 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 641 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 643 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 644 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 645 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 646 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 647 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 648 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 649 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 650 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 651 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 652 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 653 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 654 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 655 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"}, 656 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 657 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 658 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 659 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 660 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 661 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 662 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 663 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 665 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 667 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 669 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 671 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 673 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 675 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 677 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 679 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 681 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 683 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 685 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 687 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 689 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 691 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 693 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 695 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 697 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 699 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 700 {ANY, ARM_FEATURE_CORE_LOW (0), 701 SENTINEL_IWMMXT_END, 0, "" }, 702 703 /* Armv8.1-M Mainline instructions. */ 704 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 705 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, 706 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 707 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, 708 709 /* ARMv8-M Mainline Security Extensions instructions. */ 710 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 711 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 712 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 713 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 714 715 /* Register load/store. */ 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 717 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 719 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 721 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 722 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 723 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 724 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 725 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 726 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 727 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 728 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 729 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 730 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 731 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 733 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 735 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 737 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 739 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 741 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 743 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 745 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 747 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 748 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 749 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, 750 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 751 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, 752 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 754 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 756 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 758 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 760 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, 761 762 /* Data transfer between ARM and NEON registers. */ 763 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 764 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 765 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 766 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 767 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 768 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"}, 769 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 770 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"}, 771 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 772 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"}, 773 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 774 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"}, 775 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 776 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"}, 777 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 778 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"}, 779 /* Half-precision conversion instructions. */ 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 781 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 782 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 783 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 785 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 787 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 788 789 /* Floating point coprocessor (VFP) instructions. */ 790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 791 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"}, 792 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 793 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"}, 794 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 795 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"}, 796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 797 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"}, 798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 799 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"}, 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 801 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"}, 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 803 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"}, 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 805 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"}, 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 807 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"}, 808 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 809 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"}, 810 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 811 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"}, 812 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 813 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"}, 814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 815 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"}, 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 817 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"}, 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 819 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"}, 820 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 821 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"}, 822 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 823 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"}, 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 825 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"}, 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 827 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"}, 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 829 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"}, 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 831 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"}, 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 833 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"}, 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 835 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"}, 836 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 837 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"}, 838 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 839 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"}, 840 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 841 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"}, 842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 843 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"}, 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 845 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"}, 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 847 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"}, 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 849 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 851 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 853 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 855 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 856 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 857 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"}, 858 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 859 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"}, 860 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 861 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 862 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 863 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 865 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 867 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 869 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 871 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 873 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 875 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 877 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 879 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 881 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 883 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 885 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 887 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 889 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 891 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"}, 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 893 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 895 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 897 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"}, 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 899 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"}, 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 901 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 903 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"}, 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 905 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"}, 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 907 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 909 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 911 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 913 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 915 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 917 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 919 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 921 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 923 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 925 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 927 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 929 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 931 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 933 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 935 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 937 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 939 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 941 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 943 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 945 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 947 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 948 949 /* VFP Fused multiply add instructions. */ 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 951 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 953 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 955 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 957 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 959 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 961 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 963 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 965 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 966 967 /* FP v5. */ 968 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 969 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 970 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 971 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 972 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 973 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 974 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 975 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 976 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 977 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 978 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 979 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 980 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 981 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 982 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 983 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 984 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 985 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 986 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 987 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 988 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 989 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 990 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 991 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 992 993 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 994 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 995 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 996 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, 997 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 998 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, 999 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1000 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, 1001 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1002 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, 1003 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1004 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, 1005 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1006 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, 1007 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1008 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"}, 1009 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1010 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"}, 1011 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1012 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"}, 1013 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1014 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"}, 1015 1016 /* BFloat16 instructions. */ 1017 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1018 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, 1019 1020 /* Dot Product instructions in the space of coprocessor 13. */ 1021 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1022 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 1023 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1024 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"}, 1025 1026 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 1027 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1028 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, 1029 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1030 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, 1031 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1032 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, 1033 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1034 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, 1035 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1036 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, 1037 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1038 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, 1039 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1040 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, 1041 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1042 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, 1043 1044 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 1045 cp_num: bit <11:8> == 0b1001. 1046 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 1047 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1048 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 1049 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1050 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 1051 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1052 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 1053 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1054 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"}, 1055 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1056 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, 1057 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1058 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"}, 1059 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1060 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 1061 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1062 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 1063 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1064 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 1065 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1066 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 1067 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1068 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 1069 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1070 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 1071 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1072 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 1073 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1074 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 1075 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1076 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 1077 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1078 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 1079 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1080 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 1081 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1082 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 1083 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1084 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 1085 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1086 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1088 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1090 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1092 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1094 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1096 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"}, 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1098 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1100 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1102 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1103 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1104 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1105 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1106 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1107 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1108 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1109 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1110 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1111 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1112 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1113 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1114 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1115 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1116 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1117 1118 /* ARMv8.3 javascript conversion instruction. */ 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1120 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1121 1122 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1123 }; 1124 1125 /* Generic coprocessor instructions. These are only matched if a more specific 1126 SIMD or co-processor instruction does not match first. */ 1127 1128 static const struct sopcode32 generic_coprocessor_opcodes[] = 1129 { 1130 /* Generic coprocessor instructions. */ 1131 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1132 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"}, 1133 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1134 0x0c500000, 0x0ff00000, 1135 "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, 1136 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1137 0x0e000000, 0x0f000010, 1138 "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1139 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1140 0x0e10f010, 0x0f10f010, 1141 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1142 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1143 0x0e100010, 0x0f100010, 1144 "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1145 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1146 0x0e000010, 0x0f100010, 1147 "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1148 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1149 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1150 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1151 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1152 1153 /* V6 coprocessor instructions. */ 1154 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1155 0xfc500000, 0xfff00000, 1156 "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, 1157 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1158 0xfc400000, 0xfff00000, 1159 "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"}, 1160 1161 /* V5 coprocessor instructions. */ 1162 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1163 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1164 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1165 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, 1166 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1167 0xfe000000, 0xff000010, 1168 "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1169 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1170 0xfe000010, 0xff100010, 1171 "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1172 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1173 0xfe100010, 0xff100010, 1174 "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, 1175 1176 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1177 }; 1178 1179 /* Neon opcode table: This does not encode the top byte -- that is 1180 checked by the print_insn_neon routine, as it depends on whether we are 1181 doing thumb32 or arm32 disassembly. */ 1182 1183 /* print_insn_neon recognizes the following format control codes: 1184 1185 %% % 1186 1187 %c print condition code 1188 %u print condition code (unconditional in ARM mode, 1189 UNPREDICTABLE if not AL in Thumb) 1190 %A print v{st,ld}[1234] operands 1191 %B print v{st,ld}[1234] any one operands 1192 %C print v{st,ld}[1234] single->all operands 1193 %D print scalar 1194 %E print vmov, vmvn, vorr, vbic encoded constant 1195 %F print vtbl,vtbx register list 1196 1197 %<bitfield>r print as an ARM register 1198 %<bitfield>d print the bitfield in decimal 1199 %<bitfield>e print the 2^N - bitfield in decimal 1200 %<bitfield>D print as a NEON D register 1201 %<bitfield>Q print as a NEON Q register 1202 %<bitfield>R print as a NEON D or Q register 1203 %<bitfield>Sn print byte scaled width limited by n 1204 %<bitfield>Tn print short scaled width limited by n 1205 %<bitfield>Un print long scaled width limited by n 1206 1207 %<bitfield>'c print specified char iff bitfield is all ones 1208 %<bitfield>`c print specified char iff bitfield is all zeroes 1209 %<bitfield>?ab... select from array of values in big endian order. */ 1210 1211 static const struct opcode32 neon_opcodes[] = 1212 { 1213 /* Extract. */ 1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1215 0xf2b00840, 0xffb00850, 1216 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, 1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1218 0xf2b00000, 0xffb00810, 1219 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, 1220 1221 /* Data transfer between ARM and NEON registers. */ 1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1223 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1225 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1227 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1229 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1231 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1233 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 1234 1235 /* Move data element to all lanes. */ 1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1237 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"}, 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1239 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"}, 1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1241 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"}, 1242 1243 /* Table lookup. */ 1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1245 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1247 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1248 1249 /* Half-precision conversions. */ 1250 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1251 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1252 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1253 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1254 1255 /* NEON fused multiply add instructions. */ 1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1257 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1259 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1261 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1262 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1263 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1264 1265 /* BFloat16 instructions. */ 1266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1267 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1269 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1271 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1273 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, 1274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1275 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1277 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"}, 1278 1279 /* Matrix Multiply instructions. */ 1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1281 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1283 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1285 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1287 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1289 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1290 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1291 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, 1292 1293 /* Two registers, miscellaneous. */ 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1295 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1297 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1299 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1301 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1302 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1303 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1304 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1305 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1306 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1307 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1308 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1309 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1310 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1311 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1312 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1313 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1314 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1315 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1317 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1319 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1321 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1323 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1325 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1327 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1329 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1331 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1333 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1335 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1337 0xf3b20300, 0xffb30fd0, 1338 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"}, 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1340 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1342 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1344 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1345 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1346 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1348 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1350 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1352 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1354 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1356 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1358 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1360 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1362 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1364 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1366 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1368 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1370 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1372 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1374 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1376 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1378 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1380 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1382 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1386 0xf3bb0600, 0xffbf0e10, 1387 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1388 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1389 0xf3b70600, 0xffbf0e10, 1390 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1391 1392 /* Three registers of the same length. */ 1393 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1394 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1395 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1396 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1397 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1398 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1399 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1400 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1401 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1402 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1403 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1404 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1405 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1406 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1408 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1410 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1412 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1414 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1416 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1418 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1420 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1422 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1424 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1426 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1428 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1430 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1432 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1434 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1436 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1437 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1438 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1440 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1442 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1444 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1446 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1448 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1449 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1450 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1452 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1454 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1456 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1458 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1460 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1462 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1464 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1466 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1468 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1470 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1472 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1473 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1474 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1476 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1478 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1480 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1482 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1484 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1486 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1488 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1490 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1492 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1494 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1496 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1497 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1498 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1500 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1502 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1504 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1506 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1508 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1510 0xf2000b00, 0xff800f10, 1511 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf2000b10, 0xff800f10, 1514 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1516 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1518 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1520 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1522 0xf3000b00, 0xff800f10, 1523 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1525 0xf2000000, 0xfe800f10, 1526 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1528 0xf2000010, 0xfe800f10, 1529 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1531 0xf2000100, 0xfe800f10, 1532 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1534 0xf2000200, 0xfe800f10, 1535 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1537 0xf2000210, 0xfe800f10, 1538 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1540 0xf2000300, 0xfe800f10, 1541 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1543 0xf2000310, 0xfe800f10, 1544 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1546 0xf2000400, 0xfe800f10, 1547 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1549 0xf2000410, 0xfe800f10, 1550 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1552 0xf2000500, 0xfe800f10, 1553 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2000510, 0xfe800f10, 1556 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2000600, 0xfe800f10, 1559 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1561 0xf2000610, 0xfe800f10, 1562 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2000700, 0xfe800f10, 1565 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf2000710, 0xfe800f10, 1568 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1570 0xf2000910, 0xfe800f10, 1571 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1573 0xf2000a00, 0xfe800f10, 1574 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2000a10, 0xfe800f10, 1577 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1579 0xf3000b10, 0xff800f10, 1580 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1582 0xf3000c10, 0xff800f10, 1583 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1584 1585 /* One register and an immediate value. */ 1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1587 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1589 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1593 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1595 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1599 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1601 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1603 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1607 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1609 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1612 1613 /* Two registers and a shift amount. */ 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1615 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1617 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1619 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1621 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1625 0xf2880950, 0xfeb80fd0, 1626 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1628 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"}, 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1630 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1632 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1634 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1636 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1638 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1640 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1642 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1644 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1646 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1648 0xf2900950, 0xfeb00fd0, 1649 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1651 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"}, 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1653 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1657 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1659 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1661 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1663 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1665 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1667 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1669 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1671 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1673 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1675 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"}, 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1677 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1679 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1681 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1683 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1685 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1687 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1689 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1691 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1693 0xf2a00950, 0xfea00fd0, 1694 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, 1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1696 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1698 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1700 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1702 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1704 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1706 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1708 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1710 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1712 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1714 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1716 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1718 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1720 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1722 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1724 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1726 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1728 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, 1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1730 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, 1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1732 0xf2a00e10, 0xfea00e90, 1733 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1735 0xf2a00c10, 0xfea00e90, 1736 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, 1737 1738 /* Three registers of different lengths. */ 1739 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1740 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1742 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1744 0xf2800400, 0xff800f50, 1745 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1747 0xf2800600, 0xff800f50, 1748 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1750 0xf2800900, 0xff800f50, 1751 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1753 0xf2800b00, 0xff800f50, 1754 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1756 0xf2800d00, 0xff800f50, 1757 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1759 0xf3800400, 0xff800f50, 1760 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1762 0xf3800600, 0xff800f50, 1763 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1765 0xf2800000, 0xfe800f50, 1766 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1768 0xf2800100, 0xfe800f50, 1769 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1771 0xf2800200, 0xfe800f50, 1772 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1774 0xf2800300, 0xfe800f50, 1775 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1777 0xf2800500, 0xfe800f50, 1778 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1780 0xf2800700, 0xfe800f50, 1781 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1783 0xf2800800, 0xfe800f50, 1784 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1786 0xf2800a00, 0xfe800f50, 1787 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1789 0xf2800c00, 0xfe800f50, 1790 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1791 1792 /* Two registers and a scalar. */ 1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1794 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1796 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1797 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1798 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1800 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1802 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1804 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1805 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1806 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1808 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1810 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1812 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1813 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1814 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1816 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1818 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1820 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1822 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1824 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1825 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1826 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1828 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1830 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1831 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1832 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1834 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1836 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1837 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1838 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1840 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1842 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1844 0xf2800240, 0xfe800f50, 1845 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1847 0xf2800640, 0xfe800f50, 1848 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1850 0xf2800a40, 0xfe800f50, 1851 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1853 0xf2800e40, 0xff800f50, 1854 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1856 0xf2800f40, 0xff800f50, 1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1859 0xf3800e40, 0xff800f50, 1860 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1862 0xf3800f40, 0xff800f50, 1863 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1864 }, 1865 1866 /* Element and structure load/store. */ 1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1868 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1870 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1872 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1874 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1876 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1878 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1880 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1882 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1884 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1886 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1888 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1890 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1892 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1894 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1896 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1898 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1900 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1902 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1904 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1905 1906 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1907 }; 1908 1909 /* mve opcode table. */ 1910 1911 /* print_insn_mve recognizes the following format control codes: 1912 1913 %% % 1914 1915 %a print '+' or '-' or imm offset in vldr[bhwd] and 1916 vstr[bhwd] 1917 %c print condition code 1918 %d print addr mode of MVE vldr[bhw] and vstr[bhw] 1919 %u print 'U' (unsigned) or 'S' for various mve instructions 1920 %i print MVE predicate(s) for vpt and vpst 1921 %j print a 5-bit immediate from hw2[14:12,7:6] 1922 %k print 48 if the 7th position bit is set else print 64. 1923 %m print rounding mode for vcvt and vrint 1924 %n print vector comparison code for predicated instruction 1925 %s print size for various vcvt instructions 1926 %v print vector predicate for instruction in predicated 1927 block 1928 %o print offset scaled for vldr[hwd] and vstr[hwd] 1929 %w print writeback mode for MVE v{st,ld}[24] 1930 %B print v{st,ld}[24] any one operands 1931 %E print vmov, vmvn, vorr, vbic encoded constant 1932 %N print generic index for vmov 1933 %T print bottom ('b') or top ('t') of source register 1934 %X print exchange field in vmla* instructions 1935 1936 %<bitfield>r print as an ARM register 1937 %<bitfield>d print the bitfield in decimal 1938 %<bitfield>A print accumulate or not 1939 %<bitfield>c print bitfield as a condition code 1940 %<bitfield>C print bitfield as an inverted condition code 1941 %<bitfield>Q print as a MVE Q register 1942 %<bitfield>F print as a MVE S register 1943 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is 1944 UNPREDICTABLE 1945 1946 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE 1947 %<bitfield>s print size for vector predicate & non VMOV instructions 1948 %<bitfield>I print carry flag or not 1949 %<bitfield>i print immediate for vstr/vldr reg +/- imm 1950 %<bitfield>h print high half of 64-bit destination reg 1951 %<bitfield>k print immediate for vector conversion instruction 1952 %<bitfield>l print low half of 64-bit destination reg 1953 %<bitfield>o print rotate value for vcmul 1954 %<bitfield>u print immediate value for vddup/vdwdup 1955 %<bitfield>x print the bitfield in hex. 1956 */ 1957 1958 static const struct mopcode32 mve_opcodes[] = 1959 { 1960 /* MVE. */ 1961 1962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 1963 MVE_VPST, 1964 0xfe310f4d, 0xffbf1fff, 1965 "vpst%i" 1966 }, 1967 1968 /* Floating point VPT T1. */ 1969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 1970 MVE_VPT_FP_T1, 1971 0xee310f00, 0xefb10f50, 1972 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, 1973 /* Floating point VPT T2. */ 1974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 1975 MVE_VPT_FP_T2, 1976 0xee310f40, 0xefb10f50, 1977 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, 1978 1979 /* Vector VPT T1. */ 1980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 1981 MVE_VPT_VEC_T1, 1982 0xfe010f00, 0xff811f51, 1983 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 1984 /* Vector VPT T2. */ 1985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 1986 MVE_VPT_VEC_T2, 1987 0xfe010f01, 0xff811f51, 1988 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 1989 /* Vector VPT T3. */ 1990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 1991 MVE_VPT_VEC_T3, 1992 0xfe011f00, 0xff811f50, 1993 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 1994 /* Vector VPT T4. */ 1995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 1996 MVE_VPT_VEC_T4, 1997 0xfe010f40, 0xff811f70, 1998 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, 1999 /* Vector VPT T5. */ 2000 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2001 MVE_VPT_VEC_T5, 2002 0xfe010f60, 0xff811f70, 2003 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2004 /* Vector VPT T6. */ 2005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2006 MVE_VPT_VEC_T6, 2007 0xfe011f40, 0xff811f50, 2008 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2009 2010 /* Vector VBIC immediate. */ 2011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2012 MVE_VBIC_IMM, 2013 0xef800070, 0xefb81070, 2014 "vbic%v.i%8-11s\t%13-15,22Q, %E"}, 2015 2016 /* Vector VBIC register. */ 2017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2018 MVE_VBIC_REG, 2019 0xef100150, 0xffb11f51, 2020 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2021 2022 /* Vector VABAV. */ 2023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2024 MVE_VABAV, 2025 0xee800f01, 0xefc10f51, 2026 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, 2027 2028 /* Vector VABD floating point. */ 2029 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2030 MVE_VABD_FP, 2031 0xff200d40, 0xffa11f51, 2032 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2033 2034 /* Vector VABD. */ 2035 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2036 MVE_VABD_VEC, 2037 0xef000740, 0xef811f51, 2038 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2039 2040 /* Vector VABS floating point. */ 2041 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2042 MVE_VABS_FP, 2043 0xFFB10740, 0xFFB31FD1, 2044 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2045 /* Vector VABS. */ 2046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2047 MVE_VABS_VEC, 2048 0xffb10340, 0xffb31fd1, 2049 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2050 2051 /* Vector VADD floating point T1. */ 2052 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2053 MVE_VADD_FP_T1, 2054 0xef000d40, 0xffa11f51, 2055 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2056 /* Vector VADD floating point T2. */ 2057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2058 MVE_VADD_FP_T2, 2059 0xee300f40, 0xefb11f70, 2060 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2061 /* Vector VADD T1. */ 2062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2063 MVE_VADD_VEC_T1, 2064 0xef000840, 0xff811f51, 2065 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2066 /* Vector VADD T2. */ 2067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2068 MVE_VADD_VEC_T2, 2069 0xee010f40, 0xff811f70, 2070 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2071 2072 /* Vector VADDLV. */ 2073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2074 MVE_VADDLV, 2075 0xee890f00, 0xef8f1fd1, 2076 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, 2077 2078 /* Vector VADDV. */ 2079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2080 MVE_VADDV, 2081 0xeef10f00, 0xeff31fd1, 2082 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, 2083 2084 /* Vector VADC. */ 2085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2086 MVE_VADC, 2087 0xee300f00, 0xffb10f51, 2088 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2089 2090 /* Vector VAND. */ 2091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2092 MVE_VAND, 2093 0xef000150, 0xffb11f51, 2094 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2095 2096 /* Vector VBRSR register. */ 2097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2098 MVE_VBRSR, 2099 0xfe011e60, 0xff811f70, 2100 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2101 2102 /* Vector VCADD floating point. */ 2103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2104 MVE_VCADD_FP, 2105 0xfc800840, 0xfea11f51, 2106 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"}, 2107 2108 /* Vector VCADD. */ 2109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2110 MVE_VCADD_VEC, 2111 0xfe000f00, 0xff810f51, 2112 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, 2113 2114 /* Vector VCLS. */ 2115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2116 MVE_VCLS, 2117 0xffb00440, 0xffb31fd1, 2118 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2119 2120 /* Vector VCLZ. */ 2121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2122 MVE_VCLZ, 2123 0xffb004c0, 0xffb31fd1, 2124 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2125 2126 /* Vector VCMLA. */ 2127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2128 MVE_VCMLA_FP, 2129 0xfc200840, 0xfe211f51, 2130 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"}, 2131 2132 /* Vector VCMP floating point T1. */ 2133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2134 MVE_VCMP_FP_T1, 2135 0xee310f00, 0xeff1ef50, 2136 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2137 2138 /* Vector VCMP floating point T2. */ 2139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2140 MVE_VCMP_FP_T2, 2141 0xee310f40, 0xeff1ef50, 2142 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, 2143 2144 /* Vector VCMP T1. */ 2145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2146 MVE_VCMP_VEC_T1, 2147 0xfe010f00, 0xffc1ff51, 2148 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2149 /* Vector VCMP T2. */ 2150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2151 MVE_VCMP_VEC_T2, 2152 0xfe010f01, 0xffc1ff51, 2153 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2154 /* Vector VCMP T3. */ 2155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2156 MVE_VCMP_VEC_T3, 2157 0xfe011f00, 0xffc1ff50, 2158 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2159 /* Vector VCMP T4. */ 2160 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2161 MVE_VCMP_VEC_T4, 2162 0xfe010f40, 0xffc1ff70, 2163 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2164 /* Vector VCMP T5. */ 2165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2166 MVE_VCMP_VEC_T5, 2167 0xfe010f60, 0xffc1ff70, 2168 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2169 /* Vector VCMP T6. */ 2170 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2171 MVE_VCMP_VEC_T6, 2172 0xfe011f40, 0xffc1ff50, 2173 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2174 2175 /* Vector VDUP. */ 2176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2177 MVE_VDUP, 2178 0xeea00b10, 0xffb10f5f, 2179 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2180 2181 /* Vector VEOR. */ 2182 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2183 MVE_VEOR, 2184 0xff000150, 0xffd11f51, 2185 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2186 2187 /* Vector VFMA, vector * scalar. */ 2188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2189 MVE_VFMA_FP_SCALAR, 2190 0xee310e40, 0xefb11f70, 2191 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2192 2193 /* Vector VFMA floating point. */ 2194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2195 MVE_VFMA_FP, 2196 0xef000c50, 0xffa11f51, 2197 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2198 2199 /* Vector VFMS floating point. */ 2200 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2201 MVE_VFMS_FP, 2202 0xef200c50, 0xffa11f51, 2203 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2204 2205 /* Vector VFMAS, vector * scalar. */ 2206 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2207 MVE_VFMAS_FP_SCALAR, 2208 0xee311e40, 0xefb11f70, 2209 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2210 2211 /* Vector VHADD T1. */ 2212 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2213 MVE_VHADD_T1, 2214 0xef000040, 0xef811f51, 2215 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2216 2217 /* Vector VHADD T2. */ 2218 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2219 MVE_VHADD_T2, 2220 0xee000f40, 0xef811f70, 2221 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2222 2223 /* Vector VHSUB T1. */ 2224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2225 MVE_VHSUB_T1, 2226 0xef000240, 0xef811f51, 2227 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2228 2229 /* Vector VHSUB T2. */ 2230 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2231 MVE_VHSUB_T2, 2232 0xee001f40, 0xef811f70, 2233 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2234 2235 /* Vector VCMUL. */ 2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2237 MVE_VCMUL_FP, 2238 0xee300e00, 0xefb10f50, 2239 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"}, 2240 2241 /* Vector VCTP. */ 2242 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2243 MVE_VCTP, 2244 0xf000e801, 0xffc0ffff, 2245 "vctp%v.%20-21s\t%16-19r"}, 2246 2247 /* Vector VDUP. */ 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2249 MVE_VDUP, 2250 0xeea00b10, 0xffb10f5f, 2251 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2252 2253 /* Vector VRHADD. */ 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2255 MVE_VRHADD, 2256 0xef000140, 0xef811f51, 2257 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2258 2259 /* Vector VCVT. */ 2260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2261 MVE_VCVT_FP_FIX_VEC, 2262 0xef800c50, 0xef801cd1, 2263 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"}, 2264 2265 /* Vector VCVT. */ 2266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2267 MVE_VCVT_BETWEEN_FP_INT, 2268 0xffb30640, 0xffb31e51, 2269 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2270 2271 /* Vector VCVT between single and half-precision float, bottom half. */ 2272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2273 MVE_VCVT_FP_HALF_FP, 2274 0xee3f0e01, 0xefbf1fd1, 2275 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, 2276 2277 /* Vector VCVT between single and half-precision float, top half. */ 2278 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2279 MVE_VCVT_FP_HALF_FP, 2280 0xee3f1e01, 0xefbf1fd1, 2281 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2282 2283 /* Vector VCVT. */ 2284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2285 MVE_VCVT_FROM_FP_TO_INT, 2286 0xffb30040, 0xffb31c51, 2287 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, 2288 2289 /* Vector VDDUP. */ 2290 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2291 MVE_VDDUP, 2292 0xee011f6e, 0xff811f7e, 2293 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, 2294 2295 /* Vector VDWDUP. */ 2296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2297 MVE_VDWDUP, 2298 0xee011f60, 0xff811f70, 2299 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, 2300 2301 /* Vector VHCADD. */ 2302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2303 MVE_VHCADD, 2304 0xee000f00, 0xff810f51, 2305 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, 2306 2307 /* Vector VIWDUP. */ 2308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2309 MVE_VIWDUP, 2310 0xee010f60, 0xff811f70, 2311 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, 2312 2313 /* Vector VIDUP. */ 2314 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2315 MVE_VIDUP, 2316 0xee010f6e, 0xff811f7e, 2317 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, 2318 2319 /* Vector VLD2. */ 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2321 MVE_VLD2, 2322 0xfc901e00, 0xff901e5f, 2323 "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, 2324 2325 /* Vector VLD4. */ 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2327 MVE_VLD4, 2328 0xfc901e01, 0xff901e1f, 2329 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, 2330 2331 /* Vector VLDRB gather load. */ 2332 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2333 MVE_VLDRB_GATHER_T1, 2334 0xec900e00, 0xefb01e50, 2335 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 2336 2337 /* Vector VLDRH gather load. */ 2338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2339 MVE_VLDRH_GATHER_T2, 2340 0xec900e10, 0xefb01e50, 2341 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2342 2343 /* Vector VLDRW gather load. */ 2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2345 MVE_VLDRW_GATHER_T3, 2346 0xfc900f40, 0xffb01fd0, 2347 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2348 2349 /* Vector VLDRD gather load. */ 2350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2351 MVE_VLDRD_GATHER_T4, 2352 0xec900fd0, 0xefb01fd0, 2353 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2354 2355 /* Vector VLDRW gather load. */ 2356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2357 MVE_VLDRW_GATHER_T5, 2358 0xfd101e00, 0xff111f00, 2359 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 2360 2361 /* Vector VLDRD gather load, variant T6. */ 2362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2363 MVE_VLDRD_GATHER_T6, 2364 0xfd101f00, 0xff111f00, 2365 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 2366 2367 /* Vector VLDRB. */ 2368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2369 MVE_VLDRB_T1, 2370 0xec100e00, 0xee581e00, 2371 "vldrb%v.%u%7-8s\t%13-15Q, %d"}, 2372 2373 /* Vector VLDRH. */ 2374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2375 MVE_VLDRH_T2, 2376 0xec180e00, 0xee581e00, 2377 "vldrh%v.%u%7-8s\t%13-15Q, %d"}, 2378 2379 /* Vector VLDRB unsigned, variant T5. */ 2380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2381 MVE_VLDRB_T5, 2382 0xec101e00, 0xfe101f80, 2383 "vldrb%v.u8\t%13-15,22Q, %d"}, 2384 2385 /* Vector VLDRH unsigned, variant T6. */ 2386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2387 MVE_VLDRH_T6, 2388 0xec101e80, 0xfe101f80, 2389 "vldrh%v.u16\t%13-15,22Q, %d"}, 2390 2391 /* Vector VLDRW unsigned, variant T7. */ 2392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2393 MVE_VLDRW_T7, 2394 0xec101f00, 0xfe101f80, 2395 "vldrw%v.u32\t%13-15,22Q, %d"}, 2396 2397 /* Vector VMAX. */ 2398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2399 MVE_VMAX, 2400 0xef000640, 0xef811f51, 2401 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2402 2403 /* Vector VMAXA. */ 2404 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2405 MVE_VMAXA, 2406 0xee330e81, 0xffb31fd1, 2407 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2408 2409 /* Vector VMAXNM floating point. */ 2410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2411 MVE_VMAXNM_FP, 2412 0xff000f50, 0xffa11f51, 2413 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2414 2415 /* Vector VMAXNMA floating point. */ 2416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2417 MVE_VMAXNMA_FP, 2418 0xee3f0e81, 0xefbf1fd1, 2419 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2420 2421 /* Vector VMAXNMV floating point. */ 2422 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2423 MVE_VMAXNMV_FP, 2424 0xeeee0f00, 0xefff0fd1, 2425 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2426 2427 /* Vector VMAXNMAV floating point. */ 2428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2429 MVE_VMAXNMAV_FP, 2430 0xeeec0f00, 0xefff0fd1, 2431 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2432 2433 /* Vector VMAXV. */ 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2435 MVE_VMAXV, 2436 0xeee20f00, 0xeff30fd1, 2437 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2438 2439 /* Vector VMAXAV. */ 2440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2441 MVE_VMAXAV, 2442 0xeee00f00, 0xfff30fd1, 2443 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2444 2445 /* Vector VMIN. */ 2446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2447 MVE_VMIN, 2448 0xef000650, 0xef811f51, 2449 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2450 2451 /* Vector VMINA. */ 2452 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2453 MVE_VMINA, 2454 0xee331e81, 0xffb31fd1, 2455 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2456 2457 /* Vector VMINNM floating point. */ 2458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2459 MVE_VMINNM_FP, 2460 0xff200f50, 0xffa11f51, 2461 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2462 2463 /* Vector VMINNMA floating point. */ 2464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2465 MVE_VMINNMA_FP, 2466 0xee3f1e81, 0xefbf1fd1, 2467 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2468 2469 /* Vector VMINNMV floating point. */ 2470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2471 MVE_VMINNMV_FP, 2472 0xeeee0f80, 0xefff0fd1, 2473 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2474 2475 /* Vector VMINNMAV floating point. */ 2476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2477 MVE_VMINNMAV_FP, 2478 0xeeec0f80, 0xefff0fd1, 2479 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2480 2481 /* Vector VMINV. */ 2482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2483 MVE_VMINV, 2484 0xeee20f80, 0xeff30fd1, 2485 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2486 2487 /* Vector VMINAV. */ 2488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2489 MVE_VMINAV, 2490 0xeee00f80, 0xfff30fd1, 2491 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2492 2493 /* Vector VMLA. */ 2494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2495 MVE_VMLA, 2496 0xee010e40, 0xef811f70, 2497 "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2498 2499 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction 2500 opcode aliasing. */ 2501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2502 MVE_VMLALDAV, 2503 0xee801e00, 0xef801f51, 2504 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2505 2506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2507 MVE_VMLALDAV, 2508 0xee800e00, 0xef801f51, 2509 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2510 2511 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ 2512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2513 MVE_VMLADAV_T1, 2514 0xeef00e00, 0xeff01f51, 2515 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2516 2517 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ 2518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2519 MVE_VMLADAV_T2, 2520 0xeef00f00, 0xeff11f51, 2521 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2522 2523 /* Vector VMLADAV T1 variant. */ 2524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2525 MVE_VMLADAV_T1, 2526 0xeef01e00, 0xeff01f51, 2527 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2528 2529 /* Vector VMLADAV T2 variant. */ 2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2531 MVE_VMLADAV_T2, 2532 0xeef01f00, 0xeff11f51, 2533 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2534 2535 /* Vector VMLAS. */ 2536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2537 MVE_VMLAS, 2538 0xee011e40, 0xef811f70, 2539 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2540 2541 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction 2542 opcode aliasing. */ 2543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2544 MVE_VRMLSLDAVH, 2545 0xfe800e01, 0xff810f51, 2546 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2547 2548 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction 2549 opcdoe aliasing. */ 2550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2551 MVE_VMLSLDAV, 2552 0xee800e01, 0xff800f51, 2553 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2554 2555 /* Vector VMLSDAV T1 Variant. */ 2556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2557 MVE_VMLSDAV_T1, 2558 0xeef00e01, 0xfff00f51, 2559 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2560 2561 /* Vector VMLSDAV T2 Variant. */ 2562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2563 MVE_VMLSDAV_T2, 2564 0xfef00e01, 0xfff10f51, 2565 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, 2566 2567 /* Vector VMOV between gpr and half precision register, op == 0. */ 2568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2569 MVE_VMOV_HFP_TO_GP, 2570 0xee000910, 0xfff00f7f, 2571 "vmov.f16\t%7,16-19F, %12-15r"}, 2572 2573 /* Vector VMOV between gpr and half precision register, op == 1. */ 2574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2575 MVE_VMOV_HFP_TO_GP, 2576 0xee100910, 0xfff00f7f, 2577 "vmov.f16\t%12-15r, %7,16-19F"}, 2578 2579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2580 MVE_VMOV_GP_TO_VEC_LANE, 2581 0xee000b10, 0xff900f1f, 2582 "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"}, 2583 2584 /* Vector VORR immediate to vector. 2585 NOTE: MVE_VORR_IMM must appear in the table 2586 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2588 MVE_VORR_IMM, 2589 0xef800050, 0xefb810f0, 2590 "vorr%v.i%8-11s\t%13-15,22Q, %E"}, 2591 2592 /* Vector VQSHL T2 Variant. 2593 NOTE: MVE_VQSHL_T2 must appear in the table before 2594 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2596 MVE_VQSHL_T2, 2597 0xef800750, 0xef801fd1, 2598 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2599 2600 /* Vector VQSHLU T3 Variant 2601 NOTE: MVE_VQSHL_T2 must appear in the table before 2602 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2603 2604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2605 MVE_VQSHLU_T3, 2606 0xff800650, 0xff801fd1, 2607 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2608 2609 /* Vector VRSHR 2610 NOTE: MVE_VRSHR must appear in the table before 2611 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2613 MVE_VRSHR, 2614 0xef800250, 0xef801fd1, 2615 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2616 2617 /* Vector VSHL. 2618 NOTE: MVE_VSHL must appear in the table before 2619 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2620 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2621 MVE_VSHL_T1, 2622 0xef800550, 0xff801fd1, 2623 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2624 2625 /* Vector VSHR 2626 NOTE: MVE_VSHR must appear in the table before 2627 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2629 MVE_VSHR, 2630 0xef800050, 0xef801fd1, 2631 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2632 2633 /* Vector VSLI 2634 NOTE: MVE_VSLI must appear in the table before 2635 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2637 MVE_VSLI, 2638 0xff800550, 0xff801fd1, 2639 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2640 2641 /* Vector VSRI 2642 NOTE: MVE_VSRI must appear in the table before 2643 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2645 MVE_VSRI, 2646 0xff800450, 0xff801fd1, 2647 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2648 2649 /* Vector VMOV immediate to vector, 2650 undefinded for cmode == 1111 */ 2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2652 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, 2653 2654 /* Vector VMOV immediate to vector, 2655 cmode == 1101 */ 2656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2657 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, 2658 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2659 2660 /* Vector VMOV immediate to vector. */ 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2662 MVE_VMOV_IMM_TO_VEC, 2663 0xef800050, 0xefb810d0, 2664 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2665 2666 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2668 MVE_VMOV2_VEC_LANE_TO_GP, 2669 0xec000f00, 0xffb01ff0, 2670 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"}, 2671 2672 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2674 MVE_VMOV2_VEC_LANE_TO_GP, 2675 0xec000f10, 0xffb01ff0, 2676 "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"}, 2677 2678 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2680 MVE_VMOV2_GP_TO_VEC_LANE, 2681 0xec100f00, 0xffb01ff0, 2682 "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"}, 2683 2684 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2686 MVE_VMOV2_GP_TO_VEC_LANE, 2687 0xec100f10, 0xffb01ff0, 2688 "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"}, 2689 2690 /* Vector VMOV Vector lane to gpr. */ 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2692 MVE_VMOV_VEC_LANE_TO_GP, 2693 0xee100b10, 0xff100f1f, 2694 "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"}, 2695 2696 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due 2697 to instruction opcode aliasing. */ 2698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2699 MVE_VSHLL_T1, 2700 0xeea00f40, 0xefa00fd1, 2701 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2702 2703 /* Vector VMOVL long. */ 2704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2705 MVE_VMOVL, 2706 0xeea00f40, 0xefa70fd1, 2707 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, 2708 2709 /* Vector VMOV and narrow. */ 2710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2711 MVE_VMOVN, 2712 0xfe310e81, 0xffb30fd1, 2713 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2714 2715 /* Floating point move extract. */ 2716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2717 MVE_VMOVX, 2718 0xfeb00a40, 0xffbf0fd0, 2719 "vmovx.f16\t%22,12-15F, %5,0-3F"}, 2720 2721 /* Vector VMUL floating-point T1 variant. */ 2722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2723 MVE_VMUL_FP_T1, 2724 0xff000d50, 0xffa11f51, 2725 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2726 2727 /* Vector VMUL floating-point T2 variant. */ 2728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2729 MVE_VMUL_FP_T2, 2730 0xee310e60, 0xefb11f70, 2731 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2732 2733 /* Vector VMUL T1 variant. */ 2734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2735 MVE_VMUL_VEC_T1, 2736 0xef000950, 0xff811f51, 2737 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2738 2739 /* Vector VMUL T2 variant. */ 2740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2741 MVE_VMUL_VEC_T2, 2742 0xee011e60, 0xff811f70, 2743 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2744 2745 /* Vector VMULH. */ 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2747 MVE_VMULH, 2748 0xee010e01, 0xef811f51, 2749 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2750 2751 /* Vector VRMULH. */ 2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2753 MVE_VRMULH, 2754 0xee011e01, 0xef811f51, 2755 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2756 2757 /* Vector VMULL integer. */ 2758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2759 MVE_VMULL_INT, 2760 0xee010e00, 0xef810f51, 2761 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2762 2763 /* Vector VMULL polynomial. */ 2764 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2765 MVE_VMULL_POLY, 2766 0xee310e00, 0xefb10f51, 2767 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2768 2769 /* Vector VMVN immediate to vector. */ 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2771 MVE_VMVN_IMM, 2772 0xef800070, 0xefb810f0, 2773 "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, 2774 2775 /* Vector VMVN register. */ 2776 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2777 MVE_VMVN_REG, 2778 0xffb005c0, 0xffbf1fd1, 2779 "vmvn%v\t%13-15,22Q, %1-3,5Q"}, 2780 2781 /* Vector VNEG floating point. */ 2782 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2783 MVE_VNEG_FP, 2784 0xffb107c0, 0xffb31fd1, 2785 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2786 2787 /* Vector VNEG. */ 2788 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2789 MVE_VNEG_VEC, 2790 0xffb103c0, 0xffb31fd1, 2791 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2792 2793 /* Vector VORN, vector bitwise or not. */ 2794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2795 MVE_VORN, 2796 0xef300150, 0xffb11f51, 2797 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2798 2799 /* Vector VORR register. */ 2800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2801 MVE_VORR_REG, 2802 0xef200150, 0xffb11f51, 2803 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2804 2805 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if 2806 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen 2807 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes 2808 array. */ 2809 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2811 MVE_VMOV_VEC_TO_VEC, 2812 0xef200150, 0xffb11f51, 2813 "vmov%v\t%13-15,22Q, %17-19,7Q"}, 2814 2815 /* Vector VQDMULL T1 variant. */ 2816 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2817 MVE_VQDMULL_T1, 2818 0xee300f01, 0xefb10f51, 2819 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2820 2821 /* Vector VPNOT. */ 2822 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2823 MVE_VPNOT, 2824 0xfe310f4d, 0xffffffff, 2825 "vpnot%v"}, 2826 2827 /* Vector VPSEL. */ 2828 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2829 MVE_VPSEL, 2830 0xfe310f01, 0xffb11f51, 2831 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2832 2833 /* Vector VQABS. */ 2834 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2835 MVE_VQABS, 2836 0xffb00740, 0xffb31fd1, 2837 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2838 2839 /* Vector VQADD T1 variant. */ 2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2841 MVE_VQADD_T1, 2842 0xef000050, 0xef811f51, 2843 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2844 2845 /* Vector VQADD T2 variant. */ 2846 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2847 MVE_VQADD_T2, 2848 0xee000f60, 0xef811f70, 2849 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2850 2851 /* Vector VQDMULL T2 variant. */ 2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2853 MVE_VQDMULL_T2, 2854 0xee300f60, 0xefb10f70, 2855 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2856 2857 /* Vector VQMOVN. */ 2858 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2859 MVE_VQMOVN, 2860 0xee330e01, 0xefb30fd1, 2861 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, 2862 2863 /* Vector VQMOVUN. */ 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2865 MVE_VQMOVUN, 2866 0xee310e81, 0xffb30fd1, 2867 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2868 2869 /* Vector VQDMLADH. */ 2870 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2871 MVE_VQDMLADH, 2872 0xee000e00, 0xff810f51, 2873 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2874 2875 /* Vector VQRDMLADH. */ 2876 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2877 MVE_VQRDMLADH, 2878 0xee000e01, 0xff810f51, 2879 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2880 2881 /* Vector VQDMLAH. */ 2882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2883 MVE_VQDMLAH, 2884 0xee000e60, 0xff811f70, 2885 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2886 2887 /* Vector VQRDMLAH. */ 2888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2889 MVE_VQRDMLAH, 2890 0xee000e40, 0xff811f70, 2891 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2892 2893 /* Vector VQDMLASH. */ 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2895 MVE_VQDMLASH, 2896 0xee001e60, 0xff811f70, 2897 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2898 2899 /* Vector VQRDMLASH. */ 2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2901 MVE_VQRDMLASH, 2902 0xee001e40, 0xff811f70, 2903 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2904 2905 /* Vector VQDMLSDH. */ 2906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2907 MVE_VQDMLSDH, 2908 0xfe000e00, 0xff810f51, 2909 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2910 2911 /* Vector VQRDMLSDH. */ 2912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2913 MVE_VQRDMLSDH, 2914 0xfe000e01, 0xff810f51, 2915 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2916 2917 /* Vector VQDMULH T1 variant. */ 2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2919 MVE_VQDMULH_T1, 2920 0xef000b40, 0xff811f51, 2921 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2922 2923 /* Vector VQRDMULH T2 variant. */ 2924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2925 MVE_VQRDMULH_T2, 2926 0xff000b40, 0xff811f51, 2927 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2928 2929 /* Vector VQDMULH T3 variant. */ 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2931 MVE_VQDMULH_T3, 2932 0xee010e60, 0xff811f70, 2933 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2934 2935 /* Vector VQRDMULH T4 variant. */ 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2937 MVE_VQRDMULH_T4, 2938 0xfe010e60, 0xff811f70, 2939 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2940 2941 /* Vector VQNEG. */ 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2943 MVE_VQNEG, 2944 0xffb007c0, 0xffb31fd1, 2945 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2946 2947 /* Vector VQRSHL T1 variant. */ 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2949 MVE_VQRSHL_T1, 2950 0xef000550, 0xef811f51, 2951 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 2952 2953 /* Vector VQRSHL T2 variant. */ 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2955 MVE_VQRSHL_T2, 2956 0xee331ee0, 0xefb31ff0, 2957 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 2958 2959 /* Vector VQRSHRN. */ 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2961 MVE_VQRSHRN, 2962 0xee800f41, 0xefa00fd1, 2963 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2964 2965 /* Vector VQRSHRUN. */ 2966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2967 MVE_VQRSHRUN, 2968 0xfe800fc0, 0xffa00fd1, 2969 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2970 2971 /* Vector VQSHL T1 Variant. */ 2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2973 MVE_VQSHL_T1, 2974 0xee311ee0, 0xefb31ff0, 2975 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 2976 2977 /* Vector VQSHL T4 Variant. */ 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2979 MVE_VQSHL_T4, 2980 0xef000450, 0xef811f51, 2981 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 2982 2983 /* Vector VQSHRN. */ 2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2985 MVE_VQSHRN, 2986 0xee800f40, 0xefa00fd1, 2987 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2988 2989 /* Vector VQSHRUN. */ 2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2991 MVE_VQSHRUN, 2992 0xee800fc0, 0xffa00fd1, 2993 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 2994 2995 /* Vector VQSUB T1 Variant. */ 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2997 MVE_VQSUB_T1, 2998 0xef000250, 0xef811f51, 2999 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3000 3001 /* Vector VQSUB T2 Variant. */ 3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3003 MVE_VQSUB_T2, 3004 0xee001f60, 0xef811f70, 3005 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3006 3007 /* Vector VREV16. */ 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3009 MVE_VREV16, 3010 0xffb00140, 0xffb31fd1, 3011 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"}, 3012 3013 /* Vector VREV32. */ 3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3015 MVE_VREV32, 3016 0xffb000c0, 0xffb31fd1, 3017 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3018 3019 /* Vector VREV64. */ 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3021 MVE_VREV64, 3022 0xffb00040, 0xffb31fd1, 3023 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3024 3025 /* Vector VRINT floating point. */ 3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3027 MVE_VRINT_FP, 3028 0xffb20440, 0xffb31c51, 3029 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3030 3031 /* Vector VRMLALDAVH. */ 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3033 MVE_VRMLALDAVH, 3034 0xee800f00, 0xef811f51, 3035 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3036 3037 /* Vector VRMLALDAVH. */ 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3039 MVE_VRMLALDAVH, 3040 0xee801f00, 0xef811f51, 3041 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3042 3043 /* Vector VRSHL T1 Variant. */ 3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3045 MVE_VRSHL_T1, 3046 0xef000540, 0xef811f51, 3047 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3048 3049 /* Vector VRSHL T2 Variant. */ 3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3051 MVE_VRSHL_T2, 3052 0xee331e60, 0xefb31ff0, 3053 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3054 3055 /* Vector VRSHRN. */ 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3057 MVE_VRSHRN, 3058 0xfe800fc1, 0xffa00fd1, 3059 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3060 3061 /* Vector VSBC. */ 3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3063 MVE_VSBC, 3064 0xfe300f00, 0xffb10f51, 3065 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3066 3067 /* Vector VSHL T2 Variant. */ 3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3069 MVE_VSHL_T2, 3070 0xee311e60, 0xefb31ff0, 3071 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3072 3073 /* Vector VSHL T3 Variant. */ 3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3075 MVE_VSHL_T3, 3076 0xef000440, 0xef811f51, 3077 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3078 3079 /* Vector VSHLC. */ 3080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3081 MVE_VSHLC, 3082 0xeea00fc0, 0xffa01ff0, 3083 "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"}, 3084 3085 /* Vector VSHLL T2 Variant. */ 3086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3087 MVE_VSHLL_T2, 3088 0xee310e01, 0xefb30fd1, 3089 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"}, 3090 3091 /* Vector VSHRN. */ 3092 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3093 MVE_VSHRN, 3094 0xee800fc1, 0xffa00fd1, 3095 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, 3096 3097 /* Vector VST2 no writeback. */ 3098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3099 MVE_VST2, 3100 0xfc801e00, 0xffb01e5f, 3101 "vst2%5d.%7-8s\t%B, [%16-19r]"}, 3102 3103 /* Vector VST2 writeback. */ 3104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3105 MVE_VST2, 3106 0xfca01e00, 0xffb01e5f, 3107 "vst2%5d.%7-8s\t%B, [%16-19r]!"}, 3108 3109 /* Vector VST4 no writeback. */ 3110 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3111 MVE_VST4, 3112 0xfc801e01, 0xffb01e1f, 3113 "vst4%5-6d.%7-8s\t%B, [%16-19r]"}, 3114 3115 /* Vector VST4 writeback. */ 3116 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3117 MVE_VST4, 3118 0xfca01e01, 0xffb01e1f, 3119 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"}, 3120 3121 /* Vector VSTRB scatter store, T1 variant. */ 3122 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3123 MVE_VSTRB_SCATTER_T1, 3124 0xec800e00, 0xffb01e50, 3125 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 3126 3127 /* Vector VSTRH scatter store, T2 variant. */ 3128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3129 MVE_VSTRH_SCATTER_T2, 3130 0xec800e10, 0xffb01e50, 3131 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3132 3133 /* Vector VSTRW scatter store, T3 variant. */ 3134 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3135 MVE_VSTRW_SCATTER_T3, 3136 0xec800e40, 0xffb01e50, 3137 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3138 3139 /* Vector VSTRD scatter store, T4 variant. */ 3140 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3141 MVE_VSTRD_SCATTER_T4, 3142 0xec800fd0, 0xffb01fd0, 3143 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3144 3145 /* Vector VSTRW scatter store, T5 variant. */ 3146 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3147 MVE_VSTRW_SCATTER_T5, 3148 0xfd001e00, 0xff111f00, 3149 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 3150 3151 /* Vector VSTRD scatter store, T6 variant. */ 3152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3153 MVE_VSTRD_SCATTER_T6, 3154 0xfd001f00, 0xff111f00, 3155 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, 3156 3157 /* Vector VSTRB. */ 3158 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3159 MVE_VSTRB_T1, 3160 0xec000e00, 0xfe581e00, 3161 "vstrb%v.%7-8s\t%13-15Q, %d"}, 3162 3163 /* Vector VSTRH. */ 3164 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3165 MVE_VSTRH_T2, 3166 0xec080e00, 0xfe581e00, 3167 "vstrh%v.%7-8s\t%13-15Q, %d"}, 3168 3169 /* Vector VSTRB variant T5. */ 3170 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3171 MVE_VSTRB_T5, 3172 0xec001e00, 0xfe101f80, 3173 "vstrb%v.8\t%13-15,22Q, %d"}, 3174 3175 /* Vector VSTRH variant T6. */ 3176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3177 MVE_VSTRH_T6, 3178 0xec001e80, 0xfe101f80, 3179 "vstrh%v.16\t%13-15,22Q, %d"}, 3180 3181 /* Vector VSTRW variant T7. */ 3182 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3183 MVE_VSTRW_T7, 3184 0xec001f00, 0xfe101f80, 3185 "vstrw%v.32\t%13-15,22Q, %d"}, 3186 3187 /* Vector VSUB floating point T1 variant. */ 3188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3189 MVE_VSUB_FP_T1, 3190 0xef200d40, 0xffa11f51, 3191 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3192 3193 /* Vector VSUB floating point T2 variant. */ 3194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3195 MVE_VSUB_FP_T2, 3196 0xee301f40, 0xefb11f70, 3197 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3198 3199 /* Vector VSUB T1 variant. */ 3200 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3201 MVE_VSUB_VEC_T1, 3202 0xff000840, 0xff811f51, 3203 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3204 3205 /* Vector VSUB T2 variant. */ 3206 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3207 MVE_VSUB_VEC_T2, 3208 0xee011f40, 0xff811f70, 3209 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3210 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3212 MVE_ASRLI, 3213 0xea50012f, 0xfff1813f, 3214 "asrl%c\t%17-19l, %9-11h, %j"}, 3215 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3217 MVE_ASRL, 3218 0xea50012d, 0xfff101ff, 3219 "asrl%c\t%17-19l, %9-11h, %12-15S"}, 3220 3221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3222 MVE_LSLLI, 3223 0xea50010f, 0xfff1813f, 3224 "lsll%c\t%17-19l, %9-11h, %j"}, 3225 3226 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3227 MVE_LSLL, 3228 0xea50010d, 0xfff101ff, 3229 "lsll%c\t%17-19l, %9-11h, %12-15S"}, 3230 3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3232 MVE_LSRL, 3233 0xea50011f, 0xfff1813f, 3234 "lsrl%c\t%17-19l, %9-11h, %j"}, 3235 3236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3237 MVE_SQRSHRL, 3238 0xea51012d, 0xfff1017f, 3239 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, 3240 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3242 MVE_SQRSHR, 3243 0xea500f2d, 0xfff00fff, 3244 "sqrshr%c\t%16-19S, %12-15S"}, 3245 3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3247 MVE_SQSHLL, 3248 0xea51013f, 0xfff1813f, 3249 "sqshll%c\t%17-19l, %9-11h, %j"}, 3250 3251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3252 MVE_SQSHL, 3253 0xea500f3f, 0xfff08f3f, 3254 "sqshl%c\t%16-19S, %j"}, 3255 3256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3257 MVE_SRSHRL, 3258 0xea51012f, 0xfff1813f, 3259 "srshrl%c\t%17-19l, %9-11h, %j"}, 3260 3261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3262 MVE_SRSHR, 3263 0xea500f2f, 0xfff08f3f, 3264 "srshr%c\t%16-19S, %j"}, 3265 3266 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3267 MVE_UQRSHLL, 3268 0xea51010d, 0xfff1017f, 3269 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, 3270 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3272 MVE_UQRSHL, 3273 0xea500f0d, 0xfff00fff, 3274 "uqrshl%c\t%16-19S, %12-15S"}, 3275 3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3277 MVE_UQSHLL, 3278 0xea51010f, 0xfff1813f, 3279 "uqshll%c\t%17-19l, %9-11h, %j"}, 3280 3281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3282 MVE_UQSHL, 3283 0xea500f0f, 0xfff08f3f, 3284 "uqshl%c\t%16-19S, %j"}, 3285 3286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3287 MVE_URSHRL, 3288 0xea51011f, 0xfff1813f, 3289 "urshrl%c\t%17-19l, %9-11h, %j"}, 3290 3291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3292 MVE_URSHR, 3293 0xea500f1f, 0xfff08f3f, 3294 "urshr%c\t%16-19S, %j"}, 3295 3296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3297 MVE_CSINC, 3298 0xea509000, 0xfff0f000, 3299 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3300 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3302 MVE_CSINV, 3303 0xea50a000, 0xfff0f000, 3304 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3305 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3307 MVE_CSET, 3308 0xea5f900f, 0xfffff00f, 3309 "cset\t%8-11S, %4-7C"}, 3310 3311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3312 MVE_CSETM, 3313 0xea5fa00f, 0xfffff00f, 3314 "csetm\t%8-11S, %4-7C"}, 3315 3316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3317 MVE_CSEL, 3318 0xea508000, 0xfff0f000, 3319 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3320 3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3322 MVE_CSNEG, 3323 0xea50b000, 0xfff0f000, 3324 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3325 3326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3327 MVE_CINC, 3328 0xea509000, 0xfff0f000, 3329 "cinc\t%8-11S, %16-19Z, %4-7C"}, 3330 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3332 MVE_CINV, 3333 0xea50a000, 0xfff0f000, 3334 "cinv\t%8-11S, %16-19Z, %4-7C"}, 3335 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3337 MVE_CNEG, 3338 0xea50b000, 0xfff0f000, 3339 "cneg\t%8-11S, %16-19Z, %4-7C"}, 3340 3341 {ARM_FEATURE_CORE_LOW (0), 3342 MVE_NONE, 3343 0x00000000, 0x00000000, 0} 3344 }; 3345 3346 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 3347 ordered: they must be searched linearly from the top to obtain a correct 3348 match. */ 3349 3350 /* print_insn_arm recognizes the following format control codes: 3351 3352 %% % 3353 3354 %a print address for ldr/str instruction 3355 %s print address for ldr/str halfword/signextend instruction 3356 %S like %s but allow UNPREDICTABLE addressing 3357 %b print branch destination 3358 %c print condition code (always bits 28-31) 3359 %m print register mask for ldm/stm instruction 3360 %o print operand2 (immediate or register + shift) 3361 %p print 'p' iff bits 12-15 are 15 3362 %O print 'OBSOLETE' iff bits 12-15 are 15 3363 %t print 't' iff bit 21 set and bit 24 clear 3364 %B print arm BLX(1) destination 3365 %C print the PSR sub type. 3366 %U print barrier type. 3367 %P print address for pli instruction. 3368 %T print 'from Armv4T onwards' 3369 3370 %<bitfield>r print as an ARM register 3371 %<bitfield>T print as an ARM register + 1 3372 %<bitfield>R as %r but r15 is UNPREDICTABLE 3373 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 3374 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 3375 %<bitfield>d print the bitfield in decimal 3376 %<bitfield>W print the bitfield plus one in decimal 3377 %<bitfield>x print the bitfield in hex 3378 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 3379 3380 %<bitfield>'c print specified char iff bitfield is all ones 3381 %<bitfield>`c print specified char iff bitfield is all zeroes 3382 %<bitfield>?ab... select from array of values in big endian order 3383 3384 %e print arm SMI operand (bits 0..7,8..19). 3385 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 3386 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 3387 %R print the SPSR/CPSR or banked register of an MRS. */ 3388 3389 static const struct opcode32 arm_opcodes[] = 3390 { 3391 /* ARM instructions. */ 3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3393 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"}, 3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3395 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"}, 3396 3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4), 3398 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r%T"}, 3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3400 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3402 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 3404 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3406 0x00800090, 0x0fa000f0, 3407 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3409 0x00a00090, 0x0fa000f0, 3410 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3411 3412 /* V8.2 RAS extension instructions. */ 3413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 3414 0xe320f010, 0xffffffff, "esb"}, 3415 3416 /* V8-R instructions. */ 3417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 3418 0xf57ff04c, 0xffffffff, "dfb"}, 3419 3420 /* V8 instructions. */ 3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3422 0x0320f005, 0x0fffffff, "sevl"}, 3423 /* Defined in V8 but is in NOP space so available to all arch. */ 3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3425 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"}, 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 3427 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 3428 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3429 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3431 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3433 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 3434 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3435 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 3436 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3437 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 3438 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3439 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 3440 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3441 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 3442 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3443 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 3444 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3445 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 3446 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3447 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 3448 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3449 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 3450 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3451 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 3452 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3453 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 3454 /* CRC32 instructions. */ 3455 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3456 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3458 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 3459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3460 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 3461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3462 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3464 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3466 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 3467 3468 /* Privileged Access Never extension instructions. */ 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 3470 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"}, 3471 3472 /* Virtualization Extension instructions. */ 3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 3475 3476 /* Integer Divide Extension instructions. */ 3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3478 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3480 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 3481 3482 /* MP Extension instructions. */ 3483 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 3484 3485 /* Speculation Barriers. */ 3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 3489 3490 /* V7 instructions. */ 3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"}, 3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 3499 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"}, 3500 3501 /* ARM V6T2 instructions. */ 3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3503 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3505 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3507 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3509 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 3510 3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3512 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3514 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 3515 3516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3517 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 3518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3519 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3521 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3523 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"}, 3524 3525 /* ARM Security extension instructions. */ 3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 3527 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 3528 3529 /* ARM V6K instructions. */ 3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3531 0xf57ff01f, 0xffffffff, "clrex"}, 3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3533 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3535 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3537 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3539 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3541 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3543 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 3544 3545 /* ARMv8.5-A instructions. */ 3546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 3547 3548 /* ARM V6K NOP hints. */ 3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3550 0x0320f001, 0x0fffffff, "yield%c"}, 3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3552 0x0320f002, 0x0fffffff, "wfe%c"}, 3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3554 0x0320f003, 0x0fffffff, "wfi%c"}, 3555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3556 0x0320f004, 0x0fffffff, "sev%c"}, 3557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3558 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"}, 3559 3560 /* ARM V6 instructions. */ 3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3562 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"}, 3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3564 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"}, 3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3566 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"}, 3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3568 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"}, 3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3570 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"}, 3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3572 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3574 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3576 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"}, 3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3578 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3580 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"}, 3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3582 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3584 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3586 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3588 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3590 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3592 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3594 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3596 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3598 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3600 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3602 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3604 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3606 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3608 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3610 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3612 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3614 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3616 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3618 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3620 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3622 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3624 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3626 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3628 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3630 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3632 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3634 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3636 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3638 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3640 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3642 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3644 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3646 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3648 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3650 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3652 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3654 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3656 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3658 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3660 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3662 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3664 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3666 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3668 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3670 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3672 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3674 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3676 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3678 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3680 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3682 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3684 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3686 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3688 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3690 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3692 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3694 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3696 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3698 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3700 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3702 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3704 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"}, 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3706 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"}, 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3708 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"}, 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3710 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3712 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3714 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3716 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3718 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3720 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3722 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3724 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3726 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3728 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3730 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3732 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3734 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3736 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3738 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3740 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3742 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3744 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3746 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3748 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"}, 3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3750 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3752 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"}, 3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3754 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"}, 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3756 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"}, 3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3758 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3760 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"}, 3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3762 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3764 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3766 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3768 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3770 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3772 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3774 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3776 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3778 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3780 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"}, 3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3782 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"}, 3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3784 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3786 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3788 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"}, 3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3790 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3792 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3794 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3796 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3798 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"}, 3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3800 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"}, 3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3802 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"}, 3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3804 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"}, 3805 3806 /* V5J instruction. */ 3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 3808 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 3809 3810 /* V5 Instructions. */ 3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3812 0xe1200070, 0xfff000f0, 3813 "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"}, 3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3815 0xfa000000, 0xfe000000, "blx\t%B"}, 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3817 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 3819 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 3820 3821 /* V5E "El Segundo" Instructions. */ 3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3823 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3825 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 3827 0xf450f000, 0xfc70f000, "pld\t%a"}, 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3829 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3831 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3833 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3835 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 3836 3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3838 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3840 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 3841 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3843 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3845 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3847 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3849 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3850 3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3852 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3854 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3856 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3858 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 3859 3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3861 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3863 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 3864 3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3866 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3868 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3870 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 3872 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 3873 3874 /* ARM Instructions. */ 3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3876 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"}, 3877 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3879 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3881 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3883 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3885 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3887 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3889 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 3890 3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3892 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3894 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3896 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3898 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 3899 3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3901 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3903 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3905 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3907 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 3908 3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3910 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3912 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3914 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 3915 3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3917 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3919 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3921 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 3922 3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3924 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3926 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3928 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 3929 3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3931 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3933 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3935 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 3936 3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3938 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3940 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3942 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 3943 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3945 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3947 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3949 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 3950 3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3952 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3954 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3956 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 3957 3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3959 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3961 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3963 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 3964 3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 3966 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 3968 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 3970 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 3971 3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3973 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o%O"}, 3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3975 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o%O"}, 3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3977 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o%O"}, 3978 3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3980 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o%O"}, 3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3982 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o%O"}, 3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3984 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o%O"}, 3985 3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3987 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o%O"}, 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3989 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o%O"}, 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3991 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o%O"}, 3992 3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3994 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o%O"}, 3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3996 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o%O"}, 3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3998 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o%O"}, 3999 4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4001 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4003 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4005 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 4006 4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4008 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4010 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4012 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4014 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4016 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4018 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4020 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 4021 4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4023 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4025 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4027 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 4028 4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4030 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4032 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4034 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 4035 4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4037 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4039 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"}, 4040 4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4042 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 4043 4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4045 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4047 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 4048 4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4050 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4052 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4054 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4056 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4058 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4060 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4062 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4064 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4066 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4068 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4070 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4072 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4074 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4076 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4078 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4080 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4082 0x092d0000, 0x0fff0000, "push%c\t%m"}, 4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4084 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4086 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4087 4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4089 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4091 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4093 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4095 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4097 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4099 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4101 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4103 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4105 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4107 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4109 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4111 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4113 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4115 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4117 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4119 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4121 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4123 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4125 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4126 4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4128 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4130 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 4131 4132 /* The rest. */ 4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 4134 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION}, 4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4136 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 4137 {ARM_FEATURE_CORE_LOW (0), 4138 0x00000000, 0x00000000, 0} 4139 }; 4140 4141 /* print_insn_thumb16 recognizes the following format control codes: 4142 4143 %S print Thumb register (bits 3..5 as high number if bit 6 set) 4144 %D print Thumb register (bits 0..2 as high number if bit 7 set) 4145 %<bitfield>I print bitfield as a signed decimal 4146 (top bit of range being the sign bit) 4147 %N print Thumb register mask (with LR) 4148 %O print Thumb register mask (with PC) 4149 %M print Thumb register mask 4150 %b print CZB's 6-bit unsigned branch destination 4151 %s print Thumb right-shift immediate (6..10; 0 == 32). 4152 %c print the condition code 4153 %C print the condition code, or "s" if not conditional 4154 %x print warning if conditional an not at end of IT block" 4155 %X print "\t@ unpredictable <IT:code>" if conditional 4156 %I print IT instruction suffix and operands 4157 %W print Thumb Writeback indicator for LDMIA 4158 %<bitfield>r print bitfield as an ARM register 4159 %<bitfield>d print bitfield as a decimal 4160 %<bitfield>H print (bitfield * 2) as a decimal 4161 %<bitfield>W print (bitfield * 4) as a decimal 4162 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 4163 %<bitfield>B print Thumb branch destination (signed displacement) 4164 %<bitfield>c print bitfield as a condition code 4165 %<bitnum>'c print specified char iff bit is one 4166 %<bitnum>?ab print a if bit is one else print b. */ 4167 4168 static const struct opcode16 thumb_opcodes[] = 4169 { 4170 /* Thumb instructions. */ 4171 4172 /* ARMv8-M Security Extensions instructions. */ 4173 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 4174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 4175 4176 /* ARM V8 instructions. */ 4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 4179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"}, 4180 4181 /* ARM V6K no-argument instructions. */ 4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 4188 4189 /* ARM V6T2 instructions. */ 4190 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4191 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 4192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4193 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 4195 4196 /* ARM V6. */ 4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"}, 4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"}, 4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"}, 4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 4208 4209 /* ARM V5 ISA extends Thumb. */ 4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4211 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 4212 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4214 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 4215 /* ARM V4T ISA (Thumb v1). */ 4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4217 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"}, 4218 /* Format 4. */ 4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 4235 /* format 13 */ 4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"}, 4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"}, 4238 /* format 5 */ 4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 4243 /* format 14 */ 4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 4246 /* format 2 */ 4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4248 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4250 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4252 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"}, 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4254 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"}, 4255 /* format 8 */ 4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4257 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4259 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4261 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 4262 /* format 7 */ 4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4264 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4266 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4267 /* format 1 */ 4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4270 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"}, 4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 4273 /* format 3 */ 4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"}, 4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"}, 4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"}, 4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"}, 4278 /* format 6 */ 4279 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4281 0x4800, 0xF800, 4282 "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"}, 4283 /* format 9 */ 4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4285 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"}, 4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4287 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"}, 4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4289 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"}, 4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4291 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"}, 4292 /* format 10 */ 4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4294 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"}, 4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4296 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"}, 4297 /* format 11 */ 4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4299 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"}, 4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4301 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"}, 4302 /* format 12 */ 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4304 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"}, 4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4306 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"}, 4307 /* format 15 */ 4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 4310 /* format 17 */ 4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 4312 /* format 16 */ 4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"}, 4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 4316 /* format 18 */ 4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 4318 4319 /* The E800 .. FFFF range is unconditionally redirected to the 4320 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 4321 are processed via that table. Thus, we can never encounter a 4322 bare "second half of BL/BLX(1)" instruction here. */ 4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 4324 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 4325 }; 4326 4327 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 4328 We adopt the convention that hw1 is the high 16 bits of .value and 4329 .mask, hw2 the low 16 bits. 4330 4331 print_insn_thumb32 recognizes the following format control codes: 4332 4333 %% % 4334 4335 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 4336 %M print a modified 12-bit immediate (same location) 4337 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 4338 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 4339 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 4340 %S print a possibly-shifted Rm 4341 4342 %L print address for a ldrd/strd instruction 4343 %a print the address of a plain load/store 4344 %w print the width and signedness of a core load/store 4345 %m print register mask for ldm/stm 4346 %n print register mask for clrm 4347 4348 %E print the lsb and width fields of a bfc/bfi instruction 4349 %F print the lsb and width fields of a sbfx/ubfx instruction 4350 %G print a fallback offset for Branch Future instructions 4351 %W print an offset for BF instruction 4352 %Y print an offset for BFL instruction 4353 %Z print an offset for BFCSEL instruction 4354 %Q print an offset for Low Overhead Loop instructions 4355 %P print an offset for Low Overhead Loop end instructions 4356 %b print a conditional branch offset 4357 %B print an unconditional branch offset 4358 %s print the shift field of an SSAT instruction 4359 %R print the rotation field of an SXT instruction 4360 %U print barrier type. 4361 %P print address for pli instruction. 4362 %c print the condition code 4363 %x print warning if conditional an not at end of IT block" 4364 %X print "\t@ unpredictable <IT:code>" if conditional 4365 4366 %<bitfield>d print bitfield in decimal 4367 %<bitfield>D print bitfield plus one in decimal 4368 %<bitfield>W print bitfield*4 in decimal 4369 %<bitfield>r print bitfield as an ARM register 4370 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 4371 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE 4372 %<bitfield>c print bitfield as a condition code 4373 4374 %<bitfield>'c print specified char iff bitfield is all ones 4375 %<bitfield>`c print specified char iff bitfield is all zeroes 4376 %<bitfield>?ab... select from array of values in big endian order 4377 4378 With one exception at the bottom (done because BL and BLX(1) need 4379 to come dead last), this table was machine-sorted first in 4380 decreasing order of number of bits set in the mask, then in 4381 increasing numeric order of mask, then in increasing numeric order 4382 of opcode. This order is not the clearest for a human reader, but 4383 is guaranteed never to catch a special-case bit pattern with a more 4384 general mask, which is important, because this instruction encoding 4385 makes heavy use of special-case bit patterns. */ 4386 static const struct opcode32 thumb32_opcodes[] = 4387 { 4388 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target 4389 Identification Extension. */ 4390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4391 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4392 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4393 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"}, 4394 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4395 0xf3af800f, 0xffffffff, "bti"}, 4396 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4397 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"}, 4398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4399 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4400 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4401 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"}, 4402 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4403 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"}, 4404 4405 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions 4406 instructions. */ 4407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4408 0xf00fe001, 0xffffffff, "lctp%c"}, 4409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4410 0xf02fc001, 0xfffff001, "le\t%P"}, 4411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4412 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"}, 4413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4414 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"}, 4415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4416 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"}, 4417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4418 0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"}, 4419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4420 0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"}, 4421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4422 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"}, 4423 4424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4425 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, 4426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4427 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, 4428 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4429 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"}, 4430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4431 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, 4432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4433 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"}, 4434 4435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4436 0xe89f0000, 0xffff2000, "clrm%c\t%n"}, 4437 4438 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 4439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4441 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 4442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4443 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 4444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4445 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4447 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 4448 4449 /* ARM V8.2 RAS extension instructions. */ 4450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 4451 0xf3af8010, 0xffffffff, "esb"}, 4452 4453 /* V8 instructions. */ 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4455 0xf3af8005, 0xffffffff, "sevl%c.w"}, 4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4457 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4459 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4461 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4463 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4465 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4467 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4469 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4471 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4473 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4475 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4477 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4479 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4481 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4483 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4485 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 4486 4487 /* V8-R instructions. */ 4488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 4489 0xf3bf8f4c, 0xffffffff, "dfb%c"}, 4490 4491 /* CRC32 instructions. */ 4492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4493 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 4494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4495 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 4496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4497 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 4498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4499 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 4500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4501 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 4502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4503 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 4504 4505 /* Speculation Barriers. */ 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 4509 4510 /* V7 instructions. */ 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"}, 4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4519 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4521 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 4522 4523 /* Virtualization Extension instructions. */ 4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 4525 /* We skip ERET as that is SUBS pc, lr, #0. */ 4526 4527 /* MP Extension instructions. */ 4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 4529 4530 /* Security extension instructions. */ 4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 4532 4533 /* ARMv8.5-A instructions. */ 4534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 4535 4536 /* Instructions defined in the basic V6T2 set. */ 4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4543 0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"}, 4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 4545 4546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4547 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4549 0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"}, 4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4551 0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"}, 4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4553 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4555 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4557 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4559 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4561 0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"}, 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4563 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4565 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"}, 4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4567 0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"}, 4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4569 0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"}, 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4571 0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"}, 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4573 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4575 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4577 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4579 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"}, 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4581 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"}, 4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4583 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4585 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4587 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4589 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4591 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4593 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 4594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4595 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4597 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4599 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4601 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4603 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4605 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4607 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4609 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4611 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 4612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4613 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 4614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4615 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 4616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4617 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4619 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 4620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4621 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 4622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4623 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4625 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4627 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4629 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4631 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4633 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4635 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4637 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4639 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4641 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4643 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4645 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4647 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4649 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4651 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4653 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4655 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4657 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 4658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4659 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4661 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4663 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4665 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4667 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4669 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4671 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4673 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4675 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4677 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4679 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4681 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4683 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4685 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4687 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4689 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4691 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4693 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4695 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4697 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4699 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4701 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4703 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4705 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"}, 4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4707 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"}, 4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4709 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4711 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4713 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4715 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4717 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4719 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4721 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4723 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4725 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4727 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4729 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4731 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4733 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4735 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4737 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4739 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4741 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4743 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4745 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4747 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4749 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4751 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4753 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4755 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4757 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4759 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4761 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4763 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4765 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4767 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4769 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4771 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"}, 4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4773 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4775 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4777 0xf810f000, 0xff70f000, "pld%c\t%a"}, 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4779 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4781 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4783 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4785 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4787 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4789 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4791 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4793 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4795 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4797 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4799 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4801 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4803 0xfb100000, 0xfff000c0, 4804 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4806 0xfbc00080, 0xfff000c0, 4807 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4809 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4811 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4813 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"}, 4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4815 0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"}, 4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4817 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 4818 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4819 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4821 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 4822 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4823 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4825 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4827 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4829 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4831 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4833 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4835 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4837 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4839 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4841 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4843 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 4844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4845 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"}, 4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4847 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4849 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4851 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4853 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4855 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4857 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4859 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4861 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4863 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4865 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4867 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4869 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4871 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4873 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4875 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4877 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4879 0xe9400000, 0xff500000, 4880 "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"}, 4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4882 0xe9500000, 0xff500000, 4883 "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"}, 4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4885 0xe8600000, 0xff700000, 4886 "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"}, 4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4888 0xe8700000, 0xff700000, 4889 "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"}, 4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4891 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4893 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 4894 4895 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4897 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4899 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4901 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4903 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 4904 4905 /* These have been 32-bit since the invention of Thumb. */ 4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4907 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4909 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 4910 4911 /* Fallback. */ 4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4913 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 4914 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 4915 }; 4916 4917 static const char *const arm_conditional[] = 4918 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 4919 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 4920 4921 static const char *const arm_shift[] = 4922 {"lsl", "lsr", "asr", "ror"}; 4923 4924 typedef struct 4925 { 4926 const char *name; 4927 const char *description; 4928 const char *reg_names[16]; 4929 } 4930 arm_regname; 4931 4932 static const arm_regname regnames[] = 4933 { 4934 { "reg-names-raw", N_("Select raw register names"), 4935 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 4936 { "reg-names-gcc", N_("Select register names used by GCC"), 4937 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 4938 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 4939 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 4940 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 4941 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 4942 { "reg-names-apcs", N_("Select register names used in the APCS"), 4943 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 4944 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 4945 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 4946 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 4947 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 4948 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } } 4949 }; 4950 4951 static const char *const iwmmxt_wwnames[] = 4952 {"b", "h", "w", "d"}; 4953 4954 static const char *const iwmmxt_wwssnames[] = 4955 {"b", "bus", "bc", "bss", 4956 "h", "hus", "hc", "hss", 4957 "w", "wus", "wc", "wss", 4958 "d", "dus", "dc", "dss" 4959 }; 4960 4961 static const char *const iwmmxt_regnames[] = 4962 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 4963 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 4964 }; 4965 4966 static const char *const iwmmxt_cregnames[] = 4967 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 4968 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 4969 }; 4970 4971 static const char *const vec_condnames[] = 4972 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le" 4973 }; 4974 4975 static const char *const mve_predicatenames[] = 4976 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "", 4977 "eee", "ee", "eet", "e", "ett", "et", "ete" 4978 }; 4979 4980 /* Names for 2-bit size field for mve vector isntructions. */ 4981 static const char *const mve_vec_sizename[] = 4982 { "8", "16", "32", "64"}; 4983 4984 /* Indicates whether we are processing a then predicate, 4985 else predicate or none at all. */ 4986 enum vpt_pred_state 4987 { 4988 PRED_NONE, 4989 PRED_THEN, 4990 PRED_ELSE 4991 }; 4992 4993 /* Information used to process a vpt block and subsequent instructions. */ 4994 struct vpt_block 4995 { 4996 /* Are we in a vpt block. */ 4997 bool in_vpt_block; 4998 4999 /* Next predicate state if in vpt block. */ 5000 enum vpt_pred_state next_pred_state; 5001 5002 /* Mask from vpt/vpst instruction. */ 5003 long predicate_mask; 5004 5005 /* Instruction number in vpt block. */ 5006 long current_insn_num; 5007 5008 /* Number of instructions in vpt block.. */ 5009 long num_pred_insn; 5010 }; 5011 5012 static struct vpt_block vpt_block_state = 5013 { 5014 false, 5015 PRED_NONE, 5016 0, 5017 0, 5018 0 5019 }; 5020 5021 /* Default to GCC register name set. */ 5022 static unsigned int regname_selected = 1; 5023 5024 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 5025 #define arm_regnames regnames[regname_selected].reg_names 5026 5027 static bool force_thumb = false; 5028 static uint16_t cde_coprocs = 0; 5029 5030 /* Current IT instruction state. This contains the same state as the IT 5031 bits in the CPSR. */ 5032 static unsigned int ifthen_state; 5033 /* IT state for the next instruction. */ 5034 static unsigned int ifthen_next_state; 5035 /* The address of the insn for which the IT state is valid. */ 5036 static bfd_vma ifthen_address; 5037 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 5038 /* Indicates that the current Conditional state is unconditional or outside 5039 an IT block. */ 5040 #define COND_UNCOND 16 5041 5042 5043 /* Functions. */ 5045 /* Extract the predicate mask for a VPT or VPST instruction. 5046 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */ 5047 5048 static long 5049 mve_extract_pred_mask (long given) 5050 { 5051 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13); 5052 } 5053 5054 /* Return the number of instructions in a MVE predicate block. */ 5055 static long 5056 num_instructions_vpt_block (long given) 5057 { 5058 long mask = mve_extract_pred_mask (given); 5059 if (mask == 0) 5060 return 0; 5061 5062 if (mask == 8) 5063 return 1; 5064 5065 if ((mask & 7) == 4) 5066 return 2; 5067 5068 if ((mask & 3) == 2) 5069 return 3; 5070 5071 if ((mask & 1) == 1) 5072 return 4; 5073 5074 return 0; 5075 } 5076 5077 static void 5078 mark_outside_vpt_block (void) 5079 { 5080 vpt_block_state.in_vpt_block = false; 5081 vpt_block_state.next_pred_state = PRED_NONE; 5082 vpt_block_state.predicate_mask = 0; 5083 vpt_block_state.current_insn_num = 0; 5084 vpt_block_state.num_pred_insn = 0; 5085 } 5086 5087 static void 5088 mark_inside_vpt_block (long given) 5089 { 5090 vpt_block_state.in_vpt_block = true; 5091 vpt_block_state.next_pred_state = PRED_THEN; 5092 vpt_block_state.predicate_mask = mve_extract_pred_mask (given); 5093 vpt_block_state.current_insn_num = 0; 5094 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given); 5095 assert (vpt_block_state.num_pred_insn >= 1); 5096 } 5097 5098 static enum vpt_pred_state 5099 invert_next_predicate_state (enum vpt_pred_state astate) 5100 { 5101 if (astate == PRED_THEN) 5102 return PRED_ELSE; 5103 else if (astate == PRED_ELSE) 5104 return PRED_THEN; 5105 else 5106 return PRED_NONE; 5107 } 5108 5109 static enum vpt_pred_state 5110 update_next_predicate_state (void) 5111 { 5112 long pred_mask = vpt_block_state.predicate_mask; 5113 long mask_for_insn = 0; 5114 5115 switch (vpt_block_state.current_insn_num) 5116 { 5117 case 1: 5118 mask_for_insn = 8; 5119 break; 5120 5121 case 2: 5122 mask_for_insn = 4; 5123 break; 5124 5125 case 3: 5126 mask_for_insn = 2; 5127 break; 5128 5129 case 4: 5130 return PRED_NONE; 5131 } 5132 5133 if (pred_mask & mask_for_insn) 5134 return invert_next_predicate_state (vpt_block_state.next_pred_state); 5135 else 5136 return vpt_block_state.next_pred_state; 5137 } 5138 5139 static void 5140 update_vpt_block_state (void) 5141 { 5142 vpt_block_state.current_insn_num++; 5143 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn) 5144 { 5145 /* No more instructions to process in vpt block. */ 5146 mark_outside_vpt_block (); 5147 return; 5148 } 5149 5150 vpt_block_state.next_pred_state = update_next_predicate_state (); 5151 } 5152 5153 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 5154 Returns pointer to following character of the format string and 5155 fills in *VALUEP and *WIDTHP with the extracted value and number of 5156 bits extracted. WIDTHP can be NULL. */ 5157 5158 static const char * 5159 arm_decode_bitfield (const char *ptr, 5160 unsigned long insn, 5161 unsigned long *valuep, 5162 int *widthp) 5163 { 5164 unsigned long value = 0; 5165 int width = 0; 5166 5167 do 5168 { 5169 int start, end; 5170 int bits; 5171 5172 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 5173 start = start * 10 + *ptr - '0'; 5174 if (*ptr == '-') 5175 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 5176 end = end * 10 + *ptr - '0'; 5177 else 5178 end = start; 5179 bits = end - start; 5180 if (bits < 0) 5181 abort (); 5182 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 5183 width += bits + 1; 5184 } 5185 while (*ptr++ == ','); 5186 *valuep = value; 5187 if (widthp) 5188 *widthp = width; 5189 return ptr - 1; 5190 } 5191 5192 static void 5193 arm_decode_shift (long given, fprintf_styled_ftype func, void *stream, 5194 bool print_shift) 5195 { 5196 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]); 5197 5198 if ((given & 0xff0) != 0) 5199 { 5200 if ((given & 0x10) == 0) 5201 { 5202 int amount = (given & 0xf80) >> 7; 5203 int shift = (given & 0x60) >> 5; 5204 5205 if (amount == 0) 5206 { 5207 if (shift == 3) 5208 { 5209 func (stream, dis_style_text, ", "); 5210 func (stream, dis_style_sub_mnemonic, "rrx"); 5211 return; 5212 } 5213 5214 amount = 32; 5215 } 5216 5217 if (print_shift) 5218 { 5219 func (stream, dis_style_text, ", "); 5220 func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]); 5221 func (stream, dis_style_immediate, "#%d", amount); 5222 } 5223 else 5224 { 5225 func (stream, dis_style_text, ", "); 5226 func (stream, dis_style_immediate, "#%d", amount); 5227 } 5228 } 5229 else if ((given & 0x80) == 0x80) 5230 func (stream, dis_style_comment_start, 5231 "\t@ <illegal shifter operand>"); 5232 else if (print_shift) 5233 { 5234 func (stream, dis_style_text, ", "); 5235 func (stream, dis_style_sub_mnemonic, "%s ", 5236 arm_shift[(given & 0x60) >> 5]); 5237 func (stream, dis_style_register, "%s", 5238 arm_regnames[(given & 0xf00) >> 8]); 5239 } 5240 else 5241 { 5242 func (stream, dis_style_text, ", "); 5243 func (stream, dis_style_register, "%s", 5244 arm_regnames[(given & 0xf00) >> 8]); 5245 } 5246 } 5247 } 5248 5249 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */ 5250 5251 static bool 5252 is_mve_okay_in_it (enum mve_instructions matched_insn) 5253 { 5254 switch (matched_insn) 5255 { 5256 case MVE_VMOV_GP_TO_VEC_LANE: 5257 case MVE_VMOV2_VEC_LANE_TO_GP: 5258 case MVE_VMOV2_GP_TO_VEC_LANE: 5259 case MVE_VMOV_VEC_LANE_TO_GP: 5260 case MVE_LSLL: 5261 case MVE_LSLLI: 5262 case MVE_LSRL: 5263 case MVE_ASRL: 5264 case MVE_ASRLI: 5265 case MVE_SQRSHRL: 5266 case MVE_SQRSHR: 5267 case MVE_UQRSHL: 5268 case MVE_UQRSHLL: 5269 case MVE_UQSHL: 5270 case MVE_UQSHLL: 5271 case MVE_URSHRL: 5272 case MVE_URSHR: 5273 case MVE_SRSHRL: 5274 case MVE_SRSHR: 5275 case MVE_SQSHLL: 5276 case MVE_SQSHL: 5277 return true; 5278 default: 5279 return false; 5280 } 5281 } 5282 5283 static bool 5284 is_v81m_architecture (struct disassemble_info *info) 5285 { 5286 struct arm_private_data *private_data = info->private_data; 5287 arm_feature_set allowed_arches = private_data->features; 5288 5289 arm_feature_set arm_ext_v8_1m_main 5290 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 5291 5292 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 5293 && !ARM_CPU_IS_ANY (allowed_arches)) 5294 return true; 5295 else 5296 return false; 5297 } 5298 5299 static bool 5300 is_vpt_instruction (long given) 5301 { 5302 5303 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */ 5304 if ((given & 0x0040e000) == 0) 5305 return false; 5306 5307 /* VPT floating point T1 variant. */ 5308 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1)) 5309 /* VPT floating point T2 variant. */ 5310 || ((given & 0xefb10f50) == 0xee310f40) 5311 /* VPT vector T1 variant. */ 5312 || ((given & 0xff811f51) == 0xfe010f00) 5313 /* VPT vector T2 variant. */ 5314 || ((given & 0xff811f51) == 0xfe010f01 5315 && ((given & 0x300000) != 0x300000)) 5316 /* VPT vector T3 variant. */ 5317 || ((given & 0xff811f50) == 0xfe011f00) 5318 /* VPT vector T4 variant. */ 5319 || ((given & 0xff811f70) == 0xfe010f40) 5320 /* VPT vector T5 variant. */ 5321 || ((given & 0xff811f70) == 0xfe010f60) 5322 /* VPT vector T6 variant. */ 5323 || ((given & 0xff811f50) == 0xfe011f40) 5324 /* VPST vector T variant. */ 5325 || ((given & 0xffbf1fff) == 0xfe310f4d)) 5326 return true; 5327 else 5328 return false; 5329 } 5330 5331 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START 5332 and ending bitfield = END. END must be greater than START. */ 5333 5334 static unsigned long 5335 arm_decode_field (unsigned long given, unsigned int start, unsigned int end) 5336 { 5337 int bits = end - start; 5338 5339 if (bits < 0) 5340 abort (); 5341 5342 return ((given >> start) & ((2ul << bits) - 1)); 5343 } 5344 5345 /* Decode a bitfield from opcode GIVEN, with multiple bitfields: 5346 START:END and START2:END2. END/END2 must be greater than 5347 START/START2. */ 5348 5349 static unsigned long 5350 arm_decode_field_multiple (unsigned long given, unsigned int start, 5351 unsigned int end, unsigned int start2, 5352 unsigned int end2) 5353 { 5354 int bits = end - start; 5355 int bits2 = end2 - start2; 5356 unsigned long value = 0; 5357 int width = 0; 5358 5359 if (bits2 < 0) 5360 abort (); 5361 5362 value = arm_decode_field (given, start, end); 5363 width += bits + 1; 5364 5365 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width; 5366 return value; 5367 } 5368 5369 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN. 5370 This helps us decode instructions that change mnemonic depending on specific 5371 operand values/encodings. */ 5372 5373 static bool 5374 is_mve_encoding_conflict (unsigned long given, 5375 enum mve_instructions matched_insn) 5376 { 5377 switch (matched_insn) 5378 { 5379 case MVE_VPST: 5380 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5381 return true; 5382 else 5383 return false; 5384 5385 case MVE_VPT_FP_T1: 5386 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5387 return true; 5388 if ((arm_decode_field (given, 12, 12) == 0) 5389 && (arm_decode_field (given, 0, 0) == 1)) 5390 return true; 5391 return false; 5392 5393 case MVE_VPT_FP_T2: 5394 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5395 return true; 5396 if (arm_decode_field (given, 0, 3) == 0xd) 5397 return true; 5398 return false; 5399 5400 case MVE_VPT_VEC_T1: 5401 case MVE_VPT_VEC_T2: 5402 case MVE_VPT_VEC_T3: 5403 case MVE_VPT_VEC_T4: 5404 case MVE_VPT_VEC_T5: 5405 case MVE_VPT_VEC_T6: 5406 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5407 return true; 5408 if (arm_decode_field (given, 20, 21) == 3) 5409 return true; 5410 return false; 5411 5412 case MVE_VCMP_FP_T1: 5413 if ((arm_decode_field (given, 12, 12) == 0) 5414 && (arm_decode_field (given, 0, 0) == 1)) 5415 return true; 5416 else 5417 return false; 5418 5419 case MVE_VCMP_FP_T2: 5420 if (arm_decode_field (given, 0, 3) == 0xd) 5421 return true; 5422 else 5423 return false; 5424 5425 case MVE_VQADD_T2: 5426 case MVE_VQSUB_T2: 5427 case MVE_VMUL_VEC_T2: 5428 case MVE_VMULH: 5429 case MVE_VRMULH: 5430 case MVE_VMLA: 5431 case MVE_VMAX: 5432 case MVE_VMIN: 5433 case MVE_VBRSR: 5434 case MVE_VADD_VEC_T2: 5435 case MVE_VSUB_VEC_T2: 5436 case MVE_VABAV: 5437 case MVE_VQRSHL_T1: 5438 case MVE_VQSHL_T4: 5439 case MVE_VRSHL_T1: 5440 case MVE_VSHL_T3: 5441 case MVE_VCADD_VEC: 5442 case MVE_VHCADD: 5443 case MVE_VDDUP: 5444 case MVE_VIDUP: 5445 case MVE_VQRDMLADH: 5446 case MVE_VQDMLAH: 5447 case MVE_VQRDMLAH: 5448 case MVE_VQDMLASH: 5449 case MVE_VQRDMLASH: 5450 case MVE_VQDMLSDH: 5451 case MVE_VQRDMLSDH: 5452 case MVE_VQDMULH_T3: 5453 case MVE_VQRDMULH_T4: 5454 case MVE_VQDMLADH: 5455 case MVE_VMLAS: 5456 case MVE_VMULL_INT: 5457 case MVE_VHADD_T2: 5458 case MVE_VHSUB_T2: 5459 case MVE_VCMP_VEC_T1: 5460 case MVE_VCMP_VEC_T2: 5461 case MVE_VCMP_VEC_T3: 5462 case MVE_VCMP_VEC_T4: 5463 case MVE_VCMP_VEC_T5: 5464 case MVE_VCMP_VEC_T6: 5465 if (arm_decode_field (given, 20, 21) == 3) 5466 return true; 5467 else 5468 return false; 5469 5470 case MVE_VLD2: 5471 case MVE_VLD4: 5472 case MVE_VST2: 5473 case MVE_VST4: 5474 if (arm_decode_field (given, 7, 8) == 3) 5475 return true; 5476 else 5477 return false; 5478 5479 case MVE_VSTRB_T1: 5480 case MVE_VSTRH_T2: 5481 if ((arm_decode_field (given, 24, 24) == 0) 5482 && (arm_decode_field (given, 21, 21) == 0)) 5483 { 5484 return true; 5485 } 5486 else if ((arm_decode_field (given, 7, 8) == 3)) 5487 return true; 5488 else 5489 return false; 5490 5491 case MVE_VLDRB_T1: 5492 case MVE_VLDRH_T2: 5493 case MVE_VLDRW_T7: 5494 case MVE_VSTRB_T5: 5495 case MVE_VSTRH_T6: 5496 case MVE_VSTRW_T7: 5497 if ((arm_decode_field (given, 24, 24) == 0) 5498 && (arm_decode_field (given, 21, 21) == 0)) 5499 { 5500 return true; 5501 } 5502 else 5503 return false; 5504 5505 case MVE_VCVT_FP_FIX_VEC: 5506 return (arm_decode_field (given, 16, 21) & 0x38) == 0; 5507 5508 case MVE_VBIC_IMM: 5509 case MVE_VORR_IMM: 5510 { 5511 unsigned long cmode = arm_decode_field (given, 8, 11); 5512 5513 if ((cmode & 1) == 0) 5514 return true; 5515 else if ((cmode & 0xc) == 0xc) 5516 return true; 5517 else 5518 return false; 5519 } 5520 5521 case MVE_VMVN_IMM: 5522 { 5523 unsigned long cmode = arm_decode_field (given, 8, 11); 5524 5525 if (cmode == 0xe) 5526 return true; 5527 else if ((cmode & 0x9) == 1) 5528 return true; 5529 else if ((cmode & 0xd) == 9) 5530 return true; 5531 else 5532 return false; 5533 } 5534 5535 case MVE_VMOV_IMM_TO_VEC: 5536 if ((arm_decode_field (given, 5, 5) == 1) 5537 && (arm_decode_field (given, 8, 11) != 0xe)) 5538 return true; 5539 else 5540 return false; 5541 5542 case MVE_VMOVL: 5543 { 5544 unsigned long size = arm_decode_field (given, 19, 20); 5545 if ((size == 0) || (size == 3)) 5546 return true; 5547 else 5548 return false; 5549 } 5550 5551 case MVE_VMAXA: 5552 case MVE_VMINA: 5553 case MVE_VMAXV: 5554 case MVE_VMAXAV: 5555 case MVE_VMINV: 5556 case MVE_VMINAV: 5557 case MVE_VQRSHL_T2: 5558 case MVE_VQSHL_T1: 5559 case MVE_VRSHL_T2: 5560 case MVE_VSHL_T2: 5561 case MVE_VSHLL_T2: 5562 case MVE_VADDV: 5563 case MVE_VMOVN: 5564 case MVE_VQMOVUN: 5565 case MVE_VQMOVN: 5566 if (arm_decode_field (given, 18, 19) == 3) 5567 return true; 5568 else 5569 return false; 5570 5571 case MVE_VMLSLDAV: 5572 case MVE_VRMLSLDAVH: 5573 case MVE_VMLALDAV: 5574 case MVE_VADDLV: 5575 if (arm_decode_field (given, 20, 22) == 7) 5576 return true; 5577 else 5578 return false; 5579 5580 case MVE_VRMLALDAVH: 5581 if ((arm_decode_field (given, 20, 22) & 6) == 6) 5582 return true; 5583 else 5584 return false; 5585 5586 case MVE_VDWDUP: 5587 case MVE_VIWDUP: 5588 if ((arm_decode_field (given, 20, 21) == 3) 5589 || (arm_decode_field (given, 1, 3) == 7)) 5590 return true; 5591 else 5592 return false; 5593 5594 5595 case MVE_VSHLL_T1: 5596 if (arm_decode_field (given, 16, 18) == 0) 5597 { 5598 unsigned long sz = arm_decode_field (given, 19, 20); 5599 5600 if ((sz == 1) || (sz == 2)) 5601 return true; 5602 else 5603 return false; 5604 } 5605 else 5606 return false; 5607 5608 case MVE_VQSHL_T2: 5609 case MVE_VQSHLU_T3: 5610 case MVE_VRSHR: 5611 case MVE_VSHL_T1: 5612 case MVE_VSHR: 5613 case MVE_VSLI: 5614 case MVE_VSRI: 5615 if (arm_decode_field (given, 19, 21) == 0) 5616 return true; 5617 else 5618 return false; 5619 5620 case MVE_VCTP: 5621 if (arm_decode_field (given, 16, 19) == 0xf) 5622 return true; 5623 else 5624 return false; 5625 5626 case MVE_ASRLI: 5627 case MVE_ASRL: 5628 case MVE_LSLLI: 5629 case MVE_LSLL: 5630 case MVE_LSRL: 5631 case MVE_SQRSHRL: 5632 case MVE_SQSHLL: 5633 case MVE_SRSHRL: 5634 case MVE_UQRSHLL: 5635 case MVE_UQSHLL: 5636 case MVE_URSHRL: 5637 if (arm_decode_field (given, 9, 11) == 0x7) 5638 return true; 5639 else 5640 return false; 5641 5642 case MVE_CSINC: 5643 case MVE_CSINV: 5644 { 5645 unsigned long rm, rn; 5646 rm = arm_decode_field (given, 0, 3); 5647 rn = arm_decode_field (given, 16, 19); 5648 /* CSET/CSETM. */ 5649 if (rm == 0xf && rn == 0xf) 5650 return true; 5651 /* CINC/CINV. */ 5652 else if (rn == rm && rn != 0xf) 5653 return true; 5654 } 5655 /* Fall through. */ 5656 case MVE_CSEL: 5657 case MVE_CSNEG: 5658 if (arm_decode_field (given, 0, 3) == 0xd) 5659 return true; 5660 /* CNEG. */ 5661 else if (matched_insn == MVE_CSNEG) 5662 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19)) 5663 return true; 5664 return false; 5665 5666 default: 5667 case MVE_VADD_FP_T1: 5668 case MVE_VADD_FP_T2: 5669 case MVE_VADD_VEC_T1: 5670 return false; 5671 5672 } 5673 } 5674 5675 static void 5676 print_mve_vld_str_addr (struct disassemble_info *info, 5677 unsigned long given, 5678 enum mve_instructions matched_insn) 5679 { 5680 void *stream = info->stream; 5681 fprintf_styled_ftype func = info->fprintf_styled_func; 5682 5683 unsigned long p, w, gpr, imm, add, mod_imm; 5684 5685 imm = arm_decode_field (given, 0, 6); 5686 mod_imm = imm; 5687 5688 switch (matched_insn) 5689 { 5690 case MVE_VLDRB_T1: 5691 case MVE_VSTRB_T1: 5692 gpr = arm_decode_field (given, 16, 18); 5693 break; 5694 5695 case MVE_VLDRH_T2: 5696 case MVE_VSTRH_T2: 5697 gpr = arm_decode_field (given, 16, 18); 5698 mod_imm = imm << 1; 5699 break; 5700 5701 case MVE_VLDRH_T6: 5702 case MVE_VSTRH_T6: 5703 gpr = arm_decode_field (given, 16, 19); 5704 mod_imm = imm << 1; 5705 break; 5706 5707 case MVE_VLDRW_T7: 5708 case MVE_VSTRW_T7: 5709 gpr = arm_decode_field (given, 16, 19); 5710 mod_imm = imm << 2; 5711 break; 5712 5713 case MVE_VLDRB_T5: 5714 case MVE_VSTRB_T5: 5715 gpr = arm_decode_field (given, 16, 19); 5716 break; 5717 5718 default: 5719 return; 5720 } 5721 5722 p = arm_decode_field (given, 24, 24); 5723 w = arm_decode_field (given, 21, 21); 5724 5725 add = arm_decode_field (given, 23, 23); 5726 5727 char * add_sub; 5728 5729 /* Don't print anything for '+' as it is implied. */ 5730 if (add == 1) 5731 add_sub = ""; 5732 else 5733 add_sub = "-"; 5734 5735 func (stream, dis_style_text, "["); 5736 func (stream, dis_style_register, "%s", arm_regnames[gpr]); 5737 if (p == 1) 5738 { 5739 func (stream, dis_style_text, ", "); 5740 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm); 5741 /* Offset mode. */ 5742 if (w == 0) 5743 func (stream, dis_style_text, "]"); 5744 /* Pre-indexed mode. */ 5745 else 5746 func (stream, dis_style_text, "]!"); 5747 } 5748 else if ((p == 0) && (w == 1)) 5749 { 5750 /* Post-index mode. */ 5751 func (stream, dis_style_text, "], "); 5752 func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm); 5753 } 5754 } 5755 5756 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN. 5757 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why 5758 this encoding is undefined. */ 5759 5760 static bool 5761 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn, 5762 enum mve_undefined *undefined_code) 5763 { 5764 *undefined_code = UNDEF_NONE; 5765 5766 switch (matched_insn) 5767 { 5768 case MVE_VDUP: 5769 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3) 5770 { 5771 *undefined_code = UNDEF_SIZE_3; 5772 return true; 5773 } 5774 else 5775 return false; 5776 5777 case MVE_VQADD_T1: 5778 case MVE_VQSUB_T1: 5779 case MVE_VMUL_VEC_T1: 5780 case MVE_VABD_VEC: 5781 case MVE_VADD_VEC_T1: 5782 case MVE_VSUB_VEC_T1: 5783 case MVE_VQDMULH_T1: 5784 case MVE_VQRDMULH_T2: 5785 case MVE_VRHADD: 5786 case MVE_VHADD_T1: 5787 case MVE_VHSUB_T1: 5788 if (arm_decode_field (given, 20, 21) == 3) 5789 { 5790 *undefined_code = UNDEF_SIZE_3; 5791 return true; 5792 } 5793 else 5794 return false; 5795 5796 case MVE_VLDRB_T1: 5797 if (arm_decode_field (given, 7, 8) == 3) 5798 { 5799 *undefined_code = UNDEF_SIZE_3; 5800 return true; 5801 } 5802 else 5803 return false; 5804 5805 case MVE_VLDRH_T2: 5806 if (arm_decode_field (given, 7, 8) <= 1) 5807 { 5808 *undefined_code = UNDEF_SIZE_LE_1; 5809 return true; 5810 } 5811 else 5812 return false; 5813 5814 case MVE_VSTRB_T1: 5815 if ((arm_decode_field (given, 7, 8) == 0)) 5816 { 5817 *undefined_code = UNDEF_SIZE_0; 5818 return true; 5819 } 5820 else 5821 return false; 5822 5823 case MVE_VSTRH_T2: 5824 if ((arm_decode_field (given, 7, 8) <= 1)) 5825 { 5826 *undefined_code = UNDEF_SIZE_LE_1; 5827 return true; 5828 } 5829 else 5830 return false; 5831 5832 case MVE_VLDRB_GATHER_T1: 5833 if (arm_decode_field (given, 7, 8) == 3) 5834 { 5835 *undefined_code = UNDEF_SIZE_3; 5836 return true; 5837 } 5838 else if ((arm_decode_field (given, 28, 28) == 0) 5839 && (arm_decode_field (given, 7, 8) == 0)) 5840 { 5841 *undefined_code = UNDEF_NOT_UNS_SIZE_0; 5842 return true; 5843 } 5844 else 5845 return false; 5846 5847 case MVE_VLDRH_GATHER_T2: 5848 if (arm_decode_field (given, 7, 8) == 3) 5849 { 5850 *undefined_code = UNDEF_SIZE_3; 5851 return true; 5852 } 5853 else if ((arm_decode_field (given, 28, 28) == 0) 5854 && (arm_decode_field (given, 7, 8) == 1)) 5855 { 5856 *undefined_code = UNDEF_NOT_UNS_SIZE_1; 5857 return true; 5858 } 5859 else if (arm_decode_field (given, 7, 8) == 0) 5860 { 5861 *undefined_code = UNDEF_SIZE_0; 5862 return true; 5863 } 5864 else 5865 return false; 5866 5867 case MVE_VLDRW_GATHER_T3: 5868 if (arm_decode_field (given, 7, 8) != 2) 5869 { 5870 *undefined_code = UNDEF_SIZE_NOT_2; 5871 return true; 5872 } 5873 else if (arm_decode_field (given, 28, 28) == 0) 5874 { 5875 *undefined_code = UNDEF_NOT_UNSIGNED; 5876 return true; 5877 } 5878 else 5879 return false; 5880 5881 case MVE_VLDRD_GATHER_T4: 5882 if (arm_decode_field (given, 7, 8) != 3) 5883 { 5884 *undefined_code = UNDEF_SIZE_NOT_3; 5885 return true; 5886 } 5887 else if (arm_decode_field (given, 28, 28) == 0) 5888 { 5889 *undefined_code = UNDEF_NOT_UNSIGNED; 5890 return true; 5891 } 5892 else 5893 return false; 5894 5895 case MVE_VSTRB_SCATTER_T1: 5896 if (arm_decode_field (given, 7, 8) == 3) 5897 { 5898 *undefined_code = UNDEF_SIZE_3; 5899 return true; 5900 } 5901 else 5902 return false; 5903 5904 case MVE_VSTRH_SCATTER_T2: 5905 { 5906 unsigned long size = arm_decode_field (given, 7, 8); 5907 if (size == 3) 5908 { 5909 *undefined_code = UNDEF_SIZE_3; 5910 return true; 5911 } 5912 else if (size == 0) 5913 { 5914 *undefined_code = UNDEF_SIZE_0; 5915 return true; 5916 } 5917 else 5918 return false; 5919 } 5920 5921 case MVE_VSTRW_SCATTER_T3: 5922 if (arm_decode_field (given, 7, 8) != 2) 5923 { 5924 *undefined_code = UNDEF_SIZE_NOT_2; 5925 return true; 5926 } 5927 else 5928 return false; 5929 5930 case MVE_VSTRD_SCATTER_T4: 5931 if (arm_decode_field (given, 7, 8) != 3) 5932 { 5933 *undefined_code = UNDEF_SIZE_NOT_3; 5934 return true; 5935 } 5936 else 5937 return false; 5938 5939 case MVE_VCVT_FP_FIX_VEC: 5940 { 5941 unsigned long imm6 = arm_decode_field (given, 16, 21); 5942 if ((imm6 & 0x20) == 0) 5943 { 5944 *undefined_code = UNDEF_VCVT_IMM6; 5945 return true; 5946 } 5947 5948 if ((arm_decode_field (given, 9, 9) == 0) 5949 && ((imm6 & 0x30) == 0x20)) 5950 { 5951 *undefined_code = UNDEF_VCVT_FSI_IMM6; 5952 return true; 5953 } 5954 5955 return false; 5956 } 5957 5958 case MVE_VNEG_FP: 5959 case MVE_VABS_FP: 5960 case MVE_VCVT_BETWEEN_FP_INT: 5961 case MVE_VCVT_FROM_FP_TO_INT: 5962 { 5963 unsigned long size = arm_decode_field (given, 18, 19); 5964 if (size == 0) 5965 { 5966 *undefined_code = UNDEF_SIZE_0; 5967 return true; 5968 } 5969 else if (size == 3) 5970 { 5971 *undefined_code = UNDEF_SIZE_3; 5972 return true; 5973 } 5974 else 5975 return false; 5976 } 5977 5978 case MVE_VMOV_VEC_LANE_TO_GP: 5979 { 5980 unsigned long op1 = arm_decode_field (given, 21, 22); 5981 unsigned long op2 = arm_decode_field (given, 5, 6); 5982 unsigned long u = arm_decode_field (given, 23, 23); 5983 5984 if ((op2 == 0) && (u == 1)) 5985 { 5986 if ((op1 == 0) || (op1 == 1)) 5987 { 5988 *undefined_code = UNDEF_BAD_U_OP1_OP2; 5989 return true; 5990 } 5991 else 5992 return false; 5993 } 5994 else if (op2 == 2) 5995 { 5996 if ((op1 == 0) || (op1 == 1)) 5997 { 5998 *undefined_code = UNDEF_BAD_OP1_OP2; 5999 return true; 6000 } 6001 else 6002 return false; 6003 } 6004 6005 return false; 6006 } 6007 6008 case MVE_VMOV_GP_TO_VEC_LANE: 6009 if (arm_decode_field (given, 5, 6) == 2) 6010 { 6011 unsigned long op1 = arm_decode_field (given, 21, 22); 6012 if ((op1 == 0) || (op1 == 1)) 6013 { 6014 *undefined_code = UNDEF_BAD_OP1_OP2; 6015 return true; 6016 } 6017 else 6018 return false; 6019 } 6020 else 6021 return false; 6022 6023 case MVE_VMOV_VEC_TO_VEC: 6024 if ((arm_decode_field (given, 5, 5) == 1) 6025 || (arm_decode_field (given, 22, 22) == 1)) 6026 return true; 6027 return false; 6028 6029 case MVE_VMOV_IMM_TO_VEC: 6030 if (arm_decode_field (given, 5, 5) == 0) 6031 { 6032 unsigned long cmode = arm_decode_field (given, 8, 11); 6033 6034 if (((cmode & 9) == 1) || ((cmode & 5) == 1)) 6035 { 6036 *undefined_code = UNDEF_OP_0_BAD_CMODE; 6037 return true; 6038 } 6039 else 6040 return false; 6041 } 6042 else 6043 return false; 6044 6045 case MVE_VSHLL_T2: 6046 case MVE_VMOVN: 6047 if (arm_decode_field (given, 18, 19) == 2) 6048 { 6049 *undefined_code = UNDEF_SIZE_2; 6050 return true; 6051 } 6052 else 6053 return false; 6054 6055 case MVE_VRMLALDAVH: 6056 case MVE_VMLADAV_T1: 6057 case MVE_VMLADAV_T2: 6058 case MVE_VMLALDAV: 6059 if ((arm_decode_field (given, 28, 28) == 1) 6060 && (arm_decode_field (given, 12, 12) == 1)) 6061 { 6062 *undefined_code = UNDEF_XCHG_UNS; 6063 return true; 6064 } 6065 else 6066 return false; 6067 6068 case MVE_VQSHRN: 6069 case MVE_VQSHRUN: 6070 case MVE_VSHLL_T1: 6071 case MVE_VSHRN: 6072 { 6073 unsigned long sz = arm_decode_field (given, 19, 20); 6074 if (sz == 1) 6075 return false; 6076 else if ((sz & 2) == 2) 6077 return false; 6078 else 6079 { 6080 *undefined_code = UNDEF_SIZE; 6081 return true; 6082 } 6083 } 6084 break; 6085 6086 case MVE_VQSHL_T2: 6087 case MVE_VQSHLU_T3: 6088 case MVE_VRSHR: 6089 case MVE_VSHL_T1: 6090 case MVE_VSHR: 6091 case MVE_VSLI: 6092 case MVE_VSRI: 6093 { 6094 unsigned long sz = arm_decode_field (given, 19, 21); 6095 if ((sz & 7) == 1) 6096 return false; 6097 else if ((sz & 6) == 2) 6098 return false; 6099 else if ((sz & 4) == 4) 6100 return false; 6101 else 6102 { 6103 *undefined_code = UNDEF_SIZE; 6104 return true; 6105 } 6106 } 6107 6108 case MVE_VQRSHRN: 6109 case MVE_VQRSHRUN: 6110 if (arm_decode_field (given, 19, 20) == 0) 6111 { 6112 *undefined_code = UNDEF_SIZE_0; 6113 return true; 6114 } 6115 else 6116 return false; 6117 6118 case MVE_VABS_VEC: 6119 if (arm_decode_field (given, 18, 19) == 3) 6120 { 6121 *undefined_code = UNDEF_SIZE_3; 6122 return true; 6123 } 6124 else 6125 return false; 6126 6127 case MVE_VQNEG: 6128 case MVE_VQABS: 6129 case MVE_VNEG_VEC: 6130 case MVE_VCLS: 6131 case MVE_VCLZ: 6132 if (arm_decode_field (given, 18, 19) == 3) 6133 { 6134 *undefined_code = UNDEF_SIZE_3; 6135 return true; 6136 } 6137 else 6138 return false; 6139 6140 case MVE_VREV16: 6141 if (arm_decode_field (given, 18, 19) == 0) 6142 return false; 6143 else 6144 { 6145 *undefined_code = UNDEF_SIZE_NOT_0; 6146 return true; 6147 } 6148 6149 case MVE_VREV32: 6150 { 6151 unsigned long size = arm_decode_field (given, 18, 19); 6152 if ((size & 2) == 2) 6153 { 6154 *undefined_code = UNDEF_SIZE_2; 6155 return true; 6156 } 6157 else 6158 return false; 6159 } 6160 6161 case MVE_VREV64: 6162 if (arm_decode_field (given, 18, 19) != 3) 6163 return false; 6164 else 6165 { 6166 *undefined_code = UNDEF_SIZE_3; 6167 return true; 6168 } 6169 6170 default: 6171 return false; 6172 } 6173 } 6174 6175 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN. 6176 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to 6177 why this encoding is unpredictable. */ 6178 6179 static bool 6180 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, 6181 enum mve_unpredictable *unpredictable_code) 6182 { 6183 *unpredictable_code = UNPRED_NONE; 6184 6185 switch (matched_insn) 6186 { 6187 case MVE_VCMP_FP_T2: 6188 case MVE_VPT_FP_T2: 6189 if ((arm_decode_field (given, 12, 12) == 0) 6190 && (arm_decode_field (given, 5, 5) == 1)) 6191 { 6192 *unpredictable_code = UNPRED_FCA_0_FCB_1; 6193 return true; 6194 } 6195 else 6196 return false; 6197 6198 case MVE_VPT_VEC_T4: 6199 case MVE_VPT_VEC_T5: 6200 case MVE_VPT_VEC_T6: 6201 case MVE_VCMP_VEC_T4: 6202 case MVE_VCMP_VEC_T5: 6203 case MVE_VCMP_VEC_T6: 6204 if (arm_decode_field (given, 0, 3) == 0xd) 6205 { 6206 *unpredictable_code = UNPRED_R13; 6207 return true; 6208 } 6209 else 6210 return false; 6211 6212 case MVE_VDUP: 6213 { 6214 unsigned long gpr = arm_decode_field (given, 12, 15); 6215 if (gpr == 0xd) 6216 { 6217 *unpredictable_code = UNPRED_R13; 6218 return true; 6219 } 6220 else if (gpr == 0xf) 6221 { 6222 *unpredictable_code = UNPRED_R15; 6223 return true; 6224 } 6225 6226 return false; 6227 } 6228 6229 case MVE_VQADD_T2: 6230 case MVE_VQSUB_T2: 6231 case MVE_VMUL_FP_T2: 6232 case MVE_VMUL_VEC_T2: 6233 case MVE_VMLA: 6234 case MVE_VBRSR: 6235 case MVE_VADD_FP_T2: 6236 case MVE_VSUB_FP_T2: 6237 case MVE_VADD_VEC_T2: 6238 case MVE_VSUB_VEC_T2: 6239 case MVE_VQRSHL_T2: 6240 case MVE_VQSHL_T1: 6241 case MVE_VRSHL_T2: 6242 case MVE_VSHL_T2: 6243 case MVE_VSHLC: 6244 case MVE_VQDMLAH: 6245 case MVE_VQRDMLAH: 6246 case MVE_VQDMLASH: 6247 case MVE_VQRDMLASH: 6248 case MVE_VQDMULH_T3: 6249 case MVE_VQRDMULH_T4: 6250 case MVE_VMLAS: 6251 case MVE_VFMA_FP_SCALAR: 6252 case MVE_VFMAS_FP_SCALAR: 6253 case MVE_VHADD_T2: 6254 case MVE_VHSUB_T2: 6255 { 6256 unsigned long gpr = arm_decode_field (given, 0, 3); 6257 if (gpr == 0xd) 6258 { 6259 *unpredictable_code = UNPRED_R13; 6260 return true; 6261 } 6262 else if (gpr == 0xf) 6263 { 6264 *unpredictable_code = UNPRED_R15; 6265 return true; 6266 } 6267 6268 return false; 6269 } 6270 6271 case MVE_VLD2: 6272 case MVE_VST2: 6273 { 6274 unsigned long rn = arm_decode_field (given, 16, 19); 6275 6276 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6277 { 6278 *unpredictable_code = UNPRED_R13_AND_WB; 6279 return true; 6280 } 6281 6282 if (rn == 0xf) 6283 { 6284 *unpredictable_code = UNPRED_R15; 6285 return true; 6286 } 6287 6288 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6) 6289 { 6290 *unpredictable_code = UNPRED_Q_GT_6; 6291 return true; 6292 } 6293 else 6294 return false; 6295 } 6296 6297 case MVE_VLD4: 6298 case MVE_VST4: 6299 { 6300 unsigned long rn = arm_decode_field (given, 16, 19); 6301 6302 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6303 { 6304 *unpredictable_code = UNPRED_R13_AND_WB; 6305 return true; 6306 } 6307 6308 if (rn == 0xf) 6309 { 6310 *unpredictable_code = UNPRED_R15; 6311 return true; 6312 } 6313 6314 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4) 6315 { 6316 *unpredictable_code = UNPRED_Q_GT_4; 6317 return true; 6318 } 6319 else 6320 return false; 6321 } 6322 6323 case MVE_VLDRB_T5: 6324 case MVE_VLDRH_T6: 6325 case MVE_VLDRW_T7: 6326 case MVE_VSTRB_T5: 6327 case MVE_VSTRH_T6: 6328 case MVE_VSTRW_T7: 6329 { 6330 unsigned long rn = arm_decode_field (given, 16, 19); 6331 6332 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6333 { 6334 *unpredictable_code = UNPRED_R13_AND_WB; 6335 return true; 6336 } 6337 else if (rn == 0xf) 6338 { 6339 *unpredictable_code = UNPRED_R15; 6340 return true; 6341 } 6342 else 6343 return false; 6344 } 6345 6346 case MVE_VLDRB_GATHER_T1: 6347 if (arm_decode_field (given, 0, 0) == 1) 6348 { 6349 *unpredictable_code = UNPRED_OS; 6350 return true; 6351 } 6352 6353 /* fall through. */ 6354 /* To handle common code with T2-T4 variants. */ 6355 case MVE_VLDRH_GATHER_T2: 6356 case MVE_VLDRW_GATHER_T3: 6357 case MVE_VLDRD_GATHER_T4: 6358 { 6359 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6360 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6361 6362 if (qd == qm) 6363 { 6364 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6365 return true; 6366 } 6367 6368 if (arm_decode_field (given, 16, 19) == 0xf) 6369 { 6370 *unpredictable_code = UNPRED_R15; 6371 return true; 6372 } 6373 6374 return false; 6375 } 6376 6377 case MVE_VLDRW_GATHER_T5: 6378 case MVE_VLDRD_GATHER_T6: 6379 { 6380 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6381 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7); 6382 6383 if (qd == qm) 6384 { 6385 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6386 return true; 6387 } 6388 else 6389 return false; 6390 } 6391 6392 case MVE_VSTRB_SCATTER_T1: 6393 if (arm_decode_field (given, 16, 19) == 0xf) 6394 { 6395 *unpredictable_code = UNPRED_R15; 6396 return true; 6397 } 6398 else if (arm_decode_field (given, 0, 0) == 1) 6399 { 6400 *unpredictable_code = UNPRED_OS; 6401 return true; 6402 } 6403 else 6404 return false; 6405 6406 case MVE_VSTRH_SCATTER_T2: 6407 case MVE_VSTRW_SCATTER_T3: 6408 case MVE_VSTRD_SCATTER_T4: 6409 if (arm_decode_field (given, 16, 19) == 0xf) 6410 { 6411 *unpredictable_code = UNPRED_R15; 6412 return true; 6413 } 6414 else 6415 return false; 6416 6417 case MVE_VMOV2_VEC_LANE_TO_GP: 6418 case MVE_VMOV2_GP_TO_VEC_LANE: 6419 case MVE_VCVT_BETWEEN_FP_INT: 6420 case MVE_VCVT_FROM_FP_TO_INT: 6421 { 6422 unsigned long rt = arm_decode_field (given, 0, 3); 6423 unsigned long rt2 = arm_decode_field (given, 16, 19); 6424 6425 if ((rt == 0xd) || (rt2 == 0xd)) 6426 { 6427 *unpredictable_code = UNPRED_R13; 6428 return true; 6429 } 6430 else if ((rt == 0xf) || (rt2 == 0xf)) 6431 { 6432 *unpredictable_code = UNPRED_R15; 6433 return true; 6434 } 6435 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE) 6436 { 6437 *unpredictable_code = UNPRED_GP_REGS_EQUAL; 6438 return true; 6439 } 6440 6441 return false; 6442 } 6443 6444 case MVE_VMAXV: 6445 case MVE_VMAXAV: 6446 case MVE_VMAXNMV_FP: 6447 case MVE_VMAXNMAV_FP: 6448 case MVE_VMINNMV_FP: 6449 case MVE_VMINNMAV_FP: 6450 case MVE_VMINV: 6451 case MVE_VMINAV: 6452 case MVE_VABAV: 6453 case MVE_VMOV_HFP_TO_GP: 6454 case MVE_VMOV_GP_TO_VEC_LANE: 6455 case MVE_VMOV_VEC_LANE_TO_GP: 6456 { 6457 unsigned long rda = arm_decode_field (given, 12, 15); 6458 if (rda == 0xd) 6459 { 6460 *unpredictable_code = UNPRED_R13; 6461 return true; 6462 } 6463 else if (rda == 0xf) 6464 { 6465 *unpredictable_code = UNPRED_R15; 6466 return true; 6467 } 6468 6469 return false; 6470 } 6471 6472 case MVE_VMULL_INT: 6473 { 6474 unsigned long Qd; 6475 unsigned long Qm; 6476 unsigned long Qn; 6477 6478 if (arm_decode_field (given, 20, 21) == 2) 6479 { 6480 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6481 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6482 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6483 6484 if ((Qd == Qn) || (Qd == Qm)) 6485 { 6486 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6487 return true; 6488 } 6489 else 6490 return false; 6491 } 6492 else 6493 return false; 6494 } 6495 6496 case MVE_VCMUL_FP: 6497 case MVE_VQDMULL_T1: 6498 { 6499 unsigned long Qd; 6500 unsigned long Qm; 6501 unsigned long Qn; 6502 6503 if (arm_decode_field (given, 28, 28) == 1) 6504 { 6505 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6506 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6507 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6508 6509 if ((Qd == Qn) || (Qd == Qm)) 6510 { 6511 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6512 return true; 6513 } 6514 else 6515 return false; 6516 } 6517 else 6518 return false; 6519 } 6520 6521 case MVE_VQDMULL_T2: 6522 { 6523 unsigned long gpr = arm_decode_field (given, 0, 3); 6524 if (gpr == 0xd) 6525 { 6526 *unpredictable_code = UNPRED_R13; 6527 return true; 6528 } 6529 else if (gpr == 0xf) 6530 { 6531 *unpredictable_code = UNPRED_R15; 6532 return true; 6533 } 6534 6535 if (arm_decode_field (given, 28, 28) == 1) 6536 { 6537 unsigned long Qd 6538 = arm_decode_field_multiple (given, 13, 15, 22, 22); 6539 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6540 6541 if (Qd == Qn) 6542 { 6543 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6544 return true; 6545 } 6546 else 6547 return false; 6548 } 6549 6550 return false; 6551 } 6552 6553 case MVE_VMLSLDAV: 6554 case MVE_VRMLSLDAVH: 6555 case MVE_VMLALDAV: 6556 case MVE_VADDLV: 6557 if (arm_decode_field (given, 20, 22) == 6) 6558 { 6559 *unpredictable_code = UNPRED_R13; 6560 return true; 6561 } 6562 else 6563 return false; 6564 6565 case MVE_VDWDUP: 6566 case MVE_VIWDUP: 6567 if (arm_decode_field (given, 1, 3) == 6) 6568 { 6569 *unpredictable_code = UNPRED_R13; 6570 return true; 6571 } 6572 else 6573 return false; 6574 6575 case MVE_VCADD_VEC: 6576 case MVE_VHCADD: 6577 { 6578 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6579 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6580 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2) 6581 { 6582 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6583 return true; 6584 } 6585 else 6586 return false; 6587 } 6588 6589 case MVE_VCADD_FP: 6590 { 6591 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6592 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6593 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1) 6594 { 6595 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6596 return true; 6597 } 6598 else 6599 return false; 6600 } 6601 6602 case MVE_VCMLA_FP: 6603 { 6604 unsigned long Qda; 6605 unsigned long Qm; 6606 unsigned long Qn; 6607 6608 if (arm_decode_field (given, 20, 20) == 1) 6609 { 6610 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22); 6611 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6612 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6613 6614 if ((Qda == Qn) || (Qda == Qm)) 6615 { 6616 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6617 return true; 6618 } 6619 else 6620 return false; 6621 } 6622 else 6623 return false; 6624 6625 } 6626 6627 case MVE_VCTP: 6628 if (arm_decode_field (given, 16, 19) == 0xd) 6629 { 6630 *unpredictable_code = UNPRED_R13; 6631 return true; 6632 } 6633 else 6634 return false; 6635 6636 case MVE_VREV64: 6637 { 6638 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6639 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6); 6640 6641 if (qd == qm) 6642 { 6643 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6644 return true; 6645 } 6646 else 6647 return false; 6648 } 6649 6650 case MVE_LSLL: 6651 case MVE_LSLLI: 6652 case MVE_LSRL: 6653 case MVE_ASRL: 6654 case MVE_ASRLI: 6655 case MVE_UQSHLL: 6656 case MVE_UQRSHLL: 6657 case MVE_URSHRL: 6658 case MVE_SRSHRL: 6659 case MVE_SQSHLL: 6660 case MVE_SQRSHRL: 6661 { 6662 unsigned long gpr = arm_decode_field (given, 9, 11); 6663 gpr = ((gpr << 1) | 1); 6664 if (gpr == 0xd) 6665 { 6666 *unpredictable_code = UNPRED_R13; 6667 return true; 6668 } 6669 else if (gpr == 0xf) 6670 { 6671 *unpredictable_code = UNPRED_R15; 6672 return true; 6673 } 6674 6675 return false; 6676 } 6677 6678 default: 6679 return false; 6680 } 6681 } 6682 6683 static void 6684 print_mve_vmov_index (struct disassemble_info *info, unsigned long given) 6685 { 6686 unsigned long op1 = arm_decode_field (given, 21, 22); 6687 unsigned long op2 = arm_decode_field (given, 5, 6); 6688 unsigned long h = arm_decode_field (given, 16, 16); 6689 unsigned long index_operand, esize, targetBeat, idx; 6690 void *stream = info->stream; 6691 fprintf_styled_ftype func = info->fprintf_styled_func; 6692 6693 if ((op1 & 0x2) == 0x2) 6694 { 6695 index_operand = op2; 6696 esize = 8; 6697 } 6698 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) 6699 { 6700 index_operand = op2 >> 1; 6701 esize = 16; 6702 } 6703 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) 6704 { 6705 index_operand = 0; 6706 esize = 32; 6707 } 6708 else 6709 { 6710 func (stream, dis_style_text, "<undefined index>"); 6711 return; 6712 } 6713 6714 targetBeat = (op1 & 0x1) | (h << 1); 6715 idx = index_operand + targetBeat * (32/esize); 6716 6717 func (stream, dis_style_immediate, "%lu", idx); 6718 } 6719 6720 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits 6721 in length and integer of floating-point type. */ 6722 static void 6723 print_simd_imm8 (struct disassemble_info *info, unsigned long given, 6724 unsigned int ibit_loc, const struct mopcode32 *insn) 6725 { 6726 int bits = 0; 6727 int cmode = (given >> 8) & 0xf; 6728 int op = (given >> 5) & 0x1; 6729 unsigned long value = 0, hival = 0; 6730 unsigned shift; 6731 int size = 0; 6732 int isfloat = 0; 6733 void *stream = info->stream; 6734 fprintf_styled_ftype func = info->fprintf_styled_func; 6735 6736 /* On Neon the 'i' bit is at bit 24, on mve it is 6737 at bit 28. */ 6738 bits |= ((given >> ibit_loc) & 1) << 7; 6739 bits |= ((given >> 16) & 7) << 4; 6740 bits |= ((given >> 0) & 15) << 0; 6741 6742 if (cmode < 8) 6743 { 6744 shift = (cmode >> 1) & 3; 6745 value = (unsigned long) bits << (8 * shift); 6746 size = 32; 6747 } 6748 else if (cmode < 12) 6749 { 6750 shift = (cmode >> 1) & 1; 6751 value = (unsigned long) bits << (8 * shift); 6752 size = 16; 6753 } 6754 else if (cmode < 14) 6755 { 6756 shift = (cmode & 1) + 1; 6757 value = (unsigned long) bits << (8 * shift); 6758 value |= (1ul << (8 * shift)) - 1; 6759 size = 32; 6760 } 6761 else if (cmode == 14) 6762 { 6763 if (op) 6764 { 6765 /* Bit replication into bytes. */ 6766 int ix; 6767 unsigned long mask; 6768 6769 value = 0; 6770 hival = 0; 6771 for (ix = 7; ix >= 0; ix--) 6772 { 6773 mask = ((bits >> ix) & 1) ? 0xff : 0; 6774 if (ix <= 3) 6775 value = (value << 8) | mask; 6776 else 6777 hival = (hival << 8) | mask; 6778 } 6779 size = 64; 6780 } 6781 else 6782 { 6783 /* Byte replication. */ 6784 value = (unsigned long) bits; 6785 size = 8; 6786 } 6787 } 6788 else if (!op) 6789 { 6790 /* Floating point encoding. */ 6791 int tmp; 6792 6793 value = (unsigned long) (bits & 0x7f) << 19; 6794 value |= (unsigned long) (bits & 0x80) << 24; 6795 tmp = bits & 0x40 ? 0x3c : 0x40; 6796 value |= (unsigned long) tmp << 24; 6797 size = 32; 6798 isfloat = 1; 6799 } 6800 else 6801 { 6802 func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>", 6803 bits, cmode, op); 6804 size = 32; 6805 return; 6806 } 6807 6808 /* printU determines whether the immediate value should be printed as 6809 unsigned. */ 6810 unsigned printU = 0; 6811 switch (insn->mve_op) 6812 { 6813 default: 6814 break; 6815 /* We want this for instructions that don't have a 'signed' type. */ 6816 case MVE_VBIC_IMM: 6817 case MVE_VORR_IMM: 6818 case MVE_VMVN_IMM: 6819 case MVE_VMOV_IMM_TO_VEC: 6820 printU = 1; 6821 break; 6822 } 6823 switch (size) 6824 { 6825 case 8: 6826 func (stream, dis_style_immediate, "#%ld", value); 6827 func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value); 6828 break; 6829 6830 case 16: 6831 func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value); 6832 func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value); 6833 break; 6834 6835 case 32: 6836 if (isfloat) 6837 { 6838 unsigned char valbytes[4]; 6839 double fvalue; 6840 6841 /* Do this a byte at a time so we don't have to 6842 worry about the host's endianness. */ 6843 valbytes[0] = value & 0xff; 6844 valbytes[1] = (value >> 8) & 0xff; 6845 valbytes[2] = (value >> 16) & 0xff; 6846 valbytes[3] = (value >> 24) & 0xff; 6847 6848 floatformat_to_double 6849 (& floatformat_ieee_single_little, valbytes, 6850 & fvalue); 6851 6852 func (stream, dis_style_immediate, "#%.7g", fvalue); 6853 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value); 6854 } 6855 else 6856 { 6857 func (stream, dis_style_immediate, 6858 printU ? "#%lu" : "#%ld", 6859 (long) (((value & 0x80000000L) != 0) 6860 && !printU 6861 ? value | ~0xffffffffL : value)); 6862 func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value); 6863 } 6864 break; 6865 6866 case 64: 6867 func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value); 6868 break; 6869 6870 default: 6871 abort (); 6872 } 6873 6874 } 6875 6876 static void 6877 print_mve_undefined (struct disassemble_info *info, 6878 enum mve_undefined undefined_code) 6879 { 6880 void *stream = info->stream; 6881 fprintf_styled_ftype func = info->fprintf_styled_func; 6882 /* Initialize REASON to avoid compiler warning about uninitialized 6883 usage, though such usage should be impossible. */ 6884 const char *reason = "??"; 6885 6886 switch (undefined_code) 6887 { 6888 case UNDEF_SIZE: 6889 reason = "illegal size"; 6890 break; 6891 6892 case UNDEF_SIZE_0: 6893 reason = "size equals zero"; 6894 break; 6895 6896 case UNDEF_SIZE_2: 6897 reason = "size equals two"; 6898 break; 6899 6900 case UNDEF_SIZE_3: 6901 reason = "size equals three"; 6902 break; 6903 6904 case UNDEF_SIZE_LE_1: 6905 reason = "size <= 1"; 6906 break; 6907 6908 case UNDEF_SIZE_NOT_0: 6909 reason = "size not equal to 0"; 6910 break; 6911 6912 case UNDEF_SIZE_NOT_2: 6913 reason = "size not equal to 2"; 6914 break; 6915 6916 case UNDEF_SIZE_NOT_3: 6917 reason = "size not equal to 3"; 6918 break; 6919 6920 case UNDEF_NOT_UNS_SIZE_0: 6921 reason = "not unsigned and size = zero"; 6922 break; 6923 6924 case UNDEF_NOT_UNS_SIZE_1: 6925 reason = "not unsigned and size = one"; 6926 break; 6927 6928 case UNDEF_NOT_UNSIGNED: 6929 reason = "not unsigned"; 6930 break; 6931 6932 case UNDEF_VCVT_IMM6: 6933 reason = "invalid imm6"; 6934 break; 6935 6936 case UNDEF_VCVT_FSI_IMM6: 6937 reason = "fsi = 0 and invalid imm6"; 6938 break; 6939 6940 case UNDEF_BAD_OP1_OP2: 6941 reason = "bad size with op2 = 2 and op1 = 0 or 1"; 6942 break; 6943 6944 case UNDEF_BAD_U_OP1_OP2: 6945 reason = "unsigned with op2 = 0 and op1 = 0 or 1"; 6946 break; 6947 6948 case UNDEF_OP_0_BAD_CMODE: 6949 reason = "op field equal 0 and bad cmode"; 6950 break; 6951 6952 case UNDEF_XCHG_UNS: 6953 reason = "exchange and unsigned together"; 6954 break; 6955 6956 case UNDEF_NONE: 6957 reason = ""; 6958 break; 6959 } 6960 6961 func (stream, dis_style_text, "\t\tundefined instruction: %s", reason); 6962 } 6963 6964 static void 6965 print_mve_unpredictable (struct disassemble_info *info, 6966 enum mve_unpredictable unpredict_code) 6967 { 6968 void *stream = info->stream; 6969 fprintf_styled_ftype func = info->fprintf_styled_func; 6970 /* Initialize REASON to avoid compiler warning about uninitialized 6971 usage, though such usage should be impossible. */ 6972 const char *reason = "??"; 6973 6974 switch (unpredict_code) 6975 { 6976 case UNPRED_IT_BLOCK: 6977 reason = "mve instruction in it block"; 6978 break; 6979 6980 case UNPRED_FCA_0_FCB_1: 6981 reason = "condition bits, fca = 0 and fcb = 1"; 6982 break; 6983 6984 case UNPRED_R13: 6985 reason = "use of r13 (sp)"; 6986 break; 6987 6988 case UNPRED_R15: 6989 reason = "use of r15 (pc)"; 6990 break; 6991 6992 case UNPRED_Q_GT_4: 6993 reason = "start register block > r4"; 6994 break; 6995 6996 case UNPRED_Q_GT_6: 6997 reason = "start register block > r6"; 6998 break; 6999 7000 case UNPRED_R13_AND_WB: 7001 reason = "use of r13 and write back"; 7002 break; 7003 7004 case UNPRED_Q_REGS_EQUAL: 7005 reason = "same vector register used for destination and other operand"; 7006 break; 7007 7008 case UNPRED_OS: 7009 reason = "use of offset scaled"; 7010 break; 7011 7012 case UNPRED_GP_REGS_EQUAL: 7013 reason = "same general-purpose register used for both operands"; 7014 break; 7015 7016 case UNPRED_Q_REGS_EQ_AND_SIZE_1: 7017 reason = "use of identical q registers and size = 1"; 7018 break; 7019 7020 case UNPRED_Q_REGS_EQ_AND_SIZE_2: 7021 reason = "use of identical q registers and size = 1"; 7022 break; 7023 7024 case UNPRED_NONE: 7025 reason = ""; 7026 break; 7027 } 7028 7029 func (stream, dis_style_comment_start, "%s: %s", 7030 UNPREDICTABLE_INSTRUCTION, reason); 7031 } 7032 7033 /* Print register block operand for mve vld2/vld4/vst2/vld4. */ 7034 7035 static void 7036 print_mve_register_blocks (struct disassemble_info *info, 7037 unsigned long given, 7038 enum mve_instructions matched_insn) 7039 { 7040 void *stream = info->stream; 7041 fprintf_styled_ftype func = info->fprintf_styled_func; 7042 7043 unsigned long q_reg_start = arm_decode_field_multiple (given, 7044 13, 15, 7045 22, 22); 7046 switch (matched_insn) 7047 { 7048 case MVE_VLD2: 7049 case MVE_VST2: 7050 if (q_reg_start <= 6) 7051 { 7052 func (stream, dis_style_text, "{"); 7053 func (stream, dis_style_register, "q%ld", q_reg_start); 7054 func (stream, dis_style_text, ", "); 7055 func (stream, dis_style_register, "q%ld", q_reg_start + 1); 7056 func (stream, dis_style_text, "}"); 7057 } 7058 else 7059 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start); 7060 break; 7061 7062 case MVE_VLD4: 7063 case MVE_VST4: 7064 if (q_reg_start <= 4) 7065 { 7066 func (stream, dis_style_text, "{"); 7067 func (stream, dis_style_register, "q%ld", q_reg_start); 7068 func (stream, dis_style_text, ", "); 7069 func (stream, dis_style_register, "q%ld", q_reg_start + 1); 7070 func (stream, dis_style_text, ", "); 7071 func (stream, dis_style_register, "q%ld", q_reg_start + 2); 7072 func (stream, dis_style_text, ", "); 7073 func (stream, dis_style_register, "q%ld", q_reg_start + 3); 7074 func (stream, dis_style_text, "}"); 7075 } 7076 else 7077 func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start); 7078 break; 7079 7080 default: 7081 break; 7082 } 7083 } 7084 7085 static void 7086 print_mve_rounding_mode (struct disassemble_info *info, 7087 unsigned long given, 7088 enum mve_instructions matched_insn) 7089 { 7090 void *stream = info->stream; 7091 fprintf_styled_ftype func = info->fprintf_styled_func; 7092 7093 switch (matched_insn) 7094 { 7095 case MVE_VCVT_FROM_FP_TO_INT: 7096 { 7097 switch (arm_decode_field (given, 8, 9)) 7098 { 7099 case 0: 7100 func (stream, dis_style_mnemonic, "a"); 7101 break; 7102 7103 case 1: 7104 func (stream, dis_style_mnemonic, "n"); 7105 break; 7106 7107 case 2: 7108 func (stream, dis_style_mnemonic, "p"); 7109 break; 7110 7111 case 3: 7112 func (stream, dis_style_mnemonic, "m"); 7113 break; 7114 7115 default: 7116 break; 7117 } 7118 } 7119 break; 7120 7121 case MVE_VRINT_FP: 7122 { 7123 switch (arm_decode_field (given, 7, 9)) 7124 { 7125 case 0: 7126 func (stream, dis_style_mnemonic, "n"); 7127 break; 7128 7129 case 1: 7130 func (stream, dis_style_mnemonic, "x"); 7131 break; 7132 7133 case 2: 7134 func (stream, dis_style_mnemonic, "a"); 7135 break; 7136 7137 case 3: 7138 func (stream, dis_style_mnemonic, "z"); 7139 break; 7140 7141 case 5: 7142 func (stream, dis_style_mnemonic, "m"); 7143 break; 7144 7145 case 7: 7146 func (stream, dis_style_mnemonic, "p"); 7147 7148 case 4: 7149 case 6: 7150 default: 7151 break; 7152 } 7153 } 7154 break; 7155 7156 default: 7157 break; 7158 } 7159 } 7160 7161 static void 7162 print_mve_vcvt_size (struct disassemble_info *info, 7163 unsigned long given, 7164 enum mve_instructions matched_insn) 7165 { 7166 unsigned long mode = 0; 7167 void *stream = info->stream; 7168 fprintf_styled_ftype func = info->fprintf_styled_func; 7169 7170 switch (matched_insn) 7171 { 7172 case MVE_VCVT_FP_FIX_VEC: 7173 { 7174 mode = (((given & 0x200) >> 7) 7175 | ((given & 0x10000000) >> 27) 7176 | ((given & 0x100) >> 8)); 7177 7178 switch (mode) 7179 { 7180 case 0: 7181 func (stream, dis_style_mnemonic, "f16.s16"); 7182 break; 7183 7184 case 1: 7185 func (stream, dis_style_mnemonic, "s16.f16"); 7186 break; 7187 7188 case 2: 7189 func (stream, dis_style_mnemonic, "f16.u16"); 7190 break; 7191 7192 case 3: 7193 func (stream, dis_style_mnemonic, "u16.f16"); 7194 break; 7195 7196 case 4: 7197 func (stream, dis_style_mnemonic, "f32.s32"); 7198 break; 7199 7200 case 5: 7201 func (stream, dis_style_mnemonic, "s32.f32"); 7202 break; 7203 7204 case 6: 7205 func (stream, dis_style_mnemonic, "f32.u32"); 7206 break; 7207 7208 case 7: 7209 func (stream, dis_style_mnemonic, "u32.f32"); 7210 break; 7211 7212 default: 7213 break; 7214 } 7215 break; 7216 } 7217 case MVE_VCVT_BETWEEN_FP_INT: 7218 { 7219 unsigned long size = arm_decode_field (given, 18, 19); 7220 unsigned long op = arm_decode_field (given, 7, 8); 7221 7222 if (size == 1) 7223 { 7224 switch (op) 7225 { 7226 case 0: 7227 func (stream, dis_style_mnemonic, "f16.s16"); 7228 break; 7229 7230 case 1: 7231 func (stream, dis_style_mnemonic, "f16.u16"); 7232 break; 7233 7234 case 2: 7235 func (stream, dis_style_mnemonic, "s16.f16"); 7236 break; 7237 7238 case 3: 7239 func (stream, dis_style_mnemonic, "u16.f16"); 7240 break; 7241 7242 default: 7243 break; 7244 } 7245 } 7246 else if (size == 2) 7247 { 7248 switch (op) 7249 { 7250 case 0: 7251 func (stream, dis_style_mnemonic, "f32.s32"); 7252 break; 7253 7254 case 1: 7255 func (stream, dis_style_mnemonic, "f32.u32"); 7256 break; 7257 7258 case 2: 7259 func (stream, dis_style_mnemonic, "s32.f32"); 7260 break; 7261 7262 case 3: 7263 func (stream, dis_style_mnemonic, "u32.f32"); 7264 break; 7265 } 7266 } 7267 } 7268 break; 7269 7270 case MVE_VCVT_FP_HALF_FP: 7271 { 7272 unsigned long op = arm_decode_field (given, 28, 28); 7273 if (op == 0) 7274 func (stream, dis_style_mnemonic, "f16.f32"); 7275 else if (op == 1) 7276 func (stream, dis_style_mnemonic, "f32.f16"); 7277 } 7278 break; 7279 7280 case MVE_VCVT_FROM_FP_TO_INT: 7281 { 7282 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19); 7283 7284 switch (size) 7285 { 7286 case 2: 7287 func (stream, dis_style_mnemonic, "s16.f16"); 7288 break; 7289 7290 case 3: 7291 func (stream, dis_style_mnemonic, "u16.f16"); 7292 break; 7293 7294 case 4: 7295 func (stream, dis_style_mnemonic, "s32.f32"); 7296 break; 7297 7298 case 5: 7299 func (stream, dis_style_mnemonic, "u32.f32"); 7300 break; 7301 7302 default: 7303 break; 7304 } 7305 } 7306 break; 7307 7308 default: 7309 break; 7310 } 7311 } 7312 7313 static void 7314 print_mve_rotate (struct disassemble_info *info, unsigned long rot, 7315 unsigned long rot_width) 7316 { 7317 void *stream = info->stream; 7318 fprintf_styled_ftype func = info->fprintf_styled_func; 7319 7320 if (rot_width == 1) 7321 { 7322 switch (rot) 7323 { 7324 case 0: 7325 func (stream, dis_style_immediate, "90"); 7326 break; 7327 case 1: 7328 func (stream, dis_style_immediate, "270"); 7329 break; 7330 default: 7331 break; 7332 } 7333 } 7334 else if (rot_width == 2) 7335 { 7336 switch (rot) 7337 { 7338 case 0: 7339 func (stream, dis_style_immediate, "0"); 7340 break; 7341 case 1: 7342 func (stream, dis_style_immediate, "90"); 7343 break; 7344 case 2: 7345 func (stream, dis_style_immediate, "180"); 7346 break; 7347 case 3: 7348 func (stream, dis_style_immediate, "270"); 7349 break; 7350 default: 7351 break; 7352 } 7353 } 7354 } 7355 7356 static void 7357 print_instruction_predicate (struct disassemble_info *info) 7358 { 7359 void *stream = info->stream; 7360 fprintf_styled_ftype func = info->fprintf_styled_func; 7361 7362 if (vpt_block_state.next_pred_state == PRED_THEN) 7363 func (stream, dis_style_mnemonic, "t"); 7364 else if (vpt_block_state.next_pred_state == PRED_ELSE) 7365 func (stream, dis_style_mnemonic, "e"); 7366 } 7367 7368 static void 7369 print_mve_size (struct disassemble_info *info, 7370 unsigned long size, 7371 enum mve_instructions matched_insn) 7372 { 7373 void *stream = info->stream; 7374 fprintf_styled_ftype func = info->fprintf_styled_func; 7375 7376 switch (matched_insn) 7377 { 7378 case MVE_VABAV: 7379 case MVE_VABD_VEC: 7380 case MVE_VABS_FP: 7381 case MVE_VABS_VEC: 7382 case MVE_VADD_VEC_T1: 7383 case MVE_VADD_VEC_T2: 7384 case MVE_VADDV: 7385 case MVE_VBRSR: 7386 case MVE_VCADD_VEC: 7387 case MVE_VCLS: 7388 case MVE_VCLZ: 7389 case MVE_VCMP_VEC_T1: 7390 case MVE_VCMP_VEC_T2: 7391 case MVE_VCMP_VEC_T3: 7392 case MVE_VCMP_VEC_T4: 7393 case MVE_VCMP_VEC_T5: 7394 case MVE_VCMP_VEC_T6: 7395 case MVE_VCTP: 7396 case MVE_VDDUP: 7397 case MVE_VDWDUP: 7398 case MVE_VHADD_T1: 7399 case MVE_VHADD_T2: 7400 case MVE_VHCADD: 7401 case MVE_VHSUB_T1: 7402 case MVE_VHSUB_T2: 7403 case MVE_VIDUP: 7404 case MVE_VIWDUP: 7405 case MVE_VLD2: 7406 case MVE_VLD4: 7407 case MVE_VLDRB_GATHER_T1: 7408 case MVE_VLDRH_GATHER_T2: 7409 case MVE_VLDRW_GATHER_T3: 7410 case MVE_VLDRD_GATHER_T4: 7411 case MVE_VLDRB_T1: 7412 case MVE_VLDRH_T2: 7413 case MVE_VMAX: 7414 case MVE_VMAXA: 7415 case MVE_VMAXV: 7416 case MVE_VMAXAV: 7417 case MVE_VMIN: 7418 case MVE_VMINA: 7419 case MVE_VMINV: 7420 case MVE_VMINAV: 7421 case MVE_VMLA: 7422 case MVE_VMLAS: 7423 case MVE_VMUL_VEC_T1: 7424 case MVE_VMUL_VEC_T2: 7425 case MVE_VMULH: 7426 case MVE_VRMULH: 7427 case MVE_VMULL_INT: 7428 case MVE_VNEG_FP: 7429 case MVE_VNEG_VEC: 7430 case MVE_VPT_VEC_T1: 7431 case MVE_VPT_VEC_T2: 7432 case MVE_VPT_VEC_T3: 7433 case MVE_VPT_VEC_T4: 7434 case MVE_VPT_VEC_T5: 7435 case MVE_VPT_VEC_T6: 7436 case MVE_VQABS: 7437 case MVE_VQADD_T1: 7438 case MVE_VQADD_T2: 7439 case MVE_VQDMLADH: 7440 case MVE_VQRDMLADH: 7441 case MVE_VQDMLAH: 7442 case MVE_VQRDMLAH: 7443 case MVE_VQDMLASH: 7444 case MVE_VQRDMLASH: 7445 case MVE_VQDMLSDH: 7446 case MVE_VQRDMLSDH: 7447 case MVE_VQDMULH_T1: 7448 case MVE_VQRDMULH_T2: 7449 case MVE_VQDMULH_T3: 7450 case MVE_VQRDMULH_T4: 7451 case MVE_VQNEG: 7452 case MVE_VQRSHL_T1: 7453 case MVE_VQRSHL_T2: 7454 case MVE_VQSHL_T1: 7455 case MVE_VQSHL_T4: 7456 case MVE_VQSUB_T1: 7457 case MVE_VQSUB_T2: 7458 case MVE_VREV32: 7459 case MVE_VREV64: 7460 case MVE_VRHADD: 7461 case MVE_VRINT_FP: 7462 case MVE_VRSHL_T1: 7463 case MVE_VRSHL_T2: 7464 case MVE_VSHL_T2: 7465 case MVE_VSHL_T3: 7466 case MVE_VSHLL_T2: 7467 case MVE_VST2: 7468 case MVE_VST4: 7469 case MVE_VSTRB_SCATTER_T1: 7470 case MVE_VSTRH_SCATTER_T2: 7471 case MVE_VSTRW_SCATTER_T3: 7472 case MVE_VSTRB_T1: 7473 case MVE_VSTRH_T2: 7474 case MVE_VSUB_VEC_T1: 7475 case MVE_VSUB_VEC_T2: 7476 if (size <= 3) 7477 func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]); 7478 else 7479 func (stream, dis_style_text, "<undef size>"); 7480 break; 7481 7482 case MVE_VABD_FP: 7483 case MVE_VADD_FP_T1: 7484 case MVE_VADD_FP_T2: 7485 case MVE_VSUB_FP_T1: 7486 case MVE_VSUB_FP_T2: 7487 case MVE_VCMP_FP_T1: 7488 case MVE_VCMP_FP_T2: 7489 case MVE_VFMA_FP_SCALAR: 7490 case MVE_VFMA_FP: 7491 case MVE_VFMS_FP: 7492 case MVE_VFMAS_FP_SCALAR: 7493 case MVE_VMAXNM_FP: 7494 case MVE_VMAXNMA_FP: 7495 case MVE_VMAXNMV_FP: 7496 case MVE_VMAXNMAV_FP: 7497 case MVE_VMINNM_FP: 7498 case MVE_VMINNMA_FP: 7499 case MVE_VMINNMV_FP: 7500 case MVE_VMINNMAV_FP: 7501 case MVE_VMUL_FP_T1: 7502 case MVE_VMUL_FP_T2: 7503 case MVE_VPT_FP_T1: 7504 case MVE_VPT_FP_T2: 7505 if (size == 0) 7506 func (stream, dis_style_mnemonic, "32"); 7507 else if (size == 1) 7508 func (stream, dis_style_mnemonic, "16"); 7509 break; 7510 7511 case MVE_VCADD_FP: 7512 case MVE_VCMLA_FP: 7513 case MVE_VCMUL_FP: 7514 case MVE_VMLADAV_T1: 7515 case MVE_VMLALDAV: 7516 case MVE_VMLSDAV_T1: 7517 case MVE_VMLSLDAV: 7518 case MVE_VMOVN: 7519 case MVE_VQDMULL_T1: 7520 case MVE_VQDMULL_T2: 7521 case MVE_VQMOVN: 7522 case MVE_VQMOVUN: 7523 if (size == 0) 7524 func (stream, dis_style_mnemonic, "16"); 7525 else if (size == 1) 7526 func (stream, dis_style_mnemonic, "32"); 7527 break; 7528 7529 case MVE_VMOVL: 7530 if (size == 1) 7531 func (stream, dis_style_mnemonic, "8"); 7532 else if (size == 2) 7533 func (stream, dis_style_mnemonic, "16"); 7534 break; 7535 7536 case MVE_VDUP: 7537 switch (size) 7538 { 7539 case 0: 7540 func (stream, dis_style_mnemonic, "32"); 7541 break; 7542 case 1: 7543 func (stream, dis_style_mnemonic, "16"); 7544 break; 7545 case 2: 7546 func (stream, dis_style_mnemonic, "8"); 7547 break; 7548 default: 7549 break; 7550 } 7551 break; 7552 7553 case MVE_VMOV_GP_TO_VEC_LANE: 7554 case MVE_VMOV_VEC_LANE_TO_GP: 7555 switch (size) 7556 { 7557 case 0: case 4: 7558 func (stream, dis_style_mnemonic, "32"); 7559 break; 7560 7561 case 1: case 3: 7562 case 5: case 7: 7563 func (stream, dis_style_mnemonic, "16"); 7564 break; 7565 7566 case 8: case 9: case 10: case 11: 7567 case 12: case 13: case 14: case 15: 7568 func (stream, dis_style_mnemonic, "8"); 7569 break; 7570 7571 default: 7572 break; 7573 } 7574 break; 7575 7576 case MVE_VMOV_IMM_TO_VEC: 7577 switch (size) 7578 { 7579 case 0: case 4: case 8: 7580 case 12: case 24: case 26: 7581 func (stream, dis_style_mnemonic, "i32"); 7582 break; 7583 case 16: case 20: 7584 func (stream, dis_style_mnemonic, "i16"); 7585 break; 7586 case 28: 7587 func (stream, dis_style_mnemonic, "i8"); 7588 break; 7589 case 29: 7590 func (stream, dis_style_mnemonic, "i64"); 7591 break; 7592 case 30: 7593 func (stream, dis_style_mnemonic, "f32"); 7594 break; 7595 default: 7596 break; 7597 } 7598 break; 7599 7600 case MVE_VMULL_POLY: 7601 if (size == 0) 7602 func (stream, dis_style_mnemonic, "p8"); 7603 else if (size == 1) 7604 func (stream, dis_style_mnemonic, "p16"); 7605 break; 7606 7607 case MVE_VMVN_IMM: 7608 switch (size) 7609 { 7610 case 0: case 2: case 4: 7611 case 6: case 12: case 13: 7612 func (stream, dis_style_mnemonic, "32"); 7613 break; 7614 7615 case 8: case 10: 7616 func (stream, dis_style_mnemonic, "16"); 7617 break; 7618 7619 default: 7620 break; 7621 } 7622 break; 7623 7624 case MVE_VBIC_IMM: 7625 case MVE_VORR_IMM: 7626 switch (size) 7627 { 7628 case 1: case 3: 7629 case 5: case 7: 7630 func (stream, dis_style_mnemonic, "32"); 7631 break; 7632 7633 case 9: case 11: 7634 func (stream, dis_style_mnemonic, "16"); 7635 break; 7636 7637 default: 7638 break; 7639 } 7640 break; 7641 7642 case MVE_VQSHRN: 7643 case MVE_VQSHRUN: 7644 case MVE_VQRSHRN: 7645 case MVE_VQRSHRUN: 7646 case MVE_VRSHRN: 7647 case MVE_VSHRN: 7648 { 7649 switch (size) 7650 { 7651 case 1: 7652 func (stream, dis_style_mnemonic, "16"); 7653 break; 7654 7655 case 2: case 3: 7656 func (stream, dis_style_mnemonic, "32"); 7657 break; 7658 7659 default: 7660 break; 7661 } 7662 } 7663 break; 7664 7665 case MVE_VQSHL_T2: 7666 case MVE_VQSHLU_T3: 7667 case MVE_VRSHR: 7668 case MVE_VSHL_T1: 7669 case MVE_VSHLL_T1: 7670 case MVE_VSHR: 7671 case MVE_VSLI: 7672 case MVE_VSRI: 7673 { 7674 switch (size) 7675 { 7676 case 1: 7677 func (stream, dis_style_mnemonic, "8"); 7678 break; 7679 7680 case 2: case 3: 7681 func (stream, dis_style_mnemonic, "16"); 7682 break; 7683 7684 case 4: case 5: case 6: case 7: 7685 func (stream, dis_style_mnemonic, "32"); 7686 break; 7687 7688 default: 7689 break; 7690 } 7691 } 7692 break; 7693 7694 default: 7695 break; 7696 } 7697 } 7698 7699 /* Return true if INSN is a shift insn with an immediate shift amount 7700 which needs decoding as per print_mve_shift_n. */ 7701 7702 static bool 7703 mve_shift_insn_p (enum mve_instructions insn) 7704 { 7705 switch (insn) 7706 { 7707 case MVE_VQSHL_T2: 7708 case MVE_VQSHLU_T3: 7709 case MVE_VQSHRN: 7710 case MVE_VQSHRUN: 7711 case MVE_VQRSHRN: 7712 case MVE_VQRSHRUN: 7713 case MVE_VRSHR: 7714 case MVE_VRSHRN: 7715 case MVE_VSHL_T1: 7716 case MVE_VSHLL_T1: 7717 case MVE_VSHR: 7718 case MVE_VSHRN: 7719 case MVE_VSLI: 7720 case MVE_VSRI: 7721 return true; 7722 default: 7723 return false; 7724 } 7725 } 7726 7727 static void 7728 print_mve_shift_n (struct disassemble_info *info, long given, 7729 enum mve_instructions matched_insn) 7730 { 7731 void *stream = info->stream; 7732 fprintf_styled_ftype func = info->fprintf_styled_func; 7733 7734 int startAt0 7735 = matched_insn == MVE_VQSHL_T2 7736 || matched_insn == MVE_VQSHLU_T3 7737 || matched_insn == MVE_VSHL_T1 7738 || matched_insn == MVE_VSHLL_T1 7739 || matched_insn == MVE_VSLI; 7740 7741 unsigned imm6 = (given & 0x3f0000) >> 16; 7742 7743 if (matched_insn == MVE_VSHLL_T1) 7744 imm6 &= 0x1f; 7745 7746 unsigned shiftAmount = 0; 7747 if ((imm6 & 0x20) != 0) 7748 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6; 7749 else if ((imm6 & 0x10) != 0) 7750 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6; 7751 else if ((imm6 & 0x08) != 0) 7752 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6; 7753 else 7754 print_mve_undefined (info, UNDEF_SIZE_0); 7755 7756 func (stream, dis_style_immediate, "%u", shiftAmount); 7757 } 7758 7759 static void 7760 print_vec_condition (struct disassemble_info *info, long given, 7761 enum mve_instructions matched_insn) 7762 { 7763 void *stream = info->stream; 7764 fprintf_styled_ftype func = info->fprintf_styled_func; 7765 long vec_cond = 0; 7766 7767 switch (matched_insn) 7768 { 7769 case MVE_VPT_FP_T1: 7770 case MVE_VCMP_FP_T1: 7771 vec_cond = (((given & 0x1000) >> 10) 7772 | ((given & 1) << 1) 7773 | ((given & 0x0080) >> 7)); 7774 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7775 break; 7776 7777 case MVE_VPT_FP_T2: 7778 case MVE_VCMP_FP_T2: 7779 vec_cond = (((given & 0x1000) >> 10) 7780 | ((given & 0x0020) >> 4) 7781 | ((given & 0x0080) >> 7)); 7782 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7783 break; 7784 7785 case MVE_VPT_VEC_T1: 7786 case MVE_VCMP_VEC_T1: 7787 vec_cond = (given & 0x0080) >> 7; 7788 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7789 break; 7790 7791 case MVE_VPT_VEC_T2: 7792 case MVE_VCMP_VEC_T2: 7793 vec_cond = 2 | ((given & 0x0080) >> 7); 7794 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7795 break; 7796 7797 case MVE_VPT_VEC_T3: 7798 case MVE_VCMP_VEC_T3: 7799 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7); 7800 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7801 break; 7802 7803 case MVE_VPT_VEC_T4: 7804 case MVE_VCMP_VEC_T4: 7805 vec_cond = (given & 0x0080) >> 7; 7806 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7807 break; 7808 7809 case MVE_VPT_VEC_T5: 7810 case MVE_VCMP_VEC_T5: 7811 vec_cond = 2 | ((given & 0x0080) >> 7); 7812 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7813 break; 7814 7815 case MVE_VPT_VEC_T6: 7816 case MVE_VCMP_VEC_T6: 7817 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7); 7818 func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]); 7819 break; 7820 7821 case MVE_NONE: 7822 case MVE_VPST: 7823 default: 7824 break; 7825 } 7826 } 7827 7828 #define W_BIT 21 7829 #define I_BIT 22 7830 #define U_BIT 23 7831 #define P_BIT 24 7832 7833 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 7834 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 7835 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 7836 #define PRE_BIT_SET (given & (1 << P_BIT)) 7837 7838 /* The assembler string for an instruction can include %{X:...%} patterns, 7839 where the 'X' is one of the characters understood by this function. 7840 7841 This function takes the X character, and returns a new style. This new 7842 style will be used by the caller to temporarily change the current base 7843 style. */ 7844 7845 static enum disassembler_style 7846 decode_base_style (const char x) 7847 { 7848 switch (x) 7849 { 7850 case 'A': return dis_style_address; 7851 case 'B': return dis_style_sub_mnemonic; 7852 case 'C': return dis_style_comment_start; 7853 case 'D': return dis_style_assembler_directive; 7854 case 'I': return dis_style_immediate; 7855 case 'M': return dis_style_mnemonic; 7856 case 'O': return dis_style_address_offset; 7857 case 'R': return dis_style_register; 7858 case 'S': return dis_style_symbol; 7859 case 'T': return dis_style_text; 7860 default: 7861 abort (); 7862 } 7863 } 7864 7865 /* Print one coprocessor instruction on INFO->STREAM. 7866 Return TRUE if the instuction matched, FALSE if this is not a 7867 recognised coprocessor instruction. */ 7868 7869 static bool 7870 print_insn_coprocessor_1 (const struct sopcode32 *opcodes, 7871 bfd_vma pc, 7872 struct disassemble_info *info, 7873 long given, 7874 bool thumb) 7875 { 7876 const struct sopcode32 *insn; 7877 void *stream = info->stream; 7878 fprintf_styled_ftype func = info->fprintf_styled_func; 7879 unsigned long mask; 7880 unsigned long value = 0; 7881 int cond; 7882 int cp_num; 7883 struct arm_private_data *private_data = info->private_data; 7884 arm_feature_set allowed_arches = ARM_ARCH_NONE; 7885 arm_feature_set arm_ext_v8_1m_main = 7886 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 7887 enum disassembler_style base_style = dis_style_mnemonic; 7888 enum disassembler_style old_base_style = base_style; 7889 7890 allowed_arches = private_data->features; 7891 7892 for (insn = opcodes; insn->assembler; insn++) 7893 { 7894 unsigned long u_reg = 16; 7895 bool is_unpredictable = false; 7896 signed long value_in_comment = 0; 7897 const char *c; 7898 7899 if (ARM_FEATURE_ZERO (insn->arch)) 7900 switch (insn->value) 7901 { 7902 case SENTINEL_IWMMXT_START: 7903 if (info->mach != bfd_mach_arm_XScale 7904 && info->mach != bfd_mach_arm_iWMMXt 7905 && info->mach != bfd_mach_arm_iWMMXt2) 7906 do 7907 insn++; 7908 while ((! ARM_FEATURE_ZERO (insn->arch)) 7909 && insn->value != SENTINEL_IWMMXT_END); 7910 continue; 7911 7912 case SENTINEL_IWMMXT_END: 7913 continue; 7914 7915 case SENTINEL_GENERIC_START: 7916 allowed_arches = private_data->features; 7917 continue; 7918 7919 default: 7920 abort (); 7921 } 7922 7923 mask = insn->mask; 7924 value = insn->value; 7925 cp_num = (given >> 8) & 0xf; 7926 7927 if (thumb) 7928 { 7929 /* The high 4 bits are 0xe for Arm conditional instructions, and 7930 0xe for arm unconditional instructions. The rest of the 7931 encoding is the same. */ 7932 mask |= 0xf0000000; 7933 value |= 0xe0000000; 7934 if (ifthen_state) 7935 cond = IFTHEN_COND; 7936 else 7937 cond = COND_UNCOND; 7938 } 7939 else 7940 { 7941 /* Only match unconditional instuctions against unconditional 7942 patterns. */ 7943 if ((given & 0xf0000000) == 0xf0000000) 7944 { 7945 mask |= 0xf0000000; 7946 cond = COND_UNCOND; 7947 } 7948 else 7949 { 7950 cond = (given >> 28) & 0xf; 7951 if (cond == 0xe) 7952 cond = COND_UNCOND; 7953 } 7954 } 7955 7956 if ((insn->isa == T32 && !thumb) 7957 || (insn->isa == ARM && thumb)) 7958 continue; 7959 7960 if ((given & mask) != value) 7961 continue; 7962 7963 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 7964 continue; 7965 7966 if (insn->value == 0xfe000010 /* mcr2 */ 7967 || insn->value == 0xfe100010 /* mrc2 */ 7968 || insn->value == 0xfc100000 /* ldc2 */ 7969 || insn->value == 0xfc000000) /* stc2 */ 7970 { 7971 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 7972 is_unpredictable = true; 7973 7974 /* Armv8.1-M Mainline FP & MVE instructions. */ 7975 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 7976 && !ARM_CPU_IS_ANY (allowed_arches) 7977 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 7978 continue; 7979 7980 } 7981 else if (insn->value == 0x0e000000 /* cdp */ 7982 || insn->value == 0xfe000000 /* cdp2 */ 7983 || insn->value == 0x0e000010 /* mcr */ 7984 || insn->value == 0x0e100010 /* mrc */ 7985 || insn->value == 0x0c100000 /* ldc */ 7986 || insn->value == 0x0c000000) /* stc */ 7987 { 7988 /* Floating-point instructions. */ 7989 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 7990 continue; 7991 7992 /* Armv8.1-M Mainline FP & MVE instructions. */ 7993 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 7994 && !ARM_CPU_IS_ANY (allowed_arches) 7995 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 7996 continue; 7997 } 7998 else if ((insn->value == 0xec100f80 /* vldr (system register) */ 7999 || insn->value == 0xec000f80) /* vstr (system register) */ 8000 && arm_decode_field (given, 24, 24) == 0 8001 && arm_decode_field (given, 21, 21) == 0) 8002 /* If the P and W bits are both 0 then these encodings match the MVE 8003 VLDR and VSTR instructions, these are in a different table, so we 8004 don't let it match here. */ 8005 continue; 8006 8007 for (c = insn->assembler; *c; c++) 8008 { 8009 if (*c == '%') 8010 { 8011 const char mod = *++c; 8012 8013 switch (mod) 8014 { 8015 case '{': 8016 ++c; 8017 if (*c == '\0') 8018 abort (); 8019 old_base_style = base_style; 8020 base_style = decode_base_style (*c); 8021 ++c; 8022 if (*c != ':') 8023 abort (); 8024 break; 8025 8026 case '}': 8027 base_style = old_base_style; 8028 break; 8029 8030 case '%': 8031 func (stream, base_style, "%%"); 8032 break; 8033 8034 case 'A': 8035 case 'K': 8036 { 8037 int rn = (given >> 16) & 0xf; 8038 bfd_vma offset = given & 0xff; 8039 8040 if (mod == 'K') 8041 offset = given & 0x7f; 8042 8043 func (stream, dis_style_text, "["); 8044 func (stream, dis_style_register, "%s", 8045 arm_regnames [(given >> 16) & 0xf]); 8046 8047 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 8048 { 8049 /* Not unindexed. The offset is scaled. */ 8050 if (cp_num == 9) 8051 /* vldr.16/vstr.16 will shift the address 8052 left by 1 bit only. */ 8053 offset = offset * 2; 8054 else 8055 offset = offset * 4; 8056 8057 if (NEGATIVE_BIT_SET) 8058 offset = - offset; 8059 if (rn != 15) 8060 value_in_comment = offset; 8061 } 8062 8063 if (PRE_BIT_SET) 8064 { 8065 if (offset) 8066 { 8067 func (stream, dis_style_text, ", "); 8068 func (stream, dis_style_immediate, "#%d", 8069 (int) offset); 8070 func (stream, dis_style_text, "]%s", 8071 WRITEBACK_BIT_SET ? "!" : ""); 8072 } 8073 else if (NEGATIVE_BIT_SET) 8074 { 8075 func (stream, dis_style_text, ", "); 8076 func (stream, dis_style_immediate, "#-0"); 8077 func (stream, dis_style_text, "]"); 8078 } 8079 else 8080 func (stream, dis_style_text, "]"); 8081 } 8082 else 8083 { 8084 func (stream, dis_style_text, "]"); 8085 8086 if (WRITEBACK_BIT_SET) 8087 { 8088 if (offset) 8089 { 8090 func (stream, dis_style_text, ", "); 8091 func (stream, dis_style_immediate, 8092 "#%d", (int) offset); 8093 } 8094 else if (NEGATIVE_BIT_SET) 8095 { 8096 func (stream, dis_style_text, ", "); 8097 func (stream, dis_style_immediate, "#-0"); 8098 } 8099 } 8100 else 8101 { 8102 func (stream, dis_style_text, ", {"); 8103 func (stream, dis_style_immediate, "%s%d", 8104 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 8105 (int) offset); 8106 func (stream, dis_style_text, "}"); 8107 value_in_comment = offset; 8108 } 8109 } 8110 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 8111 { 8112 func (stream, dis_style_comment_start, "\t@ "); 8113 /* For unaligned PCs, apply off-by-alignment 8114 correction. */ 8115 info->print_address_func (offset + pc 8116 + info->bytes_per_chunk * 2 8117 - (pc & 3), 8118 info); 8119 } 8120 } 8121 break; 8122 8123 case 'B': 8124 { 8125 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 8126 int offset = (given >> 1) & 0x3f; 8127 8128 func (stream, dis_style_text, "{"); 8129 if (offset == 1) 8130 func (stream, dis_style_register, "d%d", regno); 8131 else if (regno + offset > 32) 8132 { 8133 func (stream, dis_style_register, "d%d", regno); 8134 func (stream, dis_style_text, "-<overflow reg d%d>", 8135 regno + offset - 1); 8136 } 8137 else 8138 { 8139 func (stream, dis_style_register, "d%d", regno); 8140 func (stream, dis_style_text, "-"); 8141 func (stream, dis_style_register, "d%d", 8142 regno + offset - 1); 8143 } 8144 func (stream, dis_style_text, "}"); 8145 } 8146 break; 8147 8148 case 'C': 8149 { 8150 bool single = ((given >> 8) & 1) == 0; 8151 char reg_prefix = single ? 's' : 'd'; 8152 int Dreg = (given >> 22) & 0x1; 8153 int Vdreg = (given >> 12) & 0xf; 8154 int reg = single ? ((Vdreg << 1) | Dreg) 8155 : ((Dreg << 4) | Vdreg); 8156 int num = (given >> (single ? 0 : 1)) & 0x7f; 8157 int maxreg = single ? 31 : 15; 8158 int topreg = reg + num - 1; 8159 8160 func (stream, dis_style_text, "{"); 8161 if (!num) 8162 { 8163 /* Nothing. */ 8164 } 8165 else if (num == 1) 8166 { 8167 func (stream, dis_style_register, 8168 "%c%d", reg_prefix, reg); 8169 func (stream, dis_style_text, ", "); 8170 } 8171 else if (topreg > maxreg) 8172 { 8173 func (stream, dis_style_register, "%c%d", 8174 reg_prefix, reg); 8175 func (stream, dis_style_text, "-<overflow reg d%d, ", 8176 single ? topreg >> 1 : topreg); 8177 } 8178 else 8179 { 8180 func (stream, dis_style_register, 8181 "%c%d", reg_prefix, reg); 8182 func (stream, dis_style_text, "-"); 8183 func (stream, dis_style_register, "%c%d", 8184 reg_prefix, topreg); 8185 func (stream, dis_style_text, ", "); 8186 } 8187 func (stream, dis_style_register, "VPR"); 8188 func (stream, dis_style_text, "}"); 8189 } 8190 break; 8191 8192 case 'u': 8193 if (cond != COND_UNCOND) 8194 is_unpredictable = true; 8195 8196 /* Fall through. */ 8197 case 'c': 8198 if (cond != COND_UNCOND && cp_num == 9) 8199 is_unpredictable = true; 8200 8201 /* Fall through. */ 8202 case 'b': 8203 func (stream, dis_style_mnemonic, "%s", 8204 arm_conditional[cond]); 8205 break; 8206 8207 case 'J': 8208 { 8209 unsigned long regno 8210 = arm_decode_field_multiple (given, 13, 15, 22, 22); 8211 8212 switch (regno) 8213 { 8214 case 0x1: 8215 func (stream, dis_style_register, "FPSCR"); 8216 break; 8217 case 0x2: 8218 func (stream, dis_style_register, "FPSCR_nzcvqc"); 8219 break; 8220 case 0xc: 8221 func (stream, dis_style_register, "VPR"); 8222 break; 8223 case 0xd: 8224 func (stream, dis_style_register, "P0"); 8225 break; 8226 case 0xe: 8227 func (stream, dis_style_register, "FPCXTNS"); 8228 break; 8229 case 0xf: 8230 func (stream, dis_style_register, "FPCXTS"); 8231 break; 8232 default: 8233 func (stream, dis_style_text, "<invalid reg %lu>", 8234 regno); 8235 break; 8236 } 8237 } 8238 break; 8239 8240 case '0': case '1': case '2': case '3': case '4': 8241 case '5': case '6': case '7': case '8': case '9': 8242 { 8243 int width; 8244 8245 c = arm_decode_bitfield (c, given, &value, &width); 8246 8247 switch (*c) 8248 { 8249 case 'R': 8250 if (value == 15) 8251 is_unpredictable = true; 8252 /* Fall through. */ 8253 case 'r': 8254 if (c[1] == 'u') 8255 { 8256 /* Eat the 'u' character. */ 8257 ++ c; 8258 8259 if (u_reg == value) 8260 is_unpredictable = true; 8261 u_reg = value; 8262 } 8263 func (stream, dis_style_register, "%s", 8264 arm_regnames[value]); 8265 break; 8266 case 'V': 8267 if (given & (1 << 6)) 8268 goto Q; 8269 /* FALLTHROUGH */ 8270 case 'D': 8271 func (stream, dis_style_register, "d%ld", value); 8272 break; 8273 case 'Q': 8274 Q: 8275 if (value & 1) 8276 func (stream, dis_style_text, 8277 "<illegal reg q%ld.5>", value >> 1); 8278 else 8279 func (stream, dis_style_register, 8280 "q%ld", value >> 1); 8281 break; 8282 case 'd': 8283 func (stream, base_style, "%ld", value); 8284 value_in_comment = value; 8285 break; 8286 case 'E': 8287 { 8288 /* Converts immediate 8 bit back to float value. */ 8289 unsigned floatVal = (value & 0x80) << 24 8290 | (value & 0x3F) << 19 8291 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 8292 8293 /* Quarter float have a maximum value of 31.0. 8294 Get floating point value multiplied by 1e7. 8295 The maximum value stays in limit of a 32-bit int. */ 8296 unsigned decVal = 8297 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 8298 (16 + (value & 0xF)); 8299 8300 if (!(decVal % 1000000)) 8301 { 8302 func (stream, dis_style_immediate, "%ld", value); 8303 func (stream, dis_style_comment_start, 8304 "\t@ 0x%08x %c%u.%01u", 8305 floatVal, value & 0x80 ? '-' : ' ', 8306 decVal / 10000000, 8307 decVal % 10000000 / 1000000); 8308 } 8309 else if (!(decVal % 10000)) 8310 { 8311 func (stream, dis_style_immediate, "%ld", value); 8312 func (stream, dis_style_comment_start, 8313 "\t@ 0x%08x %c%u.%03u", 8314 floatVal, value & 0x80 ? '-' : ' ', 8315 decVal / 10000000, 8316 decVal % 10000000 / 10000); 8317 } 8318 else 8319 { 8320 func (stream, dis_style_immediate, "%ld", value); 8321 func (stream, dis_style_comment_start, 8322 "\t@ 0x%08x %c%u.%07u", 8323 floatVal, value & 0x80 ? '-' : ' ', 8324 decVal / 10000000, decVal % 10000000); 8325 } 8326 break; 8327 } 8328 case 'k': 8329 { 8330 int from = (given & (1 << 7)) ? 32 : 16; 8331 func (stream, dis_style_immediate, "%ld", 8332 from - value); 8333 } 8334 break; 8335 8336 case 'w': 8337 if (width == 2) 8338 func (stream, dis_style_mnemonic, "%s", 8339 iwmmxt_wwnames[value]); 8340 else 8341 func (stream, dis_style_mnemonic, "%s", 8342 iwmmxt_wwssnames[value]); 8343 break; 8344 8345 case 'g': 8346 func (stream, dis_style_register, "%s", 8347 iwmmxt_regnames[value]); 8348 break; 8349 case 'G': 8350 func (stream, dis_style_register, "%s", 8351 iwmmxt_cregnames[value]); 8352 break; 8353 8354 case 'x': 8355 func (stream, dis_style_immediate, "0x%lx", 8356 (value & 0xffffffffUL)); 8357 break; 8358 8359 case 'c': 8360 switch (value) 8361 { 8362 case 0: 8363 func (stream, dis_style_mnemonic, "eq"); 8364 break; 8365 8366 case 1: 8367 func (stream, dis_style_mnemonic, "vs"); 8368 break; 8369 8370 case 2: 8371 func (stream, dis_style_mnemonic, "ge"); 8372 break; 8373 8374 case 3: 8375 func (stream, dis_style_mnemonic, "gt"); 8376 break; 8377 8378 default: 8379 func (stream, dis_style_text, "??"); 8380 break; 8381 } 8382 break; 8383 8384 case '`': 8385 c++; 8386 if (value == 0) 8387 func (stream, dis_style_mnemonic, "%c", *c); 8388 break; 8389 case '\'': 8390 c++; 8391 if (value == ((1ul << width) - 1)) 8392 func (stream, base_style, "%c", *c); 8393 break; 8394 case '?': 8395 func (stream, base_style, "%c", 8396 c[(1 << width) - (int) value]); 8397 c += 1 << width; 8398 break; 8399 default: 8400 abort (); 8401 } 8402 } 8403 break; 8404 8405 case 'y': 8406 case 'z': 8407 { 8408 int single = *c++ == 'y'; 8409 int regno; 8410 8411 switch (*c) 8412 { 8413 case '4': /* Sm pair */ 8414 case '0': /* Sm, Dm */ 8415 regno = given & 0x0000000f; 8416 if (single) 8417 { 8418 regno <<= 1; 8419 regno += (given >> 5) & 1; 8420 } 8421 else 8422 regno += ((given >> 5) & 1) << 4; 8423 break; 8424 8425 case '1': /* Sd, Dd */ 8426 regno = (given >> 12) & 0x0000000f; 8427 if (single) 8428 { 8429 regno <<= 1; 8430 regno += (given >> 22) & 1; 8431 } 8432 else 8433 regno += ((given >> 22) & 1) << 4; 8434 break; 8435 8436 case '2': /* Sn, Dn */ 8437 regno = (given >> 16) & 0x0000000f; 8438 if (single) 8439 { 8440 regno <<= 1; 8441 regno += (given >> 7) & 1; 8442 } 8443 else 8444 regno += ((given >> 7) & 1) << 4; 8445 break; 8446 8447 case '3': /* List */ 8448 func (stream, dis_style_text, "{"); 8449 regno = (given >> 12) & 0x0000000f; 8450 if (single) 8451 { 8452 regno <<= 1; 8453 regno += (given >> 22) & 1; 8454 } 8455 else 8456 regno += ((given >> 22) & 1) << 4; 8457 break; 8458 8459 default: 8460 abort (); 8461 } 8462 8463 func (stream, dis_style_register, "%c%d", 8464 single ? 's' : 'd', regno); 8465 8466 if (*c == '3') 8467 { 8468 int count = given & 0xff; 8469 8470 if (single == 0) 8471 count >>= 1; 8472 8473 if (--count) 8474 { 8475 func (stream, dis_style_text, "-"); 8476 func (stream, dis_style_register, "%c%d", 8477 single ? 's' : 'd', 8478 regno + count); 8479 } 8480 8481 func (stream, dis_style_text, "}"); 8482 } 8483 else if (*c == '4') 8484 { 8485 func (stream, dis_style_text, ", "); 8486 func (stream, dis_style_register, "%c%d", 8487 single ? 's' : 'd', regno + 1); 8488 } 8489 } 8490 break; 8491 8492 case 'L': 8493 switch (given & 0x00400100) 8494 { 8495 case 0x00000000: 8496 func (stream, dis_style_mnemonic, "b"); 8497 break; 8498 case 0x00400000: 8499 func (stream, dis_style_mnemonic, "h"); 8500 break; 8501 case 0x00000100: 8502 func (stream, dis_style_mnemonic, "w"); 8503 break; 8504 case 0x00400100: 8505 func (stream, dis_style_mnemonic, "d"); 8506 break; 8507 default: 8508 break; 8509 } 8510 break; 8511 8512 case 'Z': 8513 { 8514 /* given (20, 23) | given (0, 3) */ 8515 value = ((given >> 16) & 0xf0) | (given & 0xf); 8516 func (stream, dis_style_immediate, "%d", (int) value); 8517 } 8518 break; 8519 8520 case 'l': 8521 /* This is like the 'A' operator, except that if 8522 the width field "M" is zero, then the offset is 8523 *not* multiplied by four. */ 8524 { 8525 int offset = given & 0xff; 8526 int multiplier = (given & 0x00000100) ? 4 : 1; 8527 8528 func (stream, dis_style_text, "["); 8529 func (stream, dis_style_register, "%s", 8530 arm_regnames [(given >> 16) & 0xf]); 8531 8532 if (multiplier > 1) 8533 { 8534 value_in_comment = offset * multiplier; 8535 if (NEGATIVE_BIT_SET) 8536 value_in_comment = - value_in_comment; 8537 } 8538 8539 if (offset) 8540 { 8541 if (PRE_BIT_SET) 8542 { 8543 func (stream, dis_style_text, ", "); 8544 func (stream, dis_style_immediate, "#%s%d", 8545 NEGATIVE_BIT_SET ? "-" : "", 8546 offset * multiplier); 8547 func (stream, dis_style_text, "]%s", 8548 WRITEBACK_BIT_SET ? "!" : ""); 8549 } 8550 else 8551 { 8552 func (stream, dis_style_text, "], "); 8553 func (stream, dis_style_immediate, "#%s%d", 8554 NEGATIVE_BIT_SET ? "-" : "", 8555 offset * multiplier); 8556 } 8557 } 8558 else 8559 func (stream, dis_style_text, "]"); 8560 } 8561 break; 8562 8563 case 'r': 8564 { 8565 int imm4 = (given >> 4) & 0xf; 8566 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 8567 int ubit = ! NEGATIVE_BIT_SET; 8568 const char *rm = arm_regnames [given & 0xf]; 8569 const char *rn = arm_regnames [(given >> 16) & 0xf]; 8570 8571 switch (puw_bits) 8572 { 8573 case 1: 8574 case 3: 8575 func (stream, dis_style_text, "["); 8576 func (stream, dis_style_register, "%s", rn); 8577 func (stream, dis_style_text, "], "); 8578 func (stream, dis_style_text, "%c", ubit ? '+' : '-'); 8579 func (stream, dis_style_register, "%s", rm); 8580 if (imm4) 8581 { 8582 func (stream, dis_style_text, ", "); 8583 func (stream, dis_style_sub_mnemonic, "lsl "); 8584 func (stream, dis_style_immediate, "#%d", imm4); 8585 } 8586 break; 8587 8588 case 4: 8589 case 5: 8590 case 6: 8591 case 7: 8592 func (stream, dis_style_text, "["); 8593 func (stream, dis_style_register, "%s", rn); 8594 func (stream, dis_style_text, ", "); 8595 func (stream, dis_style_text, "%c", ubit ? '+' : '-'); 8596 func (stream, dis_style_register, "%s", rm); 8597 if (imm4 > 0) 8598 { 8599 func (stream, dis_style_text, ", "); 8600 func (stream, dis_style_sub_mnemonic, "lsl "); 8601 func (stream, dis_style_immediate, "#%d", imm4); 8602 } 8603 func (stream, dis_style_text, "]"); 8604 if (puw_bits == 5 || puw_bits == 7) 8605 func (stream, dis_style_text, "!"); 8606 break; 8607 8608 default: 8609 func (stream, dis_style_text, "INVALID"); 8610 } 8611 } 8612 break; 8613 8614 case 'i': 8615 { 8616 long imm5; 8617 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 8618 func (stream, dis_style_immediate, "%ld", 8619 (imm5 == 0) ? 32 : imm5); 8620 } 8621 break; 8622 8623 default: 8624 abort (); 8625 } 8626 } 8627 else 8628 { 8629 if (*c == '@') 8630 base_style = dis_style_comment_start; 8631 8632 if (*c == '\t') 8633 base_style = dis_style_text; 8634 8635 func (stream, base_style, "%c", *c); 8636 } 8637 } 8638 8639 if (value_in_comment > 32 || value_in_comment < -16) 8640 func (stream, dis_style_comment_start, "\t@ 0x%lx", 8641 (value_in_comment & 0xffffffffUL)); 8642 8643 if (is_unpredictable) 8644 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 8645 8646 return true; 8647 } 8648 return false; 8649 } 8650 8651 static bool 8652 print_insn_coprocessor (bfd_vma pc, 8653 struct disassemble_info *info, 8654 long given, 8655 bool thumb) 8656 { 8657 return print_insn_coprocessor_1 (coprocessor_opcodes, 8658 pc, info, given, thumb); 8659 } 8660 8661 static bool 8662 print_insn_generic_coprocessor (bfd_vma pc, 8663 struct disassemble_info *info, 8664 long given, 8665 bool thumb) 8666 { 8667 return print_insn_coprocessor_1 (generic_coprocessor_opcodes, 8668 pc, info, given, thumb); 8669 } 8670 8671 /* Decodes and prints ARM addressing modes. Returns the offset 8672 used in the address, if any, if it is worthwhile printing the 8673 offset as a hexadecimal value in a comment at the end of the 8674 line of disassembly. */ 8675 8676 static signed long 8677 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 8678 { 8679 void *stream = info->stream; 8680 fprintf_styled_ftype func = info->fprintf_styled_func; 8681 bfd_vma offset = 0; 8682 8683 if (((given & 0x000f0000) == 0x000f0000) 8684 && ((given & 0x02000000) == 0)) 8685 { 8686 offset = given & 0xfff; 8687 8688 func (stream, dis_style_text, "["); 8689 func (stream, dis_style_register, "pc"); 8690 8691 if (PRE_BIT_SET) 8692 { 8693 /* Pre-indexed. Elide offset of positive zero when 8694 non-writeback. */ 8695 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8696 { 8697 func (stream, dis_style_text, ", "); 8698 func (stream, dis_style_immediate, "#%s%d", 8699 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8700 } 8701 8702 if (NEGATIVE_BIT_SET) 8703 offset = -offset; 8704 8705 offset += pc + 8; 8706 8707 /* Cope with the possibility of write-back 8708 being used. Probably a very dangerous thing 8709 for the programmer to do, but who are we to 8710 argue ? */ 8711 func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 8712 } 8713 else /* Post indexed. */ 8714 { 8715 func (stream, dis_style_text, "], "); 8716 func (stream, dis_style_immediate, "#%s%d", 8717 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8718 8719 /* Ie ignore the offset. */ 8720 offset = pc + 8; 8721 } 8722 8723 func (stream, dis_style_comment_start, "\t@ "); 8724 info->print_address_func (offset, info); 8725 offset = 0; 8726 } 8727 else 8728 { 8729 func (stream, dis_style_text, "["); 8730 func (stream, dis_style_register, "%s", 8731 arm_regnames[(given >> 16) & 0xf]); 8732 8733 if (PRE_BIT_SET) 8734 { 8735 if ((given & 0x02000000) == 0) 8736 { 8737 /* Elide offset of positive zero when non-writeback. */ 8738 offset = given & 0xfff; 8739 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8740 { 8741 func (stream, dis_style_text, ", "); 8742 func (stream, dis_style_immediate, "#%s%d", 8743 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8744 } 8745 } 8746 else 8747 { 8748 func (stream, dis_style_text, ", %s", 8749 NEGATIVE_BIT_SET ? "-" : ""); 8750 arm_decode_shift (given, func, stream, true); 8751 } 8752 8753 func (stream, dis_style_text, "]%s", 8754 WRITEBACK_BIT_SET ? "!" : ""); 8755 } 8756 else 8757 { 8758 if ((given & 0x02000000) == 0) 8759 { 8760 /* Always show offset. */ 8761 offset = given & 0xfff; 8762 func (stream, dis_style_text, "], "); 8763 func (stream, dis_style_immediate, "#%s%d", 8764 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8765 } 8766 else 8767 { 8768 func (stream, dis_style_text, "], %s", 8769 NEGATIVE_BIT_SET ? "-" : ""); 8770 arm_decode_shift (given, func, stream, true); 8771 } 8772 } 8773 if (NEGATIVE_BIT_SET) 8774 offset = -offset; 8775 } 8776 8777 return (signed long) offset; 8778 } 8779 8780 8781 /* Print one cde instruction on INFO->STREAM. 8782 Return TRUE if the instuction matched, FALSE if this is not a 8783 recognised cde instruction. */ 8784 static bool 8785 print_insn_cde (struct disassemble_info *info, long given, bool thumb) 8786 { 8787 const struct cdeopcode32 *insn; 8788 void *stream = info->stream; 8789 fprintf_styled_ftype func = info->fprintf_styled_func; 8790 enum disassembler_style base_style = dis_style_mnemonic; 8791 enum disassembler_style old_base_style = base_style; 8792 8793 if (thumb) 8794 { 8795 /* Manually extract the coprocessor code from a known point. 8796 This position is the same across all CDE instructions. */ 8797 for (insn = cde_opcodes; insn->assembler; insn++) 8798 { 8799 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask; 8800 uint16_t coproc_mask = 1 << coproc; 8801 if (! (coproc_mask & cde_coprocs)) 8802 continue; 8803 8804 if ((given & insn->mask) == insn->value) 8805 { 8806 bool is_unpredictable = false; 8807 const char *c; 8808 8809 for (c = insn->assembler; *c; c++) 8810 { 8811 if (*c == '%') 8812 { 8813 switch (*++c) 8814 { 8815 case '{': 8816 ++c; 8817 if (*c == '\0') 8818 abort (); 8819 old_base_style = base_style; 8820 base_style = decode_base_style (*c); 8821 ++c; 8822 if (*c != ':') 8823 abort (); 8824 break; 8825 8826 case '}': 8827 base_style = old_base_style; 8828 break; 8829 8830 case '%': 8831 func (stream, base_style, "%%"); 8832 break; 8833 8834 case '0': case '1': case '2': case '3': case '4': 8835 case '5': case '6': case '7': case '8': case '9': 8836 { 8837 int width; 8838 unsigned long value; 8839 8840 c = arm_decode_bitfield (c, given, &value, &width); 8841 8842 switch (*c) 8843 { 8844 case 'S': 8845 if (value > 10) 8846 is_unpredictable = true; 8847 /* Fall through. */ 8848 case 'R': 8849 if (value == 13) 8850 is_unpredictable = true; 8851 /* Fall through. */ 8852 case 'r': 8853 func (stream, dis_style_register, "%s", 8854 arm_regnames[value]); 8855 break; 8856 8857 case 'n': 8858 if (value == 15) 8859 func (stream, dis_style_register, "%s", "APSR_nzcv"); 8860 else 8861 func (stream, dis_style_register, "%s", 8862 arm_regnames[value]); 8863 break; 8864 8865 case 'T': 8866 func (stream, dis_style_register, "%s", 8867 arm_regnames[(value + 1) & 15]); 8868 break; 8869 8870 case 'd': 8871 func (stream, dis_style_immediate, "%ld", value); 8872 break; 8873 8874 case 'V': 8875 if (given & (1 << 6)) 8876 func (stream, dis_style_register, "q%ld", value >> 1); 8877 else if (given & (1 << 24)) 8878 func (stream, dis_style_register, "d%ld", value); 8879 else 8880 { 8881 /* Encoding for S register is different than for D and 8882 Q registers. S registers are encoded using the top 8883 single bit in position 22 as the lowest bit of the 8884 register number, while for Q and D it represents the 8885 highest bit of the register number. */ 8886 uint8_t top_bit = (value >> 4) & 1; 8887 uint8_t tmp = (value << 1) & 0x1e; 8888 uint8_t res = tmp | top_bit; 8889 func (stream, dis_style_register, "s%u", res); 8890 } 8891 break; 8892 8893 default: 8894 abort (); 8895 } 8896 } 8897 break; 8898 8899 case 'p': 8900 { 8901 uint8_t proc_number = (given >> 8) & 0x7; 8902 func (stream, dis_style_register, "p%u", proc_number); 8903 break; 8904 } 8905 8906 case 'a': 8907 { 8908 uint8_t a_offset = 28; 8909 if (given & (1 << a_offset)) 8910 func (stream, dis_style_mnemonic, "a"); 8911 break; 8912 } 8913 default: 8914 abort (); 8915 } 8916 } 8917 else 8918 { 8919 if (*c == '@') 8920 base_style = dis_style_comment_start; 8921 if (*c == '\t') 8922 base_style = dis_style_text; 8923 8924 func (stream, base_style, "%c", *c); 8925 } 8926 } 8927 8928 if (is_unpredictable) 8929 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 8930 8931 return true; 8932 } 8933 } 8934 return false; 8935 } 8936 else 8937 return false; 8938 } 8939 8940 8941 /* Print one neon instruction on INFO->STREAM. 8942 Return TRUE if the instuction matched, FALSE if this is not a 8943 recognised neon instruction. */ 8944 8945 static bool 8946 print_insn_neon (struct disassemble_info *info, long given, bool thumb) 8947 { 8948 const struct opcode32 *insn; 8949 void *stream = info->stream; 8950 fprintf_styled_ftype func = info->fprintf_styled_func; 8951 enum disassembler_style base_style = dis_style_mnemonic; 8952 enum disassembler_style old_base_style = base_style; 8953 8954 if (thumb) 8955 { 8956 if ((given & 0xef000000) == 0xef000000) 8957 { 8958 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 8959 unsigned long bit28 = given & (1 << 28); 8960 8961 given &= 0x00ffffff; 8962 if (bit28) 8963 given |= 0xf3000000; 8964 else 8965 given |= 0xf2000000; 8966 } 8967 else if ((given & 0xff000000) == 0xf9000000) 8968 given ^= 0xf9000000 ^ 0xf4000000; 8969 /* BFloat16 neon instructions without special top byte handling. */ 8970 else if ((given & 0xff000000) == 0xfe000000 8971 || (given & 0xff000000) == 0xfc000000) 8972 ; 8973 /* vdup is also a valid neon instruction. */ 8974 else if ((given & 0xff900f5f) != 0xee800b10) 8975 return false; 8976 } 8977 8978 for (insn = neon_opcodes; insn->assembler; insn++) 8979 { 8980 unsigned long cond_mask = insn->mask; 8981 unsigned long cond_value = insn->value; 8982 int cond; 8983 8984 if (thumb) 8985 { 8986 if ((cond_mask & 0xf0000000) == 0) { 8987 /* For the entries in neon_opcodes, an opcode mask/value with 8988 the high 4 bits equal to 0 indicates a conditional 8989 instruction. For thumb however, we need to include those 8990 bits in the instruction matching. */ 8991 cond_mask |= 0xf0000000; 8992 /* Furthermore, the thumb encoding of a conditional instruction 8993 will have the high 4 bits equal to 0xe. */ 8994 cond_value |= 0xe0000000; 8995 } 8996 if (ifthen_state) 8997 cond = IFTHEN_COND; 8998 else 8999 cond = COND_UNCOND; 9000 } 9001 else 9002 { 9003 if ((given & 0xf0000000) == 0xf0000000) 9004 { 9005 /* If the instruction is unconditional, update the mask to only 9006 match against unconditional opcode values. */ 9007 cond_mask |= 0xf0000000; 9008 cond = COND_UNCOND; 9009 } 9010 else 9011 { 9012 cond = (given >> 28) & 0xf; 9013 if (cond == 0xe) 9014 cond = COND_UNCOND; 9015 } 9016 } 9017 9018 if ((given & cond_mask) == cond_value) 9019 { 9020 signed long value_in_comment = 0; 9021 bool is_unpredictable = false; 9022 const char *c; 9023 9024 for (c = insn->assembler; *c; c++) 9025 { 9026 if (*c == '%') 9027 { 9028 switch (*++c) 9029 { 9030 case '{': 9031 ++c; 9032 if (*c == '\0') 9033 abort (); 9034 old_base_style = base_style; 9035 base_style = decode_base_style (*c); 9036 ++c; 9037 if (*c != ':') 9038 abort (); 9039 break; 9040 9041 case '}': 9042 base_style = old_base_style; 9043 break; 9044 9045 case '%': 9046 func (stream, base_style, "%%"); 9047 break; 9048 9049 case 'u': 9050 if (thumb && ifthen_state) 9051 is_unpredictable = true; 9052 9053 /* Fall through. */ 9054 case 'c': 9055 func (stream, dis_style_mnemonic, "%s", 9056 arm_conditional[cond]); 9057 break; 9058 9059 case 'A': 9060 { 9061 static const unsigned char enc[16] = 9062 { 9063 0x4, 0x14, /* st4 0,1 */ 9064 0x4, /* st1 2 */ 9065 0x4, /* st2 3 */ 9066 0x3, /* st3 4 */ 9067 0x13, /* st3 5 */ 9068 0x3, /* st1 6 */ 9069 0x1, /* st1 7 */ 9070 0x2, /* st2 8 */ 9071 0x12, /* st2 9 */ 9072 0x2, /* st1 10 */ 9073 0, 0, 0, 0, 0 9074 }; 9075 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9076 int rn = ((given >> 16) & 0xf); 9077 int rm = ((given >> 0) & 0xf); 9078 int align = ((given >> 4) & 0x3); 9079 int type = ((given >> 8) & 0xf); 9080 int n = enc[type] & 0xf; 9081 int stride = (enc[type] >> 4) + 1; 9082 int ix; 9083 9084 func (stream, dis_style_text, "{"); 9085 if (stride > 1) 9086 for (ix = 0; ix != n; ix++) 9087 { 9088 if (ix > 0) 9089 func (stream, dis_style_text, ","); 9090 func (stream, dis_style_register, "d%d", 9091 rd + ix * stride); 9092 } 9093 else if (n == 1) 9094 func (stream, dis_style_register, "d%d", rd); 9095 else 9096 { 9097 func (stream, dis_style_register, "d%d", rd); 9098 func (stream, dis_style_text, "-"); 9099 func (stream, dis_style_register, "d%d", 9100 rd + n - 1); 9101 } 9102 func (stream, dis_style_text, "}, ["); 9103 func (stream, dis_style_register, "%s", 9104 arm_regnames[rn]); 9105 if (align) 9106 { 9107 func (stream, dis_style_text, " :"); 9108 func (stream, dis_style_immediate, "%d", 9109 32 << align); 9110 } 9111 func (stream, dis_style_text, "]"); 9112 if (rm == 0xd) 9113 func (stream, dis_style_text, "!"); 9114 else if (rm != 0xf) 9115 { 9116 func (stream, dis_style_text, ", "); 9117 func (stream, dis_style_register, "%s", 9118 arm_regnames[rm]); 9119 } 9120 } 9121 break; 9122 9123 case 'B': 9124 { 9125 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9126 int rn = ((given >> 16) & 0xf); 9127 int rm = ((given >> 0) & 0xf); 9128 int idx_align = ((given >> 4) & 0xf); 9129 int align = 0; 9130 int size = ((given >> 10) & 0x3); 9131 int idx = idx_align >> (size + 1); 9132 int length = ((given >> 8) & 3) + 1; 9133 int stride = 1; 9134 int i; 9135 9136 if (length > 1 && size > 0) 9137 stride = (idx_align & (1 << size)) ? 2 : 1; 9138 9139 switch (length) 9140 { 9141 case 1: 9142 { 9143 int amask = (1 << size) - 1; 9144 if ((idx_align & (1 << size)) != 0) 9145 return false; 9146 if (size > 0) 9147 { 9148 if ((idx_align & amask) == amask) 9149 align = 8 << size; 9150 else if ((idx_align & amask) != 0) 9151 return false; 9152 } 9153 } 9154 break; 9155 9156 case 2: 9157 if (size == 2 && (idx_align & 2) != 0) 9158 return false; 9159 align = (idx_align & 1) ? 16 << size : 0; 9160 break; 9161 9162 case 3: 9163 if ((size == 2 && (idx_align & 3) != 0) 9164 || (idx_align & 1) != 0) 9165 return false; 9166 break; 9167 9168 case 4: 9169 if (size == 2) 9170 { 9171 if ((idx_align & 3) == 3) 9172 return false; 9173 align = (idx_align & 3) * 64; 9174 } 9175 else 9176 align = (idx_align & 1) ? 32 << size : 0; 9177 break; 9178 9179 default: 9180 abort (); 9181 } 9182 9183 func (stream, dis_style_text, "{"); 9184 for (i = 0; i < length; i++) 9185 { 9186 if (i > 0) 9187 func (stream, dis_style_text, ","); 9188 func (stream, dis_style_register, "d%d[%d]", 9189 rd + i * stride, idx); 9190 } 9191 func (stream, dis_style_text, "}, ["); 9192 func (stream, dis_style_register, "%s", 9193 arm_regnames[rn]); 9194 if (align) 9195 { 9196 func (stream, dis_style_text, " :"); 9197 func (stream, dis_style_immediate, "%d", align); 9198 } 9199 func (stream, dis_style_text, "]"); 9200 if (rm == 0xd) 9201 func (stream, dis_style_text, "!"); 9202 else if (rm != 0xf) 9203 { 9204 func (stream, dis_style_text, ", "); 9205 func (stream, dis_style_register, "%s", 9206 arm_regnames[rm]); 9207 } 9208 } 9209 break; 9210 9211 case 'C': 9212 { 9213 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9214 int rn = ((given >> 16) & 0xf); 9215 int rm = ((given >> 0) & 0xf); 9216 int align = ((given >> 4) & 0x1); 9217 int size = ((given >> 6) & 0x3); 9218 int type = ((given >> 8) & 0x3); 9219 int n = type + 1; 9220 int stride = ((given >> 5) & 0x1); 9221 int ix; 9222 9223 if (stride && (n == 1)) 9224 n++; 9225 else 9226 stride++; 9227 9228 func (stream, dis_style_text, "{"); 9229 if (stride > 1) 9230 for (ix = 0; ix != n; ix++) 9231 { 9232 if (ix > 0) 9233 func (stream, dis_style_text, ","); 9234 func (stream, dis_style_register, "d%d[]", 9235 rd + ix * stride); 9236 } 9237 else if (n == 1) 9238 func (stream, dis_style_register, "d%d[]", rd); 9239 else 9240 { 9241 func (stream, dis_style_register, "d%d[]", rd); 9242 func (stream, dis_style_text, "-"); 9243 func (stream, dis_style_register, "d%d[]", 9244 rd + n - 1); 9245 } 9246 func (stream, dis_style_text, "}, ["); 9247 func (stream, dis_style_register, "%s", 9248 arm_regnames[rn]); 9249 if (align) 9250 { 9251 align = (8 * (type + 1)) << size; 9252 if (type == 3) 9253 align = (size > 1) ? align >> 1 : align; 9254 if (type == 2 || (type == 0 && !size)) 9255 func (stream, dis_style_text, 9256 " :<bad align %d>", align); 9257 else 9258 { 9259 func (stream, dis_style_text, " :"); 9260 func (stream, dis_style_immediate, 9261 "%d", align); 9262 } 9263 } 9264 func (stream, dis_style_text, "]"); 9265 if (rm == 0xd) 9266 func (stream, dis_style_text, "!"); 9267 else if (rm != 0xf) 9268 { 9269 func (stream, dis_style_text, ", "); 9270 func (stream, dis_style_register, "%s", 9271 arm_regnames[rm]); 9272 } 9273 } 9274 break; 9275 9276 case 'D': 9277 { 9278 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 9279 int size = (given >> 20) & 3; 9280 int reg = raw_reg & ((4 << size) - 1); 9281 int ix = raw_reg >> size >> 2; 9282 9283 func (stream, dis_style_register, "d%d[%d]", reg, ix); 9284 } 9285 break; 9286 9287 case 'E': 9288 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 9289 { 9290 int bits = 0; 9291 int cmode = (given >> 8) & 0xf; 9292 int op = (given >> 5) & 0x1; 9293 unsigned long value = 0, hival = 0; 9294 unsigned shift; 9295 int size = 0; 9296 int isfloat = 0; 9297 9298 bits |= ((given >> 24) & 1) << 7; 9299 bits |= ((given >> 16) & 7) << 4; 9300 bits |= ((given >> 0) & 15) << 0; 9301 9302 if (cmode < 8) 9303 { 9304 shift = (cmode >> 1) & 3; 9305 value = (unsigned long) bits << (8 * shift); 9306 size = 32; 9307 } 9308 else if (cmode < 12) 9309 { 9310 shift = (cmode >> 1) & 1; 9311 value = (unsigned long) bits << (8 * shift); 9312 size = 16; 9313 } 9314 else if (cmode < 14) 9315 { 9316 shift = (cmode & 1) + 1; 9317 value = (unsigned long) bits << (8 * shift); 9318 value |= (1ul << (8 * shift)) - 1; 9319 size = 32; 9320 } 9321 else if (cmode == 14) 9322 { 9323 if (op) 9324 { 9325 /* Bit replication into bytes. */ 9326 int ix; 9327 unsigned long mask; 9328 9329 value = 0; 9330 hival = 0; 9331 for (ix = 7; ix >= 0; ix--) 9332 { 9333 mask = ((bits >> ix) & 1) ? 0xff : 0; 9334 if (ix <= 3) 9335 value = (value << 8) | mask; 9336 else 9337 hival = (hival << 8) | mask; 9338 } 9339 size = 64; 9340 } 9341 else 9342 { 9343 /* Byte replication. */ 9344 value = (unsigned long) bits; 9345 size = 8; 9346 } 9347 } 9348 else if (!op) 9349 { 9350 /* Floating point encoding. */ 9351 int tmp; 9352 9353 value = (unsigned long) (bits & 0x7f) << 19; 9354 value |= (unsigned long) (bits & 0x80) << 24; 9355 tmp = bits & 0x40 ? 0x3c : 0x40; 9356 value |= (unsigned long) tmp << 24; 9357 size = 32; 9358 isfloat = 1; 9359 } 9360 else 9361 { 9362 func (stream, dis_style_text, 9363 "<illegal constant %.8x:%x:%x>", 9364 bits, cmode, op); 9365 size = 32; 9366 break; 9367 } 9368 switch (size) 9369 { 9370 case 8: 9371 func (stream, dis_style_immediate, "#%ld", value); 9372 func (stream, dis_style_comment_start, 9373 "\t@ 0x%.2lx", value); 9374 break; 9375 9376 case 16: 9377 func (stream, dis_style_immediate, "#%ld", value); 9378 func (stream, dis_style_comment_start, 9379 "\t@ 0x%.4lx", value); 9380 break; 9381 9382 case 32: 9383 if (isfloat) 9384 { 9385 unsigned char valbytes[4]; 9386 double fvalue; 9387 9388 /* Do this a byte at a time so we don't have to 9389 worry about the host's endianness. */ 9390 valbytes[0] = value & 0xff; 9391 valbytes[1] = (value >> 8) & 0xff; 9392 valbytes[2] = (value >> 16) & 0xff; 9393 valbytes[3] = (value >> 24) & 0xff; 9394 9395 floatformat_to_double 9396 (& floatformat_ieee_single_little, valbytes, 9397 & fvalue); 9398 9399 func (stream, dis_style_immediate, 9400 "#%.7g", fvalue); 9401 func (stream, dis_style_comment_start, 9402 "\t@ 0x%.8lx", value); 9403 } 9404 else 9405 { 9406 func (stream, dis_style_immediate, "#%ld", 9407 (long) (((value & 0x80000000L) != 0) 9408 ? value | ~0xffffffffL : value)); 9409 func (stream, dis_style_comment_start, 9410 "\t@ 0x%.8lx", value); 9411 } 9412 break; 9413 9414 case 64: 9415 func (stream, dis_style_immediate, 9416 "#0x%.8lx%.8lx", hival, value); 9417 break; 9418 9419 default: 9420 abort (); 9421 } 9422 } 9423 break; 9424 9425 case 'F': 9426 { 9427 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 9428 int num = (given >> 8) & 0x3; 9429 9430 func (stream, dis_style_text, "{"); 9431 if (!num) 9432 func (stream, dis_style_register, "d%d", regno); 9433 else if (num + regno >= 32) 9434 { 9435 func (stream, dis_style_register, "d%d", regno); 9436 func (stream, dis_style_text, "-<overflow reg d%d", 9437 regno + num); 9438 } 9439 else 9440 { 9441 func (stream, dis_style_register, "d%d", regno); 9442 func (stream, dis_style_text, "-"); 9443 func (stream, dis_style_register, "d%d", 9444 regno + num); 9445 } 9446 func (stream, dis_style_text, "}"); 9447 } 9448 break; 9449 9450 9451 case '0': case '1': case '2': case '3': case '4': 9452 case '5': case '6': case '7': case '8': case '9': 9453 { 9454 int width; 9455 unsigned long value; 9456 9457 c = arm_decode_bitfield (c, given, &value, &width); 9458 9459 switch (*c) 9460 { 9461 case 'r': 9462 func (stream, dis_style_register, "%s", 9463 arm_regnames[value]); 9464 break; 9465 case 'd': 9466 func (stream, base_style, "%ld", value); 9467 value_in_comment = value; 9468 break; 9469 case 'e': 9470 func (stream, dis_style_immediate, "%ld", 9471 (1ul << width) - value); 9472 break; 9473 9474 case 'S': 9475 case 'T': 9476 case 'U': 9477 /* Various width encodings. */ 9478 { 9479 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 9480 int limit; 9481 unsigned low, high; 9482 9483 c++; 9484 if (*c >= '0' && *c <= '9') 9485 limit = *c - '0'; 9486 else if (*c >= 'a' && *c <= 'f') 9487 limit = *c - 'a' + 10; 9488 else 9489 abort (); 9490 low = limit >> 2; 9491 high = limit & 3; 9492 9493 if (value < low || value > high) 9494 func (stream, dis_style_text, 9495 "<illegal width %d>", base << value); 9496 else 9497 func (stream, base_style, "%d", 9498 base << value); 9499 } 9500 break; 9501 case 'R': 9502 if (given & (1 << 6)) 9503 goto Q; 9504 /* FALLTHROUGH */ 9505 case 'D': 9506 func (stream, dis_style_register, "d%ld", value); 9507 break; 9508 case 'Q': 9509 Q: 9510 if (value & 1) 9511 func (stream, dis_style_text, 9512 "<illegal reg q%ld.5>", value >> 1); 9513 else 9514 func (stream, dis_style_register, 9515 "q%ld", value >> 1); 9516 break; 9517 9518 case '`': 9519 c++; 9520 if (value == 0) 9521 func (stream, dis_style_text, "%c", *c); 9522 break; 9523 case '\'': 9524 c++; 9525 if (value == ((1ul << width) - 1)) 9526 func (stream, dis_style_text, "%c", *c); 9527 break; 9528 case '?': 9529 func (stream, dis_style_mnemonic, "%c", 9530 c[(1 << width) - (int) value]); 9531 c += 1 << width; 9532 break; 9533 default: 9534 abort (); 9535 } 9536 } 9537 break; 9538 9539 default: 9540 abort (); 9541 } 9542 } 9543 else 9544 { 9545 if (*c == '@') 9546 base_style = dis_style_comment_start; 9547 9548 if (*c == '\t') 9549 base_style = dis_style_text; 9550 9551 func (stream, base_style, "%c", *c); 9552 9553 } 9554 } 9555 9556 if (value_in_comment > 32 || value_in_comment < -16) 9557 func (stream, dis_style_comment_start, "\t@ 0x%lx", 9558 value_in_comment); 9559 9560 if (is_unpredictable) 9561 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 9562 9563 return true; 9564 } 9565 } 9566 return false; 9567 } 9568 9569 /* Print one mve instruction on INFO->STREAM. 9570 Return TRUE if the instuction matched, FALSE if this is not a 9571 recognised mve instruction. */ 9572 9573 static bool 9574 print_insn_mve (struct disassemble_info *info, long given) 9575 { 9576 const struct mopcode32 *insn; 9577 void *stream = info->stream; 9578 fprintf_styled_ftype func = info->fprintf_styled_func; 9579 enum disassembler_style base_style = dis_style_mnemonic; 9580 enum disassembler_style old_base_style = base_style; 9581 9582 for (insn = mve_opcodes; insn->assembler; insn++) 9583 { 9584 if (((given & insn->mask) == insn->value) 9585 && !is_mve_encoding_conflict (given, insn->mve_op)) 9586 { 9587 signed long value_in_comment = 0; 9588 bool is_unpredictable = false; 9589 bool is_undefined = false; 9590 const char *c; 9591 enum mve_unpredictable unpredictable_cond = UNPRED_NONE; 9592 enum mve_undefined undefined_cond = UNDEF_NONE; 9593 9594 /* Most vector mve instruction are illegal in a it block. 9595 There are a few exceptions; check for them. */ 9596 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op)) 9597 { 9598 is_unpredictable = true; 9599 unpredictable_cond = UNPRED_IT_BLOCK; 9600 } 9601 else if (is_mve_unpredictable (given, insn->mve_op, 9602 &unpredictable_cond)) 9603 is_unpredictable = true; 9604 9605 if (is_mve_undefined (given, insn->mve_op, &undefined_cond)) 9606 is_undefined = true; 9607 9608 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV, 9609 i.e "VMOV Qd, Qm". */ 9610 if ((insn->mve_op == MVE_VORR_REG) 9611 && (arm_decode_field (given, 1, 3) 9612 == arm_decode_field (given, 17, 19))) 9613 continue; 9614 9615 for (c = insn->assembler; *c; c++) 9616 { 9617 if (*c == '%') 9618 { 9619 switch (*++c) 9620 { 9621 case '{': 9622 ++c; 9623 if (*c == '\0') 9624 abort (); 9625 old_base_style = base_style; 9626 base_style = decode_base_style (*c); 9627 ++c; 9628 if (*c != ':') 9629 abort (); 9630 break; 9631 9632 case '}': 9633 base_style = old_base_style; 9634 break; 9635 9636 case '%': 9637 func (stream, base_style, "%%"); 9638 break; 9639 9640 case 'a': 9641 /* Don't print anything for '+' as it is implied. */ 9642 if (arm_decode_field (given, 23, 23) == 0) 9643 func (stream, dis_style_immediate, "-"); 9644 break; 9645 9646 case 'c': 9647 if (ifthen_state) 9648 func (stream, dis_style_mnemonic, "%s", 9649 arm_conditional[IFTHEN_COND]); 9650 break; 9651 9652 case 'd': 9653 print_mve_vld_str_addr (info, given, insn->mve_op); 9654 break; 9655 9656 case 'i': 9657 { 9658 long mve_mask = mve_extract_pred_mask (given); 9659 func (stream, dis_style_mnemonic, "%s", 9660 mve_predicatenames[mve_mask]); 9661 } 9662 break; 9663 9664 case 'j': 9665 { 9666 unsigned int imm5 = 0; 9667 imm5 |= arm_decode_field (given, 6, 7); 9668 imm5 |= (arm_decode_field (given, 12, 14) << 2); 9669 func (stream, dis_style_immediate, "#%u", 9670 (imm5 == 0) ? 32 : imm5); 9671 } 9672 break; 9673 9674 case 'k': 9675 func (stream, dis_style_immediate, "#%u", 9676 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); 9677 break; 9678 9679 case 'n': 9680 print_vec_condition (info, given, insn->mve_op); 9681 break; 9682 9683 case 'o': 9684 if (arm_decode_field (given, 0, 0) == 1) 9685 { 9686 unsigned long size 9687 = arm_decode_field (given, 4, 4) 9688 | (arm_decode_field (given, 6, 6) << 1); 9689 9690 func (stream, dis_style_text, ", "); 9691 func (stream, dis_style_sub_mnemonic, "uxtw "); 9692 func (stream, dis_style_immediate, "#%lu", size); 9693 } 9694 break; 9695 9696 case 'm': 9697 print_mve_rounding_mode (info, given, insn->mve_op); 9698 break; 9699 9700 case 's': 9701 print_mve_vcvt_size (info, given, insn->mve_op); 9702 break; 9703 9704 case 'u': 9705 { 9706 unsigned long op1 = arm_decode_field (given, 21, 22); 9707 9708 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP)) 9709 { 9710 /* Check for signed. */ 9711 if (arm_decode_field (given, 23, 23) == 0) 9712 { 9713 /* We don't print 's' for S32. */ 9714 if ((arm_decode_field (given, 5, 6) == 0) 9715 && ((op1 == 0) || (op1 == 1))) 9716 ; 9717 else 9718 func (stream, dis_style_mnemonic, "s"); 9719 } 9720 else 9721 func (stream, dis_style_mnemonic, "u"); 9722 } 9723 else 9724 { 9725 if (arm_decode_field (given, 28, 28) == 0) 9726 func (stream, dis_style_mnemonic, "s"); 9727 else 9728 func (stream, dis_style_mnemonic, "u"); 9729 } 9730 } 9731 break; 9732 9733 case 'v': 9734 print_instruction_predicate (info); 9735 break; 9736 9737 case 'w': 9738 if (arm_decode_field (given, 21, 21) == 1) 9739 func (stream, dis_style_text, "!"); 9740 break; 9741 9742 case 'B': 9743 print_mve_register_blocks (info, given, insn->mve_op); 9744 break; 9745 9746 case 'E': 9747 /* SIMD encoded constant for mov, mvn, vorr, vbic. */ 9748 9749 print_simd_imm8 (info, given, 28, insn); 9750 break; 9751 9752 case 'N': 9753 print_mve_vmov_index (info, given); 9754 break; 9755 9756 case 'T': 9757 if (arm_decode_field (given, 12, 12) == 0) 9758 func (stream, dis_style_mnemonic, "b"); 9759 else 9760 func (stream, dis_style_mnemonic, "t"); 9761 break; 9762 9763 case 'X': 9764 if (arm_decode_field (given, 12, 12) == 1) 9765 func (stream, dis_style_mnemonic, "x"); 9766 break; 9767 9768 case '0': case '1': case '2': case '3': case '4': 9769 case '5': case '6': case '7': case '8': case '9': 9770 { 9771 int width; 9772 unsigned long value; 9773 9774 c = arm_decode_bitfield (c, given, &value, &width); 9775 9776 switch (*c) 9777 { 9778 case 'Z': 9779 if (value == 13) 9780 is_unpredictable = true; 9781 else if (value == 15) 9782 func (stream, dis_style_register, "zr"); 9783 else 9784 func (stream, dis_style_register, "%s", 9785 arm_regnames[value]); 9786 break; 9787 9788 case 'c': 9789 func (stream, dis_style_sub_mnemonic, "%s", 9790 arm_conditional[value]); 9791 break; 9792 9793 case 'C': 9794 value ^= 1; 9795 func (stream, dis_style_sub_mnemonic, "%s", 9796 arm_conditional[value]); 9797 break; 9798 9799 case 'S': 9800 if (value == 13 || value == 15) 9801 is_unpredictable = true; 9802 else 9803 func (stream, dis_style_register, "%s", 9804 arm_regnames[value]); 9805 break; 9806 9807 case 's': 9808 print_mve_size (info, 9809 value, 9810 insn->mve_op); 9811 break; 9812 case 'I': 9813 if (value == 1) 9814 func (stream, dis_style_mnemonic, "i"); 9815 break; 9816 case 'A': 9817 if (value == 1) 9818 func (stream, dis_style_mnemonic, "a"); 9819 break; 9820 case 'h': 9821 { 9822 unsigned int odd_reg = (value << 1) | 1; 9823 func (stream, dis_style_register, "%s", 9824 arm_regnames[odd_reg]); 9825 } 9826 break; 9827 case 'i': 9828 { 9829 unsigned long imm 9830 = arm_decode_field (given, 0, 6); 9831 unsigned long mod_imm = imm; 9832 9833 switch (insn->mve_op) 9834 { 9835 case MVE_VLDRW_GATHER_T5: 9836 case MVE_VSTRW_SCATTER_T5: 9837 mod_imm = mod_imm << 2; 9838 break; 9839 case MVE_VSTRD_SCATTER_T6: 9840 case MVE_VLDRD_GATHER_T6: 9841 mod_imm = mod_imm << 3; 9842 break; 9843 9844 default: 9845 break; 9846 } 9847 9848 func (stream, dis_style_immediate, "%lu", 9849 mod_imm); 9850 } 9851 break; 9852 case 'k': 9853 func (stream, dis_style_immediate, "%lu", 9854 64 - value); 9855 break; 9856 case 'l': 9857 { 9858 unsigned int even_reg = value << 1; 9859 func (stream, dis_style_register, "%s", 9860 arm_regnames[even_reg]); 9861 } 9862 break; 9863 case 'u': 9864 switch (value) 9865 { 9866 case 0: 9867 func (stream, dis_style_immediate, "1"); 9868 break; 9869 case 1: 9870 func (stream, dis_style_immediate, "2"); 9871 break; 9872 case 2: 9873 func (stream, dis_style_immediate, "4"); 9874 break; 9875 case 3: 9876 func (stream, dis_style_immediate, "8"); 9877 break; 9878 default: 9879 break; 9880 } 9881 break; 9882 case 'o': 9883 print_mve_rotate (info, value, width); 9884 break; 9885 case 'r': 9886 func (stream, dis_style_register, "%s", 9887 arm_regnames[value]); 9888 break; 9889 case 'd': 9890 if (mve_shift_insn_p (insn->mve_op)) 9891 print_mve_shift_n (info, given, insn->mve_op); 9892 else if (insn->mve_op == MVE_VSHLL_T2) 9893 func (stream, dis_style_immediate, "%s", 9894 mve_vec_sizename[value]); 9895 else 9896 { 9897 if (insn->mve_op == MVE_VSHLC && value == 0) 9898 value = 32; 9899 func (stream, base_style, "%ld", value); 9900 value_in_comment = value; 9901 } 9902 break; 9903 case 'F': 9904 func (stream, dis_style_register, "s%ld", value); 9905 break; 9906 case 'Q': 9907 if (value & 0x8) 9908 func (stream, dis_style_text, 9909 "<illegal reg q%ld.5>", value); 9910 else 9911 func (stream, dis_style_register, "q%ld", value); 9912 break; 9913 case 'x': 9914 func (stream, dis_style_immediate, 9915 "0x%08lx", value); 9916 break; 9917 default: 9918 abort (); 9919 } 9920 break; 9921 default: 9922 abort (); 9923 } 9924 } 9925 } 9926 else 9927 { 9928 if (*c == '@') 9929 base_style = dis_style_comment_start; 9930 9931 if (*c == '\t') 9932 base_style = dis_style_text; 9933 9934 func (stream, base_style, "%c", *c); 9935 } 9936 } 9937 9938 if (value_in_comment > 32 || value_in_comment < -16) 9939 func (stream, dis_style_comment_start, "\t@ 0x%lx", 9940 value_in_comment); 9941 9942 if (is_unpredictable) 9943 print_mve_unpredictable (info, unpredictable_cond); 9944 9945 if (is_undefined) 9946 print_mve_undefined (info, undefined_cond); 9947 9948 if (!vpt_block_state.in_vpt_block 9949 && !ifthen_state 9950 && is_vpt_instruction (given)) 9951 mark_inside_vpt_block (given); 9952 else if (vpt_block_state.in_vpt_block) 9953 update_vpt_block_state (); 9954 9955 return true; 9956 } 9957 } 9958 return false; 9959 } 9960 9961 9962 /* Return the name of a v7A special register. */ 9963 9964 static const char * 9965 banked_regname (unsigned reg) 9966 { 9967 switch (reg) 9968 { 9969 case 15: return "CPSR"; 9970 case 32: return "R8_usr"; 9971 case 33: return "R9_usr"; 9972 case 34: return "R10_usr"; 9973 case 35: return "R11_usr"; 9974 case 36: return "R12_usr"; 9975 case 37: return "SP_usr"; 9976 case 38: return "LR_usr"; 9977 case 40: return "R8_fiq"; 9978 case 41: return "R9_fiq"; 9979 case 42: return "R10_fiq"; 9980 case 43: return "R11_fiq"; 9981 case 44: return "R12_fiq"; 9982 case 45: return "SP_fiq"; 9983 case 46: return "LR_fiq"; 9984 case 48: return "LR_irq"; 9985 case 49: return "SP_irq"; 9986 case 50: return "LR_svc"; 9987 case 51: return "SP_svc"; 9988 case 52: return "LR_abt"; 9989 case 53: return "SP_abt"; 9990 case 54: return "LR_und"; 9991 case 55: return "SP_und"; 9992 case 60: return "LR_mon"; 9993 case 61: return "SP_mon"; 9994 case 62: return "ELR_hyp"; 9995 case 63: return "SP_hyp"; 9996 case 79: return "SPSR"; 9997 case 110: return "SPSR_fiq"; 9998 case 112: return "SPSR_irq"; 9999 case 114: return "SPSR_svc"; 10000 case 116: return "SPSR_abt"; 10001 case 118: return "SPSR_und"; 10002 case 124: return "SPSR_mon"; 10003 case 126: return "SPSR_hyp"; 10004 default: return NULL; 10005 } 10006 } 10007 10008 /* Return the name of the DMB/DSB option. */ 10009 static const char * 10010 data_barrier_option (unsigned option) 10011 { 10012 switch (option & 0xf) 10013 { 10014 case 0xf: return "sy"; 10015 case 0xe: return "st"; 10016 case 0xd: return "ld"; 10017 case 0xb: return "ish"; 10018 case 0xa: return "ishst"; 10019 case 0x9: return "ishld"; 10020 case 0x7: return "un"; 10021 case 0x6: return "unst"; 10022 case 0x5: return "nshld"; 10023 case 0x3: return "osh"; 10024 case 0x2: return "oshst"; 10025 case 0x1: return "oshld"; 10026 default: return NULL; 10027 } 10028 } 10029 10030 /* Print one ARM instruction from PC on INFO->STREAM. */ 10031 10032 static void 10033 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 10034 { 10035 const struct opcode32 *insn; 10036 void *stream = info->stream; 10037 fprintf_styled_ftype func = info->fprintf_styled_func; 10038 struct arm_private_data *private_data = info->private_data; 10039 enum disassembler_style base_style = dis_style_mnemonic; 10040 enum disassembler_style old_base_style = base_style; 10041 10042 if (print_insn_coprocessor (pc, info, given, false)) 10043 return; 10044 10045 if (print_insn_neon (info, given, false)) 10046 return; 10047 10048 if (print_insn_generic_coprocessor (pc, info, given, false)) 10049 return; 10050 10051 for (insn = arm_opcodes; insn->assembler; insn++) 10052 { 10053 if ((given & insn->mask) != insn->value) 10054 continue; 10055 10056 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 10057 continue; 10058 10059 /* Special case: an instruction with all bits set in the condition field 10060 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 10061 or by the catchall at the end of the table. */ 10062 if ((given & 0xF0000000) != 0xF0000000 10063 || (insn->mask & 0xF0000000) == 0xF0000000 10064 || (insn->mask == 0 && insn->value == 0)) 10065 { 10066 unsigned long u_reg = 16; 10067 unsigned long U_reg = 16; 10068 bool is_unpredictable = false; 10069 signed long value_in_comment = 0; 10070 const char *c; 10071 10072 for (c = insn->assembler; *c; c++) 10073 { 10074 if (*c == '%') 10075 { 10076 bool allow_unpredictable = false; 10077 10078 switch (*++c) 10079 { 10080 case '{': 10081 ++c; 10082 if (*c == '\0') 10083 abort (); 10084 old_base_style = base_style; 10085 base_style = decode_base_style (*c); 10086 ++c; 10087 if (*c != ':') 10088 abort (); 10089 break; 10090 10091 case '}': 10092 base_style = old_base_style; 10093 break; 10094 10095 case '%': 10096 func (stream, base_style, "%%"); 10097 break; 10098 10099 case 'a': 10100 value_in_comment = print_arm_address (pc, info, given); 10101 break; 10102 10103 case 'P': 10104 /* Set P address bit and use normal address 10105 printing routine. */ 10106 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 10107 break; 10108 10109 case 'T': 10110 /* Armv4 does not have a BX instruction, however, when 10111 assembled with the --fix-v4bx option GAS will accept 10112 and assemble a BX instruction when assembling for 10113 Armv4. When disassembling we also disassemble it as a 10114 BX instruction, but do make the user aware that this 10115 instruction is only supported on HW from Armv4T 10116 onwards. */ 10117 if (info->mach == bfd_mach_arm_4) 10118 func (stream, dis_style_text, "\t@ from Armv4T onwards"); 10119 break; 10120 10121 case 'S': 10122 allow_unpredictable = true; 10123 /* Fall through. */ 10124 case 's': 10125 if ((given & 0x004f0000) == 0x004f0000) 10126 { 10127 /* PC relative with immediate offset. */ 10128 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 10129 10130 if (PRE_BIT_SET) 10131 { 10132 /* Elide positive zero offset. */ 10133 if (offset || NEGATIVE_BIT_SET) 10134 { 10135 func (stream, dis_style_text, "["); 10136 func (stream, dis_style_register, "pc"); 10137 func (stream, dis_style_text, ", "); 10138 func (stream, dis_style_immediate, "#%s%d", 10139 (NEGATIVE_BIT_SET ? "-" : ""), 10140 (int) offset); 10141 func (stream, dis_style_text, "]"); 10142 } 10143 else 10144 { 10145 func (stream, dis_style_text, "["); 10146 func (stream, dis_style_register, "pc"); 10147 func (stream, dis_style_text, "]"); 10148 } 10149 if (NEGATIVE_BIT_SET) 10150 offset = -offset; 10151 func (stream, dis_style_comment_start, "\t@ "); 10152 info->print_address_func (offset + pc + 8, info); 10153 } 10154 else 10155 { 10156 /* Always show the offset. */ 10157 func (stream, dis_style_text, "["); 10158 func (stream, dis_style_register, "pc"); 10159 func (stream, dis_style_text, "], "); 10160 func (stream, dis_style_immediate, "#%s%d", 10161 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10162 if (! allow_unpredictable) 10163 is_unpredictable = true; 10164 } 10165 } 10166 else 10167 { 10168 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 10169 10170 func (stream, dis_style_text, "["); 10171 func (stream, dis_style_register, "%s", 10172 arm_regnames[(given >> 16) & 0xf]); 10173 10174 if (PRE_BIT_SET) 10175 { 10176 if (IMMEDIATE_BIT_SET) 10177 { 10178 /* Elide offset for non-writeback 10179 positive zero. */ 10180 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 10181 || offset) 10182 { 10183 func (stream, dis_style_text, ", "); 10184 func (stream, dis_style_immediate, 10185 "#%s%d", 10186 (NEGATIVE_BIT_SET ? "-" : ""), 10187 offset); 10188 } 10189 10190 if (NEGATIVE_BIT_SET) 10191 offset = -offset; 10192 10193 value_in_comment = offset; 10194 } 10195 else 10196 { 10197 /* Register Offset or Register Pre-Indexed. */ 10198 func (stream, dis_style_text, ", %s", 10199 NEGATIVE_BIT_SET ? "-" : ""); 10200 func (stream, dis_style_register, "%s", 10201 arm_regnames[given & 0xf]); 10202 10203 /* Writing back to the register that is the source/ 10204 destination of the load/store is unpredictable. */ 10205 if (! allow_unpredictable 10206 && WRITEBACK_BIT_SET 10207 && ((given & 0xf) == ((given >> 12) & 0xf))) 10208 is_unpredictable = true; 10209 } 10210 10211 func (stream, dis_style_text, "]%s", 10212 WRITEBACK_BIT_SET ? "!" : ""); 10213 } 10214 else 10215 { 10216 if (IMMEDIATE_BIT_SET) 10217 { 10218 /* Immediate Post-indexed. */ 10219 /* PR 10924: Offset must be printed, even if it is zero. */ 10220 func (stream, dis_style_text, "], "); 10221 func (stream, dis_style_immediate, "#%s%d", 10222 NEGATIVE_BIT_SET ? "-" : "", offset); 10223 if (NEGATIVE_BIT_SET) 10224 offset = -offset; 10225 value_in_comment = offset; 10226 } 10227 else 10228 { 10229 /* Register Post-indexed. */ 10230 func (stream, dis_style_text, "], %s", 10231 NEGATIVE_BIT_SET ? "-" : ""); 10232 func (stream, dis_style_register, "%s", 10233 arm_regnames[given & 0xf]); 10234 10235 /* Writing back to the register that is the source/ 10236 destination of the load/store is unpredictable. */ 10237 if (! allow_unpredictable 10238 && (given & 0xf) == ((given >> 12) & 0xf)) 10239 is_unpredictable = true; 10240 } 10241 10242 if (! allow_unpredictable) 10243 { 10244 /* Writeback is automatically implied by post- addressing. 10245 Setting the W bit is unnecessary and ARM specify it as 10246 being unpredictable. */ 10247 if (WRITEBACK_BIT_SET 10248 /* Specifying the PC register as the post-indexed 10249 registers is also unpredictable. */ 10250 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 10251 is_unpredictable = true; 10252 } 10253 } 10254 } 10255 break; 10256 10257 case 'b': 10258 { 10259 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 10260 bfd_vma target = disp * 4 + pc + 8; 10261 info->print_address_func (target, info); 10262 10263 /* Fill in instruction information. */ 10264 info->insn_info_valid = 1; 10265 info->insn_type = dis_branch; 10266 info->target = target; 10267 } 10268 break; 10269 10270 case 'c': 10271 if (((given >> 28) & 0xf) != 0xe) 10272 func (stream, dis_style_mnemonic, "%s", 10273 arm_conditional [(given >> 28) & 0xf]); 10274 break; 10275 10276 case 'm': 10277 { 10278 int started = 0; 10279 int reg; 10280 10281 func (stream, dis_style_text, "{"); 10282 for (reg = 0; reg < 16; reg++) 10283 if ((given & (1 << reg)) != 0) 10284 { 10285 if (started) 10286 func (stream, dis_style_text, ", "); 10287 started = 1; 10288 func (stream, dis_style_register, "%s", 10289 arm_regnames[reg]); 10290 } 10291 func (stream, dis_style_text, "}"); 10292 if (! started) 10293 is_unpredictable = true; 10294 } 10295 break; 10296 10297 case 'q': 10298 arm_decode_shift (given, func, stream, false); 10299 break; 10300 10301 case 'o': 10302 if ((given & 0x02000000) != 0) 10303 { 10304 unsigned int rotate = (given & 0xf00) >> 7; 10305 unsigned int immed = (given & 0xff); 10306 unsigned int a, i; 10307 10308 a = (immed << ((32 - rotate) & 31) 10309 | immed >> rotate) & 0xffffffff; 10310 /* If there is another encoding with smaller rotate, 10311 the rotate should be specified directly. */ 10312 for (i = 0; i < 32; i += 2) 10313 if ((a << i | a >> ((32 - i) & 31)) <= 0xff) 10314 break; 10315 10316 if (i != rotate) 10317 { 10318 func (stream, dis_style_immediate, "#%d", immed); 10319 func (stream, dis_style_text, ", "); 10320 func (stream, dis_style_immediate, "%d", rotate); 10321 } 10322 else 10323 func (stream, dis_style_immediate, "#%d", a); 10324 value_in_comment = a; 10325 } 10326 else 10327 arm_decode_shift (given, func, stream, true); 10328 break; 10329 10330 case 'p': 10331 if ((given & 0x0000f000) == 0x0000f000) 10332 func (stream, dis_style_mnemonic, "p"); 10333 break; 10334 case 'O': 10335 if ((given & 0x0000f000) == 0x0000f000) 10336 func (stream, dis_style_text, 10337 "\t@ p-variant is OBSOLETE"); 10338 break; 10339 10340 case 't': 10341 if ((given & 0x01200000) == 0x00200000) 10342 func (stream, dis_style_mnemonic, "t"); 10343 break; 10344 10345 case 'A': 10346 { 10347 int offset = given & 0xff; 10348 10349 value_in_comment = offset * 4; 10350 if (NEGATIVE_BIT_SET) 10351 value_in_comment = - value_in_comment; 10352 10353 func (stream, dis_style_text, "[%s", 10354 arm_regnames [(given >> 16) & 0xf]); 10355 10356 if (PRE_BIT_SET) 10357 { 10358 if (offset) 10359 func (stream, dis_style_text, ", #%d]%s", 10360 (int) value_in_comment, 10361 WRITEBACK_BIT_SET ? "!" : ""); 10362 else 10363 func (stream, dis_style_text, "]"); 10364 } 10365 else 10366 { 10367 func (stream, dis_style_text, "]"); 10368 10369 if (WRITEBACK_BIT_SET) 10370 { 10371 if (offset) 10372 func (stream, dis_style_text, 10373 ", #%d", (int) value_in_comment); 10374 } 10375 else 10376 { 10377 func (stream, dis_style_text, 10378 ", {%d}", (int) offset); 10379 value_in_comment = offset; 10380 } 10381 } 10382 } 10383 break; 10384 10385 case 'B': 10386 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 10387 { 10388 bfd_vma address; 10389 bfd_vma offset = 0; 10390 10391 if (! NEGATIVE_BIT_SET) 10392 /* Is signed, hi bits should be ones. */ 10393 offset = (-1) ^ 0x00ffffff; 10394 10395 /* Offset is (SignExtend(offset field)<<2). */ 10396 offset += given & 0x00ffffff; 10397 offset <<= 2; 10398 address = offset + pc + 8; 10399 10400 if (given & 0x01000000) 10401 /* H bit allows addressing to 2-byte boundaries. */ 10402 address += 2; 10403 10404 info->print_address_func (address, info); 10405 10406 /* Fill in instruction information. */ 10407 info->insn_info_valid = 1; 10408 info->insn_type = dis_branch; 10409 info->target = address; 10410 } 10411 break; 10412 10413 case 'C': 10414 if ((given & 0x02000200) == 0x200) 10415 { 10416 const char * name; 10417 unsigned sysm = (given & 0x004f0000) >> 16; 10418 10419 sysm |= (given & 0x300) >> 4; 10420 name = banked_regname (sysm); 10421 10422 if (name != NULL) 10423 func (stream, dis_style_register, "%s", name); 10424 else 10425 func (stream, dis_style_text, 10426 "(UNDEF: %lu)", (unsigned long) sysm); 10427 } 10428 else 10429 { 10430 func (stream, dis_style_register, "%cPSR_", 10431 (given & 0x00400000) ? 'S' : 'C'); 10432 10433 if (given & 0x80000) 10434 func (stream, dis_style_register, "f"); 10435 if (given & 0x40000) 10436 func (stream, dis_style_register, "s"); 10437 if (given & 0x20000) 10438 func (stream, dis_style_register, "x"); 10439 if (given & 0x10000) 10440 func (stream, dis_style_register, "c"); 10441 } 10442 break; 10443 10444 case 'U': 10445 if ((given & 0xf0) == 0x60) 10446 { 10447 switch (given & 0xf) 10448 { 10449 case 0xf: 10450 func (stream, dis_style_sub_mnemonic, "sy"); 10451 break; 10452 default: 10453 func (stream, dis_style_immediate, "#%d", 10454 (int) given & 0xf); 10455 break; 10456 } 10457 } 10458 else 10459 { 10460 const char * opt = data_barrier_option (given & 0xf); 10461 if (opt != NULL) 10462 func (stream, dis_style_sub_mnemonic, "%s", opt); 10463 else 10464 func (stream, dis_style_immediate, 10465 "#%d", (int) given & 0xf); 10466 } 10467 break; 10468 10469 case '0': case '1': case '2': case '3': case '4': 10470 case '5': case '6': case '7': case '8': case '9': 10471 { 10472 int width; 10473 unsigned long value; 10474 10475 c = arm_decode_bitfield (c, given, &value, &width); 10476 10477 switch (*c) 10478 { 10479 case 'R': 10480 if (value == 15) 10481 is_unpredictable = true; 10482 /* Fall through. */ 10483 case 'r': 10484 case 'T': 10485 /* We want register + 1 when decoding T. */ 10486 if (*c == 'T') 10487 value = (value + 1) & 0xf; 10488 10489 if (c[1] == 'u') 10490 { 10491 /* Eat the 'u' character. */ 10492 ++ c; 10493 10494 if (u_reg == value) 10495 is_unpredictable = true; 10496 u_reg = value; 10497 } 10498 if (c[1] == 'U') 10499 { 10500 /* Eat the 'U' character. */ 10501 ++ c; 10502 10503 if (U_reg == value) 10504 is_unpredictable = true; 10505 U_reg = value; 10506 } 10507 func (stream, dis_style_register, "%s", 10508 arm_regnames[value]); 10509 break; 10510 case 'd': 10511 func (stream, base_style, "%ld", value); 10512 value_in_comment = value; 10513 break; 10514 case 'b': 10515 func (stream, dis_style_immediate, 10516 "%ld", value * 8); 10517 value_in_comment = value * 8; 10518 break; 10519 case 'W': 10520 func (stream, dis_style_immediate, 10521 "%ld", value + 1); 10522 value_in_comment = value + 1; 10523 break; 10524 case 'x': 10525 func (stream, dis_style_immediate, 10526 "0x%08lx", value); 10527 10528 /* Some SWI instructions have special 10529 meanings. */ 10530 if ((given & 0x0fffffff) == 0x0FF00000) 10531 func (stream, dis_style_comment_start, 10532 "\t@ IMB"); 10533 else if ((given & 0x0fffffff) == 0x0FF00001) 10534 func (stream, dis_style_comment_start, 10535 "\t@ IMBRange"); 10536 break; 10537 case 'X': 10538 func (stream, dis_style_immediate, 10539 "%01lx", value & 0xf); 10540 value_in_comment = value; 10541 break; 10542 case '`': 10543 c++; 10544 if (value == 0) 10545 func (stream, dis_style_text, "%c", *c); 10546 break; 10547 case '\'': 10548 c++; 10549 if (value == ((1ul << width) - 1)) 10550 func (stream, base_style, "%c", *c); 10551 break; 10552 case '?': 10553 func (stream, base_style, "%c", 10554 c[(1 << width) - (int) value]); 10555 c += 1 << width; 10556 break; 10557 default: 10558 abort (); 10559 } 10560 } 10561 break; 10562 10563 case 'e': 10564 { 10565 int imm; 10566 10567 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 10568 func (stream, dis_style_immediate, "%d", imm); 10569 value_in_comment = imm; 10570 } 10571 break; 10572 10573 case 'E': 10574 /* LSB and WIDTH fields of BFI or BFC. The machine- 10575 language instruction encodes LSB and MSB. */ 10576 { 10577 long msb = (given & 0x001f0000) >> 16; 10578 long lsb = (given & 0x00000f80) >> 7; 10579 long w = msb - lsb + 1; 10580 10581 if (w > 0) 10582 { 10583 func (stream, dis_style_immediate, "#%lu", lsb); 10584 func (stream, dis_style_text, ", "); 10585 func (stream, dis_style_immediate, "#%lu", w); 10586 } 10587 else 10588 func (stream, dis_style_text, 10589 "(invalid: %lu:%lu)", lsb, msb); 10590 } 10591 break; 10592 10593 case 'R': 10594 /* Get the PSR/banked register name. */ 10595 { 10596 const char * name; 10597 unsigned sysm = (given & 0x004f0000) >> 16; 10598 10599 sysm |= (given & 0x300) >> 4; 10600 name = banked_regname (sysm); 10601 10602 if (name != NULL) 10603 func (stream, dis_style_register, "%s", name); 10604 else 10605 func (stream, dis_style_text, 10606 "(UNDEF: %lu)", (unsigned long) sysm); 10607 } 10608 break; 10609 10610 case 'V': 10611 /* 16-bit unsigned immediate from a MOVT or MOVW 10612 instruction, encoded in bits 0:11 and 15:19. */ 10613 { 10614 long hi = (given & 0x000f0000) >> 4; 10615 long lo = (given & 0x00000fff); 10616 long imm16 = hi | lo; 10617 10618 func (stream, dis_style_immediate, "#%lu", imm16); 10619 value_in_comment = imm16; 10620 } 10621 break; 10622 10623 default: 10624 abort (); 10625 } 10626 } 10627 else 10628 { 10629 10630 if (*c == '@') 10631 base_style = dis_style_comment_start; 10632 10633 if (*c == '\t') 10634 base_style = dis_style_text; 10635 10636 func (stream, base_style, "%c", *c); 10637 } 10638 } 10639 10640 if (value_in_comment > 32 || value_in_comment < -16) 10641 func (stream, dis_style_comment_start, "\t@ 0x%lx", 10642 (value_in_comment & 0xffffffffUL)); 10643 10644 if (is_unpredictable) 10645 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 10646 10647 return; 10648 } 10649 } 10650 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT, 10651 (unsigned) given); 10652 return; 10653 } 10654 10655 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 10656 10657 static void 10658 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 10659 { 10660 const struct opcode16 *insn; 10661 void *stream = info->stream; 10662 fprintf_styled_ftype func = info->fprintf_styled_func; 10663 enum disassembler_style base_style = dis_style_mnemonic; 10664 enum disassembler_style old_base_style = base_style; 10665 10666 for (insn = thumb_opcodes; insn->assembler; insn++) 10667 if ((given & insn->mask) == insn->value) 10668 { 10669 signed long value_in_comment = 0; 10670 const char *c = insn->assembler; 10671 10672 for (; *c; c++) 10673 { 10674 int domaskpc = 0; 10675 int domasklr = 0; 10676 10677 if (*c != '%') 10678 { 10679 if (*c == '@') 10680 base_style = dis_style_comment_start; 10681 10682 if (*c == '\t') 10683 base_style = dis_style_text; 10684 10685 func (stream, base_style, "%c", *c); 10686 10687 continue; 10688 } 10689 10690 switch (*++c) 10691 { 10692 case '{': 10693 ++c; 10694 if (*c == '\0') 10695 abort (); 10696 old_base_style = base_style; 10697 base_style = decode_base_style (*c); 10698 ++c; 10699 if (*c != ':') 10700 abort (); 10701 break; 10702 10703 case '}': 10704 base_style = old_base_style; 10705 break; 10706 10707 case '%': 10708 func (stream, base_style, "%%"); 10709 break; 10710 10711 case 'c': 10712 if (ifthen_state) 10713 func (stream, dis_style_mnemonic, "%s", 10714 arm_conditional[IFTHEN_COND]); 10715 break; 10716 10717 case 'C': 10718 if (ifthen_state) 10719 func (stream, dis_style_mnemonic, "%s", 10720 arm_conditional[IFTHEN_COND]); 10721 else 10722 func (stream, dis_style_mnemonic, "s"); 10723 break; 10724 10725 case 'I': 10726 { 10727 unsigned int tmp; 10728 10729 ifthen_next_state = given & 0xff; 10730 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 10731 func (stream, dis_style_mnemonic, 10732 ((given ^ tmp) & 0x10) ? "e" : "t"); 10733 func (stream, dis_style_text, "\t"); 10734 func (stream, dis_style_sub_mnemonic, "%s", 10735 arm_conditional[(given >> 4) & 0xf]); 10736 } 10737 break; 10738 10739 case 'x': 10740 if (ifthen_next_state) 10741 func (stream, dis_style_comment_start, 10742 "\t@ unpredictable branch in IT block\n"); 10743 break; 10744 10745 case 'X': 10746 if (ifthen_state) 10747 func (stream, dis_style_comment_start, 10748 "\t@ unpredictable <IT:%s>", 10749 arm_conditional[IFTHEN_COND]); 10750 break; 10751 10752 case 'S': 10753 { 10754 long reg; 10755 10756 reg = (given >> 3) & 0x7; 10757 if (given & (1 << 6)) 10758 reg += 8; 10759 10760 func (stream, dis_style_register, "%s", arm_regnames[reg]); 10761 } 10762 break; 10763 10764 case 'D': 10765 { 10766 long reg; 10767 10768 reg = given & 0x7; 10769 if (given & (1 << 7)) 10770 reg += 8; 10771 10772 func (stream, dis_style_register, "%s", arm_regnames[reg]); 10773 } 10774 break; 10775 10776 case 'N': 10777 if (given & (1 << 8)) 10778 domasklr = 1; 10779 /* Fall through. */ 10780 case 'O': 10781 if (*c == 'O' && (given & (1 << 8))) 10782 domaskpc = 1; 10783 /* Fall through. */ 10784 case 'M': 10785 { 10786 int started = 0; 10787 int reg; 10788 10789 func (stream, dis_style_text, "{"); 10790 10791 /* It would be nice if we could spot 10792 ranges, and generate the rS-rE format: */ 10793 for (reg = 0; (reg < 8); reg++) 10794 if ((given & (1 << reg)) != 0) 10795 { 10796 if (started) 10797 func (stream, dis_style_text, ", "); 10798 started = 1; 10799 func (stream, dis_style_register, "%s", 10800 arm_regnames[reg]); 10801 } 10802 10803 if (domasklr) 10804 { 10805 if (started) 10806 func (stream, dis_style_text, ", "); 10807 started = 1; 10808 func (stream, dis_style_register, "%s", 10809 arm_regnames[14] /* "lr" */); 10810 } 10811 10812 if (domaskpc) 10813 { 10814 if (started) 10815 func (stream, dis_style_text, ", "); 10816 func (stream, dis_style_register, "%s", 10817 arm_regnames[15] /* "pc" */); 10818 } 10819 10820 func (stream, dis_style_text, "}"); 10821 } 10822 break; 10823 10824 case 'W': 10825 /* Print writeback indicator for a LDMIA. We are doing a 10826 writeback if the base register is not in the register 10827 mask. */ 10828 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 10829 func (stream, dis_style_text, "!"); 10830 break; 10831 10832 case 'b': 10833 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 10834 { 10835 bfd_vma address = (pc + 4 10836 + ((given & 0x00f8) >> 2) 10837 + ((given & 0x0200) >> 3)); 10838 info->print_address_func (address, info); 10839 10840 /* Fill in instruction information. */ 10841 info->insn_info_valid = 1; 10842 info->insn_type = dis_branch; 10843 info->target = address; 10844 } 10845 break; 10846 10847 case 's': 10848 /* Right shift immediate -- bits 6..10; 1-31 print 10849 as themselves, 0 prints as 32. */ 10850 { 10851 long imm = (given & 0x07c0) >> 6; 10852 if (imm == 0) 10853 imm = 32; 10854 func (stream, dis_style_immediate, "#%ld", imm); 10855 } 10856 break; 10857 10858 case '0': case '1': case '2': case '3': case '4': 10859 case '5': case '6': case '7': case '8': case '9': 10860 { 10861 int bitstart = *c++ - '0'; 10862 int bitend = 0; 10863 10864 while (*c >= '0' && *c <= '9') 10865 bitstart = (bitstart * 10) + *c++ - '0'; 10866 10867 switch (*c) 10868 { 10869 case '-': 10870 { 10871 bfd_vma reg; 10872 10873 c++; 10874 while (*c >= '0' && *c <= '9') 10875 bitend = (bitend * 10) + *c++ - '0'; 10876 if (!bitend) 10877 abort (); 10878 reg = given >> bitstart; 10879 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1; 10880 10881 switch (*c) 10882 { 10883 case 'r': 10884 func (stream, dis_style_register, "%s", 10885 arm_regnames[reg]); 10886 break; 10887 10888 case 'd': 10889 func (stream, dis_style_immediate, "%ld", 10890 (long) reg); 10891 value_in_comment = reg; 10892 break; 10893 10894 case 'H': 10895 func (stream, dis_style_immediate, "%ld", 10896 (long) (reg << 1)); 10897 value_in_comment = reg << 1; 10898 break; 10899 10900 case 'W': 10901 func (stream, dis_style_immediate, "%ld", 10902 (long) (reg << 2)); 10903 value_in_comment = reg << 2; 10904 break; 10905 10906 case 'a': 10907 /* PC-relative address -- the bottom two 10908 bits of the address are dropped 10909 before the calculation. */ 10910 info->print_address_func 10911 (((pc + 4) & ~3) + (reg << 2), info); 10912 value_in_comment = 0; 10913 break; 10914 10915 case 'x': 10916 func (stream, dis_style_immediate, "0x%04lx", 10917 (long) reg); 10918 break; 10919 10920 case 'B': 10921 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 10922 bfd_vma target = reg * 2 + pc + 4; 10923 info->print_address_func (target, info); 10924 value_in_comment = 0; 10925 10926 /* Fill in instruction information. */ 10927 info->insn_info_valid = 1; 10928 info->insn_type = dis_branch; 10929 info->target = target; 10930 break; 10931 10932 case 'c': 10933 func (stream, dis_style_mnemonic, "%s", 10934 arm_conditional [reg]); 10935 break; 10936 10937 default: 10938 abort (); 10939 } 10940 } 10941 break; 10942 10943 case '\'': 10944 c++; 10945 if ((given & (1 << bitstart)) != 0) 10946 func (stream, base_style, "%c", *c); 10947 break; 10948 10949 case '?': 10950 ++c; 10951 if ((given & (1 << bitstart)) != 0) 10952 func (stream, base_style, "%c", *c++); 10953 else 10954 func (stream, base_style, "%c", *++c); 10955 break; 10956 10957 default: 10958 abort (); 10959 } 10960 } 10961 break; 10962 10963 default: 10964 abort (); 10965 } 10966 } 10967 10968 if (value_in_comment > 32 || value_in_comment < -16) 10969 func (stream, dis_style_comment_start, 10970 "\t@ 0x%lx", value_in_comment); 10971 return; 10972 } 10973 10974 /* No match. */ 10975 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT, 10976 (unsigned) given); 10977 return; 10978 } 10979 10980 /* Return the name of an V7M special register. */ 10981 10982 static const char * 10983 psr_name (int regno) 10984 { 10985 switch (regno) 10986 { 10987 case 0x0: return "APSR"; 10988 case 0x1: return "IAPSR"; 10989 case 0x2: return "EAPSR"; 10990 case 0x3: return "PSR"; 10991 case 0x5: return "IPSR"; 10992 case 0x6: return "EPSR"; 10993 case 0x7: return "IEPSR"; 10994 case 0x8: return "MSP"; 10995 case 0x9: return "PSP"; 10996 case 0xa: return "MSPLIM"; 10997 case 0xb: return "PSPLIM"; 10998 case 0x10: return "PRIMASK"; 10999 case 0x11: return "BASEPRI"; 11000 case 0x12: return "BASEPRI_MAX"; 11001 case 0x13: return "FAULTMASK"; 11002 case 0x14: return "CONTROL"; 11003 case 0x20: return "PAC_KEY_P_0"; 11004 case 0x21: return "PAC_KEY_P_1"; 11005 case 0x22: return "PAC_KEY_P_2"; 11006 case 0x23: return "PAC_KEY_P_3"; 11007 case 0x24: return "PAC_KEY_U_0"; 11008 case 0x25: return "PAC_KEY_U_1"; 11009 case 0x26: return "PAC_KEY_U_2"; 11010 case 0x27: return "PAC_KEY_U_3"; 11011 case 0x88: return "MSP_NS"; 11012 case 0x89: return "PSP_NS"; 11013 case 0x8a: return "MSPLIM_NS"; 11014 case 0x8b: return "PSPLIM_NS"; 11015 case 0x90: return "PRIMASK_NS"; 11016 case 0x91: return "BASEPRI_NS"; 11017 case 0x93: return "FAULTMASK_NS"; 11018 case 0x94: return "CONTROL_NS"; 11019 case 0x98: return "SP_NS"; 11020 case 0xa0: return "PAC_KEY_P_0_NS"; 11021 case 0xa1: return "PAC_KEY_P_1_NS"; 11022 case 0xa2: return "PAC_KEY_P_2_NS"; 11023 case 0xa3: return "PAC_KEY_P_3_NS"; 11024 case 0xa4: return "PAC_KEY_U_0_NS"; 11025 case 0xa5: return "PAC_KEY_U_1_NS"; 11026 case 0xa6: return "PAC_KEY_U_2_NS"; 11027 case 0xa7: return "PAC_KEY_U_3_NS"; 11028 default: return "<unknown>"; 11029 } 11030 } 11031 11032 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 11033 11034 static void 11035 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 11036 { 11037 const struct opcode32 *insn; 11038 void *stream = info->stream; 11039 fprintf_styled_ftype func = info->fprintf_styled_func; 11040 bool is_mve = is_v81m_architecture (info); 11041 enum disassembler_style base_style = dis_style_mnemonic; 11042 enum disassembler_style old_base_style = base_style; 11043 11044 if (print_insn_coprocessor (pc, info, given, true)) 11045 return; 11046 11047 if (!is_mve && print_insn_neon (info, given, true)) 11048 return; 11049 11050 if (is_mve && print_insn_mve (info, given)) 11051 return; 11052 11053 if (print_insn_cde (info, given, true)) 11054 return; 11055 11056 if (print_insn_generic_coprocessor (pc, info, given, true)) 11057 return; 11058 11059 for (insn = thumb32_opcodes; insn->assembler; insn++) 11060 if ((given & insn->mask) == insn->value) 11061 { 11062 bool is_clrm = false; 11063 bool is_unpredictable = false; 11064 signed long value_in_comment = 0; 11065 const char *c = insn->assembler; 11066 11067 for (; *c; c++) 11068 { 11069 if (*c != '%') 11070 { 11071 if (*c == '@') 11072 base_style = dis_style_comment_start; 11073 if (*c == '\t') 11074 base_style = dis_style_text; 11075 func (stream, base_style, "%c", *c); 11076 continue; 11077 } 11078 11079 switch (*++c) 11080 { 11081 case '{': 11082 ++c; 11083 if (*c == '\0') 11084 abort (); 11085 old_base_style = base_style; 11086 base_style = decode_base_style (*c); 11087 ++c; 11088 if (*c != ':') 11089 abort (); 11090 break; 11091 11092 case '}': 11093 base_style = old_base_style; 11094 break; 11095 11096 case '%': 11097 func (stream, base_style, "%%"); 11098 break; 11099 11100 case 'c': 11101 if (ifthen_state) 11102 func (stream, dis_style_mnemonic, "%s", 11103 arm_conditional[IFTHEN_COND]); 11104 break; 11105 11106 case 'x': 11107 if (ifthen_next_state) 11108 func (stream, dis_style_comment_start, 11109 "\t@ unpredictable branch in IT block\n"); 11110 break; 11111 11112 case 'X': 11113 if (ifthen_state) 11114 func (stream, dis_style_comment_start, 11115 "\t@ unpredictable <IT:%s>", 11116 arm_conditional[IFTHEN_COND]); 11117 break; 11118 11119 case 'I': 11120 { 11121 unsigned int imm12 = 0; 11122 11123 imm12 |= (given & 0x000000ffu); 11124 imm12 |= (given & 0x00007000u) >> 4; 11125 imm12 |= (given & 0x04000000u) >> 15; 11126 func (stream, dis_style_immediate, "#%u", imm12); 11127 value_in_comment = imm12; 11128 } 11129 break; 11130 11131 case 'M': 11132 { 11133 unsigned int bits = 0, imm, imm8, mod; 11134 11135 bits |= (given & 0x000000ffu); 11136 bits |= (given & 0x00007000u) >> 4; 11137 bits |= (given & 0x04000000u) >> 15; 11138 imm8 = (bits & 0x0ff); 11139 mod = (bits & 0xf00) >> 8; 11140 switch (mod) 11141 { 11142 case 0: imm = imm8; break; 11143 case 1: imm = ((imm8 << 16) | imm8); break; 11144 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 11145 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 11146 default: 11147 mod = (bits & 0xf80) >> 7; 11148 imm8 = (bits & 0x07f) | 0x80; 11149 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 11150 } 11151 func (stream, dis_style_immediate, "#%u", imm); 11152 value_in_comment = imm; 11153 } 11154 break; 11155 11156 case 'J': 11157 { 11158 unsigned int imm = 0; 11159 11160 imm |= (given & 0x000000ffu); 11161 imm |= (given & 0x00007000u) >> 4; 11162 imm |= (given & 0x04000000u) >> 15; 11163 imm |= (given & 0x000f0000u) >> 4; 11164 func (stream, dis_style_immediate, "#%u", imm); 11165 value_in_comment = imm; 11166 } 11167 break; 11168 11169 case 'K': 11170 { 11171 unsigned int imm = 0; 11172 11173 imm |= (given & 0x000f0000u) >> 16; 11174 imm |= (given & 0x00000ff0u) >> 0; 11175 imm |= (given & 0x0000000fu) << 12; 11176 func (stream, dis_style_immediate, "#%u", imm); 11177 value_in_comment = imm; 11178 } 11179 break; 11180 11181 case 'H': 11182 { 11183 unsigned int imm = 0; 11184 11185 imm |= (given & 0x000f0000u) >> 4; 11186 imm |= (given & 0x00000fffu) >> 0; 11187 func (stream, dis_style_immediate, "#%u", imm); 11188 value_in_comment = imm; 11189 } 11190 break; 11191 11192 case 'V': 11193 { 11194 unsigned int imm = 0; 11195 11196 imm |= (given & 0x00000fffu); 11197 imm |= (given & 0x000f0000u) >> 4; 11198 func (stream, dis_style_immediate, "#%u", imm); 11199 value_in_comment = imm; 11200 } 11201 break; 11202 11203 case 'S': 11204 { 11205 unsigned int reg = (given & 0x0000000fu); 11206 unsigned int stp = (given & 0x00000030u) >> 4; 11207 unsigned int imm = 0; 11208 imm |= (given & 0x000000c0u) >> 6; 11209 imm |= (given & 0x00007000u) >> 10; 11210 11211 func (stream, dis_style_register, "%s", arm_regnames[reg]); 11212 switch (stp) 11213 { 11214 case 0: 11215 if (imm > 0) 11216 { 11217 func (stream, dis_style_text, ", "); 11218 func (stream, dis_style_sub_mnemonic, "lsl "); 11219 func (stream, dis_style_immediate, "#%u", imm); 11220 } 11221 break; 11222 11223 case 1: 11224 if (imm == 0) 11225 imm = 32; 11226 func (stream, dis_style_text, ", "); 11227 func (stream, dis_style_sub_mnemonic, "lsr "); 11228 func (stream, dis_style_immediate, "#%u", imm); 11229 break; 11230 11231 case 2: 11232 if (imm == 0) 11233 imm = 32; 11234 func (stream, dis_style_text, ", "); 11235 func (stream, dis_style_sub_mnemonic, "asr "); 11236 func (stream, dis_style_immediate, "#%u", imm); 11237 break; 11238 11239 case 3: 11240 if (imm == 0) 11241 { 11242 func (stream, dis_style_text, ", "); 11243 func (stream, dis_style_sub_mnemonic, "rrx"); 11244 } 11245 else 11246 { 11247 func (stream, dis_style_text, ", "); 11248 func (stream, dis_style_sub_mnemonic, "ror "); 11249 func (stream, dis_style_immediate, "#%u", imm); 11250 } 11251 } 11252 } 11253 break; 11254 11255 case 'a': 11256 { 11257 unsigned int Rn = (given & 0x000f0000) >> 16; 11258 unsigned int U = ! NEGATIVE_BIT_SET; 11259 unsigned int op = (given & 0x00000f00) >> 8; 11260 unsigned int i12 = (given & 0x00000fff); 11261 unsigned int i8 = (given & 0x000000ff); 11262 bool writeback = false, postind = false; 11263 bfd_vma offset = 0; 11264 11265 func (stream, dis_style_text, "["); 11266 func (stream, dis_style_register, "%s", arm_regnames[Rn]); 11267 if (U) /* 12-bit positive immediate offset. */ 11268 { 11269 offset = i12; 11270 if (Rn != 15) 11271 value_in_comment = offset; 11272 } 11273 else if (Rn == 15) /* 12-bit negative immediate offset. */ 11274 offset = - (int) i12; 11275 else if (op == 0x0) /* Shifted register offset. */ 11276 { 11277 unsigned int Rm = (i8 & 0x0f); 11278 unsigned int sh = (i8 & 0x30) >> 4; 11279 11280 func (stream, dis_style_text, ", "); 11281 func (stream, dis_style_register, "%s", 11282 arm_regnames[Rm]); 11283 if (sh) 11284 { 11285 func (stream, dis_style_text, ", "); 11286 func (stream, dis_style_sub_mnemonic, "lsl "); 11287 func (stream, dis_style_immediate, "#%u", sh); 11288 } 11289 func (stream, dis_style_text, "]"); 11290 break; 11291 } 11292 else switch (op) 11293 { 11294 case 0xE: /* 8-bit positive immediate offset. */ 11295 offset = i8; 11296 break; 11297 11298 case 0xC: /* 8-bit negative immediate offset. */ 11299 offset = -i8; 11300 break; 11301 11302 case 0xF: /* 8-bit + preindex with wb. */ 11303 offset = i8; 11304 writeback = true; 11305 break; 11306 11307 case 0xD: /* 8-bit - preindex with wb. */ 11308 offset = -i8; 11309 writeback = true; 11310 break; 11311 11312 case 0xB: /* 8-bit + postindex. */ 11313 offset = i8; 11314 postind = true; 11315 break; 11316 11317 case 0x9: /* 8-bit - postindex. */ 11318 offset = -i8; 11319 postind = true; 11320 break; 11321 11322 default: 11323 func (stream, dis_style_text, ", <undefined>]"); 11324 goto skip; 11325 } 11326 11327 if (postind) 11328 { 11329 func (stream, dis_style_text, "], "); 11330 func (stream, dis_style_immediate, "#%d", (int) offset); 11331 } 11332 else 11333 { 11334 if (offset) 11335 { 11336 func (stream, dis_style_text, ", "); 11337 func (stream, dis_style_immediate, "#%d", 11338 (int) offset); 11339 } 11340 func (stream, dis_style_text, writeback ? "]!" : "]"); 11341 } 11342 11343 if (Rn == 15) 11344 { 11345 func (stream, dis_style_comment_start, "\t@ "); 11346 info->print_address_func (((pc + 4) & ~3) + offset, info); 11347 } 11348 } 11349 skip: 11350 break; 11351 11352 case 'A': 11353 { 11354 unsigned int U = ! NEGATIVE_BIT_SET; 11355 unsigned int W = WRITEBACK_BIT_SET; 11356 unsigned int Rn = (given & 0x000f0000) >> 16; 11357 unsigned int off = (given & 0x000000ff); 11358 11359 func (stream, dis_style_text, "["); 11360 func (stream, dis_style_register, "%s", arm_regnames[Rn]); 11361 11362 if (PRE_BIT_SET) 11363 { 11364 if (off || !U) 11365 { 11366 func (stream, dis_style_text, ", "); 11367 func (stream, dis_style_immediate, "#%c%u", 11368 U ? '+' : '-', off * 4); 11369 value_in_comment = off * 4 * (U ? 1 : -1); 11370 } 11371 func (stream, dis_style_text, "]"); 11372 if (W) 11373 func (stream, dis_style_text, "!"); 11374 } 11375 else 11376 { 11377 func (stream, dis_style_text, "], "); 11378 if (W) 11379 { 11380 func (stream, dis_style_immediate, "#%c%u", 11381 U ? '+' : '-', off * 4); 11382 value_in_comment = off * 4 * (U ? 1 : -1); 11383 } 11384 else 11385 { 11386 func (stream, dis_style_text, "{"); 11387 func (stream, dis_style_immediate, "%u", off); 11388 func (stream, dis_style_text, "}"); 11389 value_in_comment = off; 11390 } 11391 } 11392 } 11393 break; 11394 11395 case 'w': 11396 { 11397 unsigned int Sbit = (given & 0x01000000) >> 24; 11398 unsigned int type = (given & 0x00600000) >> 21; 11399 11400 switch (type) 11401 { 11402 case 0: 11403 func (stream, dis_style_mnemonic, Sbit ? "sb" : "b"); 11404 break; 11405 case 1: 11406 func (stream, dis_style_mnemonic, Sbit ? "sh" : "h"); 11407 break; 11408 case 2: 11409 if (Sbit) 11410 func (stream, dis_style_text, "??"); 11411 break; 11412 case 3: 11413 func (stream, dis_style_text, "??"); 11414 break; 11415 } 11416 } 11417 break; 11418 11419 case 'n': 11420 is_clrm = true; 11421 /* Fall through. */ 11422 case 'm': 11423 { 11424 int started = 0; 11425 int reg; 11426 11427 func (stream, dis_style_text, "{"); 11428 for (reg = 0; reg < 16; reg++) 11429 if ((given & (1 << reg)) != 0) 11430 { 11431 if (started) 11432 func (stream, dis_style_text, ", "); 11433 started = 1; 11434 if (is_clrm && reg == 13) 11435 func (stream, dis_style_text, "(invalid: %s)", 11436 arm_regnames[reg]); 11437 else if (is_clrm && reg == 15) 11438 func (stream, dis_style_register, "%s", "APSR"); 11439 else 11440 func (stream, dis_style_register, "%s", 11441 arm_regnames[reg]); 11442 } 11443 func (stream, dis_style_text, "}"); 11444 } 11445 break; 11446 11447 case 'E': 11448 { 11449 unsigned int msb = (given & 0x0000001f); 11450 unsigned int lsb = 0; 11451 11452 lsb |= (given & 0x000000c0u) >> 6; 11453 lsb |= (given & 0x00007000u) >> 10; 11454 func (stream, dis_style_immediate, "#%u", lsb); 11455 func (stream, dis_style_text, ", "); 11456 func (stream, dis_style_immediate, "#%u", msb - lsb + 1); 11457 } 11458 break; 11459 11460 case 'F': 11461 { 11462 unsigned int width = (given & 0x0000001f) + 1; 11463 unsigned int lsb = 0; 11464 11465 lsb |= (given & 0x000000c0u) >> 6; 11466 lsb |= (given & 0x00007000u) >> 10; 11467 func (stream, dis_style_immediate, "#%u", lsb); 11468 func (stream, dis_style_text, ", "); 11469 func (stream, dis_style_immediate, "#%u", width); 11470 } 11471 break; 11472 11473 case 'G': 11474 { 11475 unsigned int boff = (((given & 0x07800000) >> 23) << 1); 11476 func (stream, dis_style_immediate, "%x", boff); 11477 } 11478 break; 11479 11480 case 'W': 11481 { 11482 unsigned int immA = (given & 0x001f0000u) >> 16; 11483 unsigned int immB = (given & 0x000007feu) >> 1; 11484 unsigned int immC = (given & 0x00000800u) >> 11; 11485 bfd_vma offset = 0; 11486 11487 offset |= immA << 12; 11488 offset |= immB << 2; 11489 offset |= immC << 1; 11490 /* Sign extend. */ 11491 offset = (offset & 0x10000) ? offset - (1 << 17) : offset; 11492 11493 info->print_address_func (pc + 4 + offset, info); 11494 } 11495 break; 11496 11497 case 'Y': 11498 { 11499 unsigned int immA = (given & 0x007f0000u) >> 16; 11500 unsigned int immB = (given & 0x000007feu) >> 1; 11501 unsigned int immC = (given & 0x00000800u) >> 11; 11502 bfd_vma offset = 0; 11503 11504 offset |= immA << 12; 11505 offset |= immB << 2; 11506 offset |= immC << 1; 11507 /* Sign extend. */ 11508 offset = (offset & 0x40000) ? offset - (1 << 19) : offset; 11509 11510 info->print_address_func (pc + 4 + offset, info); 11511 } 11512 break; 11513 11514 case 'Z': 11515 { 11516 unsigned int immA = (given & 0x00010000u) >> 16; 11517 unsigned int immB = (given & 0x000007feu) >> 1; 11518 unsigned int immC = (given & 0x00000800u) >> 11; 11519 bfd_vma offset = 0; 11520 11521 offset |= immA << 12; 11522 offset |= immB << 2; 11523 offset |= immC << 1; 11524 /* Sign extend. */ 11525 offset = (offset & 0x1000) ? offset - (1 << 13) : offset; 11526 11527 info->print_address_func (pc + 4 + offset, info); 11528 11529 unsigned int T = (given & 0x00020000u) >> 17; 11530 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1); 11531 unsigned int boffset = (T == 1) ? 4 : 2; 11532 func (stream, dis_style_text, ", "); 11533 func (stream, dis_style_immediate, "%x", 11534 endoffset + boffset); 11535 } 11536 break; 11537 11538 case 'Q': 11539 { 11540 unsigned int immh = (given & 0x000007feu) >> 1; 11541 unsigned int imml = (given & 0x00000800u) >> 11; 11542 bfd_vma imm32 = 0; 11543 11544 imm32 |= immh << 2; 11545 imm32 |= imml << 1; 11546 11547 info->print_address_func (pc + 4 + imm32, info); 11548 } 11549 break; 11550 11551 case 'P': 11552 { 11553 unsigned int immh = (given & 0x000007feu) >> 1; 11554 unsigned int imml = (given & 0x00000800u) >> 11; 11555 bfd_vma imm32 = 0; 11556 11557 imm32 |= immh << 2; 11558 imm32 |= imml << 1; 11559 11560 info->print_address_func (pc + 4 - imm32, info); 11561 } 11562 break; 11563 11564 case 'b': 11565 { 11566 unsigned int S = (given & 0x04000000u) >> 26; 11567 unsigned int J1 = (given & 0x00002000u) >> 13; 11568 unsigned int J2 = (given & 0x00000800u) >> 11; 11569 bfd_vma offset = 0; 11570 11571 offset |= !S << 20; 11572 offset |= J2 << 19; 11573 offset |= J1 << 18; 11574 offset |= (given & 0x003f0000) >> 4; 11575 offset |= (given & 0x000007ff) << 1; 11576 offset -= (1 << 20); 11577 11578 bfd_vma target = pc + 4 + offset; 11579 info->print_address_func (target, info); 11580 11581 /* Fill in instruction information. */ 11582 info->insn_info_valid = 1; 11583 info->insn_type = dis_branch; 11584 info->target = target; 11585 } 11586 break; 11587 11588 case 'B': 11589 { 11590 unsigned int S = (given & 0x04000000u) >> 26; 11591 unsigned int I1 = (given & 0x00002000u) >> 13; 11592 unsigned int I2 = (given & 0x00000800u) >> 11; 11593 bfd_vma offset = 0; 11594 11595 offset |= !S << 24; 11596 offset |= !(I1 ^ S) << 23; 11597 offset |= !(I2 ^ S) << 22; 11598 offset |= (given & 0x03ff0000u) >> 4; 11599 offset |= (given & 0x000007ffu) << 1; 11600 offset -= (1 << 24); 11601 offset += pc + 4; 11602 11603 /* BLX target addresses are always word aligned. */ 11604 if ((given & 0x00001000u) == 0) 11605 offset &= ~2u; 11606 11607 info->print_address_func (offset, info); 11608 11609 /* Fill in instruction information. */ 11610 info->insn_info_valid = 1; 11611 info->insn_type = dis_branch; 11612 info->target = offset; 11613 } 11614 break; 11615 11616 case 's': 11617 { 11618 unsigned int shift = 0; 11619 11620 shift |= (given & 0x000000c0u) >> 6; 11621 shift |= (given & 0x00007000u) >> 10; 11622 if (WRITEBACK_BIT_SET) 11623 { 11624 func (stream, dis_style_text, ", "); 11625 func (stream, dis_style_sub_mnemonic, "asr "); 11626 func (stream, dis_style_immediate, "#%u", shift); 11627 } 11628 else if (shift) 11629 { 11630 func (stream, dis_style_text, ", "); 11631 func (stream, dis_style_sub_mnemonic, "lsl "); 11632 func (stream, dis_style_immediate, "#%u", shift); 11633 } 11634 /* else print nothing - lsl #0 */ 11635 } 11636 break; 11637 11638 case 'R': 11639 { 11640 unsigned int rot = (given & 0x00000030) >> 4; 11641 11642 if (rot) 11643 { 11644 func (stream, dis_style_text, ", "); 11645 func (stream, dis_style_sub_mnemonic, "ror "); 11646 func (stream, dis_style_immediate, "#%u", rot * 8); 11647 } 11648 } 11649 break; 11650 11651 case 'U': 11652 if ((given & 0xf0) == 0x60) 11653 { 11654 switch (given & 0xf) 11655 { 11656 case 0xf: 11657 func (stream, dis_style_sub_mnemonic, "sy"); 11658 break; 11659 default: 11660 func (stream, dis_style_immediate, "#%d", 11661 (int) given & 0xf); 11662 break; 11663 } 11664 } 11665 else 11666 { 11667 const char * opt = data_barrier_option (given & 0xf); 11668 if (opt != NULL) 11669 func (stream, dis_style_sub_mnemonic, "%s", opt); 11670 else 11671 func (stream, dis_style_immediate, "#%d", 11672 (int) given & 0xf); 11673 } 11674 break; 11675 11676 case 'C': 11677 if ((given & 0xff) == 0) 11678 { 11679 func (stream, dis_style_register, "%cPSR_", 11680 (given & 0x100000) ? 'S' : 'C'); 11681 11682 if (given & 0x800) 11683 func (stream, dis_style_register, "f"); 11684 if (given & 0x400) 11685 func (stream, dis_style_register, "s"); 11686 if (given & 0x200) 11687 func (stream, dis_style_register, "x"); 11688 if (given & 0x100) 11689 func (stream, dis_style_register, "c"); 11690 } 11691 else if (is_v81m_architecture (info)) 11692 func (stream, dis_style_register, "%s", 11693 psr_name (given & 0xff)); 11694 11695 else if ((given & 0x20) == 0x20) 11696 { 11697 char const* name; 11698 unsigned sysm = (given & 0xf00) >> 8; 11699 11700 sysm |= (given & 0x30); 11701 sysm |= (given & 0x00100000) >> 14; 11702 name = banked_regname (sysm); 11703 11704 if (name != NULL) 11705 func (stream, dis_style_register, "%s", name); 11706 else 11707 func (stream, dis_style_text, 11708 "(UNDEF: %lu)", (unsigned long) sysm); 11709 } 11710 else 11711 { 11712 func (stream, dis_style_register, "%s", 11713 psr_name (given & 0xff)); 11714 } 11715 break; 11716 11717 case 'D': 11718 if (is_v81m_architecture (info)) 11719 func (stream, dis_style_register, "%s", 11720 psr_name (given & 0xff)); 11721 else if (((given & 0xff) == 0) 11722 || ((given & 0x20) == 0x20)) 11723 { 11724 char const* name; 11725 unsigned sm = (given & 0xf0000) >> 16; 11726 11727 sm |= (given & 0x30); 11728 sm |= (given & 0x00100000) >> 14; 11729 name = banked_regname (sm); 11730 11731 if (name != NULL) 11732 func (stream, dis_style_register, "%s", name); 11733 else 11734 func (stream, dis_style_text, 11735 "(UNDEF: %lu)", (unsigned long) sm); 11736 } 11737 else 11738 func (stream, dis_style_register, "%s", 11739 psr_name (given & 0xff)); 11740 break; 11741 11742 case '0': case '1': case '2': case '3': case '4': 11743 case '5': case '6': case '7': case '8': case '9': 11744 { 11745 int width; 11746 unsigned long val; 11747 11748 c = arm_decode_bitfield (c, given, &val, &width); 11749 11750 switch (*c) 11751 { 11752 case 's': 11753 if (val <= 3) 11754 func (stream, dis_style_mnemonic, "%s", 11755 mve_vec_sizename[val]); 11756 else 11757 func (stream, dis_style_text, "<undef size>"); 11758 break; 11759 11760 case 'd': 11761 func (stream, base_style, "%lu", val); 11762 value_in_comment = val; 11763 break; 11764 11765 case 'D': 11766 func (stream, dis_style_immediate, "%lu", val + 1); 11767 value_in_comment = val + 1; 11768 break; 11769 11770 case 'W': 11771 func (stream, dis_style_immediate, "%lu", val * 4); 11772 value_in_comment = val * 4; 11773 break; 11774 11775 case 'S': 11776 if (val == 13) 11777 is_unpredictable = true; 11778 /* Fall through. */ 11779 case 'R': 11780 if (val == 15) 11781 is_unpredictable = true; 11782 /* Fall through. */ 11783 case 'r': 11784 func (stream, dis_style_register, "%s", 11785 arm_regnames[val]); 11786 break; 11787 11788 case 'c': 11789 func (stream, base_style, "%s", arm_conditional[val]); 11790 break; 11791 11792 case '\'': 11793 c++; 11794 if (val == ((1ul << width) - 1)) 11795 func (stream, base_style, "%c", *c); 11796 break; 11797 11798 case '`': 11799 c++; 11800 if (val == 0) 11801 func (stream, dis_style_immediate, "%c", *c); 11802 break; 11803 11804 case '?': 11805 func (stream, dis_style_mnemonic, "%c", 11806 c[(1 << width) - (int) val]); 11807 c += 1 << width; 11808 break; 11809 11810 case 'x': 11811 func (stream, dis_style_immediate, "0x%lx", 11812 val & 0xffffffffUL); 11813 break; 11814 11815 default: 11816 abort (); 11817 } 11818 } 11819 break; 11820 11821 case 'L': 11822 /* PR binutils/12534 11823 If we have a PC relative offset in an LDRD or STRD 11824 instructions then display the decoded address. */ 11825 if (((given >> 16) & 0xf) == 0xf) 11826 { 11827 bfd_vma offset = (given & 0xff) * 4; 11828 11829 if ((given & (1 << 23)) == 0) 11830 offset = - offset; 11831 func (stream, dis_style_comment_start, "\t@ "); 11832 info->print_address_func ((pc & ~3) + 4 + offset, info); 11833 } 11834 break; 11835 11836 default: 11837 abort (); 11838 } 11839 } 11840 11841 if (value_in_comment > 32 || value_in_comment < -16) 11842 func (stream, dis_style_comment_start, "\t@ 0x%lx", 11843 value_in_comment); 11844 11845 if (is_unpredictable) 11846 func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION); 11847 11848 return; 11849 } 11850 11851 /* No match. */ 11852 func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT, 11853 (unsigned) given); 11854 return; 11855 } 11856 11857 /* Print data bytes on INFO->STREAM. */ 11858 11859 static void 11860 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 11861 struct disassemble_info *info, 11862 long given) 11863 { 11864 fprintf_styled_ftype func = info->fprintf_styled_func; 11865 11866 switch (info->bytes_per_chunk) 11867 { 11868 case 1: 11869 func (info->stream, dis_style_assembler_directive, ".byte"); 11870 func (info->stream, dis_style_text, "\t"); 11871 func (info->stream, dis_style_immediate, "0x%02lx", given); 11872 break; 11873 case 2: 11874 func (info->stream, dis_style_assembler_directive, ".short"); 11875 func (info->stream, dis_style_text, "\t"); 11876 func (info->stream, dis_style_immediate, "0x%04lx", given); 11877 break; 11878 case 4: 11879 func (info->stream, dis_style_assembler_directive, ".word"); 11880 func (info->stream, dis_style_text, "\t"); 11881 func (info->stream, dis_style_immediate, "0x%08lx", given); 11882 break; 11883 default: 11884 abort (); 11885 } 11886 } 11887 11888 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 11889 being displayed in symbol relative addresses. 11890 11891 Also disallow private symbol, with __tagsym$$ prefix, 11892 from ARM RVCT toolchain being displayed. */ 11893 11894 bool 11895 arm_symbol_is_valid (asymbol * sym, 11896 struct disassemble_info * info ATTRIBUTE_UNUSED) 11897 { 11898 const char * name; 11899 11900 if (sym == NULL) 11901 return false; 11902 11903 name = bfd_asymbol_name (sym); 11904 11905 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 11906 } 11907 11908 /* Parse the string of disassembler options. */ 11909 11910 static void 11911 parse_arm_disassembler_options (const char *options) 11912 { 11913 const char *opt; 11914 11915 force_thumb = false; 11916 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 11917 { 11918 if (startswith (opt, "reg-names-")) 11919 { 11920 unsigned int i; 11921 for (i = 0; i < NUM_ARM_OPTIONS; i++) 11922 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 11923 { 11924 regname_selected = i; 11925 break; 11926 } 11927 11928 if (i >= NUM_ARM_OPTIONS) 11929 /* xgettext: c-format */ 11930 opcodes_error_handler (_("unrecognised register name set: %s"), 11931 opt); 11932 } 11933 else if (startswith (opt, "force-thumb")) 11934 force_thumb = 1; 11935 else if (startswith (opt, "no-force-thumb")) 11936 force_thumb = 0; 11937 else if (startswith (opt, "coproc")) 11938 { 11939 const char *procptr = opt + sizeof ("coproc") - 1; 11940 char *endptr; 11941 uint8_t coproc_number = strtol (procptr, &endptr, 10); 11942 if (endptr != procptr + 1 || coproc_number > 7) 11943 { 11944 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"), 11945 opt); 11946 continue; 11947 } 11948 if (*endptr != '=') 11949 { 11950 opcodes_error_handler (_("coproc must have an argument: %s"), 11951 opt); 11952 continue; 11953 } 11954 endptr += 1; 11955 if (startswith (endptr, "generic")) 11956 cde_coprocs &= ~(1 << coproc_number); 11957 else if (startswith (endptr, "cde") 11958 || startswith (endptr, "CDE")) 11959 cde_coprocs |= (1 << coproc_number); 11960 else 11961 { 11962 opcodes_error_handler ( 11963 _("coprocN argument takes options \"generic\"," 11964 " \"cde\", or \"CDE\": %s"), opt); 11965 } 11966 } 11967 else 11968 /* xgettext: c-format */ 11969 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 11970 } 11971 11972 return; 11973 } 11974 11975 static bool 11976 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 11977 enum map_type *map_symbol); 11978 11979 /* Search back through the insn stream to determine if this instruction is 11980 conditionally executed. */ 11981 11982 static void 11983 find_ifthen_state (bfd_vma pc, 11984 struct disassemble_info *info, 11985 bool little) 11986 { 11987 unsigned char b[2]; 11988 unsigned int insn; 11989 int status; 11990 /* COUNT is twice the number of instructions seen. It will be odd if we 11991 just crossed an instruction boundary. */ 11992 int count; 11993 int it_count; 11994 unsigned int seen_it; 11995 bfd_vma addr; 11996 11997 ifthen_address = pc; 11998 ifthen_state = 0; 11999 12000 addr = pc; 12001 count = 1; 12002 it_count = 0; 12003 seen_it = 0; 12004 /* Scan backwards looking for IT instructions, keeping track of where 12005 instruction boundaries are. We don't know if something is actually an 12006 IT instruction until we find a definite instruction boundary. */ 12007 for (;;) 12008 { 12009 if (addr == 0 || info->symbol_at_address_func (addr, info)) 12010 { 12011 /* A symbol must be on an instruction boundary, and will not 12012 be within an IT block. */ 12013 if (seen_it && (count & 1)) 12014 break; 12015 12016 return; 12017 } 12018 addr -= 2; 12019 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 12020 if (status) 12021 return; 12022 12023 if (little) 12024 insn = (b[0]) | (b[1] << 8); 12025 else 12026 insn = (b[1]) | (b[0] << 8); 12027 if (seen_it) 12028 { 12029 if ((insn & 0xf800) < 0xe800) 12030 { 12031 /* Addr + 2 is an instruction boundary. See if this matches 12032 the expected boundary based on the position of the last 12033 IT candidate. */ 12034 if (count & 1) 12035 break; 12036 seen_it = 0; 12037 } 12038 } 12039 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 12040 { 12041 enum map_type type = MAP_ARM; 12042 bool found = mapping_symbol_for_insn (addr, info, &type); 12043 12044 if (!found || (found && type == MAP_THUMB)) 12045 { 12046 /* This could be an IT instruction. */ 12047 seen_it = insn; 12048 it_count = count >> 1; 12049 } 12050 } 12051 if ((insn & 0xf800) >= 0xe800) 12052 count++; 12053 else 12054 count = (count + 2) | 1; 12055 /* IT blocks contain at most 4 instructions. */ 12056 if (count >= 8 && !seen_it) 12057 return; 12058 } 12059 /* We found an IT instruction. */ 12060 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 12061 if ((ifthen_state & 0xf) == 0) 12062 ifthen_state = 0; 12063 } 12064 12065 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 12066 mapping symbol. */ 12067 12068 static int 12069 is_mapping_symbol (struct disassemble_info *info, 12070 int n, 12071 enum map_type *map_type) 12072 { 12073 const char *name = bfd_asymbol_name (info->symtab[n]); 12074 12075 if (name[0] == '$' 12076 && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 12077 && (name[2] == 0 || name[2] == '.')) 12078 { 12079 *map_type = ((name[1] == 'a') ? MAP_ARM 12080 : (name[1] == 't') ? MAP_THUMB 12081 : MAP_DATA); 12082 return true; 12083 } 12084 12085 return false; 12086 } 12087 12088 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 12089 Returns nonzero if *MAP_TYPE was set. */ 12090 12091 static int 12092 get_map_sym_type (struct disassemble_info *info, 12093 int n, 12094 enum map_type *map_type) 12095 { 12096 /* If the symbol is in a different section, ignore it. */ 12097 if (info->section != NULL && info->section != info->symtab[n]->section) 12098 return false; 12099 12100 return is_mapping_symbol (info, n, map_type); 12101 } 12102 12103 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 12104 Returns nonzero if *MAP_TYPE was set. */ 12105 12106 static int 12107 get_sym_code_type (struct disassemble_info *info, 12108 int n, 12109 enum map_type *map_type) 12110 { 12111 elf_symbol_type *es; 12112 unsigned int type; 12113 asymbol * sym; 12114 12115 /* If the symbol is in a different section, ignore it. */ 12116 if (info->section != NULL && info->section != info->symtab[n]->section) 12117 return false; 12118 12119 /* PR 30230: Reject non-ELF symbols, eg synthetic ones. */ 12120 sym = info->symtab[n]; 12121 if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour) 12122 return false; 12123 12124 es = (elf_symbol_type *) sym; 12125 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12126 12127 /* If the symbol has function type then use that. */ 12128 if (type == STT_FUNC || type == STT_GNU_IFUNC) 12129 { 12130 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12131 == ST_BRANCH_TO_THUMB) 12132 *map_type = MAP_THUMB; 12133 else 12134 *map_type = MAP_ARM; 12135 return true; 12136 } 12137 12138 return false; 12139 } 12140 12141 /* Search the mapping symbol state for instruction at pc. This is only 12142 applicable for elf target. 12143 12144 There is an assumption Here, info->private_data contains the correct AND 12145 up-to-date information about current scan process. The information will be 12146 used to speed this search process. 12147 12148 Return TRUE if the mapping state can be determined, and map_symbol 12149 will be updated accordingly. Otherwise, return FALSE. */ 12150 12151 static bool 12152 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 12153 enum map_type *map_symbol) 12154 { 12155 bfd_vma addr, section_vma = 0; 12156 int n, last_sym = -1; 12157 bool found = false; 12158 bool can_use_search_opt_p = false; 12159 12160 /* Sanity check. */ 12161 if (info == NULL) 12162 return false; 12163 12164 /* Default to DATA. A text section is required by the ABI to contain an 12165 INSN mapping symbol at the start. A data section has no such 12166 requirement, hence if no mapping symbol is found the section must 12167 contain only data. This however isn't very useful if the user has 12168 fully stripped the binaries. If this is the case use the section 12169 attributes to determine the default. If we have no section default to 12170 INSN as well, as we may be disassembling some raw bytes on a baremetal 12171 HEX file or similar. */ 12172 enum map_type type = MAP_DATA; 12173 if ((info->section && info->section->flags & SEC_CODE) || !info->section) 12174 type = MAP_ARM; 12175 struct arm_private_data *private_data; 12176 12177 if (info->private_data == NULL || info->symtab == NULL 12178 || info->symtab_size == 0 12179 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 12180 return false; 12181 12182 private_data = info->private_data; 12183 12184 /* First, look for mapping symbols. */ 12185 if (pc <= private_data->last_mapping_addr) 12186 private_data->last_mapping_sym = -1; 12187 12188 /* Start scanning at the start of the function, or wherever 12189 we finished last time. */ 12190 n = info->symtab_pos + 1; 12191 12192 /* If the last stop offset is different from the current one it means we 12193 are disassembling a different glob of bytes. As such the optimization 12194 would not be safe and we should start over. */ 12195 can_use_search_opt_p 12196 = (private_data->last_mapping_sym >= 0 12197 && info->stop_offset == private_data->last_stop_offset); 12198 12199 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 12200 n = private_data->last_mapping_sym; 12201 12202 /* Look down while we haven't passed the location being disassembled. 12203 The reason for this is that there's no defined order between a symbol 12204 and an mapping symbol that may be at the same address. We may have to 12205 look at least one position ahead. */ 12206 for (; n < info->symtab_size; n++) 12207 { 12208 addr = bfd_asymbol_value (info->symtab[n]); 12209 if (addr > pc) 12210 break; 12211 if (get_map_sym_type (info, n, &type)) 12212 { 12213 last_sym = n; 12214 found = true; 12215 } 12216 } 12217 12218 if (!found) 12219 { 12220 n = info->symtab_pos; 12221 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 12222 n = private_data->last_mapping_sym; 12223 12224 /* No mapping symbol found at this address. Look backwards 12225 for a preceeding one, but don't go pass the section start 12226 otherwise a data section with no mapping symbol can pick up 12227 a text mapping symbol of a preceeding section. The documentation 12228 says section can be NULL, in which case we will seek up all the 12229 way to the top. */ 12230 if (info->section) 12231 section_vma = info->section->vma; 12232 12233 for (; n >= 0; n--) 12234 { 12235 addr = bfd_asymbol_value (info->symtab[n]); 12236 if (addr < section_vma) 12237 break; 12238 12239 if (get_map_sym_type (info, n, &type)) 12240 { 12241 last_sym = n; 12242 found = true; 12243 break; 12244 } 12245 } 12246 } 12247 12248 /* If no mapping symbol was found, try looking up without a mapping 12249 symbol. This is done by walking up from the current PC to the nearest 12250 symbol. We don't actually have to loop here since symtab_pos will 12251 contain the nearest symbol already. */ 12252 if (!found) 12253 { 12254 n = info->symtab_pos; 12255 if (n >= 0 && get_sym_code_type (info, n, &type)) 12256 { 12257 last_sym = n; 12258 found = true; 12259 } 12260 } 12261 12262 private_data->last_mapping_sym = last_sym; 12263 private_data->last_type = type; 12264 private_data->last_stop_offset = info->stop_offset; 12265 12266 *map_symbol = type; 12267 return found; 12268 } 12269 12270 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 12271 of the supplied arm_feature_set structure with bitmasks indicating 12272 the supported base architectures and coprocessor extensions. 12273 12274 FIXME: This could more efficiently implemented as a constant array, 12275 although it would also be less robust. */ 12276 12277 static void 12278 select_arm_features (unsigned long mach, 12279 arm_feature_set * features) 12280 { 12281 arm_feature_set arch_fset; 12282 const arm_feature_set fpu_any = FPU_ANY; 12283 12284 #undef ARM_SET_FEATURES 12285 #define ARM_SET_FEATURES(FSET) \ 12286 { \ 12287 const arm_feature_set fset = FSET; \ 12288 arch_fset = fset; \ 12289 } 12290 12291 /* When several architecture versions share the same bfd_mach_arm_XXX value 12292 the most featureful is chosen. */ 12293 switch (mach) 12294 { 12295 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 12296 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 12297 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 12298 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 12299 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 12300 case bfd_mach_arm_ep9312: 12301 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 12302 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 12303 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 12304 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 12305 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 12306 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 12307 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 12308 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 12309 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 12310 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 12311 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 12312 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 12313 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 12314 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 12315 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 12316 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 12317 case bfd_mach_arm_8: 12318 { 12319 /* Add bits for extensions that Armv8.6-A recognizes. */ 12320 arm_feature_set armv8_6_ext_fset 12321 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 12322 ARM_SET_FEATURES (ARM_ARCH_V8_6A); 12323 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); 12324 break; 12325 } 12326 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R_CRC); break; 12327 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 12328 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 12329 case bfd_mach_arm_8_1M_MAIN: 12330 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); 12331 arm_feature_set mve_all 12332 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP); 12333 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all); 12334 force_thumb = 1; 12335 break; 12336 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break; 12337 /* If the machine type is unknown allow all architecture types and all 12338 extensions, with the exception of MVE as that clashes with NEON. */ 12339 case bfd_mach_arm_unknown: 12340 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN); 12341 break; 12342 default: 12343 abort (); 12344 } 12345 #undef ARM_SET_FEATURES 12346 12347 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 12348 and thus on bfd_mach_arm_XXX value. Therefore for a given 12349 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 12350 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 12351 } 12352 12353 12354 /* NOTE: There are no checks in these routines that 12355 the relevant number of data bytes exist. */ 12356 12357 static int 12358 print_insn (bfd_vma pc, struct disassemble_info *info, bool little) 12359 { 12360 unsigned char b[4]; 12361 unsigned long given; 12362 int status; 12363 int is_thumb = false; 12364 int is_data = false; 12365 int little_code; 12366 unsigned int size = 4; 12367 void (*printer) (bfd_vma, struct disassemble_info *, long); 12368 bool found = false; 12369 struct arm_private_data *private_data; 12370 12371 /* Clear instruction information field. */ 12372 info->insn_info_valid = 0; 12373 info->branch_delay_insns = 0; 12374 info->data_size = 0; 12375 info->insn_type = dis_noninsn; 12376 info->target = 0; 12377 info->target2 = 0; 12378 12379 if (info->disassembler_options) 12380 { 12381 parse_arm_disassembler_options (info->disassembler_options); 12382 12383 /* To avoid repeated parsing of these options, we remove them here. */ 12384 info->disassembler_options = NULL; 12385 } 12386 12387 /* PR 10288: Control which instructions will be disassembled. */ 12388 if (info->private_data == NULL) 12389 { 12390 static struct arm_private_data private; 12391 12392 if (info->flavour != bfd_target_elf_flavour 12393 && (info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 12394 /* If the user did not use the -m command line switch then default to 12395 disassembling all types of ARM instruction. 12396 12397 If this is an arm elf target, build attributes will be used to 12398 determine info->mach, which enable us to be more accurate when 12399 disassembling since we know what the target architecture version is. 12400 For any other target see the comment below: 12401 12402 The info->mach value has to be ignored as this will be based on 12403 the default archictecture for the target and/or hints in the notes 12404 section, but it will never be greater than the current largest arm 12405 machine value (iWMMXt2), which is only equivalent to the V5TE 12406 architecture. ARM architectures have advanced beyond the machine 12407 value encoding, and these newer architectures would be ignored if 12408 the machine value was used. 12409 12410 Ie the -m switch is used to restrict which instructions will be 12411 disassembled. If it is necessary to use the -m switch to tell 12412 objdump that an ARM binary is being disassembled, eg because the 12413 input is a raw binary file, but it is also desired to disassemble 12414 all ARM instructions then use "-marm". This will select the 12415 "unknown" arm architecture which is compatible with any ARM 12416 instruction. */ 12417 info->mach = bfd_mach_arm_unknown; 12418 12419 /* Compute the architecture bitmask from the machine number. 12420 Note: This assumes that the machine number will not change 12421 during disassembly.... */ 12422 select_arm_features (info->mach, & private.features); 12423 12424 private.last_mapping_sym = -1; 12425 private.last_mapping_addr = 0; 12426 private.last_stop_offset = 0; 12427 12428 info->private_data = & private; 12429 } 12430 12431 private_data = info->private_data; 12432 12433 /* Decide if our code is going to be little-endian, despite what the 12434 function argument might say. */ 12435 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 12436 12437 /* For ELF, consult the symbol table to determine what kind of code 12438 or data we have. */ 12439 if (info->symtab_size != 0 12440 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 12441 { 12442 bfd_vma addr; 12443 int n; 12444 int last_sym = -1; 12445 enum map_type type = MAP_ARM; 12446 12447 found = mapping_symbol_for_insn (pc, info, &type); 12448 last_sym = private_data->last_mapping_sym; 12449 12450 is_thumb = (private_data->last_type == MAP_THUMB); 12451 is_data = (private_data->last_type == MAP_DATA); 12452 12453 /* Look a little bit ahead to see if we should print out 12454 two or four bytes of data. If there's a symbol, 12455 mapping or otherwise, after two bytes then don't 12456 print more. */ 12457 if (is_data) 12458 { 12459 size = 4 - (pc & 3); 12460 for (n = last_sym + 1; n < info->symtab_size; n++) 12461 { 12462 addr = bfd_asymbol_value (info->symtab[n]); 12463 if (addr > pc 12464 && (info->section == NULL 12465 || info->section == info->symtab[n]->section)) 12466 { 12467 if (addr - pc < size) 12468 size = addr - pc; 12469 break; 12470 } 12471 } 12472 /* If the next symbol is after three bytes, we need to 12473 print only part of the data, so that we can use either 12474 .byte or .short. */ 12475 if (size == 3) 12476 size = (pc & 1) ? 1 : 2; 12477 } 12478 } 12479 12480 if (info->symbols != NULL) 12481 { 12482 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 12483 { 12484 coff_symbol_type * cs; 12485 12486 cs = coffsymbol (*info->symbols); 12487 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 12488 || cs->native->u.syment.n_sclass == C_THUMBSTAT 12489 || cs->native->u.syment.n_sclass == C_THUMBLABEL 12490 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 12491 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 12492 } 12493 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 12494 && !found) 12495 { 12496 /* If no mapping symbol has been found then fall back to the type 12497 of the function symbol. */ 12498 elf_symbol_type * es; 12499 unsigned int type; 12500 12501 es = *(elf_symbol_type **)(info->symbols); 12502 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12503 12504 is_thumb = 12505 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12506 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 12507 } 12508 else if (bfd_asymbol_flavour (*info->symbols) 12509 == bfd_target_mach_o_flavour) 12510 { 12511 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 12512 12513 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 12514 } 12515 } 12516 12517 if (force_thumb) 12518 is_thumb = true; 12519 12520 if (is_data) 12521 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12522 else 12523 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12524 12525 info->bytes_per_line = 4; 12526 12527 /* PR 10263: Disassemble data if requested to do so by the user. */ 12528 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 12529 { 12530 int i; 12531 12532 /* Size was already set above. */ 12533 info->bytes_per_chunk = size; 12534 printer = print_insn_data; 12535 12536 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 12537 given = 0; 12538 if (little) 12539 for (i = size - 1; i >= 0; i--) 12540 given = b[i] | (given << 8); 12541 else 12542 for (i = 0; i < (int) size; i++) 12543 given = b[i] | (given << 8); 12544 } 12545 else if (!is_thumb) 12546 { 12547 /* In ARM mode endianness is a straightforward issue: the instruction 12548 is four bytes long and is either ordered 0123 or 3210. */ 12549 printer = print_insn_arm; 12550 info->bytes_per_chunk = 4; 12551 size = 4; 12552 12553 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 12554 if (little_code) 12555 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24); 12556 else 12557 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24); 12558 } 12559 else 12560 { 12561 /* In Thumb mode we have the additional wrinkle of two 12562 instruction lengths. Fortunately, the bits that determine 12563 the length of the current instruction are always to be found 12564 in the first two bytes. */ 12565 printer = print_insn_thumb16; 12566 info->bytes_per_chunk = 2; 12567 size = 2; 12568 12569 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 12570 if (little_code) 12571 given = (b[0]) | (b[1] << 8); 12572 else 12573 given = (b[1]) | (b[0] << 8); 12574 12575 if (!status) 12576 { 12577 /* These bit patterns signal a four-byte Thumb 12578 instruction. */ 12579 if ((given & 0xF800) == 0xF800 12580 || (given & 0xF800) == 0xF000 12581 || (given & 0xF800) == 0xE800) 12582 { 12583 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 12584 if (little_code) 12585 given = (b[0]) | (b[1] << 8) | (given << 16); 12586 else 12587 given = (b[1]) | (b[0] << 8) | (given << 16); 12588 12589 printer = print_insn_thumb32; 12590 size = 4; 12591 } 12592 } 12593 12594 if (ifthen_address != pc) 12595 find_ifthen_state (pc, info, little_code); 12596 12597 if (ifthen_state) 12598 { 12599 if ((ifthen_state & 0xf) == 0x8) 12600 ifthen_next_state = 0; 12601 else 12602 ifthen_next_state = (ifthen_state & 0xe0) 12603 | ((ifthen_state & 0xf) << 1); 12604 } 12605 } 12606 12607 if (status) 12608 { 12609 info->memory_error_func (status, pc, info); 12610 return -1; 12611 } 12612 if (info->flags & INSN_HAS_RELOC) 12613 /* If the instruction has a reloc associated with it, then 12614 the offset field in the instruction will actually be the 12615 addend for the reloc. (We are using REL type relocs). 12616 In such cases, we can ignore the pc when computing 12617 addresses, since the addend is not currently pc-relative. */ 12618 pc = 0; 12619 12620 printer (pc, info, given); 12621 12622 if (is_thumb) 12623 { 12624 ifthen_state = ifthen_next_state; 12625 ifthen_address += size; 12626 } 12627 return size; 12628 } 12629 12630 int 12631 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 12632 { 12633 /* Detect BE8-ness and record it in the disassembler info. */ 12634 if (info->flavour == bfd_target_elf_flavour 12635 && info->section != NULL 12636 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 12637 info->endian_code = BFD_ENDIAN_LITTLE; 12638 12639 return print_insn (pc, info, false); 12640 } 12641 12642 int 12643 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 12644 { 12645 return print_insn (pc, info, true); 12646 } 12647 12648 const disasm_options_and_args_t * 12649 disassembler_options_arm (void) 12650 { 12651 static disasm_options_and_args_t *opts_and_args; 12652 12653 if (opts_and_args == NULL) 12654 { 12655 disasm_options_t *opts; 12656 unsigned int i; 12657 12658 opts_and_args = XNEW (disasm_options_and_args_t); 12659 opts_and_args->args = NULL; 12660 12661 opts = &opts_and_args->options; 12662 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12663 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12664 opts->arg = NULL; 12665 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12666 { 12667 opts->name[i] = regnames[i].name; 12668 if (regnames[i].description != NULL) 12669 opts->description[i] = _(regnames[i].description); 12670 else 12671 opts->description[i] = NULL; 12672 } 12673 /* The array we return must be NULL terminated. */ 12674 opts->name[i] = NULL; 12675 opts->description[i] = NULL; 12676 } 12677 12678 return opts_and_args; 12679 } 12680 12681 void 12682 print_arm_disassembler_options (FILE *stream) 12683 { 12684 unsigned int i, max_len = 0; 12685 fprintf (stream, _("\n\ 12686 The following ARM specific disassembler options are supported for use with\n\ 12687 the -M switch:\n")); 12688 12689 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12690 { 12691 unsigned int len = strlen (regnames[i].name); 12692 if (max_len < len) 12693 max_len = len; 12694 } 12695 12696 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 12697 fprintf (stream, " %s%*c %s\n", 12698 regnames[i].name, 12699 (int)(max_len - strlen (regnames[i].name)), ' ', 12700 _(regnames[i].description)); 12701 } 12702
Indexes created Thu Apr 30 00:23:01 UTC 2026