arm-dis.c revision 1.6
1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2019 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 25 #include "disassemble.h" 26 #include "opcode/arm.h" 27 #include "opintl.h" 28 #include "safe-ctype.h" 29 #include "libiberty.h" 30 #include "floatformat.h" 31 32 /* FIXME: This shouldn't be done here. */ 33 #include "coff/internal.h" 34 #include "libcoff.h" 35 #include "bfd.h" 36 #include "elf-bfd.h" 37 #include "elf/internal.h" 38 #include "elf/arm.h" 39 #include "mach-o.h" 40 41 /* FIXME: Belongs in global header. */ 42 #ifndef strneq 43 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 44 #endif 45 46 /* Cached mapping symbol state. */ 47 enum map_type 48 { 49 MAP_ARM, 50 MAP_THUMB, 51 MAP_DATA 52 }; 53 54 struct arm_private_data 55 { 56 /* The features to use when disassembling optional instructions. */ 57 arm_feature_set features; 58 59 /* Whether any mapping symbols are present in the provided symbol 60 table. -1 if we do not know yet, otherwise 0 or 1. */ 61 int has_mapping_symbols; 62 63 /* Track the last type (although this doesn't seem to be useful) */ 64 enum map_type last_type; 65 66 /* Tracking symbol table information */ 67 int last_mapping_sym; 68 bfd_vma last_mapping_addr; 69 }; 70 71 struct opcode32 72 { 73 arm_feature_set arch; /* Architecture defining this insn. */ 74 unsigned long value; /* If arch is 0 then value is a sentinel. */ 75 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 76 const char * assembler; /* How to disassemble this insn. */ 77 }; 78 79 struct opcode16 80 { 81 arm_feature_set arch; /* Architecture defining this insn. */ 82 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 83 const char *assembler; /* How to disassemble this insn. */ 84 }; 85 86 /* print_insn_coprocessor recognizes the following format control codes: 87 88 %% % 89 90 %c print condition code (always bits 28-31 in ARM mode) 91 %q print shifter argument 92 %u print condition code (unconditional in ARM mode, 93 UNPREDICTABLE if not AL in Thumb) 94 %A print address for ldc/stc/ldf/stf instruction 95 %B print vstm/vldm register list 96 %I print cirrus signed shift immediate: bits 0..3|4..6 97 %F print the COUNT field of a LFM/SFM instruction. 98 %P print floating point precision in arithmetic insn 99 %Q print floating point precision in ldf/stf insn 100 %R print floating point rounding mode 101 102 %<bitfield>c print as a condition code (for vsel) 103 %<bitfield>r print as an ARM register 104 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 105 %<bitfield>ru as %<>r but each u register must be unique. 106 %<bitfield>d print the bitfield in decimal 107 %<bitfield>k print immediate for VFPv3 conversion instruction 108 %<bitfield>x print the bitfield in hex 109 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 110 %<bitfield>f print a floating point constant if >7 else a 111 floating point register 112 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 113 %<bitfield>g print as an iWMMXt 64-bit register 114 %<bitfield>G print as an iWMMXt general purpose or control register 115 %<bitfield>D print as a NEON D register 116 %<bitfield>Q print as a NEON Q register 117 %<bitfield>V print as a NEON D or Q register 118 %<bitfield>E print a quarter-float immediate value 119 120 %y<code> print a single precision VFP reg. 121 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 122 %z<code> print a double precision VFP reg 123 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 124 125 %<bitfield>'c print specified char iff bitfield is all ones 126 %<bitfield>`c print specified char iff bitfield is all zeroes 127 %<bitfield>?ab... select from array of values in big endian order 128 129 %L print as an iWMMXt N/M width field. 130 %Z print the Immediate of a WSHUFH instruction. 131 %l like 'A' except use byte offsets for 'B' & 'H' 132 versions. 133 %i print 5-bit immediate in bits 8,3..0 134 (print "32" when 0) 135 %r print register offset address for wldt/wstr instruction. */ 136 137 enum opcode_sentinel_enum 138 { 139 SENTINEL_IWMMXT_START = 1, 140 SENTINEL_IWMMXT_END, 141 SENTINEL_GENERIC_START 142 } opcode_sentinels; 143 144 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 145 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x" 146 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x" 147 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 148 149 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 150 151 static const struct opcode32 coprocessor_opcodes[] = 152 { 153 /* XScale instructions. */ 154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 155 0x0e200010, 0x0fff0ff0, 156 "mia%c\tacc0, %0-3r, %12-15r"}, 157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 158 0x0e280010, 0x0fff0ff0, 159 "miaph%c\tacc0, %0-3r, %12-15r"}, 160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 161 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 163 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 165 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 166 167 /* Intel Wireless MMX technology instructions. */ 168 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 169 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 170 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 172 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 174 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 176 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 178 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 180 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 182 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 184 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 186 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 188 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 190 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 192 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 194 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 196 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 198 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 200 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 202 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 204 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 206 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 208 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 210 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 212 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 214 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 216 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 218 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 220 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 222 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 224 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 226 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 228 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 230 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 232 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 234 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 236 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 238 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 240 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 242 0x0e800120, 0x0f800ff0, 243 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 245 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 247 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 249 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 251 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 253 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 255 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 257 0x0e8000a0, 0x0f800ff0, 258 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 260 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 262 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 264 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 266 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 268 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 270 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 272 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 274 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 276 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 278 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 280 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 282 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 284 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 286 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 288 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 290 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 292 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 294 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 296 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 298 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 300 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 302 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 304 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 306 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 308 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 310 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 312 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 314 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 316 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 318 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 319 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 320 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 321 {ARM_FEATURE_CORE_LOW (0), 322 SENTINEL_IWMMXT_END, 0, "" }, 323 324 /* Floating point coprocessor (FPA) instructions. */ 325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 326 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 328 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 330 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 332 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 334 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 336 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 338 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 340 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 342 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 344 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 346 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 348 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 350 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 352 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 354 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 356 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 358 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 360 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 362 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 364 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 366 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 368 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 370 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 372 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 374 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 376 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 378 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 380 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 382 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 384 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 386 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 388 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 390 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 392 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 394 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 396 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 398 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 400 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 402 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 404 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 406 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 408 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 409 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 410 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 411 412 /* ARMv8-M Mainline Security Extensions instructions. */ 413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 414 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 416 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 417 418 /* Register load/store. */ 419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 420 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 422 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 424 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 426 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 428 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 430 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 432 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 434 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 436 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 438 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 440 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 442 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 444 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 446 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 448 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 450 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 451 452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 453 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 455 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 457 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 458 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 459 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 460 461 /* Data transfer between ARM and NEON registers. */ 462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 463 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 465 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 467 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 469 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 471 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 473 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 475 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 477 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 479 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 481 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 483 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 485 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 487 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 489 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 490 /* Half-precision conversion instructions. */ 491 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 492 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 494 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 496 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 498 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 499 500 /* Floating point coprocessor (VFP) instructions. */ 501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 502 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 504 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 506 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 508 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 510 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 512 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 514 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 516 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 518 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 520 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 522 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 524 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 526 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 528 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 530 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 532 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 534 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 536 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 538 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 540 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 542 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 544 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 546 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 548 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 550 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 552 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 554 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 556 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 558 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 560 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 562 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 564 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 566 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 568 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 570 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 572 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 574 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 576 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 578 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 580 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 582 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 584 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 586 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 588 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 590 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 592 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 594 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 596 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 598 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 600 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 602 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 604 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 606 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 608 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 610 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 612 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 614 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 616 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 618 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 620 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 622 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 624 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 626 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 627 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 628 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 629 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 630 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 631 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 632 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 633 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 634 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 635 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 636 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 637 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 638 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 639 640 /* Cirrus coprocessor instructions. */ 641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 642 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 644 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 646 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 648 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 650 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 652 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 654 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 656 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 658 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 660 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 662 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 664 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 666 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 668 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 670 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 672 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 674 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 676 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 678 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 680 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 682 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 684 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 686 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 688 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 690 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 692 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 694 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 696 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 698 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 700 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 702 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 704 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 706 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 708 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 710 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 712 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 714 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 716 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 718 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 720 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 722 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 724 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 726 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 728 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 730 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 732 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 734 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 736 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 738 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 740 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 742 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 744 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 746 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 748 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 750 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 752 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 754 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 756 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 758 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 760 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 762 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 764 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 766 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 768 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 770 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 772 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 774 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 776 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 778 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 780 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 782 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 784 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 786 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 788 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 790 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 792 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 794 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 796 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 798 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 800 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 802 0x0e000600, 0x0ff00f10, 803 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 805 0x0e100600, 0x0ff00f10, 806 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 808 0x0e200600, 0x0ff00f10, 809 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 810 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 811 0x0e300600, 0x0ff00f10, 812 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 813 814 /* VFP Fused multiply add instructions. */ 815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 816 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 818 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 819 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 820 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 822 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 824 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 826 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 827 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 828 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 830 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 831 832 /* FP v5. */ 833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 834 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 836 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 838 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 840 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 842 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 844 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 845 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 846 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 847 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 848 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 849 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 850 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 851 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 852 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 853 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 854 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 855 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 856 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 857 858 /* Generic coprocessor instructions. */ 859 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 861 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 863 0x0c500000, 0x0ff00000, 864 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 866 0x0e000000, 0x0f000010, 867 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 869 0x0e10f010, 0x0f10f010, 870 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 872 0x0e100010, 0x0f100010, 873 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 875 0x0e000010, 0x0f100010, 876 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 878 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 880 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 881 882 /* V6 coprocessor instructions. */ 883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 884 0xfc500000, 0xfff00000, 885 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 887 0xfc400000, 0xfff00000, 888 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 889 890 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 891 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 892 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 894 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 896 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 898 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 900 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 902 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 904 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 906 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, 907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 908 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 910 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, 911 912 /* Dot Product instructions in the space of coprocessor 13. */ 913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 914 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 916 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, 917 918 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 920 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 922 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 924 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 926 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 928 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 930 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 932 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 934 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 935 936 /* V5 coprocessor instructions. */ 937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 938 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 940 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 942 0xfe000000, 0xff000010, 943 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 945 0xfe000010, 0xff100010, 946 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 948 0xfe100010, 0xff100010, 949 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 950 951 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 952 cp_num: bit <11:8> == 0b1001. 953 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 955 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 957 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 959 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 961 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 963 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 965 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 967 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 969 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 971 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 973 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 975 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 977 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 979 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 981 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 983 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 985 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 987 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 989 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 991 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 993 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 995 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 997 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 999 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1000 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1001 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1003 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 1004 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1005 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1006 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1007 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1009 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1010 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1011 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1012 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1013 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1015 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1016 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1017 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1018 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1019 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1021 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1022 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1023 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1024 1025 /* ARMv8.3 javascript conversion instruction. */ 1026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1027 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1028 1029 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1030 }; 1031 1032 /* Neon opcode table: This does not encode the top byte -- that is 1033 checked by the print_insn_neon routine, as it depends on whether we are 1034 doing thumb32 or arm32 disassembly. */ 1035 1036 /* print_insn_neon recognizes the following format control codes: 1037 1038 %% % 1039 1040 %c print condition code 1041 %u print condition code (unconditional in ARM mode, 1042 UNPREDICTABLE if not AL in Thumb) 1043 %A print v{st,ld}[1234] operands 1044 %B print v{st,ld}[1234] any one operands 1045 %C print v{st,ld}[1234] single->all operands 1046 %D print scalar 1047 %E print vmov, vmvn, vorr, vbic encoded constant 1048 %F print vtbl,vtbx register list 1049 1050 %<bitfield>r print as an ARM register 1051 %<bitfield>d print the bitfield in decimal 1052 %<bitfield>e print the 2^N - bitfield in decimal 1053 %<bitfield>D print as a NEON D register 1054 %<bitfield>Q print as a NEON Q register 1055 %<bitfield>R print as a NEON D or Q register 1056 %<bitfield>Sn print byte scaled width limited by n 1057 %<bitfield>Tn print short scaled width limited by n 1058 %<bitfield>Un print long scaled width limited by n 1059 1060 %<bitfield>'c print specified char iff bitfield is all ones 1061 %<bitfield>`c print specified char iff bitfield is all zeroes 1062 %<bitfield>?ab... select from array of values in big endian order. */ 1063 1064 static const struct opcode32 neon_opcodes[] = 1065 { 1066 /* Extract. */ 1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1068 0xf2b00840, 0xffb00850, 1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1071 0xf2b00000, 0xffb00810, 1072 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1073 1074 /* Move data element to all lanes. */ 1075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1076 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1078 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1079 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1080 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1081 1082 /* Table lookup. */ 1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1084 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1086 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1087 1088 /* Half-precision conversions. */ 1089 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1090 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1091 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1092 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1093 1094 /* NEON fused multiply add instructions. */ 1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1096 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1098 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1100 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1101 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1102 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1103 1104 /* Two registers, miscellaneous. */ 1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1106 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1108 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1110 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1112 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1113 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1114 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1115 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1116 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1117 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1118 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1119 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1120 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1121 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1122 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1123 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1124 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1125 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1126 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1128 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1130 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1132 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1134 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1136 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1138 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1140 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1142 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1144 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1146 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1148 0xf3b20300, 0xffb30fd0, 1149 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1151 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1153 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1155 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1157 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1159 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1161 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1163 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1165 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1167 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1169 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1171 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1173 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1175 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1177 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1179 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1181 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1183 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1185 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1187 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1189 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1191 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1193 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1195 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1197 0xf3bb0600, 0xffbf0e10, 1198 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1200 0xf3b70600, 0xffbf0e10, 1201 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1202 1203 /* Three registers of the same length. */ 1204 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1205 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1206 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1207 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1208 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1209 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1210 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1211 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1212 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1213 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1214 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1215 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1216 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1217 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1219 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1220 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1221 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1223 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1225 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1227 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1229 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1231 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1233 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1235 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1237 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1239 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1241 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1243 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1245 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1247 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1249 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1251 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1253 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1255 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1257 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1259 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1261 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1263 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1265 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1267 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1269 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1271 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1273 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1275 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1277 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1279 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1281 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1283 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1285 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1287 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1289 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1291 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1293 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1295 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1297 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1299 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1301 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1303 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1305 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1307 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1309 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1311 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1313 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1315 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1317 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1319 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1321 0xf2000b00, 0xff800f10, 1322 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1324 0xf2000b10, 0xff800f10, 1325 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1327 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1329 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1331 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1333 0xf3000b00, 0xff800f10, 1334 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1336 0xf2000000, 0xfe800f10, 1337 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1339 0xf2000010, 0xfe800f10, 1340 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1342 0xf2000100, 0xfe800f10, 1343 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1345 0xf2000200, 0xfe800f10, 1346 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1348 0xf2000210, 0xfe800f10, 1349 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1351 0xf2000300, 0xfe800f10, 1352 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1354 0xf2000310, 0xfe800f10, 1355 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1357 0xf2000400, 0xfe800f10, 1358 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1360 0xf2000410, 0xfe800f10, 1361 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1363 0xf2000500, 0xfe800f10, 1364 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1366 0xf2000510, 0xfe800f10, 1367 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1369 0xf2000600, 0xfe800f10, 1370 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1372 0xf2000610, 0xfe800f10, 1373 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1375 0xf2000700, 0xfe800f10, 1376 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1378 0xf2000710, 0xfe800f10, 1379 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1381 0xf2000910, 0xfe800f10, 1382 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf2000a00, 0xfe800f10, 1385 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1387 0xf2000a10, 0xfe800f10, 1388 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1390 0xf3000b10, 0xff800f10, 1391 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1393 0xf3000c10, 0xff800f10, 1394 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1395 1396 /* One register and an immediate value. */ 1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1398 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1400 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1402 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1404 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1406 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1408 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1410 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1412 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1414 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1416 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1418 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1420 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1422 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1423 1424 /* Two registers and a shift amount. */ 1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1426 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1428 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1430 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1432 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1434 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1436 0xf2880950, 0xfeb80fd0, 1437 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1439 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1441 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1443 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1445 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1447 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1449 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1451 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1453 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1455 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1457 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1459 0xf2900950, 0xfeb00fd0, 1460 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1462 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1464 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1466 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1468 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1470 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1472 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1474 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1476 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1478 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1480 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1482 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1484 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1486 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1488 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1490 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1492 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1494 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1496 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1498 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1500 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1502 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1504 0xf2a00950, 0xfea00fd0, 1505 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1507 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1509 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1511 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1517 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1519 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1521 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1523 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1525 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1527 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1529 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1531 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1533 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1535 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1537 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1539 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1541 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1543 0xf2a00e10, 0xfea00e90, 1544 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1546 0xf2a00c10, 0xfea00e90, 1547 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 1548 1549 /* Three registers of different lengths. */ 1550 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1551 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1553 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2800400, 0xff800f50, 1556 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2800600, 0xff800f50, 1559 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1561 0xf2800900, 0xff800f50, 1562 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2800b00, 0xff800f50, 1565 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf2800d00, 0xff800f50, 1568 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1570 0xf3800400, 0xff800f50, 1571 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1573 0xf3800600, 0xff800f50, 1574 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2800000, 0xfe800f50, 1577 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1579 0xf2800100, 0xfe800f50, 1580 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1582 0xf2800200, 0xfe800f50, 1583 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1585 0xf2800300, 0xfe800f50, 1586 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1588 0xf2800500, 0xfe800f50, 1589 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2800700, 0xfe800f50, 1592 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1594 0xf2800800, 0xfe800f50, 1595 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf2800a00, 0xfe800f50, 1598 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1600 0xf2800c00, 0xfe800f50, 1601 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1602 1603 /* Two registers and a scalar. */ 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1607 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1608 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1609 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1613 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1615 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1616 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1617 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1619 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1621 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1624 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1625 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1627 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1629 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1631 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1633 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1635 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1636 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1637 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1639 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1641 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1642 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1643 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1645 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1647 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1648 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1649 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1651 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1653 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf2800240, 0xfe800f50, 1656 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1658 0xf2800640, 0xfe800f50, 1659 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1661 0xf2800a40, 0xfe800f50, 1662 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1664 0xf2800e40, 0xff800f50, 1665 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1667 0xf2800f40, 0xff800f50, 1668 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1670 0xf3800e40, 0xff800f50, 1671 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1673 0xf3800f40, 0xff800f50, 1674 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1675 }, 1676 1677 /* Element and structure load/store. */ 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1679 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1681 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1683 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1685 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1687 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1689 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1691 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1693 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1695 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1697 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1699 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1701 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1703 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1705 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1707 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1709 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1711 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1713 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1715 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1716 1717 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1718 }; 1719 1720 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 1721 ordered: they must be searched linearly from the top to obtain a correct 1722 match. */ 1723 1724 /* print_insn_arm recognizes the following format control codes: 1725 1726 %% % 1727 1728 %a print address for ldr/str instruction 1729 %s print address for ldr/str halfword/signextend instruction 1730 %S like %s but allow UNPREDICTABLE addressing 1731 %b print branch destination 1732 %c print condition code (always bits 28-31) 1733 %m print register mask for ldm/stm instruction 1734 %o print operand2 (immediate or register + shift) 1735 %p print 'p' iff bits 12-15 are 15 1736 %t print 't' iff bit 21 set and bit 24 clear 1737 %B print arm BLX(1) destination 1738 %C print the PSR sub type. 1739 %U print barrier type. 1740 %P print address for pli instruction. 1741 1742 %<bitfield>r print as an ARM register 1743 %<bitfield>T print as an ARM register + 1 1744 %<bitfield>R as %r but r15 is UNPREDICTABLE 1745 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 1746 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 1747 %<bitfield>d print the bitfield in decimal 1748 %<bitfield>W print the bitfield plus one in decimal 1749 %<bitfield>x print the bitfield in hex 1750 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 1751 1752 %<bitfield>'c print specified char iff bitfield is all ones 1753 %<bitfield>`c print specified char iff bitfield is all zeroes 1754 %<bitfield>?ab... select from array of values in big endian order 1755 1756 %e print arm SMI operand (bits 0..7,8..19). 1757 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 1758 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 1759 %R print the SPSR/CPSR or banked register of an MRS. */ 1760 1761 static const struct opcode32 arm_opcodes[] = 1762 { 1763 /* ARM instructions. */ 1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1765 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1767 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 1768 1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 1770 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1772 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1774 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 1776 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1778 0x00800090, 0x0fa000f0, 1779 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1781 0x00a00090, 0x0fa000f0, 1782 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1783 1784 /* V8.2 RAS extension instructions. */ 1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 1786 0xe320f010, 0xffffffff, "esb"}, 1787 1788 /* V8 instructions. */ 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1790 0x0320f005, 0x0fffffff, "sevl"}, 1791 /* Defined in V8 but is in NOP space so available to all arch. */ 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1793 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 1794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 1795 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 1796 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1797 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1799 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1801 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1803 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1805 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 1806 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1807 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 1808 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1809 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 1810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1811 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1813 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 1814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1815 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1817 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 1818 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1819 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 1820 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1821 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 1822 /* CRC32 instructions. */ 1823 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1824 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 1825 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1826 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 1827 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1828 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 1829 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1830 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 1831 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1832 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 1833 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1834 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 1835 1836 /* Privileged Access Never extension instructions. */ 1837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 1838 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 1839 1840 /* Virtualization Extension instructions. */ 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 1843 1844 /* Integer Divide Extension instructions. */ 1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1846 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1848 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 1849 1850 /* MP Extension instructions. */ 1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 1852 1853 /* Speculation Barriers. */ 1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 1857 1858 /* V7 instructions. */ 1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 1867 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 1868 1869 /* ARM V6T2 instructions. */ 1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1871 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1873 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1875 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1877 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 1878 1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1880 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1882 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 1883 1884 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1885 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 1886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1887 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1889 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1891 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 1892 1893 /* ARM Security extension instructions. */ 1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 1895 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 1896 1897 /* ARM V6K instructions. */ 1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1899 0xf57ff01f, 0xffffffff, "clrex"}, 1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1901 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1903 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1905 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1907 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1909 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1911 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 1912 1913 /* ARMv8.5-A instructions. */ 1914 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 1915 1916 /* ARM V6K NOP hints. */ 1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1918 0x0320f001, 0x0fffffff, "yield%c"}, 1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1920 0x0320f002, 0x0fffffff, "wfe%c"}, 1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1922 0x0320f003, 0x0fffffff, "wfi%c"}, 1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1924 0x0320f004, 0x0fffffff, "sev%c"}, 1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1926 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 1927 1928 /* ARM V6 instructions. */ 1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1930 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1932 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1934 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1936 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1938 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1940 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1942 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1944 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1946 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1948 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1950 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1952 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1954 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1956 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1958 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1960 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1962 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1964 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1966 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1968 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1970 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1972 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1974 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1976 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1978 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1980 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1982 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1984 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1986 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1988 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1990 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1992 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1994 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1996 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1998 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2000 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2002 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2004 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2006 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2008 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2010 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2012 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2014 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2016 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2018 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2020 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2022 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2024 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2026 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2028 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2030 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2032 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2034 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2036 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2038 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2040 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2042 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2044 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2046 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2048 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2050 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2052 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2054 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2056 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2058 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2060 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2062 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2064 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2066 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2068 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2070 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2072 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2074 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2076 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2078 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2080 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2082 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2084 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2086 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2088 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2090 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2092 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2094 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2096 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2098 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2100 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2102 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2104 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2106 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2108 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2110 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2112 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2114 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2116 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2118 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2120 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2122 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2124 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2126 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2128 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2130 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2132 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2134 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2136 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2138 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2140 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2142 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2144 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2146 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2148 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2150 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2152 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2154 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2156 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2158 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2160 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2162 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2164 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2166 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2168 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2170 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2172 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 2173 2174 /* V5J instruction. */ 2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 2176 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 2177 2178 /* V5 Instructions. */ 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2180 0xe1200070, 0xfff000f0, 2181 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2183 0xfa000000, 0xfe000000, "blx\t%B"}, 2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2185 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2187 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 2188 2189 /* V5E "El Segundo" Instructions. */ 2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2191 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2193 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2195 0xf450f000, 0xfc70f000, "pld\t%a"}, 2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2197 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2199 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2201 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2203 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 2204 2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2206 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2208 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 2209 2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2211 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2213 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2215 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2217 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2218 2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2220 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2222 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2224 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2226 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 2227 2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2229 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2231 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 2232 2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2234 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2236 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2238 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2240 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 2241 2242 /* ARM Instructions. */ 2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2244 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 2245 2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2247 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2249 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2251 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2253 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2255 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2257 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 2258 2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2260 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2262 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2264 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2266 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 2267 2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2269 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2271 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2273 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2275 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2276 2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2278 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2280 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2282 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 2283 2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2285 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2287 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2289 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 2290 2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2292 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2294 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2296 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 2297 2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2299 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2301 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2303 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 2304 2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2306 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2308 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2310 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 2311 2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2313 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2315 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2317 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 2318 2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2320 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2322 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2324 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 2325 2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2327 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2329 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2331 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 2332 2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 2334 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2336 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2338 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 2339 2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2341 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2343 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2345 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 2346 2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2348 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2350 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2352 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 2353 2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2355 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2357 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2359 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 2360 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2362 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2364 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2366 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 2367 2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2369 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2371 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2373 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 2374 2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2376 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2378 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2380 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2382 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2384 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2386 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2388 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 2389 2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2391 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2393 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2395 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 2396 2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2398 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2400 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2402 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 2403 2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2405 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2407 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 2408 2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2410 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 2411 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2413 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2415 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 2416 2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2418 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2420 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2422 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2424 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2426 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2428 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2430 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2432 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2434 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2436 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2438 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2440 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2442 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2444 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2446 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2448 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2450 0x092d0000, 0x0fff0000, "push%c\t%m"}, 2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2452 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2454 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2455 2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2457 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2459 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2461 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2463 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2465 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2467 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2469 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2471 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2473 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2475 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2477 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2479 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2481 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2483 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2485 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2487 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2489 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2491 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2493 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2494 2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2496 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2498 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 2499 2500 /* The rest. */ 2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 2502 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2504 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 2505 {ARM_FEATURE_CORE_LOW (0), 2506 0x00000000, 0x00000000, 0} 2507 }; 2508 2509 /* print_insn_thumb16 recognizes the following format control codes: 2510 2511 %S print Thumb register (bits 3..5 as high number if bit 6 set) 2512 %D print Thumb register (bits 0..2 as high number if bit 7 set) 2513 %<bitfield>I print bitfield as a signed decimal 2514 (top bit of range being the sign bit) 2515 %N print Thumb register mask (with LR) 2516 %O print Thumb register mask (with PC) 2517 %M print Thumb register mask 2518 %b print CZB's 6-bit unsigned branch destination 2519 %s print Thumb right-shift immediate (6..10; 0 == 32). 2520 %c print the condition code 2521 %C print the condition code, or "s" if not conditional 2522 %x print warning if conditional an not at end of IT block" 2523 %X print "\t; unpredictable <IT:code>" if conditional 2524 %I print IT instruction suffix and operands 2525 %W print Thumb Writeback indicator for LDMIA 2526 %<bitfield>r print bitfield as an ARM register 2527 %<bitfield>d print bitfield as a decimal 2528 %<bitfield>H print (bitfield * 2) as a decimal 2529 %<bitfield>W print (bitfield * 4) as a decimal 2530 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 2531 %<bitfield>B print Thumb branch destination (signed displacement) 2532 %<bitfield>c print bitfield as a condition code 2533 %<bitnum>'c print specified char iff bit is one 2534 %<bitnum>?ab print a if bit is one else print b. */ 2535 2536 static const struct opcode16 thumb_opcodes[] = 2537 { 2538 /* Thumb instructions. */ 2539 2540 /* ARMv8-M Security Extensions instructions. */ 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 2542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 2543 2544 /* ARM V8 instructions. */ 2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 2548 2549 /* ARM V6K no-argument instructions. */ 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 2556 2557 /* ARM V6T2 instructions. */ 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2559 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 2560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2561 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 2563 2564 /* ARM V6. */ 2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 2576 2577 /* ARM V5 ISA extends Thumb. */ 2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2579 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 2580 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2582 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 2583 /* ARM V4T ISA (Thumb v1). */ 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2585 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 2586 /* Format 4. */ 2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 2603 /* format 13 */ 2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 2606 /* format 5 */ 2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 2611 /* format 14 */ 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 2614 /* format 2 */ 2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2616 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2618 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2620 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2622 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 2623 /* format 8 */ 2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2625 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2627 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2629 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 2630 /* format 7 */ 2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2632 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2634 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2635 /* format 1 */ 2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2638 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 2641 /* format 3 */ 2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 2646 /* format 6 */ 2647 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2649 0x4800, 0xF800, 2650 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 2651 /* format 9 */ 2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2653 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2655 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2657 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2659 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2660 /* format 10 */ 2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2662 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2664 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2665 /* format 11 */ 2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2667 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2669 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 2670 /* format 12 */ 2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2672 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2674 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 2675 /* format 15 */ 2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 2678 /* format 17 */ 2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 2680 /* format 16 */ 2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 2684 /* format 18 */ 2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 2686 2687 /* The E800 .. FFFF range is unconditionally redirected to the 2688 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 2689 are processed via that table. Thus, we can never encounter a 2690 bare "second half of BL/BLX(1)" instruction here. */ 2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 2692 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 2693 }; 2694 2695 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 2696 We adopt the convention that hw1 is the high 16 bits of .value and 2697 .mask, hw2 the low 16 bits. 2698 2699 print_insn_thumb32 recognizes the following format control codes: 2700 2701 %% % 2702 2703 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 2704 %M print a modified 12-bit immediate (same location) 2705 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 2706 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 2707 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 2708 %S print a possibly-shifted Rm 2709 2710 %L print address for a ldrd/strd instruction 2711 %a print the address of a plain load/store 2712 %w print the width and signedness of a core load/store 2713 %m print register mask for ldm/stm 2714 2715 %E print the lsb and width fields of a bfc/bfi instruction 2716 %F print the lsb and width fields of a sbfx/ubfx instruction 2717 %b print a conditional branch offset 2718 %B print an unconditional branch offset 2719 %s print the shift field of an SSAT instruction 2720 %R print the rotation field of an SXT instruction 2721 %U print barrier type. 2722 %P print address for pli instruction. 2723 %c print the condition code 2724 %x print warning if conditional an not at end of IT block" 2725 %X print "\t; unpredictable <IT:code>" if conditional 2726 2727 %<bitfield>d print bitfield in decimal 2728 %<bitfield>D print bitfield plus one in decimal 2729 %<bitfield>W print bitfield*4 in decimal 2730 %<bitfield>r print bitfield as an ARM register 2731 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 2732 %<bitfield>c print bitfield as a condition code 2733 2734 %<bitfield>'c print specified char iff bitfield is all ones 2735 %<bitfield>`c print specified char iff bitfield is all zeroes 2736 %<bitfield>?ab... select from array of values in big endian order 2737 2738 With one exception at the bottom (done because BL and BLX(1) need 2739 to come dead last), this table was machine-sorted first in 2740 decreasing order of number of bits set in the mask, then in 2741 increasing numeric order of mask, then in increasing numeric order 2742 of opcode. This order is not the clearest for a human reader, but 2743 is guaranteed never to catch a special-case bit pattern with a more 2744 general mask, which is important, because this instruction encoding 2745 makes heavy use of special-case bit patterns. */ 2746 static const struct opcode32 thumb32_opcodes[] = 2747 { 2748 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 2749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2751 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2753 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2755 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2757 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 2758 2759 /* ARM V8.2 RAS extension instructions. */ 2760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 2761 0xf3af8010, 0xffffffff, "esb"}, 2762 2763 /* V8 instructions. */ 2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2765 0xf3af8005, 0xffffffff, "sevl%c.w"}, 2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2767 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2769 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2771 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2773 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2775 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2777 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2779 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2781 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2783 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2785 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2787 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2789 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2791 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2793 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2795 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 2796 2797 /* CRC32 instructions. */ 2798 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2799 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 2800 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2801 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 2802 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2803 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 2804 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2805 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 2806 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2807 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 2808 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2809 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 2810 2811 /* Speculation Barriers. */ 2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 2815 2816 /* V7 instructions. */ 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2825 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2827 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 2828 2829 /* Virtualization Extension instructions. */ 2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 2831 /* We skip ERET as that is SUBS pc, lr, #0. */ 2832 2833 /* MP Extension instructions. */ 2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 2835 2836 /* Security extension instructions. */ 2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 2838 2839 /* ARMv8.5-A instructions. */ 2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 2841 2842 /* Instructions defined in the basic V6T2 set. */ 2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2849 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 2851 2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2853 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2855 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2857 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2859 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2861 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2863 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2865 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2867 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2869 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2871 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2873 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2875 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2877 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2879 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 2880 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2881 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 2882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2883 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2885 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2887 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2889 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2891 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2893 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2895 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2897 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2899 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2901 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2903 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2905 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2907 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2909 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2911 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2913 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2915 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2917 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2919 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2921 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2923 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2925 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2927 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2929 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2931 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2933 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2935 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2937 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2939 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2941 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2943 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2945 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2947 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2949 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2951 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2953 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2955 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2957 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2959 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2961 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2963 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2965 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2967 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2969 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2971 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2973 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2975 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2977 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2979 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2981 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2983 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2985 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2987 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2989 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2991 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2993 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2995 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2997 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2999 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3001 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3003 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3005 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3007 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3009 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3011 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3013 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3015 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3017 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3019 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3021 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3023 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3025 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3027 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3029 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3031 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3033 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3035 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3037 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3039 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3041 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3043 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3045 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3047 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3049 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3051 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3053 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3055 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3057 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3059 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3061 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3063 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3065 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3067 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3069 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3071 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3073 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3075 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3077 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3079 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3081 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3083 0xf810f000, 0xff70f000, "pld%c\t%a"}, 3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3085 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3087 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3089 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3091 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3093 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3095 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3097 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3099 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3101 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3103 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3105 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3107 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3109 0xfb100000, 0xfff000c0, 3110 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3112 0xfbc00080, 0xfff000c0, 3113 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3115 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3117 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3119 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3121 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3123 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 3124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3125 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3127 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 3128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3129 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3131 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3133 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3135 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3137 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3139 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3141 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3143 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3145 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3147 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3149 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3151 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3153 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3155 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3157 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3159 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3161 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3163 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3165 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3167 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3169 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3171 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3173 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3175 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3177 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3179 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3181 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3183 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3185 0xe9400000, 0xff500000, 3186 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3188 0xe9500000, 0xff500000, 3189 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3191 0xe8600000, 0xff700000, 3192 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3194 0xe8700000, 0xff700000, 3195 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3197 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3199 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 3200 3201 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3203 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3205 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3207 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3209 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 3210 3211 /* These have been 32-bit since the invention of Thumb. */ 3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3213 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3215 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 3216 3217 /* Fallback. */ 3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3219 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 3220 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 3221 }; 3222 3223 static const char *const arm_conditional[] = 3224 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 3225 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 3226 3227 static const char *const arm_fp_const[] = 3228 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 3229 3230 static const char *const arm_shift[] = 3231 {"lsl", "lsr", "asr", "ror"}; 3232 3233 typedef struct 3234 { 3235 const char *name; 3236 const char *description; 3237 const char *reg_names[16]; 3238 } 3239 arm_regname; 3240 3241 static const arm_regname regnames[] = 3242 { 3243 { "reg-names-raw", N_("Select raw register names"), 3244 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 3245 { "reg-names-gcc", N_("Select register names used by GCC"), 3246 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3247 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 3248 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 3249 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 3250 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 3251 { "reg-names-apcs", N_("Select register names used in the APCS"), 3252 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3253 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 3254 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 3255 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 3256 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 3257 }; 3258 3259 static const char *const iwmmxt_wwnames[] = 3260 {"b", "h", "w", "d"}; 3261 3262 static const char *const iwmmxt_wwssnames[] = 3263 {"b", "bus", "bc", "bss", 3264 "h", "hus", "hc", "hss", 3265 "w", "wus", "wc", "wss", 3266 "d", "dus", "dc", "dss" 3267 }; 3268 3269 static const char *const iwmmxt_regnames[] = 3270 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 3271 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 3272 }; 3273 3274 static const char *const iwmmxt_cregnames[] = 3275 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 3276 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 3277 }; 3278 3279 /* Default to GCC register name set. */ 3280 static unsigned int regname_selected = 1; 3281 3282 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 3283 #define arm_regnames regnames[regname_selected].reg_names 3284 3285 static bfd_boolean force_thumb = FALSE; 3286 3287 /* Current IT instruction state. This contains the same state as the IT 3288 bits in the CPSR. */ 3289 static unsigned int ifthen_state; 3290 /* IT state for the next instruction. */ 3291 static unsigned int ifthen_next_state; 3292 /* The address of the insn for which the IT state is valid. */ 3293 static bfd_vma ifthen_address; 3294 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 3295 /* Indicates that the current Conditional state is unconditional or outside 3296 an IT block. */ 3297 #define COND_UNCOND 16 3298 3299 3300 /* Functions. */ 3302 3303 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 3304 Returns pointer to following character of the format string and 3305 fills in *VALUEP and *WIDTHP with the extracted value and number of 3306 bits extracted. WIDTHP can be NULL. */ 3307 3308 static const char * 3309 arm_decode_bitfield (const char *ptr, 3310 unsigned long insn, 3311 unsigned long *valuep, 3312 int *widthp) 3313 { 3314 unsigned long value = 0; 3315 int width = 0; 3316 3317 do 3318 { 3319 int start, end; 3320 int bits; 3321 3322 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 3323 start = start * 10 + *ptr - '0'; 3324 if (*ptr == '-') 3325 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 3326 end = end * 10 + *ptr - '0'; 3327 else 3328 end = start; 3329 bits = end - start; 3330 if (bits < 0) 3331 abort (); 3332 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 3333 width += bits + 1; 3334 } 3335 while (*ptr++ == ','); 3336 *valuep = value; 3337 if (widthp) 3338 *widthp = width; 3339 return ptr - 1; 3340 } 3341 3342 static void 3343 arm_decode_shift (long given, fprintf_ftype func, void *stream, 3344 bfd_boolean print_shift) 3345 { 3346 func (stream, "%s", arm_regnames[given & 0xf]); 3347 3348 if ((given & 0xff0) != 0) 3349 { 3350 if ((given & 0x10) == 0) 3351 { 3352 int amount = (given & 0xf80) >> 7; 3353 int shift = (given & 0x60) >> 5; 3354 3355 if (amount == 0) 3356 { 3357 if (shift == 3) 3358 { 3359 func (stream, ", rrx"); 3360 return; 3361 } 3362 3363 amount = 32; 3364 } 3365 3366 if (print_shift) 3367 func (stream, ", %s #%d", arm_shift[shift], amount); 3368 else 3369 func (stream, ", #%d", amount); 3370 } 3371 else if ((given & 0x80) == 0x80) 3372 func (stream, "\t; <illegal shifter operand>"); 3373 else if (print_shift) 3374 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 3375 arm_regnames[(given & 0xf00) >> 8]); 3376 else 3377 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 3378 } 3379 } 3380 3381 #define W_BIT 21 3382 #define I_BIT 22 3383 #define U_BIT 23 3384 #define P_BIT 24 3385 3386 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 3387 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 3388 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 3389 #define PRE_BIT_SET (given & (1 << P_BIT)) 3390 3391 /* Print one coprocessor instruction on INFO->STREAM. 3392 Return TRUE if the instuction matched, FALSE if this is not a 3393 recognised coprocessor instruction. */ 3394 3395 static bfd_boolean 3396 print_insn_coprocessor (bfd_vma pc, 3397 struct disassemble_info *info, 3398 long given, 3399 bfd_boolean thumb) 3400 { 3401 const struct opcode32 *insn; 3402 void *stream = info->stream; 3403 fprintf_ftype func = info->fprintf_func; 3404 unsigned long mask; 3405 unsigned long value = 0; 3406 int cond; 3407 int cp_num; 3408 struct arm_private_data *private_data = info->private_data; 3409 arm_feature_set allowed_arches = ARM_ARCH_NONE; 3410 3411 allowed_arches = private_data->features; 3412 3413 for (insn = coprocessor_opcodes; insn->assembler; insn++) 3414 { 3415 unsigned long u_reg = 16; 3416 bfd_boolean is_unpredictable = FALSE; 3417 signed long value_in_comment = 0; 3418 const char *c; 3419 3420 if (ARM_FEATURE_ZERO (insn->arch)) 3421 switch (insn->value) 3422 { 3423 case SENTINEL_IWMMXT_START: 3424 if (info->mach != bfd_mach_arm_XScale 3425 && info->mach != bfd_mach_arm_iWMMXt 3426 && info->mach != bfd_mach_arm_iWMMXt2) 3427 do 3428 insn++; 3429 while ((! ARM_FEATURE_ZERO (insn->arch)) 3430 && insn->value != SENTINEL_IWMMXT_END); 3431 continue; 3432 3433 case SENTINEL_IWMMXT_END: 3434 continue; 3435 3436 case SENTINEL_GENERIC_START: 3437 allowed_arches = private_data->features; 3438 continue; 3439 3440 default: 3441 abort (); 3442 } 3443 3444 mask = insn->mask; 3445 value = insn->value; 3446 cp_num = (given >> 8) & 0xf; 3447 3448 if (thumb) 3449 { 3450 /* The high 4 bits are 0xe for Arm conditional instructions, and 3451 0xe for arm unconditional instructions. The rest of the 3452 encoding is the same. */ 3453 mask |= 0xf0000000; 3454 value |= 0xe0000000; 3455 if (ifthen_state) 3456 cond = IFTHEN_COND; 3457 else 3458 cond = COND_UNCOND; 3459 } 3460 else 3461 { 3462 /* Only match unconditional instuctions against unconditional 3463 patterns. */ 3464 if ((given & 0xf0000000) == 0xf0000000) 3465 { 3466 mask |= 0xf0000000; 3467 cond = COND_UNCOND; 3468 } 3469 else 3470 { 3471 cond = (given >> 28) & 0xf; 3472 if (cond == 0xe) 3473 cond = COND_UNCOND; 3474 } 3475 } 3476 3477 if ((given & mask) != value) 3478 continue; 3479 3480 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 3481 continue; 3482 3483 if (insn->value == 0xfe000010 /* mcr2 */ 3484 || insn->value == 0xfe100010 /* mrc2 */ 3485 || insn->value == 0xfc100000 /* ldc2 */ 3486 || insn->value == 0xfc000000) /* stc2 */ 3487 { 3488 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3489 is_unpredictable = TRUE; 3490 } 3491 else if (insn->value == 0x0e000000 /* cdp */ 3492 || insn->value == 0xfe000000 /* cdp2 */ 3493 || insn->value == 0x0e000010 /* mcr */ 3494 || insn->value == 0x0e100010 /* mrc */ 3495 || insn->value == 0x0c100000 /* ldc */ 3496 || insn->value == 0x0c000000) /* stc */ 3497 { 3498 /* Floating-point instructions. */ 3499 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3500 continue; 3501 } 3502 3503 for (c = insn->assembler; *c; c++) 3504 { 3505 if (*c == '%') 3506 { 3507 switch (*++c) 3508 { 3509 case '%': 3510 func (stream, "%%"); 3511 break; 3512 3513 case 'A': 3514 { 3515 int rn = (given >> 16) & 0xf; 3516 bfd_vma offset = given & 0xff; 3517 3518 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3519 3520 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 3521 { 3522 /* Not unindexed. The offset is scaled. */ 3523 if (cp_num == 9) 3524 /* vldr.16/vstr.16 will shift the address 3525 left by 1 bit only. */ 3526 offset = offset * 2; 3527 else 3528 offset = offset * 4; 3529 3530 if (NEGATIVE_BIT_SET) 3531 offset = - offset; 3532 if (rn != 15) 3533 value_in_comment = offset; 3534 } 3535 3536 if (PRE_BIT_SET) 3537 { 3538 if (offset) 3539 func (stream, ", #%d]%s", 3540 (int) offset, 3541 WRITEBACK_BIT_SET ? "!" : ""); 3542 else if (NEGATIVE_BIT_SET) 3543 func (stream, ", #-0]"); 3544 else 3545 func (stream, "]"); 3546 } 3547 else 3548 { 3549 func (stream, "]"); 3550 3551 if (WRITEBACK_BIT_SET) 3552 { 3553 if (offset) 3554 func (stream, ", #%d", (int) offset); 3555 else if (NEGATIVE_BIT_SET) 3556 func (stream, ", #-0"); 3557 } 3558 else 3559 { 3560 func (stream, ", {%s%d}", 3561 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 3562 (int) offset); 3563 value_in_comment = offset; 3564 } 3565 } 3566 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 3567 { 3568 func (stream, "\t; "); 3569 /* For unaligned PCs, apply off-by-alignment 3570 correction. */ 3571 info->print_address_func (offset + pc 3572 + info->bytes_per_chunk * 2 3573 - (pc & 3), 3574 info); 3575 } 3576 } 3577 break; 3578 3579 case 'B': 3580 { 3581 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 3582 int offset = (given >> 1) & 0x3f; 3583 3584 if (offset == 1) 3585 func (stream, "{d%d}", regno); 3586 else if (regno + offset > 32) 3587 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 3588 else 3589 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 3590 } 3591 break; 3592 3593 case 'u': 3594 if (cond != COND_UNCOND) 3595 is_unpredictable = TRUE; 3596 3597 /* Fall through. */ 3598 case 'c': 3599 if (cond != COND_UNCOND && cp_num == 9) 3600 is_unpredictable = TRUE; 3601 3602 func (stream, "%s", arm_conditional[cond]); 3603 break; 3604 3605 case 'I': 3606 /* Print a Cirrus/DSP shift immediate. */ 3607 /* Immediates are 7bit signed ints with bits 0..3 in 3608 bits 0..3 of opcode and bits 4..6 in bits 5..7 3609 of opcode. */ 3610 { 3611 int imm; 3612 3613 imm = (given & 0xf) | ((given & 0xe0) >> 1); 3614 3615 /* Is ``imm'' a negative number? */ 3616 if (imm & 0x40) 3617 imm -= 0x80; 3618 3619 func (stream, "%d", imm); 3620 } 3621 3622 break; 3623 3624 case 'F': 3625 switch (given & 0x00408000) 3626 { 3627 case 0: 3628 func (stream, "4"); 3629 break; 3630 case 0x8000: 3631 func (stream, "1"); 3632 break; 3633 case 0x00400000: 3634 func (stream, "2"); 3635 break; 3636 default: 3637 func (stream, "3"); 3638 } 3639 break; 3640 3641 case 'P': 3642 switch (given & 0x00080080) 3643 { 3644 case 0: 3645 func (stream, "s"); 3646 break; 3647 case 0x80: 3648 func (stream, "d"); 3649 break; 3650 case 0x00080000: 3651 func (stream, "e"); 3652 break; 3653 default: 3654 func (stream, _("<illegal precision>")); 3655 break; 3656 } 3657 break; 3658 3659 case 'Q': 3660 switch (given & 0x00408000) 3661 { 3662 case 0: 3663 func (stream, "s"); 3664 break; 3665 case 0x8000: 3666 func (stream, "d"); 3667 break; 3668 case 0x00400000: 3669 func (stream, "e"); 3670 break; 3671 default: 3672 func (stream, "p"); 3673 break; 3674 } 3675 break; 3676 3677 case 'R': 3678 switch (given & 0x60) 3679 { 3680 case 0: 3681 break; 3682 case 0x20: 3683 func (stream, "p"); 3684 break; 3685 case 0x40: 3686 func (stream, "m"); 3687 break; 3688 default: 3689 func (stream, "z"); 3690 break; 3691 } 3692 break; 3693 3694 case '0': case '1': case '2': case '3': case '4': 3695 case '5': case '6': case '7': case '8': case '9': 3696 { 3697 int width; 3698 3699 c = arm_decode_bitfield (c, given, &value, &width); 3700 3701 switch (*c) 3702 { 3703 case 'R': 3704 if (value == 15) 3705 is_unpredictable = TRUE; 3706 /* Fall through. */ 3707 case 'r': 3708 if (c[1] == 'u') 3709 { 3710 /* Eat the 'u' character. */ 3711 ++ c; 3712 3713 if (u_reg == value) 3714 is_unpredictable = TRUE; 3715 u_reg = value; 3716 } 3717 func (stream, "%s", arm_regnames[value]); 3718 break; 3719 case 'V': 3720 if (given & (1 << 6)) 3721 goto Q; 3722 /* FALLTHROUGH */ 3723 case 'D': 3724 func (stream, "d%ld", value); 3725 break; 3726 case 'Q': 3727 Q: 3728 if (value & 1) 3729 func (stream, "<illegal reg q%ld.5>", value >> 1); 3730 else 3731 func (stream, "q%ld", value >> 1); 3732 break; 3733 case 'd': 3734 func (stream, "%ld", value); 3735 value_in_comment = value; 3736 break; 3737 case 'E': 3738 { 3739 /* Converts immediate 8 bit back to float value. */ 3740 unsigned floatVal = (value & 0x80) << 24 3741 | (value & 0x3F) << 19 3742 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 3743 3744 /* Quarter float have a maximum value of 31.0. 3745 Get floating point value multiplied by 1e7. 3746 The maximum value stays in limit of a 32-bit int. */ 3747 unsigned decVal = 3748 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 3749 (16 + (value & 0xF)); 3750 3751 if (!(decVal % 1000000)) 3752 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 3753 floatVal, value & 0x80 ? '-' : ' ', 3754 decVal / 10000000, 3755 decVal % 10000000 / 1000000); 3756 else if (!(decVal % 10000)) 3757 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 3758 floatVal, value & 0x80 ? '-' : ' ', 3759 decVal / 10000000, 3760 decVal % 10000000 / 10000); 3761 else 3762 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 3763 floatVal, value & 0x80 ? '-' : ' ', 3764 decVal / 10000000, decVal % 10000000); 3765 break; 3766 } 3767 case 'k': 3768 { 3769 int from = (given & (1 << 7)) ? 32 : 16; 3770 func (stream, "%ld", from - value); 3771 } 3772 break; 3773 3774 case 'f': 3775 if (value > 7) 3776 func (stream, "#%s", arm_fp_const[value & 7]); 3777 else 3778 func (stream, "f%ld", value); 3779 break; 3780 3781 case 'w': 3782 if (width == 2) 3783 func (stream, "%s", iwmmxt_wwnames[value]); 3784 else 3785 func (stream, "%s", iwmmxt_wwssnames[value]); 3786 break; 3787 3788 case 'g': 3789 func (stream, "%s", iwmmxt_regnames[value]); 3790 break; 3791 case 'G': 3792 func (stream, "%s", iwmmxt_cregnames[value]); 3793 break; 3794 3795 case 'x': 3796 func (stream, "0x%lx", (value & 0xffffffffUL)); 3797 break; 3798 3799 case 'c': 3800 switch (value) 3801 { 3802 case 0: 3803 func (stream, "eq"); 3804 break; 3805 3806 case 1: 3807 func (stream, "vs"); 3808 break; 3809 3810 case 2: 3811 func (stream, "ge"); 3812 break; 3813 3814 case 3: 3815 func (stream, "gt"); 3816 break; 3817 3818 default: 3819 func (stream, "??"); 3820 break; 3821 } 3822 break; 3823 3824 case '`': 3825 c++; 3826 if (value == 0) 3827 func (stream, "%c", *c); 3828 break; 3829 case '\'': 3830 c++; 3831 if (value == ((1ul << width) - 1)) 3832 func (stream, "%c", *c); 3833 break; 3834 case '?': 3835 func (stream, "%c", c[(1 << width) - (int) value]); 3836 c += 1 << width; 3837 break; 3838 default: 3839 abort (); 3840 } 3841 break; 3842 3843 case 'y': 3844 case 'z': 3845 { 3846 int single = *c++ == 'y'; 3847 int regno; 3848 3849 switch (*c) 3850 { 3851 case '4': /* Sm pair */ 3852 case '0': /* Sm, Dm */ 3853 regno = given & 0x0000000f; 3854 if (single) 3855 { 3856 regno <<= 1; 3857 regno += (given >> 5) & 1; 3858 } 3859 else 3860 regno += ((given >> 5) & 1) << 4; 3861 break; 3862 3863 case '1': /* Sd, Dd */ 3864 regno = (given >> 12) & 0x0000000f; 3865 if (single) 3866 { 3867 regno <<= 1; 3868 regno += (given >> 22) & 1; 3869 } 3870 else 3871 regno += ((given >> 22) & 1) << 4; 3872 break; 3873 3874 case '2': /* Sn, Dn */ 3875 regno = (given >> 16) & 0x0000000f; 3876 if (single) 3877 { 3878 regno <<= 1; 3879 regno += (given >> 7) & 1; 3880 } 3881 else 3882 regno += ((given >> 7) & 1) << 4; 3883 break; 3884 3885 case '3': /* List */ 3886 func (stream, "{"); 3887 regno = (given >> 12) & 0x0000000f; 3888 if (single) 3889 { 3890 regno <<= 1; 3891 regno += (given >> 22) & 1; 3892 } 3893 else 3894 regno += ((given >> 22) & 1) << 4; 3895 break; 3896 3897 default: 3898 abort (); 3899 } 3900 3901 func (stream, "%c%d", single ? 's' : 'd', regno); 3902 3903 if (*c == '3') 3904 { 3905 int count = given & 0xff; 3906 3907 if (single == 0) 3908 count >>= 1; 3909 3910 if (--count) 3911 { 3912 func (stream, "-%c%d", 3913 single ? 's' : 'd', 3914 regno + count); 3915 } 3916 3917 func (stream, "}"); 3918 } 3919 else if (*c == '4') 3920 func (stream, ", %c%d", single ? 's' : 'd', 3921 regno + 1); 3922 } 3923 break; 3924 3925 case 'L': 3926 switch (given & 0x00400100) 3927 { 3928 case 0x00000000: func (stream, "b"); break; 3929 case 0x00400000: func (stream, "h"); break; 3930 case 0x00000100: func (stream, "w"); break; 3931 case 0x00400100: func (stream, "d"); break; 3932 default: 3933 break; 3934 } 3935 break; 3936 3937 case 'Z': 3938 { 3939 /* given (20, 23) | given (0, 3) */ 3940 value = ((given >> 16) & 0xf0) | (given & 0xf); 3941 func (stream, "%d", (int) value); 3942 } 3943 break; 3944 3945 case 'l': 3946 /* This is like the 'A' operator, except that if 3947 the width field "M" is zero, then the offset is 3948 *not* multiplied by four. */ 3949 { 3950 int offset = given & 0xff; 3951 int multiplier = (given & 0x00000100) ? 4 : 1; 3952 3953 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3954 3955 if (multiplier > 1) 3956 { 3957 value_in_comment = offset * multiplier; 3958 if (NEGATIVE_BIT_SET) 3959 value_in_comment = - value_in_comment; 3960 } 3961 3962 if (offset) 3963 { 3964 if (PRE_BIT_SET) 3965 func (stream, ", #%s%d]%s", 3966 NEGATIVE_BIT_SET ? "-" : "", 3967 offset * multiplier, 3968 WRITEBACK_BIT_SET ? "!" : ""); 3969 else 3970 func (stream, "], #%s%d", 3971 NEGATIVE_BIT_SET ? "-" : "", 3972 offset * multiplier); 3973 } 3974 else 3975 func (stream, "]"); 3976 } 3977 break; 3978 3979 case 'r': 3980 { 3981 int imm4 = (given >> 4) & 0xf; 3982 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 3983 int ubit = ! NEGATIVE_BIT_SET; 3984 const char *rm = arm_regnames [given & 0xf]; 3985 const char *rn = arm_regnames [(given >> 16) & 0xf]; 3986 3987 switch (puw_bits) 3988 { 3989 case 1: 3990 case 3: 3991 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 3992 if (imm4) 3993 func (stream, ", lsl #%d", imm4); 3994 break; 3995 3996 case 4: 3997 case 5: 3998 case 6: 3999 case 7: 4000 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 4001 if (imm4 > 0) 4002 func (stream, ", lsl #%d", imm4); 4003 func (stream, "]"); 4004 if (puw_bits == 5 || puw_bits == 7) 4005 func (stream, "!"); 4006 break; 4007 4008 default: 4009 func (stream, "INVALID"); 4010 } 4011 } 4012 break; 4013 4014 case 'i': 4015 { 4016 long imm5; 4017 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 4018 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 4019 } 4020 break; 4021 4022 default: 4023 abort (); 4024 } 4025 } 4026 } 4027 else 4028 func (stream, "%c", *c); 4029 } 4030 4031 if (value_in_comment > 32 || value_in_comment < -16) 4032 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 4033 4034 if (is_unpredictable) 4035 func (stream, UNPREDICTABLE_INSTRUCTION); 4036 4037 return TRUE; 4038 } 4039 return FALSE; 4040 } 4041 4042 /* Decodes and prints ARM addressing modes. Returns the offset 4043 used in the address, if any, if it is worthwhile printing the 4044 offset as a hexadecimal value in a comment at the end of the 4045 line of disassembly. */ 4046 4047 static signed long 4048 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 4049 { 4050 void *stream = info->stream; 4051 fprintf_ftype func = info->fprintf_func; 4052 bfd_vma offset = 0; 4053 4054 if (((given & 0x000f0000) == 0x000f0000) 4055 && ((given & 0x02000000) == 0)) 4056 { 4057 offset = given & 0xfff; 4058 4059 func (stream, "[pc"); 4060 4061 if (PRE_BIT_SET) 4062 { 4063 /* Pre-indexed. Elide offset of positive zero when 4064 non-writeback. */ 4065 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4066 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4067 4068 if (NEGATIVE_BIT_SET) 4069 offset = -offset; 4070 4071 offset += pc + 8; 4072 4073 /* Cope with the possibility of write-back 4074 being used. Probably a very dangerous thing 4075 for the programmer to do, but who are we to 4076 argue ? */ 4077 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 4078 } 4079 else /* Post indexed. */ 4080 { 4081 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4082 4083 /* Ie ignore the offset. */ 4084 offset = pc + 8; 4085 } 4086 4087 func (stream, "\t; "); 4088 info->print_address_func (offset, info); 4089 offset = 0; 4090 } 4091 else 4092 { 4093 func (stream, "[%s", 4094 arm_regnames[(given >> 16) & 0xf]); 4095 4096 if (PRE_BIT_SET) 4097 { 4098 if ((given & 0x02000000) == 0) 4099 { 4100 /* Elide offset of positive zero when non-writeback. */ 4101 offset = given & 0xfff; 4102 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4103 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4104 } 4105 else 4106 { 4107 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 4108 arm_decode_shift (given, func, stream, TRUE); 4109 } 4110 4111 func (stream, "]%s", 4112 WRITEBACK_BIT_SET ? "!" : ""); 4113 } 4114 else 4115 { 4116 if ((given & 0x02000000) == 0) 4117 { 4118 /* Always show offset. */ 4119 offset = given & 0xfff; 4120 func (stream, "], #%s%d", 4121 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4122 } 4123 else 4124 { 4125 func (stream, "], %s", 4126 NEGATIVE_BIT_SET ? "-" : ""); 4127 arm_decode_shift (given, func, stream, TRUE); 4128 } 4129 } 4130 if (NEGATIVE_BIT_SET) 4131 offset = -offset; 4132 } 4133 4134 return (signed long) offset; 4135 } 4136 4137 /* Print one neon instruction on INFO->STREAM. 4138 Return TRUE if the instuction matched, FALSE if this is not a 4139 recognised neon instruction. */ 4140 4141 static bfd_boolean 4142 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 4143 { 4144 const struct opcode32 *insn; 4145 void *stream = info->stream; 4146 fprintf_ftype func = info->fprintf_func; 4147 4148 if (thumb) 4149 { 4150 if ((given & 0xef000000) == 0xef000000) 4151 { 4152 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 4153 unsigned long bit28 = given & (1 << 28); 4154 4155 given &= 0x00ffffff; 4156 if (bit28) 4157 given |= 0xf3000000; 4158 else 4159 given |= 0xf2000000; 4160 } 4161 else if ((given & 0xff000000) == 0xf9000000) 4162 given ^= 0xf9000000 ^ 0xf4000000; 4163 else 4164 return FALSE; 4165 } 4166 4167 for (insn = neon_opcodes; insn->assembler; insn++) 4168 { 4169 if ((given & insn->mask) == insn->value) 4170 { 4171 signed long value_in_comment = 0; 4172 bfd_boolean is_unpredictable = FALSE; 4173 const char *c; 4174 4175 for (c = insn->assembler; *c; c++) 4176 { 4177 if (*c == '%') 4178 { 4179 switch (*++c) 4180 { 4181 case '%': 4182 func (stream, "%%"); 4183 break; 4184 4185 case 'u': 4186 if (thumb && ifthen_state) 4187 is_unpredictable = TRUE; 4188 4189 /* Fall through. */ 4190 case 'c': 4191 if (thumb && ifthen_state) 4192 func (stream, "%s", arm_conditional[IFTHEN_COND]); 4193 break; 4194 4195 case 'A': 4196 { 4197 static const unsigned char enc[16] = 4198 { 4199 0x4, 0x14, /* st4 0,1 */ 4200 0x4, /* st1 2 */ 4201 0x4, /* st2 3 */ 4202 0x3, /* st3 4 */ 4203 0x13, /* st3 5 */ 4204 0x3, /* st1 6 */ 4205 0x1, /* st1 7 */ 4206 0x2, /* st2 8 */ 4207 0x12, /* st2 9 */ 4208 0x2, /* st1 10 */ 4209 0, 0, 0, 0, 0 4210 }; 4211 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4212 int rn = ((given >> 16) & 0xf); 4213 int rm = ((given >> 0) & 0xf); 4214 int align = ((given >> 4) & 0x3); 4215 int type = ((given >> 8) & 0xf); 4216 int n = enc[type] & 0xf; 4217 int stride = (enc[type] >> 4) + 1; 4218 int ix; 4219 4220 func (stream, "{"); 4221 if (stride > 1) 4222 for (ix = 0; ix != n; ix++) 4223 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 4224 else if (n == 1) 4225 func (stream, "d%d", rd); 4226 else 4227 func (stream, "d%d-d%d", rd, rd + n - 1); 4228 func (stream, "}, [%s", arm_regnames[rn]); 4229 if (align) 4230 func (stream, " :%d", 32 << align); 4231 func (stream, "]"); 4232 if (rm == 0xd) 4233 func (stream, "!"); 4234 else if (rm != 0xf) 4235 func (stream, ", %s", arm_regnames[rm]); 4236 } 4237 break; 4238 4239 case 'B': 4240 { 4241 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4242 int rn = ((given >> 16) & 0xf); 4243 int rm = ((given >> 0) & 0xf); 4244 int idx_align = ((given >> 4) & 0xf); 4245 int align = 0; 4246 int size = ((given >> 10) & 0x3); 4247 int idx = idx_align >> (size + 1); 4248 int length = ((given >> 8) & 3) + 1; 4249 int stride = 1; 4250 int i; 4251 4252 if (length > 1 && size > 0) 4253 stride = (idx_align & (1 << size)) ? 2 : 1; 4254 4255 switch (length) 4256 { 4257 case 1: 4258 { 4259 int amask = (1 << size) - 1; 4260 if ((idx_align & (1 << size)) != 0) 4261 return FALSE; 4262 if (size > 0) 4263 { 4264 if ((idx_align & amask) == amask) 4265 align = 8 << size; 4266 else if ((idx_align & amask) != 0) 4267 return FALSE; 4268 } 4269 } 4270 break; 4271 4272 case 2: 4273 if (size == 2 && (idx_align & 2) != 0) 4274 return FALSE; 4275 align = (idx_align & 1) ? 16 << size : 0; 4276 break; 4277 4278 case 3: 4279 if ((size == 2 && (idx_align & 3) != 0) 4280 || (idx_align & 1) != 0) 4281 return FALSE; 4282 break; 4283 4284 case 4: 4285 if (size == 2) 4286 { 4287 if ((idx_align & 3) == 3) 4288 return FALSE; 4289 align = (idx_align & 3) * 64; 4290 } 4291 else 4292 align = (idx_align & 1) ? 32 << size : 0; 4293 break; 4294 4295 default: 4296 abort (); 4297 } 4298 4299 func (stream, "{"); 4300 for (i = 0; i < length; i++) 4301 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 4302 rd + i * stride, idx); 4303 func (stream, "}, [%s", arm_regnames[rn]); 4304 if (align) 4305 func (stream, " :%d", align); 4306 func (stream, "]"); 4307 if (rm == 0xd) 4308 func (stream, "!"); 4309 else if (rm != 0xf) 4310 func (stream, ", %s", arm_regnames[rm]); 4311 } 4312 break; 4313 4314 case 'C': 4315 { 4316 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4317 int rn = ((given >> 16) & 0xf); 4318 int rm = ((given >> 0) & 0xf); 4319 int align = ((given >> 4) & 0x1); 4320 int size = ((given >> 6) & 0x3); 4321 int type = ((given >> 8) & 0x3); 4322 int n = type + 1; 4323 int stride = ((given >> 5) & 0x1); 4324 int ix; 4325 4326 if (stride && (n == 1)) 4327 n++; 4328 else 4329 stride++; 4330 4331 func (stream, "{"); 4332 if (stride > 1) 4333 for (ix = 0; ix != n; ix++) 4334 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 4335 else if (n == 1) 4336 func (stream, "d%d[]", rd); 4337 else 4338 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 4339 func (stream, "}, [%s", arm_regnames[rn]); 4340 if (align) 4341 { 4342 align = (8 * (type + 1)) << size; 4343 if (type == 3) 4344 align = (size > 1) ? align >> 1 : align; 4345 if (type == 2 || (type == 0 && !size)) 4346 func (stream, " :<bad align %d>", align); 4347 else 4348 func (stream, " :%d", align); 4349 } 4350 func (stream, "]"); 4351 if (rm == 0xd) 4352 func (stream, "!"); 4353 else if (rm != 0xf) 4354 func (stream, ", %s", arm_regnames[rm]); 4355 } 4356 break; 4357 4358 case 'D': 4359 { 4360 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 4361 int size = (given >> 20) & 3; 4362 int reg = raw_reg & ((4 << size) - 1); 4363 int ix = raw_reg >> size >> 2; 4364 4365 func (stream, "d%d[%d]", reg, ix); 4366 } 4367 break; 4368 4369 case 'E': 4370 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 4371 { 4372 int bits = 0; 4373 int cmode = (given >> 8) & 0xf; 4374 int op = (given >> 5) & 0x1; 4375 unsigned long value = 0, hival = 0; 4376 unsigned shift; 4377 int size = 0; 4378 int isfloat = 0; 4379 4380 bits |= ((given >> 24) & 1) << 7; 4381 bits |= ((given >> 16) & 7) << 4; 4382 bits |= ((given >> 0) & 15) << 0; 4383 4384 if (cmode < 8) 4385 { 4386 shift = (cmode >> 1) & 3; 4387 value = (unsigned long) bits << (8 * shift); 4388 size = 32; 4389 } 4390 else if (cmode < 12) 4391 { 4392 shift = (cmode >> 1) & 1; 4393 value = (unsigned long) bits << (8 * shift); 4394 size = 16; 4395 } 4396 else if (cmode < 14) 4397 { 4398 shift = (cmode & 1) + 1; 4399 value = (unsigned long) bits << (8 * shift); 4400 value |= (1ul << (8 * shift)) - 1; 4401 size = 32; 4402 } 4403 else if (cmode == 14) 4404 { 4405 if (op) 4406 { 4407 /* Bit replication into bytes. */ 4408 int ix; 4409 unsigned long mask; 4410 4411 value = 0; 4412 hival = 0; 4413 for (ix = 7; ix >= 0; ix--) 4414 { 4415 mask = ((bits >> ix) & 1) ? 0xff : 0; 4416 if (ix <= 3) 4417 value = (value << 8) | mask; 4418 else 4419 hival = (hival << 8) | mask; 4420 } 4421 size = 64; 4422 } 4423 else 4424 { 4425 /* Byte replication. */ 4426 value = (unsigned long) bits; 4427 size = 8; 4428 } 4429 } 4430 else if (!op) 4431 { 4432 /* Floating point encoding. */ 4433 int tmp; 4434 4435 value = (unsigned long) (bits & 0x7f) << 19; 4436 value |= (unsigned long) (bits & 0x80) << 24; 4437 tmp = bits & 0x40 ? 0x3c : 0x40; 4438 value |= (unsigned long) tmp << 24; 4439 size = 32; 4440 isfloat = 1; 4441 } 4442 else 4443 { 4444 func (stream, "<illegal constant %.8x:%x:%x>", 4445 bits, cmode, op); 4446 size = 32; 4447 break; 4448 } 4449 switch (size) 4450 { 4451 case 8: 4452 func (stream, "#%ld\t; 0x%.2lx", value, value); 4453 break; 4454 4455 case 16: 4456 func (stream, "#%ld\t; 0x%.4lx", value, value); 4457 break; 4458 4459 case 32: 4460 if (isfloat) 4461 { 4462 unsigned char valbytes[4]; 4463 double fvalue; 4464 4465 /* Do this a byte at a time so we don't have to 4466 worry about the host's endianness. */ 4467 valbytes[0] = value & 0xff; 4468 valbytes[1] = (value >> 8) & 0xff; 4469 valbytes[2] = (value >> 16) & 0xff; 4470 valbytes[3] = (value >> 24) & 0xff; 4471 4472 floatformat_to_double 4473 (& floatformat_ieee_single_little, valbytes, 4474 & fvalue); 4475 4476 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 4477 value); 4478 } 4479 else 4480 func (stream, "#%ld\t; 0x%.8lx", 4481 (long) (((value & 0x80000000L) != 0) 4482 ? value | ~0xffffffffL : value), 4483 value); 4484 break; 4485 4486 case 64: 4487 func (stream, "#0x%.8lx%.8lx", hival, value); 4488 break; 4489 4490 default: 4491 abort (); 4492 } 4493 } 4494 break; 4495 4496 case 'F': 4497 { 4498 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 4499 int num = (given >> 8) & 0x3; 4500 4501 if (!num) 4502 func (stream, "{d%d}", regno); 4503 else if (num + regno >= 32) 4504 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 4505 else 4506 func (stream, "{d%d-d%d}", regno, regno + num); 4507 } 4508 break; 4509 4510 4511 case '0': case '1': case '2': case '3': case '4': 4512 case '5': case '6': case '7': case '8': case '9': 4513 { 4514 int width; 4515 unsigned long value; 4516 4517 c = arm_decode_bitfield (c, given, &value, &width); 4518 4519 switch (*c) 4520 { 4521 case 'r': 4522 func (stream, "%s", arm_regnames[value]); 4523 break; 4524 case 'd': 4525 func (stream, "%ld", value); 4526 value_in_comment = value; 4527 break; 4528 case 'e': 4529 func (stream, "%ld", (1ul << width) - value); 4530 break; 4531 4532 case 'S': 4533 case 'T': 4534 case 'U': 4535 /* Various width encodings. */ 4536 { 4537 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 4538 int limit; 4539 unsigned low, high; 4540 4541 c++; 4542 if (*c >= '0' && *c <= '9') 4543 limit = *c - '0'; 4544 else if (*c >= 'a' && *c <= 'f') 4545 limit = *c - 'a' + 10; 4546 else 4547 abort (); 4548 low = limit >> 2; 4549 high = limit & 3; 4550 4551 if (value < low || value > high) 4552 func (stream, "<illegal width %d>", base << value); 4553 else 4554 func (stream, "%d", base << value); 4555 } 4556 break; 4557 case 'R': 4558 if (given & (1 << 6)) 4559 goto Q; 4560 /* FALLTHROUGH */ 4561 case 'D': 4562 func (stream, "d%ld", value); 4563 break; 4564 case 'Q': 4565 Q: 4566 if (value & 1) 4567 func (stream, "<illegal reg q%ld.5>", value >> 1); 4568 else 4569 func (stream, "q%ld", value >> 1); 4570 break; 4571 4572 case '`': 4573 c++; 4574 if (value == 0) 4575 func (stream, "%c", *c); 4576 break; 4577 case '\'': 4578 c++; 4579 if (value == ((1ul << width) - 1)) 4580 func (stream, "%c", *c); 4581 break; 4582 case '?': 4583 func (stream, "%c", c[(1 << width) - (int) value]); 4584 c += 1 << width; 4585 break; 4586 default: 4587 abort (); 4588 } 4589 break; 4590 4591 default: 4592 abort (); 4593 } 4594 } 4595 } 4596 else 4597 func (stream, "%c", *c); 4598 } 4599 4600 if (value_in_comment > 32 || value_in_comment < -16) 4601 func (stream, "\t; 0x%lx", value_in_comment); 4602 4603 if (is_unpredictable) 4604 func (stream, UNPREDICTABLE_INSTRUCTION); 4605 4606 return TRUE; 4607 } 4608 } 4609 return FALSE; 4610 } 4611 4612 /* Return the name of a v7A special register. */ 4613 4614 static const char * 4615 banked_regname (unsigned reg) 4616 { 4617 switch (reg) 4618 { 4619 case 15: return "CPSR"; 4620 case 32: return "R8_usr"; 4621 case 33: return "R9_usr"; 4622 case 34: return "R10_usr"; 4623 case 35: return "R11_usr"; 4624 case 36: return "R12_usr"; 4625 case 37: return "SP_usr"; 4626 case 38: return "LR_usr"; 4627 case 40: return "R8_fiq"; 4628 case 41: return "R9_fiq"; 4629 case 42: return "R10_fiq"; 4630 case 43: return "R11_fiq"; 4631 case 44: return "R12_fiq"; 4632 case 45: return "SP_fiq"; 4633 case 46: return "LR_fiq"; 4634 case 48: return "LR_irq"; 4635 case 49: return "SP_irq"; 4636 case 50: return "LR_svc"; 4637 case 51: return "SP_svc"; 4638 case 52: return "LR_abt"; 4639 case 53: return "SP_abt"; 4640 case 54: return "LR_und"; 4641 case 55: return "SP_und"; 4642 case 60: return "LR_mon"; 4643 case 61: return "SP_mon"; 4644 case 62: return "ELR_hyp"; 4645 case 63: return "SP_hyp"; 4646 case 79: return "SPSR"; 4647 case 110: return "SPSR_fiq"; 4648 case 112: return "SPSR_irq"; 4649 case 114: return "SPSR_svc"; 4650 case 116: return "SPSR_abt"; 4651 case 118: return "SPSR_und"; 4652 case 124: return "SPSR_mon"; 4653 case 126: return "SPSR_hyp"; 4654 default: return NULL; 4655 } 4656 } 4657 4658 /* Return the name of the DMB/DSB option. */ 4659 static const char * 4660 data_barrier_option (unsigned option) 4661 { 4662 switch (option & 0xf) 4663 { 4664 case 0xf: return "sy"; 4665 case 0xe: return "st"; 4666 case 0xd: return "ld"; 4667 case 0xb: return "ish"; 4668 case 0xa: return "ishst"; 4669 case 0x9: return "ishld"; 4670 case 0x7: return "un"; 4671 case 0x6: return "unst"; 4672 case 0x5: return "nshld"; 4673 case 0x3: return "osh"; 4674 case 0x2: return "oshst"; 4675 case 0x1: return "oshld"; 4676 default: return NULL; 4677 } 4678 } 4679 4680 /* Print one ARM instruction from PC on INFO->STREAM. */ 4681 4682 static void 4683 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 4684 { 4685 const struct opcode32 *insn; 4686 void *stream = info->stream; 4687 fprintf_ftype func = info->fprintf_func; 4688 struct arm_private_data *private_data = info->private_data; 4689 4690 if (print_insn_coprocessor (pc, info, given, FALSE)) 4691 return; 4692 4693 if (print_insn_neon (info, given, FALSE)) 4694 return; 4695 4696 for (insn = arm_opcodes; insn->assembler; insn++) 4697 { 4698 if ((given & insn->mask) != insn->value) 4699 continue; 4700 4701 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 4702 continue; 4703 4704 /* Special case: an instruction with all bits set in the condition field 4705 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 4706 or by the catchall at the end of the table. */ 4707 if ((given & 0xF0000000) != 0xF0000000 4708 || (insn->mask & 0xF0000000) == 0xF0000000 4709 || (insn->mask == 0 && insn->value == 0)) 4710 { 4711 unsigned long u_reg = 16; 4712 unsigned long U_reg = 16; 4713 bfd_boolean is_unpredictable = FALSE; 4714 signed long value_in_comment = 0; 4715 const char *c; 4716 4717 for (c = insn->assembler; *c; c++) 4718 { 4719 if (*c == '%') 4720 { 4721 bfd_boolean allow_unpredictable = FALSE; 4722 4723 switch (*++c) 4724 { 4725 case '%': 4726 func (stream, "%%"); 4727 break; 4728 4729 case 'a': 4730 value_in_comment = print_arm_address (pc, info, given); 4731 break; 4732 4733 case 'P': 4734 /* Set P address bit and use normal address 4735 printing routine. */ 4736 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 4737 break; 4738 4739 case 'S': 4740 allow_unpredictable = TRUE; 4741 /* Fall through. */ 4742 case 's': 4743 if ((given & 0x004f0000) == 0x004f0000) 4744 { 4745 /* PC relative with immediate offset. */ 4746 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 4747 4748 if (PRE_BIT_SET) 4749 { 4750 /* Elide positive zero offset. */ 4751 if (offset || NEGATIVE_BIT_SET) 4752 func (stream, "[pc, #%s%d]\t; ", 4753 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4754 else 4755 func (stream, "[pc]\t; "); 4756 if (NEGATIVE_BIT_SET) 4757 offset = -offset; 4758 info->print_address_func (offset + pc + 8, info); 4759 } 4760 else 4761 { 4762 /* Always show the offset. */ 4763 func (stream, "[pc], #%s%d", 4764 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4765 if (! allow_unpredictable) 4766 is_unpredictable = TRUE; 4767 } 4768 } 4769 else 4770 { 4771 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 4772 4773 func (stream, "[%s", 4774 arm_regnames[(given >> 16) & 0xf]); 4775 4776 if (PRE_BIT_SET) 4777 { 4778 if (IMMEDIATE_BIT_SET) 4779 { 4780 /* Elide offset for non-writeback 4781 positive zero. */ 4782 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 4783 || offset) 4784 func (stream, ", #%s%d", 4785 NEGATIVE_BIT_SET ? "-" : "", offset); 4786 4787 if (NEGATIVE_BIT_SET) 4788 offset = -offset; 4789 4790 value_in_comment = offset; 4791 } 4792 else 4793 { 4794 /* Register Offset or Register Pre-Indexed. */ 4795 func (stream, ", %s%s", 4796 NEGATIVE_BIT_SET ? "-" : "", 4797 arm_regnames[given & 0xf]); 4798 4799 /* Writing back to the register that is the source/ 4800 destination of the load/store is unpredictable. */ 4801 if (! allow_unpredictable 4802 && WRITEBACK_BIT_SET 4803 && ((given & 0xf) == ((given >> 12) & 0xf))) 4804 is_unpredictable = TRUE; 4805 } 4806 4807 func (stream, "]%s", 4808 WRITEBACK_BIT_SET ? "!" : ""); 4809 } 4810 else 4811 { 4812 if (IMMEDIATE_BIT_SET) 4813 { 4814 /* Immediate Post-indexed. */ 4815 /* PR 10924: Offset must be printed, even if it is zero. */ 4816 func (stream, "], #%s%d", 4817 NEGATIVE_BIT_SET ? "-" : "", offset); 4818 if (NEGATIVE_BIT_SET) 4819 offset = -offset; 4820 value_in_comment = offset; 4821 } 4822 else 4823 { 4824 /* Register Post-indexed. */ 4825 func (stream, "], %s%s", 4826 NEGATIVE_BIT_SET ? "-" : "", 4827 arm_regnames[given & 0xf]); 4828 4829 /* Writing back to the register that is the source/ 4830 destination of the load/store is unpredictable. */ 4831 if (! allow_unpredictable 4832 && (given & 0xf) == ((given >> 12) & 0xf)) 4833 is_unpredictable = TRUE; 4834 } 4835 4836 if (! allow_unpredictable) 4837 { 4838 /* Writeback is automatically implied by post- addressing. 4839 Setting the W bit is unnecessary and ARM specify it as 4840 being unpredictable. */ 4841 if (WRITEBACK_BIT_SET 4842 /* Specifying the PC register as the post-indexed 4843 registers is also unpredictable. */ 4844 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 4845 is_unpredictable = TRUE; 4846 } 4847 } 4848 } 4849 break; 4850 4851 case 'b': 4852 { 4853 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 4854 info->print_address_func (disp * 4 + pc + 8, info); 4855 } 4856 break; 4857 4858 case 'c': 4859 if (((given >> 28) & 0xf) != 0xe) 4860 func (stream, "%s", 4861 arm_conditional [(given >> 28) & 0xf]); 4862 break; 4863 4864 case 'm': 4865 { 4866 int started = 0; 4867 int reg; 4868 4869 func (stream, "{"); 4870 for (reg = 0; reg < 16; reg++) 4871 if ((given & (1 << reg)) != 0) 4872 { 4873 if (started) 4874 func (stream, ", "); 4875 started = 1; 4876 func (stream, "%s", arm_regnames[reg]); 4877 } 4878 func (stream, "}"); 4879 if (! started) 4880 is_unpredictable = TRUE; 4881 } 4882 break; 4883 4884 case 'q': 4885 arm_decode_shift (given, func, stream, FALSE); 4886 break; 4887 4888 case 'o': 4889 if ((given & 0x02000000) != 0) 4890 { 4891 unsigned int rotate = (given & 0xf00) >> 7; 4892 unsigned int immed = (given & 0xff); 4893 unsigned int a, i; 4894 4895 a = (((immed << (32 - rotate)) 4896 | (immed >> rotate)) & 0xffffffff); 4897 /* If there is another encoding with smaller rotate, 4898 the rotate should be specified directly. */ 4899 for (i = 0; i < 32; i += 2) 4900 if ((a << i | a >> (32 - i)) <= 0xff) 4901 break; 4902 4903 if (i != rotate) 4904 func (stream, "#%d, %d", immed, rotate); 4905 else 4906 func (stream, "#%d", a); 4907 value_in_comment = a; 4908 } 4909 else 4910 arm_decode_shift (given, func, stream, TRUE); 4911 break; 4912 4913 case 'p': 4914 if ((given & 0x0000f000) == 0x0000f000) 4915 { 4916 arm_feature_set arm_ext_v6 = 4917 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 4918 4919 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 4920 mechanism for setting PSR flag bits. They are 4921 obsolete in V6 onwards. */ 4922 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 4923 arm_ext_v6)) 4924 func (stream, "p"); 4925 else 4926 is_unpredictable = TRUE; 4927 } 4928 break; 4929 4930 case 't': 4931 if ((given & 0x01200000) == 0x00200000) 4932 func (stream, "t"); 4933 break; 4934 4935 case 'A': 4936 { 4937 int offset = given & 0xff; 4938 4939 value_in_comment = offset * 4; 4940 if (NEGATIVE_BIT_SET) 4941 value_in_comment = - value_in_comment; 4942 4943 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 4944 4945 if (PRE_BIT_SET) 4946 { 4947 if (offset) 4948 func (stream, ", #%d]%s", 4949 (int) value_in_comment, 4950 WRITEBACK_BIT_SET ? "!" : ""); 4951 else 4952 func (stream, "]"); 4953 } 4954 else 4955 { 4956 func (stream, "]"); 4957 4958 if (WRITEBACK_BIT_SET) 4959 { 4960 if (offset) 4961 func (stream, ", #%d", (int) value_in_comment); 4962 } 4963 else 4964 { 4965 func (stream, ", {%d}", (int) offset); 4966 value_in_comment = offset; 4967 } 4968 } 4969 } 4970 break; 4971 4972 case 'B': 4973 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 4974 { 4975 bfd_vma address; 4976 bfd_vma offset = 0; 4977 4978 if (! NEGATIVE_BIT_SET) 4979 /* Is signed, hi bits should be ones. */ 4980 offset = (-1) ^ 0x00ffffff; 4981 4982 /* Offset is (SignExtend(offset field)<<2). */ 4983 offset += given & 0x00ffffff; 4984 offset <<= 2; 4985 address = offset + pc + 8; 4986 4987 if (given & 0x01000000) 4988 /* H bit allows addressing to 2-byte boundaries. */ 4989 address += 2; 4990 4991 info->print_address_func (address, info); 4992 } 4993 break; 4994 4995 case 'C': 4996 if ((given & 0x02000200) == 0x200) 4997 { 4998 const char * name; 4999 unsigned sysm = (given & 0x004f0000) >> 16; 5000 5001 sysm |= (given & 0x300) >> 4; 5002 name = banked_regname (sysm); 5003 5004 if (name != NULL) 5005 func (stream, "%s", name); 5006 else 5007 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5008 } 5009 else 5010 { 5011 func (stream, "%cPSR_", 5012 (given & 0x00400000) ? 'S' : 'C'); 5013 if (given & 0x80000) 5014 func (stream, "f"); 5015 if (given & 0x40000) 5016 func (stream, "s"); 5017 if (given & 0x20000) 5018 func (stream, "x"); 5019 if (given & 0x10000) 5020 func (stream, "c"); 5021 } 5022 break; 5023 5024 case 'U': 5025 if ((given & 0xf0) == 0x60) 5026 { 5027 switch (given & 0xf) 5028 { 5029 case 0xf: func (stream, "sy"); break; 5030 default: 5031 func (stream, "#%d", (int) given & 0xf); 5032 break; 5033 } 5034 } 5035 else 5036 { 5037 const char * opt = data_barrier_option (given & 0xf); 5038 if (opt != NULL) 5039 func (stream, "%s", opt); 5040 else 5041 func (stream, "#%d", (int) given & 0xf); 5042 } 5043 break; 5044 5045 case '0': case '1': case '2': case '3': case '4': 5046 case '5': case '6': case '7': case '8': case '9': 5047 { 5048 int width; 5049 unsigned long value; 5050 5051 c = arm_decode_bitfield (c, given, &value, &width); 5052 5053 switch (*c) 5054 { 5055 case 'R': 5056 if (value == 15) 5057 is_unpredictable = TRUE; 5058 /* Fall through. */ 5059 case 'r': 5060 case 'T': 5061 /* We want register + 1 when decoding T. */ 5062 if (*c == 'T') 5063 ++value; 5064 5065 if (c[1] == 'u') 5066 { 5067 /* Eat the 'u' character. */ 5068 ++ c; 5069 5070 if (u_reg == value) 5071 is_unpredictable = TRUE; 5072 u_reg = value; 5073 } 5074 if (c[1] == 'U') 5075 { 5076 /* Eat the 'U' character. */ 5077 ++ c; 5078 5079 if (U_reg == value) 5080 is_unpredictable = TRUE; 5081 U_reg = value; 5082 } 5083 func (stream, "%s", arm_regnames[value]); 5084 break; 5085 case 'd': 5086 func (stream, "%ld", value); 5087 value_in_comment = value; 5088 break; 5089 case 'b': 5090 func (stream, "%ld", value * 8); 5091 value_in_comment = value * 8; 5092 break; 5093 case 'W': 5094 func (stream, "%ld", value + 1); 5095 value_in_comment = value + 1; 5096 break; 5097 case 'x': 5098 func (stream, "0x%08lx", value); 5099 5100 /* Some SWI instructions have special 5101 meanings. */ 5102 if ((given & 0x0fffffff) == 0x0FF00000) 5103 func (stream, "\t; IMB"); 5104 else if ((given & 0x0fffffff) == 0x0FF00001) 5105 func (stream, "\t; IMBRange"); 5106 break; 5107 case 'X': 5108 func (stream, "%01lx", value & 0xf); 5109 value_in_comment = value; 5110 break; 5111 case '`': 5112 c++; 5113 if (value == 0) 5114 func (stream, "%c", *c); 5115 break; 5116 case '\'': 5117 c++; 5118 if (value == ((1ul << width) - 1)) 5119 func (stream, "%c", *c); 5120 break; 5121 case '?': 5122 func (stream, "%c", c[(1 << width) - (int) value]); 5123 c += 1 << width; 5124 break; 5125 default: 5126 abort (); 5127 } 5128 break; 5129 5130 case 'e': 5131 { 5132 int imm; 5133 5134 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 5135 func (stream, "%d", imm); 5136 value_in_comment = imm; 5137 } 5138 break; 5139 5140 case 'E': 5141 /* LSB and WIDTH fields of BFI or BFC. The machine- 5142 language instruction encodes LSB and MSB. */ 5143 { 5144 long msb = (given & 0x001f0000) >> 16; 5145 long lsb = (given & 0x00000f80) >> 7; 5146 long w = msb - lsb + 1; 5147 5148 if (w > 0) 5149 func (stream, "#%lu, #%lu", lsb, w); 5150 else 5151 func (stream, "(invalid: %lu:%lu)", lsb, msb); 5152 } 5153 break; 5154 5155 case 'R': 5156 /* Get the PSR/banked register name. */ 5157 { 5158 const char * name; 5159 unsigned sysm = (given & 0x004f0000) >> 16; 5160 5161 sysm |= (given & 0x300) >> 4; 5162 name = banked_regname (sysm); 5163 5164 if (name != NULL) 5165 func (stream, "%s", name); 5166 else 5167 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5168 } 5169 break; 5170 5171 case 'V': 5172 /* 16-bit unsigned immediate from a MOVT or MOVW 5173 instruction, encoded in bits 0:11 and 15:19. */ 5174 { 5175 long hi = (given & 0x000f0000) >> 4; 5176 long lo = (given & 0x00000fff); 5177 long imm16 = hi | lo; 5178 5179 func (stream, "#%lu", imm16); 5180 value_in_comment = imm16; 5181 } 5182 break; 5183 5184 default: 5185 abort (); 5186 } 5187 } 5188 } 5189 else 5190 func (stream, "%c", *c); 5191 } 5192 5193 if (value_in_comment > 32 || value_in_comment < -16) 5194 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 5195 5196 if (is_unpredictable) 5197 func (stream, UNPREDICTABLE_INSTRUCTION); 5198 5199 return; 5200 } 5201 } 5202 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 5203 return; 5204 } 5205 5206 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 5207 5208 static void 5209 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 5210 { 5211 const struct opcode16 *insn; 5212 void *stream = info->stream; 5213 fprintf_ftype func = info->fprintf_func; 5214 5215 for (insn = thumb_opcodes; insn->assembler; insn++) 5216 if ((given & insn->mask) == insn->value) 5217 { 5218 signed long value_in_comment = 0; 5219 const char *c = insn->assembler; 5220 5221 for (; *c; c++) 5222 { 5223 int domaskpc = 0; 5224 int domasklr = 0; 5225 5226 if (*c != '%') 5227 { 5228 func (stream, "%c", *c); 5229 continue; 5230 } 5231 5232 switch (*++c) 5233 { 5234 case '%': 5235 func (stream, "%%"); 5236 break; 5237 5238 case 'c': 5239 if (ifthen_state) 5240 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5241 break; 5242 5243 case 'C': 5244 if (ifthen_state) 5245 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5246 else 5247 func (stream, "s"); 5248 break; 5249 5250 case 'I': 5251 { 5252 unsigned int tmp; 5253 5254 ifthen_next_state = given & 0xff; 5255 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 5256 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 5257 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 5258 } 5259 break; 5260 5261 case 'x': 5262 if (ifthen_next_state) 5263 func (stream, "\t; unpredictable branch in IT block\n"); 5264 break; 5265 5266 case 'X': 5267 if (ifthen_state) 5268 func (stream, "\t; unpredictable <IT:%s>", 5269 arm_conditional[IFTHEN_COND]); 5270 break; 5271 5272 case 'S': 5273 { 5274 long reg; 5275 5276 reg = (given >> 3) & 0x7; 5277 if (given & (1 << 6)) 5278 reg += 8; 5279 5280 func (stream, "%s", arm_regnames[reg]); 5281 } 5282 break; 5283 5284 case 'D': 5285 { 5286 long reg; 5287 5288 reg = given & 0x7; 5289 if (given & (1 << 7)) 5290 reg += 8; 5291 5292 func (stream, "%s", arm_regnames[reg]); 5293 } 5294 break; 5295 5296 case 'N': 5297 if (given & (1 << 8)) 5298 domasklr = 1; 5299 /* Fall through. */ 5300 case 'O': 5301 if (*c == 'O' && (given & (1 << 8))) 5302 domaskpc = 1; 5303 /* Fall through. */ 5304 case 'M': 5305 { 5306 int started = 0; 5307 int reg; 5308 5309 func (stream, "{"); 5310 5311 /* It would be nice if we could spot 5312 ranges, and generate the rS-rE format: */ 5313 for (reg = 0; (reg < 8); reg++) 5314 if ((given & (1 << reg)) != 0) 5315 { 5316 if (started) 5317 func (stream, ", "); 5318 started = 1; 5319 func (stream, "%s", arm_regnames[reg]); 5320 } 5321 5322 if (domasklr) 5323 { 5324 if (started) 5325 func (stream, ", "); 5326 started = 1; 5327 func (stream, "%s", arm_regnames[14] /* "lr" */); 5328 } 5329 5330 if (domaskpc) 5331 { 5332 if (started) 5333 func (stream, ", "); 5334 func (stream, "%s", arm_regnames[15] /* "pc" */); 5335 } 5336 5337 func (stream, "}"); 5338 } 5339 break; 5340 5341 case 'W': 5342 /* Print writeback indicator for a LDMIA. We are doing a 5343 writeback if the base register is not in the register 5344 mask. */ 5345 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 5346 func (stream, "!"); 5347 break; 5348 5349 case 'b': 5350 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 5351 { 5352 bfd_vma address = (pc + 4 5353 + ((given & 0x00f8) >> 2) 5354 + ((given & 0x0200) >> 3)); 5355 info->print_address_func (address, info); 5356 } 5357 break; 5358 5359 case 's': 5360 /* Right shift immediate -- bits 6..10; 1-31 print 5361 as themselves, 0 prints as 32. */ 5362 { 5363 long imm = (given & 0x07c0) >> 6; 5364 if (imm == 0) 5365 imm = 32; 5366 func (stream, "#%ld", imm); 5367 } 5368 break; 5369 5370 case '0': case '1': case '2': case '3': case '4': 5371 case '5': case '6': case '7': case '8': case '9': 5372 { 5373 int bitstart = *c++ - '0'; 5374 int bitend = 0; 5375 5376 while (*c >= '0' && *c <= '9') 5377 bitstart = (bitstart * 10) + *c++ - '0'; 5378 5379 switch (*c) 5380 { 5381 case '-': 5382 { 5383 bfd_vma reg; 5384 5385 c++; 5386 while (*c >= '0' && *c <= '9') 5387 bitend = (bitend * 10) + *c++ - '0'; 5388 if (!bitend) 5389 abort (); 5390 reg = given >> bitstart; 5391 reg &= (2 << (bitend - bitstart)) - 1; 5392 5393 switch (*c) 5394 { 5395 case 'r': 5396 func (stream, "%s", arm_regnames[reg]); 5397 break; 5398 5399 case 'd': 5400 func (stream, "%ld", (long) reg); 5401 value_in_comment = reg; 5402 break; 5403 5404 case 'H': 5405 func (stream, "%ld", (long) (reg << 1)); 5406 value_in_comment = reg << 1; 5407 break; 5408 5409 case 'W': 5410 func (stream, "%ld", (long) (reg << 2)); 5411 value_in_comment = reg << 2; 5412 break; 5413 5414 case 'a': 5415 /* PC-relative address -- the bottom two 5416 bits of the address are dropped 5417 before the calculation. */ 5418 info->print_address_func 5419 (((pc + 4) & ~3) + (reg << 2), info); 5420 value_in_comment = 0; 5421 break; 5422 5423 case 'x': 5424 func (stream, "0x%04lx", (long) reg); 5425 break; 5426 5427 case 'B': 5428 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 5429 info->print_address_func (reg * 2 + pc + 4, info); 5430 value_in_comment = 0; 5431 break; 5432 5433 case 'c': 5434 func (stream, "%s", arm_conditional [reg]); 5435 break; 5436 5437 default: 5438 abort (); 5439 } 5440 } 5441 break; 5442 5443 case '\'': 5444 c++; 5445 if ((given & (1 << bitstart)) != 0) 5446 func (stream, "%c", *c); 5447 break; 5448 5449 case '?': 5450 ++c; 5451 if ((given & (1 << bitstart)) != 0) 5452 func (stream, "%c", *c++); 5453 else 5454 func (stream, "%c", *++c); 5455 break; 5456 5457 default: 5458 abort (); 5459 } 5460 } 5461 break; 5462 5463 default: 5464 abort (); 5465 } 5466 } 5467 5468 if (value_in_comment > 32 || value_in_comment < -16) 5469 func (stream, "\t; 0x%lx", value_in_comment); 5470 return; 5471 } 5472 5473 /* No match. */ 5474 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given); 5475 return; 5476 } 5477 5478 /* Return the name of an V7M special register. */ 5479 5480 static const char * 5481 psr_name (int regno) 5482 { 5483 switch (regno) 5484 { 5485 case 0x0: return "APSR"; 5486 case 0x1: return "IAPSR"; 5487 case 0x2: return "EAPSR"; 5488 case 0x3: return "PSR"; 5489 case 0x5: return "IPSR"; 5490 case 0x6: return "EPSR"; 5491 case 0x7: return "IEPSR"; 5492 case 0x8: return "MSP"; 5493 case 0x9: return "PSP"; 5494 case 0xa: return "MSPLIM"; 5495 case 0xb: return "PSPLIM"; 5496 case 0x10: return "PRIMASK"; 5497 case 0x11: return "BASEPRI"; 5498 case 0x12: return "BASEPRI_MAX"; 5499 case 0x13: return "FAULTMASK"; 5500 case 0x14: return "CONTROL"; 5501 case 0x88: return "MSP_NS"; 5502 case 0x89: return "PSP_NS"; 5503 case 0x8a: return "MSPLIM_NS"; 5504 case 0x8b: return "PSPLIM_NS"; 5505 case 0x90: return "PRIMASK_NS"; 5506 case 0x91: return "BASEPRI_NS"; 5507 case 0x93: return "FAULTMASK_NS"; 5508 case 0x94: return "CONTROL_NS"; 5509 case 0x98: return "SP_NS"; 5510 default: return "<unknown>"; 5511 } 5512 } 5513 5514 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 5515 5516 static void 5517 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 5518 { 5519 const struct opcode32 *insn; 5520 void *stream = info->stream; 5521 fprintf_ftype func = info->fprintf_func; 5522 5523 if (print_insn_coprocessor (pc, info, given, TRUE)) 5524 return; 5525 5526 if (print_insn_neon (info, given, TRUE)) 5527 return; 5528 5529 for (insn = thumb32_opcodes; insn->assembler; insn++) 5530 if ((given & insn->mask) == insn->value) 5531 { 5532 bfd_boolean is_unpredictable = FALSE; 5533 signed long value_in_comment = 0; 5534 const char *c = insn->assembler; 5535 5536 for (; *c; c++) 5537 { 5538 if (*c != '%') 5539 { 5540 func (stream, "%c", *c); 5541 continue; 5542 } 5543 5544 switch (*++c) 5545 { 5546 case '%': 5547 func (stream, "%%"); 5548 break; 5549 5550 case 'c': 5551 if (ifthen_state) 5552 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5553 break; 5554 5555 case 'x': 5556 if (ifthen_next_state) 5557 func (stream, "\t; unpredictable branch in IT block\n"); 5558 break; 5559 5560 case 'X': 5561 if (ifthen_state) 5562 func (stream, "\t; unpredictable <IT:%s>", 5563 arm_conditional[IFTHEN_COND]); 5564 break; 5565 5566 case 'I': 5567 { 5568 unsigned int imm12 = 0; 5569 5570 imm12 |= (given & 0x000000ffu); 5571 imm12 |= (given & 0x00007000u) >> 4; 5572 imm12 |= (given & 0x04000000u) >> 15; 5573 func (stream, "#%u", imm12); 5574 value_in_comment = imm12; 5575 } 5576 break; 5577 5578 case 'M': 5579 { 5580 unsigned int bits = 0, imm, imm8, mod; 5581 5582 bits |= (given & 0x000000ffu); 5583 bits |= (given & 0x00007000u) >> 4; 5584 bits |= (given & 0x04000000u) >> 15; 5585 imm8 = (bits & 0x0ff); 5586 mod = (bits & 0xf00) >> 8; 5587 switch (mod) 5588 { 5589 case 0: imm = imm8; break; 5590 case 1: imm = ((imm8 << 16) | imm8); break; 5591 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 5592 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 5593 default: 5594 mod = (bits & 0xf80) >> 7; 5595 imm8 = (bits & 0x07f) | 0x80; 5596 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 5597 } 5598 func (stream, "#%u", imm); 5599 value_in_comment = imm; 5600 } 5601 break; 5602 5603 case 'J': 5604 { 5605 unsigned int imm = 0; 5606 5607 imm |= (given & 0x000000ffu); 5608 imm |= (given & 0x00007000u) >> 4; 5609 imm |= (given & 0x04000000u) >> 15; 5610 imm |= (given & 0x000f0000u) >> 4; 5611 func (stream, "#%u", imm); 5612 value_in_comment = imm; 5613 } 5614 break; 5615 5616 case 'K': 5617 { 5618 unsigned int imm = 0; 5619 5620 imm |= (given & 0x000f0000u) >> 16; 5621 imm |= (given & 0x00000ff0u) >> 0; 5622 imm |= (given & 0x0000000fu) << 12; 5623 func (stream, "#%u", imm); 5624 value_in_comment = imm; 5625 } 5626 break; 5627 5628 case 'H': 5629 { 5630 unsigned int imm = 0; 5631 5632 imm |= (given & 0x000f0000u) >> 4; 5633 imm |= (given & 0x00000fffu) >> 0; 5634 func (stream, "#%u", imm); 5635 value_in_comment = imm; 5636 } 5637 break; 5638 5639 case 'V': 5640 { 5641 unsigned int imm = 0; 5642 5643 imm |= (given & 0x00000fffu); 5644 imm |= (given & 0x000f0000u) >> 4; 5645 func (stream, "#%u", imm); 5646 value_in_comment = imm; 5647 } 5648 break; 5649 5650 case 'S': 5651 { 5652 unsigned int reg = (given & 0x0000000fu); 5653 unsigned int stp = (given & 0x00000030u) >> 4; 5654 unsigned int imm = 0; 5655 imm |= (given & 0x000000c0u) >> 6; 5656 imm |= (given & 0x00007000u) >> 10; 5657 5658 func (stream, "%s", arm_regnames[reg]); 5659 switch (stp) 5660 { 5661 case 0: 5662 if (imm > 0) 5663 func (stream, ", lsl #%u", imm); 5664 break; 5665 5666 case 1: 5667 if (imm == 0) 5668 imm = 32; 5669 func (stream, ", lsr #%u", imm); 5670 break; 5671 5672 case 2: 5673 if (imm == 0) 5674 imm = 32; 5675 func (stream, ", asr #%u", imm); 5676 break; 5677 5678 case 3: 5679 if (imm == 0) 5680 func (stream, ", rrx"); 5681 else 5682 func (stream, ", ror #%u", imm); 5683 } 5684 } 5685 break; 5686 5687 case 'a': 5688 { 5689 unsigned int Rn = (given & 0x000f0000) >> 16; 5690 unsigned int U = ! NEGATIVE_BIT_SET; 5691 unsigned int op = (given & 0x00000f00) >> 8; 5692 unsigned int i12 = (given & 0x00000fff); 5693 unsigned int i8 = (given & 0x000000ff); 5694 bfd_boolean writeback = FALSE, postind = FALSE; 5695 bfd_vma offset = 0; 5696 5697 func (stream, "[%s", arm_regnames[Rn]); 5698 if (U) /* 12-bit positive immediate offset. */ 5699 { 5700 offset = i12; 5701 if (Rn != 15) 5702 value_in_comment = offset; 5703 } 5704 else if (Rn == 15) /* 12-bit negative immediate offset. */ 5705 offset = - (int) i12; 5706 else if (op == 0x0) /* Shifted register offset. */ 5707 { 5708 unsigned int Rm = (i8 & 0x0f); 5709 unsigned int sh = (i8 & 0x30) >> 4; 5710 5711 func (stream, ", %s", arm_regnames[Rm]); 5712 if (sh) 5713 func (stream, ", lsl #%u", sh); 5714 func (stream, "]"); 5715 break; 5716 } 5717 else switch (op) 5718 { 5719 case 0xE: /* 8-bit positive immediate offset. */ 5720 offset = i8; 5721 break; 5722 5723 case 0xC: /* 8-bit negative immediate offset. */ 5724 offset = -i8; 5725 break; 5726 5727 case 0xF: /* 8-bit + preindex with wb. */ 5728 offset = i8; 5729 writeback = TRUE; 5730 break; 5731 5732 case 0xD: /* 8-bit - preindex with wb. */ 5733 offset = -i8; 5734 writeback = TRUE; 5735 break; 5736 5737 case 0xB: /* 8-bit + postindex. */ 5738 offset = i8; 5739 postind = TRUE; 5740 break; 5741 5742 case 0x9: /* 8-bit - postindex. */ 5743 offset = -i8; 5744 postind = TRUE; 5745 break; 5746 5747 default: 5748 func (stream, ", <undefined>]"); 5749 goto skip; 5750 } 5751 5752 if (postind) 5753 func (stream, "], #%d", (int) offset); 5754 else 5755 { 5756 if (offset) 5757 func (stream, ", #%d", (int) offset); 5758 func (stream, writeback ? "]!" : "]"); 5759 } 5760 5761 if (Rn == 15) 5762 { 5763 func (stream, "\t; "); 5764 info->print_address_func (((pc + 4) & ~3) + offset, info); 5765 } 5766 } 5767 skip: 5768 break; 5769 5770 case 'A': 5771 { 5772 unsigned int U = ! NEGATIVE_BIT_SET; 5773 unsigned int W = WRITEBACK_BIT_SET; 5774 unsigned int Rn = (given & 0x000f0000) >> 16; 5775 unsigned int off = (given & 0x000000ff); 5776 5777 func (stream, "[%s", arm_regnames[Rn]); 5778 5779 if (PRE_BIT_SET) 5780 { 5781 if (off || !U) 5782 { 5783 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 5784 value_in_comment = off * 4 * (U ? 1 : -1); 5785 } 5786 func (stream, "]"); 5787 if (W) 5788 func (stream, "!"); 5789 } 5790 else 5791 { 5792 func (stream, "], "); 5793 if (W) 5794 { 5795 func (stream, "#%c%u", U ? '+' : '-', off * 4); 5796 value_in_comment = off * 4 * (U ? 1 : -1); 5797 } 5798 else 5799 { 5800 func (stream, "{%u}", off); 5801 value_in_comment = off; 5802 } 5803 } 5804 } 5805 break; 5806 5807 case 'w': 5808 { 5809 unsigned int Sbit = (given & 0x01000000) >> 24; 5810 unsigned int type = (given & 0x00600000) >> 21; 5811 5812 switch (type) 5813 { 5814 case 0: func (stream, Sbit ? "sb" : "b"); break; 5815 case 1: func (stream, Sbit ? "sh" : "h"); break; 5816 case 2: 5817 if (Sbit) 5818 func (stream, "??"); 5819 break; 5820 case 3: 5821 func (stream, "??"); 5822 break; 5823 } 5824 } 5825 break; 5826 5827 case 'm': 5828 { 5829 int started = 0; 5830 int reg; 5831 5832 func (stream, "{"); 5833 for (reg = 0; reg < 16; reg++) 5834 if ((given & (1 << reg)) != 0) 5835 { 5836 if (started) 5837 func (stream, ", "); 5838 started = 1; 5839 func (stream, "%s", arm_regnames[reg]); 5840 } 5841 func (stream, "}"); 5842 } 5843 break; 5844 5845 case 'E': 5846 { 5847 unsigned int msb = (given & 0x0000001f); 5848 unsigned int lsb = 0; 5849 5850 lsb |= (given & 0x000000c0u) >> 6; 5851 lsb |= (given & 0x00007000u) >> 10; 5852 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 5853 } 5854 break; 5855 5856 case 'F': 5857 { 5858 unsigned int width = (given & 0x0000001f) + 1; 5859 unsigned int lsb = 0; 5860 5861 lsb |= (given & 0x000000c0u) >> 6; 5862 lsb |= (given & 0x00007000u) >> 10; 5863 func (stream, "#%u, #%u", lsb, width); 5864 } 5865 break; 5866 5867 case 'b': 5868 { 5869 unsigned int S = (given & 0x04000000u) >> 26; 5870 unsigned int J1 = (given & 0x00002000u) >> 13; 5871 unsigned int J2 = (given & 0x00000800u) >> 11; 5872 bfd_vma offset = 0; 5873 5874 offset |= !S << 20; 5875 offset |= J2 << 19; 5876 offset |= J1 << 18; 5877 offset |= (given & 0x003f0000) >> 4; 5878 offset |= (given & 0x000007ff) << 1; 5879 offset -= (1 << 20); 5880 5881 info->print_address_func (pc + 4 + offset, info); 5882 } 5883 break; 5884 5885 case 'B': 5886 { 5887 unsigned int S = (given & 0x04000000u) >> 26; 5888 unsigned int I1 = (given & 0x00002000u) >> 13; 5889 unsigned int I2 = (given & 0x00000800u) >> 11; 5890 bfd_vma offset = 0; 5891 5892 offset |= !S << 24; 5893 offset |= !(I1 ^ S) << 23; 5894 offset |= !(I2 ^ S) << 22; 5895 offset |= (given & 0x03ff0000u) >> 4; 5896 offset |= (given & 0x000007ffu) << 1; 5897 offset -= (1 << 24); 5898 offset += pc + 4; 5899 5900 /* BLX target addresses are always word aligned. */ 5901 if ((given & 0x00001000u) == 0) 5902 offset &= ~2u; 5903 5904 info->print_address_func (offset, info); 5905 } 5906 break; 5907 5908 case 's': 5909 { 5910 unsigned int shift = 0; 5911 5912 shift |= (given & 0x000000c0u) >> 6; 5913 shift |= (given & 0x00007000u) >> 10; 5914 if (WRITEBACK_BIT_SET) 5915 func (stream, ", asr #%u", shift); 5916 else if (shift) 5917 func (stream, ", lsl #%u", shift); 5918 /* else print nothing - lsl #0 */ 5919 } 5920 break; 5921 5922 case 'R': 5923 { 5924 unsigned int rot = (given & 0x00000030) >> 4; 5925 5926 if (rot) 5927 func (stream, ", ror #%u", rot * 8); 5928 } 5929 break; 5930 5931 case 'U': 5932 if ((given & 0xf0) == 0x60) 5933 { 5934 switch (given & 0xf) 5935 { 5936 case 0xf: func (stream, "sy"); break; 5937 default: 5938 func (stream, "#%d", (int) given & 0xf); 5939 break; 5940 } 5941 } 5942 else 5943 { 5944 const char * opt = data_barrier_option (given & 0xf); 5945 if (opt != NULL) 5946 func (stream, "%s", opt); 5947 else 5948 func (stream, "#%d", (int) given & 0xf); 5949 } 5950 break; 5951 5952 case 'C': 5953 if ((given & 0xff) == 0) 5954 { 5955 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 5956 if (given & 0x800) 5957 func (stream, "f"); 5958 if (given & 0x400) 5959 func (stream, "s"); 5960 if (given & 0x200) 5961 func (stream, "x"); 5962 if (given & 0x100) 5963 func (stream, "c"); 5964 } 5965 else if ((given & 0x20) == 0x20) 5966 { 5967 char const* name; 5968 unsigned sysm = (given & 0xf00) >> 8; 5969 5970 sysm |= (given & 0x30); 5971 sysm |= (given & 0x00100000) >> 14; 5972 name = banked_regname (sysm); 5973 5974 if (name != NULL) 5975 func (stream, "%s", name); 5976 else 5977 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5978 } 5979 else 5980 { 5981 func (stream, "%s", psr_name (given & 0xff)); 5982 } 5983 break; 5984 5985 case 'D': 5986 if (((given & 0xff) == 0) 5987 || ((given & 0x20) == 0x20)) 5988 { 5989 char const* name; 5990 unsigned sm = (given & 0xf0000) >> 16; 5991 5992 sm |= (given & 0x30); 5993 sm |= (given & 0x00100000) >> 14; 5994 name = banked_regname (sm); 5995 5996 if (name != NULL) 5997 func (stream, "%s", name); 5998 else 5999 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 6000 } 6001 else 6002 func (stream, "%s", psr_name (given & 0xff)); 6003 break; 6004 6005 case '0': case '1': case '2': case '3': case '4': 6006 case '5': case '6': case '7': case '8': case '9': 6007 { 6008 int width; 6009 unsigned long val; 6010 6011 c = arm_decode_bitfield (c, given, &val, &width); 6012 6013 switch (*c) 6014 { 6015 case 'd': 6016 func (stream, "%lu", val); 6017 value_in_comment = val; 6018 break; 6019 6020 case 'D': 6021 func (stream, "%lu", val + 1); 6022 value_in_comment = val + 1; 6023 break; 6024 6025 case 'W': 6026 func (stream, "%lu", val * 4); 6027 value_in_comment = val * 4; 6028 break; 6029 6030 case 'R': 6031 if (val == 15) 6032 is_unpredictable = TRUE; 6033 /* Fall through. */ 6034 case 'r': 6035 func (stream, "%s", arm_regnames[val]); 6036 break; 6037 6038 case 'c': 6039 func (stream, "%s", arm_conditional[val]); 6040 break; 6041 6042 case '\'': 6043 c++; 6044 if (val == ((1ul << width) - 1)) 6045 func (stream, "%c", *c); 6046 break; 6047 6048 case '`': 6049 c++; 6050 if (val == 0) 6051 func (stream, "%c", *c); 6052 break; 6053 6054 case '?': 6055 func (stream, "%c", c[(1 << width) - (int) val]); 6056 c += 1 << width; 6057 break; 6058 6059 case 'x': 6060 func (stream, "0x%lx", val & 0xffffffffUL); 6061 break; 6062 6063 default: 6064 abort (); 6065 } 6066 } 6067 break; 6068 6069 case 'L': 6070 /* PR binutils/12534 6071 If we have a PC relative offset in an LDRD or STRD 6072 instructions then display the decoded address. */ 6073 if (((given >> 16) & 0xf) == 0xf) 6074 { 6075 bfd_vma offset = (given & 0xff) * 4; 6076 6077 if ((given & (1 << 23)) == 0) 6078 offset = - offset; 6079 func (stream, "\t; "); 6080 info->print_address_func ((pc & ~3) + 4 + offset, info); 6081 } 6082 break; 6083 6084 default: 6085 abort (); 6086 } 6087 } 6088 6089 if (value_in_comment > 32 || value_in_comment < -16) 6090 func (stream, "\t; 0x%lx", value_in_comment); 6091 6092 if (is_unpredictable) 6093 func (stream, UNPREDICTABLE_INSTRUCTION); 6094 6095 return; 6096 } 6097 6098 /* No match. */ 6099 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 6100 return; 6101 } 6102 6103 /* Print data bytes on INFO->STREAM. */ 6104 6105 static void 6106 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 6107 struct disassemble_info *info, 6108 long given) 6109 { 6110 switch (info->bytes_per_chunk) 6111 { 6112 case 1: 6113 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 6114 break; 6115 case 2: 6116 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 6117 break; 6118 case 4: 6119 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 6120 break; 6121 default: 6122 abort (); 6123 } 6124 } 6125 6126 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 6127 being displayed in symbol relative addresses. 6128 6129 Also disallow private symbol, with __tagsym$$ prefix, 6130 from ARM RVCT toolchain being displayed. */ 6131 6132 bfd_boolean 6133 arm_symbol_is_valid (asymbol * sym, 6134 struct disassemble_info * info ATTRIBUTE_UNUSED) 6135 { 6136 const char * name; 6137 6138 if (sym == NULL) 6139 return FALSE; 6140 6141 name = bfd_asymbol_name (sym); 6142 6143 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 6144 } 6145 6146 /* Parse the string of disassembler options. */ 6147 6148 static void 6149 parse_arm_disassembler_options (const char *options) 6150 { 6151 const char *opt; 6152 6153 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 6154 { 6155 if (CONST_STRNEQ (opt, "reg-names-")) 6156 { 6157 unsigned int i; 6158 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6159 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 6160 { 6161 regname_selected = i; 6162 break; 6163 } 6164 6165 if (i >= NUM_ARM_OPTIONS) 6166 /* xgettext: c-format */ 6167 opcodes_error_handler (_("unrecognised register name set: %s"), 6168 opt); 6169 } 6170 else if (CONST_STRNEQ (opt, "force-thumb")) 6171 force_thumb = 1; 6172 else if (CONST_STRNEQ (opt, "no-force-thumb")) 6173 force_thumb = 0; 6174 else 6175 /* xgettext: c-format */ 6176 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 6177 } 6178 6179 return; 6180 } 6181 6182 static bfd_boolean 6183 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6184 enum map_type *map_symbol); 6185 6186 /* Search back through the insn stream to determine if this instruction is 6187 conditionally executed. */ 6188 6189 static void 6190 find_ifthen_state (bfd_vma pc, 6191 struct disassemble_info *info, 6192 bfd_boolean little) 6193 { 6194 unsigned char b[2]; 6195 unsigned int insn; 6196 int status; 6197 /* COUNT is twice the number of instructions seen. It will be odd if we 6198 just crossed an instruction boundary. */ 6199 int count; 6200 int it_count; 6201 unsigned int seen_it; 6202 bfd_vma addr; 6203 6204 ifthen_address = pc; 6205 ifthen_state = 0; 6206 6207 addr = pc; 6208 count = 1; 6209 it_count = 0; 6210 seen_it = 0; 6211 /* Scan backwards looking for IT instructions, keeping track of where 6212 instruction boundaries are. We don't know if something is actually an 6213 IT instruction until we find a definite instruction boundary. */ 6214 for (;;) 6215 { 6216 if (addr == 0 || info->symbol_at_address_func (addr, info)) 6217 { 6218 /* A symbol must be on an instruction boundary, and will not 6219 be within an IT block. */ 6220 if (seen_it && (count & 1)) 6221 break; 6222 6223 return; 6224 } 6225 addr -= 2; 6226 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 6227 if (status) 6228 return; 6229 6230 if (little) 6231 insn = (b[0]) | (b[1] << 8); 6232 else 6233 insn = (b[1]) | (b[0] << 8); 6234 if (seen_it) 6235 { 6236 if ((insn & 0xf800) < 0xe800) 6237 { 6238 /* Addr + 2 is an instruction boundary. See if this matches 6239 the expected boundary based on the position of the last 6240 IT candidate. */ 6241 if (count & 1) 6242 break; 6243 seen_it = 0; 6244 } 6245 } 6246 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 6247 { 6248 enum map_type type = MAP_ARM; 6249 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 6250 6251 if (!found || (found && type == MAP_THUMB)) 6252 { 6253 /* This could be an IT instruction. */ 6254 seen_it = insn; 6255 it_count = count >> 1; 6256 } 6257 } 6258 if ((insn & 0xf800) >= 0xe800) 6259 count++; 6260 else 6261 count = (count + 2) | 1; 6262 /* IT blocks contain at most 4 instructions. */ 6263 if (count >= 8 && !seen_it) 6264 return; 6265 } 6266 /* We found an IT instruction. */ 6267 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 6268 if ((ifthen_state & 0xf) == 0) 6269 ifthen_state = 0; 6270 } 6271 6272 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 6273 mapping symbol. */ 6274 6275 static int 6276 is_mapping_symbol (struct disassemble_info *info, int n, 6277 enum map_type *map_type) 6278 { 6279 const char *name; 6280 6281 name = bfd_asymbol_name (info->symtab[n]); 6282 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 6283 && (name[2] == 0 || name[2] == '.')) 6284 { 6285 *map_type = ((name[1] == 'a') ? MAP_ARM 6286 : (name[1] == 't') ? MAP_THUMB 6287 : MAP_DATA); 6288 return TRUE; 6289 } 6290 6291 return FALSE; 6292 } 6293 6294 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 6295 Returns nonzero if *MAP_TYPE was set. */ 6296 6297 static int 6298 get_map_sym_type (struct disassemble_info *info, 6299 int n, 6300 enum map_type *map_type) 6301 { 6302 /* If the symbol is in a different section, ignore it. */ 6303 if (info->section != NULL && info->section != info->symtab[n]->section) 6304 return FALSE; 6305 6306 return is_mapping_symbol (info, n, map_type); 6307 } 6308 6309 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 6310 Returns nonzero if *MAP_TYPE was set. */ 6311 6312 static int 6313 get_sym_code_type (struct disassemble_info *info, 6314 int n, 6315 enum map_type *map_type) 6316 { 6317 elf_symbol_type *es; 6318 unsigned int type; 6319 6320 /* If the symbol is in a different section, ignore it. */ 6321 if (info->section != NULL && info->section != info->symtab[n]->section) 6322 return FALSE; 6323 6324 es = *(elf_symbol_type **)(info->symtab + n); 6325 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6326 6327 /* If the symbol has function type then use that. */ 6328 if (type == STT_FUNC || type == STT_GNU_IFUNC) 6329 { 6330 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6331 == ST_BRANCH_TO_THUMB) 6332 *map_type = MAP_THUMB; 6333 else 6334 *map_type = MAP_ARM; 6335 return TRUE; 6336 } 6337 6338 return FALSE; 6339 } 6340 6341 /* Search the mapping symbol state for instruction at pc. This is only 6342 applicable for elf target. 6343 6344 There is an assumption Here, info->private_data contains the correct AND 6345 up-to-date information about current scan process. The information will be 6346 used to speed this search process. 6347 6348 Return TRUE if the mapping state can be determined, and map_symbol 6349 will be updated accordingly. Otherwise, return FALSE. */ 6350 6351 static bfd_boolean 6352 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6353 enum map_type *map_symbol) 6354 { 6355 bfd_vma addr; 6356 int n, start = 0; 6357 bfd_boolean found = FALSE; 6358 enum map_type type = MAP_ARM; 6359 struct arm_private_data *private_data; 6360 6361 if (info->private_data == NULL || info->symtab_size == 0 6362 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 6363 return FALSE; 6364 6365 private_data = info->private_data; 6366 if (pc == 0) 6367 start = 0; 6368 else 6369 start = private_data->last_mapping_sym; 6370 6371 start = (start == -1)? 0 : start; 6372 addr = bfd_asymbol_value (info->symtab[start]); 6373 6374 if (pc >= addr) 6375 { 6376 if (get_map_sym_type (info, start, &type)) 6377 found = TRUE; 6378 } 6379 else 6380 { 6381 for (n = start - 1; n >= 0; n--) 6382 { 6383 if (get_map_sym_type (info, n, &type)) 6384 { 6385 found = TRUE; 6386 break; 6387 } 6388 } 6389 } 6390 6391 /* No mapping symbols were found. A leading $d may be 6392 omitted for sections which start with data; but for 6393 compatibility with legacy and stripped binaries, only 6394 assume the leading $d if there is at least one mapping 6395 symbol in the file. */ 6396 if (!found && private_data->has_mapping_symbols == 1) 6397 { 6398 type = MAP_DATA; 6399 found = TRUE; 6400 } 6401 6402 *map_symbol = type; 6403 return found; 6404 } 6405 6406 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 6407 of the supplied arm_feature_set structure with bitmasks indicating 6408 the supported base architectures and coprocessor extensions. 6409 6410 FIXME: This could more efficiently implemented as a constant array, 6411 although it would also be less robust. */ 6412 6413 static void 6414 select_arm_features (unsigned long mach, 6415 arm_feature_set * features) 6416 { 6417 arm_feature_set arch_fset; 6418 const arm_feature_set fpu_any = FPU_ANY; 6419 6420 #undef ARM_SET_FEATURES 6421 #define ARM_SET_FEATURES(FSET) \ 6422 { \ 6423 const arm_feature_set fset = FSET; \ 6424 arch_fset = fset; \ 6425 } 6426 6427 /* When several architecture versions share the same bfd_mach_arm_XXX value 6428 the most featureful is chosen. */ 6429 switch (mach) 6430 { 6431 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 6432 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 6433 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 6434 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 6435 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 6436 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 6437 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 6438 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 6439 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 6440 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 6441 case bfd_mach_arm_ep9312: 6442 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 6443 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 6444 break; 6445 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 6446 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 6447 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 6448 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 6449 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 6450 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 6451 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 6452 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 6453 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 6454 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 6455 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 6456 case bfd_mach_arm_8: 6457 { 6458 /* Add bits for extensions that Armv8.5-A recognizes. */ 6459 arm_feature_set armv8_5_ext_fset 6460 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 6461 ARM_SET_FEATURES (ARM_ARCH_V8_5A); 6462 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset); 6463 break; 6464 } 6465 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; 6466 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 6467 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 6468 /* If the machine type is unknown allow all architecture types and all 6469 extensions. */ 6470 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; 6471 default: 6472 abort (); 6473 } 6474 #undef ARM_SET_FEATURES 6475 6476 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 6477 and thus on bfd_mach_arm_XXX value. Therefore for a given 6478 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 6479 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 6480 } 6481 6482 6483 /* NOTE: There are no checks in these routines that 6484 the relevant number of data bytes exist. */ 6485 6486 static int 6487 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 6488 { 6489 unsigned char b[4]; 6490 long given; 6491 int status; 6492 int is_thumb = FALSE; 6493 int is_data = FALSE; 6494 int little_code; 6495 unsigned int size = 4; 6496 void (*printer) (bfd_vma, struct disassemble_info *, long); 6497 bfd_boolean found = FALSE; 6498 struct arm_private_data *private_data; 6499 6500 if (info->disassembler_options) 6501 { 6502 parse_arm_disassembler_options (info->disassembler_options); 6503 6504 /* To avoid repeated parsing of these options, we remove them here. */ 6505 info->disassembler_options = NULL; 6506 } 6507 6508 /* PR 10288: Control which instructions will be disassembled. */ 6509 if (info->private_data == NULL) 6510 { 6511 static struct arm_private_data private; 6512 6513 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 6514 /* If the user did not use the -m command line switch then default to 6515 disassembling all types of ARM instruction. 6516 6517 The info->mach value has to be ignored as this will be based on 6518 the default archictecture for the target and/or hints in the notes 6519 section, but it will never be greater than the current largest arm 6520 machine value (iWMMXt2), which is only equivalent to the V5TE 6521 architecture. ARM architectures have advanced beyond the machine 6522 value encoding, and these newer architectures would be ignored if 6523 the machine value was used. 6524 6525 Ie the -m switch is used to restrict which instructions will be 6526 disassembled. If it is necessary to use the -m switch to tell 6527 objdump that an ARM binary is being disassembled, eg because the 6528 input is a raw binary file, but it is also desired to disassemble 6529 all ARM instructions then use "-marm". This will select the 6530 "unknown" arm architecture which is compatible with any ARM 6531 instruction. */ 6532 info->mach = bfd_mach_arm_unknown; 6533 6534 /* Compute the architecture bitmask from the machine number. 6535 Note: This assumes that the machine number will not change 6536 during disassembly.... */ 6537 select_arm_features (info->mach, & private.features); 6538 6539 private.has_mapping_symbols = -1; 6540 private.last_mapping_sym = -1; 6541 private.last_mapping_addr = 0; 6542 6543 info->private_data = & private; 6544 } 6545 6546 private_data = info->private_data; 6547 6548 /* Decide if our code is going to be little-endian, despite what the 6549 function argument might say. */ 6550 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 6551 6552 /* For ELF, consult the symbol table to determine what kind of code 6553 or data we have. */ 6554 if (info->symtab_size != 0 6555 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 6556 { 6557 bfd_vma addr; 6558 int n, start; 6559 int last_sym = -1; 6560 enum map_type type = MAP_ARM; 6561 6562 /* Start scanning at the start of the function, or wherever 6563 we finished last time. */ 6564 /* PR 14006. When the address is 0 we are either at the start of the 6565 very first function, or else the first function in a new, unlinked 6566 executable section (eg because of -ffunction-sections). Either way 6567 start scanning from the beginning of the symbol table, not where we 6568 left off last time. */ 6569 if (pc == 0) 6570 start = 0; 6571 else 6572 { 6573 start = info->symtab_pos + 1; 6574 if (start < private_data->last_mapping_sym) 6575 start = private_data->last_mapping_sym; 6576 } 6577 found = FALSE; 6578 6579 /* First, look for mapping symbols. */ 6580 if (private_data->has_mapping_symbols != 0) 6581 { 6582 /* Scan up to the location being disassembled. */ 6583 for (n = start; n < info->symtab_size; n++) 6584 { 6585 addr = bfd_asymbol_value (info->symtab[n]); 6586 if (addr > pc) 6587 break; 6588 if (get_map_sym_type (info, n, &type)) 6589 { 6590 last_sym = n; 6591 found = TRUE; 6592 } 6593 } 6594 6595 if (!found) 6596 { 6597 /* No mapping symbol found at this address. Look backwards 6598 for a preceding one. */ 6599 for (n = start - 1; n >= 0; n--) 6600 { 6601 if (get_map_sym_type (info, n, &type)) 6602 { 6603 last_sym = n; 6604 found = TRUE; 6605 break; 6606 } 6607 } 6608 } 6609 6610 if (found) 6611 private_data->has_mapping_symbols = 1; 6612 6613 /* No mapping symbols were found. A leading $d may be 6614 omitted for sections which start with data; but for 6615 compatibility with legacy and stripped binaries, only 6616 assume the leading $d if there is at least one mapping 6617 symbol in the file. */ 6618 if (!found && private_data->has_mapping_symbols == -1) 6619 { 6620 /* Look for mapping symbols, in any section. */ 6621 for (n = 0; n < info->symtab_size; n++) 6622 if (is_mapping_symbol (info, n, &type)) 6623 { 6624 private_data->has_mapping_symbols = 1; 6625 break; 6626 } 6627 if (private_data->has_mapping_symbols == -1) 6628 private_data->has_mapping_symbols = 0; 6629 } 6630 6631 if (!found && private_data->has_mapping_symbols == 1) 6632 { 6633 type = MAP_DATA; 6634 found = TRUE; 6635 } 6636 } 6637 6638 /* Next search for function symbols to separate ARM from Thumb 6639 in binaries without mapping symbols. */ 6640 if (!found) 6641 { 6642 /* Scan up to the location being disassembled. */ 6643 for (n = start; n < info->symtab_size; n++) 6644 { 6645 addr = bfd_asymbol_value (info->symtab[n]); 6646 if (addr > pc) 6647 break; 6648 if (get_sym_code_type (info, n, &type)) 6649 { 6650 last_sym = n; 6651 found = TRUE; 6652 } 6653 } 6654 6655 if (!found) 6656 { 6657 /* No mapping symbol found at this address. Look backwards 6658 for a preceding one. */ 6659 for (n = start - 1; n >= 0; n--) 6660 { 6661 if (get_sym_code_type (info, n, &type)) 6662 { 6663 last_sym = n; 6664 found = TRUE; 6665 break; 6666 } 6667 } 6668 } 6669 } 6670 6671 private_data->last_mapping_sym = last_sym; 6672 private_data->last_type = type; 6673 is_thumb = (private_data->last_type == MAP_THUMB); 6674 is_data = (private_data->last_type == MAP_DATA); 6675 6676 /* Look a little bit ahead to see if we should print out 6677 two or four bytes of data. If there's a symbol, 6678 mapping or otherwise, after two bytes then don't 6679 print more. */ 6680 if (is_data) 6681 { 6682 size = 4 - (pc & 3); 6683 for (n = last_sym + 1; n < info->symtab_size; n++) 6684 { 6685 addr = bfd_asymbol_value (info->symtab[n]); 6686 if (addr > pc 6687 && (info->section == NULL 6688 || info->section == info->symtab[n]->section)) 6689 { 6690 if (addr - pc < size) 6691 size = addr - pc; 6692 break; 6693 } 6694 } 6695 /* If the next symbol is after three bytes, we need to 6696 print only part of the data, so that we can use either 6697 .byte or .short. */ 6698 if (size == 3) 6699 size = (pc & 1) ? 1 : 2; 6700 } 6701 } 6702 6703 if (info->symbols != NULL) 6704 { 6705 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 6706 { 6707 coff_symbol_type * cs; 6708 6709 cs = coffsymbol (*info->symbols); 6710 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 6711 || cs->native->u.syment.n_sclass == C_THUMBSTAT 6712 || cs->native->u.syment.n_sclass == C_THUMBLABEL 6713 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 6714 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 6715 } 6716 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 6717 && !found) 6718 { 6719 /* If no mapping symbol has been found then fall back to the type 6720 of the function symbol. */ 6721 elf_symbol_type * es; 6722 unsigned int type; 6723 6724 es = *(elf_symbol_type **)(info->symbols); 6725 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6726 6727 is_thumb = 6728 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6729 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 6730 } 6731 else if (bfd_asymbol_flavour (*info->symbols) 6732 == bfd_target_mach_o_flavour) 6733 { 6734 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 6735 6736 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 6737 } 6738 } 6739 6740 if (force_thumb) 6741 is_thumb = TRUE; 6742 6743 if (is_data) 6744 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6745 else 6746 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6747 6748 info->bytes_per_line = 4; 6749 6750 /* PR 10263: Disassemble data if requested to do so by the user. */ 6751 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 6752 { 6753 int i; 6754 6755 /* Size was already set above. */ 6756 info->bytes_per_chunk = size; 6757 printer = print_insn_data; 6758 6759 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 6760 given = 0; 6761 if (little) 6762 for (i = size - 1; i >= 0; i--) 6763 given = b[i] | (given << 8); 6764 else 6765 for (i = 0; i < (int) size; i++) 6766 given = b[i] | (given << 8); 6767 } 6768 else if (!is_thumb) 6769 { 6770 /* In ARM mode endianness is a straightforward issue: the instruction 6771 is four bytes long and is either ordered 0123 or 3210. */ 6772 printer = print_insn_arm; 6773 info->bytes_per_chunk = 4; 6774 size = 4; 6775 6776 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 6777 if (little_code) 6778 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 6779 else 6780 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 6781 } 6782 else 6783 { 6784 /* In Thumb mode we have the additional wrinkle of two 6785 instruction lengths. Fortunately, the bits that determine 6786 the length of the current instruction are always to be found 6787 in the first two bytes. */ 6788 printer = print_insn_thumb16; 6789 info->bytes_per_chunk = 2; 6790 size = 2; 6791 6792 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 6793 if (little_code) 6794 given = (b[0]) | (b[1] << 8); 6795 else 6796 given = (b[1]) | (b[0] << 8); 6797 6798 if (!status) 6799 { 6800 /* These bit patterns signal a four-byte Thumb 6801 instruction. */ 6802 if ((given & 0xF800) == 0xF800 6803 || (given & 0xF800) == 0xF000 6804 || (given & 0xF800) == 0xE800) 6805 { 6806 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 6807 if (little_code) 6808 given = (b[0]) | (b[1] << 8) | (given << 16); 6809 else 6810 given = (b[1]) | (b[0] << 8) | (given << 16); 6811 6812 printer = print_insn_thumb32; 6813 size = 4; 6814 } 6815 } 6816 6817 if (ifthen_address != pc) 6818 find_ifthen_state (pc, info, little_code); 6819 6820 if (ifthen_state) 6821 { 6822 if ((ifthen_state & 0xf) == 0x8) 6823 ifthen_next_state = 0; 6824 else 6825 ifthen_next_state = (ifthen_state & 0xe0) 6826 | ((ifthen_state & 0xf) << 1); 6827 } 6828 } 6829 6830 if (status) 6831 { 6832 info->memory_error_func (status, pc, info); 6833 return -1; 6834 } 6835 if (info->flags & INSN_HAS_RELOC) 6836 /* If the instruction has a reloc associated with it, then 6837 the offset field in the instruction will actually be the 6838 addend for the reloc. (We are using REL type relocs). 6839 In such cases, we can ignore the pc when computing 6840 addresses, since the addend is not currently pc-relative. */ 6841 pc = 0; 6842 6843 printer (pc, info, given); 6844 6845 if (is_thumb) 6846 { 6847 ifthen_state = ifthen_next_state; 6848 ifthen_address += size; 6849 } 6850 return size; 6851 } 6852 6853 int 6854 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 6855 { 6856 /* Detect BE8-ness and record it in the disassembler info. */ 6857 if (info->flavour == bfd_target_elf_flavour 6858 && info->section != NULL 6859 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 6860 info->endian_code = BFD_ENDIAN_LITTLE; 6861 6862 return print_insn (pc, info, FALSE); 6863 } 6864 6865 int 6866 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 6867 { 6868 return print_insn (pc, info, TRUE); 6869 } 6870 6871 const disasm_options_and_args_t * 6872 disassembler_options_arm (void) 6873 { 6874 static disasm_options_and_args_t *opts_and_args; 6875 6876 if (opts_and_args == NULL) 6877 { 6878 disasm_options_t *opts; 6879 unsigned int i; 6880 6881 opts_and_args = XNEW (disasm_options_and_args_t); 6882 opts_and_args->args = NULL; 6883 6884 opts = &opts_and_args->options; 6885 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6886 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6887 opts->arg = NULL; 6888 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6889 { 6890 opts->name[i] = regnames[i].name; 6891 if (regnames[i].description != NULL) 6892 opts->description[i] = _(regnames[i].description); 6893 else 6894 opts->description[i] = NULL; 6895 } 6896 /* The array we return must be NULL terminated. */ 6897 opts->name[i] = NULL; 6898 opts->description[i] = NULL; 6899 } 6900 6901 return opts_and_args; 6902 } 6903 6904 void 6905 print_arm_disassembler_options (FILE *stream) 6906 { 6907 unsigned int i, max_len = 0; 6908 fprintf (stream, _("\n\ 6909 The following ARM specific disassembler options are supported for use with\n\ 6910 the -M switch:\n")); 6911 6912 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6913 { 6914 unsigned int len = strlen (regnames[i].name); 6915 if (max_len < len) 6916 max_len = len; 6917 } 6918 6919 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 6920 fprintf (stream, " %s%*c %s\n", 6921 regnames[i].name, 6922 (int)(max_len - strlen (regnames[i].name)), ' ', 6923 _(regnames[i].description)); 6924 } 6925
Indexes created Thu Apr 30 00:23:01 UTC 2026