i386-dis.c revision 1.1.1.12
1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright (C) 1988-2024 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* 80386 instruction printer by Pace Willisson (pace (at) prep.ai.mit.edu) 23 July 1988 24 modified by John Hassey (hassey (at) dg-rtp.dg.com) 25 x86-64 support added by Jan Hubicka (jh (at) suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz). */ 27 28 /* The main tables describing the instructions is essentially a copy 29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 30 Programmers Manual. Usually, there is a capital letter, followed 31 by a small letter. The capital letter tell the addressing mode, 32 and the small letter tells about the operand size. Refer to 33 the Intel manual for details. */ 34 35 #include "sysdep.h" 36 #include "disassemble.h" 37 #include "opintl.h" 38 #include "opcode/i386.h" 39 #include "libiberty.h" 40 #include "safe-ctype.h" 41 42 typedef struct instr_info instr_info; 43 44 static bool dofloat (instr_info *, int); 45 static int putop (instr_info *, const char *, int); 46 static void oappend_with_style (instr_info *, const char *, 47 enum disassembler_style); 48 49 static bool OP_E (instr_info *, int, int); 50 static bool OP_E_memory (instr_info *, int, int); 51 static bool OP_indirE (instr_info *, int, int); 52 static bool OP_G (instr_info *, int, int); 53 static bool OP_ST (instr_info *, int, int); 54 static bool OP_STi (instr_info *, int, int); 55 static bool OP_Skip_MODRM (instr_info *, int, int); 56 static bool OP_REG (instr_info *, int, int); 57 static bool OP_IMREG (instr_info *, int, int); 58 static bool OP_I (instr_info *, int, int); 59 static bool OP_I64 (instr_info *, int, int); 60 static bool OP_sI (instr_info *, int, int); 61 static bool OP_J (instr_info *, int, int); 62 static bool OP_SEG (instr_info *, int, int); 63 static bool OP_DIR (instr_info *, int, int); 64 static bool OP_OFF (instr_info *, int, int); 65 static bool OP_OFF64 (instr_info *, int, int); 66 static bool OP_ESreg (instr_info *, int, int); 67 static bool OP_DSreg (instr_info *, int, int); 68 static bool OP_C (instr_info *, int, int); 69 static bool OP_D (instr_info *, int, int); 70 static bool OP_T (instr_info *, int, int); 71 static bool OP_MMX (instr_info *, int, int); 72 static bool OP_XMM (instr_info *, int, int); 73 static bool OP_EM (instr_info *, int, int); 74 static bool OP_EX (instr_info *, int, int); 75 static bool OP_EMC (instr_info *, int,int); 76 static bool OP_MXC (instr_info *, int,int); 77 static bool OP_R (instr_info *, int, int); 78 static bool OP_M (instr_info *, int, int); 79 static bool OP_VEX (instr_info *, int, int); 80 static bool OP_VexR (instr_info *, int, int); 81 static bool OP_VexW (instr_info *, int, int); 82 static bool OP_Rounding (instr_info *, int, int); 83 static bool OP_REG_VexI4 (instr_info *, int, int); 84 static bool OP_VexI4 (instr_info *, int, int); 85 static bool OP_0f07 (instr_info *, int, int); 86 static bool OP_Monitor (instr_info *, int, int); 87 static bool OP_Mwait (instr_info *, int, int); 88 89 static bool PCLMUL_Fixup (instr_info *, int, int); 90 static bool VPCMP_Fixup (instr_info *, int, int); 91 static bool VPCOM_Fixup (instr_info *, int, int); 92 static bool NOP_Fixup (instr_info *, int, int); 93 static bool MONTMUL_Fixup (instr_info *, int, int); 94 static bool OP_3DNowSuffix (instr_info *, int, int); 95 static bool CMP_Fixup (instr_info *, int, int); 96 static bool REP_Fixup (instr_info *, int, int); 97 static bool SEP_Fixup (instr_info *, int, int); 98 static bool BND_Fixup (instr_info *, int, int); 99 static bool NOTRACK_Fixup (instr_info *, int, int); 100 static bool HLE_Fixup1 (instr_info *, int, int); 101 static bool HLE_Fixup2 (instr_info *, int, int); 102 static bool HLE_Fixup3 (instr_info *, int, int); 103 static bool CMPXCHG8B_Fixup (instr_info *, int, int); 104 static bool XMM_Fixup (instr_info *, int, int); 105 static bool FXSAVE_Fixup (instr_info *, int, int); 106 static bool MOVSXD_Fixup (instr_info *, int, int); 107 static bool DistinctDest_Fixup (instr_info *, int, int); 108 static bool PREFETCHI_Fixup (instr_info *, int, int); 109 static bool PUSH2_POP2_Fixup (instr_info *, int, int); 110 static bool JMPABS_Fixup (instr_info *, int, int); 111 static bool CFCMOV_Fixup (instr_info *, int, int); 112 113 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, 114 enum disassembler_style, 115 const char *, ...); 116 117 /* This character is used to encode style information within the output 118 buffers. See oappend_insert_style for more details. */ 119 #define STYLE_MARKER_CHAR '\002' 120 121 /* The maximum operand buffer size. */ 122 #define MAX_OPERAND_BUFFER_SIZE 128 123 124 enum address_mode 125 { 126 mode_16bit, 127 mode_32bit, 128 mode_64bit 129 }; 130 131 static const char *prefix_name (enum address_mode, uint8_t, int); 132 133 enum x86_64_isa 134 { 135 amd64 = 1, 136 intel64 137 }; 138 139 enum evex_type 140 { 141 evex_default = 0, 142 evex_from_legacy, 143 evex_from_vex, 144 }; 145 146 struct instr_info 147 { 148 enum address_mode address_mode; 149 150 /* Flags for the prefixes for the current instruction. See below. */ 151 int prefixes; 152 153 /* REX prefix the current instruction. See below. */ 154 uint8_t rex; 155 /* Bits of REX we've already used. */ 156 uint8_t rex_used; 157 158 /* Record W R4 X4 B4 bits for rex2. */ 159 unsigned char rex2; 160 /* Bits of rex2 we've already used. */ 161 unsigned char rex2_used; 162 unsigned char rex2_payload; 163 164 bool need_modrm; 165 unsigned char condition_code; 166 unsigned char need_vex; 167 bool has_sib; 168 169 /* Flags for ins->prefixes which we somehow handled when printing the 170 current instruction. */ 171 int used_prefixes; 172 173 /* Flags for EVEX bits which we somehow handled when printing the 174 current instruction. */ 175 int evex_used; 176 177 char obuf[MAX_OPERAND_BUFFER_SIZE]; 178 char *obufp; 179 char *mnemonicendp; 180 const uint8_t *start_codep; 181 uint8_t *codep; 182 const uint8_t *end_codep; 183 unsigned char nr_prefixes; 184 signed char last_lock_prefix; 185 signed char last_repz_prefix; 186 signed char last_repnz_prefix; 187 signed char last_data_prefix; 188 signed char last_addr_prefix; 189 signed char last_rex_prefix; 190 signed char last_rex2_prefix; 191 signed char last_seg_prefix; 192 signed char fwait_prefix; 193 /* The active segment register prefix. */ 194 unsigned char active_seg_prefix; 195 196 #define MAX_CODE_LENGTH 15 197 /* We can up to 14 ins->prefixes since the maximum instruction length is 198 15bytes. */ 199 uint8_t all_prefixes[MAX_CODE_LENGTH - 1]; 200 disassemble_info *info; 201 202 struct 203 { 204 int mod; 205 int reg; 206 int rm; 207 } 208 modrm; 209 210 struct 211 { 212 int scale; 213 int index; 214 int base; 215 } 216 sib; 217 218 struct 219 { 220 int register_specifier; 221 int length; 222 int prefix; 223 int mask_register_specifier; 224 int scc; 225 int ll; 226 bool w; 227 bool evex; 228 bool v; 229 bool zeroing; 230 bool b; 231 bool no_broadcast; 232 bool nf; 233 bool u; 234 } 235 vex; 236 237 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */ 238 #define nd b 239 240 enum evex_type evex_type; 241 242 /* Remember if the current op is a jump instruction. */ 243 bool op_is_jump; 244 245 bool two_source_ops; 246 247 /* Record whether EVEX masking is used incorrectly. */ 248 bool illegal_masking; 249 250 /* Record whether the modrm byte has been skipped. */ 251 bool has_skipped_modrm; 252 253 unsigned char op_ad; 254 signed char op_index[MAX_OPERANDS]; 255 bool op_riprel[MAX_OPERANDS]; 256 char *op_out[MAX_OPERANDS]; 257 bfd_vma op_address[MAX_OPERANDS]; 258 bfd_vma start_pc; 259 260 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes. 261 * (see topic "Redundant ins->prefixes" in the "Differences from 8086" 262 * section of the "Virtual 8086 Mode" chapter.) 263 * 'pc' should be the address of this instruction, it will 264 * be used to print the target address if this is a relative jump or call 265 * The function returns the length of this instruction in bytes. 266 */ 267 char intel_syntax; 268 bool intel_mnemonic; 269 char open_char; 270 char close_char; 271 char separator_char; 272 char scale_char; 273 274 enum x86_64_isa isa64; 275 }; 276 277 struct dis_private { 278 bfd_vma insn_start; 279 int orig_sizeflag; 280 281 /* Indexes first byte not fetched. */ 282 unsigned int fetched; 283 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1]; 284 }; 285 286 /* Mark parts used in the REX prefix. When we are testing for 287 empty prefix (for 8bit register REX extension), just mask it 288 out. Otherwise test for REX bit is excuse for existence of REX 289 only in case value is nonzero. */ 290 #define USED_REX(value) \ 291 { \ 292 if (value) \ 293 { \ 294 if (ins->rex & value) \ 295 ins->rex_used |= (value) | REX_OPCODE; \ 296 if (ins->rex2 & value) \ 297 { \ 298 ins->rex2_used |= (value); \ 299 ins->rex_used |= REX_OPCODE; \ 300 } \ 301 } \ 302 else \ 303 ins->rex_used |= REX_OPCODE; \ 304 } 305 306 307 #define EVEX_b_used 1 308 #define EVEX_len_used 2 309 310 311 /* {rex2} is not printed when the REX2_SPECIAL is set. */ 312 #define REX2_SPECIAL 16 313 314 /* Flags stored in PREFIXES. */ 315 #define PREFIX_REPZ 1 316 #define PREFIX_REPNZ 2 317 #define PREFIX_CS 4 318 #define PREFIX_SS 8 319 #define PREFIX_DS 0x10 320 #define PREFIX_ES 0x20 321 #define PREFIX_FS 0x40 322 #define PREFIX_GS 0x80 323 #define PREFIX_LOCK 0x100 324 #define PREFIX_DATA 0x200 325 #define PREFIX_ADDR 0x400 326 #define PREFIX_FWAIT 0x800 327 #define PREFIX_REX2 0x1000 328 #define PREFIX_NP_OR_DATA 0x2000 329 #define NO_PREFIX 0x4000 330 331 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 332 to ADDR (exclusive) are valid. Returns true for success, false 333 on error. */ 334 static bool 335 fetch_code (struct disassemble_info *info, const uint8_t *until) 336 { 337 int status = -1; 338 struct dis_private *priv = info->private_data; 339 bfd_vma start = priv->insn_start + priv->fetched; 340 uint8_t *fetch_end = priv->the_buffer + priv->fetched; 341 ptrdiff_t needed = until - fetch_end; 342 343 if (needed <= 0) 344 return true; 345 346 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer)) 347 status = (*info->read_memory_func) (start, fetch_end, needed, info); 348 if (status != 0) 349 { 350 /* If we did manage to read at least one byte, then 351 print_insn_i386 will do something sensible. Otherwise, print 352 an error. We do that here because this is where we know 353 STATUS. */ 354 if (!priv->fetched) 355 (*info->memory_error_func) (status, start, info); 356 return false; 357 } 358 359 priv->fetched += needed; 360 return true; 361 } 362 363 static bool 364 fetch_modrm (instr_info *ins) 365 { 366 if (!fetch_code (ins->info, ins->codep + 1)) 367 return false; 368 369 ins->modrm.mod = (*ins->codep >> 6) & 3; 370 ins->modrm.reg = (*ins->codep >> 3) & 7; 371 ins->modrm.rm = *ins->codep & 7; 372 373 return true; 374 } 375 376 static int 377 fetch_error (const instr_info *ins) 378 { 379 /* Getting here means we tried for data but didn't get it. That 380 means we have an incomplete instruction of some sort. Just 381 print the first byte as a prefix or a .byte pseudo-op. */ 382 const struct dis_private *priv = ins->info->private_data; 383 const char *name = NULL; 384 385 if (ins->codep <= priv->the_buffer) 386 return -1; 387 388 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE)) 389 name = prefix_name (ins->address_mode, priv->the_buffer[0], 390 priv->orig_sizeflag); 391 if (name != NULL) 392 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name); 393 else 394 { 395 /* Just print the first byte as a .byte instruction. */ 396 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte "); 397 i386_dis_printf (ins->info, dis_style_immediate, "%#x", 398 (unsigned int) priv->the_buffer[0]); 399 } 400 401 return 1; 402 } 403 404 /* Possible values for prefix requirement. */ 405 #define PREFIX_IGNORED_SHIFT 16 406 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) 407 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) 408 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) 409 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) 410 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) 411 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT) 412 413 /* Opcode prefixes. */ 414 #define PREFIX_OPCODE (PREFIX_REPZ \ 415 | PREFIX_REPNZ \ 416 | PREFIX_DATA) 417 418 /* Prefixes ignored. */ 419 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ 420 | PREFIX_IGNORED_REPNZ \ 421 | PREFIX_IGNORED_DATA) 422 423 #define XX { NULL, 0 } 424 #define Bad_Opcode NULL, { { NULL, 0 } }, 0 425 426 #define Eb { OP_E, b_mode } 427 #define Ebnd { OP_E, bnd_mode } 428 #define EbS { OP_E, b_swap_mode } 429 #define EbndS { OP_E, bnd_swap_mode } 430 #define Ev { OP_E, v_mode } 431 #define Eva { OP_E, va_mode } 432 #define Ev_bnd { OP_E, v_bnd_mode } 433 #define EvS { OP_E, v_swap_mode } 434 #define Ed { OP_E, d_mode } 435 #define Edq { OP_E, dq_mode } 436 #define Edb { OP_E, db_mode } 437 #define Edw { OP_E, dw_mode } 438 #define Eq { OP_E, q_mode } 439 #define indirEv { OP_indirE, indir_v_mode } 440 #define indirEp { OP_indirE, f_mode } 441 #define stackEv { OP_E, stack_v_mode } 442 #define Em { OP_E, m_mode } 443 #define Ew { OP_E, w_mode } 444 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 445 #define Ma { OP_M, a_mode } 446 #define Mb { OP_M, b_mode } 447 #define Md { OP_M, d_mode } 448 #define Mdq { OP_M, dq_mode } 449 #define Mo { OP_M, o_mode } 450 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 451 #define Mq { OP_M, q_mode } 452 #define Mv { OP_M, v_mode } 453 #define Mv_bnd { OP_M, v_bndmk_mode } 454 #define Mw { OP_M, w_mode } 455 #define Mx { OP_M, x_mode } 456 #define Mxmm { OP_M, xmm_mode } 457 #define Mymm { OP_M, ymm_mode } 458 #define Gb { OP_G, b_mode } 459 #define Gbnd { OP_G, bnd_mode } 460 #define Gv { OP_G, v_mode } 461 #define Gd { OP_G, d_mode } 462 #define Gdq { OP_G, dq_mode } 463 #define Gq { OP_G, q_mode } 464 #define Gm { OP_G, m_mode } 465 #define Gva { OP_G, va_mode } 466 #define Gw { OP_G, w_mode } 467 #define Ib { OP_I, b_mode } 468 #define sIb { OP_sI, b_mode } /* sign extened byte */ 469 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ 470 #define Iv { OP_I, v_mode } 471 #define sIv { OP_sI, v_mode } 472 #define Iv64 { OP_I64, v_mode } 473 #define Id { OP_I, d_mode } 474 #define Iw { OP_I, w_mode } 475 #define I1 { OP_I, const_1_mode } 476 #define Jb { OP_J, b_mode } 477 #define Jv { OP_J, v_mode } 478 #define Jdqw { OP_J, dqw_mode } 479 #define Cm { OP_C, m_mode } 480 #define Dm { OP_D, m_mode } 481 #define Td { OP_T, d_mode } 482 #define Skip_MODRM { OP_Skip_MODRM, 0 } 483 484 #define RMeAX { OP_REG, eAX_reg } 485 #define RMeBX { OP_REG, eBX_reg } 486 #define RMeCX { OP_REG, eCX_reg } 487 #define RMeDX { OP_REG, eDX_reg } 488 #define RMeSP { OP_REG, eSP_reg } 489 #define RMeBP { OP_REG, eBP_reg } 490 #define RMeSI { OP_REG, eSI_reg } 491 #define RMeDI { OP_REG, eDI_reg } 492 #define RMrAX { OP_REG, rAX_reg } 493 #define RMrBX { OP_REG, rBX_reg } 494 #define RMrCX { OP_REG, rCX_reg } 495 #define RMrDX { OP_REG, rDX_reg } 496 #define RMrSP { OP_REG, rSP_reg } 497 #define RMrBP { OP_REG, rBP_reg } 498 #define RMrSI { OP_REG, rSI_reg } 499 #define RMrDI { OP_REG, rDI_reg } 500 #define RMAL { OP_REG, al_reg } 501 #define RMCL { OP_REG, cl_reg } 502 #define RMDL { OP_REG, dl_reg } 503 #define RMBL { OP_REG, bl_reg } 504 #define RMAH { OP_REG, ah_reg } 505 #define RMCH { OP_REG, ch_reg } 506 #define RMDH { OP_REG, dh_reg } 507 #define RMBH { OP_REG, bh_reg } 508 #define RMAX { OP_REG, ax_reg } 509 #define RMDX { OP_REG, dx_reg } 510 511 #define eAX { OP_IMREG, eAX_reg } 512 #define AL { OP_IMREG, al_reg } 513 #define CL { OP_IMREG, cl_reg } 514 #define zAX { OP_IMREG, z_mode_ax_reg } 515 #define indirDX { OP_IMREG, indir_dx_reg } 516 517 #define Sw { OP_SEG, w_mode } 518 #define Sv { OP_SEG, v_mode } 519 #define Ap { OP_DIR, 0 } 520 #define Ob { OP_OFF64, b_mode } 521 #define Ov { OP_OFF64, v_mode } 522 #define Xb { OP_DSreg, eSI_reg } 523 #define Xv { OP_DSreg, eSI_reg } 524 #define Xz { OP_DSreg, eSI_reg } 525 #define Yb { OP_ESreg, eDI_reg } 526 #define Yv { OP_ESreg, eDI_reg } 527 #define DSBX { OP_DSreg, eBX_reg } 528 529 #define es { OP_REG, es_reg } 530 #define ss { OP_REG, ss_reg } 531 #define cs { OP_REG, cs_reg } 532 #define ds { OP_REG, ds_reg } 533 #define fs { OP_REG, fs_reg } 534 #define gs { OP_REG, gs_reg } 535 536 #define MX { OP_MMX, 0 } 537 #define XM { OP_XMM, 0 } 538 #define XMScalar { OP_XMM, scalar_mode } 539 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode } 540 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } 541 #define XMM { OP_XMM, xmm_mode } 542 #define TMM { OP_XMM, tmm_mode } 543 #define XMxmmq { OP_XMM, xmmq_mode } 544 #define EM { OP_EM, v_mode } 545 #define EMS { OP_EM, v_swap_mode } 546 #define EMd { OP_EM, d_mode } 547 #define EMx { OP_EM, x_mode } 548 #define EXbwUnit { OP_EX, bw_unit_mode } 549 #define EXb { OP_EX, b_mode } 550 #define EXw { OP_EX, w_mode } 551 #define EXd { OP_EX, d_mode } 552 #define EXdS { OP_EX, d_swap_mode } 553 #define EXwS { OP_EX, w_swap_mode } 554 #define EXq { OP_EX, q_mode } 555 #define EXqS { OP_EX, q_swap_mode } 556 #define EXdq { OP_EX, dq_mode } 557 #define EXx { OP_EX, x_mode } 558 #define EXxh { OP_EX, xh_mode } 559 #define EXxS { OP_EX, x_swap_mode } 560 #define EXxmm { OP_EX, xmm_mode } 561 #define EXymm { OP_EX, ymm_mode } 562 #define EXxmmq { OP_EX, xmmq_mode } 563 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode } 564 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } 565 #define EXxmmdw { OP_EX, xmmdw_mode } 566 #define EXxmmqd { OP_EX, xmmqd_mode } 567 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode } 568 #define EXymmq { OP_EX, ymmq_mode } 569 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } 570 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } 571 #define Rd { OP_R, d_mode } 572 #define Rdq { OP_R, dq_mode } 573 #define Rq { OP_R, q_mode } 574 #define Nq { OP_R, q_mm_mode } 575 #define Ux { OP_R, x_mode } 576 #define Uxmm { OP_R, xmm_mode } 577 #define Rxmmq { OP_R, xmmq_mode } 578 #define Rymm { OP_R, ymm_mode } 579 #define Rtmm { OP_R, tmm_mode } 580 #define EMCq { OP_EMC, q_mode } 581 #define MXC { OP_MXC, 0 } 582 #define OPSUF { OP_3DNowSuffix, 0 } 583 #define SEP { SEP_Fixup, 0 } 584 #define CMP { CMP_Fixup, 0 } 585 #define XMM0 { XMM_Fixup, 0 } 586 #define FXSAVE { FXSAVE_Fixup, 0 } 587 588 #define Vex { OP_VEX, x_mode } 589 #define VexW { OP_VexW, x_mode } 590 #define VexScalar { OP_VEX, scalar_mode } 591 #define VexScalarR { OP_VexR, scalar_mode } 592 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } 593 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } 594 #define VexGdq { OP_VEX, dq_mode } 595 #define VexGb { OP_VEX, b_mode } 596 #define VexGv { OP_VEX, v_mode } 597 #define VexTmm { OP_VEX, tmm_mode } 598 #define XMVexI4 { OP_REG_VexI4, x_mode } 599 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } 600 #define VexI4 { OP_VexI4, 0 } 601 #define PCLMUL { PCLMUL_Fixup, 0 } 602 #define VPCMP { VPCMP_Fixup, 0 } 603 #define VPCOM { VPCOM_Fixup, 0 } 604 605 #define EXxEVexR { OP_Rounding, evex_rounding_mode } 606 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } 607 #define EXxEVexS { OP_Rounding, evex_sae_mode } 608 609 #define MaskG { OP_G, mask_mode } 610 #define MaskE { OP_E, mask_mode } 611 #define MaskR { OP_R, mask_mode } 612 #define MaskBDE { OP_E, mask_bd_mode } 613 #define MaskVex { OP_VEX, mask_mode } 614 615 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } 616 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } 617 618 #define MVexSIBMEM { OP_M, vex_sibmem_mode } 619 620 /* Used handle "rep" prefix for string instructions. */ 621 #define Xbr { REP_Fixup, eSI_reg } 622 #define Xvr { REP_Fixup, eSI_reg } 623 #define Ybr { REP_Fixup, eDI_reg } 624 #define Yvr { REP_Fixup, eDI_reg } 625 #define Yzr { REP_Fixup, eDI_reg } 626 #define indirDXr { REP_Fixup, indir_dx_reg } 627 #define ALr { REP_Fixup, al_reg } 628 #define eAXr { REP_Fixup, eAX_reg } 629 630 /* Used handle HLE prefix for lockable instructions. */ 631 #define Ebh1 { HLE_Fixup1, b_mode } 632 #define Evh1 { HLE_Fixup1, v_mode } 633 #define Ebh2 { HLE_Fixup2, b_mode } 634 #define Evh2 { HLE_Fixup2, v_mode } 635 #define Ebh3 { HLE_Fixup3, b_mode } 636 #define Evh3 { HLE_Fixup3, v_mode } 637 638 #define BND { BND_Fixup, 0 } 639 #define NOTRACK { NOTRACK_Fixup, 0 } 640 641 #define cond_jump_flag { NULL, cond_jump_mode } 642 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 643 644 /* bits in sizeflag */ 645 #define SUFFIX_ALWAYS 4 646 #define AFLAG 2 647 #define DFLAG 1 648 649 enum 650 { 651 /* byte operand */ 652 b_mode = 1, 653 /* byte operand with operand swapped */ 654 b_swap_mode, 655 /* byte operand, sign extend like 'T' suffix */ 656 b_T_mode, 657 /* operand size depends on prefixes */ 658 v_mode, 659 /* operand size depends on prefixes with operand swapped */ 660 v_swap_mode, 661 /* operand size depends on address prefix */ 662 va_mode, 663 /* word operand */ 664 w_mode, 665 /* double word operand */ 666 d_mode, 667 /* word operand with operand swapped */ 668 w_swap_mode, 669 /* double word operand with operand swapped */ 670 d_swap_mode, 671 /* quad word operand */ 672 q_mode, 673 /* 8-byte MM operand */ 674 q_mm_mode, 675 /* quad word operand with operand swapped */ 676 q_swap_mode, 677 /* ten-byte operand */ 678 t_mode, 679 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 680 broadcast enabled. */ 681 x_mode, 682 /* Similar to x_mode, but with different EVEX mem shifts. */ 683 evex_x_gscat_mode, 684 /* Similar to x_mode, but with yet different EVEX mem shifts. */ 685 bw_unit_mode, 686 /* Similar to x_mode, but with disabled broadcast. */ 687 evex_x_nobcst_mode, 688 /* Similar to x_mode, but with operands swapped and disabled broadcast 689 in EVEX. */ 690 x_swap_mode, 691 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 692 broadcast of 16bit enabled. */ 693 xh_mode, 694 /* 16-byte XMM operand */ 695 xmm_mode, 696 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 697 memory operand (depending on vector length). Broadcast isn't 698 allowed. */ 699 xmmq_mode, 700 /* Same as xmmq_mode, but broadcast is allowed. */ 701 evex_half_bcst_xmmq_mode, 702 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 703 memory operand (depending on vector length). 16bit broadcast. */ 704 evex_half_bcst_xmmqh_mode, 705 /* 16-byte XMM, word, double word or quad word operand. */ 706 xmmdw_mode, 707 /* 16-byte XMM, double word, quad word operand or xmm word operand. */ 708 xmmqd_mode, 709 /* 16-byte XMM, double word, quad word operand or xmm word operand. 710 16bit broadcast. */ 711 evex_half_bcst_xmmqdh_mode, 712 /* 32-byte YMM operand */ 713 ymm_mode, 714 /* quad word, ymmword or zmmword memory operand. */ 715 ymmq_mode, 716 /* TMM operand */ 717 tmm_mode, 718 /* d_mode in 32bit, q_mode in 64bit mode. */ 719 m_mode, 720 /* pair of v_mode operands */ 721 a_mode, 722 cond_jump_mode, 723 loop_jcxz_mode, 724 movsxd_mode, 725 v_bnd_mode, 726 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ 727 v_bndmk_mode, 728 /* operand size depends on REX.W / VEX.W. */ 729 dq_mode, 730 /* Displacements like v_mode without considering Intel64 ISA. */ 731 dqw_mode, 732 /* bounds operand */ 733 bnd_mode, 734 /* bounds operand with operand swapped */ 735 bnd_swap_mode, 736 /* 4- or 6-byte pointer operand */ 737 f_mode, 738 const_1_mode, 739 /* v_mode for indirect branch opcodes. */ 740 indir_v_mode, 741 /* v_mode for stack-related opcodes. */ 742 stack_v_mode, 743 /* non-quad operand size depends on prefixes */ 744 z_mode, 745 /* 16-byte operand */ 746 o_mode, 747 /* registers like d_mode, memory like b_mode. */ 748 db_mode, 749 /* registers like d_mode, memory like w_mode. */ 750 dw_mode, 751 752 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ 753 vex_vsib_d_w_dq_mode, 754 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ 755 vex_vsib_q_w_dq_mode, 756 /* mandatory non-vector SIB. */ 757 vex_sibmem_mode, 758 759 /* scalar, ignore vector length. */ 760 scalar_mode, 761 762 /* Static rounding. */ 763 evex_rounding_mode, 764 /* Static rounding, 64-bit mode only. */ 765 evex_rounding_64_mode, 766 /* Supress all exceptions. */ 767 evex_sae_mode, 768 769 /* Mask register operand. */ 770 mask_mode, 771 /* Mask register operand. */ 772 mask_bd_mode, 773 774 es_reg, 775 cs_reg, 776 ss_reg, 777 ds_reg, 778 fs_reg, 779 gs_reg, 780 781 eAX_reg, 782 eCX_reg, 783 eDX_reg, 784 eBX_reg, 785 eSP_reg, 786 eBP_reg, 787 eSI_reg, 788 eDI_reg, 789 790 al_reg, 791 cl_reg, 792 dl_reg, 793 bl_reg, 794 ah_reg, 795 ch_reg, 796 dh_reg, 797 bh_reg, 798 799 ax_reg, 800 cx_reg, 801 dx_reg, 802 bx_reg, 803 sp_reg, 804 bp_reg, 805 si_reg, 806 di_reg, 807 808 rAX_reg, 809 rCX_reg, 810 rDX_reg, 811 rBX_reg, 812 rSP_reg, 813 rBP_reg, 814 rSI_reg, 815 rDI_reg, 816 817 z_mode_ax_reg, 818 indir_dx_reg 819 }; 820 821 enum 822 { 823 FLOATCODE = 1, 824 USE_REG_TABLE, 825 USE_MOD_TABLE, 826 USE_RM_TABLE, 827 USE_PREFIX_TABLE, 828 USE_X86_64_TABLE, 829 USE_X86_64_EVEX_FROM_VEX_TABLE, 830 USE_X86_64_EVEX_PFX_TABLE, 831 USE_X86_64_EVEX_W_TABLE, 832 USE_X86_64_EVEX_MEM_W_TABLE, 833 USE_3BYTE_TABLE, 834 USE_XOP_8F_TABLE, 835 USE_VEX_C4_TABLE, 836 USE_VEX_C5_TABLE, 837 USE_VEX_LEN_TABLE, 838 USE_VEX_W_TABLE, 839 USE_EVEX_TABLE, 840 USE_EVEX_LEN_TABLE 841 }; 842 843 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 844 845 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 846 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 847 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 848 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 849 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 850 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 851 #define X86_64_EVEX_FROM_VEX_TABLE(I) \ 852 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) 853 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I)) 854 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I)) 855 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I)) 856 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 857 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) 858 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) 859 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0) 860 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 861 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) 862 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0) 863 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) 864 865 enum 866 { 867 REG_80 = 0, 868 REG_81, 869 REG_83, 870 REG_8F, 871 REG_C0, 872 REG_C1, 873 REG_C6, 874 REG_C7, 875 REG_D0, 876 REG_D1, 877 REG_D2, 878 REG_D3, 879 REG_F6, 880 REG_F7, 881 REG_FE, 882 REG_FF, 883 REG_0F00, 884 REG_0F01, 885 REG_0F0D, 886 REG_0F18, 887 REG_0F1C_P_0_MOD_0, 888 REG_0F1E_P_1_MOD_3, 889 REG_0F38D8_PREFIX_1, 890 REG_0F3A0F_P_1, 891 REG_0F71, 892 REG_0F72, 893 REG_0F73, 894 REG_0FA6, 895 REG_0FA7, 896 REG_0FAE, 897 REG_0FBA, 898 REG_0FC7, 899 REG_VEX_0F71, 900 REG_VEX_0F72, 901 REG_VEX_0F73, 902 REG_VEX_0FAE, 903 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, 904 REG_VEX_0F38F3_L_0_P_0, 905 REG_VEX_MAP7_F6_L_0_W_0, 906 REG_VEX_MAP7_F8_L_0_W_0, 907 908 REG_XOP_09_01_L_0, 909 REG_XOP_09_02_L_0, 910 REG_XOP_09_12_L_0, 911 REG_XOP_0A_12_L_0, 912 913 REG_EVEX_0F71, 914 REG_EVEX_0F72, 915 REG_EVEX_0F73, 916 REG_EVEX_0F38C6_L_2, 917 REG_EVEX_0F38C7_L_2, 918 REG_EVEX_MAP4_80, 919 REG_EVEX_MAP4_81, 920 REG_EVEX_MAP4_83, 921 REG_EVEX_MAP4_8F, 922 REG_EVEX_MAP4_F6, 923 REG_EVEX_MAP4_F7, 924 REG_EVEX_MAP4_FE, 925 REG_EVEX_MAP4_FF, 926 }; 927 928 enum 929 { 930 MOD_62_32BIT = 0, 931 MOD_C4_32BIT, 932 MOD_C5_32BIT, 933 MOD_0F01_REG_0, 934 MOD_0F01_REG_1, 935 MOD_0F01_REG_2, 936 MOD_0F01_REG_3, 937 MOD_0F01_REG_5, 938 MOD_0F01_REG_7, 939 MOD_0F12_PREFIX_0, 940 MOD_0F16_PREFIX_0, 941 MOD_0F18_REG_0, 942 MOD_0F18_REG_1, 943 MOD_0F18_REG_2, 944 MOD_0F18_REG_3, 945 MOD_0F18_REG_6, 946 MOD_0F18_REG_7, 947 MOD_0F1A_PREFIX_0, 948 MOD_0F1B_PREFIX_0, 949 MOD_0F1B_PREFIX_1, 950 MOD_0F1C_PREFIX_0, 951 MOD_0F1E_PREFIX_1, 952 MOD_0FAE_REG_0, 953 MOD_0FAE_REG_1, 954 MOD_0FAE_REG_2, 955 MOD_0FAE_REG_3, 956 MOD_0FAE_REG_4, 957 MOD_0FAE_REG_5, 958 MOD_0FAE_REG_6, 959 MOD_0FAE_REG_7, 960 MOD_0FC7_REG_6, 961 MOD_0FC7_REG_7, 962 MOD_0F38DC_PREFIX_1, 963 MOD_0F38F8, 964 965 MOD_VEX_0F3849_X86_64_L_0_W_0, 966 967 MOD_EVEX_MAP4_60, 968 MOD_EVEX_MAP4_61, 969 MOD_EVEX_MAP4_F8_P_1, 970 MOD_EVEX_MAP4_F8_P_3, 971 }; 972 973 enum 974 { 975 RM_C6_REG_7 = 0, 976 RM_C7_REG_7, 977 RM_0F01_REG_0, 978 RM_0F01_REG_1, 979 RM_0F01_REG_2, 980 RM_0F01_REG_3, 981 RM_0F01_REG_5_MOD_3, 982 RM_0F01_REG_7_MOD_3, 983 RM_0F1E_P_1_MOD_3_REG_7, 984 RM_0FAE_REG_6_MOD_3_P_0, 985 RM_0FAE_REG_7_MOD_3, 986 RM_0F3A0F_P_1_R_0, 987 988 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0, 989 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3, 990 }; 991 992 enum 993 { 994 PREFIX_90 = 0, 995 PREFIX_0F00_REG_6_X86_64, 996 PREFIX_0F01_REG_0_MOD_3_RM_6, 997 PREFIX_0F01_REG_0_MOD_3_RM_7, 998 PREFIX_0F01_REG_1_RM_2, 999 PREFIX_0F01_REG_1_RM_4, 1000 PREFIX_0F01_REG_1_RM_5, 1001 PREFIX_0F01_REG_1_RM_6, 1002 PREFIX_0F01_REG_1_RM_7, 1003 PREFIX_0F01_REG_3_RM_1, 1004 PREFIX_0F01_REG_5_MOD_0, 1005 PREFIX_0F01_REG_5_MOD_3_RM_0, 1006 PREFIX_0F01_REG_5_MOD_3_RM_1, 1007 PREFIX_0F01_REG_5_MOD_3_RM_2, 1008 PREFIX_0F01_REG_5_MOD_3_RM_4, 1009 PREFIX_0F01_REG_5_MOD_3_RM_5, 1010 PREFIX_0F01_REG_5_MOD_3_RM_6, 1011 PREFIX_0F01_REG_5_MOD_3_RM_7, 1012 PREFIX_0F01_REG_7_MOD_3_RM_2, 1013 PREFIX_0F01_REG_7_MOD_3_RM_5, 1014 PREFIX_0F01_REG_7_MOD_3_RM_6, 1015 PREFIX_0F01_REG_7_MOD_3_RM_7, 1016 PREFIX_0F09, 1017 PREFIX_0F10, 1018 PREFIX_0F11, 1019 PREFIX_0F12, 1020 PREFIX_0F16, 1021 PREFIX_0F18_REG_6_MOD_0_X86_64, 1022 PREFIX_0F18_REG_7_MOD_0_X86_64, 1023 PREFIX_0F1A, 1024 PREFIX_0F1B, 1025 PREFIX_0F1C, 1026 PREFIX_0F1E, 1027 PREFIX_0F2A, 1028 PREFIX_0F2B, 1029 PREFIX_0F2C, 1030 PREFIX_0F2D, 1031 PREFIX_0F2E, 1032 PREFIX_0F2F, 1033 PREFIX_0F51, 1034 PREFIX_0F52, 1035 PREFIX_0F53, 1036 PREFIX_0F58, 1037 PREFIX_0F59, 1038 PREFIX_0F5A, 1039 PREFIX_0F5B, 1040 PREFIX_0F5C, 1041 PREFIX_0F5D, 1042 PREFIX_0F5E, 1043 PREFIX_0F5F, 1044 PREFIX_0F60, 1045 PREFIX_0F61, 1046 PREFIX_0F62, 1047 PREFIX_0F6F, 1048 PREFIX_0F70, 1049 PREFIX_0F78, 1050 PREFIX_0F79, 1051 PREFIX_0F7C, 1052 PREFIX_0F7D, 1053 PREFIX_0F7E, 1054 PREFIX_0F7F, 1055 PREFIX_0FA6_REG_0, 1056 PREFIX_0FA6_REG_5, 1057 PREFIX_0FA7_REG_6, 1058 PREFIX_0FAE_REG_0_MOD_3, 1059 PREFIX_0FAE_REG_1_MOD_3, 1060 PREFIX_0FAE_REG_2_MOD_3, 1061 PREFIX_0FAE_REG_3_MOD_3, 1062 PREFIX_0FAE_REG_4_MOD_0, 1063 PREFIX_0FAE_REG_4_MOD_3, 1064 PREFIX_0FAE_REG_5_MOD_3, 1065 PREFIX_0FAE_REG_6_MOD_0, 1066 PREFIX_0FAE_REG_6_MOD_3, 1067 PREFIX_0FAE_REG_7_MOD_0, 1068 PREFIX_0FB8, 1069 PREFIX_0FBC, 1070 PREFIX_0FBD, 1071 PREFIX_0FC2, 1072 PREFIX_0FC7_REG_6_MOD_0, 1073 PREFIX_0FC7_REG_6_MOD_3, 1074 PREFIX_0FC7_REG_7_MOD_3, 1075 PREFIX_0FD0, 1076 PREFIX_0FD6, 1077 PREFIX_0FE6, 1078 PREFIX_0FE7, 1079 PREFIX_0FF0, 1080 PREFIX_0FF7, 1081 PREFIX_0F38D8, 1082 PREFIX_0F38DC, 1083 PREFIX_0F38DD, 1084 PREFIX_0F38DE, 1085 PREFIX_0F38DF, 1086 PREFIX_0F38F0, 1087 PREFIX_0F38F1, 1088 PREFIX_0F38F6, 1089 PREFIX_0F38F8_M_0, 1090 PREFIX_0F38F8_M_1_X86_64, 1091 PREFIX_0F38FA, 1092 PREFIX_0F38FB, 1093 PREFIX_0F38FC, 1094 PREFIX_0F3A0F, 1095 PREFIX_VEX_0F12, 1096 PREFIX_VEX_0F16, 1097 PREFIX_VEX_0F2A, 1098 PREFIX_VEX_0F2C, 1099 PREFIX_VEX_0F2D, 1100 PREFIX_VEX_0F41_L_1_W_0, 1101 PREFIX_VEX_0F41_L_1_W_1, 1102 PREFIX_VEX_0F42_L_1_W_0, 1103 PREFIX_VEX_0F42_L_1_W_1, 1104 PREFIX_VEX_0F44_L_0_W_0, 1105 PREFIX_VEX_0F44_L_0_W_1, 1106 PREFIX_VEX_0F45_L_1_W_0, 1107 PREFIX_VEX_0F45_L_1_W_1, 1108 PREFIX_VEX_0F46_L_1_W_0, 1109 PREFIX_VEX_0F46_L_1_W_1, 1110 PREFIX_VEX_0F47_L_1_W_0, 1111 PREFIX_VEX_0F47_L_1_W_1, 1112 PREFIX_VEX_0F4A_L_1_W_0, 1113 PREFIX_VEX_0F4A_L_1_W_1, 1114 PREFIX_VEX_0F4B_L_1_W_0, 1115 PREFIX_VEX_0F4B_L_1_W_1, 1116 PREFIX_VEX_0F6F, 1117 PREFIX_VEX_0F70, 1118 PREFIX_VEX_0F7E, 1119 PREFIX_VEX_0F7F, 1120 PREFIX_VEX_0F90_L_0_W_0, 1121 PREFIX_VEX_0F90_L_0_W_1, 1122 PREFIX_VEX_0F91_L_0_W_0, 1123 PREFIX_VEX_0F91_L_0_W_1, 1124 PREFIX_VEX_0F92_L_0_W_0, 1125 PREFIX_VEX_0F92_L_0_W_1, 1126 PREFIX_VEX_0F93_L_0_W_0, 1127 PREFIX_VEX_0F93_L_0_W_1, 1128 PREFIX_VEX_0F98_L_0_W_0, 1129 PREFIX_VEX_0F98_L_0_W_1, 1130 PREFIX_VEX_0F99_L_0_W_0, 1131 PREFIX_VEX_0F99_L_0_W_1, 1132 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0, 1133 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1, 1134 PREFIX_VEX_0F384B_X86_64_L_0_W_0, 1135 PREFIX_VEX_0F3850_W_0, 1136 PREFIX_VEX_0F3851_W_0, 1137 PREFIX_VEX_0F385C_X86_64_L_0_W_0, 1138 PREFIX_VEX_0F385E_X86_64_L_0_W_0, 1139 PREFIX_VEX_0F386C_X86_64_L_0_W_0, 1140 PREFIX_VEX_0F3872, 1141 PREFIX_VEX_0F38B0_W_0, 1142 PREFIX_VEX_0F38B1_W_0, 1143 PREFIX_VEX_0F38D2_W_0, 1144 PREFIX_VEX_0F38D3_W_0, 1145 PREFIX_VEX_0F38CB, 1146 PREFIX_VEX_0F38CC, 1147 PREFIX_VEX_0F38CD, 1148 PREFIX_VEX_0F38DA_W_0, 1149 PREFIX_VEX_0F38F2_L_0, 1150 PREFIX_VEX_0F38F3_L_0, 1151 PREFIX_VEX_0F38F5_L_0, 1152 PREFIX_VEX_0F38F6_L_0, 1153 PREFIX_VEX_0F38F7_L_0, 1154 PREFIX_VEX_0F3AF0_L_0, 1155 PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, 1156 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, 1157 1158 PREFIX_EVEX_0F2E, 1159 PREFIX_EVEX_0F2F, 1160 PREFIX_EVEX_0F5B, 1161 PREFIX_EVEX_0F6F, 1162 PREFIX_EVEX_0F70, 1163 PREFIX_EVEX_0F78, 1164 PREFIX_EVEX_0F79, 1165 PREFIX_EVEX_0F7A, 1166 PREFIX_EVEX_0F7B, 1167 PREFIX_EVEX_0F7E, 1168 PREFIX_EVEX_0F7F, 1169 PREFIX_EVEX_0FC2, 1170 PREFIX_EVEX_0FE6, 1171 PREFIX_EVEX_0F3810, 1172 PREFIX_EVEX_0F3811, 1173 PREFIX_EVEX_0F3812, 1174 PREFIX_EVEX_0F3813, 1175 PREFIX_EVEX_0F3814, 1176 PREFIX_EVEX_0F3815, 1177 PREFIX_EVEX_0F3820, 1178 PREFIX_EVEX_0F3821, 1179 PREFIX_EVEX_0F3822, 1180 PREFIX_EVEX_0F3823, 1181 PREFIX_EVEX_0F3824, 1182 PREFIX_EVEX_0F3825, 1183 PREFIX_EVEX_0F3826, 1184 PREFIX_EVEX_0F3827, 1185 PREFIX_EVEX_0F3828, 1186 PREFIX_EVEX_0F3829, 1187 PREFIX_EVEX_0F382A, 1188 PREFIX_EVEX_0F3830, 1189 PREFIX_EVEX_0F3831, 1190 PREFIX_EVEX_0F3832, 1191 PREFIX_EVEX_0F3833, 1192 PREFIX_EVEX_0F3834, 1193 PREFIX_EVEX_0F3835, 1194 PREFIX_EVEX_0F3838, 1195 PREFIX_EVEX_0F3839, 1196 PREFIX_EVEX_0F383A, 1197 PREFIX_EVEX_0F3852, 1198 PREFIX_EVEX_0F3853, 1199 PREFIX_EVEX_0F3868, 1200 PREFIX_EVEX_0F3872, 1201 PREFIX_EVEX_0F3874, 1202 PREFIX_EVEX_0F389A, 1203 PREFIX_EVEX_0F389B, 1204 PREFIX_EVEX_0F38AA, 1205 PREFIX_EVEX_0F38AB, 1206 1207 PREFIX_EVEX_0F3A08, 1208 PREFIX_EVEX_0F3A0A, 1209 PREFIX_EVEX_0F3A26, 1210 PREFIX_EVEX_0F3A27, 1211 PREFIX_EVEX_0F3A42_W_0, 1212 PREFIX_EVEX_0F3A52, 1213 PREFIX_EVEX_0F3A53, 1214 PREFIX_EVEX_0F3A56, 1215 PREFIX_EVEX_0F3A57, 1216 PREFIX_EVEX_0F3A66, 1217 PREFIX_EVEX_0F3A67, 1218 PREFIX_EVEX_0F3AC2, 1219 1220 PREFIX_EVEX_MAP4_4x, 1221 PREFIX_EVEX_MAP4_F0, 1222 PREFIX_EVEX_MAP4_F1, 1223 PREFIX_EVEX_MAP4_F2, 1224 PREFIX_EVEX_MAP4_F8, 1225 1226 PREFIX_EVEX_MAP5_10, 1227 PREFIX_EVEX_MAP5_11, 1228 PREFIX_EVEX_MAP5_18, 1229 PREFIX_EVEX_MAP5_1B, 1230 PREFIX_EVEX_MAP5_1D, 1231 PREFIX_EVEX_MAP5_1E, 1232 PREFIX_EVEX_MAP5_2A, 1233 PREFIX_EVEX_MAP5_2C, 1234 PREFIX_EVEX_MAP5_2D, 1235 PREFIX_EVEX_MAP5_2E, 1236 PREFIX_EVEX_MAP5_2F, 1237 PREFIX_EVEX_MAP5_51, 1238 PREFIX_EVEX_MAP5_58, 1239 PREFIX_EVEX_MAP5_59, 1240 PREFIX_EVEX_MAP5_5A, 1241 PREFIX_EVEX_MAP5_5B, 1242 PREFIX_EVEX_MAP5_5C, 1243 PREFIX_EVEX_MAP5_5D, 1244 PREFIX_EVEX_MAP5_5E, 1245 PREFIX_EVEX_MAP5_5F, 1246 PREFIX_EVEX_MAP5_68, 1247 PREFIX_EVEX_MAP5_69, 1248 PREFIX_EVEX_MAP5_6A, 1249 PREFIX_EVEX_MAP5_6B, 1250 PREFIX_EVEX_MAP5_6C, 1251 PREFIX_EVEX_MAP5_6D, 1252 PREFIX_EVEX_MAP5_6E_L_0, 1253 PREFIX_EVEX_MAP5_74, 1254 PREFIX_EVEX_MAP5_78, 1255 PREFIX_EVEX_MAP5_79, 1256 PREFIX_EVEX_MAP5_7A, 1257 PREFIX_EVEX_MAP5_7B, 1258 PREFIX_EVEX_MAP5_7C, 1259 PREFIX_EVEX_MAP5_7D, 1260 PREFIX_EVEX_MAP5_7E_L_0, 1261 1262 PREFIX_EVEX_MAP6_13, 1263 PREFIX_EVEX_MAP6_2C, 1264 PREFIX_EVEX_MAP6_42, 1265 PREFIX_EVEX_MAP6_4C, 1266 PREFIX_EVEX_MAP6_4E, 1267 PREFIX_EVEX_MAP6_56, 1268 PREFIX_EVEX_MAP6_57, 1269 PREFIX_EVEX_MAP6_98, 1270 PREFIX_EVEX_MAP6_9A, 1271 PREFIX_EVEX_MAP6_9C, 1272 PREFIX_EVEX_MAP6_9E, 1273 PREFIX_EVEX_MAP6_A8, 1274 PREFIX_EVEX_MAP6_AA, 1275 PREFIX_EVEX_MAP6_AC, 1276 PREFIX_EVEX_MAP6_AE, 1277 PREFIX_EVEX_MAP6_B8, 1278 PREFIX_EVEX_MAP6_BA, 1279 PREFIX_EVEX_MAP6_BC, 1280 PREFIX_EVEX_MAP6_BE, 1281 PREFIX_EVEX_MAP6_D6, 1282 PREFIX_EVEX_MAP6_D7, 1283 }; 1284 1285 enum 1286 { 1287 X86_64_06 = 0, 1288 X86_64_07, 1289 X86_64_0E, 1290 X86_64_16, 1291 X86_64_17, 1292 X86_64_1E, 1293 X86_64_1F, 1294 X86_64_27, 1295 X86_64_2F, 1296 X86_64_37, 1297 X86_64_3F, 1298 X86_64_60, 1299 X86_64_61, 1300 X86_64_62, 1301 X86_64_63, 1302 X86_64_6D, 1303 X86_64_6F, 1304 X86_64_82, 1305 X86_64_9A, 1306 X86_64_C2, 1307 X86_64_C3, 1308 X86_64_C4, 1309 X86_64_C5, 1310 X86_64_CE, 1311 X86_64_D4, 1312 X86_64_D5, 1313 X86_64_E8, 1314 X86_64_E9, 1315 X86_64_EA, 1316 X86_64_0F00_REG_6, 1317 X86_64_0F01_REG_0, 1318 X86_64_0F01_REG_0_MOD_3_RM_6_P_1, 1319 X86_64_0F01_REG_0_MOD_3_RM_6_P_3, 1320 X86_64_0F01_REG_0_MOD_3_RM_7_P_0, 1321 X86_64_0F01_REG_1, 1322 X86_64_0F01_REG_1_RM_2_PREFIX_1, 1323 X86_64_0F01_REG_1_RM_2_PREFIX_3, 1324 X86_64_0F01_REG_1_RM_5_PREFIX_2, 1325 X86_64_0F01_REG_1_RM_6_PREFIX_2, 1326 X86_64_0F01_REG_1_RM_7_PREFIX_2, 1327 X86_64_0F01_REG_2, 1328 X86_64_0F01_REG_3, 1329 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, 1330 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, 1331 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, 1332 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, 1333 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1, 1334 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, 1335 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, 1336 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, 1337 X86_64_0F18_REG_6_MOD_0, 1338 X86_64_0F18_REG_7_MOD_0, 1339 X86_64_0F24, 1340 X86_64_0F26, 1341 X86_64_0F38F8_M_1, 1342 X86_64_0FC7_REG_6_MOD_3_PREFIX_1, 1343 1344 X86_64_VEX_0F3849, 1345 X86_64_VEX_0F384B, 1346 X86_64_VEX_0F385C, 1347 X86_64_VEX_0F385E, 1348 X86_64_VEX_0F386C, 1349 X86_64_VEX_0F38Ex, 1350 1351 X86_64_VEX_MAP7_F6_L_0_W_0_R_0, 1352 X86_64_VEX_MAP7_F8_L_0_W_0_R_0, 1353 }; 1354 1355 enum 1356 { 1357 THREE_BYTE_0F38 = 0, 1358 THREE_BYTE_0F3A 1359 }; 1360 1361 enum 1362 { 1363 XOP_08 = 0, 1364 XOP_09, 1365 XOP_0A 1366 }; 1367 1368 enum 1369 { 1370 VEX_0F = 0, 1371 VEX_0F38, 1372 VEX_0F3A, 1373 VEX_MAP7, 1374 }; 1375 1376 enum 1377 { 1378 EVEX_0F = 0, 1379 EVEX_0F38, 1380 EVEX_0F3A, 1381 EVEX_MAP4, 1382 EVEX_MAP5, 1383 EVEX_MAP6, 1384 EVEX_MAP7, 1385 }; 1386 1387 enum 1388 { 1389 VEX_LEN_0F12_P_0 = 0, 1390 VEX_LEN_0F12_P_2, 1391 VEX_LEN_0F13, 1392 VEX_LEN_0F16_P_0, 1393 VEX_LEN_0F16_P_2, 1394 VEX_LEN_0F17, 1395 VEX_LEN_0F41, 1396 VEX_LEN_0F42, 1397 VEX_LEN_0F44, 1398 VEX_LEN_0F45, 1399 VEX_LEN_0F46, 1400 VEX_LEN_0F47, 1401 VEX_LEN_0F4A, 1402 VEX_LEN_0F4B, 1403 VEX_LEN_0F6E, 1404 VEX_LEN_0F77, 1405 VEX_LEN_0F7E_P_1, 1406 VEX_LEN_0F7E_P_2, 1407 VEX_LEN_0F90, 1408 VEX_LEN_0F91, 1409 VEX_LEN_0F92, 1410 VEX_LEN_0F93, 1411 VEX_LEN_0F98, 1412 VEX_LEN_0F99, 1413 VEX_LEN_0FAE_R_2, 1414 VEX_LEN_0FAE_R_3, 1415 VEX_LEN_0FC4, 1416 VEX_LEN_0FD6, 1417 VEX_LEN_0F3816, 1418 VEX_LEN_0F3819, 1419 VEX_LEN_0F381A, 1420 VEX_LEN_0F3836, 1421 VEX_LEN_0F3841, 1422 VEX_LEN_0F3849_X86_64, 1423 VEX_LEN_0F384B_X86_64, 1424 VEX_LEN_0F385A, 1425 VEX_LEN_0F385C_X86_64, 1426 VEX_LEN_0F385E_X86_64, 1427 VEX_LEN_0F386C_X86_64, 1428 VEX_LEN_0F38CB_P_3_W_0, 1429 VEX_LEN_0F38CC_P_3_W_0, 1430 VEX_LEN_0F38CD_P_3_W_0, 1431 VEX_LEN_0F38DA_W_0_P_0, 1432 VEX_LEN_0F38DA_W_0_P_2, 1433 VEX_LEN_0F38DB, 1434 VEX_LEN_0F38F2, 1435 VEX_LEN_0F38F3, 1436 VEX_LEN_0F38F5, 1437 VEX_LEN_0F38F6, 1438 VEX_LEN_0F38F7, 1439 VEX_LEN_0F3A00, 1440 VEX_LEN_0F3A01, 1441 VEX_LEN_0F3A06, 1442 VEX_LEN_0F3A14, 1443 VEX_LEN_0F3A15, 1444 VEX_LEN_0F3A16, 1445 VEX_LEN_0F3A17, 1446 VEX_LEN_0F3A18, 1447 VEX_LEN_0F3A19, 1448 VEX_LEN_0F3A20, 1449 VEX_LEN_0F3A21, 1450 VEX_LEN_0F3A22, 1451 VEX_LEN_0F3A30, 1452 VEX_LEN_0F3A31, 1453 VEX_LEN_0F3A32, 1454 VEX_LEN_0F3A33, 1455 VEX_LEN_0F3A38, 1456 VEX_LEN_0F3A39, 1457 VEX_LEN_0F3A41, 1458 VEX_LEN_0F3A46, 1459 VEX_LEN_0F3A60, 1460 VEX_LEN_0F3A61, 1461 VEX_LEN_0F3A62, 1462 VEX_LEN_0F3A63, 1463 VEX_LEN_0F3ADE_W_0, 1464 VEX_LEN_0F3ADF, 1465 VEX_LEN_0F3AF0, 1466 VEX_LEN_MAP7_F6, 1467 VEX_LEN_MAP7_F8, 1468 VEX_LEN_XOP_08_85, 1469 VEX_LEN_XOP_08_86, 1470 VEX_LEN_XOP_08_87, 1471 VEX_LEN_XOP_08_8E, 1472 VEX_LEN_XOP_08_8F, 1473 VEX_LEN_XOP_08_95, 1474 VEX_LEN_XOP_08_96, 1475 VEX_LEN_XOP_08_97, 1476 VEX_LEN_XOP_08_9E, 1477 VEX_LEN_XOP_08_9F, 1478 VEX_LEN_XOP_08_A3, 1479 VEX_LEN_XOP_08_A6, 1480 VEX_LEN_XOP_08_B6, 1481 VEX_LEN_XOP_08_C0, 1482 VEX_LEN_XOP_08_C1, 1483 VEX_LEN_XOP_08_C2, 1484 VEX_LEN_XOP_08_C3, 1485 VEX_LEN_XOP_08_CC, 1486 VEX_LEN_XOP_08_CD, 1487 VEX_LEN_XOP_08_CE, 1488 VEX_LEN_XOP_08_CF, 1489 VEX_LEN_XOP_08_EC, 1490 VEX_LEN_XOP_08_ED, 1491 VEX_LEN_XOP_08_EE, 1492 VEX_LEN_XOP_08_EF, 1493 VEX_LEN_XOP_09_01, 1494 VEX_LEN_XOP_09_02, 1495 VEX_LEN_XOP_09_12, 1496 VEX_LEN_XOP_09_82_W_0, 1497 VEX_LEN_XOP_09_83_W_0, 1498 VEX_LEN_XOP_09_90, 1499 VEX_LEN_XOP_09_91, 1500 VEX_LEN_XOP_09_92, 1501 VEX_LEN_XOP_09_93, 1502 VEX_LEN_XOP_09_94, 1503 VEX_LEN_XOP_09_95, 1504 VEX_LEN_XOP_09_96, 1505 VEX_LEN_XOP_09_97, 1506 VEX_LEN_XOP_09_98, 1507 VEX_LEN_XOP_09_99, 1508 VEX_LEN_XOP_09_9A, 1509 VEX_LEN_XOP_09_9B, 1510 VEX_LEN_XOP_09_C1, 1511 VEX_LEN_XOP_09_C2, 1512 VEX_LEN_XOP_09_C3, 1513 VEX_LEN_XOP_09_C6, 1514 VEX_LEN_XOP_09_C7, 1515 VEX_LEN_XOP_09_CB, 1516 VEX_LEN_XOP_09_D1, 1517 VEX_LEN_XOP_09_D2, 1518 VEX_LEN_XOP_09_D3, 1519 VEX_LEN_XOP_09_D6, 1520 VEX_LEN_XOP_09_D7, 1521 VEX_LEN_XOP_09_DB, 1522 VEX_LEN_XOP_09_E1, 1523 VEX_LEN_XOP_09_E2, 1524 VEX_LEN_XOP_09_E3, 1525 VEX_LEN_XOP_0A_12, 1526 }; 1527 1528 enum 1529 { 1530 EVEX_LEN_0F7E_P_1_W_0 = 0, 1531 EVEX_LEN_0FD6_P_2_W_0, 1532 EVEX_LEN_0F3816, 1533 EVEX_LEN_0F3819, 1534 EVEX_LEN_0F381A, 1535 EVEX_LEN_0F381B, 1536 EVEX_LEN_0F3836, 1537 EVEX_LEN_0F385A, 1538 EVEX_LEN_0F385B, 1539 EVEX_LEN_0F38C6, 1540 EVEX_LEN_0F38C7, 1541 EVEX_LEN_0F3A00, 1542 EVEX_LEN_0F3A01, 1543 EVEX_LEN_0F3A18, 1544 EVEX_LEN_0F3A19, 1545 EVEX_LEN_0F3A1A, 1546 EVEX_LEN_0F3A1B, 1547 EVEX_LEN_0F3A23, 1548 EVEX_LEN_0F3A38, 1549 EVEX_LEN_0F3A39, 1550 EVEX_LEN_0F3A3A, 1551 EVEX_LEN_0F3A3B, 1552 EVEX_LEN_0F3A43, 1553 1554 EVEX_LEN_MAP5_6E, 1555 EVEX_LEN_MAP5_7E, 1556 }; 1557 1558 enum 1559 { 1560 VEX_W_0F41_L_1 = 0, 1561 VEX_W_0F42_L_1, 1562 VEX_W_0F44_L_0, 1563 VEX_W_0F45_L_1, 1564 VEX_W_0F46_L_1, 1565 VEX_W_0F47_L_1, 1566 VEX_W_0F4A_L_1, 1567 VEX_W_0F4B_L_1, 1568 VEX_W_0F90_L_0, 1569 VEX_W_0F91_L_0, 1570 VEX_W_0F92_L_0, 1571 VEX_W_0F93_L_0, 1572 VEX_W_0F98_L_0, 1573 VEX_W_0F99_L_0, 1574 VEX_W_0F380C, 1575 VEX_W_0F380D, 1576 VEX_W_0F380E, 1577 VEX_W_0F380F, 1578 VEX_W_0F3813, 1579 VEX_W_0F3816_L_1, 1580 VEX_W_0F3818, 1581 VEX_W_0F3819_L_1, 1582 VEX_W_0F381A_L_1, 1583 VEX_W_0F382C, 1584 VEX_W_0F382D, 1585 VEX_W_0F382E, 1586 VEX_W_0F382F, 1587 VEX_W_0F3836, 1588 VEX_W_0F3846, 1589 VEX_W_0F3849_X86_64_L_0, 1590 VEX_W_0F384B_X86_64_L_0, 1591 VEX_W_0F3850, 1592 VEX_W_0F3851, 1593 VEX_W_0F3852, 1594 VEX_W_0F3853, 1595 VEX_W_0F3858, 1596 VEX_W_0F3859, 1597 VEX_W_0F385A_L_0, 1598 VEX_W_0F385C_X86_64_L_0, 1599 VEX_W_0F385E_X86_64_L_0, 1600 VEX_W_0F386C_X86_64_L_0, 1601 VEX_W_0F3872_P_1, 1602 VEX_W_0F3878, 1603 VEX_W_0F3879, 1604 VEX_W_0F38B0, 1605 VEX_W_0F38B1, 1606 VEX_W_0F38B4, 1607 VEX_W_0F38B5, 1608 VEX_W_0F38CB_P_3, 1609 VEX_W_0F38CC_P_3, 1610 VEX_W_0F38CD_P_3, 1611 VEX_W_0F38CF, 1612 VEX_W_0F38D2, 1613 VEX_W_0F38D3, 1614 VEX_W_0F38DA, 1615 VEX_W_0F3A00_L_1, 1616 VEX_W_0F3A01_L_1, 1617 VEX_W_0F3A02, 1618 VEX_W_0F3A04, 1619 VEX_W_0F3A05, 1620 VEX_W_0F3A06_L_1, 1621 VEX_W_0F3A18_L_1, 1622 VEX_W_0F3A19_L_1, 1623 VEX_W_0F3A1D, 1624 VEX_W_0F3A38_L_1, 1625 VEX_W_0F3A39_L_1, 1626 VEX_W_0F3A46_L_1, 1627 VEX_W_0F3A4A, 1628 VEX_W_0F3A4B, 1629 VEX_W_0F3A4C, 1630 VEX_W_0F3ACE, 1631 VEX_W_0F3ACF, 1632 VEX_W_0F3ADE, 1633 VEX_W_MAP7_F6_L_0, 1634 VEX_W_MAP7_F8_L_0, 1635 1636 VEX_W_XOP_08_85_L_0, 1637 VEX_W_XOP_08_86_L_0, 1638 VEX_W_XOP_08_87_L_0, 1639 VEX_W_XOP_08_8E_L_0, 1640 VEX_W_XOP_08_8F_L_0, 1641 VEX_W_XOP_08_95_L_0, 1642 VEX_W_XOP_08_96_L_0, 1643 VEX_W_XOP_08_97_L_0, 1644 VEX_W_XOP_08_9E_L_0, 1645 VEX_W_XOP_08_9F_L_0, 1646 VEX_W_XOP_08_A6_L_0, 1647 VEX_W_XOP_08_B6_L_0, 1648 VEX_W_XOP_08_C0_L_0, 1649 VEX_W_XOP_08_C1_L_0, 1650 VEX_W_XOP_08_C2_L_0, 1651 VEX_W_XOP_08_C3_L_0, 1652 VEX_W_XOP_08_CC_L_0, 1653 VEX_W_XOP_08_CD_L_0, 1654 VEX_W_XOP_08_CE_L_0, 1655 VEX_W_XOP_08_CF_L_0, 1656 VEX_W_XOP_08_EC_L_0, 1657 VEX_W_XOP_08_ED_L_0, 1658 VEX_W_XOP_08_EE_L_0, 1659 VEX_W_XOP_08_EF_L_0, 1660 1661 VEX_W_XOP_09_80, 1662 VEX_W_XOP_09_81, 1663 VEX_W_XOP_09_82, 1664 VEX_W_XOP_09_83, 1665 VEX_W_XOP_09_C1_L_0, 1666 VEX_W_XOP_09_C2_L_0, 1667 VEX_W_XOP_09_C3_L_0, 1668 VEX_W_XOP_09_C6_L_0, 1669 VEX_W_XOP_09_C7_L_0, 1670 VEX_W_XOP_09_CB_L_0, 1671 VEX_W_XOP_09_D1_L_0, 1672 VEX_W_XOP_09_D2_L_0, 1673 VEX_W_XOP_09_D3_L_0, 1674 VEX_W_XOP_09_D6_L_0, 1675 VEX_W_XOP_09_D7_L_0, 1676 VEX_W_XOP_09_DB_L_0, 1677 VEX_W_XOP_09_E1_L_0, 1678 VEX_W_XOP_09_E2_L_0, 1679 VEX_W_XOP_09_E3_L_0, 1680 1681 EVEX_W_0F5B_P_0, 1682 EVEX_W_0F62, 1683 EVEX_W_0F66, 1684 EVEX_W_0F6A, 1685 EVEX_W_0F6B, 1686 EVEX_W_0F6C, 1687 EVEX_W_0F6D, 1688 EVEX_W_0F6F_P_1, 1689 EVEX_W_0F6F_P_2, 1690 EVEX_W_0F6F_P_3, 1691 EVEX_W_0F70_P_2, 1692 EVEX_W_0F72_R_2, 1693 EVEX_W_0F72_R_4, 1694 EVEX_W_0F72_R_6, 1695 EVEX_W_0F73_R_2, 1696 EVEX_W_0F73_R_6, 1697 EVEX_W_0F76, 1698 EVEX_W_0F78_P_0, 1699 EVEX_W_0F78_P_2, 1700 EVEX_W_0F79_P_0, 1701 EVEX_W_0F79_P_2, 1702 EVEX_W_0F7A_P_1, 1703 EVEX_W_0F7A_P_2, 1704 EVEX_W_0F7A_P_3, 1705 EVEX_W_0F7B_P_2, 1706 EVEX_W_0F7E_P_1, 1707 EVEX_W_0F7F_P_1, 1708 EVEX_W_0F7F_P_2, 1709 EVEX_W_0F7F_P_3, 1710 EVEX_W_0FD2, 1711 EVEX_W_0FD3, 1712 EVEX_W_0FD4, 1713 EVEX_W_0FD6, 1714 EVEX_W_0FE2, 1715 EVEX_W_0FE6_P_1, 1716 EVEX_W_0FE7, 1717 EVEX_W_0FF2, 1718 EVEX_W_0FF3, 1719 EVEX_W_0FF4, 1720 EVEX_W_0FFA, 1721 EVEX_W_0FFB, 1722 EVEX_W_0FFE, 1723 1724 EVEX_W_0F3810_P_1, 1725 EVEX_W_0F3810_P_2, 1726 EVEX_W_0F3811_P_1, 1727 EVEX_W_0F3811_P_2, 1728 EVEX_W_0F3812_P_1, 1729 EVEX_W_0F3812_P_2, 1730 EVEX_W_0F3813_P_1, 1731 EVEX_W_0F3814_P_1, 1732 EVEX_W_0F3815_P_1, 1733 EVEX_W_0F3819_L_n, 1734 EVEX_W_0F381A_L_n, 1735 EVEX_W_0F381B_L_2, 1736 EVEX_W_0F381E, 1737 EVEX_W_0F381F, 1738 EVEX_W_0F3820_P_1, 1739 EVEX_W_0F3821_P_1, 1740 EVEX_W_0F3822_P_1, 1741 EVEX_W_0F3823_P_1, 1742 EVEX_W_0F3824_P_1, 1743 EVEX_W_0F3825_P_1, 1744 EVEX_W_0F3825_P_2, 1745 EVEX_W_0F3828_P_2, 1746 EVEX_W_0F3829_P_2, 1747 EVEX_W_0F382A_P_1, 1748 EVEX_W_0F382A_P_2, 1749 EVEX_W_0F382B, 1750 EVEX_W_0F3830_P_1, 1751 EVEX_W_0F3831_P_1, 1752 EVEX_W_0F3832_P_1, 1753 EVEX_W_0F3833_P_1, 1754 EVEX_W_0F3834_P_1, 1755 EVEX_W_0F3835_P_1, 1756 EVEX_W_0F3835_P_2, 1757 EVEX_W_0F3837, 1758 EVEX_W_0F383A_P_1, 1759 EVEX_W_0F3859, 1760 EVEX_W_0F385A_L_n, 1761 EVEX_W_0F385B_L_2, 1762 EVEX_W_0F3870, 1763 EVEX_W_0F3872_P_2, 1764 EVEX_W_0F387A, 1765 EVEX_W_0F387B, 1766 EVEX_W_0F3883, 1767 1768 EVEX_W_0F3A18_L_n, 1769 EVEX_W_0F3A19_L_n, 1770 EVEX_W_0F3A1A_L_2, 1771 EVEX_W_0F3A1B_L_2, 1772 EVEX_W_0F3A21, 1773 EVEX_W_0F3A23_L_n, 1774 EVEX_W_0F3A38_L_n, 1775 EVEX_W_0F3A39_L_n, 1776 EVEX_W_0F3A3A_L_2, 1777 EVEX_W_0F3A3B_L_2, 1778 EVEX_W_0F3A42, 1779 EVEX_W_0F3A43_L_n, 1780 EVEX_W_0F3A70, 1781 EVEX_W_0F3A72, 1782 1783 EVEX_W_MAP4_8F_R_0, 1784 EVEX_W_MAP4_F8_P1_M_1, 1785 EVEX_W_MAP4_F8_P3_M_1, 1786 EVEX_W_MAP4_FF_R_6, 1787 1788 EVEX_W_MAP5_5B_P_0, 1789 EVEX_W_MAP5_6C_P_0, 1790 EVEX_W_MAP5_6C_P_2, 1791 EVEX_W_MAP5_6D_P_0, 1792 EVEX_W_MAP5_6D_P_2, 1793 EVEX_W_MAP5_6E_P_1, 1794 EVEX_W_MAP5_7A_P_3, 1795 EVEX_W_MAP5_7E_P_1, 1796 }; 1797 1798 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag); 1799 1800 struct dis386 { 1801 const char *name; 1802 struct 1803 { 1804 op_rtn rtn; 1805 int bytemode; 1806 } op[MAX_OPERANDS]; 1807 unsigned int prefix_requirement; 1808 }; 1809 1810 /* Upper case letters in the instruction names here are macros. 1811 'A' => print 'b' if no (suitable) register operand or suffix_always is true 1812 'B' => print 'b' if suffix_always is true 1813 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 1814 size prefix 1815 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 1816 suffix_always is true 1817 'E' => print 'e' if 32-bit form of jcxz 1818 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 1819 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 1820 'H' => print ",pt" or ",pn" branch hint 1821 'I' unused. 1822 'J' unused. 1823 'K' => print 'd' or 'q' if rex prefix is present. 1824 'L' => print 'l' or 'q' if suffix_always is true 1825 'M' => print 'r' if intel_mnemonic is false. 1826 'N' => print 'n' if instruction has no wait "prefix" 1827 'O' => print 'd' or 'o' (or 'q' in Intel mode) 1828 'P' => behave as 'T' except with register operand outside of suffix_always 1829 mode 1830 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or 1831 suffix_always is true 1832 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 1833 'S' => print 'w', 'l' or 'q' if suffix_always is true 1834 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size 1835 prefix or if suffix_always is true. 1836 'U' unused. 1837 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings. 1838 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 1839 'X' => print 's', 'd' depending on data16 prefix (for XMM) 1840 'Y' => no output, mark EVEX.aaa != 0 as bad. 1841 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. 1842 '!' => change condition from true to false or from false to true. 1843 '%' => add 1 upper case letter to the macro. 1844 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size 1845 prefix or suffix_always is true (lcall/ljmp). 1846 '@' => in 64bit mode for Intel64 ISA or if instruction 1847 has no operand sizing prefix, print 'q' if suffix_always is true or 1848 nothing otherwise; behave as 'P' in all other cases 1849 1850 2 upper case letter macros: 1851 "CC" => print condition code 1852 "XY" => print 'x' or 'y' if suffix_always is true or no register 1853 operands and no broadcast. 1854 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no 1855 register operands and no broadcast. 1856 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) 1857 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding 1858 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16) 1859 "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding 1860 (for BF16) 1861 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding 1862 "XV" => print "{vex} " pseudo prefix 1863 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is 1864 is used by an EVEX-encoded (AVX512VL) instruction. 1865 "ME" => Similar to "XE", but only print "{evex} " when there is no 1866 memory operand. 1867 "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} " 1868 pseudo prefix when instructions without NF, EGPR and VVVV, 1869 "NE" => don't print "{evex} " pseudo prefix for some special instructions 1870 in MAP4. 1871 "ZU" => print 'zu' if EVEX.ZU=1. 1872 "SC" => print suffix SCC for SCC insns 1873 "YK" keep unused, to avoid ambiguity with the combined use of Y and K. 1874 "YX" keep unused, to avoid ambiguity with the combined use of Y and X. 1875 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond 1876 being false, or no operand at all in 64bit mode, or if suffix_always 1877 is true. 1878 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise 1879 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise 1880 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise 1881 "DQ" => print 'd' or 'q' depending on the VEX.W bit 1882 "DF" => print default flag value for SCC insns 1883 "BW" => print 'b' or 'w' depending on the VEX.W bit 1884 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has 1885 an operand size prefix, or suffix_always is true. print 1886 'q' if rex prefix is present. 1887 1888 Many of the above letters print nothing in Intel mode. See "putop" 1889 for the details. 1890 1891 Braces '{' and '}', and vertical bars '|', indicate alternative 1892 mnemonic strings for AT&T and Intel. */ 1893 1894 static const struct dis386 dis386[] = { 1895 /* 00 */ 1896 { "addB", { Ebh1, Gb }, 0 }, 1897 { "addS", { Evh1, Gv }, 0 }, 1898 { "addB", { Gb, EbS }, 0 }, 1899 { "addS", { Gv, EvS }, 0 }, 1900 { "addB", { AL, Ib }, 0 }, 1901 { "addS", { eAX, Iv }, 0 }, 1902 { X86_64_TABLE (X86_64_06) }, 1903 { X86_64_TABLE (X86_64_07) }, 1904 /* 08 */ 1905 { "orB", { Ebh1, Gb }, 0 }, 1906 { "orS", { Evh1, Gv }, 0 }, 1907 { "orB", { Gb, EbS }, 0 }, 1908 { "orS", { Gv, EvS }, 0 }, 1909 { "orB", { AL, Ib }, 0 }, 1910 { "orS", { eAX, Iv }, 0 }, 1911 { X86_64_TABLE (X86_64_0E) }, 1912 { Bad_Opcode }, /* 0x0f extended opcode escape */ 1913 /* 10 */ 1914 { "adcB", { Ebh1, Gb }, 0 }, 1915 { "adcS", { Evh1, Gv }, 0 }, 1916 { "adcB", { Gb, EbS }, 0 }, 1917 { "adcS", { Gv, EvS }, 0 }, 1918 { "adcB", { AL, Ib }, 0 }, 1919 { "adcS", { eAX, Iv }, 0 }, 1920 { X86_64_TABLE (X86_64_16) }, 1921 { X86_64_TABLE (X86_64_17) }, 1922 /* 18 */ 1923 { "sbbB", { Ebh1, Gb }, 0 }, 1924 { "sbbS", { Evh1, Gv }, 0 }, 1925 { "sbbB", { Gb, EbS }, 0 }, 1926 { "sbbS", { Gv, EvS }, 0 }, 1927 { "sbbB", { AL, Ib }, 0 }, 1928 { "sbbS", { eAX, Iv }, 0 }, 1929 { X86_64_TABLE (X86_64_1E) }, 1930 { X86_64_TABLE (X86_64_1F) }, 1931 /* 20 */ 1932 { "andB", { Ebh1, Gb }, 0 }, 1933 { "andS", { Evh1, Gv }, 0 }, 1934 { "andB", { Gb, EbS }, 0 }, 1935 { "andS", { Gv, EvS }, 0 }, 1936 { "andB", { AL, Ib }, 0 }, 1937 { "andS", { eAX, Iv }, 0 }, 1938 { Bad_Opcode }, /* SEG ES prefix */ 1939 { X86_64_TABLE (X86_64_27) }, 1940 /* 28 */ 1941 { "subB", { Ebh1, Gb }, 0 }, 1942 { "subS", { Evh1, Gv }, 0 }, 1943 { "subB", { Gb, EbS }, 0 }, 1944 { "subS", { Gv, EvS }, 0 }, 1945 { "subB", { AL, Ib }, 0 }, 1946 { "subS", { eAX, Iv }, 0 }, 1947 { Bad_Opcode }, /* SEG CS prefix */ 1948 { X86_64_TABLE (X86_64_2F) }, 1949 /* 30 */ 1950 { "xorB", { Ebh1, Gb }, 0 }, 1951 { "xorS", { Evh1, Gv }, 0 }, 1952 { "xorB", { Gb, EbS }, 0 }, 1953 { "xorS", { Gv, EvS }, 0 }, 1954 { "xorB", { AL, Ib }, 0 }, 1955 { "xorS", { eAX, Iv }, 0 }, 1956 { Bad_Opcode }, /* SEG SS prefix */ 1957 { X86_64_TABLE (X86_64_37) }, 1958 /* 38 */ 1959 { "cmpB", { Eb, Gb }, 0 }, 1960 { "cmpS", { Ev, Gv }, 0 }, 1961 { "cmpB", { Gb, EbS }, 0 }, 1962 { "cmpS", { Gv, EvS }, 0 }, 1963 { "cmpB", { AL, Ib }, 0 }, 1964 { "cmpS", { eAX, Iv }, 0 }, 1965 { Bad_Opcode }, /* SEG DS prefix */ 1966 { X86_64_TABLE (X86_64_3F) }, 1967 /* 40 */ 1968 { "inc{S|}", { RMeAX }, 0 }, 1969 { "inc{S|}", { RMeCX }, 0 }, 1970 { "inc{S|}", { RMeDX }, 0 }, 1971 { "inc{S|}", { RMeBX }, 0 }, 1972 { "inc{S|}", { RMeSP }, 0 }, 1973 { "inc{S|}", { RMeBP }, 0 }, 1974 { "inc{S|}", { RMeSI }, 0 }, 1975 { "inc{S|}", { RMeDI }, 0 }, 1976 /* 48 */ 1977 { "dec{S|}", { RMeAX }, 0 }, 1978 { "dec{S|}", { RMeCX }, 0 }, 1979 { "dec{S|}", { RMeDX }, 0 }, 1980 { "dec{S|}", { RMeBX }, 0 }, 1981 { "dec{S|}", { RMeSP }, 0 }, 1982 { "dec{S|}", { RMeBP }, 0 }, 1983 { "dec{S|}", { RMeSI }, 0 }, 1984 { "dec{S|}", { RMeDI }, 0 }, 1985 /* 50 */ 1986 { "push!P", { RMrAX }, 0 }, 1987 { "push!P", { RMrCX }, 0 }, 1988 { "push!P", { RMrDX }, 0 }, 1989 { "push!P", { RMrBX }, 0 }, 1990 { "push!P", { RMrSP }, 0 }, 1991 { "push!P", { RMrBP }, 0 }, 1992 { "push!P", { RMrSI }, 0 }, 1993 { "push!P", { RMrDI }, 0 }, 1994 /* 58 */ 1995 { "pop!P", { RMrAX }, 0 }, 1996 { "pop!P", { RMrCX }, 0 }, 1997 { "pop!P", { RMrDX }, 0 }, 1998 { "pop!P", { RMrBX }, 0 }, 1999 { "pop!P", { RMrSP }, 0 }, 2000 { "pop!P", { RMrBP }, 0 }, 2001 { "pop!P", { RMrSI }, 0 }, 2002 { "pop!P", { RMrDI }, 0 }, 2003 /* 60 */ 2004 { X86_64_TABLE (X86_64_60) }, 2005 { X86_64_TABLE (X86_64_61) }, 2006 { X86_64_TABLE (X86_64_62) }, 2007 { X86_64_TABLE (X86_64_63) }, 2008 { Bad_Opcode }, /* seg fs */ 2009 { Bad_Opcode }, /* seg gs */ 2010 { Bad_Opcode }, /* op size prefix */ 2011 { Bad_Opcode }, /* adr size prefix */ 2012 /* 68 */ 2013 { "pushP", { sIv }, 0 }, 2014 { "imulS", { Gv, Ev, Iv }, 0 }, 2015 { "pushP", { sIbT }, 0 }, 2016 { "imulS", { Gv, Ev, sIb }, 0 }, 2017 { "ins{b|}", { Ybr, indirDX }, 0 }, 2018 { X86_64_TABLE (X86_64_6D) }, 2019 { "outs{b|}", { indirDXr, Xb }, 0 }, 2020 { X86_64_TABLE (X86_64_6F) }, 2021 /* 70 */ 2022 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2023 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2024 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2025 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2026 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2027 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2028 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2029 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2030 /* 78 */ 2031 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2032 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2033 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2034 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2035 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2036 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2037 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2038 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2039 /* 80 */ 2040 { REG_TABLE (REG_80) }, 2041 { REG_TABLE (REG_81) }, 2042 { X86_64_TABLE (X86_64_82) }, 2043 { REG_TABLE (REG_83) }, 2044 { "testB", { Eb, Gb }, 0 }, 2045 { "testS", { Ev, Gv }, 0 }, 2046 { "xchgB", { Ebh2, Gb }, 0 }, 2047 { "xchgS", { Evh2, Gv }, 0 }, 2048 /* 88 */ 2049 { "movB", { Ebh3, Gb }, 0 }, 2050 { "movS", { Evh3, Gv }, 0 }, 2051 { "movB", { Gb, EbS }, 0 }, 2052 { "movS", { Gv, EvS }, 0 }, 2053 { "movD", { Sv, Sw }, 0 }, 2054 { "leaS", { Gv, M }, 0 }, 2055 { "movD", { Sw, Sv }, 0 }, 2056 { REG_TABLE (REG_8F) }, 2057 /* 90 */ 2058 { PREFIX_TABLE (PREFIX_90) }, 2059 { "xchgS", { RMeCX, eAX }, 0 }, 2060 { "xchgS", { RMeDX, eAX }, 0 }, 2061 { "xchgS", { RMeBX, eAX }, 0 }, 2062 { "xchgS", { RMeSP, eAX }, 0 }, 2063 { "xchgS", { RMeBP, eAX }, 0 }, 2064 { "xchgS", { RMeSI, eAX }, 0 }, 2065 { "xchgS", { RMeDI, eAX }, 0 }, 2066 /* 98 */ 2067 { "cW{t|}R", { XX }, 0 }, 2068 { "cR{t|}O", { XX }, 0 }, 2069 { X86_64_TABLE (X86_64_9A) }, 2070 { Bad_Opcode }, /* fwait */ 2071 { "pushfP", { XX }, 0 }, 2072 { "popfP", { XX }, 0 }, 2073 { "sahf", { XX }, 0 }, 2074 { "lahf", { XX }, 0 }, 2075 /* a0 */ 2076 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL }, 2077 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL }, 2078 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL }, 2079 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL }, 2080 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL }, 2081 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL }, 2082 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL }, 2083 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL }, 2084 /* a8 */ 2085 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, 2086 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL }, 2087 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL }, 2088 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL }, 2089 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL }, 2090 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL }, 2091 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL }, 2092 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL }, 2093 /* b0 */ 2094 { "movB", { RMAL, Ib }, 0 }, 2095 { "movB", { RMCL, Ib }, 0 }, 2096 { "movB", { RMDL, Ib }, 0 }, 2097 { "movB", { RMBL, Ib }, 0 }, 2098 { "movB", { RMAH, Ib }, 0 }, 2099 { "movB", { RMCH, Ib }, 0 }, 2100 { "movB", { RMDH, Ib }, 0 }, 2101 { "movB", { RMBH, Ib }, 0 }, 2102 /* b8 */ 2103 { "mov%LV", { RMeAX, Iv64 }, 0 }, 2104 { "mov%LV", { RMeCX, Iv64 }, 0 }, 2105 { "mov%LV", { RMeDX, Iv64 }, 0 }, 2106 { "mov%LV", { RMeBX, Iv64 }, 0 }, 2107 { "mov%LV", { RMeSP, Iv64 }, 0 }, 2108 { "mov%LV", { RMeBP, Iv64 }, 0 }, 2109 { "mov%LV", { RMeSI, Iv64 }, 0 }, 2110 { "mov%LV", { RMeDI, Iv64 }, 0 }, 2111 /* c0 */ 2112 { REG_TABLE (REG_C0) }, 2113 { REG_TABLE (REG_C1) }, 2114 { X86_64_TABLE (X86_64_C2) }, 2115 { X86_64_TABLE (X86_64_C3) }, 2116 { X86_64_TABLE (X86_64_C4) }, 2117 { X86_64_TABLE (X86_64_C5) }, 2118 { REG_TABLE (REG_C6) }, 2119 { REG_TABLE (REG_C7) }, 2120 /* c8 */ 2121 { "enterP", { Iw, Ib }, 0 }, 2122 { "leaveP", { XX }, 0 }, 2123 { "{l|}ret{|f}%LP", { Iw }, 0 }, 2124 { "{l|}ret{|f}%LP", { XX }, 0 }, 2125 { "int3", { XX }, 0 }, 2126 { "int", { Ib }, 0 }, 2127 { X86_64_TABLE (X86_64_CE) }, 2128 { "iret%LP", { XX }, 0 }, 2129 /* d0 */ 2130 { REG_TABLE (REG_D0) }, 2131 { REG_TABLE (REG_D1) }, 2132 { REG_TABLE (REG_D2) }, 2133 { REG_TABLE (REG_D3) }, 2134 { X86_64_TABLE (X86_64_D4) }, 2135 { X86_64_TABLE (X86_64_D5) }, 2136 { Bad_Opcode }, 2137 { "xlat", { DSBX }, 0 }, 2138 /* d8 */ 2139 { FLOAT }, 2140 { FLOAT }, 2141 { FLOAT }, 2142 { FLOAT }, 2143 { FLOAT }, 2144 { FLOAT }, 2145 { FLOAT }, 2146 { FLOAT }, 2147 /* e0 */ 2148 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2149 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2150 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2151 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2152 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, 2153 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL }, 2154 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL }, 2155 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL }, 2156 /* e8 */ 2157 { X86_64_TABLE (X86_64_E8) }, 2158 { X86_64_TABLE (X86_64_E9) }, 2159 { X86_64_TABLE (X86_64_EA) }, 2160 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL }, 2161 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL }, 2162 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL }, 2163 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL }, 2164 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL }, 2165 /* f0 */ 2166 { Bad_Opcode }, /* lock prefix */ 2167 { "int1", { XX }, 0 }, 2168 { Bad_Opcode }, /* repne */ 2169 { Bad_Opcode }, /* repz */ 2170 { "hlt", { XX }, 0 }, 2171 { "cmc", { XX }, 0 }, 2172 { REG_TABLE (REG_F6) }, 2173 { REG_TABLE (REG_F7) }, 2174 /* f8 */ 2175 { "clc", { XX }, 0 }, 2176 { "stc", { XX }, 0 }, 2177 { "cli", { XX }, 0 }, 2178 { "sti", { XX }, 0 }, 2179 { "cld", { XX }, 0 }, 2180 { "std", { XX }, 0 }, 2181 { REG_TABLE (REG_FE) }, 2182 { REG_TABLE (REG_FF) }, 2183 }; 2184 2185 static const struct dis386 dis386_twobyte[] = { 2186 /* 00 */ 2187 { REG_TABLE (REG_0F00 ) }, 2188 { REG_TABLE (REG_0F01 ) }, 2189 { "larS", { Gv, Sv }, 0 }, 2190 { "lslS", { Gv, Sv }, 0 }, 2191 { Bad_Opcode }, 2192 { "syscall", { XX }, 0 }, 2193 { "clts", { XX }, 0 }, 2194 { "sysret%LQ", { XX }, 0 }, 2195 /* 08 */ 2196 { "invd", { XX }, 0 }, 2197 { PREFIX_TABLE (PREFIX_0F09) }, 2198 { Bad_Opcode }, 2199 { "ud2", { XX }, 0 }, 2200 { Bad_Opcode }, 2201 { REG_TABLE (REG_0F0D) }, 2202 { "femms", { XX }, 0 }, 2203 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ 2204 /* 10 */ 2205 { PREFIX_TABLE (PREFIX_0F10) }, 2206 { PREFIX_TABLE (PREFIX_0F11) }, 2207 { PREFIX_TABLE (PREFIX_0F12) }, 2208 { "movlpX", { Mq, XM }, PREFIX_OPCODE }, 2209 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, 2210 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, 2211 { PREFIX_TABLE (PREFIX_0F16) }, 2212 { "movhpX", { Mq, XM }, PREFIX_OPCODE }, 2213 /* 18 */ 2214 { REG_TABLE (REG_0F18) }, 2215 { "nopQ", { Ev }, 0 }, 2216 { PREFIX_TABLE (PREFIX_0F1A) }, 2217 { PREFIX_TABLE (PREFIX_0F1B) }, 2218 { PREFIX_TABLE (PREFIX_0F1C) }, 2219 { "nopQ", { Ev }, 0 }, 2220 { PREFIX_TABLE (PREFIX_0F1E) }, 2221 { "nopQ", { Ev }, 0 }, 2222 /* 20 */ 2223 { "movZ", { Em, Cm }, 0 }, 2224 { "movZ", { Em, Dm }, 0 }, 2225 { "movZ", { Cm, Em }, 0 }, 2226 { "movZ", { Dm, Em }, 0 }, 2227 { X86_64_TABLE (X86_64_0F24) }, 2228 { Bad_Opcode }, 2229 { X86_64_TABLE (X86_64_0F26) }, 2230 { Bad_Opcode }, 2231 /* 28 */ 2232 { "movapX", { XM, EXx }, PREFIX_OPCODE }, 2233 { "movapX", { EXxS, XM }, PREFIX_OPCODE }, 2234 { PREFIX_TABLE (PREFIX_0F2A) }, 2235 { PREFIX_TABLE (PREFIX_0F2B) }, 2236 { PREFIX_TABLE (PREFIX_0F2C) }, 2237 { PREFIX_TABLE (PREFIX_0F2D) }, 2238 { PREFIX_TABLE (PREFIX_0F2E) }, 2239 { PREFIX_TABLE (PREFIX_0F2F) }, 2240 /* 30 */ 2241 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL }, 2242 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL }, 2243 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL }, 2244 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL }, 2245 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL }, 2246 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL }, 2247 { Bad_Opcode }, 2248 { "getsec", { XX }, 0 }, 2249 /* 38 */ 2250 { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, 2251 { Bad_Opcode }, 2252 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, 2253 { Bad_Opcode }, 2254 { Bad_Opcode }, 2255 { Bad_Opcode }, 2256 { Bad_Opcode }, 2257 { Bad_Opcode }, 2258 /* 40 */ 2259 { "cmovoS", { Gv, Ev }, 0 }, 2260 { "cmovnoS", { Gv, Ev }, 0 }, 2261 { "cmovbS", { Gv, Ev }, 0 }, 2262 { "cmovaeS", { Gv, Ev }, 0 }, 2263 { "cmoveS", { Gv, Ev }, 0 }, 2264 { "cmovneS", { Gv, Ev }, 0 }, 2265 { "cmovbeS", { Gv, Ev }, 0 }, 2266 { "cmovaS", { Gv, Ev }, 0 }, 2267 /* 48 */ 2268 { "cmovsS", { Gv, Ev }, 0 }, 2269 { "cmovnsS", { Gv, Ev }, 0 }, 2270 { "cmovpS", { Gv, Ev }, 0 }, 2271 { "cmovnpS", { Gv, Ev }, 0 }, 2272 { "cmovlS", { Gv, Ev }, 0 }, 2273 { "cmovgeS", { Gv, Ev }, 0 }, 2274 { "cmovleS", { Gv, Ev }, 0 }, 2275 { "cmovgS", { Gv, Ev }, 0 }, 2276 /* 50 */ 2277 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE }, 2278 { PREFIX_TABLE (PREFIX_0F51) }, 2279 { PREFIX_TABLE (PREFIX_0F52) }, 2280 { PREFIX_TABLE (PREFIX_0F53) }, 2281 { "andpX", { XM, EXx }, PREFIX_OPCODE }, 2282 { "andnpX", { XM, EXx }, PREFIX_OPCODE }, 2283 { "orpX", { XM, EXx }, PREFIX_OPCODE }, 2284 { "xorpX", { XM, EXx }, PREFIX_OPCODE }, 2285 /* 58 */ 2286 { PREFIX_TABLE (PREFIX_0F58) }, 2287 { PREFIX_TABLE (PREFIX_0F59) }, 2288 { PREFIX_TABLE (PREFIX_0F5A) }, 2289 { PREFIX_TABLE (PREFIX_0F5B) }, 2290 { PREFIX_TABLE (PREFIX_0F5C) }, 2291 { PREFIX_TABLE (PREFIX_0F5D) }, 2292 { PREFIX_TABLE (PREFIX_0F5E) }, 2293 { PREFIX_TABLE (PREFIX_0F5F) }, 2294 /* 60 */ 2295 { PREFIX_TABLE (PREFIX_0F60) }, 2296 { PREFIX_TABLE (PREFIX_0F61) }, 2297 { PREFIX_TABLE (PREFIX_0F62) }, 2298 { "packsswb", { MX, EM }, PREFIX_OPCODE }, 2299 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, 2300 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, 2301 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, 2302 { "packuswb", { MX, EM }, PREFIX_OPCODE }, 2303 /* 68 */ 2304 { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, 2305 { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, 2306 { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, 2307 { "packssdw", { MX, EM }, PREFIX_OPCODE }, 2308 { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, 2309 { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, 2310 { "movK", { MX, Edq }, PREFIX_OPCODE }, 2311 { PREFIX_TABLE (PREFIX_0F6F) }, 2312 /* 70 */ 2313 { PREFIX_TABLE (PREFIX_0F70) }, 2314 { REG_TABLE (REG_0F71) }, 2315 { REG_TABLE (REG_0F72) }, 2316 { REG_TABLE (REG_0F73) }, 2317 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, 2318 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, 2319 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, 2320 { "emms", { XX }, PREFIX_OPCODE }, 2321 /* 78 */ 2322 { PREFIX_TABLE (PREFIX_0F78) }, 2323 { PREFIX_TABLE (PREFIX_0F79) }, 2324 { Bad_Opcode }, 2325 { Bad_Opcode }, 2326 { PREFIX_TABLE (PREFIX_0F7C) }, 2327 { PREFIX_TABLE (PREFIX_0F7D) }, 2328 { PREFIX_TABLE (PREFIX_0F7E) }, 2329 { PREFIX_TABLE (PREFIX_0F7F) }, 2330 /* 80 */ 2331 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2332 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2333 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2334 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2335 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2336 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2337 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2338 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2339 /* 88 */ 2340 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2341 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2342 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2343 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2344 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2345 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2346 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2347 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2348 /* 90 */ 2349 { "seto", { Eb }, 0 }, 2350 { "setno", { Eb }, 0 }, 2351 { "setb", { Eb }, 0 }, 2352 { "setae", { Eb }, 0 }, 2353 { "sete", { Eb }, 0 }, 2354 { "setne", { Eb }, 0 }, 2355 { "setbe", { Eb }, 0 }, 2356 { "seta", { Eb }, 0 }, 2357 /* 98 */ 2358 { "sets", { Eb }, 0 }, 2359 { "setns", { Eb }, 0 }, 2360 { "setp", { Eb }, 0 }, 2361 { "setnp", { Eb }, 0 }, 2362 { "setl", { Eb }, 0 }, 2363 { "setge", { Eb }, 0 }, 2364 { "setle", { Eb }, 0 }, 2365 { "setg", { Eb }, 0 }, 2366 /* a0 */ 2367 { "pushP", { fs }, 0 }, 2368 { "popP", { fs }, 0 }, 2369 { "cpuid", { XX }, 0 }, 2370 { "btS", { Ev, Gv }, 0 }, 2371 { "shldS", { Ev, Gv, Ib }, 0 }, 2372 { "shldS", { Ev, Gv, CL }, 0 }, 2373 { REG_TABLE (REG_0FA6) }, 2374 { REG_TABLE (REG_0FA7) }, 2375 /* a8 */ 2376 { "pushP", { gs }, 0 }, 2377 { "popP", { gs }, 0 }, 2378 { "rsm", { XX }, 0 }, 2379 { "btsS", { Evh1, Gv }, 0 }, 2380 { "shrdS", { Ev, Gv, Ib }, 0 }, 2381 { "shrdS", { Ev, Gv, CL }, 0 }, 2382 { REG_TABLE (REG_0FAE) }, 2383 { "imulS", { Gv, Ev }, 0 }, 2384 /* b0 */ 2385 { "cmpxchgB", { Ebh1, Gb }, 0 }, 2386 { "cmpxchgS", { Evh1, Gv }, 0 }, 2387 { "lssS", { Gv, Mp }, 0 }, 2388 { "btrS", { Evh1, Gv }, 0 }, 2389 { "lfsS", { Gv, Mp }, 0 }, 2390 { "lgsS", { Gv, Mp }, 0 }, 2391 { "movz{bR|x}", { Gv, Eb }, 0 }, 2392 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ 2393 /* b8 */ 2394 { PREFIX_TABLE (PREFIX_0FB8) }, 2395 { "ud1S", { Gv, Ev }, 0 }, 2396 { REG_TABLE (REG_0FBA) }, 2397 { "btcS", { Evh1, Gv }, 0 }, 2398 { PREFIX_TABLE (PREFIX_0FBC) }, 2399 { PREFIX_TABLE (PREFIX_0FBD) }, 2400 { "movs{bR|x}", { Gv, Eb }, 0 }, 2401 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ 2402 /* c0 */ 2403 { "xaddB", { Ebh1, Gb }, 0 }, 2404 { "xaddS", { Evh1, Gv }, 0 }, 2405 { PREFIX_TABLE (PREFIX_0FC2) }, 2406 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE }, 2407 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE }, 2408 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE }, 2409 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, 2410 { REG_TABLE (REG_0FC7) }, 2411 /* c8 */ 2412 { "bswap", { RMeAX }, 0 }, 2413 { "bswap", { RMeCX }, 0 }, 2414 { "bswap", { RMeDX }, 0 }, 2415 { "bswap", { RMeBX }, 0 }, 2416 { "bswap", { RMeSP }, 0 }, 2417 { "bswap", { RMeBP }, 0 }, 2418 { "bswap", { RMeSI }, 0 }, 2419 { "bswap", { RMeDI }, 0 }, 2420 /* d0 */ 2421 { PREFIX_TABLE (PREFIX_0FD0) }, 2422 { "psrlw", { MX, EM }, PREFIX_OPCODE }, 2423 { "psrld", { MX, EM }, PREFIX_OPCODE }, 2424 { "psrlq", { MX, EM }, PREFIX_OPCODE }, 2425 { "paddq", { MX, EM }, PREFIX_OPCODE }, 2426 { "pmullw", { MX, EM }, PREFIX_OPCODE }, 2427 { PREFIX_TABLE (PREFIX_0FD6) }, 2428 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE }, 2429 /* d8 */ 2430 { "psubusb", { MX, EM }, PREFIX_OPCODE }, 2431 { "psubusw", { MX, EM }, PREFIX_OPCODE }, 2432 { "pminub", { MX, EM }, PREFIX_OPCODE }, 2433 { "pand", { MX, EM }, PREFIX_OPCODE }, 2434 { "paddusb", { MX, EM }, PREFIX_OPCODE }, 2435 { "paddusw", { MX, EM }, PREFIX_OPCODE }, 2436 { "pmaxub", { MX, EM }, PREFIX_OPCODE }, 2437 { "pandn", { MX, EM }, PREFIX_OPCODE }, 2438 /* e0 */ 2439 { "pavgb", { MX, EM }, PREFIX_OPCODE }, 2440 { "psraw", { MX, EM }, PREFIX_OPCODE }, 2441 { "psrad", { MX, EM }, PREFIX_OPCODE }, 2442 { "pavgw", { MX, EM }, PREFIX_OPCODE }, 2443 { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, 2444 { "pmulhw", { MX, EM }, PREFIX_OPCODE }, 2445 { PREFIX_TABLE (PREFIX_0FE6) }, 2446 { PREFIX_TABLE (PREFIX_0FE7) }, 2447 /* e8 */ 2448 { "psubsb", { MX, EM }, PREFIX_OPCODE }, 2449 { "psubsw", { MX, EM }, PREFIX_OPCODE }, 2450 { "pminsw", { MX, EM }, PREFIX_OPCODE }, 2451 { "por", { MX, EM }, PREFIX_OPCODE }, 2452 { "paddsb", { MX, EM }, PREFIX_OPCODE }, 2453 { "paddsw", { MX, EM }, PREFIX_OPCODE }, 2454 { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, 2455 { "pxor", { MX, EM }, PREFIX_OPCODE }, 2456 /* f0 */ 2457 { PREFIX_TABLE (PREFIX_0FF0) }, 2458 { "psllw", { MX, EM }, PREFIX_OPCODE }, 2459 { "pslld", { MX, EM }, PREFIX_OPCODE }, 2460 { "psllq", { MX, EM }, PREFIX_OPCODE }, 2461 { "pmuludq", { MX, EM }, PREFIX_OPCODE }, 2462 { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, 2463 { "psadbw", { MX, EM }, PREFIX_OPCODE }, 2464 { PREFIX_TABLE (PREFIX_0FF7) }, 2465 /* f8 */ 2466 { "psubb", { MX, EM }, PREFIX_OPCODE }, 2467 { "psubw", { MX, EM }, PREFIX_OPCODE }, 2468 { "psubd", { MX, EM }, PREFIX_OPCODE }, 2469 { "psubq", { MX, EM }, PREFIX_OPCODE }, 2470 { "paddb", { MX, EM }, PREFIX_OPCODE }, 2471 { "paddw", { MX, EM }, PREFIX_OPCODE }, 2472 { "paddd", { MX, EM }, PREFIX_OPCODE }, 2473 { "ud0S", { Gv, Ev }, 0 }, 2474 }; 2475 2476 static const bool onebyte_has_modrm[256] = { 2477 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2478 /* ------------------------------- */ 2479 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 2480 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 2481 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 2482 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 2483 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 2484 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 2485 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 2486 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 2487 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 2488 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 2489 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 2490 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 2491 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 2492 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 2493 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 2494 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 2495 /* ------------------------------- */ 2496 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2497 }; 2498 2499 static const bool twobyte_has_modrm[256] = { 2500 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2501 /* ------------------------------- */ 2502 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 2503 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 2504 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 2505 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 2506 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 2507 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 2508 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 2509 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 2510 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 2511 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 2512 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 2513 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ 2514 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 2515 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 2516 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 2517 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ 2518 /* ------------------------------- */ 2519 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2520 }; 2521 2522 2523 struct op 2524 { 2525 const char *name; 2526 unsigned int len; 2527 }; 2528 2529 /* If we are accessing mod/rm/reg without need_modrm set, then the 2530 values are stale. Hitting this abort likely indicates that you 2531 need to update onebyte_has_modrm or twobyte_has_modrm. */ 2532 #define MODRM_CHECK if (!ins->need_modrm) abort () 2533 2534 static const char intel_index16[][6] = { 2535 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 2536 }; 2537 2538 static const char att_names64[][8] = { 2539 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 2540 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 2541 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", 2542 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", 2543 }; 2544 static const char att_names32[][8] = { 2545 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 2546 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d", 2547 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d", 2548 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d", 2549 }; 2550 static const char att_names16[][8] = { 2551 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 2552 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w", 2553 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w", 2554 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w", 2555 }; 2556 static const char att_names8[][8] = { 2557 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 2558 }; 2559 static const char att_names8rex[][8] = { 2560 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 2561 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b", 2562 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b", 2563 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b", 2564 }; 2565 static const char att_names_seg[][4] = { 2566 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 2567 }; 2568 static const char att_index64[] = "%riz"; 2569 static const char att_index32[] = "%eiz"; 2570 static const char att_index16[][8] = { 2571 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 2572 }; 2573 2574 static const char att_names_mm[][8] = { 2575 "%mm0", "%mm1", "%mm2", "%mm3", 2576 "%mm4", "%mm5", "%mm6", "%mm7" 2577 }; 2578 2579 static const char att_names_bnd[][8] = { 2580 "%bnd0", "%bnd1", "%bnd2", "%bnd3" 2581 }; 2582 2583 static const char att_names_xmm[][8] = { 2584 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 2585 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 2586 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 2587 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 2588 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 2589 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 2590 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 2591 "%xmm28", "%xmm29", "%xmm30", "%xmm31" 2592 }; 2593 2594 static const char att_names_ymm[][8] = { 2595 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 2596 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 2597 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 2598 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 2599 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 2600 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 2601 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 2602 "%ymm28", "%ymm29", "%ymm30", "%ymm31" 2603 }; 2604 2605 static const char att_names_zmm[][8] = { 2606 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 2607 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 2608 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 2609 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 2610 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 2611 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 2612 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 2613 "%zmm28", "%zmm29", "%zmm30", "%zmm31" 2614 }; 2615 2616 static const char att_names_tmm[][8] = { 2617 "%tmm0", "%tmm1", "%tmm2", "%tmm3", 2618 "%tmm4", "%tmm5", "%tmm6", "%tmm7" 2619 }; 2620 2621 static const char att_names_mask[][8] = { 2622 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 2623 }; 2624 2625 static const char *const names_rounding[] = 2626 { 2627 "{rn-", 2628 "{rd-", 2629 "{ru-", 2630 "{rz-" 2631 }; 2632 2633 static const struct dis386 reg_table[][8] = { 2634 /* REG_80 */ 2635 { 2636 { "addA", { Ebh1, Ib }, 0 }, 2637 { "orA", { Ebh1, Ib }, 0 }, 2638 { "adcA", { Ebh1, Ib }, 0 }, 2639 { "sbbA", { Ebh1, Ib }, 0 }, 2640 { "andA", { Ebh1, Ib }, 0 }, 2641 { "subA", { Ebh1, Ib }, 0 }, 2642 { "xorA", { Ebh1, Ib }, 0 }, 2643 { "cmpA", { Eb, Ib }, 0 }, 2644 }, 2645 /* REG_81 */ 2646 { 2647 { "addQ", { Evh1, Iv }, 0 }, 2648 { "orQ", { Evh1, Iv }, 0 }, 2649 { "adcQ", { Evh1, Iv }, 0 }, 2650 { "sbbQ", { Evh1, Iv }, 0 }, 2651 { "andQ", { Evh1, Iv }, 0 }, 2652 { "subQ", { Evh1, Iv }, 0 }, 2653 { "xorQ", { Evh1, Iv }, 0 }, 2654 { "cmpQ", { Ev, Iv }, 0 }, 2655 }, 2656 /* REG_83 */ 2657 { 2658 { "addQ", { Evh1, sIb }, 0 }, 2659 { "orQ", { Evh1, sIb }, 0 }, 2660 { "adcQ", { Evh1, sIb }, 0 }, 2661 { "sbbQ", { Evh1, sIb }, 0 }, 2662 { "andQ", { Evh1, sIb }, 0 }, 2663 { "subQ", { Evh1, sIb }, 0 }, 2664 { "xorQ", { Evh1, sIb }, 0 }, 2665 { "cmpQ", { Ev, sIb }, 0 }, 2666 }, 2667 /* REG_8F */ 2668 { 2669 { "pop{P|}", { stackEv }, 0 }, 2670 { XOP_8F_TABLE () }, 2671 { Bad_Opcode }, 2672 { Bad_Opcode }, 2673 { Bad_Opcode }, 2674 { XOP_8F_TABLE () }, 2675 }, 2676 /* REG_C0 */ 2677 { 2678 { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX }, 2679 { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX }, 2680 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX }, 2681 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX }, 2682 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, 2683 { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX }, 2684 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, 2685 { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX }, 2686 }, 2687 /* REG_C1 */ 2688 { 2689 { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2690 { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2691 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2692 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2693 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2694 { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2695 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2696 { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2697 }, 2698 /* REG_C6 */ 2699 { 2700 { "movA", { Ebh3, Ib }, 0 }, 2701 { Bad_Opcode }, 2702 { Bad_Opcode }, 2703 { Bad_Opcode }, 2704 { Bad_Opcode }, 2705 { Bad_Opcode }, 2706 { Bad_Opcode }, 2707 { RM_TABLE (RM_C6_REG_7) }, 2708 }, 2709 /* REG_C7 */ 2710 { 2711 { "movQ", { Evh3, Iv }, 0 }, 2712 { Bad_Opcode }, 2713 { Bad_Opcode }, 2714 { Bad_Opcode }, 2715 { Bad_Opcode }, 2716 { Bad_Opcode }, 2717 { Bad_Opcode }, 2718 { RM_TABLE (RM_C7_REG_7) }, 2719 }, 2720 /* REG_D0 */ 2721 { 2722 { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX }, 2723 { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX }, 2724 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX }, 2725 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX }, 2726 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, 2727 { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX }, 2728 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, 2729 { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX }, 2730 }, 2731 /* REG_D1 */ 2732 { 2733 { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2734 { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2735 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2736 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2737 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2738 { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2739 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2740 { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2741 }, 2742 /* REG_D2 */ 2743 { 2744 { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX }, 2745 { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX }, 2746 { "rclA", { VexGb, Eb, CL }, NO_PREFIX }, 2747 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX }, 2748 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, 2749 { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX }, 2750 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, 2751 { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX }, 2752 }, 2753 /* REG_D3 */ 2754 { 2755 { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2756 { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2757 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2758 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2759 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2760 { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2761 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2762 { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2763 }, 2764 /* REG_F6 */ 2765 { 2766 { "testA", { Eb, Ib }, 0 }, 2767 { "testA", { Eb, Ib }, 0 }, 2768 { "notA", { Ebh1 }, 0 }, 2769 { "negA", { Ebh1 }, 0 }, 2770 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ 2771 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ 2772 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ 2773 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ 2774 }, 2775 /* REG_F7 */ 2776 { 2777 { "testQ", { Ev, Iv }, 0 }, 2778 { "testQ", { Ev, Iv }, 0 }, 2779 { "notQ", { Evh1 }, 0 }, 2780 { "negQ", { Evh1 }, 0 }, 2781 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ 2782 { "imulQ", { Ev }, 0 }, 2783 { "divQ", { Ev }, 0 }, 2784 { "idivQ", { Ev }, 0 }, 2785 }, 2786 /* REG_FE */ 2787 { 2788 { "incA", { Ebh1 }, 0 }, 2789 { "decA", { Ebh1 }, 0 }, 2790 }, 2791 /* REG_FF */ 2792 { 2793 { "incQ", { Evh1 }, 0 }, 2794 { "decQ", { Evh1 }, 0 }, 2795 { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, 2796 { "{l|}call^", { indirEp }, 0 }, 2797 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, 2798 { "{l|}jmp^", { indirEp }, 0 }, 2799 { "push{P|}", { stackEv }, 0 }, 2800 { Bad_Opcode }, 2801 }, 2802 /* REG_0F00 */ 2803 { 2804 { "sldtD", { Sv }, 0 }, 2805 { "strD", { Sv }, 0 }, 2806 { "lldtD", { Sv }, 0 }, 2807 { "ltrD", { Sv }, 0 }, 2808 { "verrD", { Sv }, 0 }, 2809 { "verwD", { Sv }, 0 }, 2810 { X86_64_TABLE (X86_64_0F00_REG_6) }, 2811 { Bad_Opcode }, 2812 }, 2813 /* REG_0F01 */ 2814 { 2815 { MOD_TABLE (MOD_0F01_REG_0) }, 2816 { MOD_TABLE (MOD_0F01_REG_1) }, 2817 { MOD_TABLE (MOD_0F01_REG_2) }, 2818 { MOD_TABLE (MOD_0F01_REG_3) }, 2819 { "smswD", { Sv }, 0 }, 2820 { MOD_TABLE (MOD_0F01_REG_5) }, 2821 { "lmsw", { Ew }, 0 }, 2822 { MOD_TABLE (MOD_0F01_REG_7) }, 2823 }, 2824 /* REG_0F0D */ 2825 { 2826 { "prefetch", { Mb }, 0 }, 2827 { "prefetchw", { Mb }, 0 }, 2828 { "prefetchwt1", { Mb }, 0 }, 2829 { "prefetch", { Mb }, 0 }, 2830 { "prefetch", { Mb }, 0 }, 2831 { "prefetch", { Mb }, 0 }, 2832 { "prefetch", { Mb }, 0 }, 2833 { "prefetch", { Mb }, 0 }, 2834 }, 2835 /* REG_0F18 */ 2836 { 2837 { MOD_TABLE (MOD_0F18_REG_0) }, 2838 { MOD_TABLE (MOD_0F18_REG_1) }, 2839 { MOD_TABLE (MOD_0F18_REG_2) }, 2840 { MOD_TABLE (MOD_0F18_REG_3) }, 2841 { "nopQ", { Ev }, 0 }, 2842 { "nopQ", { Ev }, 0 }, 2843 { MOD_TABLE (MOD_0F18_REG_6) }, 2844 { MOD_TABLE (MOD_0F18_REG_7) }, 2845 }, 2846 /* REG_0F1C_P_0_MOD_0 */ 2847 { 2848 { "cldemote", { Mb }, 0 }, 2849 { "nopQ", { Ev }, 0 }, 2850 { "nopQ", { Ev }, 0 }, 2851 { "nopQ", { Ev }, 0 }, 2852 { "nopQ", { Ev }, 0 }, 2853 { "nopQ", { Ev }, 0 }, 2854 { "nopQ", { Ev }, 0 }, 2855 { "nopQ", { Ev }, 0 }, 2856 }, 2857 /* REG_0F1E_P_1_MOD_3 */ 2858 { 2859 { "nopQ", { Ev }, PREFIX_IGNORED }, 2860 { "rdsspK", { Edq }, 0 }, 2861 { "nopQ", { Ev }, PREFIX_IGNORED }, 2862 { "nopQ", { Ev }, PREFIX_IGNORED }, 2863 { "nopQ", { Ev }, PREFIX_IGNORED }, 2864 { "nopQ", { Ev }, PREFIX_IGNORED }, 2865 { "nopQ", { Ev }, PREFIX_IGNORED }, 2866 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, 2867 }, 2868 /* REG_0F38D8_PREFIX_1 */ 2869 { 2870 { "aesencwide128kl", { M }, 0 }, 2871 { "aesdecwide128kl", { M }, 0 }, 2872 { "aesencwide256kl", { M }, 0 }, 2873 { "aesdecwide256kl", { M }, 0 }, 2874 }, 2875 /* REG_0F3A0F_P_1 */ 2876 { 2877 { RM_TABLE (RM_0F3A0F_P_1_R_0) }, 2878 }, 2879 /* REG_0F71 */ 2880 { 2881 { Bad_Opcode }, 2882 { Bad_Opcode }, 2883 { "psrlw", { Nq, Ib }, PREFIX_OPCODE }, 2884 { Bad_Opcode }, 2885 { "psraw", { Nq, Ib }, PREFIX_OPCODE }, 2886 { Bad_Opcode }, 2887 { "psllw", { Nq, Ib }, PREFIX_OPCODE }, 2888 }, 2889 /* REG_0F72 */ 2890 { 2891 { Bad_Opcode }, 2892 { Bad_Opcode }, 2893 { "psrld", { Nq, Ib }, PREFIX_OPCODE }, 2894 { Bad_Opcode }, 2895 { "psrad", { Nq, Ib }, PREFIX_OPCODE }, 2896 { Bad_Opcode }, 2897 { "pslld", { Nq, Ib }, PREFIX_OPCODE }, 2898 }, 2899 /* REG_0F73 */ 2900 { 2901 { Bad_Opcode }, 2902 { Bad_Opcode }, 2903 { "psrlq", { Nq, Ib }, PREFIX_OPCODE }, 2904 { "psrldq", { Ux, Ib }, PREFIX_DATA }, 2905 { Bad_Opcode }, 2906 { Bad_Opcode }, 2907 { "psllq", { Nq, Ib }, PREFIX_OPCODE }, 2908 { "pslldq", { Ux, Ib }, PREFIX_DATA }, 2909 }, 2910 /* REG_0FA6 */ 2911 { 2912 { PREFIX_TABLE (PREFIX_0FA6_REG_0) }, 2913 { "xsha1", { { OP_0f07, 0 } }, 0 }, 2914 { "xsha256", { { OP_0f07, 0 } }, 0 }, 2915 { Bad_Opcode }, 2916 { Bad_Opcode }, 2917 { PREFIX_TABLE (PREFIX_0FA6_REG_5) }, 2918 }, 2919 /* REG_0FA7 */ 2920 { 2921 { "xstore-rng", { { OP_0f07, 0 } }, 0 }, 2922 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, 2923 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, 2924 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, 2925 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, 2926 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, 2927 { PREFIX_TABLE (PREFIX_0FA7_REG_6) }, 2928 }, 2929 /* REG_0FAE */ 2930 { 2931 { MOD_TABLE (MOD_0FAE_REG_0) }, 2932 { MOD_TABLE (MOD_0FAE_REG_1) }, 2933 { MOD_TABLE (MOD_0FAE_REG_2) }, 2934 { MOD_TABLE (MOD_0FAE_REG_3) }, 2935 { MOD_TABLE (MOD_0FAE_REG_4) }, 2936 { MOD_TABLE (MOD_0FAE_REG_5) }, 2937 { MOD_TABLE (MOD_0FAE_REG_6) }, 2938 { MOD_TABLE (MOD_0FAE_REG_7) }, 2939 }, 2940 /* REG_0FBA */ 2941 { 2942 { Bad_Opcode }, 2943 { Bad_Opcode }, 2944 { Bad_Opcode }, 2945 { Bad_Opcode }, 2946 { "btQ", { Ev, Ib }, 0 }, 2947 { "btsQ", { Evh1, Ib }, 0 }, 2948 { "btrQ", { Evh1, Ib }, 0 }, 2949 { "btcQ", { Evh1, Ib }, 0 }, 2950 }, 2951 /* REG_0FC7 */ 2952 { 2953 { Bad_Opcode }, 2954 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, 2955 { Bad_Opcode }, 2956 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 2957 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 2958 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 2959 { MOD_TABLE (MOD_0FC7_REG_6) }, 2960 { MOD_TABLE (MOD_0FC7_REG_7) }, 2961 }, 2962 /* REG_VEX_0F71 */ 2963 { 2964 { Bad_Opcode }, 2965 { Bad_Opcode }, 2966 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA }, 2967 { Bad_Opcode }, 2968 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA }, 2969 { Bad_Opcode }, 2970 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA }, 2971 }, 2972 /* REG_VEX_0F72 */ 2973 { 2974 { Bad_Opcode }, 2975 { Bad_Opcode }, 2976 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA }, 2977 { Bad_Opcode }, 2978 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA }, 2979 { Bad_Opcode }, 2980 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA }, 2981 }, 2982 /* REG_VEX_0F73 */ 2983 { 2984 { Bad_Opcode }, 2985 { Bad_Opcode }, 2986 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA }, 2987 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA }, 2988 { Bad_Opcode }, 2989 { Bad_Opcode }, 2990 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA }, 2991 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA }, 2992 }, 2993 /* REG_VEX_0FAE */ 2994 { 2995 { Bad_Opcode }, 2996 { Bad_Opcode }, 2997 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) }, 2998 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) }, 2999 }, 3000 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */ 3001 { 3002 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) }, 3003 }, 3004 /* REG_VEX_0F38F3_L_0_P_0 */ 3005 { 3006 { Bad_Opcode }, 3007 { "%NFblsrS", { VexGdq, Edq }, 0 }, 3008 { "%NFblsmskS", { VexGdq, Edq }, 0 }, 3009 { "%NFblsiS", { VexGdq, Edq }, 0 }, 3010 }, 3011 /* REG_VEX_MAP7_F6_L_0_W_0 */ 3012 { 3013 { X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) }, 3014 }, 3015 /* REG_VEX_MAP7_F8_L_0_W_0 */ 3016 { 3017 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, 3018 }, 3019 /* REG_XOP_09_01_L_0 */ 3020 { 3021 { Bad_Opcode }, 3022 { "blcfill", { VexGdq, Edq }, 0 }, 3023 { "blsfill", { VexGdq, Edq }, 0 }, 3024 { "blcs", { VexGdq, Edq }, 0 }, 3025 { "tzmsk", { VexGdq, Edq }, 0 }, 3026 { "blcic", { VexGdq, Edq }, 0 }, 3027 { "blsic", { VexGdq, Edq }, 0 }, 3028 { "t1mskc", { VexGdq, Edq }, 0 }, 3029 }, 3030 /* REG_XOP_09_02_L_0 */ 3031 { 3032 { Bad_Opcode }, 3033 { "blcmsk", { VexGdq, Edq }, 0 }, 3034 { Bad_Opcode }, 3035 { Bad_Opcode }, 3036 { Bad_Opcode }, 3037 { Bad_Opcode }, 3038 { "blci", { VexGdq, Edq }, 0 }, 3039 }, 3040 /* REG_XOP_09_12_L_0 */ 3041 { 3042 { "llwpcb", { Rdq }, 0 }, 3043 { "slwpcb", { Rdq }, 0 }, 3044 }, 3045 /* REG_XOP_0A_12_L_0 */ 3046 { 3047 { "lwpins", { VexGdq, Ed, Id }, 0 }, 3048 { "lwpval", { VexGdq, Ed, Id }, 0 }, 3049 }, 3050 3051 #include "i386-dis-evex-reg.h" 3052 }; 3053 3054 static const struct dis386 prefix_table[][4] = { 3055 /* PREFIX_90 */ 3056 { 3057 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, 3058 { "pause", { XX }, 0 }, 3059 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, 3060 { NULL, { { NULL, 0 } }, PREFIX_IGNORED } 3061 }, 3062 3063 /* PREFIX_0F00_REG_6_X86_64 */ 3064 { 3065 { Bad_Opcode }, 3066 { Bad_Opcode }, 3067 { Bad_Opcode }, 3068 { "lkgsD", { Sv }, 0 }, 3069 }, 3070 3071 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ 3072 { 3073 { "wrmsrns", { Skip_MODRM }, 0 }, 3074 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, 3075 { Bad_Opcode }, 3076 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, 3077 }, 3078 3079 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */ 3080 { 3081 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) }, 3082 }, 3083 3084 /* PREFIX_0F01_REG_1_RM_2 */ 3085 { 3086 { "clac", { Skip_MODRM }, 0 }, 3087 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) }, 3088 { Bad_Opcode }, 3089 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)}, 3090 }, 3091 3092 /* PREFIX_0F01_REG_1_RM_4 */ 3093 { 3094 { Bad_Opcode }, 3095 { Bad_Opcode }, 3096 { "tdcall", { Skip_MODRM }, 0 }, 3097 { Bad_Opcode }, 3098 }, 3099 3100 /* PREFIX_0F01_REG_1_RM_5 */ 3101 { 3102 { Bad_Opcode }, 3103 { Bad_Opcode }, 3104 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, 3105 { Bad_Opcode }, 3106 }, 3107 3108 /* PREFIX_0F01_REG_1_RM_6 */ 3109 { 3110 { Bad_Opcode }, 3111 { Bad_Opcode }, 3112 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, 3113 { Bad_Opcode }, 3114 }, 3115 3116 /* PREFIX_0F01_REG_1_RM_7 */ 3117 { 3118 { "encls", { Skip_MODRM }, 0 }, 3119 { Bad_Opcode }, 3120 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, 3121 { Bad_Opcode }, 3122 }, 3123 3124 /* PREFIX_0F01_REG_3_RM_1 */ 3125 { 3126 { "vmmcall", { Skip_MODRM }, 0 }, 3127 { "vmgexit", { Skip_MODRM }, 0 }, 3128 { Bad_Opcode }, 3129 { "vmgexit", { Skip_MODRM }, 0 }, 3130 }, 3131 3132 /* PREFIX_0F01_REG_5_MOD_0 */ 3133 { 3134 { Bad_Opcode }, 3135 { "rstorssp", { Mq }, PREFIX_OPCODE }, 3136 }, 3137 3138 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ 3139 { 3140 { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, 3141 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, 3142 { Bad_Opcode }, 3143 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, 3144 }, 3145 3146 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ 3147 { 3148 { Bad_Opcode }, 3149 { Bad_Opcode }, 3150 { Bad_Opcode }, 3151 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, 3152 }, 3153 3154 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ 3155 { 3156 { Bad_Opcode }, 3157 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, 3158 }, 3159 3160 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */ 3161 { 3162 { Bad_Opcode }, 3163 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) }, 3164 }, 3165 3166 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */ 3167 { 3168 { Bad_Opcode }, 3169 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) }, 3170 }, 3171 3172 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */ 3173 { 3174 { "rdpkru", { Skip_MODRM }, 0 }, 3175 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) }, 3176 }, 3177 3178 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */ 3179 { 3180 { "wrpkru", { Skip_MODRM }, 0 }, 3181 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) }, 3182 }, 3183 3184 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ 3185 { 3186 { "monitorx", { { OP_Monitor, 0 } }, 0 }, 3187 { "mcommit", { Skip_MODRM }, 0 }, 3188 }, 3189 3190 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */ 3191 { 3192 { "rdpru", { Skip_MODRM }, 0 }, 3193 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) }, 3194 }, 3195 3196 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ 3197 { 3198 { "invlpgb", { Skip_MODRM }, 0 }, 3199 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) }, 3200 { Bad_Opcode }, 3201 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) }, 3202 }, 3203 3204 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ 3205 { 3206 { "tlbsync", { Skip_MODRM }, 0 }, 3207 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) }, 3208 { Bad_Opcode }, 3209 { "pvalidate", { Skip_MODRM }, 0 }, 3210 }, 3211 3212 /* PREFIX_0F09 */ 3213 { 3214 { "wbinvd", { XX }, 0 }, 3215 { "wbnoinvd", { XX }, 0 }, 3216 }, 3217 3218 /* PREFIX_0F10 */ 3219 { 3220 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, 3221 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 }, 3222 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, 3223 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 }, 3224 }, 3225 3226 /* PREFIX_0F11 */ 3227 { 3228 { "%XEVmovupX", { EXxS, XM }, 0 }, 3229 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 }, 3230 { "%XEVmovupX", { EXxS, XM }, 0 }, 3231 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 }, 3232 }, 3233 3234 /* PREFIX_0F12 */ 3235 { 3236 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 3237 { "movsldup", { XM, EXx }, 0 }, 3238 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, 3239 { "movddup", { XM, EXq }, 0 }, 3240 }, 3241 3242 /* PREFIX_0F16 */ 3243 { 3244 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 3245 { "movshdup", { XM, EXx }, 0 }, 3246 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, 3247 }, 3248 3249 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */ 3250 { 3251 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 }, 3252 { "nopQ", { Ev }, 0 }, 3253 { "nopQ", { Ev }, 0 }, 3254 { "nopQ", { Ev }, 0 }, 3255 }, 3256 3257 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */ 3258 { 3259 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 }, 3260 { "nopQ", { Ev }, 0 }, 3261 { "nopQ", { Ev }, 0 }, 3262 { "nopQ", { Ev }, 0 }, 3263 }, 3264 3265 /* PREFIX_0F1A */ 3266 { 3267 { MOD_TABLE (MOD_0F1A_PREFIX_0) }, 3268 { "bndcl", { Gbnd, Ev_bnd }, 0 }, 3269 { "bndmov", { Gbnd, Ebnd }, 0 }, 3270 { "bndcu", { Gbnd, Ev_bnd }, 0 }, 3271 }, 3272 3273 /* PREFIX_0F1B */ 3274 { 3275 { MOD_TABLE (MOD_0F1B_PREFIX_0) }, 3276 { MOD_TABLE (MOD_0F1B_PREFIX_1) }, 3277 { "bndmov", { EbndS, Gbnd }, 0 }, 3278 { "bndcn", { Gbnd, Ev_bnd }, 0 }, 3279 }, 3280 3281 /* PREFIX_0F1C */ 3282 { 3283 { MOD_TABLE (MOD_0F1C_PREFIX_0) }, 3284 { "nopQ", { Ev }, PREFIX_IGNORED }, 3285 { "nopQ", { Ev }, 0 }, 3286 { "nopQ", { Ev }, PREFIX_IGNORED }, 3287 }, 3288 3289 /* PREFIX_0F1E */ 3290 { 3291 { "nopQ", { Ev }, 0 }, 3292 { MOD_TABLE (MOD_0F1E_PREFIX_1) }, 3293 { "nopQ", { Ev }, 0 }, 3294 { NULL, { XX }, PREFIX_IGNORED }, 3295 }, 3296 3297 /* PREFIX_0F2A */ 3298 { 3299 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, 3300 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, 3301 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, 3302 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, 3303 }, 3304 3305 /* PREFIX_0F2B */ 3306 { 3307 { "movntps", { Mx, XM }, 0 }, 3308 { "movntss", { Md, XM }, 0 }, 3309 { "movntpd", { Mx, XM }, 0 }, 3310 { "movntsd", { Mq, XM }, 0 }, 3311 }, 3312 3313 /* PREFIX_0F2C */ 3314 { 3315 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3316 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, 3317 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3318 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, 3319 }, 3320 3321 /* PREFIX_0F2D */ 3322 { 3323 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3324 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, 3325 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3326 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, 3327 }, 3328 3329 /* PREFIX_0F2E */ 3330 { 3331 { "VucomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, 3332 { Bad_Opcode }, 3333 { "VucomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, 3334 }, 3335 3336 /* PREFIX_0F2F */ 3337 { 3338 { "VcomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, 3339 { Bad_Opcode }, 3340 { "VcomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, 3341 }, 3342 3343 /* PREFIX_0F51 */ 3344 { 3345 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, 3346 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3347 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, 3348 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3349 }, 3350 3351 /* PREFIX_0F52 */ 3352 { 3353 { "Vrsqrtps", { XM, EXx }, 0 }, 3354 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 }, 3355 }, 3356 3357 /* PREFIX_0F53 */ 3358 { 3359 { "Vrcpps", { XM, EXx }, 0 }, 3360 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 }, 3361 }, 3362 3363 /* PREFIX_0F58 */ 3364 { 3365 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3366 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3367 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3368 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3369 }, 3370 3371 /* PREFIX_0F59 */ 3372 { 3373 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3374 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3375 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3376 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3377 }, 3378 3379 /* PREFIX_0F5A */ 3380 { 3381 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, 3382 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3383 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, 3384 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3385 }, 3386 3387 /* PREFIX_0F5B */ 3388 { 3389 { "Vcvtdq2ps", { XM, EXx }, 0 }, 3390 { "Vcvttps2dq", { XM, EXx }, 0 }, 3391 { "Vcvtps2dq", { XM, EXx }, 0 }, 3392 }, 3393 3394 /* PREFIX_0F5C */ 3395 { 3396 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3397 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3398 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3399 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3400 }, 3401 3402 /* PREFIX_0F5D */ 3403 { 3404 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3405 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3406 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3407 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, 3408 }, 3409 3410 /* PREFIX_0F5E */ 3411 { 3412 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3413 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3414 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3415 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3416 }, 3417 3418 /* PREFIX_0F5F */ 3419 { 3420 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3421 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3422 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3423 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, 3424 }, 3425 3426 /* PREFIX_0F60 */ 3427 { 3428 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, 3429 { Bad_Opcode }, 3430 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, 3431 }, 3432 3433 /* PREFIX_0F61 */ 3434 { 3435 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, 3436 { Bad_Opcode }, 3437 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, 3438 }, 3439 3440 /* PREFIX_0F62 */ 3441 { 3442 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, 3443 { Bad_Opcode }, 3444 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, 3445 }, 3446 3447 /* PREFIX_0F6F */ 3448 { 3449 { "movq", { MX, EM }, PREFIX_OPCODE }, 3450 { "movdqu", { XM, EXx }, PREFIX_OPCODE }, 3451 { "movdqa", { XM, EXx }, PREFIX_OPCODE }, 3452 }, 3453 3454 /* PREFIX_0F70 */ 3455 { 3456 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, 3457 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3458 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, 3459 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3460 }, 3461 3462 /* PREFIX_0F78 */ 3463 { 3464 {"vmread", { Em, Gm }, 0 }, 3465 { Bad_Opcode }, 3466 {"extrq", { Uxmm, Ib, Ib }, 0 }, 3467 {"insertq", { XM, Uxmm, Ib, Ib }, 0 }, 3468 }, 3469 3470 /* PREFIX_0F79 */ 3471 { 3472 {"vmwrite", { Gm, Em }, 0 }, 3473 { Bad_Opcode }, 3474 {"extrq", { XM, Uxmm }, 0 }, 3475 {"insertq", { XM, Uxmm }, 0 }, 3476 }, 3477 3478 /* PREFIX_0F7C */ 3479 { 3480 { Bad_Opcode }, 3481 { Bad_Opcode }, 3482 { "Vhaddpd", { XM, Vex, EXx }, 0 }, 3483 { "Vhaddps", { XM, Vex, EXx }, 0 }, 3484 }, 3485 3486 /* PREFIX_0F7D */ 3487 { 3488 { Bad_Opcode }, 3489 { Bad_Opcode }, 3490 { "Vhsubpd", { XM, Vex, EXx }, 0 }, 3491 { "Vhsubps", { XM, Vex, EXx }, 0 }, 3492 }, 3493 3494 /* PREFIX_0F7E */ 3495 { 3496 { "movK", { Edq, MX }, PREFIX_OPCODE }, 3497 { "movq", { XM, EXq }, PREFIX_OPCODE }, 3498 { "movK", { Edq, XM }, PREFIX_OPCODE }, 3499 }, 3500 3501 /* PREFIX_0F7F */ 3502 { 3503 { "movq", { EMS, MX }, PREFIX_OPCODE }, 3504 { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, 3505 { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, 3506 }, 3507 3508 /* PREFIX_0FA6_REG_0 */ 3509 { 3510 { Bad_Opcode }, 3511 { "montmul", { { MONTMUL_Fixup, 0 } }, 0}, 3512 { Bad_Opcode }, 3513 { "sm2", { Skip_MODRM }, 0 }, 3514 }, 3515 3516 /* PREFIX_0FA6_REG_5 */ 3517 { 3518 { Bad_Opcode }, 3519 { "sm3", { Skip_MODRM }, 0 }, 3520 }, 3521 3522 /* PREFIX_0FA7_REG_6 */ 3523 { 3524 { Bad_Opcode }, 3525 { "sm4", { Skip_MODRM }, 0 }, 3526 }, 3527 3528 /* PREFIX_0FAE_REG_0_MOD_3 */ 3529 { 3530 { Bad_Opcode }, 3531 { "rdfsbase", { Ev }, 0 }, 3532 }, 3533 3534 /* PREFIX_0FAE_REG_1_MOD_3 */ 3535 { 3536 { Bad_Opcode }, 3537 { "rdgsbase", { Ev }, 0 }, 3538 }, 3539 3540 /* PREFIX_0FAE_REG_2_MOD_3 */ 3541 { 3542 { Bad_Opcode }, 3543 { "wrfsbase", { Ev }, 0 }, 3544 }, 3545 3546 /* PREFIX_0FAE_REG_3_MOD_3 */ 3547 { 3548 { Bad_Opcode }, 3549 { "wrgsbase", { Ev }, 0 }, 3550 }, 3551 3552 /* PREFIX_0FAE_REG_4_MOD_0 */ 3553 { 3554 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 3555 { "ptwrite{%LQ|}", { Edq }, 0 }, 3556 }, 3557 3558 /* PREFIX_0FAE_REG_4_MOD_3 */ 3559 { 3560 { Bad_Opcode }, 3561 { "ptwrite{%LQ|}", { Edq }, 0 }, 3562 }, 3563 3564 /* PREFIX_0FAE_REG_5_MOD_3 */ 3565 { 3566 { "lfence", { Skip_MODRM }, 0 }, 3567 { "incsspK", { Edq }, PREFIX_OPCODE }, 3568 }, 3569 3570 /* PREFIX_0FAE_REG_6_MOD_0 */ 3571 { 3572 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, 3573 { "clrssbsy", { Mq }, PREFIX_OPCODE }, 3574 { "clwb", { Mb }, PREFIX_OPCODE }, 3575 }, 3576 3577 /* PREFIX_0FAE_REG_6_MOD_3 */ 3578 { 3579 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, 3580 { "umonitor", { Eva }, PREFIX_OPCODE }, 3581 { "tpause", { Edq }, PREFIX_OPCODE }, 3582 { "umwait", { Edq }, PREFIX_OPCODE }, 3583 }, 3584 3585 /* PREFIX_0FAE_REG_7_MOD_0 */ 3586 { 3587 { "clflush", { Mb }, 0 }, 3588 { Bad_Opcode }, 3589 { "clflushopt", { Mb }, 0 }, 3590 }, 3591 3592 /* PREFIX_0FB8 */ 3593 { 3594 { Bad_Opcode }, 3595 { "popcntS", { Gv, Ev }, 0 }, 3596 }, 3597 3598 /* PREFIX_0FBC */ 3599 { 3600 { "bsfS", { Gv, Ev }, 0 }, 3601 { "tzcntS", { Gv, Ev }, 0 }, 3602 { "bsfS", { Gv, Ev }, 0 }, 3603 }, 3604 3605 /* PREFIX_0FBD */ 3606 { 3607 { "bsrS", { Gv, Ev }, 0 }, 3608 { "lzcntS", { Gv, Ev }, 0 }, 3609 { "bsrS", { Gv, Ev }, 0 }, 3610 }, 3611 3612 /* PREFIX_0FC2 */ 3613 { 3614 { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, 3615 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 }, 3616 { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, 3617 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 }, 3618 }, 3619 3620 /* PREFIX_0FC7_REG_6_MOD_0 */ 3621 { 3622 { "vmptrld",{ Mq }, 0 }, 3623 { "vmxon", { Mq }, 0 }, 3624 { "vmclear",{ Mq }, 0 }, 3625 }, 3626 3627 /* PREFIX_0FC7_REG_6_MOD_3 */ 3628 { 3629 { "rdrand", { Ev }, 0 }, 3630 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) }, 3631 { "rdrand", { Ev }, 0 } 3632 }, 3633 3634 /* PREFIX_0FC7_REG_7_MOD_3 */ 3635 { 3636 { "rdseed", { Ev }, 0 }, 3637 { "rdpid", { Em }, 0 }, 3638 { "rdseed", { Ev }, 0 }, 3639 }, 3640 3641 /* PREFIX_0FD0 */ 3642 { 3643 { Bad_Opcode }, 3644 { Bad_Opcode }, 3645 { "VaddsubpX", { XM, Vex, EXx }, 0 }, 3646 { "VaddsubpX", { XM, Vex, EXx }, 0 }, 3647 }, 3648 3649 /* PREFIX_0FD6 */ 3650 { 3651 { Bad_Opcode }, 3652 { "movq2dq",{ XM, Nq }, 0 }, 3653 { "movq", { EXqS, XM }, 0 }, 3654 { "movdq2q",{ MX, Ux }, 0 }, 3655 }, 3656 3657 /* PREFIX_0FE6 */ 3658 { 3659 { Bad_Opcode }, 3660 { "Vcvtdq2pd", { XM, EXxmmq }, 0 }, 3661 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 }, 3662 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 }, 3663 }, 3664 3665 /* PREFIX_0FE7 */ 3666 { 3667 { "movntq", { Mq, MX }, 0 }, 3668 { Bad_Opcode }, 3669 { "movntdq", { Mx, XM }, 0 }, 3670 }, 3671 3672 /* PREFIX_0FF0 */ 3673 { 3674 { Bad_Opcode }, 3675 { Bad_Opcode }, 3676 { Bad_Opcode }, 3677 { "Vlddqu", { XM, M }, 0 }, 3678 }, 3679 3680 /* PREFIX_0FF7 */ 3681 { 3682 { "maskmovq", { MX, Nq }, PREFIX_OPCODE }, 3683 { Bad_Opcode }, 3684 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE }, 3685 }, 3686 3687 /* PREFIX_0F38D8 */ 3688 { 3689 { Bad_Opcode }, 3690 { REG_TABLE (REG_0F38D8_PREFIX_1) }, 3691 }, 3692 3693 /* PREFIX_0F38DC */ 3694 { 3695 { Bad_Opcode }, 3696 { MOD_TABLE (MOD_0F38DC_PREFIX_1) }, 3697 { "aesenc", { XM, EXx }, 0 }, 3698 }, 3699 3700 /* PREFIX_0F38DD */ 3701 { 3702 { Bad_Opcode }, 3703 { "aesdec128kl", { XM, M }, 0 }, 3704 { "aesenclast", { XM, EXx }, 0 }, 3705 }, 3706 3707 /* PREFIX_0F38DE */ 3708 { 3709 { Bad_Opcode }, 3710 { "aesenc256kl", { XM, M }, 0 }, 3711 { "aesdec", { XM, EXx }, 0 }, 3712 }, 3713 3714 /* PREFIX_0F38DF */ 3715 { 3716 { Bad_Opcode }, 3717 { "aesdec256kl", { XM, M }, 0 }, 3718 { "aesdeclast", { XM, EXx }, 0 }, 3719 }, 3720 3721 /* PREFIX_0F38F0 */ 3722 { 3723 { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, 3724 { Bad_Opcode }, 3725 { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, 3726 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, 3727 }, 3728 3729 /* PREFIX_0F38F1 */ 3730 { 3731 { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, 3732 { Bad_Opcode }, 3733 { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, 3734 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, 3735 }, 3736 3737 /* PREFIX_0F38F6 */ 3738 { 3739 { "wrssK", { M, Gdq }, 0 }, 3740 { "adoxL", { VexGdq, Gdq, Edq }, 0 }, 3741 { "adcxL", { VexGdq, Gdq, Edq }, 0 }, 3742 { Bad_Opcode }, 3743 }, 3744 3745 /* PREFIX_0F38F8_M_0 */ 3746 { 3747 { Bad_Opcode }, 3748 { "enqcmds", { Gva, M }, 0 }, 3749 { "movdir64b", { Gva, M }, 0 }, 3750 { "enqcmd", { Gva, M }, 0 }, 3751 }, 3752 3753 /* PREFIX_0F38F8_M_1_X86_64 */ 3754 { 3755 { Bad_Opcode }, 3756 { "uwrmsr", { Gq, Rq }, 0 }, 3757 { Bad_Opcode }, 3758 { "urdmsr", { Rq, Gq }, 0 }, 3759 }, 3760 3761 /* PREFIX_0F38FA */ 3762 { 3763 { Bad_Opcode }, 3764 { "encodekey128", { Gd, Rd }, 0 }, 3765 }, 3766 3767 /* PREFIX_0F38FB */ 3768 { 3769 { Bad_Opcode }, 3770 { "encodekey256", { Gd, Rd }, 0 }, 3771 }, 3772 3773 /* PREFIX_0F38FC */ 3774 { 3775 { "aadd", { Mdq, Gdq }, 0 }, 3776 { "axor", { Mdq, Gdq }, 0 }, 3777 { "aand", { Mdq, Gdq }, 0 }, 3778 { "aor", { Mdq, Gdq }, 0 }, 3779 }, 3780 3781 /* PREFIX_0F3A0F */ 3782 { 3783 { Bad_Opcode }, 3784 { REG_TABLE (REG_0F3A0F_P_1) }, 3785 }, 3786 3787 /* PREFIX_VEX_0F12 */ 3788 { 3789 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) }, 3790 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 }, 3791 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, 3792 { "%XEvmov%XDdup", { XM, EXymmq }, 0 }, 3793 }, 3794 3795 /* PREFIX_VEX_0F16 */ 3796 { 3797 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) }, 3798 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 }, 3799 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, 3800 }, 3801 3802 /* PREFIX_VEX_0F2A */ 3803 { 3804 { Bad_Opcode }, 3805 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 }, 3806 { Bad_Opcode }, 3807 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, 3808 }, 3809 3810 /* PREFIX_VEX_0F2C */ 3811 { 3812 { Bad_Opcode }, 3813 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 }, 3814 { Bad_Opcode }, 3815 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 }, 3816 }, 3817 3818 /* PREFIX_VEX_0F2D */ 3819 { 3820 { Bad_Opcode }, 3821 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 }, 3822 { Bad_Opcode }, 3823 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 }, 3824 }, 3825 3826 /* PREFIX_VEX_0F41_L_1_W_0 */ 3827 { 3828 { "kandw", { MaskG, MaskVex, MaskR }, 0 }, 3829 { Bad_Opcode }, 3830 { "kandb", { MaskG, MaskVex, MaskR }, 0 }, 3831 }, 3832 3833 /* PREFIX_VEX_0F41_L_1_W_1 */ 3834 { 3835 { "kandq", { MaskG, MaskVex, MaskR }, 0 }, 3836 { Bad_Opcode }, 3837 { "kandd", { MaskG, MaskVex, MaskR }, 0 }, 3838 }, 3839 3840 /* PREFIX_VEX_0F42_L_1_W_0 */ 3841 { 3842 { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, 3843 { Bad_Opcode }, 3844 { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, 3845 }, 3846 3847 /* PREFIX_VEX_0F42_L_1_W_1 */ 3848 { 3849 { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, 3850 { Bad_Opcode }, 3851 { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, 3852 }, 3853 3854 /* PREFIX_VEX_0F44_L_0_W_0 */ 3855 { 3856 { "knotw", { MaskG, MaskR }, 0 }, 3857 { Bad_Opcode }, 3858 { "knotb", { MaskG, MaskR }, 0 }, 3859 }, 3860 3861 /* PREFIX_VEX_0F44_L_0_W_1 */ 3862 { 3863 { "knotq", { MaskG, MaskR }, 0 }, 3864 { Bad_Opcode }, 3865 { "knotd", { MaskG, MaskR }, 0 }, 3866 }, 3867 3868 /* PREFIX_VEX_0F45_L_1_W_0 */ 3869 { 3870 { "korw", { MaskG, MaskVex, MaskR }, 0 }, 3871 { Bad_Opcode }, 3872 { "korb", { MaskG, MaskVex, MaskR }, 0 }, 3873 }, 3874 3875 /* PREFIX_VEX_0F45_L_1_W_1 */ 3876 { 3877 { "korq", { MaskG, MaskVex, MaskR }, 0 }, 3878 { Bad_Opcode }, 3879 { "kord", { MaskG, MaskVex, MaskR }, 0 }, 3880 }, 3881 3882 /* PREFIX_VEX_0F46_L_1_W_0 */ 3883 { 3884 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, 3885 { Bad_Opcode }, 3886 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, 3887 }, 3888 3889 /* PREFIX_VEX_0F46_L_1_W_1 */ 3890 { 3891 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, 3892 { Bad_Opcode }, 3893 { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, 3894 }, 3895 3896 /* PREFIX_VEX_0F47_L_1_W_0 */ 3897 { 3898 { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, 3899 { Bad_Opcode }, 3900 { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, 3901 }, 3902 3903 /* PREFIX_VEX_0F47_L_1_W_1 */ 3904 { 3905 { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, 3906 { Bad_Opcode }, 3907 { "kxord", { MaskG, MaskVex, MaskR }, 0 }, 3908 }, 3909 3910 /* PREFIX_VEX_0F4A_L_1_W_0 */ 3911 { 3912 { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, 3913 { Bad_Opcode }, 3914 { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, 3915 }, 3916 3917 /* PREFIX_VEX_0F4A_L_1_W_1 */ 3918 { 3919 { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, 3920 { Bad_Opcode }, 3921 { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, 3922 }, 3923 3924 /* PREFIX_VEX_0F4B_L_1_W_0 */ 3925 { 3926 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, 3927 { Bad_Opcode }, 3928 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, 3929 }, 3930 3931 /* PREFIX_VEX_0F4B_L_1_W_1 */ 3932 { 3933 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, 3934 }, 3935 3936 /* PREFIX_VEX_0F6F */ 3937 { 3938 { Bad_Opcode }, 3939 { "vmovdqu", { XM, EXx }, 0 }, 3940 { "vmovdqa", { XM, EXx }, 0 }, 3941 }, 3942 3943 /* PREFIX_VEX_0F70 */ 3944 { 3945 { Bad_Opcode }, 3946 { "vpshufhw", { XM, EXx, Ib }, 0 }, 3947 { "vpshufd", { XM, EXx, Ib }, 0 }, 3948 { "vpshuflw", { XM, EXx, Ib }, 0 }, 3949 }, 3950 3951 /* PREFIX_VEX_0F7E */ 3952 { 3953 { Bad_Opcode }, 3954 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, 3955 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, 3956 }, 3957 3958 /* PREFIX_VEX_0F7F */ 3959 { 3960 { Bad_Opcode }, 3961 { "vmovdqu", { EXxS, XM }, 0 }, 3962 { "vmovdqa", { EXxS, XM }, 0 }, 3963 }, 3964 3965 /* PREFIX_VEX_0F90_L_0_W_0 */ 3966 { 3967 { "%XEkmovw", { MaskG, MaskE }, 0 }, 3968 { Bad_Opcode }, 3969 { "%XEkmovb", { MaskG, MaskBDE }, 0 }, 3970 }, 3971 3972 /* PREFIX_VEX_0F90_L_0_W_1 */ 3973 { 3974 { "%XEkmovq", { MaskG, MaskE }, 0 }, 3975 { Bad_Opcode }, 3976 { "%XEkmovd", { MaskG, MaskBDE }, 0 }, 3977 }, 3978 3979 /* PREFIX_VEX_0F91_L_0_W_0 */ 3980 { 3981 { "%XEkmovw", { Mw, MaskG }, 0 }, 3982 { Bad_Opcode }, 3983 { "%XEkmovb", { Mb, MaskG }, 0 }, 3984 }, 3985 3986 /* PREFIX_VEX_0F91_L_0_W_1 */ 3987 { 3988 { "%XEkmovq", { Mq, MaskG }, 0 }, 3989 { Bad_Opcode }, 3990 { "%XEkmovd", { Md, MaskG }, 0 }, 3991 }, 3992 3993 /* PREFIX_VEX_0F92_L_0_W_0 */ 3994 { 3995 { "%XEkmovw", { MaskG, Rdq }, 0 }, 3996 { Bad_Opcode }, 3997 { "%XEkmovb", { MaskG, Rdq }, 0 }, 3998 { "%XEkmovd", { MaskG, Rdq }, 0 }, 3999 }, 4000 4001 /* PREFIX_VEX_0F92_L_0_W_1 */ 4002 { 4003 { Bad_Opcode }, 4004 { Bad_Opcode }, 4005 { Bad_Opcode }, 4006 { "%XEkmovK", { MaskG, Rdq }, 0 }, 4007 }, 4008 4009 /* PREFIX_VEX_0F93_L_0_W_0 */ 4010 { 4011 { "%XEkmovw", { Gdq, MaskR }, 0 }, 4012 { Bad_Opcode }, 4013 { "%XEkmovb", { Gdq, MaskR }, 0 }, 4014 { "%XEkmovd", { Gdq, MaskR }, 0 }, 4015 }, 4016 4017 /* PREFIX_VEX_0F93_L_0_W_1 */ 4018 { 4019 { Bad_Opcode }, 4020 { Bad_Opcode }, 4021 { Bad_Opcode }, 4022 { "%XEkmovK", { Gdq, MaskR }, 0 }, 4023 }, 4024 4025 /* PREFIX_VEX_0F98_L_0_W_0 */ 4026 { 4027 { "kortestw", { MaskG, MaskR }, 0 }, 4028 { Bad_Opcode }, 4029 { "kortestb", { MaskG, MaskR }, 0 }, 4030 }, 4031 4032 /* PREFIX_VEX_0F98_L_0_W_1 */ 4033 { 4034 { "kortestq", { MaskG, MaskR }, 0 }, 4035 { Bad_Opcode }, 4036 { "kortestd", { MaskG, MaskR }, 0 }, 4037 }, 4038 4039 /* PREFIX_VEX_0F99_L_0_W_0 */ 4040 { 4041 { "ktestw", { MaskG, MaskR }, 0 }, 4042 { Bad_Opcode }, 4043 { "ktestb", { MaskG, MaskR }, 0 }, 4044 }, 4045 4046 /* PREFIX_VEX_0F99_L_0_W_1 */ 4047 { 4048 { "ktestq", { MaskG, MaskR }, 0 }, 4049 { Bad_Opcode }, 4050 { "ktestd", { MaskG, MaskR }, 0 }, 4051 }, 4052 4053 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */ 4054 { 4055 { "ldtilecfg", { M }, 0 }, 4056 { Bad_Opcode }, 4057 { "sttilecfg", { M }, 0 }, 4058 }, 4059 4060 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */ 4061 { 4062 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) }, 4063 { Bad_Opcode }, 4064 { Bad_Opcode }, 4065 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) }, 4066 }, 4067 4068 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */ 4069 { 4070 { Bad_Opcode }, 4071 { "tilestored", { MVexSIBMEM, TMM }, 0 }, 4072 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, 4073 { "tileloadd", { TMM, MVexSIBMEM }, 0 }, 4074 }, 4075 4076 /* PREFIX_VEX_0F3850_W_0 */ 4077 { 4078 { "%XEvpdpbuud", { XM, Vex, EXx }, 0 }, 4079 { "%XEvpdpbsud", { XM, Vex, EXx }, 0 }, 4080 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 }, 4081 { "%XEvpdpbssd", { XM, Vex, EXx }, 0 }, 4082 }, 4083 4084 /* PREFIX_VEX_0F3851_W_0 */ 4085 { 4086 { "%XEvpdpbuuds", { XM, Vex, EXx }, 0 }, 4087 { "%XEvpdpbsuds", { XM, Vex, EXx }, 0 }, 4088 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 }, 4089 { "%XEvpdpbssds", { XM, Vex, EXx }, 0 }, 4090 }, 4091 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */ 4092 { 4093 { Bad_Opcode }, 4094 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 }, 4095 { Bad_Opcode }, 4096 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4097 }, 4098 4099 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */ 4100 { 4101 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 }, 4102 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 }, 4103 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 }, 4104 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 }, 4105 }, 4106 4107 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */ 4108 { 4109 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4110 { Bad_Opcode }, 4111 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4112 }, 4113 4114 /* PREFIX_VEX_0F3872 */ 4115 { 4116 { Bad_Opcode }, 4117 { VEX_W_TABLE (VEX_W_0F3872_P_1) }, 4118 }, 4119 4120 /* PREFIX_VEX_0F38B0_W_0 */ 4121 { 4122 { "vcvtneoph2ps", { XM, Mx }, 0 }, 4123 { "vcvtneebf162ps", { XM, Mx }, 0 }, 4124 { "vcvtneeph2ps", { XM, Mx }, 0 }, 4125 { "vcvtneobf162ps", { XM, Mx }, 0 }, 4126 }, 4127 4128 /* PREFIX_VEX_0F38B1_W_0 */ 4129 { 4130 { Bad_Opcode }, 4131 { "vbcstnebf162ps", { XM, Mw }, 0 }, 4132 { "vbcstnesh2ps", { XM, Mw }, 0 }, 4133 }, 4134 4135 /* PREFIX_VEX_0F38D2_W_0 */ 4136 { 4137 { "%XEvpdpwuud", { XM, Vex, EXx }, 0 }, 4138 { "%XEvpdpwsud", { XM, Vex, EXx }, 0 }, 4139 { "%XEvpdpwusd", { XM, Vex, EXx }, 0 }, 4140 }, 4141 4142 /* PREFIX_VEX_0F38D3_W_0 */ 4143 { 4144 { "%XEvpdpwuuds", { XM, Vex, EXx }, 0 }, 4145 { "%XEvpdpwsuds", { XM, Vex, EXx }, 0 }, 4146 { "%XEvpdpwusds", { XM, Vex, EXx }, 0 }, 4147 }, 4148 4149 /* PREFIX_VEX_0F38CB */ 4150 { 4151 { Bad_Opcode }, 4152 { Bad_Opcode }, 4153 { Bad_Opcode }, 4154 { VEX_W_TABLE (VEX_W_0F38CB_P_3) }, 4155 }, 4156 4157 /* PREFIX_VEX_0F38CC */ 4158 { 4159 { Bad_Opcode }, 4160 { Bad_Opcode }, 4161 { Bad_Opcode }, 4162 { VEX_W_TABLE (VEX_W_0F38CC_P_3) }, 4163 }, 4164 4165 /* PREFIX_VEX_0F38CD */ 4166 { 4167 { Bad_Opcode }, 4168 { Bad_Opcode }, 4169 { Bad_Opcode }, 4170 { VEX_W_TABLE (VEX_W_0F38CD_P_3) }, 4171 }, 4172 4173 /* PREFIX_VEX_0F38DA_W_0 */ 4174 { 4175 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) }, 4176 { "%XEvsm4key4", { XM, Vex, EXx }, 0 }, 4177 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) }, 4178 { "%XEvsm4rnds4", { XM, Vex, EXx }, 0 }, 4179 }, 4180 4181 /* PREFIX_VEX_0F38F2_L_0 */ 4182 { 4183 { "%NFandnS", { Gdq, VexGdq, Edq }, 0 }, 4184 }, 4185 4186 /* PREFIX_VEX_0F38F3_L_0 */ 4187 { 4188 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) }, 4189 }, 4190 4191 /* PREFIX_VEX_0F38F5_L_0 */ 4192 { 4193 { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 }, 4194 { "%XEpextS", { Gdq, VexGdq, Edq }, 0 }, 4195 { Bad_Opcode }, 4196 { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 }, 4197 }, 4198 4199 /* PREFIX_VEX_0F38F6_L_0 */ 4200 { 4201 { Bad_Opcode }, 4202 { Bad_Opcode }, 4203 { Bad_Opcode }, 4204 { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 }, 4205 }, 4206 4207 /* PREFIX_VEX_0F38F7_L_0 */ 4208 { 4209 { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 }, 4210 { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 }, 4211 { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 }, 4212 { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 }, 4213 }, 4214 4215 /* PREFIX_VEX_0F3AF0_L_0 */ 4216 { 4217 { Bad_Opcode }, 4218 { Bad_Opcode }, 4219 { Bad_Opcode }, 4220 { "%XErorxS", { Gdq, Edq, Ib }, 0 }, 4221 }, 4222 4223 /* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */ 4224 { 4225 { Bad_Opcode }, 4226 { "wrmsrns", { Skip_MODRM, Id, Rq }, 0 }, 4227 { Bad_Opcode }, 4228 { "rdmsr", { Rq, Id }, 0 }, 4229 }, 4230 4231 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ 4232 { 4233 { Bad_Opcode }, 4234 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, 4235 { Bad_Opcode }, 4236 { "urdmsr", { Rq, Id }, 0 }, 4237 }, 4238 4239 #include "i386-dis-evex-prefix.h" 4240 }; 4241 4242 static const struct dis386 x86_64_table[][2] = { 4243 /* X86_64_06 */ 4244 { 4245 { "pushP", { es }, 0 }, 4246 }, 4247 4248 /* X86_64_07 */ 4249 { 4250 { "popP", { es }, 0 }, 4251 }, 4252 4253 /* X86_64_0E */ 4254 { 4255 { "pushP", { cs }, 0 }, 4256 }, 4257 4258 /* X86_64_16 */ 4259 { 4260 { "pushP", { ss }, 0 }, 4261 }, 4262 4263 /* X86_64_17 */ 4264 { 4265 { "popP", { ss }, 0 }, 4266 }, 4267 4268 /* X86_64_1E */ 4269 { 4270 { "pushP", { ds }, 0 }, 4271 }, 4272 4273 /* X86_64_1F */ 4274 { 4275 { "popP", { ds }, 0 }, 4276 }, 4277 4278 /* X86_64_27 */ 4279 { 4280 { "daa", { XX }, 0 }, 4281 }, 4282 4283 /* X86_64_2F */ 4284 { 4285 { "das", { XX }, 0 }, 4286 }, 4287 4288 /* X86_64_37 */ 4289 { 4290 { "aaa", { XX }, 0 }, 4291 }, 4292 4293 /* X86_64_3F */ 4294 { 4295 { "aas", { XX }, 0 }, 4296 }, 4297 4298 /* X86_64_60 */ 4299 { 4300 { "pushaP", { XX }, 0 }, 4301 }, 4302 4303 /* X86_64_61 */ 4304 { 4305 { "popaP", { XX }, 0 }, 4306 }, 4307 4308 /* X86_64_62 */ 4309 { 4310 { MOD_TABLE (MOD_62_32BIT) }, 4311 { EVEX_TABLE () }, 4312 }, 4313 4314 /* X86_64_63 */ 4315 { 4316 { "arplS", { Sv, Gv }, 0 }, 4317 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 }, 4318 }, 4319 4320 /* X86_64_6D */ 4321 { 4322 { "ins{R|}", { Yzr, indirDX }, 0 }, 4323 { "ins{G|}", { Yzr, indirDX }, 0 }, 4324 }, 4325 4326 /* X86_64_6F */ 4327 { 4328 { "outs{R|}", { indirDXr, Xz }, 0 }, 4329 { "outs{G|}", { indirDXr, Xz }, 0 }, 4330 }, 4331 4332 /* X86_64_82 */ 4333 { 4334 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ 4335 { REG_TABLE (REG_80) }, 4336 }, 4337 4338 /* X86_64_9A */ 4339 { 4340 { "{l|}call{P|}", { Ap }, 0 }, 4341 }, 4342 4343 /* X86_64_C2 */ 4344 { 4345 { "retP", { Iw, BND }, 0 }, 4346 { "ret@", { Iw, BND }, 0 }, 4347 }, 4348 4349 /* X86_64_C3 */ 4350 { 4351 { "retP", { BND }, 0 }, 4352 { "ret@", { BND }, 0 }, 4353 }, 4354 4355 /* X86_64_C4 */ 4356 { 4357 { MOD_TABLE (MOD_C4_32BIT) }, 4358 { VEX_C4_TABLE () }, 4359 }, 4360 4361 /* X86_64_C5 */ 4362 { 4363 { MOD_TABLE (MOD_C5_32BIT) }, 4364 { VEX_C5_TABLE () }, 4365 }, 4366 4367 /* X86_64_CE */ 4368 { 4369 { "into", { XX }, 0 }, 4370 }, 4371 4372 /* X86_64_D4 */ 4373 { 4374 { "aam", { Ib }, 0 }, 4375 }, 4376 4377 /* X86_64_D5 */ 4378 { 4379 { "aad", { Ib }, 0 }, 4380 }, 4381 4382 /* X86_64_E8 */ 4383 { 4384 { "callP", { Jv, BND }, 0 }, 4385 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL } 4386 }, 4387 4388 /* X86_64_E9 */ 4389 { 4390 { "jmpP", { Jv, BND }, 0 }, 4391 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL } 4392 }, 4393 4394 /* X86_64_EA */ 4395 { 4396 { "{l|}jmp{P|}", { Ap }, 0 }, 4397 }, 4398 4399 /* X86_64_0F00_REG_6 */ 4400 { 4401 { Bad_Opcode }, 4402 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) }, 4403 }, 4404 4405 /* X86_64_0F01_REG_0 */ 4406 { 4407 { "sgdt{Q|Q}", { M }, 0 }, 4408 { "sgdt", { M }, 0 }, 4409 }, 4410 4411 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ 4412 { 4413 { Bad_Opcode }, 4414 { "wrmsrlist", { Skip_MODRM }, 0 }, 4415 }, 4416 4417 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ 4418 { 4419 { Bad_Opcode }, 4420 { "rdmsrlist", { Skip_MODRM }, 0 }, 4421 }, 4422 4423 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */ 4424 { 4425 { Bad_Opcode }, 4426 { "pbndkb", { Skip_MODRM }, 0 }, 4427 }, 4428 4429 /* X86_64_0F01_REG_1 */ 4430 { 4431 { "sidt{Q|Q}", { M }, 0 }, 4432 { "sidt", { M }, 0 }, 4433 }, 4434 4435 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */ 4436 { 4437 { Bad_Opcode }, 4438 { "eretu", { Skip_MODRM }, 0 }, 4439 }, 4440 4441 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */ 4442 { 4443 { Bad_Opcode }, 4444 { "erets", { Skip_MODRM }, 0 }, 4445 }, 4446 4447 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ 4448 { 4449 { Bad_Opcode }, 4450 { "seamret", { Skip_MODRM }, 0 }, 4451 }, 4452 4453 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ 4454 { 4455 { Bad_Opcode }, 4456 { "seamops", { Skip_MODRM }, 0 }, 4457 }, 4458 4459 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ 4460 { 4461 { Bad_Opcode }, 4462 { "seamcall", { Skip_MODRM }, 0 }, 4463 }, 4464 4465 /* X86_64_0F01_REG_2 */ 4466 { 4467 { "lgdt{Q|Q}", { M }, 0 }, 4468 { "lgdt", { M }, 0 }, 4469 }, 4470 4471 /* X86_64_0F01_REG_3 */ 4472 { 4473 { "lidt{Q|Q}", { M }, 0 }, 4474 { "lidt", { M }, 0 }, 4475 }, 4476 4477 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */ 4478 { 4479 { Bad_Opcode }, 4480 { "uiret", { Skip_MODRM }, 0 }, 4481 }, 4482 4483 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */ 4484 { 4485 { Bad_Opcode }, 4486 { "testui", { Skip_MODRM }, 0 }, 4487 }, 4488 4489 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */ 4490 { 4491 { Bad_Opcode }, 4492 { "clui", { Skip_MODRM }, 0 }, 4493 }, 4494 4495 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */ 4496 { 4497 { Bad_Opcode }, 4498 { "stui", { Skip_MODRM }, 0 }, 4499 }, 4500 4501 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */ 4502 { 4503 { Bad_Opcode }, 4504 { "rmpquery", { Skip_MODRM }, 0 }, 4505 }, 4506 4507 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ 4508 { 4509 { Bad_Opcode }, 4510 { "rmpadjust", { Skip_MODRM }, 0 }, 4511 }, 4512 4513 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ 4514 { 4515 { Bad_Opcode }, 4516 { "rmpupdate", { Skip_MODRM }, 0 }, 4517 }, 4518 4519 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ 4520 { 4521 { Bad_Opcode }, 4522 { "psmash", { Skip_MODRM }, 0 }, 4523 }, 4524 4525 /* X86_64_0F18_REG_6_MOD_0 */ 4526 { 4527 { "nopQ", { Ev }, 0 }, 4528 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) }, 4529 }, 4530 4531 /* X86_64_0F18_REG_7_MOD_0 */ 4532 { 4533 { "nopQ", { Ev }, 0 }, 4534 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) }, 4535 }, 4536 4537 { 4538 /* X86_64_0F24 */ 4539 { "movZ", { Em, Td }, 0 }, 4540 }, 4541 4542 { 4543 /* X86_64_0F26 */ 4544 { "movZ", { Td, Em }, 0 }, 4545 }, 4546 4547 { 4548 /* X86_64_0F38F8_M_1 */ 4549 { Bad_Opcode }, 4550 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, 4551 }, 4552 4553 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ 4554 { 4555 { Bad_Opcode }, 4556 { "senduipi", { Eq }, 0 }, 4557 }, 4558 4559 /* X86_64_VEX_0F3849 */ 4560 { 4561 { Bad_Opcode }, 4562 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, 4563 }, 4564 4565 /* X86_64_VEX_0F384B */ 4566 { 4567 { Bad_Opcode }, 4568 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) }, 4569 }, 4570 4571 /* X86_64_VEX_0F385C */ 4572 { 4573 { Bad_Opcode }, 4574 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) }, 4575 }, 4576 4577 /* X86_64_VEX_0F385E */ 4578 { 4579 { Bad_Opcode }, 4580 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) }, 4581 }, 4582 4583 /* X86_64_VEX_0F386C */ 4584 { 4585 { Bad_Opcode }, 4586 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) }, 4587 }, 4588 4589 /* X86_64_VEX_0F38Ex */ 4590 { 4591 { Bad_Opcode }, 4592 { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, 4593 }, 4594 4595 /* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */ 4596 { 4597 { Bad_Opcode }, 4598 { PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) }, 4599 }, 4600 4601 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ 4602 { 4603 { Bad_Opcode }, 4604 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, 4605 }, 4606 }; 4607 4608 static const struct dis386 three_byte_table[][256] = { 4609 4610 /* THREE_BYTE_0F38 */ 4611 { 4612 /* 00 */ 4613 { "pshufb", { MX, EM }, PREFIX_OPCODE }, 4614 { "phaddw", { MX, EM }, PREFIX_OPCODE }, 4615 { "phaddd", { MX, EM }, PREFIX_OPCODE }, 4616 { "phaddsw", { MX, EM }, PREFIX_OPCODE }, 4617 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, 4618 { "phsubw", { MX, EM }, PREFIX_OPCODE }, 4619 { "phsubd", { MX, EM }, PREFIX_OPCODE }, 4620 { "phsubsw", { MX, EM }, PREFIX_OPCODE }, 4621 /* 08 */ 4622 { "psignb", { MX, EM }, PREFIX_OPCODE }, 4623 { "psignw", { MX, EM }, PREFIX_OPCODE }, 4624 { "psignd", { MX, EM }, PREFIX_OPCODE }, 4625 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, 4626 { Bad_Opcode }, 4627 { Bad_Opcode }, 4628 { Bad_Opcode }, 4629 { Bad_Opcode }, 4630 /* 10 */ 4631 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, 4632 { Bad_Opcode }, 4633 { Bad_Opcode }, 4634 { Bad_Opcode }, 4635 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, 4636 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, 4637 { Bad_Opcode }, 4638 { "ptest", { XM, EXx }, PREFIX_DATA }, 4639 /* 18 */ 4640 { Bad_Opcode }, 4641 { Bad_Opcode }, 4642 { Bad_Opcode }, 4643 { Bad_Opcode }, 4644 { "pabsb", { MX, EM }, PREFIX_OPCODE }, 4645 { "pabsw", { MX, EM }, PREFIX_OPCODE }, 4646 { "pabsd", { MX, EM }, PREFIX_OPCODE }, 4647 { Bad_Opcode }, 4648 /* 20 */ 4649 { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, 4650 { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, 4651 { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, 4652 { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, 4653 { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, 4654 { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, 4655 { Bad_Opcode }, 4656 { Bad_Opcode }, 4657 /* 28 */ 4658 { "pmuldq", { XM, EXx }, PREFIX_DATA }, 4659 { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, 4660 { "movntdqa", { XM, Mx }, PREFIX_DATA }, 4661 { "packusdw", { XM, EXx }, PREFIX_DATA }, 4662 { Bad_Opcode }, 4663 { Bad_Opcode }, 4664 { Bad_Opcode }, 4665 { Bad_Opcode }, 4666 /* 30 */ 4667 { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, 4668 { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, 4669 { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, 4670 { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, 4671 { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, 4672 { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, 4673 { Bad_Opcode }, 4674 { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, 4675 /* 38 */ 4676 { "pminsb", { XM, EXx }, PREFIX_DATA }, 4677 { "pminsd", { XM, EXx }, PREFIX_DATA }, 4678 { "pminuw", { XM, EXx }, PREFIX_DATA }, 4679 { "pminud", { XM, EXx }, PREFIX_DATA }, 4680 { "pmaxsb", { XM, EXx }, PREFIX_DATA }, 4681 { "pmaxsd", { XM, EXx }, PREFIX_DATA }, 4682 { "pmaxuw", { XM, EXx }, PREFIX_DATA }, 4683 { "pmaxud", { XM, EXx }, PREFIX_DATA }, 4684 /* 40 */ 4685 { "pmulld", { XM, EXx }, PREFIX_DATA }, 4686 { "phminposuw", { XM, EXx }, PREFIX_DATA }, 4687 { Bad_Opcode }, 4688 { Bad_Opcode }, 4689 { Bad_Opcode }, 4690 { Bad_Opcode }, 4691 { Bad_Opcode }, 4692 { Bad_Opcode }, 4693 /* 48 */ 4694 { Bad_Opcode }, 4695 { Bad_Opcode }, 4696 { Bad_Opcode }, 4697 { Bad_Opcode }, 4698 { Bad_Opcode }, 4699 { Bad_Opcode }, 4700 { Bad_Opcode }, 4701 { Bad_Opcode }, 4702 /* 50 */ 4703 { Bad_Opcode }, 4704 { Bad_Opcode }, 4705 { Bad_Opcode }, 4706 { Bad_Opcode }, 4707 { Bad_Opcode }, 4708 { Bad_Opcode }, 4709 { Bad_Opcode }, 4710 { Bad_Opcode }, 4711 /* 58 */ 4712 { Bad_Opcode }, 4713 { Bad_Opcode }, 4714 { Bad_Opcode }, 4715 { Bad_Opcode }, 4716 { Bad_Opcode }, 4717 { Bad_Opcode }, 4718 { Bad_Opcode }, 4719 { Bad_Opcode }, 4720 /* 60 */ 4721 { Bad_Opcode }, 4722 { Bad_Opcode }, 4723 { Bad_Opcode }, 4724 { Bad_Opcode }, 4725 { Bad_Opcode }, 4726 { Bad_Opcode }, 4727 { Bad_Opcode }, 4728 { Bad_Opcode }, 4729 /* 68 */ 4730 { Bad_Opcode }, 4731 { Bad_Opcode }, 4732 { Bad_Opcode }, 4733 { Bad_Opcode }, 4734 { Bad_Opcode }, 4735 { Bad_Opcode }, 4736 { Bad_Opcode }, 4737 { Bad_Opcode }, 4738 /* 70 */ 4739 { Bad_Opcode }, 4740 { Bad_Opcode }, 4741 { Bad_Opcode }, 4742 { Bad_Opcode }, 4743 { Bad_Opcode }, 4744 { Bad_Opcode }, 4745 { Bad_Opcode }, 4746 { Bad_Opcode }, 4747 /* 78 */ 4748 { Bad_Opcode }, 4749 { Bad_Opcode }, 4750 { Bad_Opcode }, 4751 { Bad_Opcode }, 4752 { Bad_Opcode }, 4753 { Bad_Opcode }, 4754 { Bad_Opcode }, 4755 { Bad_Opcode }, 4756 /* 80 */ 4757 { "invept", { Gm, Mo }, PREFIX_DATA }, 4758 { "invvpid", { Gm, Mo }, PREFIX_DATA }, 4759 { "invpcid", { Gm, M }, PREFIX_DATA }, 4760 { Bad_Opcode }, 4761 { Bad_Opcode }, 4762 { Bad_Opcode }, 4763 { Bad_Opcode }, 4764 { Bad_Opcode }, 4765 /* 88 */ 4766 { Bad_Opcode }, 4767 { Bad_Opcode }, 4768 { Bad_Opcode }, 4769 { Bad_Opcode }, 4770 { Bad_Opcode }, 4771 { Bad_Opcode }, 4772 { Bad_Opcode }, 4773 { Bad_Opcode }, 4774 /* 90 */ 4775 { Bad_Opcode }, 4776 { Bad_Opcode }, 4777 { Bad_Opcode }, 4778 { Bad_Opcode }, 4779 { Bad_Opcode }, 4780 { Bad_Opcode }, 4781 { Bad_Opcode }, 4782 { Bad_Opcode }, 4783 /* 98 */ 4784 { Bad_Opcode }, 4785 { Bad_Opcode }, 4786 { Bad_Opcode }, 4787 { Bad_Opcode }, 4788 { Bad_Opcode }, 4789 { Bad_Opcode }, 4790 { Bad_Opcode }, 4791 { Bad_Opcode }, 4792 /* a0 */ 4793 { Bad_Opcode }, 4794 { Bad_Opcode }, 4795 { Bad_Opcode }, 4796 { Bad_Opcode }, 4797 { Bad_Opcode }, 4798 { Bad_Opcode }, 4799 { Bad_Opcode }, 4800 { Bad_Opcode }, 4801 /* a8 */ 4802 { Bad_Opcode }, 4803 { Bad_Opcode }, 4804 { Bad_Opcode }, 4805 { Bad_Opcode }, 4806 { Bad_Opcode }, 4807 { Bad_Opcode }, 4808 { Bad_Opcode }, 4809 { Bad_Opcode }, 4810 /* b0 */ 4811 { Bad_Opcode }, 4812 { Bad_Opcode }, 4813 { Bad_Opcode }, 4814 { Bad_Opcode }, 4815 { Bad_Opcode }, 4816 { Bad_Opcode }, 4817 { Bad_Opcode }, 4818 { Bad_Opcode }, 4819 /* b8 */ 4820 { Bad_Opcode }, 4821 { Bad_Opcode }, 4822 { Bad_Opcode }, 4823 { Bad_Opcode }, 4824 { Bad_Opcode }, 4825 { Bad_Opcode }, 4826 { Bad_Opcode }, 4827 { Bad_Opcode }, 4828 /* c0 */ 4829 { Bad_Opcode }, 4830 { Bad_Opcode }, 4831 { Bad_Opcode }, 4832 { Bad_Opcode }, 4833 { Bad_Opcode }, 4834 { Bad_Opcode }, 4835 { Bad_Opcode }, 4836 { Bad_Opcode }, 4837 /* c8 */ 4838 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, 4839 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, 4840 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, 4841 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, 4842 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, 4843 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, 4844 { Bad_Opcode }, 4845 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, 4846 /* d0 */ 4847 { Bad_Opcode }, 4848 { Bad_Opcode }, 4849 { Bad_Opcode }, 4850 { Bad_Opcode }, 4851 { Bad_Opcode }, 4852 { Bad_Opcode }, 4853 { Bad_Opcode }, 4854 { Bad_Opcode }, 4855 /* d8 */ 4856 { PREFIX_TABLE (PREFIX_0F38D8) }, 4857 { Bad_Opcode }, 4858 { Bad_Opcode }, 4859 { "aesimc", { XM, EXx }, PREFIX_DATA }, 4860 { PREFIX_TABLE (PREFIX_0F38DC) }, 4861 { PREFIX_TABLE (PREFIX_0F38DD) }, 4862 { PREFIX_TABLE (PREFIX_0F38DE) }, 4863 { PREFIX_TABLE (PREFIX_0F38DF) }, 4864 /* e0 */ 4865 { Bad_Opcode }, 4866 { Bad_Opcode }, 4867 { Bad_Opcode }, 4868 { Bad_Opcode }, 4869 { Bad_Opcode }, 4870 { Bad_Opcode }, 4871 { Bad_Opcode }, 4872 { Bad_Opcode }, 4873 /* e8 */ 4874 { Bad_Opcode }, 4875 { Bad_Opcode }, 4876 { Bad_Opcode }, 4877 { Bad_Opcode }, 4878 { Bad_Opcode }, 4879 { Bad_Opcode }, 4880 { Bad_Opcode }, 4881 { Bad_Opcode }, 4882 /* f0 */ 4883 { PREFIX_TABLE (PREFIX_0F38F0) }, 4884 { PREFIX_TABLE (PREFIX_0F38F1) }, 4885 { Bad_Opcode }, 4886 { Bad_Opcode }, 4887 { Bad_Opcode }, 4888 { "wrussK", { M, Gdq }, PREFIX_DATA }, 4889 { PREFIX_TABLE (PREFIX_0F38F6) }, 4890 { Bad_Opcode }, 4891 /* f8 */ 4892 { MOD_TABLE (MOD_0F38F8) }, 4893 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, 4894 { PREFIX_TABLE (PREFIX_0F38FA) }, 4895 { PREFIX_TABLE (PREFIX_0F38FB) }, 4896 { PREFIX_TABLE (PREFIX_0F38FC) }, 4897 { Bad_Opcode }, 4898 { Bad_Opcode }, 4899 { Bad_Opcode }, 4900 }, 4901 /* THREE_BYTE_0F3A */ 4902 { 4903 /* 00 */ 4904 { Bad_Opcode }, 4905 { Bad_Opcode }, 4906 { Bad_Opcode }, 4907 { Bad_Opcode }, 4908 { Bad_Opcode }, 4909 { Bad_Opcode }, 4910 { Bad_Opcode }, 4911 { Bad_Opcode }, 4912 /* 08 */ 4913 { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, 4914 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, 4915 { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, 4916 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, 4917 { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, 4918 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, 4919 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, 4920 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, 4921 /* 10 */ 4922 { Bad_Opcode }, 4923 { Bad_Opcode }, 4924 { Bad_Opcode }, 4925 { Bad_Opcode }, 4926 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA }, 4927 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA }, 4928 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, 4929 { "extractps", { Ed, XM, Ib }, PREFIX_DATA }, 4930 /* 18 */ 4931 { Bad_Opcode }, 4932 { Bad_Opcode }, 4933 { Bad_Opcode }, 4934 { Bad_Opcode }, 4935 { Bad_Opcode }, 4936 { Bad_Opcode }, 4937 { Bad_Opcode }, 4938 { Bad_Opcode }, 4939 /* 20 */ 4940 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA }, 4941 { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, 4942 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, 4943 { Bad_Opcode }, 4944 { Bad_Opcode }, 4945 { Bad_Opcode }, 4946 { Bad_Opcode }, 4947 { Bad_Opcode }, 4948 /* 28 */ 4949 { Bad_Opcode }, 4950 { Bad_Opcode }, 4951 { Bad_Opcode }, 4952 { Bad_Opcode }, 4953 { Bad_Opcode }, 4954 { Bad_Opcode }, 4955 { Bad_Opcode }, 4956 { Bad_Opcode }, 4957 /* 30 */ 4958 { Bad_Opcode }, 4959 { Bad_Opcode }, 4960 { Bad_Opcode }, 4961 { Bad_Opcode }, 4962 { Bad_Opcode }, 4963 { Bad_Opcode }, 4964 { Bad_Opcode }, 4965 { Bad_Opcode }, 4966 /* 38 */ 4967 { Bad_Opcode }, 4968 { Bad_Opcode }, 4969 { Bad_Opcode }, 4970 { Bad_Opcode }, 4971 { Bad_Opcode }, 4972 { Bad_Opcode }, 4973 { Bad_Opcode }, 4974 { Bad_Opcode }, 4975 /* 40 */ 4976 { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, 4977 { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, 4978 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, 4979 { Bad_Opcode }, 4980 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, 4981 { Bad_Opcode }, 4982 { Bad_Opcode }, 4983 { Bad_Opcode }, 4984 /* 48 */ 4985 { Bad_Opcode }, 4986 { Bad_Opcode }, 4987 { Bad_Opcode }, 4988 { Bad_Opcode }, 4989 { Bad_Opcode }, 4990 { Bad_Opcode }, 4991 { Bad_Opcode }, 4992 { Bad_Opcode }, 4993 /* 50 */ 4994 { Bad_Opcode }, 4995 { Bad_Opcode }, 4996 { Bad_Opcode }, 4997 { Bad_Opcode }, 4998 { Bad_Opcode }, 4999 { Bad_Opcode }, 5000 { Bad_Opcode }, 5001 { Bad_Opcode }, 5002 /* 58 */ 5003 { Bad_Opcode }, 5004 { Bad_Opcode }, 5005 { Bad_Opcode }, 5006 { Bad_Opcode }, 5007 { Bad_Opcode }, 5008 { Bad_Opcode }, 5009 { Bad_Opcode }, 5010 { Bad_Opcode }, 5011 /* 60 */ 5012 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 5013 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 5014 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, 5015 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, 5016 { Bad_Opcode }, 5017 { Bad_Opcode }, 5018 { Bad_Opcode }, 5019 { Bad_Opcode }, 5020 /* 68 */ 5021 { Bad_Opcode }, 5022 { Bad_Opcode }, 5023 { Bad_Opcode }, 5024 { Bad_Opcode }, 5025 { Bad_Opcode }, 5026 { Bad_Opcode }, 5027 { Bad_Opcode }, 5028 { Bad_Opcode }, 5029 /* 70 */ 5030 { Bad_Opcode }, 5031 { Bad_Opcode }, 5032 { Bad_Opcode }, 5033 { Bad_Opcode }, 5034 { Bad_Opcode }, 5035 { Bad_Opcode }, 5036 { Bad_Opcode }, 5037 { Bad_Opcode }, 5038 /* 78 */ 5039 { Bad_Opcode }, 5040 { Bad_Opcode }, 5041 { Bad_Opcode }, 5042 { Bad_Opcode }, 5043 { Bad_Opcode }, 5044 { Bad_Opcode }, 5045 { Bad_Opcode }, 5046 { Bad_Opcode }, 5047 /* 80 */ 5048 { Bad_Opcode }, 5049 { Bad_Opcode }, 5050 { Bad_Opcode }, 5051 { Bad_Opcode }, 5052 { Bad_Opcode }, 5053 { Bad_Opcode }, 5054 { Bad_Opcode }, 5055 { Bad_Opcode }, 5056 /* 88 */ 5057 { Bad_Opcode }, 5058 { Bad_Opcode }, 5059 { Bad_Opcode }, 5060 { Bad_Opcode }, 5061 { Bad_Opcode }, 5062 { Bad_Opcode }, 5063 { Bad_Opcode }, 5064 { Bad_Opcode }, 5065 /* 90 */ 5066 { Bad_Opcode }, 5067 { Bad_Opcode }, 5068 { Bad_Opcode }, 5069 { Bad_Opcode }, 5070 { Bad_Opcode }, 5071 { Bad_Opcode }, 5072 { Bad_Opcode }, 5073 { Bad_Opcode }, 5074 /* 98 */ 5075 { Bad_Opcode }, 5076 { Bad_Opcode }, 5077 { Bad_Opcode }, 5078 { Bad_Opcode }, 5079 { Bad_Opcode }, 5080 { Bad_Opcode }, 5081 { Bad_Opcode }, 5082 { Bad_Opcode }, 5083 /* a0 */ 5084 { Bad_Opcode }, 5085 { Bad_Opcode }, 5086 { Bad_Opcode }, 5087 { Bad_Opcode }, 5088 { Bad_Opcode }, 5089 { Bad_Opcode }, 5090 { Bad_Opcode }, 5091 { Bad_Opcode }, 5092 /* a8 */ 5093 { Bad_Opcode }, 5094 { Bad_Opcode }, 5095 { Bad_Opcode }, 5096 { Bad_Opcode }, 5097 { Bad_Opcode }, 5098 { Bad_Opcode }, 5099 { Bad_Opcode }, 5100 { Bad_Opcode }, 5101 /* b0 */ 5102 { Bad_Opcode }, 5103 { Bad_Opcode }, 5104 { Bad_Opcode }, 5105 { Bad_Opcode }, 5106 { Bad_Opcode }, 5107 { Bad_Opcode }, 5108 { Bad_Opcode }, 5109 { Bad_Opcode }, 5110 /* b8 */ 5111 { Bad_Opcode }, 5112 { Bad_Opcode }, 5113 { Bad_Opcode }, 5114 { Bad_Opcode }, 5115 { Bad_Opcode }, 5116 { Bad_Opcode }, 5117 { Bad_Opcode }, 5118 { Bad_Opcode }, 5119 /* c0 */ 5120 { Bad_Opcode }, 5121 { Bad_Opcode }, 5122 { Bad_Opcode }, 5123 { Bad_Opcode }, 5124 { Bad_Opcode }, 5125 { Bad_Opcode }, 5126 { Bad_Opcode }, 5127 { Bad_Opcode }, 5128 /* c8 */ 5129 { Bad_Opcode }, 5130 { Bad_Opcode }, 5131 { Bad_Opcode }, 5132 { Bad_Opcode }, 5133 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, 5134 { Bad_Opcode }, 5135 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, 5136 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, 5137 /* d0 */ 5138 { Bad_Opcode }, 5139 { Bad_Opcode }, 5140 { Bad_Opcode }, 5141 { Bad_Opcode }, 5142 { Bad_Opcode }, 5143 { Bad_Opcode }, 5144 { Bad_Opcode }, 5145 { Bad_Opcode }, 5146 /* d8 */ 5147 { Bad_Opcode }, 5148 { Bad_Opcode }, 5149 { Bad_Opcode }, 5150 { Bad_Opcode }, 5151 { Bad_Opcode }, 5152 { Bad_Opcode }, 5153 { Bad_Opcode }, 5154 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, 5155 /* e0 */ 5156 { Bad_Opcode }, 5157 { Bad_Opcode }, 5158 { Bad_Opcode }, 5159 { Bad_Opcode }, 5160 { Bad_Opcode }, 5161 { Bad_Opcode }, 5162 { Bad_Opcode }, 5163 { Bad_Opcode }, 5164 /* e8 */ 5165 { Bad_Opcode }, 5166 { Bad_Opcode }, 5167 { Bad_Opcode }, 5168 { Bad_Opcode }, 5169 { Bad_Opcode }, 5170 { Bad_Opcode }, 5171 { Bad_Opcode }, 5172 { Bad_Opcode }, 5173 /* f0 */ 5174 { PREFIX_TABLE (PREFIX_0F3A0F) }, 5175 { Bad_Opcode }, 5176 { Bad_Opcode }, 5177 { Bad_Opcode }, 5178 { Bad_Opcode }, 5179 { Bad_Opcode }, 5180 { Bad_Opcode }, 5181 { Bad_Opcode }, 5182 /* f8 */ 5183 { Bad_Opcode }, 5184 { Bad_Opcode }, 5185 { Bad_Opcode }, 5186 { Bad_Opcode }, 5187 { Bad_Opcode }, 5188 { Bad_Opcode }, 5189 { Bad_Opcode }, 5190 { Bad_Opcode }, 5191 }, 5192 }; 5193 5194 static const struct dis386 xop_table[][256] = { 5195 /* XOP_08 */ 5196 { 5197 /* 00 */ 5198 { Bad_Opcode }, 5199 { Bad_Opcode }, 5200 { Bad_Opcode }, 5201 { Bad_Opcode }, 5202 { Bad_Opcode }, 5203 { Bad_Opcode }, 5204 { Bad_Opcode }, 5205 { Bad_Opcode }, 5206 /* 08 */ 5207 { Bad_Opcode }, 5208 { Bad_Opcode }, 5209 { Bad_Opcode }, 5210 { Bad_Opcode }, 5211 { Bad_Opcode }, 5212 { Bad_Opcode }, 5213 { Bad_Opcode }, 5214 { Bad_Opcode }, 5215 /* 10 */ 5216 { Bad_Opcode }, 5217 { Bad_Opcode }, 5218 { Bad_Opcode }, 5219 { Bad_Opcode }, 5220 { Bad_Opcode }, 5221 { Bad_Opcode }, 5222 { Bad_Opcode }, 5223 { Bad_Opcode }, 5224 /* 18 */ 5225 { Bad_Opcode }, 5226 { Bad_Opcode }, 5227 { Bad_Opcode }, 5228 { Bad_Opcode }, 5229 { Bad_Opcode }, 5230 { Bad_Opcode }, 5231 { Bad_Opcode }, 5232 { Bad_Opcode }, 5233 /* 20 */ 5234 { Bad_Opcode }, 5235 { Bad_Opcode }, 5236 { Bad_Opcode }, 5237 { Bad_Opcode }, 5238 { Bad_Opcode }, 5239 { Bad_Opcode }, 5240 { Bad_Opcode }, 5241 { Bad_Opcode }, 5242 /* 28 */ 5243 { Bad_Opcode }, 5244 { Bad_Opcode }, 5245 { Bad_Opcode }, 5246 { Bad_Opcode }, 5247 { Bad_Opcode }, 5248 { Bad_Opcode }, 5249 { Bad_Opcode }, 5250 { Bad_Opcode }, 5251 /* 30 */ 5252 { Bad_Opcode }, 5253 { Bad_Opcode }, 5254 { Bad_Opcode }, 5255 { Bad_Opcode }, 5256 { Bad_Opcode }, 5257 { Bad_Opcode }, 5258 { Bad_Opcode }, 5259 { Bad_Opcode }, 5260 /* 38 */ 5261 { Bad_Opcode }, 5262 { Bad_Opcode }, 5263 { Bad_Opcode }, 5264 { Bad_Opcode }, 5265 { Bad_Opcode }, 5266 { Bad_Opcode }, 5267 { Bad_Opcode }, 5268 { Bad_Opcode }, 5269 /* 40 */ 5270 { Bad_Opcode }, 5271 { Bad_Opcode }, 5272 { Bad_Opcode }, 5273 { Bad_Opcode }, 5274 { Bad_Opcode }, 5275 { Bad_Opcode }, 5276 { Bad_Opcode }, 5277 { Bad_Opcode }, 5278 /* 48 */ 5279 { Bad_Opcode }, 5280 { Bad_Opcode }, 5281 { Bad_Opcode }, 5282 { Bad_Opcode }, 5283 { Bad_Opcode }, 5284 { Bad_Opcode }, 5285 { Bad_Opcode }, 5286 { Bad_Opcode }, 5287 /* 50 */ 5288 { Bad_Opcode }, 5289 { Bad_Opcode }, 5290 { Bad_Opcode }, 5291 { Bad_Opcode }, 5292 { Bad_Opcode }, 5293 { Bad_Opcode }, 5294 { Bad_Opcode }, 5295 { Bad_Opcode }, 5296 /* 58 */ 5297 { Bad_Opcode }, 5298 { Bad_Opcode }, 5299 { Bad_Opcode }, 5300 { Bad_Opcode }, 5301 { Bad_Opcode }, 5302 { Bad_Opcode }, 5303 { Bad_Opcode }, 5304 { Bad_Opcode }, 5305 /* 60 */ 5306 { Bad_Opcode }, 5307 { Bad_Opcode }, 5308 { Bad_Opcode }, 5309 { Bad_Opcode }, 5310 { Bad_Opcode }, 5311 { Bad_Opcode }, 5312 { Bad_Opcode }, 5313 { Bad_Opcode }, 5314 /* 68 */ 5315 { Bad_Opcode }, 5316 { Bad_Opcode }, 5317 { Bad_Opcode }, 5318 { Bad_Opcode }, 5319 { Bad_Opcode }, 5320 { Bad_Opcode }, 5321 { Bad_Opcode }, 5322 { Bad_Opcode }, 5323 /* 70 */ 5324 { Bad_Opcode }, 5325 { Bad_Opcode }, 5326 { Bad_Opcode }, 5327 { Bad_Opcode }, 5328 { Bad_Opcode }, 5329 { Bad_Opcode }, 5330 { Bad_Opcode }, 5331 { Bad_Opcode }, 5332 /* 78 */ 5333 { Bad_Opcode }, 5334 { Bad_Opcode }, 5335 { Bad_Opcode }, 5336 { Bad_Opcode }, 5337 { Bad_Opcode }, 5338 { Bad_Opcode }, 5339 { Bad_Opcode }, 5340 { Bad_Opcode }, 5341 /* 80 */ 5342 { Bad_Opcode }, 5343 { Bad_Opcode }, 5344 { Bad_Opcode }, 5345 { Bad_Opcode }, 5346 { Bad_Opcode }, 5347 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) }, 5348 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) }, 5349 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) }, 5350 /* 88 */ 5351 { Bad_Opcode }, 5352 { Bad_Opcode }, 5353 { Bad_Opcode }, 5354 { Bad_Opcode }, 5355 { Bad_Opcode }, 5356 { Bad_Opcode }, 5357 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) }, 5358 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) }, 5359 /* 90 */ 5360 { Bad_Opcode }, 5361 { Bad_Opcode }, 5362 { Bad_Opcode }, 5363 { Bad_Opcode }, 5364 { Bad_Opcode }, 5365 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) }, 5366 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) }, 5367 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) }, 5368 /* 98 */ 5369 { Bad_Opcode }, 5370 { Bad_Opcode }, 5371 { Bad_Opcode }, 5372 { Bad_Opcode }, 5373 { Bad_Opcode }, 5374 { Bad_Opcode }, 5375 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) }, 5376 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) }, 5377 /* a0 */ 5378 { Bad_Opcode }, 5379 { Bad_Opcode }, 5380 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, 5381 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) }, 5382 { Bad_Opcode }, 5383 { Bad_Opcode }, 5384 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) }, 5385 { Bad_Opcode }, 5386 /* a8 */ 5387 { Bad_Opcode }, 5388 { Bad_Opcode }, 5389 { Bad_Opcode }, 5390 { Bad_Opcode }, 5391 { Bad_Opcode }, 5392 { Bad_Opcode }, 5393 { Bad_Opcode }, 5394 { Bad_Opcode }, 5395 /* b0 */ 5396 { Bad_Opcode }, 5397 { Bad_Opcode }, 5398 { Bad_Opcode }, 5399 { Bad_Opcode }, 5400 { Bad_Opcode }, 5401 { Bad_Opcode }, 5402 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) }, 5403 { Bad_Opcode }, 5404 /* b8 */ 5405 { Bad_Opcode }, 5406 { Bad_Opcode }, 5407 { Bad_Opcode }, 5408 { Bad_Opcode }, 5409 { Bad_Opcode }, 5410 { Bad_Opcode }, 5411 { Bad_Opcode }, 5412 { Bad_Opcode }, 5413 /* c0 */ 5414 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) }, 5415 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) }, 5416 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) }, 5417 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) }, 5418 { Bad_Opcode }, 5419 { Bad_Opcode }, 5420 { Bad_Opcode }, 5421 { Bad_Opcode }, 5422 /* c8 */ 5423 { Bad_Opcode }, 5424 { Bad_Opcode }, 5425 { Bad_Opcode }, 5426 { Bad_Opcode }, 5427 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) }, 5428 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) }, 5429 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) }, 5430 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) }, 5431 /* d0 */ 5432 { Bad_Opcode }, 5433 { Bad_Opcode }, 5434 { Bad_Opcode }, 5435 { Bad_Opcode }, 5436 { Bad_Opcode }, 5437 { Bad_Opcode }, 5438 { Bad_Opcode }, 5439 { Bad_Opcode }, 5440 /* d8 */ 5441 { Bad_Opcode }, 5442 { Bad_Opcode }, 5443 { Bad_Opcode }, 5444 { Bad_Opcode }, 5445 { Bad_Opcode }, 5446 { Bad_Opcode }, 5447 { Bad_Opcode }, 5448 { Bad_Opcode }, 5449 /* e0 */ 5450 { Bad_Opcode }, 5451 { Bad_Opcode }, 5452 { Bad_Opcode }, 5453 { Bad_Opcode }, 5454 { Bad_Opcode }, 5455 { Bad_Opcode }, 5456 { Bad_Opcode }, 5457 { Bad_Opcode }, 5458 /* e8 */ 5459 { Bad_Opcode }, 5460 { Bad_Opcode }, 5461 { Bad_Opcode }, 5462 { Bad_Opcode }, 5463 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) }, 5464 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) }, 5465 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) }, 5466 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) }, 5467 /* f0 */ 5468 { Bad_Opcode }, 5469 { Bad_Opcode }, 5470 { Bad_Opcode }, 5471 { Bad_Opcode }, 5472 { Bad_Opcode }, 5473 { Bad_Opcode }, 5474 { Bad_Opcode }, 5475 { Bad_Opcode }, 5476 /* f8 */ 5477 { Bad_Opcode }, 5478 { Bad_Opcode }, 5479 { Bad_Opcode }, 5480 { Bad_Opcode }, 5481 { Bad_Opcode }, 5482 { Bad_Opcode }, 5483 { Bad_Opcode }, 5484 { Bad_Opcode }, 5485 }, 5486 /* XOP_09 */ 5487 { 5488 /* 00 */ 5489 { Bad_Opcode }, 5490 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) }, 5491 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) }, 5492 { Bad_Opcode }, 5493 { Bad_Opcode }, 5494 { Bad_Opcode }, 5495 { Bad_Opcode }, 5496 { Bad_Opcode }, 5497 /* 08 */ 5498 { Bad_Opcode }, 5499 { Bad_Opcode }, 5500 { Bad_Opcode }, 5501 { Bad_Opcode }, 5502 { Bad_Opcode }, 5503 { Bad_Opcode }, 5504 { Bad_Opcode }, 5505 { Bad_Opcode }, 5506 /* 10 */ 5507 { Bad_Opcode }, 5508 { Bad_Opcode }, 5509 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) }, 5510 { Bad_Opcode }, 5511 { Bad_Opcode }, 5512 { Bad_Opcode }, 5513 { Bad_Opcode }, 5514 { Bad_Opcode }, 5515 /* 18 */ 5516 { Bad_Opcode }, 5517 { Bad_Opcode }, 5518 { Bad_Opcode }, 5519 { Bad_Opcode }, 5520 { Bad_Opcode }, 5521 { Bad_Opcode }, 5522 { Bad_Opcode }, 5523 { Bad_Opcode }, 5524 /* 20 */ 5525 { Bad_Opcode }, 5526 { Bad_Opcode }, 5527 { Bad_Opcode }, 5528 { Bad_Opcode }, 5529 { Bad_Opcode }, 5530 { Bad_Opcode }, 5531 { Bad_Opcode }, 5532 { Bad_Opcode }, 5533 /* 28 */ 5534 { Bad_Opcode }, 5535 { Bad_Opcode }, 5536 { Bad_Opcode }, 5537 { Bad_Opcode }, 5538 { Bad_Opcode }, 5539 { Bad_Opcode }, 5540 { Bad_Opcode }, 5541 { Bad_Opcode }, 5542 /* 30 */ 5543 { Bad_Opcode }, 5544 { Bad_Opcode }, 5545 { Bad_Opcode }, 5546 { Bad_Opcode }, 5547 { Bad_Opcode }, 5548 { Bad_Opcode }, 5549 { Bad_Opcode }, 5550 { Bad_Opcode }, 5551 /* 38 */ 5552 { Bad_Opcode }, 5553 { Bad_Opcode }, 5554 { Bad_Opcode }, 5555 { Bad_Opcode }, 5556 { Bad_Opcode }, 5557 { Bad_Opcode }, 5558 { Bad_Opcode }, 5559 { Bad_Opcode }, 5560 /* 40 */ 5561 { Bad_Opcode }, 5562 { Bad_Opcode }, 5563 { Bad_Opcode }, 5564 { Bad_Opcode }, 5565 { Bad_Opcode }, 5566 { Bad_Opcode }, 5567 { Bad_Opcode }, 5568 { Bad_Opcode }, 5569 /* 48 */ 5570 { Bad_Opcode }, 5571 { Bad_Opcode }, 5572 { Bad_Opcode }, 5573 { Bad_Opcode }, 5574 { Bad_Opcode }, 5575 { Bad_Opcode }, 5576 { Bad_Opcode }, 5577 { Bad_Opcode }, 5578 /* 50 */ 5579 { Bad_Opcode }, 5580 { Bad_Opcode }, 5581 { Bad_Opcode }, 5582 { Bad_Opcode }, 5583 { Bad_Opcode }, 5584 { Bad_Opcode }, 5585 { Bad_Opcode }, 5586 { Bad_Opcode }, 5587 /* 58 */ 5588 { Bad_Opcode }, 5589 { Bad_Opcode }, 5590 { Bad_Opcode }, 5591 { Bad_Opcode }, 5592 { Bad_Opcode }, 5593 { Bad_Opcode }, 5594 { Bad_Opcode }, 5595 { Bad_Opcode }, 5596 /* 60 */ 5597 { Bad_Opcode }, 5598 { Bad_Opcode }, 5599 { Bad_Opcode }, 5600 { Bad_Opcode }, 5601 { Bad_Opcode }, 5602 { Bad_Opcode }, 5603 { Bad_Opcode }, 5604 { Bad_Opcode }, 5605 /* 68 */ 5606 { Bad_Opcode }, 5607 { Bad_Opcode }, 5608 { Bad_Opcode }, 5609 { Bad_Opcode }, 5610 { Bad_Opcode }, 5611 { Bad_Opcode }, 5612 { Bad_Opcode }, 5613 { Bad_Opcode }, 5614 /* 70 */ 5615 { Bad_Opcode }, 5616 { Bad_Opcode }, 5617 { Bad_Opcode }, 5618 { Bad_Opcode }, 5619 { Bad_Opcode }, 5620 { Bad_Opcode }, 5621 { Bad_Opcode }, 5622 { Bad_Opcode }, 5623 /* 78 */ 5624 { Bad_Opcode }, 5625 { Bad_Opcode }, 5626 { Bad_Opcode }, 5627 { Bad_Opcode }, 5628 { Bad_Opcode }, 5629 { Bad_Opcode }, 5630 { Bad_Opcode }, 5631 { Bad_Opcode }, 5632 /* 80 */ 5633 { VEX_W_TABLE (VEX_W_XOP_09_80) }, 5634 { VEX_W_TABLE (VEX_W_XOP_09_81) }, 5635 { VEX_W_TABLE (VEX_W_XOP_09_82) }, 5636 { VEX_W_TABLE (VEX_W_XOP_09_83) }, 5637 { Bad_Opcode }, 5638 { Bad_Opcode }, 5639 { Bad_Opcode }, 5640 { Bad_Opcode }, 5641 /* 88 */ 5642 { Bad_Opcode }, 5643 { Bad_Opcode }, 5644 { Bad_Opcode }, 5645 { Bad_Opcode }, 5646 { Bad_Opcode }, 5647 { Bad_Opcode }, 5648 { Bad_Opcode }, 5649 { Bad_Opcode }, 5650 /* 90 */ 5651 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) }, 5652 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) }, 5653 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) }, 5654 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) }, 5655 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) }, 5656 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) }, 5657 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) }, 5658 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) }, 5659 /* 98 */ 5660 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) }, 5661 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) }, 5662 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) }, 5663 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) }, 5664 { Bad_Opcode }, 5665 { Bad_Opcode }, 5666 { Bad_Opcode }, 5667 { Bad_Opcode }, 5668 /* a0 */ 5669 { Bad_Opcode }, 5670 { Bad_Opcode }, 5671 { Bad_Opcode }, 5672 { Bad_Opcode }, 5673 { Bad_Opcode }, 5674 { Bad_Opcode }, 5675 { Bad_Opcode }, 5676 { Bad_Opcode }, 5677 /* a8 */ 5678 { Bad_Opcode }, 5679 { Bad_Opcode }, 5680 { Bad_Opcode }, 5681 { Bad_Opcode }, 5682 { Bad_Opcode }, 5683 { Bad_Opcode }, 5684 { Bad_Opcode }, 5685 { Bad_Opcode }, 5686 /* b0 */ 5687 { Bad_Opcode }, 5688 { Bad_Opcode }, 5689 { Bad_Opcode }, 5690 { Bad_Opcode }, 5691 { Bad_Opcode }, 5692 { Bad_Opcode }, 5693 { Bad_Opcode }, 5694 { Bad_Opcode }, 5695 /* b8 */ 5696 { Bad_Opcode }, 5697 { Bad_Opcode }, 5698 { Bad_Opcode }, 5699 { Bad_Opcode }, 5700 { Bad_Opcode }, 5701 { Bad_Opcode }, 5702 { Bad_Opcode }, 5703 { Bad_Opcode }, 5704 /* c0 */ 5705 { Bad_Opcode }, 5706 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) }, 5707 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) }, 5708 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) }, 5709 { Bad_Opcode }, 5710 { Bad_Opcode }, 5711 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) }, 5712 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) }, 5713 /* c8 */ 5714 { Bad_Opcode }, 5715 { Bad_Opcode }, 5716 { Bad_Opcode }, 5717 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) }, 5718 { Bad_Opcode }, 5719 { Bad_Opcode }, 5720 { Bad_Opcode }, 5721 { Bad_Opcode }, 5722 /* d0 */ 5723 { Bad_Opcode }, 5724 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) }, 5725 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) }, 5726 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) }, 5727 { Bad_Opcode }, 5728 { Bad_Opcode }, 5729 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) }, 5730 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) }, 5731 /* d8 */ 5732 { Bad_Opcode }, 5733 { Bad_Opcode }, 5734 { Bad_Opcode }, 5735 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) }, 5736 { Bad_Opcode }, 5737 { Bad_Opcode }, 5738 { Bad_Opcode }, 5739 { Bad_Opcode }, 5740 /* e0 */ 5741 { Bad_Opcode }, 5742 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) }, 5743 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) }, 5744 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) }, 5745 { Bad_Opcode }, 5746 { Bad_Opcode }, 5747 { Bad_Opcode }, 5748 { Bad_Opcode }, 5749 /* e8 */ 5750 { Bad_Opcode }, 5751 { Bad_Opcode }, 5752 { Bad_Opcode }, 5753 { Bad_Opcode }, 5754 { Bad_Opcode }, 5755 { Bad_Opcode }, 5756 { Bad_Opcode }, 5757 { Bad_Opcode }, 5758 /* f0 */ 5759 { Bad_Opcode }, 5760 { Bad_Opcode }, 5761 { Bad_Opcode }, 5762 { Bad_Opcode }, 5763 { Bad_Opcode }, 5764 { Bad_Opcode }, 5765 { Bad_Opcode }, 5766 { Bad_Opcode }, 5767 /* f8 */ 5768 { Bad_Opcode }, 5769 { Bad_Opcode }, 5770 { Bad_Opcode }, 5771 { Bad_Opcode }, 5772 { Bad_Opcode }, 5773 { Bad_Opcode }, 5774 { Bad_Opcode }, 5775 { Bad_Opcode }, 5776 }, 5777 /* XOP_0A */ 5778 { 5779 /* 00 */ 5780 { Bad_Opcode }, 5781 { Bad_Opcode }, 5782 { Bad_Opcode }, 5783 { Bad_Opcode }, 5784 { Bad_Opcode }, 5785 { Bad_Opcode }, 5786 { Bad_Opcode }, 5787 { Bad_Opcode }, 5788 /* 08 */ 5789 { Bad_Opcode }, 5790 { Bad_Opcode }, 5791 { Bad_Opcode }, 5792 { Bad_Opcode }, 5793 { Bad_Opcode }, 5794 { Bad_Opcode }, 5795 { Bad_Opcode }, 5796 { Bad_Opcode }, 5797 /* 10 */ 5798 { "bextrS", { Gdq, Edq, Id }, 0 }, 5799 { Bad_Opcode }, 5800 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) }, 5801 { Bad_Opcode }, 5802 { Bad_Opcode }, 5803 { Bad_Opcode }, 5804 { Bad_Opcode }, 5805 { Bad_Opcode }, 5806 /* 18 */ 5807 { Bad_Opcode }, 5808 { Bad_Opcode }, 5809 { Bad_Opcode }, 5810 { Bad_Opcode }, 5811 { Bad_Opcode }, 5812 { Bad_Opcode }, 5813 { Bad_Opcode }, 5814 { Bad_Opcode }, 5815 /* 20 */ 5816 { Bad_Opcode }, 5817 { Bad_Opcode }, 5818 { Bad_Opcode }, 5819 { Bad_Opcode }, 5820 { Bad_Opcode }, 5821 { Bad_Opcode }, 5822 { Bad_Opcode }, 5823 { Bad_Opcode }, 5824 /* 28 */ 5825 { Bad_Opcode }, 5826 { Bad_Opcode }, 5827 { Bad_Opcode }, 5828 { Bad_Opcode }, 5829 { Bad_Opcode }, 5830 { Bad_Opcode }, 5831 { Bad_Opcode }, 5832 { Bad_Opcode }, 5833 /* 30 */ 5834 { Bad_Opcode }, 5835 { Bad_Opcode }, 5836 { Bad_Opcode }, 5837 { Bad_Opcode }, 5838 { Bad_Opcode }, 5839 { Bad_Opcode }, 5840 { Bad_Opcode }, 5841 { Bad_Opcode }, 5842 /* 38 */ 5843 { Bad_Opcode }, 5844 { Bad_Opcode }, 5845 { Bad_Opcode }, 5846 { Bad_Opcode }, 5847 { Bad_Opcode }, 5848 { Bad_Opcode }, 5849 { Bad_Opcode }, 5850 { Bad_Opcode }, 5851 /* 40 */ 5852 { Bad_Opcode }, 5853 { Bad_Opcode }, 5854 { Bad_Opcode }, 5855 { Bad_Opcode }, 5856 { Bad_Opcode }, 5857 { Bad_Opcode }, 5858 { Bad_Opcode }, 5859 { Bad_Opcode }, 5860 /* 48 */ 5861 { Bad_Opcode }, 5862 { Bad_Opcode }, 5863 { Bad_Opcode }, 5864 { Bad_Opcode }, 5865 { Bad_Opcode }, 5866 { Bad_Opcode }, 5867 { Bad_Opcode }, 5868 { Bad_Opcode }, 5869 /* 50 */ 5870 { Bad_Opcode }, 5871 { Bad_Opcode }, 5872 { Bad_Opcode }, 5873 { Bad_Opcode }, 5874 { Bad_Opcode }, 5875 { Bad_Opcode }, 5876 { Bad_Opcode }, 5877 { Bad_Opcode }, 5878 /* 58 */ 5879 { Bad_Opcode }, 5880 { Bad_Opcode }, 5881 { Bad_Opcode }, 5882 { Bad_Opcode }, 5883 { Bad_Opcode }, 5884 { Bad_Opcode }, 5885 { Bad_Opcode }, 5886 { Bad_Opcode }, 5887 /* 60 */ 5888 { Bad_Opcode }, 5889 { Bad_Opcode }, 5890 { Bad_Opcode }, 5891 { Bad_Opcode }, 5892 { Bad_Opcode }, 5893 { Bad_Opcode }, 5894 { Bad_Opcode }, 5895 { Bad_Opcode }, 5896 /* 68 */ 5897 { Bad_Opcode }, 5898 { Bad_Opcode }, 5899 { Bad_Opcode }, 5900 { Bad_Opcode }, 5901 { Bad_Opcode }, 5902 { Bad_Opcode }, 5903 { Bad_Opcode }, 5904 { Bad_Opcode }, 5905 /* 70 */ 5906 { Bad_Opcode }, 5907 { Bad_Opcode }, 5908 { Bad_Opcode }, 5909 { Bad_Opcode }, 5910 { Bad_Opcode }, 5911 { Bad_Opcode }, 5912 { Bad_Opcode }, 5913 { Bad_Opcode }, 5914 /* 78 */ 5915 { Bad_Opcode }, 5916 { Bad_Opcode }, 5917 { Bad_Opcode }, 5918 { Bad_Opcode }, 5919 { Bad_Opcode }, 5920 { Bad_Opcode }, 5921 { Bad_Opcode }, 5922 { Bad_Opcode }, 5923 /* 80 */ 5924 { Bad_Opcode }, 5925 { Bad_Opcode }, 5926 { Bad_Opcode }, 5927 { Bad_Opcode }, 5928 { Bad_Opcode }, 5929 { Bad_Opcode }, 5930 { Bad_Opcode }, 5931 { Bad_Opcode }, 5932 /* 88 */ 5933 { Bad_Opcode }, 5934 { Bad_Opcode }, 5935 { Bad_Opcode }, 5936 { Bad_Opcode }, 5937 { Bad_Opcode }, 5938 { Bad_Opcode }, 5939 { Bad_Opcode }, 5940 { Bad_Opcode }, 5941 /* 90 */ 5942 { Bad_Opcode }, 5943 { Bad_Opcode }, 5944 { Bad_Opcode }, 5945 { Bad_Opcode }, 5946 { Bad_Opcode }, 5947 { Bad_Opcode }, 5948 { Bad_Opcode }, 5949 { Bad_Opcode }, 5950 /* 98 */ 5951 { Bad_Opcode }, 5952 { Bad_Opcode }, 5953 { Bad_Opcode }, 5954 { Bad_Opcode }, 5955 { Bad_Opcode }, 5956 { Bad_Opcode }, 5957 { Bad_Opcode }, 5958 { Bad_Opcode }, 5959 /* a0 */ 5960 { Bad_Opcode }, 5961 { Bad_Opcode }, 5962 { Bad_Opcode }, 5963 { Bad_Opcode }, 5964 { Bad_Opcode }, 5965 { Bad_Opcode }, 5966 { Bad_Opcode }, 5967 { Bad_Opcode }, 5968 /* a8 */ 5969 { Bad_Opcode }, 5970 { Bad_Opcode }, 5971 { Bad_Opcode }, 5972 { Bad_Opcode }, 5973 { Bad_Opcode }, 5974 { Bad_Opcode }, 5975 { Bad_Opcode }, 5976 { Bad_Opcode }, 5977 /* b0 */ 5978 { Bad_Opcode }, 5979 { Bad_Opcode }, 5980 { Bad_Opcode }, 5981 { Bad_Opcode }, 5982 { Bad_Opcode }, 5983 { Bad_Opcode }, 5984 { Bad_Opcode }, 5985 { Bad_Opcode }, 5986 /* b8 */ 5987 { Bad_Opcode }, 5988 { Bad_Opcode }, 5989 { Bad_Opcode }, 5990 { Bad_Opcode }, 5991 { Bad_Opcode }, 5992 { Bad_Opcode }, 5993 { Bad_Opcode }, 5994 { Bad_Opcode }, 5995 /* c0 */ 5996 { Bad_Opcode }, 5997 { Bad_Opcode }, 5998 { Bad_Opcode }, 5999 { Bad_Opcode }, 6000 { Bad_Opcode }, 6001 { Bad_Opcode }, 6002 { Bad_Opcode }, 6003 { Bad_Opcode }, 6004 /* c8 */ 6005 { Bad_Opcode }, 6006 { Bad_Opcode }, 6007 { Bad_Opcode }, 6008 { Bad_Opcode }, 6009 { Bad_Opcode }, 6010 { Bad_Opcode }, 6011 { Bad_Opcode }, 6012 { Bad_Opcode }, 6013 /* d0 */ 6014 { Bad_Opcode }, 6015 { Bad_Opcode }, 6016 { Bad_Opcode }, 6017 { Bad_Opcode }, 6018 { Bad_Opcode }, 6019 { Bad_Opcode }, 6020 { Bad_Opcode }, 6021 { Bad_Opcode }, 6022 /* d8 */ 6023 { Bad_Opcode }, 6024 { Bad_Opcode }, 6025 { Bad_Opcode }, 6026 { Bad_Opcode }, 6027 { Bad_Opcode }, 6028 { Bad_Opcode }, 6029 { Bad_Opcode }, 6030 { Bad_Opcode }, 6031 /* e0 */ 6032 { Bad_Opcode }, 6033 { Bad_Opcode }, 6034 { Bad_Opcode }, 6035 { Bad_Opcode }, 6036 { Bad_Opcode }, 6037 { Bad_Opcode }, 6038 { Bad_Opcode }, 6039 { Bad_Opcode }, 6040 /* e8 */ 6041 { Bad_Opcode }, 6042 { Bad_Opcode }, 6043 { Bad_Opcode }, 6044 { Bad_Opcode }, 6045 { Bad_Opcode }, 6046 { Bad_Opcode }, 6047 { Bad_Opcode }, 6048 { Bad_Opcode }, 6049 /* f0 */ 6050 { Bad_Opcode }, 6051 { Bad_Opcode }, 6052 { Bad_Opcode }, 6053 { Bad_Opcode }, 6054 { Bad_Opcode }, 6055 { Bad_Opcode }, 6056 { Bad_Opcode }, 6057 { Bad_Opcode }, 6058 /* f8 */ 6059 { Bad_Opcode }, 6060 { Bad_Opcode }, 6061 { Bad_Opcode }, 6062 { Bad_Opcode }, 6063 { Bad_Opcode }, 6064 { Bad_Opcode }, 6065 { Bad_Opcode }, 6066 { Bad_Opcode }, 6067 }, 6068 }; 6069 6070 static const struct dis386 vex_table[][256] = { 6071 /* VEX_0F */ 6072 { 6073 /* 00 */ 6074 { Bad_Opcode }, 6075 { Bad_Opcode }, 6076 { Bad_Opcode }, 6077 { Bad_Opcode }, 6078 { Bad_Opcode }, 6079 { Bad_Opcode }, 6080 { Bad_Opcode }, 6081 { Bad_Opcode }, 6082 /* 08 */ 6083 { Bad_Opcode }, 6084 { Bad_Opcode }, 6085 { Bad_Opcode }, 6086 { Bad_Opcode }, 6087 { Bad_Opcode }, 6088 { Bad_Opcode }, 6089 { Bad_Opcode }, 6090 { Bad_Opcode }, 6091 /* 10 */ 6092 { PREFIX_TABLE (PREFIX_0F10) }, 6093 { PREFIX_TABLE (PREFIX_0F11) }, 6094 { PREFIX_TABLE (PREFIX_VEX_0F12) }, 6095 { VEX_LEN_TABLE (VEX_LEN_0F13) }, 6096 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6097 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6098 { PREFIX_TABLE (PREFIX_VEX_0F16) }, 6099 { VEX_LEN_TABLE (VEX_LEN_0F17) }, 6100 /* 18 */ 6101 { Bad_Opcode }, 6102 { Bad_Opcode }, 6103 { Bad_Opcode }, 6104 { Bad_Opcode }, 6105 { Bad_Opcode }, 6106 { Bad_Opcode }, 6107 { Bad_Opcode }, 6108 { Bad_Opcode }, 6109 /* 20 */ 6110 { Bad_Opcode }, 6111 { Bad_Opcode }, 6112 { Bad_Opcode }, 6113 { Bad_Opcode }, 6114 { Bad_Opcode }, 6115 { Bad_Opcode }, 6116 { Bad_Opcode }, 6117 { Bad_Opcode }, 6118 /* 28 */ 6119 { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, 6120 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, 6121 { PREFIX_TABLE (PREFIX_VEX_0F2A) }, 6122 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, 6123 { PREFIX_TABLE (PREFIX_VEX_0F2C) }, 6124 { PREFIX_TABLE (PREFIX_VEX_0F2D) }, 6125 { PREFIX_TABLE (PREFIX_0F2E) }, 6126 { PREFIX_TABLE (PREFIX_0F2F) }, 6127 /* 30 */ 6128 { Bad_Opcode }, 6129 { Bad_Opcode }, 6130 { Bad_Opcode }, 6131 { Bad_Opcode }, 6132 { Bad_Opcode }, 6133 { Bad_Opcode }, 6134 { Bad_Opcode }, 6135 { Bad_Opcode }, 6136 /* 38 */ 6137 { Bad_Opcode }, 6138 { Bad_Opcode }, 6139 { Bad_Opcode }, 6140 { Bad_Opcode }, 6141 { Bad_Opcode }, 6142 { Bad_Opcode }, 6143 { Bad_Opcode }, 6144 { Bad_Opcode }, 6145 /* 40 */ 6146 { Bad_Opcode }, 6147 { VEX_LEN_TABLE (VEX_LEN_0F41) }, 6148 { VEX_LEN_TABLE (VEX_LEN_0F42) }, 6149 { Bad_Opcode }, 6150 { VEX_LEN_TABLE (VEX_LEN_0F44) }, 6151 { VEX_LEN_TABLE (VEX_LEN_0F45) }, 6152 { VEX_LEN_TABLE (VEX_LEN_0F46) }, 6153 { VEX_LEN_TABLE (VEX_LEN_0F47) }, 6154 /* 48 */ 6155 { Bad_Opcode }, 6156 { Bad_Opcode }, 6157 { VEX_LEN_TABLE (VEX_LEN_0F4A) }, 6158 { VEX_LEN_TABLE (VEX_LEN_0F4B) }, 6159 { Bad_Opcode }, 6160 { Bad_Opcode }, 6161 { Bad_Opcode }, 6162 { Bad_Opcode }, 6163 /* 50 */ 6164 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE }, 6165 { PREFIX_TABLE (PREFIX_0F51) }, 6166 { PREFIX_TABLE (PREFIX_0F52) }, 6167 { PREFIX_TABLE (PREFIX_0F53) }, 6168 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6169 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6170 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6171 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6172 /* 58 */ 6173 { PREFIX_TABLE (PREFIX_0F58) }, 6174 { PREFIX_TABLE (PREFIX_0F59) }, 6175 { PREFIX_TABLE (PREFIX_0F5A) }, 6176 { PREFIX_TABLE (PREFIX_0F5B) }, 6177 { PREFIX_TABLE (PREFIX_0F5C) }, 6178 { PREFIX_TABLE (PREFIX_0F5D) }, 6179 { PREFIX_TABLE (PREFIX_0F5E) }, 6180 { PREFIX_TABLE (PREFIX_0F5F) }, 6181 /* 60 */ 6182 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, 6183 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, 6184 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, 6185 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, 6186 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, 6187 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, 6188 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, 6189 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, 6190 /* 68 */ 6191 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, 6192 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, 6193 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, 6194 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, 6195 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, 6196 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, 6197 { VEX_LEN_TABLE (VEX_LEN_0F6E) }, 6198 { PREFIX_TABLE (PREFIX_VEX_0F6F) }, 6199 /* 70 */ 6200 { PREFIX_TABLE (PREFIX_VEX_0F70) }, 6201 { REG_TABLE (REG_VEX_0F71) }, 6202 { REG_TABLE (REG_VEX_0F72) }, 6203 { REG_TABLE (REG_VEX_0F73) }, 6204 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, 6205 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, 6206 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, 6207 { VEX_LEN_TABLE (VEX_LEN_0F77) }, 6208 /* 78 */ 6209 { Bad_Opcode }, 6210 { Bad_Opcode }, 6211 { Bad_Opcode }, 6212 { Bad_Opcode }, 6213 { PREFIX_TABLE (PREFIX_0F7C) }, 6214 { PREFIX_TABLE (PREFIX_0F7D) }, 6215 { PREFIX_TABLE (PREFIX_VEX_0F7E) }, 6216 { PREFIX_TABLE (PREFIX_VEX_0F7F) }, 6217 /* 80 */ 6218 { Bad_Opcode }, 6219 { Bad_Opcode }, 6220 { Bad_Opcode }, 6221 { Bad_Opcode }, 6222 { Bad_Opcode }, 6223 { Bad_Opcode }, 6224 { Bad_Opcode }, 6225 { Bad_Opcode }, 6226 /* 88 */ 6227 { Bad_Opcode }, 6228 { Bad_Opcode }, 6229 { Bad_Opcode }, 6230 { Bad_Opcode }, 6231 { Bad_Opcode }, 6232 { Bad_Opcode }, 6233 { Bad_Opcode }, 6234 { Bad_Opcode }, 6235 /* 90 */ 6236 { VEX_LEN_TABLE (VEX_LEN_0F90) }, 6237 { VEX_LEN_TABLE (VEX_LEN_0F91) }, 6238 { VEX_LEN_TABLE (VEX_LEN_0F92) }, 6239 { VEX_LEN_TABLE (VEX_LEN_0F93) }, 6240 { Bad_Opcode }, 6241 { Bad_Opcode }, 6242 { Bad_Opcode }, 6243 { Bad_Opcode }, 6244 /* 98 */ 6245 { VEX_LEN_TABLE (VEX_LEN_0F98) }, 6246 { VEX_LEN_TABLE (VEX_LEN_0F99) }, 6247 { Bad_Opcode }, 6248 { Bad_Opcode }, 6249 { Bad_Opcode }, 6250 { Bad_Opcode }, 6251 { Bad_Opcode }, 6252 { Bad_Opcode }, 6253 /* a0 */ 6254 { Bad_Opcode }, 6255 { Bad_Opcode }, 6256 { Bad_Opcode }, 6257 { Bad_Opcode }, 6258 { Bad_Opcode }, 6259 { Bad_Opcode }, 6260 { Bad_Opcode }, 6261 { Bad_Opcode }, 6262 /* a8 */ 6263 { Bad_Opcode }, 6264 { Bad_Opcode }, 6265 { Bad_Opcode }, 6266 { Bad_Opcode }, 6267 { Bad_Opcode }, 6268 { Bad_Opcode }, 6269 { REG_TABLE (REG_VEX_0FAE) }, 6270 { Bad_Opcode }, 6271 /* b0 */ 6272 { Bad_Opcode }, 6273 { Bad_Opcode }, 6274 { Bad_Opcode }, 6275 { Bad_Opcode }, 6276 { Bad_Opcode }, 6277 { Bad_Opcode }, 6278 { Bad_Opcode }, 6279 { Bad_Opcode }, 6280 /* b8 */ 6281 { Bad_Opcode }, 6282 { Bad_Opcode }, 6283 { Bad_Opcode }, 6284 { Bad_Opcode }, 6285 { Bad_Opcode }, 6286 { Bad_Opcode }, 6287 { Bad_Opcode }, 6288 { Bad_Opcode }, 6289 /* c0 */ 6290 { Bad_Opcode }, 6291 { Bad_Opcode }, 6292 { PREFIX_TABLE (PREFIX_0FC2) }, 6293 { Bad_Opcode }, 6294 { VEX_LEN_TABLE (VEX_LEN_0FC4) }, 6295 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA }, 6296 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, 6297 { Bad_Opcode }, 6298 /* c8 */ 6299 { Bad_Opcode }, 6300 { Bad_Opcode }, 6301 { Bad_Opcode }, 6302 { Bad_Opcode }, 6303 { Bad_Opcode }, 6304 { Bad_Opcode }, 6305 { Bad_Opcode }, 6306 { Bad_Opcode }, 6307 /* d0 */ 6308 { PREFIX_TABLE (PREFIX_0FD0) }, 6309 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6310 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, 6311 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, 6312 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, 6313 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, 6314 { VEX_LEN_TABLE (VEX_LEN_0FD6) }, 6315 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA }, 6316 /* d8 */ 6317 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, 6318 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, 6319 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, 6320 { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, 6321 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, 6322 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, 6323 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, 6324 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, 6325 /* e0 */ 6326 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, 6327 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6328 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, 6329 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, 6330 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, 6331 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, 6332 { PREFIX_TABLE (PREFIX_0FE6) }, 6333 { "vmovntdq", { Mx, XM }, PREFIX_DATA }, 6334 /* e8 */ 6335 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, 6336 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6337 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, 6338 { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, 6339 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, 6340 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, 6341 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, 6342 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, 6343 /* f0 */ 6344 { PREFIX_TABLE (PREFIX_0FF0) }, 6345 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6346 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, 6347 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, 6348 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, 6349 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, 6350 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, 6351 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA }, 6352 /* f8 */ 6353 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, 6354 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, 6355 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, 6356 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, 6357 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, 6358 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, 6359 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, 6360 { Bad_Opcode }, 6361 }, 6362 /* VEX_0F38 */ 6363 { 6364 /* 00 */ 6365 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, 6366 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, 6367 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, 6368 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, 6369 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6370 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, 6371 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, 6372 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6373 /* 08 */ 6374 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, 6375 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, 6376 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, 6377 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, 6378 { VEX_W_TABLE (VEX_W_0F380C) }, 6379 { VEX_W_TABLE (VEX_W_0F380D) }, 6380 { VEX_W_TABLE (VEX_W_0F380E) }, 6381 { VEX_W_TABLE (VEX_W_0F380F) }, 6382 /* 10 */ 6383 { Bad_Opcode }, 6384 { Bad_Opcode }, 6385 { Bad_Opcode }, 6386 { VEX_W_TABLE (VEX_W_0F3813) }, 6387 { Bad_Opcode }, 6388 { Bad_Opcode }, 6389 { VEX_LEN_TABLE (VEX_LEN_0F3816) }, 6390 { "vptest", { XM, EXx }, PREFIX_DATA }, 6391 /* 18 */ 6392 { VEX_W_TABLE (VEX_W_0F3818) }, 6393 { VEX_LEN_TABLE (VEX_LEN_0F3819) }, 6394 { VEX_LEN_TABLE (VEX_LEN_0F381A) }, 6395 { Bad_Opcode }, 6396 { "vpabsb", { XM, EXx }, PREFIX_DATA }, 6397 { "vpabsw", { XM, EXx }, PREFIX_DATA }, 6398 { "vpabsd", { XM, EXx }, PREFIX_DATA }, 6399 { Bad_Opcode }, 6400 /* 20 */ 6401 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, 6402 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, 6403 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, 6404 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, 6405 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, 6406 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, 6407 { Bad_Opcode }, 6408 { Bad_Opcode }, 6409 /* 28 */ 6410 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, 6411 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, 6412 { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, 6413 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, 6414 { VEX_W_TABLE (VEX_W_0F382C) }, 6415 { VEX_W_TABLE (VEX_W_0F382D) }, 6416 { VEX_W_TABLE (VEX_W_0F382E) }, 6417 { VEX_W_TABLE (VEX_W_0F382F) }, 6418 /* 30 */ 6419 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, 6420 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, 6421 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, 6422 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, 6423 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, 6424 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, 6425 { VEX_LEN_TABLE (VEX_LEN_0F3836) }, 6426 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, 6427 /* 38 */ 6428 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, 6429 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, 6430 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, 6431 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, 6432 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, 6433 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, 6434 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, 6435 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, 6436 /* 40 */ 6437 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, 6438 { VEX_LEN_TABLE (VEX_LEN_0F3841) }, 6439 { Bad_Opcode }, 6440 { Bad_Opcode }, 6441 { Bad_Opcode }, 6442 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, 6443 { VEX_W_TABLE (VEX_W_0F3846) }, 6444 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, 6445 /* 48 */ 6446 { Bad_Opcode }, 6447 { X86_64_TABLE (X86_64_VEX_0F3849) }, 6448 { Bad_Opcode }, 6449 { X86_64_TABLE (X86_64_VEX_0F384B) }, 6450 { Bad_Opcode }, 6451 { Bad_Opcode }, 6452 { Bad_Opcode }, 6453 { Bad_Opcode }, 6454 /* 50 */ 6455 { VEX_W_TABLE (VEX_W_0F3850) }, 6456 { VEX_W_TABLE (VEX_W_0F3851) }, 6457 { VEX_W_TABLE (VEX_W_0F3852) }, 6458 { VEX_W_TABLE (VEX_W_0F3853) }, 6459 { Bad_Opcode }, 6460 { Bad_Opcode }, 6461 { Bad_Opcode }, 6462 { Bad_Opcode }, 6463 /* 58 */ 6464 { VEX_W_TABLE (VEX_W_0F3858) }, 6465 { VEX_W_TABLE (VEX_W_0F3859) }, 6466 { VEX_LEN_TABLE (VEX_LEN_0F385A) }, 6467 { Bad_Opcode }, 6468 { X86_64_TABLE (X86_64_VEX_0F385C) }, 6469 { Bad_Opcode }, 6470 { X86_64_TABLE (X86_64_VEX_0F385E) }, 6471 { Bad_Opcode }, 6472 /* 60 */ 6473 { Bad_Opcode }, 6474 { Bad_Opcode }, 6475 { Bad_Opcode }, 6476 { Bad_Opcode }, 6477 { Bad_Opcode }, 6478 { Bad_Opcode }, 6479 { Bad_Opcode }, 6480 { Bad_Opcode }, 6481 /* 68 */ 6482 { Bad_Opcode }, 6483 { Bad_Opcode }, 6484 { Bad_Opcode }, 6485 { Bad_Opcode }, 6486 { X86_64_TABLE (X86_64_VEX_0F386C) }, 6487 { Bad_Opcode }, 6488 { Bad_Opcode }, 6489 { Bad_Opcode }, 6490 /* 70 */ 6491 { Bad_Opcode }, 6492 { Bad_Opcode }, 6493 { PREFIX_TABLE (PREFIX_VEX_0F3872) }, 6494 { Bad_Opcode }, 6495 { Bad_Opcode }, 6496 { Bad_Opcode }, 6497 { Bad_Opcode }, 6498 { Bad_Opcode }, 6499 /* 78 */ 6500 { VEX_W_TABLE (VEX_W_0F3878) }, 6501 { VEX_W_TABLE (VEX_W_0F3879) }, 6502 { Bad_Opcode }, 6503 { Bad_Opcode }, 6504 { Bad_Opcode }, 6505 { Bad_Opcode }, 6506 { Bad_Opcode }, 6507 { Bad_Opcode }, 6508 /* 80 */ 6509 { Bad_Opcode }, 6510 { Bad_Opcode }, 6511 { Bad_Opcode }, 6512 { Bad_Opcode }, 6513 { Bad_Opcode }, 6514 { Bad_Opcode }, 6515 { Bad_Opcode }, 6516 { Bad_Opcode }, 6517 /* 88 */ 6518 { Bad_Opcode }, 6519 { Bad_Opcode }, 6520 { Bad_Opcode }, 6521 { Bad_Opcode }, 6522 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, 6523 { Bad_Opcode }, 6524 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, 6525 { Bad_Opcode }, 6526 /* 90 */ 6527 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, 6528 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, 6529 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, 6530 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, 6531 { Bad_Opcode }, 6532 { Bad_Opcode }, 6533 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6534 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6535 /* 98 */ 6536 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6537 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6538 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6539 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6540 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6541 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6542 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6543 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6544 /* a0 */ 6545 { Bad_Opcode }, 6546 { Bad_Opcode }, 6547 { Bad_Opcode }, 6548 { Bad_Opcode }, 6549 { Bad_Opcode }, 6550 { Bad_Opcode }, 6551 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6552 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6553 /* a8 */ 6554 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6555 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6556 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6557 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6558 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6559 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6560 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6561 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6562 /* b0 */ 6563 { VEX_W_TABLE (VEX_W_0F38B0) }, 6564 { VEX_W_TABLE (VEX_W_0F38B1) }, 6565 { Bad_Opcode }, 6566 { Bad_Opcode }, 6567 { VEX_W_TABLE (VEX_W_0F38B4) }, 6568 { VEX_W_TABLE (VEX_W_0F38B5) }, 6569 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6570 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6571 /* b8 */ 6572 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6573 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6574 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6575 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6576 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6577 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6578 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6579 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6580 /* c0 */ 6581 { Bad_Opcode }, 6582 { Bad_Opcode }, 6583 { Bad_Opcode }, 6584 { Bad_Opcode }, 6585 { Bad_Opcode }, 6586 { Bad_Opcode }, 6587 { Bad_Opcode }, 6588 { Bad_Opcode }, 6589 /* c8 */ 6590 { Bad_Opcode }, 6591 { Bad_Opcode }, 6592 { Bad_Opcode }, 6593 { PREFIX_TABLE (PREFIX_VEX_0F38CB) }, 6594 { PREFIX_TABLE (PREFIX_VEX_0F38CC) }, 6595 { PREFIX_TABLE (PREFIX_VEX_0F38CD) }, 6596 { Bad_Opcode }, 6597 { VEX_W_TABLE (VEX_W_0F38CF) }, 6598 /* d0 */ 6599 { Bad_Opcode }, 6600 { Bad_Opcode }, 6601 { VEX_W_TABLE (VEX_W_0F38D2) }, 6602 { VEX_W_TABLE (VEX_W_0F38D3) }, 6603 { Bad_Opcode }, 6604 { Bad_Opcode }, 6605 { Bad_Opcode }, 6606 { Bad_Opcode }, 6607 /* d8 */ 6608 { Bad_Opcode }, 6609 { Bad_Opcode }, 6610 { VEX_W_TABLE (VEX_W_0F38DA) }, 6611 { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, 6612 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, 6613 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, 6614 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, 6615 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, 6616 /* e0 */ 6617 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6618 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6619 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6620 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6621 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6622 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6623 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6624 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6625 /* e8 */ 6626 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6627 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6628 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6629 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6630 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6631 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6632 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6633 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6634 /* f0 */ 6635 { Bad_Opcode }, 6636 { Bad_Opcode }, 6637 { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, 6638 { VEX_LEN_TABLE (VEX_LEN_0F38F3) }, 6639 { Bad_Opcode }, 6640 { VEX_LEN_TABLE (VEX_LEN_0F38F5) }, 6641 { VEX_LEN_TABLE (VEX_LEN_0F38F6) }, 6642 { VEX_LEN_TABLE (VEX_LEN_0F38F7) }, 6643 /* f8 */ 6644 { Bad_Opcode }, 6645 { Bad_Opcode }, 6646 { Bad_Opcode }, 6647 { Bad_Opcode }, 6648 { Bad_Opcode }, 6649 { Bad_Opcode }, 6650 { Bad_Opcode }, 6651 { Bad_Opcode }, 6652 }, 6653 /* VEX_0F3A */ 6654 { 6655 /* 00 */ 6656 { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, 6657 { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, 6658 { VEX_W_TABLE (VEX_W_0F3A02) }, 6659 { Bad_Opcode }, 6660 { VEX_W_TABLE (VEX_W_0F3A04) }, 6661 { VEX_W_TABLE (VEX_W_0F3A05) }, 6662 { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, 6663 { Bad_Opcode }, 6664 /* 08 */ 6665 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, 6666 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, 6667 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA }, 6668 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA }, 6669 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6670 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6671 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6672 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6673 /* 10 */ 6674 { Bad_Opcode }, 6675 { Bad_Opcode }, 6676 { Bad_Opcode }, 6677 { Bad_Opcode }, 6678 { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, 6679 { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, 6680 { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, 6681 { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, 6682 /* 18 */ 6683 { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, 6684 { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, 6685 { Bad_Opcode }, 6686 { Bad_Opcode }, 6687 { Bad_Opcode }, 6688 { VEX_W_TABLE (VEX_W_0F3A1D) }, 6689 { Bad_Opcode }, 6690 { Bad_Opcode }, 6691 /* 20 */ 6692 { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, 6693 { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, 6694 { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, 6695 { Bad_Opcode }, 6696 { Bad_Opcode }, 6697 { Bad_Opcode }, 6698 { Bad_Opcode }, 6699 { Bad_Opcode }, 6700 /* 28 */ 6701 { Bad_Opcode }, 6702 { Bad_Opcode }, 6703 { Bad_Opcode }, 6704 { Bad_Opcode }, 6705 { Bad_Opcode }, 6706 { Bad_Opcode }, 6707 { Bad_Opcode }, 6708 { Bad_Opcode }, 6709 /* 30 */ 6710 { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, 6711 { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, 6712 { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, 6713 { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, 6714 { Bad_Opcode }, 6715 { Bad_Opcode }, 6716 { Bad_Opcode }, 6717 { Bad_Opcode }, 6718 /* 38 */ 6719 { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, 6720 { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, 6721 { Bad_Opcode }, 6722 { Bad_Opcode }, 6723 { Bad_Opcode }, 6724 { Bad_Opcode }, 6725 { Bad_Opcode }, 6726 { Bad_Opcode }, 6727 /* 40 */ 6728 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6729 { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, 6730 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6731 { Bad_Opcode }, 6732 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, 6733 { Bad_Opcode }, 6734 { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, 6735 { Bad_Opcode }, 6736 /* 48 */ 6737 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, 6738 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, 6739 { VEX_W_TABLE (VEX_W_0F3A4A) }, 6740 { VEX_W_TABLE (VEX_W_0F3A4B) }, 6741 { VEX_W_TABLE (VEX_W_0F3A4C) }, 6742 { Bad_Opcode }, 6743 { Bad_Opcode }, 6744 { Bad_Opcode }, 6745 /* 50 */ 6746 { Bad_Opcode }, 6747 { Bad_Opcode }, 6748 { Bad_Opcode }, 6749 { Bad_Opcode }, 6750 { Bad_Opcode }, 6751 { Bad_Opcode }, 6752 { Bad_Opcode }, 6753 { Bad_Opcode }, 6754 /* 58 */ 6755 { Bad_Opcode }, 6756 { Bad_Opcode }, 6757 { Bad_Opcode }, 6758 { Bad_Opcode }, 6759 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6760 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6761 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6762 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6763 /* 60 */ 6764 { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, 6765 { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, 6766 { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, 6767 { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, 6768 { Bad_Opcode }, 6769 { Bad_Opcode }, 6770 { Bad_Opcode }, 6771 { Bad_Opcode }, 6772 /* 68 */ 6773 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6774 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6775 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6776 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6777 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6778 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6779 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6780 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6781 /* 70 */ 6782 { Bad_Opcode }, 6783 { Bad_Opcode }, 6784 { Bad_Opcode }, 6785 { Bad_Opcode }, 6786 { Bad_Opcode }, 6787 { Bad_Opcode }, 6788 { Bad_Opcode }, 6789 { Bad_Opcode }, 6790 /* 78 */ 6791 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6792 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6793 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6794 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6795 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6796 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6797 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6798 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6799 /* 80 */ 6800 { Bad_Opcode }, 6801 { Bad_Opcode }, 6802 { Bad_Opcode }, 6803 { Bad_Opcode }, 6804 { Bad_Opcode }, 6805 { Bad_Opcode }, 6806 { Bad_Opcode }, 6807 { Bad_Opcode }, 6808 /* 88 */ 6809 { Bad_Opcode }, 6810 { Bad_Opcode }, 6811 { Bad_Opcode }, 6812 { Bad_Opcode }, 6813 { Bad_Opcode }, 6814 { Bad_Opcode }, 6815 { Bad_Opcode }, 6816 { Bad_Opcode }, 6817 /* 90 */ 6818 { Bad_Opcode }, 6819 { Bad_Opcode }, 6820 { Bad_Opcode }, 6821 { Bad_Opcode }, 6822 { Bad_Opcode }, 6823 { Bad_Opcode }, 6824 { Bad_Opcode }, 6825 { Bad_Opcode }, 6826 /* 98 */ 6827 { Bad_Opcode }, 6828 { Bad_Opcode }, 6829 { Bad_Opcode }, 6830 { Bad_Opcode }, 6831 { Bad_Opcode }, 6832 { Bad_Opcode }, 6833 { Bad_Opcode }, 6834 { Bad_Opcode }, 6835 /* a0 */ 6836 { Bad_Opcode }, 6837 { Bad_Opcode }, 6838 { Bad_Opcode }, 6839 { Bad_Opcode }, 6840 { Bad_Opcode }, 6841 { Bad_Opcode }, 6842 { Bad_Opcode }, 6843 { Bad_Opcode }, 6844 /* a8 */ 6845 { Bad_Opcode }, 6846 { Bad_Opcode }, 6847 { Bad_Opcode }, 6848 { Bad_Opcode }, 6849 { Bad_Opcode }, 6850 { Bad_Opcode }, 6851 { Bad_Opcode }, 6852 { Bad_Opcode }, 6853 /* b0 */ 6854 { Bad_Opcode }, 6855 { Bad_Opcode }, 6856 { Bad_Opcode }, 6857 { Bad_Opcode }, 6858 { Bad_Opcode }, 6859 { Bad_Opcode }, 6860 { Bad_Opcode }, 6861 { Bad_Opcode }, 6862 /* b8 */ 6863 { Bad_Opcode }, 6864 { Bad_Opcode }, 6865 { Bad_Opcode }, 6866 { Bad_Opcode }, 6867 { Bad_Opcode }, 6868 { Bad_Opcode }, 6869 { Bad_Opcode }, 6870 { Bad_Opcode }, 6871 /* c0 */ 6872 { Bad_Opcode }, 6873 { Bad_Opcode }, 6874 { Bad_Opcode }, 6875 { Bad_Opcode }, 6876 { Bad_Opcode }, 6877 { Bad_Opcode }, 6878 { Bad_Opcode }, 6879 { Bad_Opcode }, 6880 /* c8 */ 6881 { Bad_Opcode }, 6882 { Bad_Opcode }, 6883 { Bad_Opcode }, 6884 { Bad_Opcode }, 6885 { Bad_Opcode }, 6886 { Bad_Opcode }, 6887 { VEX_W_TABLE (VEX_W_0F3ACE) }, 6888 { VEX_W_TABLE (VEX_W_0F3ACF) }, 6889 /* d0 */ 6890 { Bad_Opcode }, 6891 { Bad_Opcode }, 6892 { Bad_Opcode }, 6893 { Bad_Opcode }, 6894 { Bad_Opcode }, 6895 { Bad_Opcode }, 6896 { Bad_Opcode }, 6897 { Bad_Opcode }, 6898 /* d8 */ 6899 { Bad_Opcode }, 6900 { Bad_Opcode }, 6901 { Bad_Opcode }, 6902 { Bad_Opcode }, 6903 { Bad_Opcode }, 6904 { Bad_Opcode }, 6905 { VEX_W_TABLE (VEX_W_0F3ADE) }, 6906 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, 6907 /* e0 */ 6908 { Bad_Opcode }, 6909 { Bad_Opcode }, 6910 { Bad_Opcode }, 6911 { Bad_Opcode }, 6912 { Bad_Opcode }, 6913 { Bad_Opcode }, 6914 { Bad_Opcode }, 6915 { Bad_Opcode }, 6916 /* e8 */ 6917 { Bad_Opcode }, 6918 { Bad_Opcode }, 6919 { Bad_Opcode }, 6920 { Bad_Opcode }, 6921 { Bad_Opcode }, 6922 { Bad_Opcode }, 6923 { Bad_Opcode }, 6924 { Bad_Opcode }, 6925 /* f0 */ 6926 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, 6927 { Bad_Opcode }, 6928 { Bad_Opcode }, 6929 { Bad_Opcode }, 6930 { Bad_Opcode }, 6931 { Bad_Opcode }, 6932 { Bad_Opcode }, 6933 { Bad_Opcode }, 6934 /* f8 */ 6935 { Bad_Opcode }, 6936 { Bad_Opcode }, 6937 { Bad_Opcode }, 6938 { Bad_Opcode }, 6939 { Bad_Opcode }, 6940 { Bad_Opcode }, 6941 { Bad_Opcode }, 6942 { Bad_Opcode }, 6943 }, 6944 }; 6945 6946 #include "i386-dis-evex.h" 6947 6948 static const struct dis386 vex_len_table[][2] = { 6949 /* VEX_LEN_0F12_P_0 */ 6950 { 6951 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 6952 }, 6953 6954 /* VEX_LEN_0F12_P_2 */ 6955 { 6956 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, 6957 }, 6958 6959 /* VEX_LEN_0F13 */ 6960 { 6961 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE }, 6962 }, 6963 6964 /* VEX_LEN_0F16_P_0 */ 6965 { 6966 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 6967 }, 6968 6969 /* VEX_LEN_0F16_P_2 */ 6970 { 6971 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, 6972 }, 6973 6974 /* VEX_LEN_0F17 */ 6975 { 6976 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE }, 6977 }, 6978 6979 /* VEX_LEN_0F41 */ 6980 { 6981 { Bad_Opcode }, 6982 { VEX_W_TABLE (VEX_W_0F41_L_1) }, 6983 }, 6984 6985 /* VEX_LEN_0F42 */ 6986 { 6987 { Bad_Opcode }, 6988 { VEX_W_TABLE (VEX_W_0F42_L_1) }, 6989 }, 6990 6991 /* VEX_LEN_0F44 */ 6992 { 6993 { VEX_W_TABLE (VEX_W_0F44_L_0) }, 6994 }, 6995 6996 /* VEX_LEN_0F45 */ 6997 { 6998 { Bad_Opcode }, 6999 { VEX_W_TABLE (VEX_W_0F45_L_1) }, 7000 }, 7001 7002 /* VEX_LEN_0F46 */ 7003 { 7004 { Bad_Opcode }, 7005 { VEX_W_TABLE (VEX_W_0F46_L_1) }, 7006 }, 7007 7008 /* VEX_LEN_0F47 */ 7009 { 7010 { Bad_Opcode }, 7011 { VEX_W_TABLE (VEX_W_0F47_L_1) }, 7012 }, 7013 7014 /* VEX_LEN_0F4A */ 7015 { 7016 { Bad_Opcode }, 7017 { VEX_W_TABLE (VEX_W_0F4A_L_1) }, 7018 }, 7019 7020 /* VEX_LEN_0F4B */ 7021 { 7022 { Bad_Opcode }, 7023 { VEX_W_TABLE (VEX_W_0F4B_L_1) }, 7024 }, 7025 7026 /* VEX_LEN_0F6E */ 7027 { 7028 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA }, 7029 }, 7030 7031 /* VEX_LEN_0F77 */ 7032 { 7033 { "vzeroupper", { XX }, 0 }, 7034 { "vzeroall", { XX }, 0 }, 7035 }, 7036 7037 /* VEX_LEN_0F7E_P_1 */ 7038 { 7039 { "%XEvmovqY", { XMScalar, EXq }, 0 }, 7040 }, 7041 7042 /* VEX_LEN_0F7E_P_2 */ 7043 { 7044 { "%XEvmovK", { Edq, XMScalar }, 0 }, 7045 }, 7046 7047 /* VEX_LEN_0F90 */ 7048 { 7049 { VEX_W_TABLE (VEX_W_0F90_L_0) }, 7050 }, 7051 7052 /* VEX_LEN_0F91 */ 7053 { 7054 { VEX_W_TABLE (VEX_W_0F91_L_0) }, 7055 }, 7056 7057 /* VEX_LEN_0F92 */ 7058 { 7059 { VEX_W_TABLE (VEX_W_0F92_L_0) }, 7060 }, 7061 7062 /* VEX_LEN_0F93 */ 7063 { 7064 { VEX_W_TABLE (VEX_W_0F93_L_0) }, 7065 }, 7066 7067 /* VEX_LEN_0F98 */ 7068 { 7069 { VEX_W_TABLE (VEX_W_0F98_L_0) }, 7070 }, 7071 7072 /* VEX_LEN_0F99 */ 7073 { 7074 { VEX_W_TABLE (VEX_W_0F99_L_0) }, 7075 }, 7076 7077 /* VEX_LEN_0FAE_R_2 */ 7078 { 7079 { "vldmxcsr", { Md }, 0 }, 7080 }, 7081 7082 /* VEX_LEN_0FAE_R_3 */ 7083 { 7084 { "vstmxcsr", { Md }, 0 }, 7085 }, 7086 7087 /* VEX_LEN_0FC4 */ 7088 { 7089 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA }, 7090 }, 7091 7092 /* VEX_LEN_0FD6 */ 7093 { 7094 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA }, 7095 }, 7096 7097 /* VEX_LEN_0F3816 */ 7098 { 7099 { Bad_Opcode }, 7100 { VEX_W_TABLE (VEX_W_0F3816_L_1) }, 7101 }, 7102 7103 /* VEX_LEN_0F3819 */ 7104 { 7105 { Bad_Opcode }, 7106 { VEX_W_TABLE (VEX_W_0F3819_L_1) }, 7107 }, 7108 7109 /* VEX_LEN_0F381A */ 7110 { 7111 { Bad_Opcode }, 7112 { VEX_W_TABLE (VEX_W_0F381A_L_1) }, 7113 }, 7114 7115 /* VEX_LEN_0F3836 */ 7116 { 7117 { Bad_Opcode }, 7118 { VEX_W_TABLE (VEX_W_0F3836) }, 7119 }, 7120 7121 /* VEX_LEN_0F3841 */ 7122 { 7123 { "vphminposuw", { XM, EXx }, PREFIX_DATA }, 7124 }, 7125 7126 /* VEX_LEN_0F3849_X86_64 */ 7127 { 7128 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, 7129 }, 7130 7131 /* VEX_LEN_0F384B_X86_64 */ 7132 { 7133 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, 7134 }, 7135 7136 /* VEX_LEN_0F385A */ 7137 { 7138 { Bad_Opcode }, 7139 { VEX_W_TABLE (VEX_W_0F385A_L_0) }, 7140 }, 7141 7142 /* VEX_LEN_0F385C_X86_64 */ 7143 { 7144 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) }, 7145 }, 7146 7147 /* VEX_LEN_0F385E_X86_64 */ 7148 { 7149 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) }, 7150 }, 7151 7152 /* VEX_LEN_0F386C_X86_64 */ 7153 { 7154 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) }, 7155 }, 7156 7157 /* VEX_LEN_0F38CB_P_3_W_0 */ 7158 { 7159 { Bad_Opcode }, 7160 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 }, 7161 }, 7162 7163 /* VEX_LEN_0F38CC_P_3_W_0 */ 7164 { 7165 { Bad_Opcode }, 7166 { "vsha512msg1", { XM, Rxmmq }, 0 }, 7167 }, 7168 7169 /* VEX_LEN_0F38CD_P_3_W_0 */ 7170 { 7171 { Bad_Opcode }, 7172 { "vsha512msg2", { XM, Rymm }, 0 }, 7173 }, 7174 7175 /* VEX_LEN_0F38DA_W_0_P_0 */ 7176 { 7177 { "vsm3msg1", { XM, Vex, EXxmm }, 0 }, 7178 }, 7179 7180 /* VEX_LEN_0F38DA_W_0_P_2 */ 7181 { 7182 { "vsm3msg2", { XM, Vex, EXxmm }, 0 }, 7183 }, 7184 7185 /* VEX_LEN_0F38DB */ 7186 { 7187 { "vaesimc", { XM, EXx }, PREFIX_DATA }, 7188 }, 7189 7190 /* VEX_LEN_0F38F2 */ 7191 { 7192 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) }, 7193 }, 7194 7195 /* VEX_LEN_0F38F3 */ 7196 { 7197 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) }, 7198 }, 7199 7200 /* VEX_LEN_0F38F5 */ 7201 { 7202 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) }, 7203 }, 7204 7205 /* VEX_LEN_0F38F6 */ 7206 { 7207 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) }, 7208 }, 7209 7210 /* VEX_LEN_0F38F7 */ 7211 { 7212 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) }, 7213 }, 7214 7215 /* VEX_LEN_0F3A00 */ 7216 { 7217 { Bad_Opcode }, 7218 { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, 7219 }, 7220 7221 /* VEX_LEN_0F3A01 */ 7222 { 7223 { Bad_Opcode }, 7224 { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, 7225 }, 7226 7227 /* VEX_LEN_0F3A06 */ 7228 { 7229 { Bad_Opcode }, 7230 { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, 7231 }, 7232 7233 /* VEX_LEN_0F3A14 */ 7234 { 7235 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA }, 7236 }, 7237 7238 /* VEX_LEN_0F3A15 */ 7239 { 7240 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA }, 7241 }, 7242 7243 /* VEX_LEN_0F3A16 */ 7244 { 7245 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA }, 7246 }, 7247 7248 /* VEX_LEN_0F3A17 */ 7249 { 7250 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA }, 7251 }, 7252 7253 /* VEX_LEN_0F3A18 */ 7254 { 7255 { Bad_Opcode }, 7256 { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, 7257 }, 7258 7259 /* VEX_LEN_0F3A19 */ 7260 { 7261 { Bad_Opcode }, 7262 { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, 7263 }, 7264 7265 /* VEX_LEN_0F3A20 */ 7266 { 7267 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA }, 7268 }, 7269 7270 /* VEX_LEN_0F3A21 */ 7271 { 7272 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA }, 7273 }, 7274 7275 /* VEX_LEN_0F3A22 */ 7276 { 7277 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, 7278 }, 7279 7280 /* VEX_LEN_0F3A30 */ 7281 { 7282 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7283 }, 7284 7285 /* VEX_LEN_0F3A31 */ 7286 { 7287 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7288 }, 7289 7290 /* VEX_LEN_0F3A32 */ 7291 { 7292 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7293 }, 7294 7295 /* VEX_LEN_0F3A33 */ 7296 { 7297 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7298 }, 7299 7300 /* VEX_LEN_0F3A38 */ 7301 { 7302 { Bad_Opcode }, 7303 { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, 7304 }, 7305 7306 /* VEX_LEN_0F3A39 */ 7307 { 7308 { Bad_Opcode }, 7309 { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, 7310 }, 7311 7312 /* VEX_LEN_0F3A41 */ 7313 { 7314 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7315 }, 7316 7317 /* VEX_LEN_0F3A46 */ 7318 { 7319 { Bad_Opcode }, 7320 { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, 7321 }, 7322 7323 /* VEX_LEN_0F3A60 */ 7324 { 7325 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 7326 }, 7327 7328 /* VEX_LEN_0F3A61 */ 7329 { 7330 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 7331 }, 7332 7333 /* VEX_LEN_0F3A62 */ 7334 { 7335 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, 7336 }, 7337 7338 /* VEX_LEN_0F3A63 */ 7339 { 7340 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, 7341 }, 7342 7343 /* VEX_LEN_0F3ADE_W_0 */ 7344 { 7345 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 7346 }, 7347 7348 /* VEX_LEN_0F3ADF */ 7349 { 7350 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, 7351 }, 7352 7353 /* VEX_LEN_0F3AF0 */ 7354 { 7355 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, 7356 }, 7357 7358 /* VEX_LEN_MAP7_F6 */ 7359 { 7360 { VEX_W_TABLE (VEX_W_MAP7_F6_L_0) }, 7361 }, 7362 7363 /* VEX_LEN_MAP7_F8 */ 7364 { 7365 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, 7366 }, 7367 7368 /* VEX_LEN_XOP_08_85 */ 7369 { 7370 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, 7371 }, 7372 7373 /* VEX_LEN_XOP_08_86 */ 7374 { 7375 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) }, 7376 }, 7377 7378 /* VEX_LEN_XOP_08_87 */ 7379 { 7380 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) }, 7381 }, 7382 7383 /* VEX_LEN_XOP_08_8E */ 7384 { 7385 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) }, 7386 }, 7387 7388 /* VEX_LEN_XOP_08_8F */ 7389 { 7390 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) }, 7391 }, 7392 7393 /* VEX_LEN_XOP_08_95 */ 7394 { 7395 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) }, 7396 }, 7397 7398 /* VEX_LEN_XOP_08_96 */ 7399 { 7400 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) }, 7401 }, 7402 7403 /* VEX_LEN_XOP_08_97 */ 7404 { 7405 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) }, 7406 }, 7407 7408 /* VEX_LEN_XOP_08_9E */ 7409 { 7410 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) }, 7411 }, 7412 7413 /* VEX_LEN_XOP_08_9F */ 7414 { 7415 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) }, 7416 }, 7417 7418 /* VEX_LEN_XOP_08_A3 */ 7419 { 7420 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, 7421 }, 7422 7423 /* VEX_LEN_XOP_08_A6 */ 7424 { 7425 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) }, 7426 }, 7427 7428 /* VEX_LEN_XOP_08_B6 */ 7429 { 7430 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) }, 7431 }, 7432 7433 /* VEX_LEN_XOP_08_C0 */ 7434 { 7435 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) }, 7436 }, 7437 7438 /* VEX_LEN_XOP_08_C1 */ 7439 { 7440 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) }, 7441 }, 7442 7443 /* VEX_LEN_XOP_08_C2 */ 7444 { 7445 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) }, 7446 }, 7447 7448 /* VEX_LEN_XOP_08_C3 */ 7449 { 7450 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) }, 7451 }, 7452 7453 /* VEX_LEN_XOP_08_CC */ 7454 { 7455 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) }, 7456 }, 7457 7458 /* VEX_LEN_XOP_08_CD */ 7459 { 7460 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) }, 7461 }, 7462 7463 /* VEX_LEN_XOP_08_CE */ 7464 { 7465 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) }, 7466 }, 7467 7468 /* VEX_LEN_XOP_08_CF */ 7469 { 7470 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) }, 7471 }, 7472 7473 /* VEX_LEN_XOP_08_EC */ 7474 { 7475 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) }, 7476 }, 7477 7478 /* VEX_LEN_XOP_08_ED */ 7479 { 7480 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) }, 7481 }, 7482 7483 /* VEX_LEN_XOP_08_EE */ 7484 { 7485 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) }, 7486 }, 7487 7488 /* VEX_LEN_XOP_08_EF */ 7489 { 7490 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) }, 7491 }, 7492 7493 /* VEX_LEN_XOP_09_01 */ 7494 { 7495 { REG_TABLE (REG_XOP_09_01_L_0) }, 7496 }, 7497 7498 /* VEX_LEN_XOP_09_02 */ 7499 { 7500 { REG_TABLE (REG_XOP_09_02_L_0) }, 7501 }, 7502 7503 /* VEX_LEN_XOP_09_12 */ 7504 { 7505 { REG_TABLE (REG_XOP_09_12_L_0) }, 7506 }, 7507 7508 /* VEX_LEN_XOP_09_82_W_0 */ 7509 { 7510 { "vfrczss", { XM, EXd }, 0 }, 7511 }, 7512 7513 /* VEX_LEN_XOP_09_83_W_0 */ 7514 { 7515 { "vfrczsd", { XM, EXq }, 0 }, 7516 }, 7517 7518 /* VEX_LEN_XOP_09_90 */ 7519 { 7520 { "vprotb", { XM, EXx, VexW }, 0 }, 7521 }, 7522 7523 /* VEX_LEN_XOP_09_91 */ 7524 { 7525 { "vprotw", { XM, EXx, VexW }, 0 }, 7526 }, 7527 7528 /* VEX_LEN_XOP_09_92 */ 7529 { 7530 { "vprotd", { XM, EXx, VexW }, 0 }, 7531 }, 7532 7533 /* VEX_LEN_XOP_09_93 */ 7534 { 7535 { "vprotq", { XM, EXx, VexW }, 0 }, 7536 }, 7537 7538 /* VEX_LEN_XOP_09_94 */ 7539 { 7540 { "vpshlb", { XM, EXx, VexW }, 0 }, 7541 }, 7542 7543 /* VEX_LEN_XOP_09_95 */ 7544 { 7545 { "vpshlw", { XM, EXx, VexW }, 0 }, 7546 }, 7547 7548 /* VEX_LEN_XOP_09_96 */ 7549 { 7550 { "vpshld", { XM, EXx, VexW }, 0 }, 7551 }, 7552 7553 /* VEX_LEN_XOP_09_97 */ 7554 { 7555 { "vpshlq", { XM, EXx, VexW }, 0 }, 7556 }, 7557 7558 /* VEX_LEN_XOP_09_98 */ 7559 { 7560 { "vpshab", { XM, EXx, VexW }, 0 }, 7561 }, 7562 7563 /* VEX_LEN_XOP_09_99 */ 7564 { 7565 { "vpshaw", { XM, EXx, VexW }, 0 }, 7566 }, 7567 7568 /* VEX_LEN_XOP_09_9A */ 7569 { 7570 { "vpshad", { XM, EXx, VexW }, 0 }, 7571 }, 7572 7573 /* VEX_LEN_XOP_09_9B */ 7574 { 7575 { "vpshaq", { XM, EXx, VexW }, 0 }, 7576 }, 7577 7578 /* VEX_LEN_XOP_09_C1 */ 7579 { 7580 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) }, 7581 }, 7582 7583 /* VEX_LEN_XOP_09_C2 */ 7584 { 7585 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) }, 7586 }, 7587 7588 /* VEX_LEN_XOP_09_C3 */ 7589 { 7590 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) }, 7591 }, 7592 7593 /* VEX_LEN_XOP_09_C6 */ 7594 { 7595 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) }, 7596 }, 7597 7598 /* VEX_LEN_XOP_09_C7 */ 7599 { 7600 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) }, 7601 }, 7602 7603 /* VEX_LEN_XOP_09_CB */ 7604 { 7605 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) }, 7606 }, 7607 7608 /* VEX_LEN_XOP_09_D1 */ 7609 { 7610 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) }, 7611 }, 7612 7613 /* VEX_LEN_XOP_09_D2 */ 7614 { 7615 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) }, 7616 }, 7617 7618 /* VEX_LEN_XOP_09_D3 */ 7619 { 7620 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) }, 7621 }, 7622 7623 /* VEX_LEN_XOP_09_D6 */ 7624 { 7625 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) }, 7626 }, 7627 7628 /* VEX_LEN_XOP_09_D7 */ 7629 { 7630 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) }, 7631 }, 7632 7633 /* VEX_LEN_XOP_09_DB */ 7634 { 7635 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) }, 7636 }, 7637 7638 /* VEX_LEN_XOP_09_E1 */ 7639 { 7640 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) }, 7641 }, 7642 7643 /* VEX_LEN_XOP_09_E2 */ 7644 { 7645 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) }, 7646 }, 7647 7648 /* VEX_LEN_XOP_09_E3 */ 7649 { 7650 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) }, 7651 }, 7652 7653 /* VEX_LEN_XOP_0A_12 */ 7654 { 7655 { REG_TABLE (REG_XOP_0A_12_L_0) }, 7656 }, 7657 }; 7658 7659 #include "i386-dis-evex-len.h" 7660 7661 static const struct dis386 vex_w_table[][2] = { 7662 { 7663 /* VEX_W_0F41_L_1_M_1 */ 7664 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) }, 7665 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) }, 7666 }, 7667 { 7668 /* VEX_W_0F42_L_1_M_1 */ 7669 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) }, 7670 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) }, 7671 }, 7672 { 7673 /* VEX_W_0F44_L_0_M_1 */ 7674 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) }, 7675 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) }, 7676 }, 7677 { 7678 /* VEX_W_0F45_L_1_M_1 */ 7679 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) }, 7680 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) }, 7681 }, 7682 { 7683 /* VEX_W_0F46_L_1_M_1 */ 7684 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) }, 7685 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) }, 7686 }, 7687 { 7688 /* VEX_W_0F47_L_1_M_1 */ 7689 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) }, 7690 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) }, 7691 }, 7692 { 7693 /* VEX_W_0F4A_L_1_M_1 */ 7694 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) }, 7695 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) }, 7696 }, 7697 { 7698 /* VEX_W_0F4B_L_1_M_1 */ 7699 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) }, 7700 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) }, 7701 }, 7702 { 7703 /* VEX_W_0F90_L_0 */ 7704 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) }, 7705 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) }, 7706 }, 7707 { 7708 /* VEX_W_0F91_L_0_M_0 */ 7709 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) }, 7710 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) }, 7711 }, 7712 { 7713 /* VEX_W_0F92_L_0_M_1 */ 7714 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) }, 7715 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) }, 7716 }, 7717 { 7718 /* VEX_W_0F93_L_0_M_1 */ 7719 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) }, 7720 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) }, 7721 }, 7722 { 7723 /* VEX_W_0F98_L_0_M_1 */ 7724 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) }, 7725 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) }, 7726 }, 7727 { 7728 /* VEX_W_0F99_L_0_M_1 */ 7729 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) }, 7730 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) }, 7731 }, 7732 { 7733 /* VEX_W_0F380C */ 7734 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA }, 7735 }, 7736 { 7737 /* VEX_W_0F380D */ 7738 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, 7739 }, 7740 { 7741 /* VEX_W_0F380E */ 7742 { "vtestps", { XM, EXx }, PREFIX_DATA }, 7743 }, 7744 { 7745 /* VEX_W_0F380F */ 7746 { "vtestpd", { XM, EXx }, PREFIX_DATA }, 7747 }, 7748 { 7749 /* VEX_W_0F3813 */ 7750 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, 7751 }, 7752 { 7753 /* VEX_W_0F3816_L_1 */ 7754 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, 7755 }, 7756 { 7757 /* VEX_W_0F3818 */ 7758 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA }, 7759 }, 7760 { 7761 /* VEX_W_0F3819_L_1 */ 7762 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA }, 7763 }, 7764 { 7765 /* VEX_W_0F381A_L_1 */ 7766 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, 7767 }, 7768 { 7769 /* VEX_W_0F382C */ 7770 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, 7771 }, 7772 { 7773 /* VEX_W_0F382D */ 7774 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, 7775 }, 7776 { 7777 /* VEX_W_0F382E */ 7778 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, 7779 }, 7780 { 7781 /* VEX_W_0F382F */ 7782 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, 7783 }, 7784 { 7785 /* VEX_W_0F3836 */ 7786 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, 7787 }, 7788 { 7789 /* VEX_W_0F3846 */ 7790 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, 7791 }, 7792 { 7793 /* VEX_W_0F3849_X86_64_L_0 */ 7794 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) }, 7795 }, 7796 { 7797 /* VEX_W_0F384B_X86_64_L_0 */ 7798 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) }, 7799 }, 7800 { 7801 /* VEX_W_0F3850 */ 7802 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, 7803 }, 7804 { 7805 /* VEX_W_0F3851 */ 7806 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, 7807 }, 7808 { 7809 /* VEX_W_0F3852 */ 7810 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA }, 7811 }, 7812 { 7813 /* VEX_W_0F3853 */ 7814 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA }, 7815 }, 7816 { 7817 /* VEX_W_0F3858 */ 7818 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA }, 7819 }, 7820 { 7821 /* VEX_W_0F3859 */ 7822 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA }, 7823 }, 7824 { 7825 /* VEX_W_0F385A_L_0 */ 7826 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, 7827 }, 7828 { 7829 /* VEX_W_0F385C_X86_64_L_0 */ 7830 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) }, 7831 }, 7832 { 7833 /* VEX_W_0F385E_X86_64_L_0 */ 7834 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) }, 7835 }, 7836 { 7837 /* VEX_W_0F386C_X86_64_L_0 */ 7838 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) }, 7839 }, 7840 { 7841 /* VEX_W_0F3872_P_1 */ 7842 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 }, 7843 }, 7844 { 7845 /* VEX_W_0F3878 */ 7846 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA }, 7847 }, 7848 { 7849 /* VEX_W_0F3879 */ 7850 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, 7851 }, 7852 { 7853 /* VEX_W_0F38B0 */ 7854 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) }, 7855 }, 7856 { 7857 /* VEX_W_0F38B1 */ 7858 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) }, 7859 }, 7860 { 7861 /* VEX_W_0F38B4 */ 7862 { Bad_Opcode }, 7863 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, 7864 }, 7865 { 7866 /* VEX_W_0F38B5 */ 7867 { Bad_Opcode }, 7868 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, 7869 }, 7870 { 7871 /* VEX_W_0F38CB_P_3 */ 7872 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) }, 7873 }, 7874 { 7875 /* VEX_W_0F38CC_P_3 */ 7876 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) }, 7877 }, 7878 { 7879 /* VEX_W_0F38CD_P_3 */ 7880 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) }, 7881 }, 7882 { 7883 /* VEX_W_0F38CF */ 7884 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, 7885 }, 7886 { 7887 /* VEX_W_0F38D2 */ 7888 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) }, 7889 }, 7890 { 7891 /* VEX_W_0F38D3 */ 7892 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) }, 7893 }, 7894 { 7895 /* VEX_W_0F38DA */ 7896 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) }, 7897 }, 7898 { 7899 /* VEX_W_0F3A00_L_1 */ 7900 { Bad_Opcode }, 7901 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA }, 7902 }, 7903 { 7904 /* VEX_W_0F3A01_L_1 */ 7905 { Bad_Opcode }, 7906 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA }, 7907 }, 7908 { 7909 /* VEX_W_0F3A02 */ 7910 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7911 }, 7912 { 7913 /* VEX_W_0F3A04 */ 7914 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA }, 7915 }, 7916 { 7917 /* VEX_W_0F3A05 */ 7918 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, 7919 }, 7920 { 7921 /* VEX_W_0F3A06_L_1 */ 7922 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7923 }, 7924 { 7925 /* VEX_W_0F3A18_L_1 */ 7926 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 7927 }, 7928 { 7929 /* VEX_W_0F3A19_L_1 */ 7930 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, 7931 }, 7932 { 7933 /* VEX_W_0F3A1D */ 7934 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, 7935 }, 7936 { 7937 /* VEX_W_0F3A38_L_1 */ 7938 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 7939 }, 7940 { 7941 /* VEX_W_0F3A39_L_1 */ 7942 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, 7943 }, 7944 { 7945 /* VEX_W_0F3A46_L_1 */ 7946 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7947 }, 7948 { 7949 /* VEX_W_0F3A4A */ 7950 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7951 }, 7952 { 7953 /* VEX_W_0F3A4B */ 7954 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7955 }, 7956 { 7957 /* VEX_W_0F3A4C */ 7958 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7959 }, 7960 { 7961 /* VEX_W_0F3ACE */ 7962 { Bad_Opcode }, 7963 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7964 }, 7965 { 7966 /* VEX_W_0F3ACF */ 7967 { Bad_Opcode }, 7968 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7969 }, 7970 { 7971 /* VEX_W_0F3ADE */ 7972 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, 7973 }, 7974 { 7975 /* VEX_W_MAP7_F6_L_0 */ 7976 { REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) }, 7977 }, 7978 { 7979 /* VEX_W_MAP7_F8_L_0 */ 7980 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, 7981 }, 7982 /* VEX_W_XOP_08_85_L_0 */ 7983 { 7984 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, 7985 }, 7986 /* VEX_W_XOP_08_86_L_0 */ 7987 { 7988 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 7989 }, 7990 /* VEX_W_XOP_08_87_L_0 */ 7991 { 7992 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, 7993 }, 7994 /* VEX_W_XOP_08_8E_L_0 */ 7995 { 7996 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, 7997 }, 7998 /* VEX_W_XOP_08_8F_L_0 */ 7999 { 8000 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, 8001 }, 8002 /* VEX_W_XOP_08_95_L_0 */ 8003 { 8004 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, 8005 }, 8006 /* VEX_W_XOP_08_96_L_0 */ 8007 { 8008 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8009 }, 8010 /* VEX_W_XOP_08_97_L_0 */ 8011 { 8012 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, 8013 }, 8014 /* VEX_W_XOP_08_9E_L_0 */ 8015 { 8016 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8017 }, 8018 /* VEX_W_XOP_08_9F_L_0 */ 8019 { 8020 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, 8021 }, 8022 /* VEX_W_XOP_08_A6_L_0 */ 8023 { 8024 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8025 }, 8026 /* VEX_W_XOP_08_B6_L_0 */ 8027 { 8028 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8029 }, 8030 /* VEX_W_XOP_08_C0_L_0 */ 8031 { 8032 { "vprotb", { XM, EXx, Ib }, 0 }, 8033 }, 8034 /* VEX_W_XOP_08_C1_L_0 */ 8035 { 8036 { "vprotw", { XM, EXx, Ib }, 0 }, 8037 }, 8038 /* VEX_W_XOP_08_C2_L_0 */ 8039 { 8040 { "vprotd", { XM, EXx, Ib }, 0 }, 8041 }, 8042 /* VEX_W_XOP_08_C3_L_0 */ 8043 { 8044 { "vprotq", { XM, EXx, Ib }, 0 }, 8045 }, 8046 /* VEX_W_XOP_08_CC_L_0 */ 8047 { 8048 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, 8049 }, 8050 /* VEX_W_XOP_08_CD_L_0 */ 8051 { 8052 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, 8053 }, 8054 /* VEX_W_XOP_08_CE_L_0 */ 8055 { 8056 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, 8057 }, 8058 /* VEX_W_XOP_08_CF_L_0 */ 8059 { 8060 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, 8061 }, 8062 /* VEX_W_XOP_08_EC_L_0 */ 8063 { 8064 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, 8065 }, 8066 /* VEX_W_XOP_08_ED_L_0 */ 8067 { 8068 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, 8069 }, 8070 /* VEX_W_XOP_08_EE_L_0 */ 8071 { 8072 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, 8073 }, 8074 /* VEX_W_XOP_08_EF_L_0 */ 8075 { 8076 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, 8077 }, 8078 /* VEX_W_XOP_09_80 */ 8079 { 8080 { "vfrczps", { XM, EXx }, 0 }, 8081 }, 8082 /* VEX_W_XOP_09_81 */ 8083 { 8084 { "vfrczpd", { XM, EXx }, 0 }, 8085 }, 8086 /* VEX_W_XOP_09_82 */ 8087 { 8088 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) }, 8089 }, 8090 /* VEX_W_XOP_09_83 */ 8091 { 8092 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) }, 8093 }, 8094 /* VEX_W_XOP_09_C1_L_0 */ 8095 { 8096 { "vphaddbw", { XM, EXxmm }, 0 }, 8097 }, 8098 /* VEX_W_XOP_09_C2_L_0 */ 8099 { 8100 { "vphaddbd", { XM, EXxmm }, 0 }, 8101 }, 8102 /* VEX_W_XOP_09_C3_L_0 */ 8103 { 8104 { "vphaddbq", { XM, EXxmm }, 0 }, 8105 }, 8106 /* VEX_W_XOP_09_C6_L_0 */ 8107 { 8108 { "vphaddwd", { XM, EXxmm }, 0 }, 8109 }, 8110 /* VEX_W_XOP_09_C7_L_0 */ 8111 { 8112 { "vphaddwq", { XM, EXxmm }, 0 }, 8113 }, 8114 /* VEX_W_XOP_09_CB_L_0 */ 8115 { 8116 { "vphadddq", { XM, EXxmm }, 0 }, 8117 }, 8118 /* VEX_W_XOP_09_D1_L_0 */ 8119 { 8120 { "vphaddubw", { XM, EXxmm }, 0 }, 8121 }, 8122 /* VEX_W_XOP_09_D2_L_0 */ 8123 { 8124 { "vphaddubd", { XM, EXxmm }, 0 }, 8125 }, 8126 /* VEX_W_XOP_09_D3_L_0 */ 8127 { 8128 { "vphaddubq", { XM, EXxmm }, 0 }, 8129 }, 8130 /* VEX_W_XOP_09_D6_L_0 */ 8131 { 8132 { "vphadduwd", { XM, EXxmm }, 0 }, 8133 }, 8134 /* VEX_W_XOP_09_D7_L_0 */ 8135 { 8136 { "vphadduwq", { XM, EXxmm }, 0 }, 8137 }, 8138 /* VEX_W_XOP_09_DB_L_0 */ 8139 { 8140 { "vphaddudq", { XM, EXxmm }, 0 }, 8141 }, 8142 /* VEX_W_XOP_09_E1_L_0 */ 8143 { 8144 { "vphsubbw", { XM, EXxmm }, 0 }, 8145 }, 8146 /* VEX_W_XOP_09_E2_L_0 */ 8147 { 8148 { "vphsubwd", { XM, EXxmm }, 0 }, 8149 }, 8150 /* VEX_W_XOP_09_E3_L_0 */ 8151 { 8152 { "vphsubdq", { XM, EXxmm }, 0 }, 8153 }, 8154 8155 #include "i386-dis-evex-w.h" 8156 }; 8157 8158 static const struct dis386 mod_table[][2] = { 8159 { 8160 /* MOD_62_32BIT */ 8161 { "bound{S|}", { Gv, Ma }, 0 }, 8162 { EVEX_TABLE () }, 8163 }, 8164 { 8165 /* MOD_C4_32BIT */ 8166 { "lesS", { Gv, Mp }, 0 }, 8167 { VEX_C4_TABLE () }, 8168 }, 8169 { 8170 /* MOD_C5_32BIT */ 8171 { "ldsS", { Gv, Mp }, 0 }, 8172 { VEX_C5_TABLE () }, 8173 }, 8174 { 8175 /* MOD_0F01_REG_0 */ 8176 { X86_64_TABLE (X86_64_0F01_REG_0) }, 8177 { RM_TABLE (RM_0F01_REG_0) }, 8178 }, 8179 { 8180 /* MOD_0F01_REG_1 */ 8181 { X86_64_TABLE (X86_64_0F01_REG_1) }, 8182 { RM_TABLE (RM_0F01_REG_1) }, 8183 }, 8184 { 8185 /* MOD_0F01_REG_2 */ 8186 { X86_64_TABLE (X86_64_0F01_REG_2) }, 8187 { RM_TABLE (RM_0F01_REG_2) }, 8188 }, 8189 { 8190 /* MOD_0F01_REG_3 */ 8191 { X86_64_TABLE (X86_64_0F01_REG_3) }, 8192 { RM_TABLE (RM_0F01_REG_3) }, 8193 }, 8194 { 8195 /* MOD_0F01_REG_5 */ 8196 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, 8197 { RM_TABLE (RM_0F01_REG_5_MOD_3) }, 8198 }, 8199 { 8200 /* MOD_0F01_REG_7 */ 8201 { "invlpg", { Mb }, 0 }, 8202 { RM_TABLE (RM_0F01_REG_7_MOD_3) }, 8203 }, 8204 { 8205 /* MOD_0F12_PREFIX_0 */ 8206 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 }, 8207 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 }, 8208 }, 8209 { 8210 /* MOD_0F16_PREFIX_0 */ 8211 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 }, 8212 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 }, 8213 }, 8214 { 8215 /* MOD_0F18_REG_0 */ 8216 { "prefetchnta", { Mb }, 0 }, 8217 { "nopQ", { Ev }, 0 }, 8218 }, 8219 { 8220 /* MOD_0F18_REG_1 */ 8221 { "prefetcht0", { Mb }, 0 }, 8222 { "nopQ", { Ev }, 0 }, 8223 }, 8224 { 8225 /* MOD_0F18_REG_2 */ 8226 { "prefetcht1", { Mb }, 0 }, 8227 { "nopQ", { Ev }, 0 }, 8228 }, 8229 { 8230 /* MOD_0F18_REG_3 */ 8231 { "prefetcht2", { Mb }, 0 }, 8232 { "nopQ", { Ev }, 0 }, 8233 }, 8234 { 8235 /* MOD_0F18_REG_6 */ 8236 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) }, 8237 { "nopQ", { Ev }, 0 }, 8238 }, 8239 { 8240 /* MOD_0F18_REG_7 */ 8241 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) }, 8242 { "nopQ", { Ev }, 0 }, 8243 }, 8244 { 8245 /* MOD_0F1A_PREFIX_0 */ 8246 { "bndldx", { Gbnd, Mv_bnd }, 0 }, 8247 { "nopQ", { Ev }, 0 }, 8248 }, 8249 { 8250 /* MOD_0F1B_PREFIX_0 */ 8251 { "bndstx", { Mv_bnd, Gbnd }, 0 }, 8252 { "nopQ", { Ev }, 0 }, 8253 }, 8254 { 8255 /* MOD_0F1B_PREFIX_1 */ 8256 { "bndmk", { Gbnd, Mv_bnd }, 0 }, 8257 { "nopQ", { Ev }, PREFIX_IGNORED }, 8258 }, 8259 { 8260 /* MOD_0F1C_PREFIX_0 */ 8261 { REG_TABLE (REG_0F1C_P_0_MOD_0) }, 8262 { "nopQ", { Ev }, 0 }, 8263 }, 8264 { 8265 /* MOD_0F1E_PREFIX_1 */ 8266 { "nopQ", { Ev }, PREFIX_IGNORED }, 8267 { REG_TABLE (REG_0F1E_P_1_MOD_3) }, 8268 }, 8269 { 8270 /* MOD_0FAE_REG_0 */ 8271 { "fxsave", { FXSAVE }, 0 }, 8272 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, 8273 }, 8274 { 8275 /* MOD_0FAE_REG_1 */ 8276 { "fxrstor", { FXSAVE }, 0 }, 8277 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, 8278 }, 8279 { 8280 /* MOD_0FAE_REG_2 */ 8281 { "ldmxcsr", { Md }, 0 }, 8282 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, 8283 }, 8284 { 8285 /* MOD_0FAE_REG_3 */ 8286 { "stmxcsr", { Md }, 0 }, 8287 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, 8288 }, 8289 { 8290 /* MOD_0FAE_REG_4 */ 8291 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, 8292 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, 8293 }, 8294 { 8295 /* MOD_0FAE_REG_5 */ 8296 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, 8297 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, 8298 }, 8299 { 8300 /* MOD_0FAE_REG_6 */ 8301 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, 8302 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, 8303 }, 8304 { 8305 /* MOD_0FAE_REG_7 */ 8306 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, 8307 { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, 8308 }, 8309 { 8310 /* MOD_0FC7_REG_6 */ 8311 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, 8312 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } 8313 }, 8314 { 8315 /* MOD_0FC7_REG_7 */ 8316 { "vmptrst", { Mq }, 0 }, 8317 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } 8318 }, 8319 { 8320 /* MOD_0F38DC_PREFIX_1 */ 8321 { "aesenc128kl", { XM, M }, 0 }, 8322 { "loadiwkey", { XM, EXx }, 0 }, 8323 }, 8324 /* MOD_0F38F8 */ 8325 { 8326 { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, 8327 { X86_64_TABLE (X86_64_0F38F8_M_1) }, 8328 }, 8329 { 8330 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ 8331 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, 8332 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) }, 8333 }, 8334 8335 #include "i386-dis-evex-mod.h" 8336 }; 8337 8338 static const struct dis386 rm_table[][8] = { 8339 { 8340 /* RM_C6_REG_7 */ 8341 { "xabort", { Skip_MODRM, Ib }, 0 }, 8342 }, 8343 { 8344 /* RM_C7_REG_7 */ 8345 { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, 8346 }, 8347 { 8348 /* RM_0F01_REG_0 */ 8349 { "enclv", { Skip_MODRM }, 0 }, 8350 { "vmcall", { Skip_MODRM }, 0 }, 8351 { "vmlaunch", { Skip_MODRM }, 0 }, 8352 { "vmresume", { Skip_MODRM }, 0 }, 8353 { "vmxoff", { Skip_MODRM }, 0 }, 8354 { "pconfig", { Skip_MODRM }, 0 }, 8355 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, 8356 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) }, 8357 }, 8358 { 8359 /* RM_0F01_REG_1 */ 8360 { "monitor", { { OP_Monitor, 0 } }, 0 }, 8361 { "mwait", { { OP_Mwait, 0 } }, 0 }, 8362 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) }, 8363 { "stac", { Skip_MODRM }, 0 }, 8364 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, 8365 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, 8366 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, 8367 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, 8368 }, 8369 { 8370 /* RM_0F01_REG_2 */ 8371 { "xgetbv", { Skip_MODRM }, 0 }, 8372 { "xsetbv", { Skip_MODRM }, 0 }, 8373 { Bad_Opcode }, 8374 { Bad_Opcode }, 8375 { "vmfunc", { Skip_MODRM }, 0 }, 8376 { "xend", { Skip_MODRM }, 0 }, 8377 { "xtest", { Skip_MODRM }, 0 }, 8378 { "enclu", { Skip_MODRM }, 0 }, 8379 }, 8380 { 8381 /* RM_0F01_REG_3 */ 8382 { "vmrun", { Skip_MODRM }, 0 }, 8383 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, 8384 { "vmload", { Skip_MODRM }, 0 }, 8385 { "vmsave", { Skip_MODRM }, 0 }, 8386 { "stgi", { Skip_MODRM }, 0 }, 8387 { "clgi", { Skip_MODRM }, 0 }, 8388 { "skinit", { Skip_MODRM }, 0 }, 8389 { "invlpga", { Skip_MODRM }, 0 }, 8390 }, 8391 { 8392 /* RM_0F01_REG_5_MOD_3 */ 8393 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, 8394 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, 8395 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, 8396 { Bad_Opcode }, 8397 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) }, 8398 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) }, 8399 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) }, 8400 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) }, 8401 }, 8402 { 8403 /* RM_0F01_REG_7_MOD_3 */ 8404 { "swapgs", { Skip_MODRM }, 0 }, 8405 { "rdtscp", { Skip_MODRM }, 0 }, 8406 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, 8407 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, 8408 { "clzero", { Skip_MODRM }, 0 }, 8409 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) }, 8410 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, 8411 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, 8412 }, 8413 { 8414 /* RM_0F1E_P_1_MOD_3_REG_7 */ 8415 { "nopQ", { Ev }, PREFIX_IGNORED }, 8416 { "nopQ", { Ev }, PREFIX_IGNORED }, 8417 { "endbr64", { Skip_MODRM }, 0 }, 8418 { "endbr32", { Skip_MODRM }, 0 }, 8419 { "nopQ", { Ev }, PREFIX_IGNORED }, 8420 { "nopQ", { Ev }, PREFIX_IGNORED }, 8421 { "nopQ", { Ev }, PREFIX_IGNORED }, 8422 { "nopQ", { Ev }, PREFIX_IGNORED }, 8423 }, 8424 { 8425 /* RM_0FAE_REG_6_MOD_3 */ 8426 { "mfence", { Skip_MODRM }, 0 }, 8427 }, 8428 { 8429 /* RM_0FAE_REG_7_MOD_3 */ 8430 { "sfence", { Skip_MODRM }, 0 }, 8431 }, 8432 { 8433 /* RM_0F3A0F_P_1_R_0 */ 8434 { "hreset", { Skip_MODRM, Ib }, 0 }, 8435 }, 8436 { 8437 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */ 8438 { "tilerelease", { Skip_MODRM }, 0 }, 8439 }, 8440 { 8441 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */ 8442 { "tilezero", { TMM, Skip_MODRM }, 0 }, 8443 }, 8444 }; 8445 8446 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") 8447 8448 /* The values used here must be non-zero, fit in 'unsigned char', and not be 8449 in conflict with actual prefix opcodes. */ 8450 #define REP_PREFIX 0x01 8451 #define XACQUIRE_PREFIX 0x02 8452 #define XRELEASE_PREFIX 0x03 8453 #define BND_PREFIX 0x04 8454 #define NOTRACK_PREFIX 0x05 8455 8456 static enum { 8457 ckp_okay, 8458 ckp_bogus, 8459 ckp_fetch_error, 8460 } 8461 ckprefix (instr_info *ins) 8462 { 8463 int i, length; 8464 uint8_t newrex; 8465 8466 i = 0; 8467 length = 0; 8468 /* The maximum instruction length is 15bytes. */ 8469 while (length < MAX_CODE_LENGTH - 1) 8470 { 8471 if (!fetch_code (ins->info, ins->codep + 1)) 8472 return ckp_fetch_error; 8473 newrex = 0; 8474 switch (*ins->codep) 8475 { 8476 /* REX prefixes family. */ 8477 case 0x40: 8478 case 0x41: 8479 case 0x42: 8480 case 0x43: 8481 case 0x44: 8482 case 0x45: 8483 case 0x46: 8484 case 0x47: 8485 case 0x48: 8486 case 0x49: 8487 case 0x4a: 8488 case 0x4b: 8489 case 0x4c: 8490 case 0x4d: 8491 case 0x4e: 8492 case 0x4f: 8493 if (ins->address_mode == mode_64bit) 8494 newrex = *ins->codep; 8495 else 8496 return ckp_okay; 8497 ins->last_rex_prefix = i; 8498 break; 8499 /* REX2 must be the last prefix. */ 8500 case REX2_OPCODE: 8501 if (ins->address_mode == mode_64bit) 8502 { 8503 if (ins->last_rex_prefix >= 0) 8504 return ckp_bogus; 8505 8506 ins->codep++; 8507 if (!fetch_code (ins->info, ins->codep + 1)) 8508 return ckp_fetch_error; 8509 ins->rex2_payload = *ins->codep; 8510 ins->rex2 = ins->rex2_payload >> 4; 8511 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE; 8512 ins->codep++; 8513 ins->last_rex2_prefix = i; 8514 ins->all_prefixes[i] = REX2_OPCODE; 8515 } 8516 return ckp_okay; 8517 case 0xf3: 8518 ins->prefixes |= PREFIX_REPZ; 8519 ins->last_repz_prefix = i; 8520 break; 8521 case 0xf2: 8522 ins->prefixes |= PREFIX_REPNZ; 8523 ins->last_repnz_prefix = i; 8524 break; 8525 case 0xf0: 8526 ins->prefixes |= PREFIX_LOCK; 8527 ins->last_lock_prefix = i; 8528 break; 8529 case 0x2e: 8530 ins->prefixes |= PREFIX_CS; 8531 ins->last_seg_prefix = i; 8532 if (ins->address_mode != mode_64bit) 8533 ins->active_seg_prefix = PREFIX_CS; 8534 break; 8535 case 0x36: 8536 ins->prefixes |= PREFIX_SS; 8537 ins->last_seg_prefix = i; 8538 if (ins->address_mode != mode_64bit) 8539 ins->active_seg_prefix = PREFIX_SS; 8540 break; 8541 case 0x3e: 8542 ins->prefixes |= PREFIX_DS; 8543 ins->last_seg_prefix = i; 8544 if (ins->address_mode != mode_64bit) 8545 ins->active_seg_prefix = PREFIX_DS; 8546 break; 8547 case 0x26: 8548 ins->prefixes |= PREFIX_ES; 8549 ins->last_seg_prefix = i; 8550 if (ins->address_mode != mode_64bit) 8551 ins->active_seg_prefix = PREFIX_ES; 8552 break; 8553 case 0x64: 8554 ins->prefixes |= PREFIX_FS; 8555 ins->last_seg_prefix = i; 8556 ins->active_seg_prefix = PREFIX_FS; 8557 break; 8558 case 0x65: 8559 ins->prefixes |= PREFIX_GS; 8560 ins->last_seg_prefix = i; 8561 ins->active_seg_prefix = PREFIX_GS; 8562 break; 8563 case 0x66: 8564 ins->prefixes |= PREFIX_DATA; 8565 ins->last_data_prefix = i; 8566 break; 8567 case 0x67: 8568 ins->prefixes |= PREFIX_ADDR; 8569 ins->last_addr_prefix = i; 8570 break; 8571 case FWAIT_OPCODE: 8572 /* fwait is really an instruction. If there are prefixes 8573 before the fwait, they belong to the fwait, *not* to the 8574 following instruction. */ 8575 ins->fwait_prefix = i; 8576 if (ins->prefixes || ins->rex) 8577 { 8578 ins->prefixes |= PREFIX_FWAIT; 8579 ins->codep++; 8580 /* This ensures that the previous REX prefixes are noticed 8581 as unused prefixes, as in the return case below. */ 8582 return ins->rex ? ckp_bogus : ckp_okay; 8583 } 8584 ins->prefixes = PREFIX_FWAIT; 8585 break; 8586 default: 8587 return ckp_okay; 8588 } 8589 /* Rex is ignored when followed by another prefix. */ 8590 if (ins->rex) 8591 return ckp_bogus; 8592 if (*ins->codep != FWAIT_OPCODE) 8593 ins->all_prefixes[i++] = *ins->codep; 8594 ins->rex = newrex; 8595 ins->codep++; 8596 length++; 8597 } 8598 return ckp_bogus; 8599 } 8600 8601 /* Return the name of the prefix byte PREF, or NULL if PREF is not a 8602 prefix byte. */ 8603 8604 static const char * 8605 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag) 8606 { 8607 static const char *rexes [16] = 8608 { 8609 "rex", /* 0x40 */ 8610 "rex.B", /* 0x41 */ 8611 "rex.X", /* 0x42 */ 8612 "rex.XB", /* 0x43 */ 8613 "rex.R", /* 0x44 */ 8614 "rex.RB", /* 0x45 */ 8615 "rex.RX", /* 0x46 */ 8616 "rex.RXB", /* 0x47 */ 8617 "rex.W", /* 0x48 */ 8618 "rex.WB", /* 0x49 */ 8619 "rex.WX", /* 0x4a */ 8620 "rex.WXB", /* 0x4b */ 8621 "rex.WR", /* 0x4c */ 8622 "rex.WRB", /* 0x4d */ 8623 "rex.WRX", /* 0x4e */ 8624 "rex.WRXB", /* 0x4f */ 8625 }; 8626 8627 switch (pref) 8628 { 8629 /* REX prefixes family. */ 8630 case 0x40: 8631 case 0x41: 8632 case 0x42: 8633 case 0x43: 8634 case 0x44: 8635 case 0x45: 8636 case 0x46: 8637 case 0x47: 8638 case 0x48: 8639 case 0x49: 8640 case 0x4a: 8641 case 0x4b: 8642 case 0x4c: 8643 case 0x4d: 8644 case 0x4e: 8645 case 0x4f: 8646 return rexes [pref - 0x40]; 8647 case 0xf3: 8648 return "repz"; 8649 case 0xf2: 8650 return "repnz"; 8651 case 0xf0: 8652 return "lock"; 8653 case 0x2e: 8654 return "cs"; 8655 case 0x36: 8656 return "ss"; 8657 case 0x3e: 8658 return "ds"; 8659 case 0x26: 8660 return "es"; 8661 case 0x64: 8662 return "fs"; 8663 case 0x65: 8664 return "gs"; 8665 case 0x66: 8666 return (sizeflag & DFLAG) ? "data16" : "data32"; 8667 case 0x67: 8668 if (mode == mode_64bit) 8669 return (sizeflag & AFLAG) ? "addr32" : "addr64"; 8670 else 8671 return (sizeflag & AFLAG) ? "addr16" : "addr32"; 8672 case FWAIT_OPCODE: 8673 return "fwait"; 8674 case REP_PREFIX: 8675 return "rep"; 8676 case XACQUIRE_PREFIX: 8677 return "xacquire"; 8678 case XRELEASE_PREFIX: 8679 return "xrelease"; 8680 case BND_PREFIX: 8681 return "bnd"; 8682 case NOTRACK_PREFIX: 8683 return "notrack"; 8684 case REX2_OPCODE: 8685 return "rex2"; 8686 default: 8687 return NULL; 8688 } 8689 } 8690 8691 void 8692 print_i386_disassembler_options (FILE *stream) 8693 { 8694 fprintf (stream, _("\n\ 8695 The following i386/x86-64 specific disassembler options are supported for use\n\ 8696 with the -M switch (multiple options should be separated by commas):\n")); 8697 8698 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); 8699 fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); 8700 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); 8701 fprintf (stream, _(" att Display instruction in AT&T syntax\n")); 8702 fprintf (stream, _(" intel Display instruction in Intel syntax\n")); 8703 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n" 8704 " Display instruction with AT&T mnemonic\n")); 8705 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n" 8706 " Display instruction with Intel mnemonic\n")); 8707 fprintf (stream, _(" addr64 Assume 64bit address size\n")); 8708 fprintf (stream, _(" addr32 Assume 32bit address size\n")); 8709 fprintf (stream, _(" addr16 Assume 16bit address size\n")); 8710 fprintf (stream, _(" data32 Assume 32bit data size\n")); 8711 fprintf (stream, _(" data16 Assume 16bit data size\n")); 8712 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); 8713 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); 8714 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); 8715 } 8716 8717 /* Bad opcode. */ 8718 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; 8719 8720 /* Fetch error indicator. */ 8721 static const struct dis386 err_opcode = { NULL, { XX }, 0 }; 8722 8723 static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) }; 8724 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; 8725 8726 /* Get a pointer to struct dis386 with a valid name. */ 8727 8728 static const struct dis386 * 8729 get_valid_dis386 (const struct dis386 *dp, instr_info *ins) 8730 { 8731 int vindex, vex_table_index; 8732 8733 if (dp->name != NULL) 8734 return dp; 8735 8736 switch (dp->op[0].bytemode) 8737 { 8738 case USE_REG_TABLE: 8739 dp = ®_table[dp->op[1].bytemode][ins->modrm.reg]; 8740 break; 8741 8742 case USE_MOD_TABLE: 8743 vindex = ins->modrm.mod == 0x3 ? 1 : 0; 8744 dp = &mod_table[dp->op[1].bytemode][vindex]; 8745 break; 8746 8747 case USE_RM_TABLE: 8748 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm]; 8749 break; 8750 8751 case USE_PREFIX_TABLE: 8752 use_prefix_table: 8753 if (ins->need_vex) 8754 { 8755 /* The prefix in VEX is implicit. */ 8756 switch (ins->vex.prefix) 8757 { 8758 case 0: 8759 vindex = 0; 8760 break; 8761 case REPE_PREFIX_OPCODE: 8762 vindex = 1; 8763 break; 8764 case DATA_PREFIX_OPCODE: 8765 vindex = 2; 8766 break; 8767 case REPNE_PREFIX_OPCODE: 8768 vindex = 3; 8769 break; 8770 default: 8771 abort (); 8772 break; 8773 } 8774 } 8775 else 8776 { 8777 int last_prefix = -1; 8778 int prefix = 0; 8779 vindex = 0; 8780 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. 8781 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the 8782 last one wins. */ 8783 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) 8784 { 8785 if (ins->last_repz_prefix > ins->last_repnz_prefix) 8786 { 8787 vindex = 1; 8788 prefix = PREFIX_REPZ; 8789 last_prefix = ins->last_repz_prefix; 8790 } 8791 else 8792 { 8793 vindex = 3; 8794 prefix = PREFIX_REPNZ; 8795 last_prefix = ins->last_repnz_prefix; 8796 } 8797 8798 /* Check if prefix should be ignored. */ 8799 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement 8800 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) 8801 & prefix) != 0 8802 && !prefix_table[dp->op[1].bytemode][vindex].name) 8803 vindex = 0; 8804 } 8805 8806 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0) 8807 { 8808 vindex = 2; 8809 prefix = PREFIX_DATA; 8810 last_prefix = ins->last_data_prefix; 8811 } 8812 8813 if (vindex != 0) 8814 { 8815 ins->used_prefixes |= prefix; 8816 ins->all_prefixes[last_prefix] = 0; 8817 } 8818 } 8819 dp = &prefix_table[dp->op[1].bytemode][vindex]; 8820 break; 8821 8822 case USE_X86_64_EVEX_FROM_VEX_TABLE: 8823 case USE_X86_64_EVEX_PFX_TABLE: 8824 case USE_X86_64_EVEX_W_TABLE: 8825 case USE_X86_64_EVEX_MEM_W_TABLE: 8826 ins->evex_type = evex_from_vex; 8827 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z, 8828 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */ 8829 if (ins->address_mode != mode_64bit 8830 || (ins->vex.mask_register_specifier & 0x3) != 0 8831 || ins->vex.ll != 0 8832 || ins->vex.zeroing != 0 8833 || ins->vex.b) 8834 return &bad_opcode; 8835 8836 if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE) 8837 goto use_prefix_table; 8838 if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE) 8839 goto use_vex_w_table; 8840 if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE) 8841 { 8842 if (ins->modrm.mod == 3) 8843 return &bad_opcode; 8844 goto use_vex_w_table; 8845 } 8846 8847 /* Fall through. */ 8848 case USE_X86_64_TABLE: 8849 vindex = ins->address_mode == mode_64bit ? 1 : 0; 8850 dp = &x86_64_table[dp->op[1].bytemode][vindex]; 8851 break; 8852 8853 case USE_3BYTE_TABLE: 8854 if (ins->last_rex2_prefix >= 0) 8855 return &err_opcode; 8856 if (!fetch_code (ins->info, ins->codep + 2)) 8857 return &err_opcode; 8858 vindex = *ins->codep++; 8859 dp = &three_byte_table[dp->op[1].bytemode][vindex]; 8860 ins->end_codep = ins->codep; 8861 if (!fetch_modrm (ins)) 8862 return &err_opcode; 8863 break; 8864 8865 case USE_VEX_LEN_TABLE: 8866 if (!ins->need_vex) 8867 abort (); 8868 8869 switch (ins->vex.length) 8870 { 8871 case 128: 8872 vindex = 0; 8873 break; 8874 case 512: 8875 /* This allows re-using in particular table entries where only 8876 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */ 8877 if (ins->vex.evex) 8878 { 8879 case 256: 8880 vindex = 1; 8881 break; 8882 } 8883 /* Fall through. */ 8884 default: 8885 abort (); 8886 break; 8887 } 8888 8889 dp = &vex_len_table[dp->op[1].bytemode][vindex]; 8890 break; 8891 8892 case USE_EVEX_LEN_TABLE: 8893 if (!ins->vex.evex) 8894 abort (); 8895 8896 switch (ins->vex.length) 8897 { 8898 case 128: 8899 vindex = 0; 8900 break; 8901 case 256: 8902 vindex = 1; 8903 break; 8904 case 512: 8905 vindex = 2; 8906 break; 8907 default: 8908 abort (); 8909 break; 8910 } 8911 8912 dp = &evex_len_table[dp->op[1].bytemode][vindex]; 8913 break; 8914 8915 case USE_XOP_8F_TABLE: 8916 if (!fetch_code (ins->info, ins->codep + 3)) 8917 return &err_opcode; 8918 ins->rex = ~(*ins->codep >> 5) & 0x7; 8919 8920 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ 8921 switch ((*ins->codep & 0x1f)) 8922 { 8923 default: 8924 dp = &bad_opcode; 8925 return dp; 8926 case 0x8: 8927 vex_table_index = XOP_08; 8928 break; 8929 case 0x9: 8930 vex_table_index = XOP_09; 8931 break; 8932 case 0xa: 8933 vex_table_index = XOP_0A; 8934 break; 8935 } 8936 ins->codep++; 8937 ins->vex.w = *ins->codep & 0x80; 8938 if (ins->vex.w && ins->address_mode == mode_64bit) 8939 ins->rex |= REX_W; 8940 8941 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 8942 if (ins->address_mode != mode_64bit) 8943 { 8944 /* In 16/32-bit mode REX_B is silently ignored. */ 8945 ins->rex &= ~REX_B; 8946 } 8947 8948 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 8949 switch ((*ins->codep & 0x3)) 8950 { 8951 case 0: 8952 break; 8953 case 1: 8954 ins->vex.prefix = DATA_PREFIX_OPCODE; 8955 break; 8956 case 2: 8957 ins->vex.prefix = REPE_PREFIX_OPCODE; 8958 break; 8959 case 3: 8960 ins->vex.prefix = REPNE_PREFIX_OPCODE; 8961 break; 8962 } 8963 ins->need_vex = 3; 8964 ins->codep++; 8965 vindex = *ins->codep++; 8966 dp = &xop_table[vex_table_index][vindex]; 8967 8968 ins->end_codep = ins->codep; 8969 if (!fetch_modrm (ins)) 8970 return &err_opcode; 8971 8972 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid 8973 having to decode the bits for every otherwise valid encoding. */ 8974 if (ins->vex.prefix) 8975 return &bad_opcode; 8976 break; 8977 8978 case USE_VEX_C4_TABLE: 8979 /* VEX prefix. */ 8980 if (!fetch_code (ins->info, ins->codep + 3)) 8981 return &err_opcode; 8982 ins->rex = ~(*ins->codep >> 5) & 0x7; 8983 switch ((*ins->codep & 0x1f)) 8984 { 8985 default: 8986 dp = &bad_opcode; 8987 return dp; 8988 case 0x1: 8989 vex_table_index = VEX_0F; 8990 break; 8991 case 0x2: 8992 vex_table_index = VEX_0F38; 8993 break; 8994 case 0x3: 8995 vex_table_index = VEX_0F3A; 8996 break; 8997 case 0x7: 8998 vex_table_index = VEX_MAP7; 8999 break; 9000 } 9001 ins->codep++; 9002 ins->vex.w = *ins->codep & 0x80; 9003 if (ins->address_mode == mode_64bit) 9004 { 9005 if (ins->vex.w) 9006 ins->rex |= REX_W; 9007 } 9008 else 9009 { 9010 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit 9011 is ignored, other REX bits are 0 and the highest bit in 9012 VEX.vvvv is also ignored (but we mustn't clear it here). */ 9013 ins->rex = 0; 9014 } 9015 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9016 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 9017 switch ((*ins->codep & 0x3)) 9018 { 9019 case 0: 9020 break; 9021 case 1: 9022 ins->vex.prefix = DATA_PREFIX_OPCODE; 9023 break; 9024 case 2: 9025 ins->vex.prefix = REPE_PREFIX_OPCODE; 9026 break; 9027 case 3: 9028 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9029 break; 9030 } 9031 ins->need_vex = 3; 9032 ins->codep++; 9033 vindex = *ins->codep++; 9034 ins->condition_code = vindex & 0xf; 9035 if (vex_table_index != VEX_MAP7) 9036 dp = &vex_table[vex_table_index][vindex]; 9037 else if (vindex == 0xf6) 9038 dp = &map7_f6_opcode; 9039 else if (vindex == 0xf8) 9040 dp = &map7_f8_opcode; 9041 else 9042 dp = &bad_opcode; 9043 ins->end_codep = ins->codep; 9044 /* There is no MODRM byte for VEX0F 77. */ 9045 if ((vex_table_index != VEX_0F || vindex != 0x77) 9046 && !fetch_modrm (ins)) 9047 return &err_opcode; 9048 break; 9049 9050 case USE_VEX_C5_TABLE: 9051 /* VEX prefix. */ 9052 if (!fetch_code (ins->info, ins->codep + 2)) 9053 return &err_opcode; 9054 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R; 9055 9056 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in 9057 VEX.vvvv is 1. */ 9058 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9059 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 9060 switch ((*ins->codep & 0x3)) 9061 { 9062 case 0: 9063 break; 9064 case 1: 9065 ins->vex.prefix = DATA_PREFIX_OPCODE; 9066 break; 9067 case 2: 9068 ins->vex.prefix = REPE_PREFIX_OPCODE; 9069 break; 9070 case 3: 9071 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9072 break; 9073 } 9074 ins->need_vex = 2; 9075 ins->codep++; 9076 vindex = *ins->codep++; 9077 dp = &vex_table[VEX_0F][vindex]; 9078 ins->end_codep = ins->codep; 9079 /* There is no MODRM byte for VEX 77. */ 9080 if (vindex != 0x77 && !fetch_modrm (ins)) 9081 return &err_opcode; 9082 break; 9083 9084 case USE_VEX_W_TABLE: 9085 use_vex_w_table: 9086 if (!ins->need_vex) 9087 abort (); 9088 9089 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w]; 9090 break; 9091 9092 case USE_EVEX_TABLE: 9093 ins->two_source_ops = false; 9094 /* EVEX prefix. */ 9095 ins->vex.evex = true; 9096 if (!fetch_code (ins->info, ins->codep + 4)) 9097 return &err_opcode; 9098 /* The first byte after 0x62. */ 9099 if (*ins->codep & 0x8) 9100 ins->rex2 |= REX_B; 9101 if (!(*ins->codep & 0x10)) 9102 ins->rex2 |= REX_R; 9103 9104 ins->rex = ~(*ins->codep >> 5) & 0x7; 9105 switch (*ins->codep & 0x7) 9106 { 9107 default: 9108 return &bad_opcode; 9109 case 0x1: 9110 vex_table_index = EVEX_0F; 9111 break; 9112 case 0x2: 9113 vex_table_index = EVEX_0F38; 9114 break; 9115 case 0x3: 9116 vex_table_index = EVEX_0F3A; 9117 break; 9118 case 0x4: 9119 vex_table_index = EVEX_MAP4; 9120 ins->evex_type = evex_from_legacy; 9121 if (ins->address_mode != mode_64bit) 9122 return &bad_opcode; 9123 ins->rex |= REX_OPCODE; 9124 break; 9125 case 0x5: 9126 vex_table_index = EVEX_MAP5; 9127 break; 9128 case 0x6: 9129 vex_table_index = EVEX_MAP6; 9130 break; 9131 case 0x7: 9132 vex_table_index = EVEX_MAP7; 9133 break; 9134 } 9135 9136 /* The second byte after 0x62. */ 9137 ins->codep++; 9138 ins->vex.w = *ins->codep & 0x80; 9139 if (ins->vex.w && ins->address_mode == mode_64bit) 9140 ins->rex |= REX_W; 9141 9142 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9143 9144 if (!(*ins->codep & 0x4)) 9145 ins->rex2 |= REX_X; 9146 9147 ins->vex.u = *ins->codep & 0x4; 9148 9149 switch ((*ins->codep & 0x3)) 9150 { 9151 case 0: 9152 break; 9153 case 1: 9154 ins->vex.prefix = DATA_PREFIX_OPCODE; 9155 break; 9156 case 2: 9157 ins->vex.prefix = REPE_PREFIX_OPCODE; 9158 break; 9159 case 3: 9160 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9161 break; 9162 } 9163 9164 /* The third byte after 0x62. */ 9165 ins->codep++; 9166 9167 /* Remember the static rounding bits. */ 9168 ins->vex.ll = (*ins->codep >> 5) & 3; 9169 ins->vex.b = *ins->codep & 0x10; 9170 9171 ins->vex.v = *ins->codep & 0x8; 9172 ins->vex.mask_register_specifier = *ins->codep & 0x7; 9173 ins->vex.scc = *ins->codep & 0xf; 9174 ins->vex.zeroing = *ins->codep & 0x80; 9175 /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared 9176 when it's an evex_default one. */ 9177 ins->vex.nf = *ins->codep & 0x4; 9178 9179 if (ins->address_mode != mode_64bit) 9180 { 9181 /* Report bad for !evex_default and when two fixed values of evex 9182 change. */ 9183 if (ins->evex_type != evex_default || (ins->rex2 & REX_B) 9184 || ((ins->rex2 & REX_X) && (ins->modrm.mod != 3))) 9185 return &bad_opcode; 9186 /* In 16/32-bit mode silently ignore following bits. */ 9187 ins->rex &= ~REX_B; 9188 ins->rex2 &= ~REX_R; 9189 } 9190 9191 ins->need_vex = 4; 9192 9193 ins->codep++; 9194 vindex = *ins->codep++; 9195 ins->condition_code = vindex & 0xf; 9196 if (vex_table_index != EVEX_MAP7) 9197 dp = &evex_table[vex_table_index][vindex]; 9198 else if (vindex == 0xf8) 9199 dp = &map7_f8_opcode; 9200 else if (vindex == 0xf6) 9201 dp = &map7_f6_opcode; 9202 else 9203 dp = &bad_opcode; 9204 ins->end_codep = ins->codep; 9205 if (!fetch_modrm (ins)) 9206 return &err_opcode; 9207 9208 /* When modrm.mod != 3, the U bit is used by APX for bit X4. 9209 When modrm.mod == 3, the U bit is used by AVX10. The U bit and 9210 the b bit should not be zero at the same time. */ 9211 if (ins->modrm.mod == 3 && !ins->vex.u && !ins->vex.b) 9212 return &bad_opcode; 9213 9214 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00, 9215 which has the same encoding as vex.length == 128 and they can share 9216 the same processing with vex.length in OP_VEX. */ 9217 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy) 9218 { 9219 if (ins->vex.u) 9220 ins->vex.length = 512; 9221 else 9222 ins->vex.length = 256; 9223 } 9224 else 9225 { 9226 switch (ins->vex.ll) 9227 { 9228 case 0x0: 9229 ins->vex.length = 128; 9230 break; 9231 case 0x1: 9232 ins->vex.length = 256; 9233 break; 9234 case 0x2: 9235 ins->vex.length = 512; 9236 break; 9237 default: 9238 return &bad_opcode; 9239 } 9240 } 9241 break; 9242 9243 case 0: 9244 dp = &bad_opcode; 9245 break; 9246 9247 default: 9248 abort (); 9249 } 9250 9251 if (dp->name != NULL) 9252 return dp; 9253 else 9254 return get_valid_dis386 (dp, ins); 9255 } 9256 9257 static bool 9258 get_sib (instr_info *ins, int sizeflag) 9259 { 9260 /* If modrm.mod == 3, operand must be register. */ 9261 if (ins->need_modrm 9262 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 9263 && ins->modrm.mod != 3 9264 && ins->modrm.rm == 4) 9265 { 9266 if (!fetch_code (ins->info, ins->codep + 2)) 9267 return false; 9268 ins->sib.index = (ins->codep[1] >> 3) & 7; 9269 ins->sib.scale = (ins->codep[1] >> 6) & 3; 9270 ins->sib.base = ins->codep[1] & 7; 9271 ins->has_sib = true; 9272 } 9273 else 9274 ins->has_sib = false; 9275 9276 return true; 9277 } 9278 9279 /* Like oappend_with_style (below) but always with text style. */ 9280 9281 static void 9282 oappend (instr_info *ins, const char *s) 9283 { 9284 oappend_with_style (ins, s, dis_style_text); 9285 } 9286 9287 /* Like oappend (above), but S is a string starting with '%'. In 9288 Intel syntax, the '%' is elided. */ 9289 9290 static void 9291 oappend_register (instr_info *ins, const char *s) 9292 { 9293 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register); 9294 } 9295 9296 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT. 9297 STYLE is the default style to use in the fprintf_styled_func calls, 9298 however, FMT might include embedded style markers (see oappend_style), 9299 these embedded markers are not printed, but instead change the style 9300 used in the next fprintf_styled_func call. */ 9301 9302 static void ATTRIBUTE_PRINTF_3 9303 i386_dis_printf (const disassemble_info *info, enum disassembler_style style, 9304 const char *fmt, ...) 9305 { 9306 va_list ap; 9307 enum disassembler_style curr_style = style; 9308 const char *start, *curr; 9309 char staging_area[50]; 9310 9311 va_start (ap, fmt); 9312 /* In particular print_insn()'s processing of op_txt[] can hand rather long 9313 strings here. Bypass vsnprintf() in such cases to avoid capacity issues 9314 with the staging area. */ 9315 if (strcmp (fmt, "%s")) 9316 { 9317 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap); 9318 9319 va_end (ap); 9320 9321 if (res < 0) 9322 return; 9323 9324 if ((size_t) res >= sizeof (staging_area)) 9325 abort (); 9326 9327 start = curr = staging_area; 9328 } 9329 else 9330 { 9331 start = curr = va_arg (ap, const char *); 9332 va_end (ap); 9333 } 9334 9335 do 9336 { 9337 if (*curr == '\0' 9338 || (*curr == STYLE_MARKER_CHAR 9339 && ISXDIGIT (*(curr + 1)) 9340 && *(curr + 2) == STYLE_MARKER_CHAR)) 9341 { 9342 /* Output content between our START position and CURR. */ 9343 int len = curr - start; 9344 int n = (*info->fprintf_styled_func) (info->stream, curr_style, 9345 "%.*s", len, start); 9346 if (n < 0) 9347 break; 9348 9349 if (*curr == '\0') 9350 break; 9351 9352 /* Skip over the initial STYLE_MARKER_CHAR. */ 9353 ++curr; 9354 9355 /* Update the CURR_STYLE. As there are less than 16 styles, it 9356 is possible, that if the input is corrupted in some way, that 9357 we might set CURR_STYLE to an invalid value. Don't worry 9358 though, we check for this situation. */ 9359 if (*curr >= '0' && *curr <= '9') 9360 curr_style = (enum disassembler_style) (*curr - '0'); 9361 else if (*curr >= 'a' && *curr <= 'f') 9362 curr_style = (enum disassembler_style) (*curr - 'a' + 10); 9363 else 9364 curr_style = dis_style_text; 9365 9366 /* Check for an invalid style having been selected. This should 9367 never happen, but it doesn't hurt to be a little paranoid. */ 9368 if (curr_style > dis_style_comment_start) 9369 curr_style = dis_style_text; 9370 9371 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */ 9372 curr += 2; 9373 9374 /* Reset the START to after the style marker. */ 9375 start = curr; 9376 } 9377 else 9378 ++curr; 9379 } 9380 while (true); 9381 } 9382 9383 static int 9384 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) 9385 { 9386 const struct dis386 *dp; 9387 int i; 9388 int ret; 9389 char *op_txt[MAX_OPERANDS]; 9390 int needcomma; 9391 bool intel_swap_2_3; 9392 int sizeflag, orig_sizeflag; 9393 const char *p; 9394 struct dis_private priv; 9395 int prefix_length; 9396 int op_count; 9397 instr_info ins = { 9398 .info = info, 9399 .intel_syntax = intel_syntax >= 0 9400 ? intel_syntax 9401 : (info->mach & bfd_mach_i386_intel_syntax) != 0, 9402 .intel_mnemonic = !SYSV386_COMPAT, 9403 .op_index[0 ... MAX_OPERANDS - 1] = -1, 9404 .start_pc = pc, 9405 .start_codep = priv.the_buffer, 9406 .codep = priv.the_buffer, 9407 .obufp = ins.obuf, 9408 .last_lock_prefix = -1, 9409 .last_repz_prefix = -1, 9410 .last_repnz_prefix = -1, 9411 .last_data_prefix = -1, 9412 .last_addr_prefix = -1, 9413 .last_rex_prefix = -1, 9414 .last_rex2_prefix = -1, 9415 .last_seg_prefix = -1, 9416 .fwait_prefix = -1, 9417 }; 9418 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE]; 9419 9420 priv.orig_sizeflag = AFLAG | DFLAG; 9421 if ((info->mach & bfd_mach_i386_i386) != 0) 9422 ins.address_mode = mode_32bit; 9423 else if (info->mach == bfd_mach_i386_i8086) 9424 { 9425 ins.address_mode = mode_16bit; 9426 priv.orig_sizeflag = 0; 9427 } 9428 else 9429 ins.address_mode = mode_64bit; 9430 9431 for (p = info->disassembler_options; p != NULL;) 9432 { 9433 if (startswith (p, "amd64")) 9434 ins.isa64 = amd64; 9435 else if (startswith (p, "intel64")) 9436 ins.isa64 = intel64; 9437 else if (startswith (p, "x86-64")) 9438 { 9439 ins.address_mode = mode_64bit; 9440 priv.orig_sizeflag |= AFLAG | DFLAG; 9441 } 9442 else if (startswith (p, "i386")) 9443 { 9444 ins.address_mode = mode_32bit; 9445 priv.orig_sizeflag |= AFLAG | DFLAG; 9446 } 9447 else if (startswith (p, "i8086")) 9448 { 9449 ins.address_mode = mode_16bit; 9450 priv.orig_sizeflag &= ~(AFLAG | DFLAG); 9451 } 9452 else if (startswith (p, "intel")) 9453 { 9454 if (startswith (p + 5, "-mnemonic")) 9455 ins.intel_mnemonic = true; 9456 else 9457 ins.intel_syntax = 1; 9458 } 9459 else if (startswith (p, "att")) 9460 { 9461 ins.intel_syntax = 0; 9462 if (startswith (p + 3, "-mnemonic")) 9463 ins.intel_mnemonic = false; 9464 } 9465 else if (startswith (p, "addr")) 9466 { 9467 if (ins.address_mode == mode_64bit) 9468 { 9469 if (p[4] == '3' && p[5] == '2') 9470 priv.orig_sizeflag &= ~AFLAG; 9471 else if (p[4] == '6' && p[5] == '4') 9472 priv.orig_sizeflag |= AFLAG; 9473 } 9474 else 9475 { 9476 if (p[4] == '1' && p[5] == '6') 9477 priv.orig_sizeflag &= ~AFLAG; 9478 else if (p[4] == '3' && p[5] == '2') 9479 priv.orig_sizeflag |= AFLAG; 9480 } 9481 } 9482 else if (startswith (p, "data")) 9483 { 9484 if (p[4] == '1' && p[5] == '6') 9485 priv.orig_sizeflag &= ~DFLAG; 9486 else if (p[4] == '3' && p[5] == '2') 9487 priv.orig_sizeflag |= DFLAG; 9488 } 9489 else if (startswith (p, "suffix")) 9490 priv.orig_sizeflag |= SUFFIX_ALWAYS; 9491 9492 p = strchr (p, ','); 9493 if (p != NULL) 9494 p++; 9495 } 9496 9497 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8) 9498 { 9499 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled")); 9500 return -1; 9501 } 9502 9503 if (ins.intel_syntax) 9504 { 9505 ins.open_char = '['; 9506 ins.close_char = ']'; 9507 ins.separator_char = '+'; 9508 ins.scale_char = '*'; 9509 } 9510 else 9511 { 9512 ins.open_char = '('; 9513 ins.close_char = ')'; 9514 ins.separator_char = ','; 9515 ins.scale_char = ','; 9516 } 9517 9518 /* The output looks better if we put 7 bytes on a line, since that 9519 puts most long word instructions on a single line. */ 9520 info->bytes_per_line = 7; 9521 9522 info->private_data = &priv; 9523 priv.fetched = 0; 9524 priv.insn_start = pc; 9525 9526 for (i = 0; i < MAX_OPERANDS; ++i) 9527 { 9528 op_out[i][0] = 0; 9529 ins.op_out[i] = op_out[i]; 9530 } 9531 9532 sizeflag = priv.orig_sizeflag; 9533 9534 switch (ckprefix (&ins)) 9535 { 9536 case ckp_okay: 9537 break; 9538 9539 case ckp_bogus: 9540 /* Too many prefixes or unused REX prefixes. */ 9541 for (i = 0; 9542 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i]; 9543 i++) 9544 i386_dis_printf (info, dis_style_mnemonic, "%s%s", 9545 (i == 0 ? "" : " "), 9546 prefix_name (ins.address_mode, ins.all_prefixes[i], 9547 sizeflag)); 9548 ret = i; 9549 goto out; 9550 9551 case ckp_fetch_error: 9552 goto fetch_error_out; 9553 } 9554 9555 ins.nr_prefixes = ins.codep - ins.start_codep; 9556 9557 if (!fetch_code (info, ins.codep + 1)) 9558 { 9559 fetch_error_out: 9560 ret = fetch_error (&ins); 9561 goto out; 9562 } 9563 9564 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8); 9565 9566 if ((ins.prefixes & PREFIX_FWAIT) 9567 && (*ins.codep < 0xd8 || *ins.codep > 0xdf)) 9568 { 9569 /* Handle ins.prefixes before fwait. */ 9570 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i]; 9571 i++) 9572 i386_dis_printf (info, dis_style_mnemonic, "%s ", 9573 prefix_name (ins.address_mode, ins.all_prefixes[i], 9574 sizeflag)); 9575 i386_dis_printf (info, dis_style_mnemonic, "fwait"); 9576 ret = i + 1; 9577 goto out; 9578 } 9579 9580 /* REX2.M in rex2 prefix represents map0 or map1. */ 9581 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M)) 9582 { 9583 if (!ins.rex2) 9584 { 9585 ins.codep++; 9586 if (!fetch_code (info, ins.codep + 1)) 9587 goto fetch_error_out; 9588 } 9589 9590 dp = &dis386_twobyte[*ins.codep]; 9591 ins.need_modrm = twobyte_has_modrm[*ins.codep]; 9592 } 9593 else 9594 { 9595 dp = &dis386[*ins.codep]; 9596 ins.need_modrm = onebyte_has_modrm[*ins.codep]; 9597 } 9598 ins.condition_code = *ins.codep & 0xf; 9599 ins.codep++; 9600 9601 /* Save sizeflag for printing the extra ins.prefixes later before updating 9602 it for mnemonic and operand processing. The prefix names depend 9603 only on the address mode. */ 9604 orig_sizeflag = sizeflag; 9605 if (ins.prefixes & PREFIX_ADDR) 9606 sizeflag ^= AFLAG; 9607 if ((ins.prefixes & PREFIX_DATA)) 9608 sizeflag ^= DFLAG; 9609 9610 ins.end_codep = ins.codep; 9611 if (ins.need_modrm && !fetch_modrm (&ins)) 9612 goto fetch_error_out; 9613 9614 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) 9615 { 9616 if (!get_sib (&ins, sizeflag) 9617 || !dofloat (&ins, sizeflag)) 9618 goto fetch_error_out; 9619 } 9620 else 9621 { 9622 dp = get_valid_dis386 (dp, &ins); 9623 if (dp == &err_opcode) 9624 goto fetch_error_out; 9625 9626 /* For APX instructions promoted from legacy maps 0/1, embedded prefix 9627 is interpreted as the operand size override. */ 9628 if (ins.evex_type == evex_from_legacy 9629 && ins.vex.prefix == DATA_PREFIX_OPCODE) 9630 sizeflag ^= DFLAG; 9631 9632 if(ins.evex_type == evex_default) 9633 ins.vex.nf = false; 9634 else 9635 /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest 9636 are cleared separately.) in mask_register_specifier and keep the low 9637 2 bits of mask_register_specifier to report errors for invalid cases 9638 . */ 9639 ins.vex.mask_register_specifier &= 0x3; 9640 9641 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) 9642 { 9643 if (!get_sib (&ins, sizeflag)) 9644 goto fetch_error_out; 9645 for (i = 0; i < MAX_OPERANDS; ++i) 9646 { 9647 ins.obufp = ins.op_out[i]; 9648 ins.op_ad = MAX_OPERANDS - 1 - i; 9649 if (dp->op[i].rtn 9650 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag)) 9651 goto fetch_error_out; 9652 /* For EVEX instruction after the last operand masking 9653 should be printed. */ 9654 if (i == 0 && ins.vex.evex) 9655 { 9656 /* Don't print {%k0}. */ 9657 if (ins.vex.mask_register_specifier) 9658 { 9659 const char *reg_name 9660 = att_names_mask[ins.vex.mask_register_specifier]; 9661 9662 oappend (&ins, "{"); 9663 oappend_register (&ins, reg_name); 9664 oappend (&ins, "}"); 9665 9666 if (ins.vex.zeroing) 9667 oappend (&ins, "{z}"); 9668 } 9669 else if (ins.vex.zeroing) 9670 { 9671 oappend (&ins, "{bad}"); 9672 continue; 9673 } 9674 9675 /* Instructions with a mask register destination allow for 9676 zeroing-masking only (if any masking at all), which is 9677 _not_ expressed by EVEX.z. */ 9678 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode) 9679 ins.illegal_masking = true; 9680 9681 /* S/G insns require a mask and don't allow 9682 zeroing-masking. */ 9683 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode 9684 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode) 9685 && (ins.vex.mask_register_specifier == 0 9686 || ins.vex.zeroing)) 9687 ins.illegal_masking = true; 9688 9689 if (ins.illegal_masking) 9690 oappend (&ins, "/(bad)"); 9691 } 9692 } 9693 /* vex.nf is cleared after being consumed. */ 9694 if (ins.vex.nf) 9695 oappend (&ins, "{bad-nf}"); 9696 9697 /* Check whether rounding control was enabled for an insn not 9698 supporting it, when evex.b is not treated as evex.nd. */ 9699 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default 9700 && !(ins.evex_used & EVEX_b_used)) 9701 { 9702 for (i = 0; i < MAX_OPERANDS; ++i) 9703 { 9704 ins.obufp = ins.op_out[i]; 9705 if (*ins.obufp) 9706 continue; 9707 oappend (&ins, names_rounding[ins.vex.ll]); 9708 oappend (&ins, "bad}"); 9709 break; 9710 } 9711 } 9712 } 9713 } 9714 9715 /* Clear instruction information. */ 9716 info->insn_info_valid = 0; 9717 info->branch_delay_insns = 0; 9718 info->data_size = 0; 9719 info->insn_type = dis_noninsn; 9720 info->target = 0; 9721 info->target2 = 0; 9722 9723 /* Reset jump operation indicator. */ 9724 ins.op_is_jump = false; 9725 { 9726 int jump_detection = 0; 9727 9728 /* Extract flags. */ 9729 for (i = 0; i < MAX_OPERANDS; ++i) 9730 { 9731 if ((dp->op[i].rtn == OP_J) 9732 || (dp->op[i].rtn == OP_indirE)) 9733 jump_detection |= 1; 9734 else if ((dp->op[i].rtn == BND_Fixup) 9735 || (!dp->op[i].rtn && !dp->op[i].bytemode)) 9736 jump_detection |= 2; 9737 else if ((dp->op[i].bytemode == cond_jump_mode) 9738 || (dp->op[i].bytemode == loop_jcxz_mode)) 9739 jump_detection |= 4; 9740 } 9741 9742 /* Determine if this is a jump or branch. */ 9743 if ((jump_detection & 0x3) == 0x3) 9744 { 9745 ins.op_is_jump = true; 9746 if (jump_detection & 0x4) 9747 info->insn_type = dis_condbranch; 9748 else 9749 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4)) 9750 ? dis_jsr : dis_branch; 9751 } 9752 } 9753 /* The purpose of placing the check here is to wait for the EVEX prefix for 9754 conditional CMP and TEST to be consumed and cleared, and then make a 9755 unified judgment. Because they are both in map4, we can not distinguish 9756 EVEX prefix for conditional CMP and TEST from others during the 9757 EVEX prefix stage of parsing. */ 9758 if (ins.evex_type == evex_from_legacy) 9759 { 9760 /* EVEX from legacy instructions, when the EVEX.ND bit is 0, 9761 all bits of EVEX.vvvv and EVEX.V' must be 1. */ 9762 if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v)) 9763 { 9764 i386_dis_printf (info, dis_style_text, "(bad)"); 9765 ret = ins.end_codep - priv.the_buffer; 9766 goto out; 9767 } 9768 9769 /* EVEX from legacy instructions require that EVEX.z, EVEX.LL and the 9770 lower 2 bits of EVEX.aaa must be 0. */ 9771 if ((ins.vex.mask_register_specifier & 0x3) != 0 9772 || ins.vex.ll != 0 || ins.vex.zeroing != 0) 9773 { 9774 i386_dis_printf (info, dis_style_text, "(bad)"); 9775 ret = ins.end_codep - priv.the_buffer; 9776 goto out; 9777 } 9778 } 9779 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which 9780 are all 0s in inverted form. */ 9781 if (ins.need_vex && ins.vex.register_specifier != 0) 9782 { 9783 i386_dis_printf (info, dis_style_text, "(bad)"); 9784 ret = ins.end_codep - priv.the_buffer; 9785 goto out; 9786 } 9787 9788 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL) 9789 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0) 9790 { 9791 i386_dis_printf (info, dis_style_text, "(bad)"); 9792 ret = ins.end_codep - priv.the_buffer; 9793 goto out; 9794 } 9795 9796 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL) 9797 { 9798 case PREFIX_DATA: 9799 /* If only the data prefix is marked as mandatory, its absence renders 9800 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ 9801 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA)) 9802 { 9803 i386_dis_printf (info, dis_style_text, "(bad)"); 9804 ret = ins.end_codep - priv.the_buffer; 9805 goto out; 9806 } 9807 ins.used_prefixes |= PREFIX_DATA; 9808 /* Fall through. */ 9809 case PREFIX_OPCODE: 9810 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is 9811 unused, opcode is invalid. Since the PREFIX_DATA prefix may be 9812 used by putop and MMX/SSE operand and may be overridden by the 9813 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix 9814 separately. */ 9815 if (((ins.need_vex 9816 ? ins.vex.prefix == REPE_PREFIX_OPCODE 9817 || ins.vex.prefix == REPNE_PREFIX_OPCODE 9818 : (ins.prefixes 9819 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) 9820 && (ins.used_prefixes 9821 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) 9822 || (((ins.need_vex 9823 ? ins.vex.prefix == DATA_PREFIX_OPCODE 9824 : ((ins.prefixes 9825 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) 9826 == PREFIX_DATA)) 9827 && (ins.used_prefixes & PREFIX_DATA) == 0)) 9828 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA 9829 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA))) 9830 { 9831 i386_dis_printf (info, dis_style_text, "(bad)"); 9832 ret = ins.end_codep - priv.the_buffer; 9833 goto out; 9834 } 9835 break; 9836 9837 case PREFIX_IGNORED: 9838 /* Zap data size and rep prefixes from used_prefixes and reinstate their 9839 origins in all_prefixes. */ 9840 ins.used_prefixes &= ~PREFIX_OPCODE; 9841 if (ins.last_data_prefix >= 0) 9842 ins.all_prefixes[ins.last_data_prefix] = 0x66; 9843 if (ins.last_repz_prefix >= 0) 9844 ins.all_prefixes[ins.last_repz_prefix] = 0xf3; 9845 if (ins.last_repnz_prefix >= 0) 9846 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2; 9847 break; 9848 9849 case PREFIX_NP_OR_DATA: 9850 if (ins.vex.prefix == REPE_PREFIX_OPCODE 9851 || ins.vex.prefix == REPNE_PREFIX_OPCODE) 9852 { 9853 i386_dis_printf (info, dis_style_text, "(bad)"); 9854 ret = ins.end_codep - priv.the_buffer; 9855 goto out; 9856 } 9857 break; 9858 9859 case NO_PREFIX: 9860 if (ins.vex.prefix) 9861 { 9862 i386_dis_printf (info, dis_style_text, "(bad)"); 9863 ret = ins.end_codep - priv.the_buffer; 9864 goto out; 9865 } 9866 break; 9867 } 9868 9869 /* Check if the REX prefix is used. */ 9870 if ((ins.rex ^ ins.rex_used) == 0 9871 && !ins.need_vex && ins.last_rex_prefix >= 0) 9872 ins.all_prefixes[ins.last_rex_prefix] = 0; 9873 9874 /* Check if the REX2 prefix is used. */ 9875 if (ins.last_rex2_prefix >= 0 9876 && ((ins.rex2 & REX2_SPECIAL) 9877 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0 9878 && (ins.rex ^ ins.rex_used) == 0 9879 && (ins.rex2 & 7)))) 9880 ins.all_prefixes[ins.last_rex2_prefix] = 0; 9881 9882 /* Check if the SEG prefix is used. */ 9883 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES 9884 | PREFIX_FS | PREFIX_GS)) != 0 9885 && (ins.used_prefixes & ins.active_seg_prefix) != 0) 9886 ins.all_prefixes[ins.last_seg_prefix] = 0; 9887 9888 /* Check if the ADDR prefix is used. */ 9889 if ((ins.prefixes & PREFIX_ADDR) != 0 9890 && (ins.used_prefixes & PREFIX_ADDR) != 0) 9891 ins.all_prefixes[ins.last_addr_prefix] = 0; 9892 9893 /* Check if the DATA prefix is used. */ 9894 if ((ins.prefixes & PREFIX_DATA) != 0 9895 && (ins.used_prefixes & PREFIX_DATA) != 0 9896 && !ins.need_vex) 9897 ins.all_prefixes[ins.last_data_prefix] = 0; 9898 9899 /* Print the extra ins.prefixes. */ 9900 prefix_length = 0; 9901 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++) 9902 if (ins.all_prefixes[i]) 9903 { 9904 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i], 9905 orig_sizeflag); 9906 9907 if (name == NULL) 9908 abort (); 9909 prefix_length += strlen (name) + 1; 9910 if (ins.all_prefixes[i] == REX2_OPCODE) 9911 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name, 9912 (unsigned int) ins.rex2_payload); 9913 else 9914 i386_dis_printf (info, dis_style_mnemonic, "%s ", name); 9915 } 9916 9917 /* Check maximum code length. */ 9918 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH) 9919 { 9920 i386_dis_printf (info, dis_style_text, "(bad)"); 9921 ret = MAX_CODE_LENGTH; 9922 goto out; 9923 } 9924 9925 /* Calculate the number of operands this instruction has. */ 9926 op_count = 0; 9927 for (i = 0; i < MAX_OPERANDS; ++i) 9928 if (*ins.op_out[i] != '\0') 9929 ++op_count; 9930 9931 /* Calculate the number of spaces to print after the mnemonic. */ 9932 ins.obufp = ins.mnemonicendp; 9933 if (op_count > 0) 9934 { 9935 i = strlen (ins.obuf) + prefix_length; 9936 if (i < 7) 9937 i = 7 - i; 9938 else 9939 i = 1; 9940 } 9941 else 9942 i = 0; 9943 9944 /* Print the instruction mnemonic along with any trailing whitespace. */ 9945 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, ""); 9946 9947 /* The enter and bound instructions are printed with operands in the same 9948 order as the intel book; everything else is printed in reverse order. */ 9949 intel_swap_2_3 = false; 9950 if (ins.intel_syntax || ins.two_source_ops) 9951 { 9952 for (i = 0; i < MAX_OPERANDS; ++i) 9953 op_txt[i] = ins.op_out[i]; 9954 9955 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding 9956 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) 9957 { 9958 op_txt[2] = ins.op_out[3]; 9959 op_txt[3] = ins.op_out[2]; 9960 intel_swap_2_3 = true; 9961 } 9962 9963 for (i = 0; i < (MAX_OPERANDS >> 1); ++i) 9964 { 9965 bool riprel; 9966 9967 ins.op_ad = ins.op_index[i]; 9968 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i]; 9969 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad; 9970 riprel = ins.op_riprel[i]; 9971 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i]; 9972 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel; 9973 } 9974 } 9975 else 9976 { 9977 for (i = 0; i < MAX_OPERANDS; ++i) 9978 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i]; 9979 } 9980 9981 needcomma = 0; 9982 for (i = 0; i < MAX_OPERANDS; ++i) 9983 if (*op_txt[i]) 9984 { 9985 /* In Intel syntax embedded rounding / SAE are not separate operands. 9986 Instead they're attached to the prior register operand. Simply 9987 suppress emission of the comma to achieve that effect. */ 9988 switch (i & -(ins.intel_syntax && dp)) 9989 { 9990 case 2: 9991 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3) 9992 needcomma = 0; 9993 break; 9994 case 3: 9995 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3) 9996 needcomma = 0; 9997 break; 9998 } 9999 if (needcomma) 10000 i386_dis_printf (info, dis_style_text, ","); 10001 if (ins.op_index[i] != -1 && !ins.op_riprel[i]) 10002 { 10003 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]]; 10004 10005 if (ins.op_is_jump) 10006 { 10007 info->insn_info_valid = 1; 10008 info->branch_delay_insns = 0; 10009 info->data_size = 0; 10010 info->target = target; 10011 info->target2 = 0; 10012 } 10013 (*info->print_address_func) (target, info); 10014 } 10015 else 10016 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]); 10017 needcomma = 1; 10018 } 10019 10020 for (i = 0; i < MAX_OPERANDS; i++) 10021 if (ins.op_index[i] != -1 && ins.op_riprel[i]) 10022 { 10023 i386_dis_printf (info, dis_style_comment_start, " # "); 10024 (*info->print_address_func) 10025 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep) 10026 + ins.op_address[ins.op_index[i]]), 10027 info); 10028 break; 10029 } 10030 ret = ins.codep - priv.the_buffer; 10031 out: 10032 info->private_data = NULL; 10033 return ret; 10034 } 10035 10036 /* Here for backwards compatibility. When gdb stops using 10037 print_insn_i386_att and print_insn_i386_intel these functions can 10038 disappear, and print_insn_i386 be merged into print_insn. */ 10039 int 10040 print_insn_i386_att (bfd_vma pc, disassemble_info *info) 10041 { 10042 return print_insn (pc, info, 0); 10043 } 10044 10045 int 10046 print_insn_i386_intel (bfd_vma pc, disassemble_info *info) 10047 { 10048 return print_insn (pc, info, 1); 10049 } 10050 10051 int 10052 print_insn_i386 (bfd_vma pc, disassemble_info *info) 10053 { 10054 return print_insn (pc, info, -1); 10055 } 10056 10057 static const char *float_mem[] = { 10058 /* d8 */ 10059 "fadd{s|}", 10060 "fmul{s|}", 10061 "fcom{s|}", 10062 "fcomp{s|}", 10063 "fsub{s|}", 10064 "fsubr{s|}", 10065 "fdiv{s|}", 10066 "fdivr{s|}", 10067 /* d9 */ 10068 "fld{s|}", 10069 "(bad)", 10070 "fst{s|}", 10071 "fstp{s|}", 10072 "fldenv{C|C}", 10073 "fldcw", 10074 "fNstenv{C|C}", 10075 "fNstcw", 10076 /* da */ 10077 "fiadd{l|}", 10078 "fimul{l|}", 10079 "ficom{l|}", 10080 "ficomp{l|}", 10081 "fisub{l|}", 10082 "fisubr{l|}", 10083 "fidiv{l|}", 10084 "fidivr{l|}", 10085 /* db */ 10086 "fild{l|}", 10087 "fisttp{l|}", 10088 "fist{l|}", 10089 "fistp{l|}", 10090 "(bad)", 10091 "fld{t|}", 10092 "(bad)", 10093 "fstp{t|}", 10094 /* dc */ 10095 "fadd{l|}", 10096 "fmul{l|}", 10097 "fcom{l|}", 10098 "fcomp{l|}", 10099 "fsub{l|}", 10100 "fsubr{l|}", 10101 "fdiv{l|}", 10102 "fdivr{l|}", 10103 /* dd */ 10104 "fld{l|}", 10105 "fisttp{ll|}", 10106 "fst{l||}", 10107 "fstp{l|}", 10108 "frstor{C|C}", 10109 "(bad)", 10110 "fNsave{C|C}", 10111 "fNstsw", 10112 /* de */ 10113 "fiadd{s|}", 10114 "fimul{s|}", 10115 "ficom{s|}", 10116 "ficomp{s|}", 10117 "fisub{s|}", 10118 "fisubr{s|}", 10119 "fidiv{s|}", 10120 "fidivr{s|}", 10121 /* df */ 10122 "fild{s|}", 10123 "fisttp{s|}", 10124 "fist{s|}", 10125 "fistp{s|}", 10126 "fbld", 10127 "fild{ll|}", 10128 "fbstp", 10129 "fistp{ll|}", 10130 }; 10131 10132 static const unsigned char float_mem_mode[] = { 10133 /* d8 */ 10134 d_mode, 10135 d_mode, 10136 d_mode, 10137 d_mode, 10138 d_mode, 10139 d_mode, 10140 d_mode, 10141 d_mode, 10142 /* d9 */ 10143 d_mode, 10144 0, 10145 d_mode, 10146 d_mode, 10147 0, 10148 w_mode, 10149 0, 10150 w_mode, 10151 /* da */ 10152 d_mode, 10153 d_mode, 10154 d_mode, 10155 d_mode, 10156 d_mode, 10157 d_mode, 10158 d_mode, 10159 d_mode, 10160 /* db */ 10161 d_mode, 10162 d_mode, 10163 d_mode, 10164 d_mode, 10165 0, 10166 t_mode, 10167 0, 10168 t_mode, 10169 /* dc */ 10170 q_mode, 10171 q_mode, 10172 q_mode, 10173 q_mode, 10174 q_mode, 10175 q_mode, 10176 q_mode, 10177 q_mode, 10178 /* dd */ 10179 q_mode, 10180 q_mode, 10181 q_mode, 10182 q_mode, 10183 0, 10184 0, 10185 0, 10186 w_mode, 10187 /* de */ 10188 w_mode, 10189 w_mode, 10190 w_mode, 10191 w_mode, 10192 w_mode, 10193 w_mode, 10194 w_mode, 10195 w_mode, 10196 /* df */ 10197 w_mode, 10198 w_mode, 10199 w_mode, 10200 w_mode, 10201 t_mode, 10202 q_mode, 10203 t_mode, 10204 q_mode 10205 }; 10206 10207 #define ST { OP_ST, 0 } 10208 #define STi { OP_STi, 0 } 10209 10210 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 10211 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 10212 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 10213 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 10214 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 10215 #define FGRPda_5 NULL, { { NULL, 6 } }, 0 10216 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 10217 #define FGRPde_3 NULL, { { NULL, 8 } }, 0 10218 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 10219 10220 static const struct dis386 float_reg[][8] = { 10221 /* d8 */ 10222 { 10223 { "fadd", { ST, STi }, 0 }, 10224 { "fmul", { ST, STi }, 0 }, 10225 { "fcom", { STi }, 0 }, 10226 { "fcomp", { STi }, 0 }, 10227 { "fsub", { ST, STi }, 0 }, 10228 { "fsubr", { ST, STi }, 0 }, 10229 { "fdiv", { ST, STi }, 0 }, 10230 { "fdivr", { ST, STi }, 0 }, 10231 }, 10232 /* d9 */ 10233 { 10234 { "fld", { STi }, 0 }, 10235 { "fxch", { STi }, 0 }, 10236 { FGRPd9_2 }, 10237 { Bad_Opcode }, 10238 { FGRPd9_4 }, 10239 { FGRPd9_5 }, 10240 { FGRPd9_6 }, 10241 { FGRPd9_7 }, 10242 }, 10243 /* da */ 10244 { 10245 { "fcmovb", { ST, STi }, 0 }, 10246 { "fcmove", { ST, STi }, 0 }, 10247 { "fcmovbe",{ ST, STi }, 0 }, 10248 { "fcmovu", { ST, STi }, 0 }, 10249 { Bad_Opcode }, 10250 { FGRPda_5 }, 10251 { Bad_Opcode }, 10252 { Bad_Opcode }, 10253 }, 10254 /* db */ 10255 { 10256 { "fcmovnb",{ ST, STi }, 0 }, 10257 { "fcmovne",{ ST, STi }, 0 }, 10258 { "fcmovnbe",{ ST, STi }, 0 }, 10259 { "fcmovnu",{ ST, STi }, 0 }, 10260 { FGRPdb_4 }, 10261 { "fucomi", { ST, STi }, 0 }, 10262 { "fcomi", { ST, STi }, 0 }, 10263 { Bad_Opcode }, 10264 }, 10265 /* dc */ 10266 { 10267 { "fadd", { STi, ST }, 0 }, 10268 { "fmul", { STi, ST }, 0 }, 10269 { Bad_Opcode }, 10270 { Bad_Opcode }, 10271 { "fsub{!M|r}", { STi, ST }, 0 }, 10272 { "fsub{M|}", { STi, ST }, 0 }, 10273 { "fdiv{!M|r}", { STi, ST }, 0 }, 10274 { "fdiv{M|}", { STi, ST }, 0 }, 10275 }, 10276 /* dd */ 10277 { 10278 { "ffree", { STi }, 0 }, 10279 { Bad_Opcode }, 10280 { "fst", { STi }, 0 }, 10281 { "fstp", { STi }, 0 }, 10282 { "fucom", { STi }, 0 }, 10283 { "fucomp", { STi }, 0 }, 10284 { Bad_Opcode }, 10285 { Bad_Opcode }, 10286 }, 10287 /* de */ 10288 { 10289 { "faddp", { STi, ST }, 0 }, 10290 { "fmulp", { STi, ST }, 0 }, 10291 { Bad_Opcode }, 10292 { FGRPde_3 }, 10293 { "fsub{!M|r}p", { STi, ST }, 0 }, 10294 { "fsub{M|}p", { STi, ST }, 0 }, 10295 { "fdiv{!M|r}p", { STi, ST }, 0 }, 10296 { "fdiv{M|}p", { STi, ST }, 0 }, 10297 }, 10298 /* df */ 10299 { 10300 { "ffreep", { STi }, 0 }, 10301 { Bad_Opcode }, 10302 { Bad_Opcode }, 10303 { Bad_Opcode }, 10304 { FGRPdf_4 }, 10305 { "fucomip", { ST, STi }, 0 }, 10306 { "fcomip", { ST, STi }, 0 }, 10307 { Bad_Opcode }, 10308 }, 10309 }; 10310 10311 static const char *const fgrps[][8] = { 10312 /* Bad opcode 0 */ 10313 { 10314 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10315 }, 10316 10317 /* d9_2 1 */ 10318 { 10319 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10320 }, 10321 10322 /* d9_4 2 */ 10323 { 10324 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", 10325 }, 10326 10327 /* d9_5 3 */ 10328 { 10329 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", 10330 }, 10331 10332 /* d9_6 4 */ 10333 { 10334 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", 10335 }, 10336 10337 /* d9_7 5 */ 10338 { 10339 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", 10340 }, 10341 10342 /* da_5 6 */ 10343 { 10344 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10345 }, 10346 10347 /* db_4 7 */ 10348 { 10349 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", 10350 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", 10351 }, 10352 10353 /* de_3 8 */ 10354 { 10355 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10356 }, 10357 10358 /* df_4 9 */ 10359 { 10360 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10361 }, 10362 }; 10363 10364 static const char *const oszc_flags[16] = { 10365 " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}", 10366 " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}", 10367 " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}", 10368 " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}" 10369 }; 10370 10371 static const char *const scc_suffix[16] = { 10372 "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f", 10373 "l", "ge", "le", "g" 10374 }; 10375 10376 static void 10377 swap_operand (instr_info *ins) 10378 { 10379 char *p = ins->mnemonicendp; 10380 10381 if (p[-1] == '}') 10382 { 10383 while (*--p != '{') 10384 { 10385 if (p <= ins->obuf + 2) 10386 abort (); 10387 } 10388 if (p[-1] == ' ') 10389 --p; 10390 } 10391 memmove (p + 2, p, ins->mnemonicendp - p + 1); 10392 p[0] = '.'; 10393 p[1] = 's'; 10394 ins->mnemonicendp += 2; 10395 } 10396 10397 static bool 10398 dofloat (instr_info *ins, int sizeflag) 10399 { 10400 const struct dis386 *dp; 10401 unsigned char floatop = ins->codep[-1]; 10402 10403 if (ins->modrm.mod != 3) 10404 { 10405 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg; 10406 10407 putop (ins, float_mem[fp_indx], sizeflag); 10408 ins->obufp = ins->op_out[0]; 10409 ins->op_ad = 2; 10410 return OP_E (ins, float_mem_mode[fp_indx], sizeflag); 10411 } 10412 /* Skip mod/rm byte. */ 10413 MODRM_CHECK; 10414 ins->codep++; 10415 10416 dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; 10417 if (dp->name == NULL) 10418 { 10419 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag); 10420 10421 /* Instruction fnstsw is only one with strange arg. */ 10422 if (floatop == 0xdf && ins->codep[-1] == 0xe0) 10423 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax); 10424 } 10425 else 10426 { 10427 putop (ins, dp->name, sizeflag); 10428 10429 ins->obufp = ins->op_out[0]; 10430 ins->op_ad = 2; 10431 if (dp->op[0].rtn 10432 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag)) 10433 return false; 10434 10435 ins->obufp = ins->op_out[1]; 10436 ins->op_ad = 1; 10437 if (dp->op[1].rtn 10438 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag)) 10439 return false; 10440 } 10441 return true; 10442 } 10443 10444 static bool 10445 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 10446 int sizeflag ATTRIBUTE_UNUSED) 10447 { 10448 oappend_register (ins, "%st"); 10449 return true; 10450 } 10451 10452 static bool 10453 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 10454 int sizeflag ATTRIBUTE_UNUSED) 10455 { 10456 char scratch[8]; 10457 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm); 10458 10459 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 10460 abort (); 10461 oappend_register (ins, scratch); 10462 return true; 10463 } 10464 10465 /* Capital letters in template are macros. */ 10466 static int 10467 putop (instr_info *ins, const char *in_template, int sizeflag) 10468 { 10469 const char *p; 10470 int alt = 0; 10471 int cond = 1; 10472 unsigned int l = 0, len = 0; 10473 char last[4]; 10474 bool evex_printed = false; 10475 10476 /* We don't want to add any prefix or suffix to (bad), so return early. */ 10477 if (!strncmp (in_template, "(bad)", 5)) 10478 { 10479 oappend (ins, "(bad)"); 10480 *ins->obufp = 0; 10481 ins->mnemonicendp = ins->obufp; 10482 return 0; 10483 } 10484 10485 for (p = in_template; *p; p++) 10486 { 10487 if (len > l) 10488 { 10489 if (l >= sizeof (last) || !ISUPPER (*p)) 10490 abort (); 10491 last[l++] = *p; 10492 continue; 10493 } 10494 switch (*p) 10495 { 10496 default: 10497 if (ins->evex_type == evex_from_legacy && !ins->vex.nd 10498 && !(ins->rex2 & 7) && !evex_printed) 10499 { 10500 oappend (ins, "{evex} "); 10501 evex_printed = true; 10502 } 10503 *ins->obufp++ = *p; 10504 break; 10505 case '%': 10506 len++; 10507 break; 10508 case '!': 10509 cond = 0; 10510 break; 10511 case '{': 10512 if (ins->intel_syntax) 10513 { 10514 while (*++p != '|') 10515 if (*p == '}' || *p == '\0') 10516 abort (); 10517 alt = 1; 10518 } 10519 break; 10520 case '|': 10521 while (*++p != '}') 10522 { 10523 if (*p == '\0') 10524 abort (); 10525 } 10526 break; 10527 case '}': 10528 alt = 0; 10529 break; 10530 case 'A': 10531 if (ins->intel_syntax) 10532 break; 10533 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) 10534 || (sizeflag & SUFFIX_ALWAYS)) 10535 *ins->obufp++ = 'b'; 10536 break; 10537 case 'B': 10538 if (l == 0) 10539 { 10540 case_B: 10541 if (ins->intel_syntax) 10542 break; 10543 if (sizeflag & SUFFIX_ALWAYS) 10544 *ins->obufp++ = 'b'; 10545 } 10546 else if (l == 1 && last[0] == 'L') 10547 { 10548 if (ins->address_mode == mode_64bit 10549 && !(ins->prefixes & PREFIX_ADDR)) 10550 { 10551 *ins->obufp++ = 'a'; 10552 *ins->obufp++ = 'b'; 10553 *ins->obufp++ = 's'; 10554 } 10555 10556 goto case_B; 10557 } 10558 else if (l && last[0] == 'X') 10559 { 10560 if (!ins->vex.w) 10561 oappend (ins, "bf16"); 10562 else 10563 oappend (ins, "{bad}"); 10564 } 10565 else 10566 abort (); 10567 break; 10568 case 'C': 10569 if (l == 1 && last[0] == 'C') 10570 { 10571 /* Condition code (taken from the map-0 Jcc entries). */ 10572 for (const char *q = dis386[0x70 | ins->condition_code].name + 1; 10573 ISLOWER(*q); ++q) 10574 *ins->obufp++ = *q; 10575 break; 10576 } 10577 else if (l == 1 && last[0] == 'S') 10578 { 10579 /* Add scc suffix. */ 10580 oappend (ins, scc_suffix[ins->vex.scc]); 10581 10582 /* For SCC insns, the ND bit is required to be set to 0. */ 10583 if (ins->vex.nd) 10584 oappend (ins, "(bad)"); 10585 10586 /* These bits have been consumed and should be cleared or restored 10587 to default values. */ 10588 ins->vex.v = 1; 10589 ins->vex.nf = false; 10590 ins->vex.mask_register_specifier = 0; 10591 break; 10592 } 10593 10594 if (l) 10595 abort (); 10596 if (ins->intel_syntax && !alt) 10597 break; 10598 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 10599 { 10600 if (sizeflag & DFLAG) 10601 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10602 else 10603 *ins->obufp++ = ins->intel_syntax ? 'w' : 's'; 10604 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10605 } 10606 break; 10607 case 'D': 10608 if (l == 1) 10609 { 10610 switch (last[0]) 10611 { 10612 case 'X': 10613 if (!ins->vex.evex || ins->vex.w) 10614 *ins->obufp++ = 'd'; 10615 else 10616 oappend (ins, "{bad}"); 10617 break; 10618 default: 10619 abort (); 10620 } 10621 break; 10622 } 10623 if (l) 10624 abort (); 10625 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 10626 break; 10627 USED_REX (REX_W); 10628 if (ins->modrm.mod == 3) 10629 { 10630 if (ins->rex & REX_W) 10631 *ins->obufp++ = 'q'; 10632 else 10633 { 10634 if (sizeflag & DFLAG) 10635 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10636 else 10637 *ins->obufp++ = 'w'; 10638 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10639 } 10640 } 10641 else 10642 *ins->obufp++ = 'w'; 10643 break; 10644 case 'E': 10645 if (l == 1) 10646 { 10647 switch (last[0]) 10648 { 10649 case 'M': 10650 if (ins->modrm.mod != 3) 10651 break; 10652 /* Fall through. */ 10653 case 'X': 10654 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 10655 || (ins->rex2 & 7) 10656 || (ins->modrm.mod == 3 && (ins->rex & REX_X)) 10657 || !ins->vex.v || ins->vex.mask_register_specifier) 10658 break; 10659 /* AVX512 extends a number of V*D insns to also have V*Q variants, 10660 merely distinguished by EVEX.W. Look for a use of the 10661 respective macro. */ 10662 if (ins->vex.w) 10663 { 10664 const char *pct = strchr (p + 1, '%'); 10665 10666 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q') 10667 break; 10668 } 10669 *ins->obufp++ = '{'; 10670 *ins->obufp++ = 'e'; 10671 *ins->obufp++ = 'v'; 10672 *ins->obufp++ = 'e'; 10673 *ins->obufp++ = 'x'; 10674 *ins->obufp++ = '}'; 10675 *ins->obufp++ = ' '; 10676 break; 10677 case 'N': 10678 /* Skip printing {evex} for some special instructions in MAP4. */ 10679 evex_printed = true; 10680 break; 10681 default: 10682 abort (); 10683 } 10684 break; 10685 } 10686 /* For jcxz/jecxz */ 10687 if (ins->address_mode == mode_64bit) 10688 { 10689 if (sizeflag & AFLAG) 10690 *ins->obufp++ = 'r'; 10691 else 10692 *ins->obufp++ = 'e'; 10693 } 10694 else 10695 if (sizeflag & AFLAG) 10696 *ins->obufp++ = 'e'; 10697 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 10698 break; 10699 case 'F': 10700 if (l == 0) 10701 { 10702 if (ins->intel_syntax) 10703 break; 10704 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) 10705 { 10706 if (sizeflag & AFLAG) 10707 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; 10708 else 10709 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w'; 10710 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 10711 } 10712 } 10713 else if (l == 1 && last[0] == 'C') 10714 { 10715 if (ins->vex.nd && !ins->vex.nf) 10716 break; 10717 *ins->obufp++ = 'c'; 10718 *ins->obufp++ = 'f'; 10719 /* Skip printing {evex} */ 10720 evex_printed = true; 10721 } 10722 else if (l == 1 && last[0] == 'N') 10723 { 10724 if (ins->vex.nf) 10725 { 10726 oappend (ins, "{nf} "); 10727 /* This bit needs to be cleared after it is consumed. */ 10728 ins->vex.nf = false; 10729 evex_printed = true; 10730 } 10731 else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7) 10732 && ins->vex.v) 10733 { 10734 oappend (ins, "{evex} "); 10735 evex_printed = true; 10736 } 10737 } 10738 else if (l == 1 && last[0] == 'D') 10739 { 10740 /* Get oszc flags value from register_specifier. */ 10741 int oszc_value = ~ins->vex.register_specifier & 0xf; 10742 10743 /* Add {dfv=of, sf, zf, cf} flags. */ 10744 oappend (ins, oszc_flags[oszc_value]); 10745 10746 /* These bits have been consumed and should be cleared. */ 10747 ins->vex.register_specifier = 0; 10748 } 10749 else 10750 abort (); 10751 break; 10752 case 'G': 10753 if (ins->intel_syntax || (ins->obufp[-1] != 's' 10754 && !(sizeflag & SUFFIX_ALWAYS))) 10755 break; 10756 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 10757 *ins->obufp++ = 'l'; 10758 else 10759 *ins->obufp++ = 'w'; 10760 if (!(ins->rex & REX_W)) 10761 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10762 break; 10763 case 'H': 10764 if (l == 0) 10765 { 10766 if (ins->intel_syntax) 10767 break; 10768 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS 10769 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) 10770 { 10771 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS); 10772 *ins->obufp++ = ','; 10773 *ins->obufp++ = 'p'; 10774 10775 /* Set active_seg_prefix even if not set in 64-bit mode 10776 because here it is a valid branch hint. */ 10777 if (ins->prefixes & PREFIX_DS) 10778 { 10779 ins->active_seg_prefix = PREFIX_DS; 10780 *ins->obufp++ = 't'; 10781 } 10782 else 10783 { 10784 ins->active_seg_prefix = PREFIX_CS; 10785 *ins->obufp++ = 'n'; 10786 } 10787 } 10788 } 10789 else if (l == 1 && last[0] == 'X') 10790 { 10791 if (!ins->vex.w) 10792 *ins->obufp++ = 'h'; 10793 else 10794 oappend (ins, "{bad}"); 10795 } 10796 else 10797 abort (); 10798 break; 10799 case 'K': 10800 USED_REX (REX_W); 10801 if (ins->rex & REX_W) 10802 *ins->obufp++ = 'q'; 10803 else 10804 *ins->obufp++ = 'd'; 10805 break; 10806 case 'L': 10807 if (ins->intel_syntax) 10808 break; 10809 if (sizeflag & SUFFIX_ALWAYS) 10810 { 10811 if (ins->rex & REX_W) 10812 *ins->obufp++ = 'q'; 10813 else 10814 *ins->obufp++ = 'l'; 10815 } 10816 break; 10817 case 'M': 10818 if (ins->intel_mnemonic != cond) 10819 *ins->obufp++ = 'r'; 10820 break; 10821 case 'N': 10822 if ((ins->prefixes & PREFIX_FWAIT) == 0) 10823 *ins->obufp++ = 'n'; 10824 else 10825 ins->used_prefixes |= PREFIX_FWAIT; 10826 break; 10827 case 'O': 10828 USED_REX (REX_W); 10829 if (ins->rex & REX_W) 10830 *ins->obufp++ = 'o'; 10831 else if (ins->intel_syntax && (sizeflag & DFLAG)) 10832 *ins->obufp++ = 'q'; 10833 else 10834 *ins->obufp++ = 'd'; 10835 if (!(ins->rex & REX_W)) 10836 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10837 break; 10838 case '@': 10839 if (ins->address_mode == mode_64bit 10840 && (ins->isa64 == intel64 || (ins->rex & REX_W) 10841 || !(ins->prefixes & PREFIX_DATA))) 10842 { 10843 if (sizeflag & SUFFIX_ALWAYS) 10844 *ins->obufp++ = 'q'; 10845 break; 10846 } 10847 /* Fall through. */ 10848 case 'P': 10849 if (l == 0) 10850 { 10851 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W)) 10852 { 10853 /* For pushp and popp, p is printed and do not print {rex2} 10854 for them. */ 10855 *ins->obufp++ = 'p'; 10856 ins->rex2 |= REX2_SPECIAL; 10857 break; 10858 } 10859 10860 /* For "!P" print nothing else in Intel syntax. */ 10861 if (!cond && ins->intel_syntax) 10862 break; 10863 10864 if ((ins->modrm.mod == 3 || !cond) 10865 && !(sizeflag & SUFFIX_ALWAYS)) 10866 break; 10867 /* Fall through. */ 10868 case 'T': 10869 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA)) 10870 || ((sizeflag & SUFFIX_ALWAYS) 10871 && ins->address_mode != mode_64bit)) 10872 { 10873 *ins->obufp++ = (sizeflag & DFLAG) 10874 ? ins->intel_syntax ? 'd' : 'l' : 'w'; 10875 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10876 } 10877 else if (sizeflag & SUFFIX_ALWAYS) 10878 *ins->obufp++ = 'q'; 10879 } 10880 else if (l == 1 && last[0] == 'L') 10881 { 10882 if ((ins->prefixes & PREFIX_DATA) 10883 || (ins->rex & REX_W) 10884 || (sizeflag & SUFFIX_ALWAYS)) 10885 { 10886 USED_REX (REX_W); 10887 if (ins->rex & REX_W) 10888 *ins->obufp++ = 'q'; 10889 else 10890 { 10891 if (sizeflag & DFLAG) 10892 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10893 else 10894 *ins->obufp++ = 'w'; 10895 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10896 } 10897 } 10898 } 10899 else 10900 abort (); 10901 break; 10902 case 'Q': 10903 if (l == 0) 10904 { 10905 if (ins->intel_syntax && !alt) 10906 break; 10907 USED_REX (REX_W); 10908 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) 10909 || (sizeflag & SUFFIX_ALWAYS)) 10910 { 10911 if (ins->rex & REX_W) 10912 *ins->obufp++ = 'q'; 10913 else 10914 { 10915 if (sizeflag & DFLAG) 10916 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10917 else 10918 *ins->obufp++ = 'w'; 10919 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10920 } 10921 } 10922 } 10923 else if (l == 1 && last[0] == 'D') 10924 *ins->obufp++ = ins->vex.w ? 'q' : 'd'; 10925 else if (l == 1 && last[0] == 'L') 10926 { 10927 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) 10928 : ins->address_mode != mode_64bit) 10929 break; 10930 if ((ins->rex & REX_W)) 10931 { 10932 USED_REX (REX_W); 10933 *ins->obufp++ = 'q'; 10934 } 10935 else if ((ins->address_mode == mode_64bit && cond) 10936 || (sizeflag & SUFFIX_ALWAYS)) 10937 *ins->obufp++ = ins->intel_syntax? 'd' : 'l'; 10938 } 10939 else 10940 abort (); 10941 break; 10942 case 'R': 10943 USED_REX (REX_W); 10944 if (ins->rex & REX_W) 10945 *ins->obufp++ = 'q'; 10946 else if (sizeflag & DFLAG) 10947 { 10948 if (ins->intel_syntax) 10949 *ins->obufp++ = 'd'; 10950 else 10951 *ins->obufp++ = 'l'; 10952 } 10953 else 10954 *ins->obufp++ = 'w'; 10955 if (ins->intel_syntax && !p[1] 10956 && ((ins->rex & REX_W) || (sizeflag & DFLAG))) 10957 *ins->obufp++ = 'e'; 10958 if (!(ins->rex & REX_W)) 10959 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10960 break; 10961 case 'S': 10962 if (l == 0) 10963 { 10964 case_S: 10965 if (ins->intel_syntax) 10966 break; 10967 if (sizeflag & SUFFIX_ALWAYS) 10968 { 10969 if (ins->rex & REX_W) 10970 *ins->obufp++ = 'q'; 10971 else 10972 { 10973 if (sizeflag & DFLAG) 10974 *ins->obufp++ = 'l'; 10975 else 10976 *ins->obufp++ = 'w'; 10977 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10978 } 10979 } 10980 break; 10981 } 10982 if (l != 1) 10983 abort (); 10984 switch (last[0]) 10985 { 10986 case 'L': 10987 if (ins->address_mode == mode_64bit 10988 && !(ins->prefixes & PREFIX_ADDR)) 10989 { 10990 *ins->obufp++ = 'a'; 10991 *ins->obufp++ = 'b'; 10992 *ins->obufp++ = 's'; 10993 } 10994 10995 goto case_S; 10996 case 'X': 10997 if (!ins->vex.evex || !ins->vex.w) 10998 *ins->obufp++ = 's'; 10999 else 11000 oappend (ins, "{bad}"); 11001 break; 11002 default: 11003 abort (); 11004 } 11005 break; 11006 case 'U': 11007 if (l == 1 && (last[0] == 'Z')) 11008 { 11009 /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is 11010 used to control whether its destination register has its upper 11011 bits zeroed. */ 11012 if (ins->vex.nd) 11013 oappend (ins, "zu"); 11014 } 11015 else 11016 abort (); 11017 break; 11018 case 'V': 11019 if (l == 0) 11020 { 11021 if (ins->need_vex) 11022 *ins->obufp++ = 'v'; 11023 } 11024 else if (l == 1) 11025 { 11026 switch (last[0]) 11027 { 11028 case 'X': 11029 if (ins->vex.evex) 11030 break; 11031 *ins->obufp++ = '{'; 11032 *ins->obufp++ = 'v'; 11033 *ins->obufp++ = 'e'; 11034 *ins->obufp++ = 'x'; 11035 *ins->obufp++ = '}'; 11036 *ins->obufp++ = ' '; 11037 break; 11038 case 'L': 11039 if (ins->rex & REX_W) 11040 { 11041 *ins->obufp++ = 'a'; 11042 *ins->obufp++ = 'b'; 11043 *ins->obufp++ = 's'; 11044 } 11045 goto case_S; 11046 default: 11047 abort (); 11048 } 11049 } 11050 else 11051 abort (); 11052 break; 11053 case 'W': 11054 if (l == 0) 11055 { 11056 /* operand size flag for cwtl, cbtw */ 11057 USED_REX (REX_W); 11058 if (ins->rex & REX_W) 11059 { 11060 if (ins->intel_syntax) 11061 *ins->obufp++ = 'd'; 11062 else 11063 *ins->obufp++ = 'l'; 11064 } 11065 else if (sizeflag & DFLAG) 11066 *ins->obufp++ = 'w'; 11067 else 11068 *ins->obufp++ = 'b'; 11069 if (!(ins->rex & REX_W)) 11070 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11071 } 11072 else if (l == 1) 11073 { 11074 if (!ins->need_vex) 11075 abort (); 11076 if (last[0] == 'X') 11077 *ins->obufp++ = ins->vex.w ? 'd': 's'; 11078 else if (last[0] == 'B') 11079 *ins->obufp++ = ins->vex.w ? 'w': 'b'; 11080 else 11081 abort (); 11082 } 11083 else 11084 abort (); 11085 break; 11086 case 'X': 11087 if (l != 0) 11088 abort (); 11089 if (ins->need_vex 11090 ? ins->vex.prefix == DATA_PREFIX_OPCODE 11091 : ins->prefixes & PREFIX_DATA) 11092 { 11093 *ins->obufp++ = 'd'; 11094 ins->used_prefixes |= PREFIX_DATA; 11095 } 11096 else 11097 *ins->obufp++ = 's'; 11098 break; 11099 case 'Y': 11100 if (l == 0) 11101 { 11102 if (ins->vex.mask_register_specifier) 11103 ins->illegal_masking = true; 11104 } 11105 else if (l == 1 && last[0] == 'X') 11106 { 11107 if (!ins->need_vex) 11108 break; 11109 if (ins->intel_syntax 11110 || ((ins->modrm.mod == 3 || ins->vex.b) 11111 && !(sizeflag & SUFFIX_ALWAYS))) 11112 break; 11113 switch (ins->vex.length) 11114 { 11115 case 128: 11116 *ins->obufp++ = 'x'; 11117 break; 11118 case 256: 11119 *ins->obufp++ = 'y'; 11120 break; 11121 case 512: 11122 if (!ins->vex.evex) 11123 default: 11124 abort (); 11125 } 11126 } 11127 else 11128 abort (); 11129 break; 11130 case 'Z': 11131 if (l == 0) 11132 { 11133 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ 11134 ins->modrm.mod = 3; 11135 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 11136 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; 11137 } 11138 else if (l == 1 && last[0] == 'X') 11139 { 11140 if (!ins->vex.evex) 11141 abort (); 11142 if (ins->intel_syntax 11143 || ((ins->modrm.mod == 3 || ins->vex.b) 11144 && !(sizeflag & SUFFIX_ALWAYS))) 11145 break; 11146 switch (ins->vex.length) 11147 { 11148 case 128: 11149 *ins->obufp++ = 'x'; 11150 break; 11151 case 256: 11152 *ins->obufp++ = 'y'; 11153 break; 11154 case 512: 11155 *ins->obufp++ = 'z'; 11156 break; 11157 default: 11158 abort (); 11159 } 11160 } 11161 else 11162 abort (); 11163 break; 11164 case '^': 11165 if (ins->intel_syntax) 11166 break; 11167 if (ins->isa64 == intel64 && (ins->rex & REX_W)) 11168 { 11169 USED_REX (REX_W); 11170 *ins->obufp++ = 'q'; 11171 break; 11172 } 11173 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 11174 { 11175 if (sizeflag & DFLAG) 11176 *ins->obufp++ = 'l'; 11177 else 11178 *ins->obufp++ = 'w'; 11179 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11180 } 11181 break; 11182 } 11183 11184 if (len == l) 11185 len = l = 0; 11186 } 11187 *ins->obufp = 0; 11188 ins->mnemonicendp = ins->obufp; 11189 return 0; 11190 } 11191 11192 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that 11193 the buffer pointed to by INS->obufp has space. A style marker is made 11194 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex 11195 digit, followed by another STYLE_MARKER_CHAR. This function assumes 11196 that the number of styles is not greater than 16. */ 11197 11198 static void 11199 oappend_insert_style (instr_info *ins, enum disassembler_style style) 11200 { 11201 unsigned num = (unsigned) style; 11202 11203 /* We currently assume that STYLE can be encoded as a single hex 11204 character. If more styles are added then this might start to fail, 11205 and we'll need to expand this code. */ 11206 if (num > 0xf) 11207 abort (); 11208 11209 *ins->obufp++ = STYLE_MARKER_CHAR; 11210 *ins->obufp++ = (num < 10 ? ('0' + num) 11211 : ((num < 16) ? ('a' + (num - 10)) : '0')); 11212 *ins->obufp++ = STYLE_MARKER_CHAR; 11213 11214 /* This final null character is not strictly necessary, after inserting a 11215 style marker we should always be inserting some additional content. 11216 However, having the buffer null terminated doesn't cost much, and make 11217 it easier to debug what's going on. Also, if we do ever forget to add 11218 any additional content after this style marker, then the buffer will 11219 still be well formed. */ 11220 *ins->obufp = '\0'; 11221 } 11222 11223 static void 11224 oappend_with_style (instr_info *ins, const char *s, 11225 enum disassembler_style style) 11226 { 11227 oappend_insert_style (ins, style); 11228 ins->obufp = stpcpy (ins->obufp, s); 11229 } 11230 11231 /* Add a single character C to the buffer pointer to by INS->obufp, marking 11232 the style for the character as STYLE. */ 11233 11234 static void 11235 oappend_char_with_style (instr_info *ins, const char c, 11236 enum disassembler_style style) 11237 { 11238 oappend_insert_style (ins, style); 11239 *ins->obufp++ = c; 11240 *ins->obufp = '\0'; 11241 } 11242 11243 /* Like oappend_char_with_style, but always uses dis_style_text. */ 11244 11245 static void 11246 oappend_char (instr_info *ins, const char c) 11247 { 11248 oappend_char_with_style (ins, c, dis_style_text); 11249 } 11250 11251 static void 11252 append_seg (instr_info *ins) 11253 { 11254 /* Only print the active segment register. */ 11255 if (!ins->active_seg_prefix) 11256 return; 11257 11258 ins->used_prefixes |= ins->active_seg_prefix; 11259 switch (ins->active_seg_prefix) 11260 { 11261 case PREFIX_CS: 11262 oappend_register (ins, att_names_seg[1]); 11263 break; 11264 case PREFIX_DS: 11265 oappend_register (ins, att_names_seg[3]); 11266 break; 11267 case PREFIX_SS: 11268 oappend_register (ins, att_names_seg[2]); 11269 break; 11270 case PREFIX_ES: 11271 oappend_register (ins, att_names_seg[0]); 11272 break; 11273 case PREFIX_FS: 11274 oappend_register (ins, att_names_seg[4]); 11275 break; 11276 case PREFIX_GS: 11277 oappend_register (ins, att_names_seg[5]); 11278 break; 11279 default: 11280 break; 11281 } 11282 oappend_char (ins, ':'); 11283 } 11284 11285 static void 11286 print_operand_value (instr_info *ins, bfd_vma disp, 11287 enum disassembler_style style) 11288 { 11289 char tmp[30]; 11290 11291 if (ins->address_mode != mode_64bit) 11292 disp &= 0xffffffff; 11293 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp); 11294 oappend_with_style (ins, tmp, style); 11295 } 11296 11297 /* Like oappend, but called for immediate operands. */ 11298 11299 static void 11300 oappend_immediate (instr_info *ins, bfd_vma imm) 11301 { 11302 if (!ins->intel_syntax) 11303 oappend_char_with_style (ins, '$', dis_style_immediate); 11304 print_operand_value (ins, imm, dis_style_immediate); 11305 } 11306 11307 /* Put DISP in BUF as signed hex number. */ 11308 11309 static void 11310 print_displacement (instr_info *ins, bfd_signed_vma val) 11311 { 11312 char tmp[30]; 11313 11314 if (val < 0) 11315 { 11316 oappend_char_with_style (ins, '-', dis_style_address_offset); 11317 val = (bfd_vma) 0 - val; 11318 11319 /* Check for possible overflow. */ 11320 if (val < 0) 11321 { 11322 switch (ins->address_mode) 11323 { 11324 case mode_64bit: 11325 oappend_with_style (ins, "0x8000000000000000", 11326 dis_style_address_offset); 11327 break; 11328 case mode_32bit: 11329 oappend_with_style (ins, "0x80000000", 11330 dis_style_address_offset); 11331 break; 11332 case mode_16bit: 11333 oappend_with_style (ins, "0x8000", 11334 dis_style_address_offset); 11335 break; 11336 } 11337 return; 11338 } 11339 } 11340 11341 sprintf (tmp, "0x%" PRIx64, (int64_t) val); 11342 oappend_with_style (ins, tmp, dis_style_address_offset); 11343 } 11344 11345 static void 11346 intel_operand_size (instr_info *ins, int bytemode, int sizeflag) 11347 { 11348 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */ 11349 if (ins->vex.b && ins->evex_type == evex_default) 11350 { 11351 if (!ins->vex.no_broadcast) 11352 switch (bytemode) 11353 { 11354 case x_mode: 11355 case evex_half_bcst_xmmq_mode: 11356 if (ins->vex.w) 11357 oappend (ins, "QWORD BCST "); 11358 else 11359 oappend (ins, "DWORD BCST "); 11360 break; 11361 case xh_mode: 11362 case evex_half_bcst_xmmqh_mode: 11363 case evex_half_bcst_xmmqdh_mode: 11364 oappend (ins, "WORD BCST "); 11365 break; 11366 default: 11367 ins->vex.no_broadcast = true; 11368 break; 11369 } 11370 return; 11371 } 11372 switch (bytemode) 11373 { 11374 case b_mode: 11375 case b_swap_mode: 11376 case db_mode: 11377 oappend (ins, "BYTE PTR "); 11378 break; 11379 case w_mode: 11380 case w_swap_mode: 11381 case dw_mode: 11382 oappend (ins, "WORD PTR "); 11383 break; 11384 case indir_v_mode: 11385 if (ins->address_mode == mode_64bit && ins->isa64 == intel64) 11386 { 11387 oappend (ins, "QWORD PTR "); 11388 break; 11389 } 11390 /* Fall through. */ 11391 case stack_v_mode: 11392 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) 11393 || (ins->rex & REX_W))) 11394 { 11395 oappend (ins, "QWORD PTR "); 11396 break; 11397 } 11398 /* Fall through. */ 11399 case v_mode: 11400 case v_swap_mode: 11401 case dq_mode: 11402 USED_REX (REX_W); 11403 if (ins->rex & REX_W) 11404 oappend (ins, "QWORD PTR "); 11405 else if (bytemode == dq_mode) 11406 oappend (ins, "DWORD PTR "); 11407 else 11408 { 11409 if (sizeflag & DFLAG) 11410 oappend (ins, "DWORD PTR "); 11411 else 11412 oappend (ins, "WORD PTR "); 11413 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11414 } 11415 break; 11416 case z_mode: 11417 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 11418 *ins->obufp++ = 'D'; 11419 oappend (ins, "WORD PTR "); 11420 if (!(ins->rex & REX_W)) 11421 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11422 break; 11423 case a_mode: 11424 if (sizeflag & DFLAG) 11425 oappend (ins, "QWORD PTR "); 11426 else 11427 oappend (ins, "DWORD PTR "); 11428 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11429 break; 11430 case movsxd_mode: 11431 if (!(sizeflag & DFLAG) && ins->isa64 == intel64) 11432 oappend (ins, "WORD PTR "); 11433 else 11434 oappend (ins, "DWORD PTR "); 11435 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11436 break; 11437 case d_mode: 11438 case d_swap_mode: 11439 oappend (ins, "DWORD PTR "); 11440 break; 11441 case q_mode: 11442 case q_swap_mode: 11443 oappend (ins, "QWORD PTR "); 11444 break; 11445 case m_mode: 11446 if (ins->address_mode == mode_64bit) 11447 oappend (ins, "QWORD PTR "); 11448 else 11449 oappend (ins, "DWORD PTR "); 11450 break; 11451 case f_mode: 11452 if (sizeflag & DFLAG) 11453 oappend (ins, "FWORD PTR "); 11454 else 11455 oappend (ins, "DWORD PTR "); 11456 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11457 break; 11458 case t_mode: 11459 oappend (ins, "TBYTE PTR "); 11460 break; 11461 case x_mode: 11462 case xh_mode: 11463 case x_swap_mode: 11464 case evex_x_gscat_mode: 11465 case evex_x_nobcst_mode: 11466 case bw_unit_mode: 11467 if (ins->need_vex) 11468 { 11469 switch (ins->vex.length) 11470 { 11471 case 128: 11472 oappend (ins, "XMMWORD PTR "); 11473 break; 11474 case 256: 11475 oappend (ins, "YMMWORD PTR "); 11476 break; 11477 case 512: 11478 oappend (ins, "ZMMWORD PTR "); 11479 break; 11480 default: 11481 abort (); 11482 } 11483 } 11484 else 11485 oappend (ins, "XMMWORD PTR "); 11486 break; 11487 case xmm_mode: 11488 oappend (ins, "XMMWORD PTR "); 11489 break; 11490 case ymm_mode: 11491 oappend (ins, "YMMWORD PTR "); 11492 break; 11493 case xmmq_mode: 11494 case evex_half_bcst_xmmqh_mode: 11495 case evex_half_bcst_xmmq_mode: 11496 switch (ins->vex.length) 11497 { 11498 case 0: 11499 case 128: 11500 oappend (ins, "QWORD PTR "); 11501 break; 11502 case 256: 11503 oappend (ins, "XMMWORD PTR "); 11504 break; 11505 case 512: 11506 oappend (ins, "YMMWORD PTR "); 11507 break; 11508 default: 11509 abort (); 11510 } 11511 break; 11512 case xmmdw_mode: 11513 if (!ins->need_vex) 11514 abort (); 11515 11516 switch (ins->vex.length) 11517 { 11518 case 128: 11519 oappend (ins, "WORD PTR "); 11520 break; 11521 case 256: 11522 oappend (ins, "DWORD PTR "); 11523 break; 11524 case 512: 11525 oappend (ins, "QWORD PTR "); 11526 break; 11527 default: 11528 abort (); 11529 } 11530 break; 11531 case xmmqd_mode: 11532 case evex_half_bcst_xmmqdh_mode: 11533 if (!ins->need_vex) 11534 abort (); 11535 11536 switch (ins->vex.length) 11537 { 11538 case 128: 11539 oappend (ins, "DWORD PTR "); 11540 break; 11541 case 256: 11542 oappend (ins, "QWORD PTR "); 11543 break; 11544 case 512: 11545 oappend (ins, "XMMWORD PTR "); 11546 break; 11547 default: 11548 abort (); 11549 } 11550 break; 11551 case ymmq_mode: 11552 if (!ins->need_vex) 11553 abort (); 11554 11555 switch (ins->vex.length) 11556 { 11557 case 128: 11558 oappend (ins, "QWORD PTR "); 11559 break; 11560 case 256: 11561 oappend (ins, "YMMWORD PTR "); 11562 break; 11563 case 512: 11564 oappend (ins, "ZMMWORD PTR "); 11565 break; 11566 default: 11567 abort (); 11568 } 11569 break; 11570 case o_mode: 11571 oappend (ins, "OWORD PTR "); 11572 break; 11573 case vex_vsib_d_w_dq_mode: 11574 case vex_vsib_q_w_dq_mode: 11575 if (!ins->need_vex) 11576 abort (); 11577 if (ins->vex.w) 11578 oappend (ins, "QWORD PTR "); 11579 else 11580 oappend (ins, "DWORD PTR "); 11581 break; 11582 case mask_bd_mode: 11583 if (!ins->need_vex || ins->vex.length != 128) 11584 abort (); 11585 if (ins->vex.w) 11586 oappend (ins, "DWORD PTR "); 11587 else 11588 oappend (ins, "BYTE PTR "); 11589 break; 11590 case mask_mode: 11591 if (!ins->need_vex) 11592 abort (); 11593 if (ins->vex.w) 11594 oappend (ins, "QWORD PTR "); 11595 else 11596 oappend (ins, "WORD PTR "); 11597 break; 11598 case v_bnd_mode: 11599 case v_bndmk_mode: 11600 default: 11601 break; 11602 } 11603 } 11604 11605 static void 11606 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, 11607 int bytemode, int sizeflag) 11608 { 11609 const char (*names)[8]; 11610 11611 /* Masking is invalid for insns with GPR destination. Set the flag uniformly, 11612 as the consumer will inspect it only for the destination operand. */ 11613 if (bytemode != mask_mode && ins->vex.mask_register_specifier) 11614 ins->illegal_masking = true; 11615 11616 USED_REX (rexmask); 11617 if (ins->rex & rexmask) 11618 reg += 8; 11619 if (ins->rex2 & rexmask) 11620 reg += 16; 11621 11622 switch (bytemode) 11623 { 11624 case b_mode: 11625 case b_swap_mode: 11626 if (reg & 4) 11627 USED_REX (0); 11628 if (ins->rex || ins->rex2) 11629 names = att_names8rex; 11630 else 11631 names = att_names8; 11632 break; 11633 case w_mode: 11634 names = att_names16; 11635 break; 11636 case d_mode: 11637 case dw_mode: 11638 case db_mode: 11639 names = att_names32; 11640 break; 11641 case q_mode: 11642 names = att_names64; 11643 break; 11644 case m_mode: 11645 case v_bnd_mode: 11646 names = ins->address_mode == mode_64bit ? att_names64 : att_names32; 11647 break; 11648 case bnd_mode: 11649 case bnd_swap_mode: 11650 if (reg > 0x3) 11651 { 11652 oappend (ins, "(bad)"); 11653 return; 11654 } 11655 names = att_names_bnd; 11656 break; 11657 case indir_v_mode: 11658 if (ins->address_mode == mode_64bit && ins->isa64 == intel64) 11659 { 11660 names = att_names64; 11661 break; 11662 } 11663 /* Fall through. */ 11664 case stack_v_mode: 11665 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) 11666 || (ins->rex & REX_W))) 11667 { 11668 names = att_names64; 11669 break; 11670 } 11671 bytemode = v_mode; 11672 /* Fall through. */ 11673 case v_mode: 11674 case v_swap_mode: 11675 case dq_mode: 11676 USED_REX (REX_W); 11677 if (ins->rex & REX_W) 11678 names = att_names64; 11679 else if (bytemode != v_mode && bytemode != v_swap_mode) 11680 names = att_names32; 11681 else 11682 { 11683 if (sizeflag & DFLAG) 11684 names = att_names32; 11685 else 11686 names = att_names16; 11687 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11688 } 11689 break; 11690 case movsxd_mode: 11691 if (!(sizeflag & DFLAG) && ins->isa64 == intel64) 11692 names = att_names16; 11693 else 11694 names = att_names32; 11695 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11696 break; 11697 case va_mode: 11698 names = (ins->address_mode == mode_64bit 11699 ? att_names64 : att_names32); 11700 if (!(ins->prefixes & PREFIX_ADDR)) 11701 names = (ins->address_mode == mode_16bit 11702 ? att_names16 : names); 11703 else 11704 { 11705 /* Remove "addr16/addr32". */ 11706 ins->all_prefixes[ins->last_addr_prefix] = 0; 11707 names = (ins->address_mode != mode_32bit 11708 ? att_names32 : att_names16); 11709 ins->used_prefixes |= PREFIX_ADDR; 11710 } 11711 break; 11712 case mask_bd_mode: 11713 case mask_mode: 11714 if (reg > 0x7) 11715 { 11716 oappend (ins, "(bad)"); 11717 return; 11718 } 11719 names = att_names_mask; 11720 break; 11721 case 0: 11722 return; 11723 default: 11724 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 11725 return; 11726 } 11727 oappend_register (ins, names[reg]); 11728 } 11729 11730 static bool 11731 get8s (instr_info *ins, bfd_vma *res) 11732 { 11733 if (!fetch_code (ins->info, ins->codep + 1)) 11734 return false; 11735 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80; 11736 return true; 11737 } 11738 11739 static bool 11740 get16 (instr_info *ins, bfd_vma *res) 11741 { 11742 if (!fetch_code (ins->info, ins->codep + 2)) 11743 return false; 11744 *res = *ins->codep++; 11745 *res |= (bfd_vma) *ins->codep++ << 8; 11746 return true; 11747 } 11748 11749 static bool 11750 get16s (instr_info *ins, bfd_vma *res) 11751 { 11752 if (!get16 (ins, res)) 11753 return false; 11754 *res = (*res ^ 0x8000) - 0x8000; 11755 return true; 11756 } 11757 11758 static bool 11759 get32 (instr_info *ins, bfd_vma *res) 11760 { 11761 if (!fetch_code (ins->info, ins->codep + 4)) 11762 return false; 11763 *res = *ins->codep++; 11764 *res |= (bfd_vma) *ins->codep++ << 8; 11765 *res |= (bfd_vma) *ins->codep++ << 16; 11766 *res |= (bfd_vma) *ins->codep++ << 24; 11767 return true; 11768 } 11769 11770 static bool 11771 get32s (instr_info *ins, bfd_vma *res) 11772 { 11773 if (!get32 (ins, res)) 11774 return false; 11775 11776 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); 11777 11778 return true; 11779 } 11780 11781 static bool 11782 get64 (instr_info *ins, uint64_t *res) 11783 { 11784 unsigned int a; 11785 unsigned int b; 11786 11787 if (!fetch_code (ins->info, ins->codep + 8)) 11788 return false; 11789 a = *ins->codep++; 11790 a |= (unsigned int) *ins->codep++ << 8; 11791 a |= (unsigned int) *ins->codep++ << 16; 11792 a |= (unsigned int) *ins->codep++ << 24; 11793 b = *ins->codep++; 11794 b |= (unsigned int) *ins->codep++ << 8; 11795 b |= (unsigned int) *ins->codep++ << 16; 11796 b |= (unsigned int) *ins->codep++ << 24; 11797 *res = a + ((uint64_t) b << 32); 11798 return true; 11799 } 11800 11801 static void 11802 set_op (instr_info *ins, bfd_vma op, bool riprel) 11803 { 11804 ins->op_index[ins->op_ad] = ins->op_ad; 11805 if (ins->address_mode == mode_64bit) 11806 ins->op_address[ins->op_ad] = op; 11807 else /* Mask to get a 32-bit address. */ 11808 ins->op_address[ins->op_ad] = op & 0xffffffff; 11809 ins->op_riprel[ins->op_ad] = riprel; 11810 } 11811 11812 static bool 11813 BadOp (instr_info *ins) 11814 { 11815 /* Throw away prefixes and 1st. opcode byte. */ 11816 struct dis_private *priv = ins->info->private_data; 11817 11818 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1; 11819 ins->obufp = stpcpy (ins->obufp, "(bad)"); 11820 return true; 11821 } 11822 11823 static bool 11824 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 11825 int sizeflag ATTRIBUTE_UNUSED) 11826 { 11827 if (ins->modrm.mod != 3) 11828 return BadOp (ins); 11829 11830 /* Skip mod/rm byte. */ 11831 MODRM_CHECK; 11832 ins->codep++; 11833 ins->has_skipped_modrm = true; 11834 return true; 11835 } 11836 11837 static bool 11838 OP_E_memory (instr_info *ins, int bytemode, int sizeflag) 11839 { 11840 int add = (ins->rex & REX_B) ? 8 : 0; 11841 int riprel = 0; 11842 int shift; 11843 11844 add += (ins->rex2 & REX_B) ? 16 : 0; 11845 11846 /* Handles EVEX other than APX EVEX-promoted instructions. */ 11847 if (ins->vex.evex && ins->evex_type == evex_default) 11848 { 11849 11850 /* Zeroing-masking is invalid for memory destinations. Set the flag 11851 uniformly, as the consumer will inspect it only for the destination 11852 operand. */ 11853 if (ins->vex.zeroing) 11854 ins->illegal_masking = true; 11855 11856 switch (bytemode) 11857 { 11858 case dw_mode: 11859 case w_mode: 11860 case w_swap_mode: 11861 shift = 1; 11862 break; 11863 case db_mode: 11864 case b_mode: 11865 shift = 0; 11866 break; 11867 case dq_mode: 11868 if (ins->address_mode != mode_64bit) 11869 { 11870 case d_mode: 11871 case d_swap_mode: 11872 shift = 2; 11873 break; 11874 } 11875 /* fall through */ 11876 case vex_vsib_d_w_dq_mode: 11877 case vex_vsib_q_w_dq_mode: 11878 case evex_x_gscat_mode: 11879 shift = ins->vex.w ? 3 : 2; 11880 break; 11881 case xh_mode: 11882 case evex_half_bcst_xmmqh_mode: 11883 case evex_half_bcst_xmmqdh_mode: 11884 if (ins->vex.b) 11885 { 11886 shift = ins->vex.w ? 2 : 1; 11887 break; 11888 } 11889 /* Fall through. */ 11890 case x_mode: 11891 case evex_half_bcst_xmmq_mode: 11892 if (ins->vex.b) 11893 { 11894 shift = ins->vex.w ? 3 : 2; 11895 break; 11896 } 11897 /* Fall through. */ 11898 case xmmqd_mode: 11899 case xmmdw_mode: 11900 case xmmq_mode: 11901 case ymmq_mode: 11902 case evex_x_nobcst_mode: 11903 case x_swap_mode: 11904 switch (ins->vex.length) 11905 { 11906 case 128: 11907 shift = 4; 11908 break; 11909 case 256: 11910 shift = 5; 11911 break; 11912 case 512: 11913 shift = 6; 11914 break; 11915 default: 11916 abort (); 11917 } 11918 /* Make necessary corrections to shift for modes that need it. */ 11919 if (bytemode == xmmq_mode 11920 || bytemode == evex_half_bcst_xmmqh_mode 11921 || bytemode == evex_half_bcst_xmmq_mode 11922 || (bytemode == ymmq_mode && ins->vex.length == 128)) 11923 shift -= 1; 11924 else if (bytemode == xmmqd_mode 11925 || bytemode == evex_half_bcst_xmmqdh_mode) 11926 shift -= 2; 11927 else if (bytemode == xmmdw_mode) 11928 shift -= 3; 11929 break; 11930 case ymm_mode: 11931 shift = 5; 11932 break; 11933 case xmm_mode: 11934 shift = 4; 11935 break; 11936 case q_mode: 11937 case q_swap_mode: 11938 shift = 3; 11939 break; 11940 case bw_unit_mode: 11941 shift = ins->vex.w ? 1 : 0; 11942 break; 11943 default: 11944 abort (); 11945 } 11946 } 11947 else 11948 shift = 0; 11949 11950 USED_REX (REX_B); 11951 if (ins->intel_syntax) 11952 intel_operand_size (ins, bytemode, sizeflag); 11953 append_seg (ins); 11954 11955 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 11956 { 11957 /* 32/64 bit address mode */ 11958 bfd_vma disp = 0; 11959 int havedisp; 11960 int havebase; 11961 int needindex; 11962 int needaddr32; 11963 int base, rbase; 11964 int vindex = 0; 11965 int scale = 0; 11966 int addr32flag = !((sizeflag & AFLAG) 11967 || bytemode == v_bnd_mode 11968 || bytemode == v_bndmk_mode 11969 || bytemode == bnd_mode 11970 || bytemode == bnd_swap_mode); 11971 bool check_gather = false; 11972 const char (*indexes)[8] = NULL; 11973 11974 havebase = 1; 11975 base = ins->modrm.rm; 11976 11977 if (base == 4) 11978 { 11979 vindex = ins->sib.index; 11980 USED_REX (REX_X); 11981 if (ins->rex & REX_X) 11982 vindex += 8; 11983 switch (bytemode) 11984 { 11985 case vex_vsib_d_w_dq_mode: 11986 case vex_vsib_q_w_dq_mode: 11987 if (!ins->need_vex) 11988 abort (); 11989 if (ins->vex.evex) 11990 { 11991 /* S/G EVEX insns require EVEX.X4 not to be set. */ 11992 if (ins->rex2 & REX_X) 11993 { 11994 oappend (ins, "(bad)"); 11995 return true; 11996 } 11997 11998 if (!ins->vex.v) 11999 vindex += 16; 12000 check_gather = ins->obufp == ins->op_out[1]; 12001 } 12002 12003 switch (ins->vex.length) 12004 { 12005 case 128: 12006 indexes = att_names_xmm; 12007 break; 12008 case 256: 12009 if (!ins->vex.w 12010 || bytemode == vex_vsib_q_w_dq_mode) 12011 indexes = att_names_ymm; 12012 else 12013 indexes = att_names_xmm; 12014 break; 12015 case 512: 12016 if (!ins->vex.w 12017 || bytemode == vex_vsib_q_w_dq_mode) 12018 indexes = att_names_zmm; 12019 else 12020 indexes = att_names_ymm; 12021 break; 12022 default: 12023 abort (); 12024 } 12025 break; 12026 default: 12027 if (ins->rex2 & REX_X) 12028 vindex += 16; 12029 12030 if (vindex != 4) 12031 indexes = ins->address_mode == mode_64bit && !addr32flag 12032 ? att_names64 : att_names32; 12033 break; 12034 } 12035 scale = ins->sib.scale; 12036 base = ins->sib.base; 12037 ins->codep++; 12038 } 12039 else 12040 { 12041 /* Check for mandatory SIB. */ 12042 if (bytemode == vex_vsib_d_w_dq_mode 12043 || bytemode == vex_vsib_q_w_dq_mode 12044 || bytemode == vex_sibmem_mode) 12045 { 12046 oappend (ins, "(bad)"); 12047 return true; 12048 } 12049 } 12050 rbase = base + add; 12051 12052 switch (ins->modrm.mod) 12053 { 12054 case 0: 12055 if (base == 5) 12056 { 12057 havebase = 0; 12058 if (ins->address_mode == mode_64bit && !ins->has_sib) 12059 riprel = 1; 12060 if (!get32s (ins, &disp)) 12061 return false; 12062 if (riprel && bytemode == v_bndmk_mode) 12063 { 12064 oappend (ins, "(bad)"); 12065 return true; 12066 } 12067 } 12068 break; 12069 case 1: 12070 if (!get8s (ins, &disp)) 12071 return false; 12072 if (ins->vex.evex && shift > 0) 12073 disp <<= shift; 12074 break; 12075 case 2: 12076 if (!get32s (ins, &disp)) 12077 return false; 12078 break; 12079 } 12080 12081 needindex = 0; 12082 needaddr32 = 0; 12083 if (ins->has_sib 12084 && !havebase 12085 && !indexes 12086 && ins->address_mode != mode_16bit) 12087 { 12088 if (ins->address_mode == mode_64bit) 12089 { 12090 if (addr32flag) 12091 { 12092 /* Without base nor index registers, zero-extend the 12093 lower 32-bit displacement to 64 bits. */ 12094 disp &= 0xffffffff; 12095 needindex = 1; 12096 } 12097 needaddr32 = 1; 12098 } 12099 else 12100 { 12101 /* In 32-bit mode, we need index register to tell [offset] 12102 from [eiz*1 + offset]. */ 12103 needindex = 1; 12104 } 12105 } 12106 12107 havedisp = (havebase 12108 || needindex 12109 || (ins->has_sib && (indexes || scale != 0))); 12110 12111 if (!ins->intel_syntax) 12112 if (ins->modrm.mod != 0 || base == 5) 12113 { 12114 if (havedisp || riprel) 12115 print_displacement (ins, disp); 12116 else 12117 print_operand_value (ins, disp, dis_style_address_offset); 12118 if (riprel) 12119 { 12120 set_op (ins, disp, true); 12121 oappend_char (ins, '('); 12122 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip", 12123 dis_style_register); 12124 oappend_char (ins, ')'); 12125 } 12126 } 12127 12128 if ((havebase || indexes || needindex || needaddr32 || riprel) 12129 && (ins->address_mode != mode_64bit 12130 || ((bytemode != v_bnd_mode) 12131 && (bytemode != v_bndmk_mode) 12132 && (bytemode != bnd_mode) 12133 && (bytemode != bnd_swap_mode)))) 12134 ins->used_prefixes |= PREFIX_ADDR; 12135 12136 if (havedisp || (ins->intel_syntax && riprel)) 12137 { 12138 oappend_char (ins, ins->open_char); 12139 if (ins->intel_syntax && riprel) 12140 { 12141 set_op (ins, disp, true); 12142 oappend_with_style (ins, !addr32flag ? "rip" : "eip", 12143 dis_style_register); 12144 } 12145 if (havebase) 12146 oappend_register 12147 (ins, 12148 (ins->address_mode == mode_64bit && !addr32flag 12149 ? att_names64 : att_names32)[rbase]); 12150 if (ins->has_sib) 12151 { 12152 /* ESP/RSP won't allow index. If base isn't ESP/RSP, 12153 print index to tell base + index from base. */ 12154 if (scale != 0 12155 || needindex 12156 || indexes 12157 || (havebase && base != ESP_REG_NUM)) 12158 { 12159 if (!ins->intel_syntax || havebase) 12160 oappend_char (ins, ins->separator_char); 12161 if (indexes) 12162 { 12163 if (ins->address_mode == mode_64bit || vindex < 16) 12164 oappend_register (ins, indexes[vindex]); 12165 else 12166 oappend (ins, "(bad)"); 12167 } 12168 else 12169 oappend_register (ins, 12170 ins->address_mode == mode_64bit 12171 && !addr32flag 12172 ? att_index64 12173 : att_index32); 12174 12175 oappend_char (ins, ins->scale_char); 12176 oappend_char_with_style (ins, '0' + (1 << scale), 12177 dis_style_immediate); 12178 } 12179 } 12180 if (ins->intel_syntax 12181 && (disp || ins->modrm.mod != 0 || base == 5)) 12182 { 12183 if (!havedisp || (bfd_signed_vma) disp >= 0) 12184 oappend_char (ins, '+'); 12185 if (havedisp) 12186 print_displacement (ins, disp); 12187 else 12188 print_operand_value (ins, disp, dis_style_address_offset); 12189 } 12190 12191 oappend_char (ins, ins->close_char); 12192 12193 if (check_gather) 12194 { 12195 /* Both XMM/YMM/ZMM registers must be distinct. */ 12196 int modrm_reg = ins->modrm.reg; 12197 12198 if (ins->rex & REX_R) 12199 modrm_reg += 8; 12200 if (ins->rex2 & REX_R) 12201 modrm_reg += 16; 12202 if (vindex == modrm_reg) 12203 oappend (ins, "/(bad)"); 12204 } 12205 } 12206 else if (ins->intel_syntax) 12207 { 12208 if (ins->modrm.mod != 0 || base == 5) 12209 { 12210 if (!ins->active_seg_prefix) 12211 { 12212 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12213 oappend (ins, ":"); 12214 } 12215 print_operand_value (ins, disp, dis_style_text); 12216 } 12217 } 12218 } 12219 else if (bytemode == v_bnd_mode 12220 || bytemode == v_bndmk_mode 12221 || bytemode == bnd_mode 12222 || bytemode == bnd_swap_mode 12223 || bytemode == vex_vsib_d_w_dq_mode 12224 || bytemode == vex_vsib_q_w_dq_mode) 12225 { 12226 oappend (ins, "(bad)"); 12227 return true; 12228 } 12229 else 12230 { 12231 /* 16 bit address mode */ 12232 bfd_vma disp = 0; 12233 12234 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR; 12235 switch (ins->modrm.mod) 12236 { 12237 case 0: 12238 if (ins->modrm.rm == 6) 12239 { 12240 case 2: 12241 if (!get16s (ins, &disp)) 12242 return false; 12243 } 12244 break; 12245 case 1: 12246 if (!get8s (ins, &disp)) 12247 return false; 12248 if (ins->vex.evex && shift > 0) 12249 disp <<= shift; 12250 break; 12251 } 12252 12253 if (!ins->intel_syntax) 12254 if (ins->modrm.mod != 0 || ins->modrm.rm == 6) 12255 print_displacement (ins, disp); 12256 12257 if (ins->modrm.mod != 0 || ins->modrm.rm != 6) 12258 { 12259 oappend_char (ins, ins->open_char); 12260 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm] 12261 : att_index16[ins->modrm.rm]); 12262 if (ins->intel_syntax 12263 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6)) 12264 { 12265 if ((bfd_signed_vma) disp >= 0) 12266 oappend_char (ins, '+'); 12267 print_displacement (ins, disp); 12268 } 12269 12270 oappend_char (ins, ins->close_char); 12271 } 12272 else if (ins->intel_syntax) 12273 { 12274 if (!ins->active_seg_prefix) 12275 { 12276 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12277 oappend (ins, ":"); 12278 } 12279 print_operand_value (ins, disp & 0xffff, dis_style_text); 12280 } 12281 } 12282 if (ins->vex.b && ins->evex_type == evex_default) 12283 { 12284 ins->evex_used |= EVEX_b_used; 12285 12286 /* Broadcast can only ever be valid for memory sources. */ 12287 if (ins->obufp == ins->op_out[0]) 12288 ins->vex.no_broadcast = true; 12289 12290 if (!ins->vex.no_broadcast 12291 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used))) 12292 { 12293 if (bytemode == xh_mode) 12294 { 12295 switch (ins->vex.length) 12296 { 12297 case 128: 12298 oappend (ins, "{1to8}"); 12299 break; 12300 case 256: 12301 oappend (ins, "{1to16}"); 12302 break; 12303 case 512: 12304 oappend (ins, "{1to32}"); 12305 break; 12306 default: 12307 abort (); 12308 } 12309 } 12310 else if (bytemode == q_mode 12311 || bytemode == ymmq_mode) 12312 ins->vex.no_broadcast = true; 12313 else if (ins->vex.w 12314 || bytemode == evex_half_bcst_xmmqdh_mode 12315 || bytemode == evex_half_bcst_xmmq_mode) 12316 { 12317 switch (ins->vex.length) 12318 { 12319 case 128: 12320 oappend (ins, "{1to2}"); 12321 break; 12322 case 256: 12323 oappend (ins, "{1to4}"); 12324 break; 12325 case 512: 12326 oappend (ins, "{1to8}"); 12327 break; 12328 default: 12329 abort (); 12330 } 12331 } 12332 else if (bytemode == x_mode 12333 || bytemode == evex_half_bcst_xmmqh_mode) 12334 { 12335 switch (ins->vex.length) 12336 { 12337 case 128: 12338 oappend (ins, "{1to4}"); 12339 break; 12340 case 256: 12341 oappend (ins, "{1to8}"); 12342 break; 12343 case 512: 12344 oappend (ins, "{1to16}"); 12345 break; 12346 default: 12347 abort (); 12348 } 12349 } 12350 else 12351 ins->vex.no_broadcast = true; 12352 } 12353 if (ins->vex.no_broadcast) 12354 oappend (ins, "{bad}"); 12355 } 12356 12357 return true; 12358 } 12359 12360 static bool 12361 OP_E (instr_info *ins, int bytemode, int sizeflag) 12362 { 12363 /* Skip mod/rm byte. */ 12364 MODRM_CHECK; 12365 if (!ins->has_skipped_modrm) 12366 { 12367 ins->codep++; 12368 ins->has_skipped_modrm = true; 12369 } 12370 12371 if (ins->modrm.mod == 3) 12372 { 12373 if ((sizeflag & SUFFIX_ALWAYS) 12374 && (bytemode == b_swap_mode 12375 || bytemode == bnd_swap_mode 12376 || bytemode == v_swap_mode)) 12377 swap_operand (ins); 12378 12379 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag); 12380 return true; 12381 } 12382 12383 /* Masking is invalid for insns with GPR-like memory destination. Set the 12384 flag uniformly, as the consumer will inspect it only for the destination 12385 operand. */ 12386 if (ins->vex.mask_register_specifier) 12387 ins->illegal_masking = true; 12388 12389 return OP_E_memory (ins, bytemode, sizeflag); 12390 } 12391 12392 static bool 12393 OP_indirE (instr_info *ins, int bytemode, int sizeflag) 12394 { 12395 if (ins->modrm.mod == 3 && bytemode == f_mode) 12396 /* bad lcall/ljmp */ 12397 return BadOp (ins); 12398 if (!ins->intel_syntax) 12399 oappend (ins, "*"); 12400 return OP_E (ins, bytemode, sizeflag); 12401 } 12402 12403 static bool 12404 OP_G (instr_info *ins, int bytemode, int sizeflag) 12405 { 12406 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); 12407 return true; 12408 } 12409 12410 static bool 12411 OP_REG (instr_info *ins, int code, int sizeflag) 12412 { 12413 const char *s; 12414 int add = 0; 12415 12416 switch (code) 12417 { 12418 case es_reg: case ss_reg: case cs_reg: 12419 case ds_reg: case fs_reg: case gs_reg: 12420 oappend_register (ins, att_names_seg[code - es_reg]); 12421 return true; 12422 } 12423 12424 USED_REX (REX_B); 12425 if (ins->rex & REX_B) 12426 add = 8; 12427 if (ins->rex2 & REX_B) 12428 add += 16; 12429 12430 switch (code) 12431 { 12432 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 12433 case sp_reg: case bp_reg: case si_reg: case di_reg: 12434 s = att_names16[code - ax_reg + add]; 12435 break; 12436 case ah_reg: case ch_reg: case dh_reg: case bh_reg: 12437 USED_REX (0); 12438 /* Fall through. */ 12439 case al_reg: case cl_reg: case dl_reg: case bl_reg: 12440 if (ins->rex) 12441 s = att_names8rex[code - al_reg + add]; 12442 else 12443 s = att_names8[code - al_reg]; 12444 break; 12445 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: 12446 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: 12447 if (ins->address_mode == mode_64bit 12448 && ((sizeflag & DFLAG) || (ins->rex & REX_W))) 12449 { 12450 s = att_names64[code - rAX_reg + add]; 12451 break; 12452 } 12453 code += eAX_reg - rAX_reg; 12454 /* Fall through. */ 12455 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 12456 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 12457 USED_REX (REX_W); 12458 if (ins->rex & REX_W) 12459 s = att_names64[code - eAX_reg + add]; 12460 else 12461 { 12462 if (sizeflag & DFLAG) 12463 s = att_names32[code - eAX_reg + add]; 12464 else 12465 s = att_names16[code - eAX_reg + add]; 12466 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12467 } 12468 break; 12469 default: 12470 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12471 return true; 12472 } 12473 oappend_register (ins, s); 12474 return true; 12475 } 12476 12477 static bool 12478 OP_IMREG (instr_info *ins, int code, int sizeflag) 12479 { 12480 const char *s; 12481 12482 switch (code) 12483 { 12484 case indir_dx_reg: 12485 if (!ins->intel_syntax) 12486 { 12487 oappend (ins, "(%dx)"); 12488 return true; 12489 } 12490 s = att_names16[dx_reg - ax_reg]; 12491 break; 12492 case al_reg: case cl_reg: 12493 s = att_names8[code - al_reg]; 12494 break; 12495 case eAX_reg: 12496 USED_REX (REX_W); 12497 if (ins->rex & REX_W) 12498 { 12499 s = *att_names64; 12500 break; 12501 } 12502 /* Fall through. */ 12503 case z_mode_ax_reg: 12504 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 12505 s = *att_names32; 12506 else 12507 s = *att_names16; 12508 if (!(ins->rex & REX_W)) 12509 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12510 break; 12511 default: 12512 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12513 return true; 12514 } 12515 oappend_register (ins, s); 12516 return true; 12517 } 12518 12519 static bool 12520 OP_I (instr_info *ins, int bytemode, int sizeflag) 12521 { 12522 bfd_vma op; 12523 12524 switch (bytemode) 12525 { 12526 case b_mode: 12527 if (!fetch_code (ins->info, ins->codep + 1)) 12528 return false; 12529 op = *ins->codep++; 12530 break; 12531 case v_mode: 12532 USED_REX (REX_W); 12533 if (ins->rex & REX_W) 12534 { 12535 if (!get32s (ins, &op)) 12536 return false; 12537 } 12538 else 12539 { 12540 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12541 if (sizeflag & DFLAG) 12542 { 12543 case d_mode: 12544 if (!get32 (ins, &op)) 12545 return false; 12546 } 12547 else 12548 { 12549 /* Fall through. */ 12550 case w_mode: 12551 if (!get16 (ins, &op)) 12552 return false; 12553 } 12554 } 12555 break; 12556 case const_1_mode: 12557 if (ins->intel_syntax) 12558 oappend_with_style (ins, "1", dis_style_immediate); 12559 else 12560 oappend_with_style (ins, "$1", dis_style_immediate); 12561 return true; 12562 default: 12563 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12564 return true; 12565 } 12566 12567 oappend_immediate (ins, op); 12568 return true; 12569 } 12570 12571 static bool 12572 OP_I64 (instr_info *ins, int bytemode, int sizeflag) 12573 { 12574 uint64_t op; 12575 12576 if (bytemode != v_mode || ins->address_mode != mode_64bit 12577 || !(ins->rex & REX_W)) 12578 return OP_I (ins, bytemode, sizeflag); 12579 12580 USED_REX (REX_W); 12581 12582 if (!get64 (ins, &op)) 12583 return false; 12584 12585 oappend_immediate (ins, op); 12586 return true; 12587 } 12588 12589 static bool 12590 OP_sI (instr_info *ins, int bytemode, int sizeflag) 12591 { 12592 bfd_vma op; 12593 12594 switch (bytemode) 12595 { 12596 case b_mode: 12597 case b_T_mode: 12598 if (!get8s (ins, &op)) 12599 return false; 12600 if (bytemode == b_T_mode) 12601 { 12602 if (ins->address_mode != mode_64bit 12603 || !((sizeflag & DFLAG) || (ins->rex & REX_W))) 12604 { 12605 /* The operand-size prefix is overridden by a REX prefix. */ 12606 if ((sizeflag & DFLAG) || (ins->rex & REX_W)) 12607 op &= 0xffffffff; 12608 else 12609 op &= 0xffff; 12610 } 12611 } 12612 else 12613 { 12614 if (!(ins->rex & REX_W)) 12615 { 12616 if (sizeflag & DFLAG) 12617 op &= 0xffffffff; 12618 else 12619 op &= 0xffff; 12620 } 12621 } 12622 break; 12623 case v_mode: 12624 /* The operand-size prefix is overridden by a REX prefix. */ 12625 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W)) 12626 { 12627 if (!get16 (ins, &op)) 12628 return false; 12629 } 12630 else if (!get32s (ins, &op)) 12631 return false; 12632 break; 12633 default: 12634 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12635 return true; 12636 } 12637 12638 oappend_immediate (ins, op); 12639 return true; 12640 } 12641 12642 static bool 12643 OP_J (instr_info *ins, int bytemode, int sizeflag) 12644 { 12645 bfd_vma disp; 12646 bfd_vma mask = -1; 12647 bfd_vma segment = 0; 12648 12649 switch (bytemode) 12650 { 12651 case b_mode: 12652 if (!get8s (ins, &disp)) 12653 return false; 12654 break; 12655 case v_mode: 12656 case dqw_mode: 12657 if ((sizeflag & DFLAG) 12658 || (ins->address_mode == mode_64bit 12659 && ((ins->isa64 == intel64 && bytemode != dqw_mode) 12660 || (ins->rex & REX_W)))) 12661 { 12662 if (!get32s (ins, &disp)) 12663 return false; 12664 } 12665 else 12666 { 12667 if (!get16s (ins, &disp)) 12668 return false; 12669 /* In 16bit mode, address is wrapped around at 64k within 12670 the same segment. Otherwise, a data16 prefix on a jump 12671 instruction means that the pc is masked to 16 bits after 12672 the displacement is added! */ 12673 mask = 0xffff; 12674 if ((ins->prefixes & PREFIX_DATA) == 0) 12675 segment = ((ins->start_pc + (ins->codep - ins->start_codep)) 12676 & ~((bfd_vma) 0xffff)); 12677 } 12678 if (ins->address_mode != mode_64bit 12679 || (ins->isa64 != intel64 && !(ins->rex & REX_W))) 12680 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12681 break; 12682 default: 12683 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12684 return true; 12685 } 12686 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask) 12687 | segment; 12688 set_op (ins, disp, false); 12689 print_operand_value (ins, disp, dis_style_text); 12690 return true; 12691 } 12692 12693 static bool 12694 OP_SEG (instr_info *ins, int bytemode, int sizeflag) 12695 { 12696 if (bytemode == w_mode) 12697 { 12698 oappend_register (ins, att_names_seg[ins->modrm.reg]); 12699 return true; 12700 } 12701 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag); 12702 } 12703 12704 static bool 12705 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag) 12706 { 12707 bfd_vma seg, offset; 12708 int res; 12709 char scratch[24]; 12710 12711 if (sizeflag & DFLAG) 12712 { 12713 if (!get32 (ins, &offset)) 12714 return false;; 12715 } 12716 else if (!get16 (ins, &offset)) 12717 return false; 12718 if (!get16 (ins, &seg)) 12719 return false;; 12720 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12721 12722 res = snprintf (scratch, ARRAY_SIZE (scratch), 12723 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x", 12724 (unsigned) seg, (unsigned) offset); 12725 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 12726 abort (); 12727 oappend (ins, scratch); 12728 return true; 12729 } 12730 12731 static bool 12732 OP_OFF (instr_info *ins, int bytemode, int sizeflag) 12733 { 12734 bfd_vma off; 12735 12736 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 12737 intel_operand_size (ins, bytemode, sizeflag); 12738 append_seg (ins); 12739 12740 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 12741 { 12742 if (!get32 (ins, &off)) 12743 return false; 12744 } 12745 else 12746 { 12747 if (!get16 (ins, &off)) 12748 return false; 12749 } 12750 12751 if (ins->intel_syntax) 12752 { 12753 if (!ins->active_seg_prefix) 12754 { 12755 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12756 oappend (ins, ":"); 12757 } 12758 } 12759 print_operand_value (ins, off, dis_style_address_offset); 12760 return true; 12761 } 12762 12763 static bool 12764 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag) 12765 { 12766 uint64_t off; 12767 12768 if (ins->address_mode != mode_64bit 12769 || (ins->prefixes & PREFIX_ADDR)) 12770 return OP_OFF (ins, bytemode, sizeflag); 12771 12772 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 12773 intel_operand_size (ins, bytemode, sizeflag); 12774 append_seg (ins); 12775 12776 if (!get64 (ins, &off)) 12777 return false; 12778 12779 if (ins->intel_syntax) 12780 { 12781 if (!ins->active_seg_prefix) 12782 { 12783 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12784 oappend (ins, ":"); 12785 } 12786 } 12787 print_operand_value (ins, off, dis_style_address_offset); 12788 return true; 12789 } 12790 12791 static void 12792 ptr_reg (instr_info *ins, int code, int sizeflag) 12793 { 12794 const char *s; 12795 12796 *ins->obufp++ = ins->open_char; 12797 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 12798 if (ins->address_mode == mode_64bit) 12799 { 12800 if (!(sizeflag & AFLAG)) 12801 s = att_names32[code - eAX_reg]; 12802 else 12803 s = att_names64[code - eAX_reg]; 12804 } 12805 else if (sizeflag & AFLAG) 12806 s = att_names32[code - eAX_reg]; 12807 else 12808 s = att_names16[code - eAX_reg]; 12809 oappend_register (ins, s); 12810 oappend_char (ins, ins->close_char); 12811 } 12812 12813 static bool 12814 OP_ESreg (instr_info *ins, int code, int sizeflag) 12815 { 12816 if (ins->intel_syntax) 12817 { 12818 switch (ins->codep[-1]) 12819 { 12820 case 0x6d: /* insw/insl */ 12821 intel_operand_size (ins, z_mode, sizeflag); 12822 break; 12823 case 0xa5: /* movsw/movsl/movsq */ 12824 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 12825 case 0xab: /* stosw/stosl */ 12826 case 0xaf: /* scasw/scasl */ 12827 intel_operand_size (ins, v_mode, sizeflag); 12828 break; 12829 default: 12830 intel_operand_size (ins, b_mode, sizeflag); 12831 } 12832 } 12833 oappend_register (ins, att_names_seg[0]); 12834 oappend_char (ins, ':'); 12835 ptr_reg (ins, code, sizeflag); 12836 return true; 12837 } 12838 12839 static bool 12840 OP_DSreg (instr_info *ins, int code, int sizeflag) 12841 { 12842 if (ins->intel_syntax) 12843 { 12844 switch (ins->codep[-1]) 12845 { 12846 case 0x6f: /* outsw/outsl */ 12847 intel_operand_size (ins, z_mode, sizeflag); 12848 break; 12849 case 0xa5: /* movsw/movsl/movsq */ 12850 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 12851 case 0xad: /* lodsw/lodsl/lodsq */ 12852 intel_operand_size (ins, v_mode, sizeflag); 12853 break; 12854 default: 12855 intel_operand_size (ins, b_mode, sizeflag); 12856 } 12857 } 12858 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the 12859 default segment register DS is printed. */ 12860 if (!ins->active_seg_prefix) 12861 ins->active_seg_prefix = PREFIX_DS; 12862 append_seg (ins); 12863 ptr_reg (ins, code, sizeflag); 12864 return true; 12865 } 12866 12867 static bool 12868 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 12869 int sizeflag ATTRIBUTE_UNUSED) 12870 { 12871 int add, res; 12872 char scratch[8]; 12873 12874 if (ins->rex & REX_R) 12875 { 12876 USED_REX (REX_R); 12877 add = 8; 12878 } 12879 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK)) 12880 { 12881 ins->all_prefixes[ins->last_lock_prefix] = 0; 12882 ins->used_prefixes |= PREFIX_LOCK; 12883 add = 8; 12884 } 12885 else 12886 add = 0; 12887 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d", 12888 ins->modrm.reg + add); 12889 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 12890 abort (); 12891 oappend_register (ins, scratch); 12892 return true; 12893 } 12894 12895 static bool 12896 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 12897 int sizeflag ATTRIBUTE_UNUSED) 12898 { 12899 int add, res; 12900 char scratch[8]; 12901 12902 USED_REX (REX_R); 12903 if (ins->rex & REX_R) 12904 add = 8; 12905 else 12906 add = 0; 12907 res = snprintf (scratch, ARRAY_SIZE (scratch), 12908 ins->intel_syntax ? "dr%d" : "%%db%d", 12909 ins->modrm.reg + add); 12910 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 12911 abort (); 12912 oappend (ins, scratch); 12913 return true; 12914 } 12915 12916 static bool 12917 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 12918 int sizeflag ATTRIBUTE_UNUSED) 12919 { 12920 int res; 12921 char scratch[8]; 12922 12923 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg); 12924 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 12925 abort (); 12926 oappend_register (ins, scratch); 12927 return true; 12928 } 12929 12930 static bool 12931 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 12932 int sizeflag ATTRIBUTE_UNUSED) 12933 { 12934 int reg = ins->modrm.reg; 12935 const char (*names)[8]; 12936 12937 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12938 if (ins->prefixes & PREFIX_DATA) 12939 { 12940 names = att_names_xmm; 12941 USED_REX (REX_R); 12942 if (ins->rex & REX_R) 12943 reg += 8; 12944 } 12945 else 12946 names = att_names_mm; 12947 oappend_register (ins, names[reg]); 12948 return true; 12949 } 12950 12951 static void 12952 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode) 12953 { 12954 const char (*names)[8]; 12955 12956 if (bytemode == xmmq_mode 12957 || bytemode == evex_half_bcst_xmmqh_mode 12958 || bytemode == evex_half_bcst_xmmq_mode) 12959 { 12960 switch (ins->vex.length) 12961 { 12962 case 0: 12963 case 128: 12964 case 256: 12965 names = att_names_xmm; 12966 break; 12967 case 512: 12968 names = att_names_ymm; 12969 ins->evex_used |= EVEX_len_used; 12970 break; 12971 default: 12972 abort (); 12973 } 12974 } 12975 else if (bytemode == ymm_mode) 12976 names = att_names_ymm; 12977 else if (bytemode == tmm_mode) 12978 { 12979 if (reg >= 8) 12980 { 12981 oappend (ins, "(bad)"); 12982 return; 12983 } 12984 names = att_names_tmm; 12985 } 12986 else if (ins->need_vex 12987 && bytemode != xmm_mode 12988 && bytemode != scalar_mode 12989 && bytemode != xmmdw_mode 12990 && bytemode != xmmqd_mode 12991 && bytemode != evex_half_bcst_xmmqdh_mode 12992 && bytemode != w_swap_mode 12993 && bytemode != b_mode 12994 && bytemode != w_mode 12995 && bytemode != d_mode 12996 && bytemode != q_mode) 12997 { 12998 ins->evex_used |= EVEX_len_used; 12999 switch (ins->vex.length) 13000 { 13001 case 128: 13002 names = att_names_xmm; 13003 break; 13004 case 256: 13005 if (ins->vex.w 13006 || bytemode != vex_vsib_q_w_dq_mode) 13007 names = att_names_ymm; 13008 else 13009 names = att_names_xmm; 13010 break; 13011 case 512: 13012 if (ins->vex.w 13013 || bytemode != vex_vsib_q_w_dq_mode) 13014 names = att_names_zmm; 13015 else 13016 names = att_names_ymm; 13017 break; 13018 default: 13019 abort (); 13020 } 13021 } 13022 else 13023 names = att_names_xmm; 13024 oappend_register (ins, names[reg]); 13025 } 13026 13027 static bool 13028 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13029 { 13030 unsigned int reg = ins->modrm.reg; 13031 13032 USED_REX (REX_R); 13033 if (ins->rex & REX_R) 13034 reg += 8; 13035 if (ins->vex.evex) 13036 { 13037 if (ins->rex2 & REX_R) 13038 reg += 16; 13039 } 13040 13041 if (bytemode == tmm_mode) 13042 ins->modrm.reg = reg; 13043 else if (bytemode == scalar_mode) 13044 ins->vex.no_broadcast = true; 13045 13046 print_vector_reg (ins, reg, bytemode); 13047 return true; 13048 } 13049 13050 static bool 13051 OP_EM (instr_info *ins, int bytemode, int sizeflag) 13052 { 13053 int reg; 13054 const char (*names)[8]; 13055 13056 if (ins->modrm.mod != 3) 13057 { 13058 if (ins->intel_syntax 13059 && (bytemode == v_mode || bytemode == v_swap_mode)) 13060 { 13061 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; 13062 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13063 } 13064 return OP_E (ins, bytemode, sizeflag); 13065 } 13066 13067 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) 13068 swap_operand (ins); 13069 13070 /* Skip mod/rm byte. */ 13071 MODRM_CHECK; 13072 ins->codep++; 13073 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13074 reg = ins->modrm.rm; 13075 if (ins->prefixes & PREFIX_DATA) 13076 { 13077 names = att_names_xmm; 13078 USED_REX (REX_B); 13079 if (ins->rex & REX_B) 13080 reg += 8; 13081 } 13082 else 13083 names = att_names_mm; 13084 oappend_register (ins, names[reg]); 13085 return true; 13086 } 13087 13088 /* cvt* are the only instructions in sse2 which have 13089 both SSE and MMX operands and also have 0x66 prefix 13090 in their opcode. 0x66 was originally used to differentiate 13091 between SSE and MMX instruction(operands). So we have to handle the 13092 cvt* separately using OP_EMC and OP_MXC */ 13093 static bool 13094 OP_EMC (instr_info *ins, int bytemode, int sizeflag) 13095 { 13096 if (ins->modrm.mod != 3) 13097 { 13098 if (ins->intel_syntax && bytemode == v_mode) 13099 { 13100 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; 13101 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13102 } 13103 return OP_E (ins, bytemode, sizeflag); 13104 } 13105 13106 /* Skip mod/rm byte. */ 13107 MODRM_CHECK; 13108 ins->codep++; 13109 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13110 oappend_register (ins, att_names_mm[ins->modrm.rm]); 13111 return true; 13112 } 13113 13114 static bool 13115 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13116 int sizeflag ATTRIBUTE_UNUSED) 13117 { 13118 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13119 oappend_register (ins, att_names_mm[ins->modrm.reg]); 13120 return true; 13121 } 13122 13123 static bool 13124 OP_EX (instr_info *ins, int bytemode, int sizeflag) 13125 { 13126 int reg; 13127 13128 /* Skip mod/rm byte. */ 13129 MODRM_CHECK; 13130 ins->codep++; 13131 13132 if (bytemode == dq_mode) 13133 bytemode = ins->vex.w ? q_mode : d_mode; 13134 13135 if (ins->modrm.mod != 3) 13136 return OP_E_memory (ins, bytemode, sizeflag); 13137 13138 reg = ins->modrm.rm; 13139 USED_REX (REX_B); 13140 if (ins->rex & REX_B) 13141 reg += 8; 13142 if (ins->vex.evex) 13143 { 13144 USED_REX (REX_X); 13145 if ((ins->rex & REX_X)) 13146 reg += 16; 13147 ins->rex2_used &= ~REX_B; 13148 } 13149 else if (ins->rex2 & REX_B) 13150 reg += 16; 13151 13152 if ((sizeflag & SUFFIX_ALWAYS) 13153 && (bytemode == x_swap_mode 13154 || bytemode == w_swap_mode 13155 || bytemode == d_swap_mode 13156 || bytemode == q_swap_mode)) 13157 swap_operand (ins); 13158 13159 if (bytemode == tmm_mode) 13160 ins->modrm.rm = reg; 13161 13162 print_vector_reg (ins, reg, bytemode); 13163 return true; 13164 } 13165 13166 static bool 13167 OP_R (instr_info *ins, int bytemode, int sizeflag) 13168 { 13169 if (ins->modrm.mod != 3) 13170 return BadOp (ins); 13171 13172 switch (bytemode) 13173 { 13174 case d_mode: 13175 case dq_mode: 13176 case q_mode: 13177 case mask_mode: 13178 return OP_E (ins, bytemode, sizeflag); 13179 case q_mm_mode: 13180 return OP_EM (ins, x_mode, sizeflag); 13181 case xmm_mode: 13182 if (ins->vex.length <= 128) 13183 break; 13184 return BadOp (ins); 13185 } 13186 13187 return OP_EX (ins, bytemode, sizeflag); 13188 } 13189 13190 static bool 13191 OP_M (instr_info *ins, int bytemode, int sizeflag) 13192 { 13193 /* Skip mod/rm byte. */ 13194 MODRM_CHECK; 13195 ins->codep++; 13196 13197 if (ins->modrm.mod == 3) 13198 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ 13199 return BadOp (ins); 13200 13201 if (bytemode == x_mode) 13202 ins->vex.no_broadcast = true; 13203 13204 return OP_E_memory (ins, bytemode, sizeflag); 13205 } 13206 13207 static bool 13208 OP_0f07 (instr_info *ins, int bytemode, int sizeflag) 13209 { 13210 if (ins->modrm.mod != 3 || ins->modrm.rm != 0) 13211 return BadOp (ins); 13212 return OP_E (ins, bytemode, sizeflag); 13213 } 13214 13215 /* montmul instruction need display repz and skip modrm */ 13216 13217 static bool 13218 MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 13219 { 13220 if (ins->modrm.mod != 3 || ins->modrm.rm != 0) 13221 return BadOp (ins); 13222 13223 /* The 0xf3 prefix should be displayed as "repz" for montmul. */ 13224 if (ins->prefixes & PREFIX_REPZ) 13225 ins->all_prefixes[ins->last_repz_prefix] = 0xf3; 13226 13227 /* Skip mod/rm byte. */ 13228 MODRM_CHECK; 13229 ins->codep++; 13230 return true; 13231 } 13232 13233 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 13234 32bit mode and "xchg %rax,%rax" in 64bit mode. */ 13235 13236 static bool 13237 NOP_Fixup (instr_info *ins, int opnd, int sizeflag) 13238 { 13239 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0) 13240 { 13241 ins->mnemonicendp = stpcpy (ins->obuf, "nop"); 13242 return true; 13243 } 13244 if (opnd == 0) 13245 return OP_REG (ins, eAX_reg, sizeflag); 13246 return OP_IMREG (ins, eAX_reg, sizeflag); 13247 } 13248 13249 static const char *const Suffix3DNow[] = { 13250 /* 00 */ NULL, NULL, NULL, NULL, 13251 /* 04 */ NULL, NULL, NULL, NULL, 13252 /* 08 */ NULL, NULL, NULL, NULL, 13253 /* 0C */ "pi2fw", "pi2fd", NULL, NULL, 13254 /* 10 */ NULL, NULL, NULL, NULL, 13255 /* 14 */ NULL, NULL, NULL, NULL, 13256 /* 18 */ NULL, NULL, NULL, NULL, 13257 /* 1C */ "pf2iw", "pf2id", NULL, NULL, 13258 /* 20 */ NULL, NULL, NULL, NULL, 13259 /* 24 */ NULL, NULL, NULL, NULL, 13260 /* 28 */ NULL, NULL, NULL, NULL, 13261 /* 2C */ NULL, NULL, NULL, NULL, 13262 /* 30 */ NULL, NULL, NULL, NULL, 13263 /* 34 */ NULL, NULL, NULL, NULL, 13264 /* 38 */ NULL, NULL, NULL, NULL, 13265 /* 3C */ NULL, NULL, NULL, NULL, 13266 /* 40 */ NULL, NULL, NULL, NULL, 13267 /* 44 */ NULL, NULL, NULL, NULL, 13268 /* 48 */ NULL, NULL, NULL, NULL, 13269 /* 4C */ NULL, NULL, NULL, NULL, 13270 /* 50 */ NULL, NULL, NULL, NULL, 13271 /* 54 */ NULL, NULL, NULL, NULL, 13272 /* 58 */ NULL, NULL, NULL, NULL, 13273 /* 5C */ NULL, NULL, NULL, NULL, 13274 /* 60 */ NULL, NULL, NULL, NULL, 13275 /* 64 */ NULL, NULL, NULL, NULL, 13276 /* 68 */ NULL, NULL, NULL, NULL, 13277 /* 6C */ NULL, NULL, NULL, NULL, 13278 /* 70 */ NULL, NULL, NULL, NULL, 13279 /* 74 */ NULL, NULL, NULL, NULL, 13280 /* 78 */ NULL, NULL, NULL, NULL, 13281 /* 7C */ NULL, NULL, NULL, NULL, 13282 /* 80 */ NULL, NULL, NULL, NULL, 13283 /* 84 */ NULL, NULL, NULL, NULL, 13284 /* 88 */ NULL, NULL, "pfnacc", NULL, 13285 /* 8C */ NULL, NULL, "pfpnacc", NULL, 13286 /* 90 */ "pfcmpge", NULL, NULL, NULL, 13287 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", 13288 /* 98 */ NULL, NULL, "pfsub", NULL, 13289 /* 9C */ NULL, NULL, "pfadd", NULL, 13290 /* A0 */ "pfcmpgt", NULL, NULL, NULL, 13291 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", 13292 /* A8 */ NULL, NULL, "pfsubr", NULL, 13293 /* AC */ NULL, NULL, "pfacc", NULL, 13294 /* B0 */ "pfcmpeq", NULL, NULL, NULL, 13295 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", 13296 /* B8 */ NULL, NULL, NULL, "pswapd", 13297 /* BC */ NULL, NULL, NULL, "pavgusb", 13298 /* C0 */ NULL, NULL, NULL, NULL, 13299 /* C4 */ NULL, NULL, NULL, NULL, 13300 /* C8 */ NULL, NULL, NULL, NULL, 13301 /* CC */ NULL, NULL, NULL, NULL, 13302 /* D0 */ NULL, NULL, NULL, NULL, 13303 /* D4 */ NULL, NULL, NULL, NULL, 13304 /* D8 */ NULL, NULL, NULL, NULL, 13305 /* DC */ NULL, NULL, NULL, NULL, 13306 /* E0 */ NULL, NULL, NULL, NULL, 13307 /* E4 */ NULL, NULL, NULL, NULL, 13308 /* E8 */ NULL, NULL, NULL, NULL, 13309 /* EC */ NULL, NULL, NULL, NULL, 13310 /* F0 */ NULL, NULL, NULL, NULL, 13311 /* F4 */ NULL, NULL, NULL, NULL, 13312 /* F8 */ NULL, NULL, NULL, NULL, 13313 /* FC */ NULL, NULL, NULL, NULL, 13314 }; 13315 13316 static bool 13317 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13318 int sizeflag ATTRIBUTE_UNUSED) 13319 { 13320 const char *mnemonic; 13321 13322 if (!fetch_code (ins->info, ins->codep + 1)) 13323 return false; 13324 /* AMD 3DNow! instructions are specified by an opcode suffix in the 13325 place where an 8-bit immediate would normally go. ie. the last 13326 byte of the instruction. */ 13327 ins->obufp = ins->mnemonicendp; 13328 mnemonic = Suffix3DNow[*ins->codep++]; 13329 if (mnemonic) 13330 ins->obufp = stpcpy (ins->obufp, mnemonic); 13331 else 13332 { 13333 /* Since a variable sized ins->modrm/ins->sib chunk is between the start 13334 of the opcode (0x0f0f) and the opcode suffix, we need to do 13335 all the ins->modrm processing first, and don't know until now that 13336 we have a bad opcode. This necessitates some cleaning up. */ 13337 ins->op_out[0][0] = '\0'; 13338 ins->op_out[1][0] = '\0'; 13339 BadOp (ins); 13340 } 13341 ins->mnemonicendp = ins->obufp; 13342 return true; 13343 } 13344 13345 static const struct op simd_cmp_op[] = 13346 { 13347 { STRING_COMMA_LEN ("eq") }, 13348 { STRING_COMMA_LEN ("lt") }, 13349 { STRING_COMMA_LEN ("le") }, 13350 { STRING_COMMA_LEN ("unord") }, 13351 { STRING_COMMA_LEN ("neq") }, 13352 { STRING_COMMA_LEN ("nlt") }, 13353 { STRING_COMMA_LEN ("nle") }, 13354 { STRING_COMMA_LEN ("ord") } 13355 }; 13356 13357 static const struct op vex_cmp_op[] = 13358 { 13359 { STRING_COMMA_LEN ("eq_uq") }, 13360 { STRING_COMMA_LEN ("nge") }, 13361 { STRING_COMMA_LEN ("ngt") }, 13362 { STRING_COMMA_LEN ("false") }, 13363 { STRING_COMMA_LEN ("neq_oq") }, 13364 { STRING_COMMA_LEN ("ge") }, 13365 { STRING_COMMA_LEN ("gt") }, 13366 { STRING_COMMA_LEN ("true") }, 13367 { STRING_COMMA_LEN ("eq_os") }, 13368 { STRING_COMMA_LEN ("lt_oq") }, 13369 { STRING_COMMA_LEN ("le_oq") }, 13370 { STRING_COMMA_LEN ("unord_s") }, 13371 { STRING_COMMA_LEN ("neq_us") }, 13372 { STRING_COMMA_LEN ("nlt_uq") }, 13373 { STRING_COMMA_LEN ("nle_uq") }, 13374 { STRING_COMMA_LEN ("ord_s") }, 13375 { STRING_COMMA_LEN ("eq_us") }, 13376 { STRING_COMMA_LEN ("nge_uq") }, 13377 { STRING_COMMA_LEN ("ngt_uq") }, 13378 { STRING_COMMA_LEN ("false_os") }, 13379 { STRING_COMMA_LEN ("neq_os") }, 13380 { STRING_COMMA_LEN ("ge_oq") }, 13381 { STRING_COMMA_LEN ("gt_oq") }, 13382 { STRING_COMMA_LEN ("true_us") }, 13383 }; 13384 13385 static bool 13386 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13387 int sizeflag ATTRIBUTE_UNUSED) 13388 { 13389 unsigned int cmp_type; 13390 13391 if (!fetch_code (ins->info, ins->codep + 1)) 13392 return false; 13393 cmp_type = *ins->codep++; 13394 if (cmp_type < ARRAY_SIZE (simd_cmp_op)) 13395 { 13396 char suffix[3]; 13397 char *p = ins->mnemonicendp - 2; 13398 suffix[0] = p[0]; 13399 suffix[1] = p[1]; 13400 suffix[2] = '\0'; 13401 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 13402 ins->mnemonicendp += simd_cmp_op[cmp_type].len; 13403 } 13404 else if (ins->need_vex 13405 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) 13406 { 13407 char suffix[3]; 13408 char *p = ins->mnemonicendp - 2; 13409 suffix[0] = p[0]; 13410 suffix[1] = p[1]; 13411 suffix[2] = '\0'; 13412 cmp_type -= ARRAY_SIZE (simd_cmp_op); 13413 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); 13414 ins->mnemonicendp += vex_cmp_op[cmp_type].len; 13415 } 13416 else 13417 { 13418 /* We have a reserved extension byte. Output it directly. */ 13419 oappend_immediate (ins, cmp_type); 13420 } 13421 return true; 13422 } 13423 13424 static bool 13425 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13426 { 13427 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ 13428 if (!ins->intel_syntax) 13429 { 13430 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax); 13431 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); 13432 if (bytemode == eBX_reg) 13433 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax); 13434 ins->two_source_ops = true; 13435 } 13436 /* Skip mod/rm byte. */ 13437 MODRM_CHECK; 13438 ins->codep++; 13439 return true; 13440 } 13441 13442 static bool 13443 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13444 int sizeflag ATTRIBUTE_UNUSED) 13445 { 13446 /* monitor %{e,r,}ax,%ecx,%edx" */ 13447 if (!ins->intel_syntax) 13448 { 13449 const char (*names)[8] = (ins->address_mode == mode_64bit 13450 ? att_names64 : att_names32); 13451 13452 if (ins->prefixes & PREFIX_ADDR) 13453 { 13454 /* Remove "addr16/addr32". */ 13455 ins->all_prefixes[ins->last_addr_prefix] = 0; 13456 names = (ins->address_mode != mode_32bit 13457 ? att_names32 : att_names16); 13458 ins->used_prefixes |= PREFIX_ADDR; 13459 } 13460 else if (ins->address_mode == mode_16bit) 13461 names = att_names16; 13462 strcpy (ins->op_out[0], names[0] + ins->intel_syntax); 13463 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); 13464 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax); 13465 ins->two_source_ops = true; 13466 } 13467 /* Skip mod/rm byte. */ 13468 MODRM_CHECK; 13469 ins->codep++; 13470 return true; 13471 } 13472 13473 static bool 13474 REP_Fixup (instr_info *ins, int bytemode, int sizeflag) 13475 { 13476 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, 13477 lods and stos. */ 13478 if (ins->prefixes & PREFIX_REPZ) 13479 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX; 13480 13481 switch (bytemode) 13482 { 13483 case al_reg: 13484 case eAX_reg: 13485 case indir_dx_reg: 13486 return OP_IMREG (ins, bytemode, sizeflag); 13487 case eDI_reg: 13488 return OP_ESreg (ins, bytemode, sizeflag); 13489 case eSI_reg: 13490 return OP_DSreg (ins, bytemode, sizeflag); 13491 default: 13492 abort (); 13493 break; 13494 } 13495 return true; 13496 } 13497 13498 static bool 13499 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13500 int sizeflag ATTRIBUTE_UNUSED) 13501 { 13502 if (ins->isa64 != amd64) 13503 return true; 13504 13505 ins->obufp = ins->obuf; 13506 BadOp (ins); 13507 ins->mnemonicendp = ins->obufp; 13508 ++ins->codep; 13509 return true; 13510 } 13511 13512 /* For BND-prefixed instructions 0xF2 prefix should be displayed as 13513 "bnd". */ 13514 13515 static bool 13516 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13517 int sizeflag ATTRIBUTE_UNUSED) 13518 { 13519 if (ins->prefixes & PREFIX_REPNZ) 13520 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX; 13521 return true; 13522 } 13523 13524 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as 13525 "notrack". */ 13526 13527 static bool 13528 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13529 int sizeflag ATTRIBUTE_UNUSED) 13530 { 13531 /* Since active_seg_prefix is not set in 64-bit mode, check whether 13532 we've seen a PREFIX_DS. */ 13533 if ((ins->prefixes & PREFIX_DS) != 0 13534 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0)) 13535 { 13536 /* NOTRACK prefix is only valid on indirect branch instructions. 13537 NB: DATA prefix is unsupported for Intel64. */ 13538 ins->active_seg_prefix = 0; 13539 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX; 13540 } 13541 return true; 13542 } 13543 13544 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as 13545 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. 13546 */ 13547 13548 static bool 13549 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag) 13550 { 13551 if (ins->modrm.mod != 3 13552 && (ins->prefixes & PREFIX_LOCK) != 0) 13553 { 13554 if (ins->prefixes & PREFIX_REPZ) 13555 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13556 if (ins->prefixes & PREFIX_REPNZ) 13557 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13558 } 13559 13560 return OP_E (ins, bytemode, sizeflag); 13561 } 13562 13563 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as 13564 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. 13565 */ 13566 13567 static bool 13568 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag) 13569 { 13570 if (ins->modrm.mod != 3) 13571 { 13572 if (ins->prefixes & PREFIX_REPZ) 13573 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13574 if (ins->prefixes & PREFIX_REPNZ) 13575 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13576 } 13577 13578 return OP_E (ins, bytemode, sizeflag); 13579 } 13580 13581 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as 13582 "xrelease" for memory operand. No check for LOCK prefix. */ 13583 13584 static bool 13585 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag) 13586 { 13587 if (ins->modrm.mod != 3 13588 && ins->last_repz_prefix > ins->last_repnz_prefix 13589 && (ins->prefixes & PREFIX_REPZ) != 0) 13590 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13591 13592 return OP_E (ins, bytemode, sizeflag); 13593 } 13594 13595 static bool 13596 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag) 13597 { 13598 USED_REX (REX_W); 13599 if (ins->rex & REX_W) 13600 { 13601 /* Change cmpxchg8b to cmpxchg16b. */ 13602 char *p = ins->mnemonicendp - 2; 13603 ins->mnemonicendp = stpcpy (p, "16b"); 13604 bytemode = o_mode; 13605 } 13606 else if ((ins->prefixes & PREFIX_LOCK) != 0) 13607 { 13608 if (ins->prefixes & PREFIX_REPZ) 13609 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13610 if (ins->prefixes & PREFIX_REPNZ) 13611 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13612 } 13613 13614 return OP_M (ins, bytemode, sizeflag); 13615 } 13616 13617 static bool 13618 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED) 13619 { 13620 const char (*names)[8] = att_names_xmm; 13621 13622 if (ins->need_vex) 13623 { 13624 switch (ins->vex.length) 13625 { 13626 case 128: 13627 break; 13628 case 256: 13629 names = att_names_ymm; 13630 break; 13631 default: 13632 abort (); 13633 } 13634 } 13635 oappend_register (ins, names[reg]); 13636 return true; 13637 } 13638 13639 static bool 13640 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag) 13641 { 13642 /* Add proper suffix to "fxsave" and "fxrstor". */ 13643 USED_REX (REX_W); 13644 if (ins->rex & REX_W) 13645 { 13646 char *p = ins->mnemonicendp; 13647 *p++ = '6'; 13648 *p++ = '4'; 13649 *p = '\0'; 13650 ins->mnemonicendp = p; 13651 } 13652 return OP_M (ins, bytemode, sizeflag); 13653 } 13654 13655 /* Display the destination register operand for instructions with 13656 VEX. */ 13657 13658 static bool 13659 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13660 { 13661 int reg, modrm_reg, sib_index = -1; 13662 const char (*names)[8]; 13663 13664 if (!ins->need_vex) 13665 return true; 13666 13667 if (ins->evex_type == evex_from_legacy) 13668 { 13669 ins->evex_used |= EVEX_b_used; 13670 if (!ins->vex.nd) 13671 return true; 13672 } 13673 13674 reg = ins->vex.register_specifier; 13675 ins->vex.register_specifier = 0; 13676 if (ins->address_mode != mode_64bit) 13677 { 13678 if (ins->vex.evex && !ins->vex.v) 13679 { 13680 oappend (ins, "(bad)"); 13681 return true; 13682 } 13683 13684 reg &= 7; 13685 } 13686 else if (ins->vex.evex && !ins->vex.v) 13687 reg += 16; 13688 13689 switch (bytemode) 13690 { 13691 case scalar_mode: 13692 oappend_register (ins, att_names_xmm[reg]); 13693 return true; 13694 13695 case vex_vsib_d_w_dq_mode: 13696 case vex_vsib_q_w_dq_mode: 13697 /* This must be the 3rd operand. */ 13698 if (ins->obufp != ins->op_out[2]) 13699 abort (); 13700 if (ins->vex.length == 128 13701 || (bytemode != vex_vsib_d_w_dq_mode 13702 && !ins->vex.w)) 13703 oappend_register (ins, att_names_xmm[reg]); 13704 else 13705 oappend_register (ins, att_names_ymm[reg]); 13706 13707 /* All 3 XMM/YMM registers must be distinct. */ 13708 modrm_reg = ins->modrm.reg; 13709 if (ins->rex & REX_R) 13710 modrm_reg += 8; 13711 13712 if (ins->has_sib && ins->modrm.rm == 4) 13713 { 13714 sib_index = ins->sib.index; 13715 if (ins->rex & REX_X) 13716 sib_index += 8; 13717 } 13718 13719 if (reg == modrm_reg || reg == sib_index) 13720 strcpy (ins->obufp, "/(bad)"); 13721 if (modrm_reg == sib_index || modrm_reg == reg) 13722 strcat (ins->op_out[0], "/(bad)"); 13723 if (sib_index == modrm_reg || sib_index == reg) 13724 strcat (ins->op_out[1], "/(bad)"); 13725 13726 return true; 13727 13728 case tmm_mode: 13729 /* All 3 TMM registers must be distinct. */ 13730 if (reg >= 8) 13731 oappend (ins, "(bad)"); 13732 else 13733 { 13734 /* This must be the 3rd operand. */ 13735 if (ins->obufp != ins->op_out[2]) 13736 abort (); 13737 oappend_register (ins, att_names_tmm[reg]); 13738 if (reg == ins->modrm.reg || reg == ins->modrm.rm) 13739 strcpy (ins->obufp, "/(bad)"); 13740 } 13741 13742 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg 13743 || ins->modrm.rm == reg) 13744 { 13745 if (ins->modrm.reg <= 8 13746 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg)) 13747 strcat (ins->op_out[0], "/(bad)"); 13748 if (ins->modrm.rm <= 8 13749 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg)) 13750 strcat (ins->op_out[1], "/(bad)"); 13751 } 13752 13753 return true; 13754 } 13755 13756 switch (ins->vex.length) 13757 { 13758 case 128: 13759 switch (bytemode) 13760 { 13761 case x_mode: 13762 names = att_names_xmm; 13763 ins->evex_used |= EVEX_len_used; 13764 break; 13765 case v_mode: 13766 case dq_mode: 13767 if (ins->rex & REX_W) 13768 names = att_names64; 13769 else if (bytemode == v_mode 13770 && !(sizeflag & DFLAG)) 13771 names = att_names16; 13772 else 13773 names = att_names32; 13774 break; 13775 case b_mode: 13776 names = att_names8rex; 13777 break; 13778 case q_mode: 13779 names = att_names64; 13780 break; 13781 case mask_bd_mode: 13782 case mask_mode: 13783 if (reg > 0x7) 13784 { 13785 oappend (ins, "(bad)"); 13786 return true; 13787 } 13788 names = att_names_mask; 13789 break; 13790 default: 13791 abort (); 13792 return true; 13793 } 13794 break; 13795 case 256: 13796 switch (bytemode) 13797 { 13798 case x_mode: 13799 names = att_names_ymm; 13800 ins->evex_used |= EVEX_len_used; 13801 break; 13802 case mask_bd_mode: 13803 case mask_mode: 13804 if (reg <= 0x7) 13805 { 13806 names = att_names_mask; 13807 break; 13808 } 13809 /* Fall through. */ 13810 default: 13811 /* See PR binutils/20893 for a reproducer. */ 13812 oappend (ins, "(bad)"); 13813 return true; 13814 } 13815 break; 13816 case 512: 13817 names = att_names_zmm; 13818 ins->evex_used |= EVEX_len_used; 13819 break; 13820 default: 13821 abort (); 13822 break; 13823 } 13824 oappend_register (ins, names[reg]); 13825 return true; 13826 } 13827 13828 static bool 13829 OP_VexR (instr_info *ins, int bytemode, int sizeflag) 13830 { 13831 if (ins->modrm.mod == 3) 13832 return OP_VEX (ins, bytemode, sizeflag); 13833 return true; 13834 } 13835 13836 static bool 13837 OP_VexW (instr_info *ins, int bytemode, int sizeflag) 13838 { 13839 OP_VEX (ins, bytemode, sizeflag); 13840 13841 if (ins->vex.w) 13842 { 13843 /* Swap 2nd and 3rd operands. */ 13844 char *tmp = ins->op_out[2]; 13845 13846 ins->op_out[2] = ins->op_out[1]; 13847 ins->op_out[1] = tmp; 13848 } 13849 return true; 13850 } 13851 13852 static bool 13853 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13854 { 13855 int reg; 13856 const char (*names)[8] = att_names_xmm; 13857 13858 if (!fetch_code (ins->info, ins->codep + 1)) 13859 return false; 13860 reg = *ins->codep++; 13861 13862 if (bytemode != x_mode && bytemode != scalar_mode) 13863 abort (); 13864 13865 reg >>= 4; 13866 if (ins->address_mode != mode_64bit) 13867 reg &= 7; 13868 13869 if (bytemode == x_mode && ins->vex.length == 256) 13870 names = att_names_ymm; 13871 13872 oappend_register (ins, names[reg]); 13873 13874 if (ins->vex.w) 13875 { 13876 /* Swap 3rd and 4th operands. */ 13877 char *tmp = ins->op_out[3]; 13878 13879 ins->op_out[3] = ins->op_out[2]; 13880 ins->op_out[2] = tmp; 13881 } 13882 return true; 13883 } 13884 13885 static bool 13886 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13887 int sizeflag ATTRIBUTE_UNUSED) 13888 { 13889 oappend_immediate (ins, ins->codep[-1] & 0xf); 13890 return true; 13891 } 13892 13893 static bool 13894 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13895 int sizeflag ATTRIBUTE_UNUSED) 13896 { 13897 unsigned int cmp_type; 13898 13899 if (!ins->vex.evex) 13900 abort (); 13901 13902 if (!fetch_code (ins->info, ins->codep + 1)) 13903 return false; 13904 cmp_type = *ins->codep++; 13905 /* There are aliases for immediates 0, 1, 2, 4, 5, 6. 13906 If it's the case, print suffix, otherwise - print the immediate. */ 13907 if (cmp_type < ARRAY_SIZE (simd_cmp_op) 13908 && cmp_type != 3 13909 && cmp_type != 7) 13910 { 13911 char suffix[3]; 13912 char *p = ins->mnemonicendp - 2; 13913 13914 /* vpcmp* can have both one- and two-lettered suffix. */ 13915 if (p[0] == 'p') 13916 { 13917 p++; 13918 suffix[0] = p[0]; 13919 suffix[1] = '\0'; 13920 } 13921 else 13922 { 13923 suffix[0] = p[0]; 13924 suffix[1] = p[1]; 13925 suffix[2] = '\0'; 13926 } 13927 13928 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 13929 ins->mnemonicendp += simd_cmp_op[cmp_type].len; 13930 } 13931 else 13932 { 13933 /* We have a reserved extension byte. Output it directly. */ 13934 oappend_immediate (ins, cmp_type); 13935 } 13936 return true; 13937 } 13938 13939 static const struct op xop_cmp_op[] = 13940 { 13941 { STRING_COMMA_LEN ("lt") }, 13942 { STRING_COMMA_LEN ("le") }, 13943 { STRING_COMMA_LEN ("gt") }, 13944 { STRING_COMMA_LEN ("ge") }, 13945 { STRING_COMMA_LEN ("eq") }, 13946 { STRING_COMMA_LEN ("neq") }, 13947 { STRING_COMMA_LEN ("false") }, 13948 { STRING_COMMA_LEN ("true") } 13949 }; 13950 13951 static bool 13952 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13953 int sizeflag ATTRIBUTE_UNUSED) 13954 { 13955 unsigned int cmp_type; 13956 13957 if (!fetch_code (ins->info, ins->codep + 1)) 13958 return false; 13959 cmp_type = *ins->codep++; 13960 if (cmp_type < ARRAY_SIZE (xop_cmp_op)) 13961 { 13962 char suffix[3]; 13963 char *p = ins->mnemonicendp - 2; 13964 13965 /* vpcom* can have both one- and two-lettered suffix. */ 13966 if (p[0] == 'm') 13967 { 13968 p++; 13969 suffix[0] = p[0]; 13970 suffix[1] = '\0'; 13971 } 13972 else 13973 { 13974 suffix[0] = p[0]; 13975 suffix[1] = p[1]; 13976 suffix[2] = '\0'; 13977 } 13978 13979 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); 13980 ins->mnemonicendp += xop_cmp_op[cmp_type].len; 13981 } 13982 else 13983 { 13984 /* We have a reserved extension byte. Output it directly. */ 13985 oappend_immediate (ins, cmp_type); 13986 } 13987 return true; 13988 } 13989 13990 static const struct op pclmul_op[] = 13991 { 13992 { STRING_COMMA_LEN ("lql") }, 13993 { STRING_COMMA_LEN ("hql") }, 13994 { STRING_COMMA_LEN ("lqh") }, 13995 { STRING_COMMA_LEN ("hqh") } 13996 }; 13997 13998 static bool 13999 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 14000 int sizeflag ATTRIBUTE_UNUSED) 14001 { 14002 unsigned int pclmul_type; 14003 14004 if (!fetch_code (ins->info, ins->codep + 1)) 14005 return false; 14006 pclmul_type = *ins->codep++; 14007 switch (pclmul_type) 14008 { 14009 case 0x10: 14010 pclmul_type = 2; 14011 break; 14012 case 0x11: 14013 pclmul_type = 3; 14014 break; 14015 default: 14016 break; 14017 } 14018 if (pclmul_type < ARRAY_SIZE (pclmul_op)) 14019 { 14020 char suffix[4]; 14021 char *p = ins->mnemonicendp - 3; 14022 suffix[0] = p[0]; 14023 suffix[1] = p[1]; 14024 suffix[2] = p[2]; 14025 suffix[3] = '\0'; 14026 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); 14027 ins->mnemonicendp += pclmul_op[pclmul_type].len; 14028 } 14029 else 14030 { 14031 /* We have a reserved extension byte. Output it directly. */ 14032 oappend_immediate (ins, pclmul_type); 14033 } 14034 return true; 14035 } 14036 14037 static bool 14038 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag) 14039 { 14040 /* Add proper suffix to "movsxd". */ 14041 char *p = ins->mnemonicendp; 14042 14043 switch (bytemode) 14044 { 14045 case movsxd_mode: 14046 if (!ins->intel_syntax) 14047 { 14048 USED_REX (REX_W); 14049 if (ins->rex & REX_W) 14050 { 14051 *p++ = 'l'; 14052 *p++ = 'q'; 14053 break; 14054 } 14055 } 14056 14057 *p++ = 'x'; 14058 *p++ = 'd'; 14059 break; 14060 default: 14061 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 14062 break; 14063 } 14064 14065 ins->mnemonicendp = p; 14066 *p = '\0'; 14067 return OP_E (ins, bytemode, sizeflag); 14068 } 14069 14070 static bool 14071 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) 14072 { 14073 unsigned int reg = ins->vex.register_specifier; 14074 unsigned int modrm_reg = ins->modrm.reg; 14075 unsigned int modrm_rm = ins->modrm.rm; 14076 14077 /* Calc destination register number. */ 14078 if (ins->rex & REX_R) 14079 modrm_reg += 8; 14080 if (ins->rex2 & REX_R) 14081 modrm_reg += 16; 14082 14083 /* Calc src1 register number. */ 14084 if (ins->address_mode != mode_64bit) 14085 reg &= 7; 14086 else if (ins->vex.evex && !ins->vex.v) 14087 reg += 16; 14088 14089 /* Calc src2 register number. */ 14090 if (ins->modrm.mod == 3) 14091 { 14092 if (ins->rex & REX_B) 14093 modrm_rm += 8; 14094 if (ins->rex & REX_X) 14095 modrm_rm += 16; 14096 } 14097 14098 /* Destination and source registers must be distinct, output bad if 14099 dest == src1 or dest == src2. */ 14100 if (modrm_reg == reg 14101 || (ins->modrm.mod == 3 14102 && modrm_reg == modrm_rm)) 14103 { 14104 oappend (ins, "(bad)"); 14105 return true; 14106 } 14107 return OP_XMM (ins, bytemode, sizeflag); 14108 } 14109 14110 static bool 14111 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14112 { 14113 if (ins->modrm.mod != 3 || !ins->vex.b) 14114 return true; 14115 14116 switch (bytemode) 14117 { 14118 case evex_rounding_64_mode: 14119 if (ins->address_mode != mode_64bit || !ins->vex.w) 14120 return true; 14121 /* Fall through. */ 14122 case evex_rounding_mode: 14123 ins->evex_used |= EVEX_b_used; 14124 oappend (ins, names_rounding[ins->vex.ll]); 14125 break; 14126 case evex_sae_mode: 14127 ins->evex_used |= EVEX_b_used; 14128 oappend (ins, "{"); 14129 break; 14130 default: 14131 abort (); 14132 } 14133 oappend (ins, "sae}"); 14134 return true; 14135 } 14136 14137 static bool 14138 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) 14139 { 14140 if (ins->modrm.mod != 0 || ins->modrm.rm != 5) 14141 { 14142 if (ins->intel_syntax) 14143 { 14144 ins->mnemonicendp = stpcpy (ins->obuf, "nop "); 14145 } 14146 else 14147 { 14148 USED_REX (REX_W); 14149 if (ins->rex & REX_W) 14150 ins->mnemonicendp = stpcpy (ins->obuf, "nopq "); 14151 else 14152 { 14153 if (sizeflag & DFLAG) 14154 ins->mnemonicendp = stpcpy (ins->obuf, "nopl "); 14155 else 14156 ins->mnemonicendp = stpcpy (ins->obuf, "nopw "); 14157 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 14158 } 14159 } 14160 bytemode = v_mode; 14161 } 14162 14163 return OP_M (ins, bytemode, sizeflag); 14164 } 14165 14166 static bool 14167 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag) 14168 { 14169 if (ins->modrm.mod != 3) 14170 return true; 14171 14172 unsigned int vvvv_reg = ins->vex.register_specifier 14173 | (!ins->vex.v << 4); 14174 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) 14175 + (ins->rex2 & REX_B ? 16 : 0); 14176 14177 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ 14178 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4 14179 || (!ins->modrm.reg 14180 && vvvv_reg == rm_reg)) 14181 { 14182 oappend (ins, "(bad)"); 14183 return true; 14184 } 14185 14186 return OP_VEX (ins, bytemode, sizeflag); 14187 } 14188 14189 static bool 14190 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag) 14191 { 14192 if (ins->last_rex2_prefix >= 0) 14193 { 14194 uint64_t op; 14195 14196 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0 14197 || (ins->rex & REX_W) != 0x0) 14198 { 14199 oappend (ins, "(bad)"); 14200 return true; 14201 } 14202 14203 if (bytemode == eAX_reg) 14204 return true; 14205 14206 if (!get64 (ins, &op)) 14207 return false; 14208 14209 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs"); 14210 ins->rex2 |= REX2_SPECIAL; 14211 oappend_immediate (ins, op); 14212 14213 return true; 14214 } 14215 14216 if (bytemode == eAX_reg) 14217 return OP_IMREG (ins, bytemode, sizeflag); 14218 return OP_OFF64 (ins, bytemode, sizeflag); 14219 } 14220 14221 static bool 14222 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag) 14223 { 14224 /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the 14225 source and destination operands. */ 14226 bool dstmem = !ins->vex.nd && ins->vex.nf; 14227 14228 if (opnd == 0) 14229 { 14230 if (dstmem) 14231 return OP_E (ins, v_swap_mode, sizeflag); 14232 return OP_G (ins, v_mode, sizeflag); 14233 } 14234 14235 /* These bits have been consumed and should be cleared. */ 14236 ins->vex.nf = false; 14237 ins->vex.mask_register_specifier = 0; 14238 14239 if (dstmem) 14240 return OP_G (ins, v_mode, sizeflag); 14241 return OP_E (ins, v_mode, sizeflag); 14242 } 14243
Indexes created Mon Mar 23 00:23:30 UTC 2026