i386-dis.c revision 1.1.1.13
1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright (C) 1988-2025 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* 80386 instruction printer by Pace Willisson (pace (at) prep.ai.mit.edu) 23 July 1988 24 modified by John Hassey (hassey (at) dg-rtp.dg.com) 25 x86-64 support added by Jan Hubicka (jh (at) suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz). */ 27 28 /* The main tables describing the instructions is essentially a copy 29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 30 Programmers Manual. Usually, there is a capital letter, followed 31 by a small letter. The capital letter tell the addressing mode, 32 and the small letter tells about the operand size. Refer to 33 the Intel manual for details. */ 34 35 #include "sysdep.h" 36 #include "disassemble.h" 37 #include "opintl.h" 38 #include "opcode/i386.h" 39 #include "libiberty.h" 40 #include "safe-ctype.h" 41 42 typedef struct instr_info instr_info; 43 44 static bool dofloat (instr_info *, int); 45 static int putop (instr_info *, const char *, int); 46 static void oappend_with_style (instr_info *, const char *, 47 enum disassembler_style); 48 49 static bool OP_E (instr_info *, int, int); 50 static bool OP_E_memory (instr_info *, int, int); 51 static bool OP_indirE (instr_info *, int, int); 52 static bool OP_G (instr_info *, int, int); 53 static bool OP_ST (instr_info *, int, int); 54 static bool OP_STi (instr_info *, int, int); 55 static bool OP_Skip_MODRM (instr_info *, int, int); 56 static bool OP_REG (instr_info *, int, int); 57 static bool OP_IMREG (instr_info *, int, int); 58 static bool OP_I (instr_info *, int, int); 59 static bool OP_I64 (instr_info *, int, int); 60 static bool OP_sI (instr_info *, int, int); 61 static bool OP_J (instr_info *, int, int); 62 static bool OP_SEG (instr_info *, int, int); 63 static bool OP_DIR (instr_info *, int, int); 64 static bool OP_OFF (instr_info *, int, int); 65 static bool OP_OFF64 (instr_info *, int, int); 66 static bool OP_ESreg (instr_info *, int, int); 67 static bool OP_DSreg (instr_info *, int, int); 68 static bool OP_C (instr_info *, int, int); 69 static bool OP_D (instr_info *, int, int); 70 static bool OP_T (instr_info *, int, int); 71 static bool OP_MMX (instr_info *, int, int); 72 static bool OP_XMM (instr_info *, int, int); 73 static bool OP_EM (instr_info *, int, int); 74 static bool OP_EX (instr_info *, int, int); 75 static bool OP_EMC (instr_info *, int,int); 76 static bool OP_MXC (instr_info *, int,int); 77 static bool OP_R (instr_info *, int, int); 78 static bool OP_M (instr_info *, int, int); 79 static bool OP_VEX (instr_info *, int, int); 80 static bool OP_VexR (instr_info *, int, int); 81 static bool OP_VexW (instr_info *, int, int); 82 static bool OP_Rounding (instr_info *, int, int); 83 static bool OP_REG_VexI4 (instr_info *, int, int); 84 static bool OP_VexI4 (instr_info *, int, int); 85 static bool OP_0f07 (instr_info *, int, int); 86 static bool OP_Monitor (instr_info *, int, int); 87 static bool OP_Mwait (instr_info *, int, int); 88 89 static bool PCLMUL_Fixup (instr_info *, int, int); 90 static bool VPCMP_Fixup (instr_info *, int, int); 91 static bool VPCOM_Fixup (instr_info *, int, int); 92 static bool NOP_Fixup (instr_info *, int, int); 93 static bool MONTMUL_Fixup (instr_info *, int, int); 94 static bool OP_3DNowSuffix (instr_info *, int, int); 95 static bool CMP_Fixup (instr_info *, int, int); 96 static bool REP_Fixup (instr_info *, int, int); 97 static bool SEP_Fixup (instr_info *, int, int); 98 static bool BND_Fixup (instr_info *, int, int); 99 static bool NOTRACK_Fixup (instr_info *, int, int); 100 static bool HLE_Fixup1 (instr_info *, int, int); 101 static bool HLE_Fixup2 (instr_info *, int, int); 102 static bool HLE_Fixup3 (instr_info *, int, int); 103 static bool CMPXCHG8B_Fixup (instr_info *, int, int); 104 static bool XMM_Fixup (instr_info *, int, int); 105 static bool FXSAVE_Fixup (instr_info *, int, int); 106 static bool MOVSXD_Fixup (instr_info *, int, int); 107 static bool DistinctDest_Fixup (instr_info *, int, int); 108 static bool PREFETCHI_Fixup (instr_info *, int, int); 109 static bool PUSH2_POP2_Fixup (instr_info *, int, int); 110 static bool JMPABS_Fixup (instr_info *, int, int); 111 static bool CFCMOV_Fixup (instr_info *, int, int); 112 113 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, 114 enum disassembler_style, 115 const char *, ...); 116 117 /* This character is used to encode style information within the output 118 buffers. See oappend_insert_style for more details. */ 119 #define STYLE_MARKER_CHAR '\002' 120 121 /* The maximum operand buffer size. */ 122 #define MAX_OPERAND_BUFFER_SIZE 128 123 124 enum address_mode 125 { 126 mode_16bit, 127 mode_32bit, 128 mode_64bit 129 }; 130 131 static const char *prefix_name (enum address_mode, uint8_t, int); 132 133 enum x86_64_isa 134 { 135 amd64 = 1, 136 intel64 137 }; 138 139 enum evex_type 140 { 141 evex_default = 0, 142 evex_from_legacy, 143 evex_from_vex, 144 }; 145 146 struct instr_info 147 { 148 enum address_mode address_mode; 149 150 /* Flags for the prefixes for the current instruction. See below. */ 151 int prefixes; 152 153 /* REX prefix the current instruction. See below. */ 154 uint8_t rex; 155 /* Bits of REX we've already used. */ 156 uint8_t rex_used; 157 158 /* Record W R4 X4 B4 bits for rex2. */ 159 unsigned char rex2; 160 /* Bits of rex2 we've already used. */ 161 unsigned char rex2_used; 162 unsigned char rex2_payload; 163 164 bool need_modrm; 165 unsigned char condition_code; 166 unsigned char need_vex; 167 bool has_sib; 168 169 /* Flags for ins->prefixes which we somehow handled when printing the 170 current instruction. */ 171 int used_prefixes; 172 173 /* Flags for EVEX bits which we somehow handled when printing the 174 current instruction. */ 175 int evex_used; 176 177 char obuf[MAX_OPERAND_BUFFER_SIZE]; 178 char *obufp; 179 char *mnemonicendp; 180 const uint8_t *start_codep; 181 uint8_t *codep; 182 const uint8_t *end_codep; 183 unsigned char nr_prefixes; 184 signed char last_lock_prefix; 185 signed char last_repz_prefix; 186 signed char last_repnz_prefix; 187 signed char last_data_prefix; 188 signed char last_addr_prefix; 189 signed char last_rex_prefix; 190 signed char last_rex2_prefix; 191 signed char last_seg_prefix; 192 signed char fwait_prefix; 193 /* The active segment register prefix. */ 194 unsigned char active_seg_prefix; 195 196 #define MAX_CODE_LENGTH 15 197 /* We can up to 14 ins->prefixes since the maximum instruction length is 198 15bytes. */ 199 uint8_t all_prefixes[MAX_CODE_LENGTH - 1]; 200 disassemble_info *info; 201 202 struct 203 { 204 int mod; 205 int reg; 206 int rm; 207 } 208 modrm; 209 210 struct 211 { 212 int scale; 213 int index; 214 int base; 215 } 216 sib; 217 218 struct 219 { 220 int register_specifier; 221 int length; 222 int prefix; 223 int mask_register_specifier; 224 int scc; 225 int ll; 226 bool w; 227 bool evex; 228 bool v; 229 bool zeroing; 230 bool b; 231 bool no_broadcast; 232 bool nf; 233 } 234 vex; 235 236 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */ 237 #define nd b 238 239 enum evex_type evex_type; 240 241 /* Remember if the current op is a jump instruction. */ 242 bool op_is_jump; 243 244 bool two_source_ops; 245 246 /* Record whether EVEX masking is used incorrectly. */ 247 bool illegal_masking; 248 249 /* Record whether the modrm byte has been skipped. */ 250 bool has_skipped_modrm; 251 252 unsigned char op_ad; 253 signed char op_index[MAX_OPERANDS]; 254 bool op_riprel[MAX_OPERANDS]; 255 char *op_out[MAX_OPERANDS]; 256 bfd_vma op_address[MAX_OPERANDS]; 257 bfd_vma start_pc; 258 259 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes. 260 * (see topic "Redundant ins->prefixes" in the "Differences from 8086" 261 * section of the "Virtual 8086 Mode" chapter.) 262 * 'pc' should be the address of this instruction, it will 263 * be used to print the target address if this is a relative jump or call 264 * The function returns the length of this instruction in bytes. 265 */ 266 char intel_syntax; 267 bool intel_mnemonic; 268 char open_char; 269 char close_char; 270 char separator_char; 271 char scale_char; 272 273 enum x86_64_isa isa64; 274 }; 275 276 struct dis_private { 277 bfd_vma insn_start; 278 int orig_sizeflag; 279 280 /* Indexes first byte not fetched. */ 281 unsigned int fetched; 282 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1]; 283 }; 284 285 /* Mark parts used in the REX prefix. When we are testing for 286 empty prefix (for 8bit register REX extension), just mask it 287 out. Otherwise test for REX bit is excuse for existence of REX 288 only in case value is nonzero. */ 289 #define USED_REX(value) \ 290 { \ 291 if (value) \ 292 { \ 293 if (ins->rex & value) \ 294 ins->rex_used |= (value) | REX_OPCODE; \ 295 if (ins->rex2 & value) \ 296 { \ 297 ins->rex2_used |= (value); \ 298 ins->rex_used |= REX_OPCODE; \ 299 } \ 300 } \ 301 else \ 302 ins->rex_used |= REX_OPCODE; \ 303 } 304 305 306 #define EVEX_b_used 1 307 #define EVEX_len_used 2 308 309 310 /* {rex2} is not printed when the REX2_SPECIAL is set. */ 311 #define REX2_SPECIAL 16 312 313 /* Flags stored in PREFIXES. */ 314 #define PREFIX_REPZ 1 315 #define PREFIX_REPNZ 2 316 #define PREFIX_CS 4 317 #define PREFIX_SS 8 318 #define PREFIX_DS 0x10 319 #define PREFIX_ES 0x20 320 #define PREFIX_FS 0x40 321 #define PREFIX_GS 0x80 322 #define PREFIX_LOCK 0x100 323 #define PREFIX_DATA 0x200 324 #define PREFIX_ADDR 0x400 325 #define PREFIX_FWAIT 0x800 326 #define PREFIX_REX2 0x1000 327 #define PREFIX_NP_OR_DATA 0x2000 328 #define NO_PREFIX 0x4000 329 330 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 331 to ADDR (exclusive) are valid. Returns true for success, false 332 on error. */ 333 static bool 334 fetch_code (struct disassemble_info *info, const uint8_t *until) 335 { 336 int status = -1; 337 struct dis_private *priv = info->private_data; 338 bfd_vma start = priv->insn_start + priv->fetched; 339 uint8_t *fetch_end = priv->the_buffer + priv->fetched; 340 ptrdiff_t needed = until - fetch_end; 341 342 if (needed <= 0) 343 return true; 344 345 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer)) 346 status = (*info->read_memory_func) (start, fetch_end, needed, info); 347 if (status != 0) 348 { 349 /* If we did manage to read at least one byte, then 350 print_insn_i386 will do something sensible. Otherwise, print 351 an error. We do that here because this is where we know 352 STATUS. */ 353 if (!priv->fetched) 354 (*info->memory_error_func) (status, start, info); 355 return false; 356 } 357 358 priv->fetched += needed; 359 return true; 360 } 361 362 static bool 363 fetch_modrm (instr_info *ins) 364 { 365 if (!fetch_code (ins->info, ins->codep + 1)) 366 return false; 367 368 ins->modrm.mod = (*ins->codep >> 6) & 3; 369 ins->modrm.reg = (*ins->codep >> 3) & 7; 370 ins->modrm.rm = *ins->codep & 7; 371 372 return true; 373 } 374 375 static int 376 fetch_error (const instr_info *ins) 377 { 378 /* Getting here means we tried for data but didn't get it. That 379 means we have an incomplete instruction of some sort. Just 380 print the first byte as a prefix or a .byte pseudo-op. */ 381 const struct dis_private *priv = ins->info->private_data; 382 const char *name = NULL; 383 384 if (ins->codep <= priv->the_buffer) 385 return -1; 386 387 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE)) 388 name = prefix_name (ins->address_mode, priv->the_buffer[0], 389 priv->orig_sizeflag); 390 if (name != NULL) 391 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name); 392 else 393 { 394 /* Just print the first byte as a .byte instruction. */ 395 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte "); 396 i386_dis_printf (ins->info, dis_style_immediate, "%#x", 397 (unsigned int) priv->the_buffer[0]); 398 } 399 400 return 1; 401 } 402 403 /* Possible values for prefix requirement. */ 404 #define PREFIX_IGNORED_SHIFT 16 405 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) 406 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) 407 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) 408 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) 409 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) 410 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT) 411 412 /* Opcode prefixes. */ 413 #define PREFIX_OPCODE (PREFIX_REPZ \ 414 | PREFIX_REPNZ \ 415 | PREFIX_DATA) 416 417 /* Prefixes ignored. */ 418 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ 419 | PREFIX_IGNORED_REPNZ \ 420 | PREFIX_IGNORED_DATA) 421 422 #define XX { NULL, 0 } 423 #define Bad_Opcode NULL, { { NULL, 0 } }, 0 424 425 #define Eb { OP_E, b_mode } 426 #define Ebnd { OP_E, bnd_mode } 427 #define EbS { OP_E, b_swap_mode } 428 #define EbndS { OP_E, bnd_swap_mode } 429 #define Ev { OP_E, v_mode } 430 #define Eva { OP_E, va_mode } 431 #define Ev_bnd { OP_E, v_bnd_mode } 432 #define EvS { OP_E, v_swap_mode } 433 #define Ed { OP_E, d_mode } 434 #define Edq { OP_E, dq_mode } 435 #define Edb { OP_E, db_mode } 436 #define Edw { OP_E, dw_mode } 437 #define Eq { OP_E, q_mode } 438 #define indirEv { OP_indirE, indir_v_mode } 439 #define indirEp { OP_indirE, f_mode } 440 #define stackEv { OP_E, stack_v_mode } 441 #define Em { OP_E, m_mode } 442 #define Ew { OP_E, w_mode } 443 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 444 #define Ma { OP_M, a_mode } 445 #define Mb { OP_M, b_mode } 446 #define Md { OP_M, d_mode } 447 #define Mdq { OP_M, dq_mode } 448 #define Mo { OP_M, o_mode } 449 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 450 #define Mq { OP_M, q_mode } 451 #define Mv { OP_M, v_mode } 452 #define Mv_bnd { OP_M, v_bndmk_mode } 453 #define Mw { OP_M, w_mode } 454 #define Mx { OP_M, x_mode } 455 #define Mxmm { OP_M, xmm_mode } 456 #define Mymm { OP_M, ymm_mode } 457 #define Gb { OP_G, b_mode } 458 #define Gbnd { OP_G, bnd_mode } 459 #define Gv { OP_G, v_mode } 460 #define Gd { OP_G, d_mode } 461 #define Gdq { OP_G, dq_mode } 462 #define Gq { OP_G, q_mode } 463 #define Gm { OP_G, m_mode } 464 #define Gva { OP_G, va_mode } 465 #define Gw { OP_G, w_mode } 466 #define Ib { OP_I, b_mode } 467 #define sIb { OP_sI, b_mode } /* sign extened byte */ 468 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ 469 #define Iv { OP_I, v_mode } 470 #define sIv { OP_sI, v_mode } 471 #define Iv64 { OP_I64, v_mode } 472 #define Id { OP_I, d_mode } 473 #define Iw { OP_I, w_mode } 474 #define I1 { OP_I, const_1_mode } 475 #define Jb { OP_J, b_mode } 476 #define Jv { OP_J, v_mode } 477 #define Jdqw { OP_J, dqw_mode } 478 #define Cm { OP_C, m_mode } 479 #define Dm { OP_D, m_mode } 480 #define Td { OP_T, d_mode } 481 #define Skip_MODRM { OP_Skip_MODRM, 0 } 482 483 #define RMeAX { OP_REG, eAX_reg } 484 #define RMeBX { OP_REG, eBX_reg } 485 #define RMeCX { OP_REG, eCX_reg } 486 #define RMeDX { OP_REG, eDX_reg } 487 #define RMeSP { OP_REG, eSP_reg } 488 #define RMeBP { OP_REG, eBP_reg } 489 #define RMeSI { OP_REG, eSI_reg } 490 #define RMeDI { OP_REG, eDI_reg } 491 #define RMrAX { OP_REG, rAX_reg } 492 #define RMrBX { OP_REG, rBX_reg } 493 #define RMrCX { OP_REG, rCX_reg } 494 #define RMrDX { OP_REG, rDX_reg } 495 #define RMrSP { OP_REG, rSP_reg } 496 #define RMrBP { OP_REG, rBP_reg } 497 #define RMrSI { OP_REG, rSI_reg } 498 #define RMrDI { OP_REG, rDI_reg } 499 #define RMAL { OP_REG, al_reg } 500 #define RMCL { OP_REG, cl_reg } 501 #define RMDL { OP_REG, dl_reg } 502 #define RMBL { OP_REG, bl_reg } 503 #define RMAH { OP_REG, ah_reg } 504 #define RMCH { OP_REG, ch_reg } 505 #define RMDH { OP_REG, dh_reg } 506 #define RMBH { OP_REG, bh_reg } 507 #define RMAX { OP_REG, ax_reg } 508 #define RMDX { OP_REG, dx_reg } 509 510 #define eAX { OP_IMREG, eAX_reg } 511 #define AL { OP_IMREG, al_reg } 512 #define CL { OP_IMREG, cl_reg } 513 #define zAX { OP_IMREG, z_mode_ax_reg } 514 #define indirDX { OP_IMREG, indir_dx_reg } 515 516 #define Sw { OP_SEG, w_mode } 517 #define Sv { OP_SEG, v_mode } 518 #define Ap { OP_DIR, 0 } 519 #define Ob { OP_OFF64, b_mode } 520 #define Ov { OP_OFF64, v_mode } 521 #define Xb { OP_DSreg, eSI_reg } 522 #define Xv { OP_DSreg, eSI_reg } 523 #define Xz { OP_DSreg, eSI_reg } 524 #define Yb { OP_ESreg, eDI_reg } 525 #define Yv { OP_ESreg, eDI_reg } 526 #define DSCX { OP_DSreg, eCX_reg } 527 #define DSBX { OP_DSreg, eBX_reg } 528 529 #define es { OP_REG, es_reg } 530 #define ss { OP_REG, ss_reg } 531 #define cs { OP_REG, cs_reg } 532 #define ds { OP_REG, ds_reg } 533 #define fs { OP_REG, fs_reg } 534 #define gs { OP_REG, gs_reg } 535 536 #define MX { OP_MMX, 0 } 537 #define XM { OP_XMM, 0 } 538 #define XMScalar { OP_XMM, scalar_mode } 539 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode } 540 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } 541 #define XMM { OP_XMM, xmm_mode } 542 #define TMM { OP_XMM, tmm_mode } 543 #define XMxmmq { OP_XMM, xmmq_mode } 544 #define EM { OP_EM, v_mode } 545 #define EMS { OP_EM, v_swap_mode } 546 #define EMd { OP_EM, d_mode } 547 #define EMx { OP_EM, x_mode } 548 #define EXbwUnit { OP_EX, bw_unit_mode } 549 #define EXb { OP_EX, b_mode } 550 #define EXw { OP_EX, w_mode } 551 #define EXd { OP_EX, d_mode } 552 #define EXdS { OP_EX, d_swap_mode } 553 #define EXwS { OP_EX, w_swap_mode } 554 #define EXq { OP_EX, q_mode } 555 #define EXqS { OP_EX, q_swap_mode } 556 #define EXdq { OP_EX, dq_mode } 557 #define EXx { OP_EX, x_mode } 558 #define EXxh { OP_EX, xh_mode } 559 #define EXxS { OP_EX, x_swap_mode } 560 #define EXxmm { OP_EX, xmm_mode } 561 #define EXymm { OP_EX, ymm_mode } 562 #define EXxmmq { OP_EX, xmmq_mode } 563 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode } 564 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } 565 #define EXxmmdw { OP_EX, xmmdw_mode } 566 #define EXxmmqd { OP_EX, xmmqd_mode } 567 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode } 568 #define EXymmq { OP_EX, ymmq_mode } 569 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } 570 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } 571 #define Rd { OP_R, d_mode } 572 #define Rdq { OP_R, dq_mode } 573 #define Rq { OP_R, q_mode } 574 #define Nq { OP_R, q_mm_mode } 575 #define Ux { OP_R, x_mode } 576 #define Uxmm { OP_R, xmm_mode } 577 #define Rxmmq { OP_R, xmmq_mode } 578 #define Rymm { OP_R, ymm_mode } 579 #define Rtmm { OP_R, tmm_mode } 580 #define EMCq { OP_EMC, q_mode } 581 #define MXC { OP_MXC, 0 } 582 #define OPSUF { OP_3DNowSuffix, 0 } 583 #define SEP { SEP_Fixup, 0 } 584 #define CMP { CMP_Fixup, 0 } 585 #define XMM0 { XMM_Fixup, 0 } 586 #define FXSAVE { FXSAVE_Fixup, 0 } 587 588 #define Vex { OP_VEX, x_mode } 589 #define VexW { OP_VexW, x_mode } 590 #define VexScalar { OP_VEX, scalar_mode } 591 #define VexScalarR { OP_VexR, scalar_mode } 592 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } 593 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } 594 #define VexGdq { OP_VEX, dq_mode } 595 #define VexGb { OP_VEX, b_mode } 596 #define VexGv { OP_VEX, v_mode } 597 #define VexTmm { OP_VEX, tmm_mode } 598 #define XMVexI4 { OP_REG_VexI4, x_mode } 599 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } 600 #define VexI4 { OP_VexI4, 0 } 601 #define PCLMUL { PCLMUL_Fixup, 0 } 602 #define VPCMP { VPCMP_Fixup, 0 } 603 #define VPCOM { VPCOM_Fixup, 0 } 604 605 #define EXxEVexR { OP_Rounding, evex_rounding_mode } 606 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } 607 #define EXxEVexS { OP_Rounding, evex_sae_mode } 608 609 #define MaskG { OP_G, mask_mode } 610 #define MaskE { OP_E, mask_mode } 611 #define MaskR { OP_R, mask_mode } 612 #define MaskBDE { OP_E, mask_bd_mode } 613 #define MaskVex { OP_VEX, mask_mode } 614 615 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } 616 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } 617 618 #define MVexSIBMEM { OP_M, vex_sibmem_mode } 619 620 /* Used handle "rep" prefix for string instructions. */ 621 #define Xbr { REP_Fixup, eSI_reg } 622 #define Xvr { REP_Fixup, eSI_reg } 623 #define Ybr { REP_Fixup, eDI_reg } 624 #define Yvr { REP_Fixup, eDI_reg } 625 #define Yzr { REP_Fixup, eDI_reg } 626 #define indirDXr { REP_Fixup, indir_dx_reg } 627 #define ALr { REP_Fixup, al_reg } 628 #define eAXr { REP_Fixup, eAX_reg } 629 630 /* Used handle HLE prefix for lockable instructions. */ 631 #define Ebh1 { HLE_Fixup1, b_mode } 632 #define Evh1 { HLE_Fixup1, v_mode } 633 #define Ebh2 { HLE_Fixup2, b_mode } 634 #define Evh2 { HLE_Fixup2, v_mode } 635 #define Ebh3 { HLE_Fixup3, b_mode } 636 #define Evh3 { HLE_Fixup3, v_mode } 637 638 #define BND { BND_Fixup, 0 } 639 #define NOTRACK { NOTRACK_Fixup, 0 } 640 641 #define cond_jump_flag { NULL, cond_jump_mode } 642 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 643 644 /* bits in sizeflag */ 645 #define SUFFIX_ALWAYS 4 646 #define AFLAG 2 647 #define DFLAG 1 648 649 enum 650 { 651 /* byte operand */ 652 b_mode = 1, 653 /* byte operand with operand swapped */ 654 b_swap_mode, 655 /* byte operand, sign extend like 'T' suffix */ 656 b_T_mode, 657 /* operand size depends on prefixes */ 658 v_mode, 659 /* operand size depends on prefixes with operand swapped */ 660 v_swap_mode, 661 /* operand size depends on address prefix */ 662 va_mode, 663 /* word operand */ 664 w_mode, 665 /* double word operand */ 666 d_mode, 667 /* word operand with operand swapped */ 668 w_swap_mode, 669 /* double word operand with operand swapped */ 670 d_swap_mode, 671 /* quad word operand */ 672 q_mode, 673 /* 8-byte MM operand */ 674 q_mm_mode, 675 /* quad word operand with operand swapped */ 676 q_swap_mode, 677 /* ten-byte operand */ 678 t_mode, 679 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 680 broadcast enabled. */ 681 x_mode, 682 /* Similar to x_mode, but with different EVEX mem shifts. */ 683 evex_x_gscat_mode, 684 /* Similar to x_mode, but with yet different EVEX mem shifts. */ 685 bw_unit_mode, 686 /* Similar to x_mode, but with disabled broadcast. */ 687 evex_x_nobcst_mode, 688 /* Similar to x_mode, but with operands swapped and disabled broadcast 689 in EVEX. */ 690 x_swap_mode, 691 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 692 broadcast of 16bit enabled. */ 693 xh_mode, 694 /* 16-byte XMM operand */ 695 xmm_mode, 696 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 697 memory operand (depending on vector length). Broadcast isn't 698 allowed. */ 699 xmmq_mode, 700 /* Same as xmmq_mode, but broadcast is allowed. */ 701 evex_half_bcst_xmmq_mode, 702 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 703 memory operand (depending on vector length). 16bit broadcast. */ 704 evex_half_bcst_xmmqh_mode, 705 /* 16-byte XMM, word, double word or quad word operand. */ 706 xmmdw_mode, 707 /* 16-byte XMM, double word, quad word operand or xmm word operand. */ 708 xmmqd_mode, 709 /* 16-byte XMM, double word, quad word operand or xmm word operand. 710 16bit broadcast. */ 711 evex_half_bcst_xmmqdh_mode, 712 /* 32-byte YMM operand */ 713 ymm_mode, 714 /* quad word, ymmword or zmmword memory operand. */ 715 ymmq_mode, 716 /* TMM operand */ 717 tmm_mode, 718 /* d_mode in 32bit, q_mode in 64bit mode. */ 719 m_mode, 720 /* pair of v_mode operands */ 721 a_mode, 722 cond_jump_mode, 723 loop_jcxz_mode, 724 movsxd_mode, 725 v_bnd_mode, 726 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ 727 v_bndmk_mode, 728 /* operand size depends on REX.W / VEX.W. */ 729 dq_mode, 730 /* Displacements like v_mode without considering Intel64 ISA. */ 731 dqw_mode, 732 /* bounds operand */ 733 bnd_mode, 734 /* bounds operand with operand swapped */ 735 bnd_swap_mode, 736 /* 4- or 6-byte pointer operand */ 737 f_mode, 738 const_1_mode, 739 /* v_mode for indirect branch opcodes. */ 740 indir_v_mode, 741 /* v_mode for stack-related opcodes. */ 742 stack_v_mode, 743 /* non-quad operand size depends on prefixes */ 744 z_mode, 745 /* 16-byte operand */ 746 o_mode, 747 /* registers like d_mode, memory like b_mode. */ 748 db_mode, 749 /* registers like d_mode, memory like w_mode. */ 750 dw_mode, 751 752 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ 753 vex_vsib_d_w_dq_mode, 754 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ 755 vex_vsib_q_w_dq_mode, 756 /* mandatory non-vector SIB. */ 757 vex_sibmem_mode, 758 759 /* scalar, ignore vector length. */ 760 scalar_mode, 761 762 /* Static rounding. */ 763 evex_rounding_mode, 764 /* Static rounding, 64-bit mode only. */ 765 evex_rounding_64_mode, 766 /* Supress all exceptions. */ 767 evex_sae_mode, 768 769 /* Mask register operand. */ 770 mask_mode, 771 /* Mask register operand. */ 772 mask_bd_mode, 773 774 es_reg, 775 cs_reg, 776 ss_reg, 777 ds_reg, 778 fs_reg, 779 gs_reg, 780 781 eAX_reg, 782 eCX_reg, 783 eDX_reg, 784 eBX_reg, 785 eSP_reg, 786 eBP_reg, 787 eSI_reg, 788 eDI_reg, 789 790 al_reg, 791 cl_reg, 792 dl_reg, 793 bl_reg, 794 ah_reg, 795 ch_reg, 796 dh_reg, 797 bh_reg, 798 799 ax_reg, 800 cx_reg, 801 dx_reg, 802 bx_reg, 803 sp_reg, 804 bp_reg, 805 si_reg, 806 di_reg, 807 808 rAX_reg, 809 rCX_reg, 810 rDX_reg, 811 rBX_reg, 812 rSP_reg, 813 rBP_reg, 814 rSI_reg, 815 rDI_reg, 816 817 z_mode_ax_reg, 818 indir_dx_reg 819 }; 820 821 enum 822 { 823 FLOATCODE = 1, 824 USE_REG_TABLE, 825 USE_MOD_TABLE, 826 USE_RM_TABLE, 827 USE_PREFIX_TABLE, 828 USE_X86_64_TABLE, 829 USE_X86_64_EVEX_FROM_VEX_TABLE, 830 USE_X86_64_EVEX_PFX_TABLE, 831 USE_X86_64_EVEX_W_TABLE, 832 USE_X86_64_EVEX_MEM_W_TABLE, 833 USE_3BYTE_TABLE, 834 USE_XOP_8F_TABLE, 835 USE_VEX_C4_TABLE, 836 USE_VEX_C5_TABLE, 837 USE_VEX_LEN_TABLE, 838 USE_VEX_W_TABLE, 839 USE_EVEX_TABLE, 840 USE_EVEX_LEN_TABLE 841 }; 842 843 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 844 845 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 846 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 847 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 848 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 849 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 850 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 851 #define X86_64_EVEX_FROM_VEX_TABLE(I) \ 852 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) 853 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I)) 854 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I)) 855 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I)) 856 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 857 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) 858 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) 859 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0) 860 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 861 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) 862 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0) 863 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) 864 865 enum 866 { 867 REG_80 = 0, 868 REG_81, 869 REG_83, 870 REG_8F, 871 REG_C0, 872 REG_C1, 873 REG_C6, 874 REG_C7, 875 REG_D0, 876 REG_D1, 877 REG_D2, 878 REG_D3, 879 REG_F6, 880 REG_F7, 881 REG_FE, 882 REG_FF, 883 REG_0F00, 884 REG_0F01, 885 REG_0F0D, 886 REG_0F18, 887 REG_0F1C_P_0_MOD_0, 888 REG_0F1E_P_1_MOD_3, 889 REG_0F38D8_PREFIX_1, 890 REG_0F3A0F_P_1, 891 REG_0F71, 892 REG_0F72, 893 REG_0F73, 894 REG_0FA6, 895 REG_0FA7, 896 REG_0FAE, 897 REG_0FBA, 898 REG_0FC7, 899 REG_VEX_0F71, 900 REG_VEX_0F72, 901 REG_VEX_0F73, 902 REG_VEX_0FAE, 903 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, 904 REG_VEX_0F38F3_L_0_P_0, 905 REG_VEX_MAP7_F6_L_0_W_0, 906 REG_VEX_MAP7_F8_L_0_W_0, 907 908 REG_XOP_09_01_L_0, 909 REG_XOP_09_02_L_0, 910 REG_XOP_09_12_L_0, 911 REG_XOP_0A_12_L_0, 912 913 REG_EVEX_0F71, 914 REG_EVEX_0F72, 915 REG_EVEX_0F73, 916 REG_EVEX_0F38C6_L_2, 917 REG_EVEX_0F38C7_L_2, 918 REG_EVEX_MAP4_80, 919 REG_EVEX_MAP4_81, 920 REG_EVEX_MAP4_83, 921 REG_EVEX_MAP4_8F, 922 REG_EVEX_MAP4_F6, 923 REG_EVEX_MAP4_F7, 924 REG_EVEX_MAP4_FE, 925 REG_EVEX_MAP4_FF, 926 }; 927 928 enum 929 { 930 MOD_62_32BIT = 0, 931 MOD_C4_32BIT, 932 MOD_C5_32BIT, 933 MOD_0F01_REG_0, 934 MOD_0F01_REG_1, 935 MOD_0F01_REG_2, 936 MOD_0F01_REG_3, 937 MOD_0F01_REG_5, 938 MOD_0F01_REG_7, 939 MOD_0F12_PREFIX_0, 940 MOD_0F16_PREFIX_0, 941 MOD_0F18_REG_0, 942 MOD_0F18_REG_1, 943 MOD_0F18_REG_2, 944 MOD_0F18_REG_3, 945 MOD_0F18_REG_4, 946 MOD_0F18_REG_6, 947 MOD_0F18_REG_7, 948 MOD_0F1A_PREFIX_0, 949 MOD_0F1B_PREFIX_0, 950 MOD_0F1B_PREFIX_1, 951 MOD_0F1C_PREFIX_0, 952 MOD_0F1E_PREFIX_1, 953 MOD_0FAE_REG_0, 954 MOD_0FAE_REG_1, 955 MOD_0FAE_REG_2, 956 MOD_0FAE_REG_3, 957 MOD_0FAE_REG_4, 958 MOD_0FAE_REG_5, 959 MOD_0FAE_REG_6, 960 MOD_0FAE_REG_7, 961 MOD_0FC7_REG_6, 962 MOD_0FC7_REG_7, 963 MOD_0F38DC_PREFIX_1, 964 MOD_0F38F8, 965 966 MOD_VEX_0F3849_X86_64_L_0_W_0, 967 968 MOD_EVEX_MAP4_60, 969 MOD_EVEX_MAP4_61, 970 MOD_EVEX_MAP4_F8_P_1, 971 MOD_EVEX_MAP4_F8_P_3, 972 }; 973 974 enum 975 { 976 RM_C6_REG_7 = 0, 977 RM_C7_REG_7, 978 RM_0F01_REG_0, 979 RM_0F01_REG_1, 980 RM_0F01_REG_2, 981 RM_0F01_REG_3, 982 RM_0F01_REG_5_MOD_3, 983 RM_0F01_REG_7_MOD_3, 984 RM_0F1E_P_1_MOD_3_REG_7, 985 RM_0FAE_REG_6_MOD_3_P_0, 986 RM_0FAE_REG_7_MOD_3, 987 RM_0F3A0F_P_1_R_0, 988 989 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0, 990 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3, 991 }; 992 993 enum 994 { 995 PREFIX_90 = 0, 996 PREFIX_0F00_REG_6_X86_64, 997 PREFIX_0F01_REG_0_MOD_3_RM_6, 998 PREFIX_0F01_REG_0_MOD_3_RM_7, 999 PREFIX_0F01_REG_1_RM_2, 1000 PREFIX_0F01_REG_1_RM_4, 1001 PREFIX_0F01_REG_1_RM_5, 1002 PREFIX_0F01_REG_1_RM_6, 1003 PREFIX_0F01_REG_1_RM_7, 1004 PREFIX_0F01_REG_3_RM_1, 1005 PREFIX_0F01_REG_5_MOD_0, 1006 PREFIX_0F01_REG_5_MOD_3_RM_0, 1007 PREFIX_0F01_REG_5_MOD_3_RM_1, 1008 PREFIX_0F01_REG_5_MOD_3_RM_2, 1009 PREFIX_0F01_REG_5_MOD_3_RM_4, 1010 PREFIX_0F01_REG_5_MOD_3_RM_5, 1011 PREFIX_0F01_REG_5_MOD_3_RM_6, 1012 PREFIX_0F01_REG_5_MOD_3_RM_7, 1013 PREFIX_0F01_REG_7_MOD_3_RM_2, 1014 PREFIX_0F01_REG_7_MOD_3_RM_5, 1015 PREFIX_0F01_REG_7_MOD_3_RM_6, 1016 PREFIX_0F01_REG_7_MOD_3_RM_7, 1017 PREFIX_0F09, 1018 PREFIX_0F10, 1019 PREFIX_0F11, 1020 PREFIX_0F12, 1021 PREFIX_0F16, 1022 PREFIX_0F18_REG_6_MOD_0_X86_64, 1023 PREFIX_0F18_REG_7_MOD_0_X86_64, 1024 PREFIX_0F1A, 1025 PREFIX_0F1B, 1026 PREFIX_0F1C, 1027 PREFIX_0F1E, 1028 PREFIX_0F2A, 1029 PREFIX_0F2B, 1030 PREFIX_0F2C, 1031 PREFIX_0F2D, 1032 PREFIX_0F2E, 1033 PREFIX_0F2F, 1034 PREFIX_0F51, 1035 PREFIX_0F52, 1036 PREFIX_0F53, 1037 PREFIX_0F58, 1038 PREFIX_0F59, 1039 PREFIX_0F5A, 1040 PREFIX_0F5B, 1041 PREFIX_0F5C, 1042 PREFIX_0F5D, 1043 PREFIX_0F5E, 1044 PREFIX_0F5F, 1045 PREFIX_0F60, 1046 PREFIX_0F61, 1047 PREFIX_0F62, 1048 PREFIX_0F6F, 1049 PREFIX_0F70, 1050 PREFIX_0F78, 1051 PREFIX_0F79, 1052 PREFIX_0F7C, 1053 PREFIX_0F7D, 1054 PREFIX_0F7E, 1055 PREFIX_0F7F, 1056 PREFIX_0FA6_REG_0, 1057 PREFIX_0FA6_REG_5, 1058 PREFIX_0FA7_REG_6, 1059 PREFIX_0FAE_REG_0_MOD_3, 1060 PREFIX_0FAE_REG_1_MOD_3, 1061 PREFIX_0FAE_REG_2_MOD_3, 1062 PREFIX_0FAE_REG_3_MOD_3, 1063 PREFIX_0FAE_REG_4_MOD_0, 1064 PREFIX_0FAE_REG_4_MOD_3, 1065 PREFIX_0FAE_REG_5_MOD_3, 1066 PREFIX_0FAE_REG_6_MOD_0, 1067 PREFIX_0FAE_REG_6_MOD_3, 1068 PREFIX_0FAE_REG_7_MOD_0, 1069 PREFIX_0FB8, 1070 PREFIX_0FBC, 1071 PREFIX_0FBD, 1072 PREFIX_0FC2, 1073 PREFIX_0FC7_REG_6_MOD_0, 1074 PREFIX_0FC7_REG_6_MOD_3, 1075 PREFIX_0FC7_REG_7_MOD_3, 1076 PREFIX_0FD0, 1077 PREFIX_0FD6, 1078 PREFIX_0FE6, 1079 PREFIX_0FE7, 1080 PREFIX_0FF0, 1081 PREFIX_0FF7, 1082 PREFIX_0F38D8, 1083 PREFIX_0F38DC, 1084 PREFIX_0F38DD, 1085 PREFIX_0F38DE, 1086 PREFIX_0F38DF, 1087 PREFIX_0F38F0, 1088 PREFIX_0F38F1, 1089 PREFIX_0F38F6, 1090 PREFIX_0F38F8_M_0, 1091 PREFIX_0F38F8_M_1_X86_64, 1092 PREFIX_0F38FA, 1093 PREFIX_0F38FB, 1094 PREFIX_0F38FC, 1095 PREFIX_0F3A0F, 1096 PREFIX_VEX_0F12, 1097 PREFIX_VEX_0F16, 1098 PREFIX_VEX_0F2A, 1099 PREFIX_VEX_0F2C, 1100 PREFIX_VEX_0F2D, 1101 PREFIX_VEX_0F41_L_1_W_0, 1102 PREFIX_VEX_0F41_L_1_W_1, 1103 PREFIX_VEX_0F42_L_1_W_0, 1104 PREFIX_VEX_0F42_L_1_W_1, 1105 PREFIX_VEX_0F44_L_0_W_0, 1106 PREFIX_VEX_0F44_L_0_W_1, 1107 PREFIX_VEX_0F45_L_1_W_0, 1108 PREFIX_VEX_0F45_L_1_W_1, 1109 PREFIX_VEX_0F46_L_1_W_0, 1110 PREFIX_VEX_0F46_L_1_W_1, 1111 PREFIX_VEX_0F47_L_1_W_0, 1112 PREFIX_VEX_0F47_L_1_W_1, 1113 PREFIX_VEX_0F4A_L_1_W_0, 1114 PREFIX_VEX_0F4A_L_1_W_1, 1115 PREFIX_VEX_0F4B_L_1_W_0, 1116 PREFIX_VEX_0F4B_L_1_W_1, 1117 PREFIX_VEX_0F6F, 1118 PREFIX_VEX_0F70, 1119 PREFIX_VEX_0F7E, 1120 PREFIX_VEX_0F7F, 1121 PREFIX_VEX_0F90_L_0_W_0, 1122 PREFIX_VEX_0F90_L_0_W_1, 1123 PREFIX_VEX_0F91_L_0_W_0, 1124 PREFIX_VEX_0F91_L_0_W_1, 1125 PREFIX_VEX_0F92_L_0_W_0, 1126 PREFIX_VEX_0F92_L_0_W_1, 1127 PREFIX_VEX_0F93_L_0_W_0, 1128 PREFIX_VEX_0F93_L_0_W_1, 1129 PREFIX_VEX_0F98_L_0_W_0, 1130 PREFIX_VEX_0F98_L_0_W_1, 1131 PREFIX_VEX_0F99_L_0_W_0, 1132 PREFIX_VEX_0F99_L_0_W_1, 1133 PREFIX_VEX_0F3848_X86_64_L_0_W_0, 1134 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0, 1135 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1, 1136 PREFIX_VEX_0F384A_X86_64_W_0_L_0, 1137 PREFIX_VEX_0F384B_X86_64_L_0_W_0, 1138 PREFIX_VEX_0F3850_W_0, 1139 PREFIX_VEX_0F3851_W_0, 1140 PREFIX_VEX_0F385C_X86_64_L_0_W_0, 1141 PREFIX_VEX_0F385E_X86_64_L_0_W_0, 1142 PREFIX_VEX_0F385F_X86_64_L_0_W_0, 1143 PREFIX_VEX_0F386B_X86_64_L_0_W_0, 1144 PREFIX_VEX_0F386C_X86_64_L_0_W_0, 1145 PREFIX_VEX_0F386E_X86_64_L_0_W_0, 1146 PREFIX_VEX_0F386F_X86_64_L_0_W_0, 1147 PREFIX_VEX_0F3872, 1148 PREFIX_VEX_0F38B0_W_0, 1149 PREFIX_VEX_0F38B1_W_0, 1150 PREFIX_VEX_0F38D2_W_0, 1151 PREFIX_VEX_0F38D3_W_0, 1152 PREFIX_VEX_0F38CB, 1153 PREFIX_VEX_0F38CC, 1154 PREFIX_VEX_0F38CD, 1155 PREFIX_VEX_0F38DA_W_0, 1156 PREFIX_VEX_0F38F2_L_0, 1157 PREFIX_VEX_0F38F3_L_0, 1158 PREFIX_VEX_0F38F5_L_0, 1159 PREFIX_VEX_0F38F6_L_0, 1160 PREFIX_VEX_0F38F7_L_0, 1161 PREFIX_VEX_0F3AF0_L_0, 1162 PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0, 1163 PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0, 1164 PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0, 1165 PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, 1166 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64, 1167 1168 PREFIX_EVEX_0F2E, 1169 PREFIX_EVEX_0F2F, 1170 PREFIX_EVEX_0F5B, 1171 PREFIX_EVEX_0F6F, 1172 PREFIX_EVEX_0F70, 1173 PREFIX_EVEX_0F78, 1174 PREFIX_EVEX_0F79, 1175 PREFIX_EVEX_0F7A, 1176 PREFIX_EVEX_0F7B, 1177 PREFIX_EVEX_0F7E, 1178 PREFIX_EVEX_0F7F, 1179 PREFIX_EVEX_0FC2, 1180 PREFIX_EVEX_0FE6, 1181 PREFIX_EVEX_0F3810, 1182 PREFIX_EVEX_0F3811, 1183 PREFIX_EVEX_0F3812, 1184 PREFIX_EVEX_0F3813, 1185 PREFIX_EVEX_0F3814, 1186 PREFIX_EVEX_0F3815, 1187 PREFIX_EVEX_0F3820, 1188 PREFIX_EVEX_0F3821, 1189 PREFIX_EVEX_0F3822, 1190 PREFIX_EVEX_0F3823, 1191 PREFIX_EVEX_0F3824, 1192 PREFIX_EVEX_0F3825, 1193 PREFIX_EVEX_0F3826, 1194 PREFIX_EVEX_0F3827, 1195 PREFIX_EVEX_0F3828, 1196 PREFIX_EVEX_0F3829, 1197 PREFIX_EVEX_0F382A, 1198 PREFIX_EVEX_0F3830, 1199 PREFIX_EVEX_0F3831, 1200 PREFIX_EVEX_0F3832, 1201 PREFIX_EVEX_0F3833, 1202 PREFIX_EVEX_0F3834, 1203 PREFIX_EVEX_0F3835, 1204 PREFIX_EVEX_0F3838, 1205 PREFIX_EVEX_0F3839, 1206 PREFIX_EVEX_0F383A, 1207 PREFIX_EVEX_0F384A_X86_64_W_0_L_2, 1208 PREFIX_EVEX_0F3852, 1209 PREFIX_EVEX_0F3853, 1210 PREFIX_EVEX_0F3868, 1211 PREFIX_EVEX_0F386D_X86_64_W_0_L_2, 1212 PREFIX_EVEX_0F3872, 1213 PREFIX_EVEX_0F3874, 1214 PREFIX_EVEX_0F389A, 1215 PREFIX_EVEX_0F389B, 1216 PREFIX_EVEX_0F38AA, 1217 PREFIX_EVEX_0F38AB, 1218 1219 PREFIX_EVEX_0F3A07_X86_64_W_0_L_2, 1220 PREFIX_EVEX_0F3A08, 1221 PREFIX_EVEX_0F3A0A, 1222 PREFIX_EVEX_0F3A26, 1223 PREFIX_EVEX_0F3A27, 1224 PREFIX_EVEX_0F3A42_W_0, 1225 PREFIX_EVEX_0F3A52, 1226 PREFIX_EVEX_0F3A53, 1227 PREFIX_EVEX_0F3A56, 1228 PREFIX_EVEX_0F3A57, 1229 PREFIX_EVEX_0F3A66, 1230 PREFIX_EVEX_0F3A67, 1231 PREFIX_EVEX_0F3A77_X86_64_W_0_L_2, 1232 PREFIX_EVEX_0F3AC2, 1233 1234 PREFIX_EVEX_MAP4_4x, 1235 PREFIX_EVEX_MAP4_F0, 1236 PREFIX_EVEX_MAP4_F1, 1237 PREFIX_EVEX_MAP4_F2, 1238 PREFIX_EVEX_MAP4_F8, 1239 1240 PREFIX_EVEX_MAP5_10, 1241 PREFIX_EVEX_MAP5_11, 1242 PREFIX_EVEX_MAP5_18, 1243 PREFIX_EVEX_MAP5_1B, 1244 PREFIX_EVEX_MAP5_1D, 1245 PREFIX_EVEX_MAP5_1E, 1246 PREFIX_EVEX_MAP5_2A, 1247 PREFIX_EVEX_MAP5_2C, 1248 PREFIX_EVEX_MAP5_2D, 1249 PREFIX_EVEX_MAP5_2E, 1250 PREFIX_EVEX_MAP5_2F, 1251 PREFIX_EVEX_MAP5_51, 1252 PREFIX_EVEX_MAP5_58, 1253 PREFIX_EVEX_MAP5_59, 1254 PREFIX_EVEX_MAP5_5A, 1255 PREFIX_EVEX_MAP5_5B, 1256 PREFIX_EVEX_MAP5_5C, 1257 PREFIX_EVEX_MAP5_5D, 1258 PREFIX_EVEX_MAP5_5E, 1259 PREFIX_EVEX_MAP5_5F, 1260 PREFIX_EVEX_MAP5_68, 1261 PREFIX_EVEX_MAP5_69, 1262 PREFIX_EVEX_MAP5_6A, 1263 PREFIX_EVEX_MAP5_6B, 1264 PREFIX_EVEX_MAP5_6C, 1265 PREFIX_EVEX_MAP5_6D, 1266 PREFIX_EVEX_MAP5_6E_L_0, 1267 PREFIX_EVEX_MAP5_6F_X86_64, 1268 PREFIX_EVEX_MAP5_74, 1269 PREFIX_EVEX_MAP5_78, 1270 PREFIX_EVEX_MAP5_79, 1271 PREFIX_EVEX_MAP5_7A, 1272 PREFIX_EVEX_MAP5_7B, 1273 PREFIX_EVEX_MAP5_7C, 1274 PREFIX_EVEX_MAP5_7D, 1275 PREFIX_EVEX_MAP5_7E_L_0, 1276 1277 PREFIX_EVEX_MAP6_13, 1278 PREFIX_EVEX_MAP6_2C, 1279 PREFIX_EVEX_MAP6_42, 1280 PREFIX_EVEX_MAP6_4C, 1281 PREFIX_EVEX_MAP6_4E, 1282 PREFIX_EVEX_MAP6_56, 1283 PREFIX_EVEX_MAP6_57, 1284 PREFIX_EVEX_MAP6_98, 1285 PREFIX_EVEX_MAP6_9A, 1286 PREFIX_EVEX_MAP6_9C, 1287 PREFIX_EVEX_MAP6_9E, 1288 PREFIX_EVEX_MAP6_A8, 1289 PREFIX_EVEX_MAP6_AA, 1290 PREFIX_EVEX_MAP6_AC, 1291 PREFIX_EVEX_MAP6_AE, 1292 PREFIX_EVEX_MAP6_B8, 1293 PREFIX_EVEX_MAP6_BA, 1294 PREFIX_EVEX_MAP6_BC, 1295 PREFIX_EVEX_MAP6_BE, 1296 PREFIX_EVEX_MAP6_D6, 1297 PREFIX_EVEX_MAP6_D7, 1298 }; 1299 1300 enum 1301 { 1302 X86_64_06 = 0, 1303 X86_64_07, 1304 X86_64_0E, 1305 X86_64_16, 1306 X86_64_17, 1307 X86_64_1E, 1308 X86_64_1F, 1309 X86_64_27, 1310 X86_64_2F, 1311 X86_64_37, 1312 X86_64_3F, 1313 X86_64_60, 1314 X86_64_61, 1315 X86_64_62, 1316 X86_64_63, 1317 X86_64_6D, 1318 X86_64_6F, 1319 X86_64_82, 1320 X86_64_9A, 1321 X86_64_C2, 1322 X86_64_C3, 1323 X86_64_C4, 1324 X86_64_C5, 1325 X86_64_CE, 1326 X86_64_D4, 1327 X86_64_D5, 1328 X86_64_D6, 1329 X86_64_E8, 1330 X86_64_E9, 1331 X86_64_EA, 1332 X86_64_0F00_REG_6, 1333 X86_64_0F01_REG_0, 1334 X86_64_0F01_REG_0_MOD_3_RM_6_P_1, 1335 X86_64_0F01_REG_0_MOD_3_RM_6_P_3, 1336 X86_64_0F01_REG_0_MOD_3_RM_7_P_0, 1337 X86_64_0F01_REG_1, 1338 X86_64_0F01_REG_1_RM_2_PREFIX_1, 1339 X86_64_0F01_REG_1_RM_2_PREFIX_3, 1340 X86_64_0F01_REG_1_RM_5_PREFIX_2, 1341 X86_64_0F01_REG_1_RM_6_PREFIX_2, 1342 X86_64_0F01_REG_1_RM_7_PREFIX_2, 1343 X86_64_0F01_REG_2, 1344 X86_64_0F01_REG_3, 1345 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, 1346 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, 1347 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, 1348 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, 1349 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1, 1350 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3, 1351 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, 1352 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, 1353 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, 1354 X86_64_0F18_REG_6_MOD_0, 1355 X86_64_0F18_REG_7_MOD_0, 1356 X86_64_0F24, 1357 X86_64_0F26, 1358 X86_64_0F388A, 1359 X86_64_0F388B, 1360 X86_64_0F38F8_M_1, 1361 X86_64_0FC7_REG_6_MOD_3_PREFIX_1, 1362 1363 X86_64_VEX_0F3848, 1364 X86_64_VEX_0F3849, 1365 X86_64_VEX_0F384A, 1366 X86_64_VEX_0F384B, 1367 X86_64_VEX_0F385C, 1368 X86_64_VEX_0F385E, 1369 X86_64_VEX_0F385F, 1370 X86_64_VEX_0F386B, 1371 X86_64_VEX_0F386C, 1372 X86_64_VEX_0F386E, 1373 X86_64_VEX_0F386F, 1374 X86_64_VEX_0F38Ex, 1375 1376 X86_64_VEX_MAP5_F8, 1377 X86_64_VEX_MAP5_F9, 1378 X86_64_VEX_MAP5_FD, 1379 X86_64_VEX_MAP7_F6_L_0_W_0_R_0, 1380 X86_64_VEX_MAP7_F8_L_0_W_0_R_0, 1381 1382 X86_64_EVEX_0F384A, 1383 X86_64_EVEX_0F386D, 1384 X86_64_EVEX_0F3A07, 1385 X86_64_EVEX_0F3A77, 1386 1387 X86_64_EVEX_MAP5_6F, 1388 }; 1389 1390 enum 1391 { 1392 THREE_BYTE_0F38 = 0, 1393 THREE_BYTE_0F3A 1394 }; 1395 1396 enum 1397 { 1398 XOP_08 = 0, 1399 XOP_09, 1400 XOP_0A 1401 }; 1402 1403 enum 1404 { 1405 VEX_0F = 0, 1406 VEX_0F38, 1407 VEX_0F3A, 1408 VEX_MAP5, 1409 VEX_MAP7, 1410 }; 1411 1412 enum 1413 { 1414 EVEX_0F = 0, 1415 EVEX_0F38, 1416 EVEX_0F3A, 1417 EVEX_MAP4, 1418 EVEX_MAP5, 1419 EVEX_MAP6, 1420 EVEX_MAP7, 1421 }; 1422 1423 enum 1424 { 1425 VEX_LEN_0F12_P_0 = 0, 1426 VEX_LEN_0F12_P_2, 1427 VEX_LEN_0F13, 1428 VEX_LEN_0F16_P_0, 1429 VEX_LEN_0F16_P_2, 1430 VEX_LEN_0F17, 1431 VEX_LEN_0F41, 1432 VEX_LEN_0F42, 1433 VEX_LEN_0F44, 1434 VEX_LEN_0F45, 1435 VEX_LEN_0F46, 1436 VEX_LEN_0F47, 1437 VEX_LEN_0F4A, 1438 VEX_LEN_0F4B, 1439 VEX_LEN_0F6E, 1440 VEX_LEN_0F77, 1441 VEX_LEN_0F7E_P_1, 1442 VEX_LEN_0F7E_P_2, 1443 VEX_LEN_0F90, 1444 VEX_LEN_0F91, 1445 VEX_LEN_0F92, 1446 VEX_LEN_0F93, 1447 VEX_LEN_0F98, 1448 VEX_LEN_0F99, 1449 VEX_LEN_0FAE_R_2, 1450 VEX_LEN_0FAE_R_3, 1451 VEX_LEN_0FC4, 1452 VEX_LEN_0FD6, 1453 VEX_LEN_0F3816, 1454 VEX_LEN_0F3819, 1455 VEX_LEN_0F381A, 1456 VEX_LEN_0F3836, 1457 VEX_LEN_0F3841, 1458 VEX_LEN_0F3848_X86_64, 1459 VEX_LEN_0F3849_X86_64, 1460 VEX_LEN_0F384A_X86_64_W_0, 1461 VEX_LEN_0F384B_X86_64, 1462 VEX_LEN_0F385A, 1463 VEX_LEN_0F385C_X86_64, 1464 VEX_LEN_0F385E_X86_64, 1465 VEX_LEN_0F385F_X86_64, 1466 VEX_LEN_0F386B_X86_64, 1467 VEX_LEN_0F386C_X86_64, 1468 VEX_LEN_0F386E_X86_64, 1469 VEX_LEN_0F386F_X86_64, 1470 VEX_LEN_0F38CB_P_3_W_0, 1471 VEX_LEN_0F38CC_P_3_W_0, 1472 VEX_LEN_0F38CD_P_3_W_0, 1473 VEX_LEN_0F38DA_W_0_P_0, 1474 VEX_LEN_0F38DA_W_0_P_2, 1475 VEX_LEN_0F38DB, 1476 VEX_LEN_0F38F2, 1477 VEX_LEN_0F38F3, 1478 VEX_LEN_0F38F5, 1479 VEX_LEN_0F38F6, 1480 VEX_LEN_0F38F7, 1481 VEX_LEN_0F3A00, 1482 VEX_LEN_0F3A01, 1483 VEX_LEN_0F3A06, 1484 VEX_LEN_0F3A14, 1485 VEX_LEN_0F3A15, 1486 VEX_LEN_0F3A16, 1487 VEX_LEN_0F3A17, 1488 VEX_LEN_0F3A18, 1489 VEX_LEN_0F3A19, 1490 VEX_LEN_0F3A20, 1491 VEX_LEN_0F3A21, 1492 VEX_LEN_0F3A22, 1493 VEX_LEN_0F3A30, 1494 VEX_LEN_0F3A31, 1495 VEX_LEN_0F3A32, 1496 VEX_LEN_0F3A33, 1497 VEX_LEN_0F3A38, 1498 VEX_LEN_0F3A39, 1499 VEX_LEN_0F3A41, 1500 VEX_LEN_0F3A46, 1501 VEX_LEN_0F3A60, 1502 VEX_LEN_0F3A61, 1503 VEX_LEN_0F3A62, 1504 VEX_LEN_0F3A63, 1505 VEX_LEN_0F3ADE_W_0, 1506 VEX_LEN_0F3ADF, 1507 VEX_LEN_0F3AF0, 1508 VEX_LEN_MAP5_F8_X86_64, 1509 VEX_LEN_MAP5_F9_X86_64, 1510 VEX_LEN_MAP5_FD_X86_64, 1511 VEX_LEN_MAP7_F6, 1512 VEX_LEN_MAP7_F8, 1513 VEX_LEN_XOP_08_85, 1514 VEX_LEN_XOP_08_86, 1515 VEX_LEN_XOP_08_87, 1516 VEX_LEN_XOP_08_8E, 1517 VEX_LEN_XOP_08_8F, 1518 VEX_LEN_XOP_08_95, 1519 VEX_LEN_XOP_08_96, 1520 VEX_LEN_XOP_08_97, 1521 VEX_LEN_XOP_08_9E, 1522 VEX_LEN_XOP_08_9F, 1523 VEX_LEN_XOP_08_A3, 1524 VEX_LEN_XOP_08_A6, 1525 VEX_LEN_XOP_08_B6, 1526 VEX_LEN_XOP_08_C0, 1527 VEX_LEN_XOP_08_C1, 1528 VEX_LEN_XOP_08_C2, 1529 VEX_LEN_XOP_08_C3, 1530 VEX_LEN_XOP_08_CC, 1531 VEX_LEN_XOP_08_CD, 1532 VEX_LEN_XOP_08_CE, 1533 VEX_LEN_XOP_08_CF, 1534 VEX_LEN_XOP_08_EC, 1535 VEX_LEN_XOP_08_ED, 1536 VEX_LEN_XOP_08_EE, 1537 VEX_LEN_XOP_08_EF, 1538 VEX_LEN_XOP_09_01, 1539 VEX_LEN_XOP_09_02, 1540 VEX_LEN_XOP_09_12, 1541 VEX_LEN_XOP_09_82_W_0, 1542 VEX_LEN_XOP_09_83_W_0, 1543 VEX_LEN_XOP_09_90, 1544 VEX_LEN_XOP_09_91, 1545 VEX_LEN_XOP_09_92, 1546 VEX_LEN_XOP_09_93, 1547 VEX_LEN_XOP_09_94, 1548 VEX_LEN_XOP_09_95, 1549 VEX_LEN_XOP_09_96, 1550 VEX_LEN_XOP_09_97, 1551 VEX_LEN_XOP_09_98, 1552 VEX_LEN_XOP_09_99, 1553 VEX_LEN_XOP_09_9A, 1554 VEX_LEN_XOP_09_9B, 1555 VEX_LEN_XOP_09_C1, 1556 VEX_LEN_XOP_09_C2, 1557 VEX_LEN_XOP_09_C3, 1558 VEX_LEN_XOP_09_C6, 1559 VEX_LEN_XOP_09_C7, 1560 VEX_LEN_XOP_09_CB, 1561 VEX_LEN_XOP_09_D1, 1562 VEX_LEN_XOP_09_D2, 1563 VEX_LEN_XOP_09_D3, 1564 VEX_LEN_XOP_09_D6, 1565 VEX_LEN_XOP_09_D7, 1566 VEX_LEN_XOP_09_DB, 1567 VEX_LEN_XOP_09_E1, 1568 VEX_LEN_XOP_09_E2, 1569 VEX_LEN_XOP_09_E3, 1570 VEX_LEN_XOP_0A_12, 1571 }; 1572 1573 enum 1574 { 1575 EVEX_LEN_0F7E_P_1_W_0 = 0, 1576 EVEX_LEN_0FD6_P_2_W_0, 1577 EVEX_LEN_0F3816, 1578 EVEX_LEN_0F3819, 1579 EVEX_LEN_0F381A, 1580 EVEX_LEN_0F381B, 1581 EVEX_LEN_0F3836, 1582 EVEX_LEN_0F384A_X86_64_W_0, 1583 EVEX_LEN_0F385A, 1584 EVEX_LEN_0F385B, 1585 EVEX_LEN_0F386D_X86_64_W_0, 1586 EVEX_LEN_0F38C6, 1587 EVEX_LEN_0F38C7, 1588 EVEX_LEN_0F3A00, 1589 EVEX_LEN_0F3A01, 1590 EVEX_LEN_0F3A07_X86_64_W_0, 1591 EVEX_LEN_0F3A18, 1592 EVEX_LEN_0F3A19, 1593 EVEX_LEN_0F3A1A, 1594 EVEX_LEN_0F3A1B, 1595 EVEX_LEN_0F3A23, 1596 EVEX_LEN_0F3A38, 1597 EVEX_LEN_0F3A39, 1598 EVEX_LEN_0F3A3A, 1599 EVEX_LEN_0F3A3B, 1600 EVEX_LEN_0F3A43, 1601 EVEX_LEN_0F3A77_X86_64_W_0, 1602 1603 EVEX_LEN_MAP5_6E, 1604 EVEX_LEN_MAP5_7E, 1605 }; 1606 1607 enum 1608 { 1609 VEX_W_0F41_L_1 = 0, 1610 VEX_W_0F42_L_1, 1611 VEX_W_0F44_L_0, 1612 VEX_W_0F45_L_1, 1613 VEX_W_0F46_L_1, 1614 VEX_W_0F47_L_1, 1615 VEX_W_0F4A_L_1, 1616 VEX_W_0F4B_L_1, 1617 VEX_W_0F90_L_0, 1618 VEX_W_0F91_L_0, 1619 VEX_W_0F92_L_0, 1620 VEX_W_0F93_L_0, 1621 VEX_W_0F98_L_0, 1622 VEX_W_0F99_L_0, 1623 VEX_W_0F380C, 1624 VEX_W_0F380D, 1625 VEX_W_0F380E, 1626 VEX_W_0F380F, 1627 VEX_W_0F3813, 1628 VEX_W_0F3816_L_1, 1629 VEX_W_0F3818, 1630 VEX_W_0F3819_L_1, 1631 VEX_W_0F381A_L_1, 1632 VEX_W_0F382C, 1633 VEX_W_0F382D, 1634 VEX_W_0F382E, 1635 VEX_W_0F382F, 1636 VEX_W_0F3836, 1637 VEX_W_0F3846, 1638 VEX_W_0F3848_X86_64_L_0, 1639 VEX_W_0F3849_X86_64_L_0, 1640 VEX_W_0F384A_X86_64, 1641 VEX_W_0F384B_X86_64_L_0, 1642 VEX_W_0F3850, 1643 VEX_W_0F3851, 1644 VEX_W_0F3852, 1645 VEX_W_0F3853, 1646 VEX_W_0F3858, 1647 VEX_W_0F3859, 1648 VEX_W_0F385A_L_0, 1649 VEX_W_0F385C_X86_64_L_0, 1650 VEX_W_0F385E_X86_64_L_0, 1651 VEX_W_0F385F_X86_64_L_0, 1652 VEX_W_0F386B_X86_64_L_0, 1653 VEX_W_0F386C_X86_64_L_0, 1654 VEX_W_0F386E_X86_64_L_0, 1655 VEX_W_0F386F_X86_64_L_0, 1656 VEX_W_0F3872_P_1, 1657 VEX_W_0F3878, 1658 VEX_W_0F3879, 1659 VEX_W_0F38B0, 1660 VEX_W_0F38B1, 1661 VEX_W_0F38B4, 1662 VEX_W_0F38B5, 1663 VEX_W_0F38CB_P_3, 1664 VEX_W_0F38CC_P_3, 1665 VEX_W_0F38CD_P_3, 1666 VEX_W_0F38CF, 1667 VEX_W_0F38D2, 1668 VEX_W_0F38D3, 1669 VEX_W_0F38DA, 1670 VEX_W_0F3A00_L_1, 1671 VEX_W_0F3A01_L_1, 1672 VEX_W_0F3A02, 1673 VEX_W_0F3A04, 1674 VEX_W_0F3A05, 1675 VEX_W_0F3A06_L_1, 1676 VEX_W_0F3A18_L_1, 1677 VEX_W_0F3A19_L_1, 1678 VEX_W_0F3A1D, 1679 VEX_W_0F3A38_L_1, 1680 VEX_W_0F3A39_L_1, 1681 VEX_W_0F3A46_L_1, 1682 VEX_W_0F3A4A, 1683 VEX_W_0F3A4B, 1684 VEX_W_0F3A4C, 1685 VEX_W_0F3ACE, 1686 VEX_W_0F3ACF, 1687 VEX_W_0F3ADE, 1688 VEX_W_MAP5_F8_X86_64_L_0, 1689 VEX_W_MAP5_F9_X86_64_L_0, 1690 VEX_W_MAP5_FD_X86_64_L_0, 1691 VEX_W_MAP7_F6_L_0, 1692 VEX_W_MAP7_F8_L_0, 1693 1694 VEX_W_XOP_08_85_L_0, 1695 VEX_W_XOP_08_86_L_0, 1696 VEX_W_XOP_08_87_L_0, 1697 VEX_W_XOP_08_8E_L_0, 1698 VEX_W_XOP_08_8F_L_0, 1699 VEX_W_XOP_08_95_L_0, 1700 VEX_W_XOP_08_96_L_0, 1701 VEX_W_XOP_08_97_L_0, 1702 VEX_W_XOP_08_9E_L_0, 1703 VEX_W_XOP_08_9F_L_0, 1704 VEX_W_XOP_08_A6_L_0, 1705 VEX_W_XOP_08_B6_L_0, 1706 VEX_W_XOP_08_C0_L_0, 1707 VEX_W_XOP_08_C1_L_0, 1708 VEX_W_XOP_08_C2_L_0, 1709 VEX_W_XOP_08_C3_L_0, 1710 VEX_W_XOP_08_CC_L_0, 1711 VEX_W_XOP_08_CD_L_0, 1712 VEX_W_XOP_08_CE_L_0, 1713 VEX_W_XOP_08_CF_L_0, 1714 VEX_W_XOP_08_EC_L_0, 1715 VEX_W_XOP_08_ED_L_0, 1716 VEX_W_XOP_08_EE_L_0, 1717 VEX_W_XOP_08_EF_L_0, 1718 1719 VEX_W_XOP_09_80, 1720 VEX_W_XOP_09_81, 1721 VEX_W_XOP_09_82, 1722 VEX_W_XOP_09_83, 1723 VEX_W_XOP_09_C1_L_0, 1724 VEX_W_XOP_09_C2_L_0, 1725 VEX_W_XOP_09_C3_L_0, 1726 VEX_W_XOP_09_C6_L_0, 1727 VEX_W_XOP_09_C7_L_0, 1728 VEX_W_XOP_09_CB_L_0, 1729 VEX_W_XOP_09_D1_L_0, 1730 VEX_W_XOP_09_D2_L_0, 1731 VEX_W_XOP_09_D3_L_0, 1732 VEX_W_XOP_09_D6_L_0, 1733 VEX_W_XOP_09_D7_L_0, 1734 VEX_W_XOP_09_DB_L_0, 1735 VEX_W_XOP_09_E1_L_0, 1736 VEX_W_XOP_09_E2_L_0, 1737 VEX_W_XOP_09_E3_L_0, 1738 1739 EVEX_W_0F5B_P_0, 1740 EVEX_W_0F62, 1741 EVEX_W_0F66, 1742 EVEX_W_0F6A, 1743 EVEX_W_0F6B, 1744 EVEX_W_0F6C, 1745 EVEX_W_0F6D, 1746 EVEX_W_0F6F_P_1, 1747 EVEX_W_0F6F_P_2, 1748 EVEX_W_0F6F_P_3, 1749 EVEX_W_0F70_P_2, 1750 EVEX_W_0F72_R_2, 1751 EVEX_W_0F72_R_4, 1752 EVEX_W_0F72_R_6, 1753 EVEX_W_0F73_R_2, 1754 EVEX_W_0F73_R_6, 1755 EVEX_W_0F76, 1756 EVEX_W_0F78_P_0, 1757 EVEX_W_0F78_P_2, 1758 EVEX_W_0F79_P_0, 1759 EVEX_W_0F79_P_2, 1760 EVEX_W_0F7A_P_1, 1761 EVEX_W_0F7A_P_2, 1762 EVEX_W_0F7A_P_3, 1763 EVEX_W_0F7B_P_2, 1764 EVEX_W_0F7E_P_1, 1765 EVEX_W_0F7F_P_1, 1766 EVEX_W_0F7F_P_2, 1767 EVEX_W_0F7F_P_3, 1768 EVEX_W_0FD2, 1769 EVEX_W_0FD3, 1770 EVEX_W_0FD4, 1771 EVEX_W_0FD6, 1772 EVEX_W_0FE2, 1773 EVEX_W_0FE6_P_1, 1774 EVEX_W_0FE7, 1775 EVEX_W_0FF2, 1776 EVEX_W_0FF3, 1777 EVEX_W_0FF4, 1778 EVEX_W_0FFA, 1779 EVEX_W_0FFB, 1780 EVEX_W_0FFE, 1781 1782 EVEX_W_0F3810_P_1, 1783 EVEX_W_0F3810_P_2, 1784 EVEX_W_0F3811_P_1, 1785 EVEX_W_0F3811_P_2, 1786 EVEX_W_0F3812_P_1, 1787 EVEX_W_0F3812_P_2, 1788 EVEX_W_0F3813_P_1, 1789 EVEX_W_0F3814_P_1, 1790 EVEX_W_0F3815_P_1, 1791 EVEX_W_0F3819_L_n, 1792 EVEX_W_0F381A_L_n, 1793 EVEX_W_0F381B_L_2, 1794 EVEX_W_0F381E, 1795 EVEX_W_0F381F, 1796 EVEX_W_0F3820_P_1, 1797 EVEX_W_0F3821_P_1, 1798 EVEX_W_0F3822_P_1, 1799 EVEX_W_0F3823_P_1, 1800 EVEX_W_0F3824_P_1, 1801 EVEX_W_0F3825_P_1, 1802 EVEX_W_0F3825_P_2, 1803 EVEX_W_0F3828_P_2, 1804 EVEX_W_0F3829_P_2, 1805 EVEX_W_0F382A_P_1, 1806 EVEX_W_0F382A_P_2, 1807 EVEX_W_0F382B, 1808 EVEX_W_0F3830_P_1, 1809 EVEX_W_0F3831_P_1, 1810 EVEX_W_0F3832_P_1, 1811 EVEX_W_0F3833_P_1, 1812 EVEX_W_0F3834_P_1, 1813 EVEX_W_0F3835_P_1, 1814 EVEX_W_0F3835_P_2, 1815 EVEX_W_0F3837, 1816 EVEX_W_0F383A_P_1, 1817 EVEX_W_0F384A_X86_64, 1818 EVEX_W_0F3859, 1819 EVEX_W_0F385A_L_n, 1820 EVEX_W_0F385B_L_2, 1821 EVEX_W_0F386D_X86_64, 1822 EVEX_W_0F3870, 1823 EVEX_W_0F3872_P_2, 1824 EVEX_W_0F387A, 1825 EVEX_W_0F387B, 1826 EVEX_W_0F3883, 1827 1828 EVEX_W_0F3A07_X86_64, 1829 EVEX_W_0F3A18_L_n, 1830 EVEX_W_0F3A19_L_n, 1831 EVEX_W_0F3A1A_L_2, 1832 EVEX_W_0F3A1B_L_2, 1833 EVEX_W_0F3A21, 1834 EVEX_W_0F3A23_L_n, 1835 EVEX_W_0F3A38_L_n, 1836 EVEX_W_0F3A39_L_n, 1837 EVEX_W_0F3A3A_L_2, 1838 EVEX_W_0F3A3B_L_2, 1839 EVEX_W_0F3A42, 1840 EVEX_W_0F3A43_L_n, 1841 EVEX_W_0F3A70, 1842 EVEX_W_0F3A72, 1843 EVEX_W_0F3A77_X86_64, 1844 1845 EVEX_W_MAP4_8F_R_0, 1846 EVEX_W_MAP4_F8_P1_M_1, 1847 EVEX_W_MAP4_F8_P3_M_1, 1848 EVEX_W_MAP4_FF_R_6, 1849 1850 EVEX_W_MAP5_5B_P_0, 1851 EVEX_W_MAP5_6C_P_0, 1852 EVEX_W_MAP5_6C_P_2, 1853 EVEX_W_MAP5_6D_P_0, 1854 EVEX_W_MAP5_6D_P_2, 1855 EVEX_W_MAP5_6E_P_1, 1856 EVEX_W_MAP5_7A_P_3, 1857 EVEX_W_MAP5_7E_P_1, 1858 }; 1859 1860 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag); 1861 1862 struct dis386 { 1863 const char *name; 1864 struct 1865 { 1866 op_rtn rtn; 1867 int bytemode; 1868 } op[MAX_OPERANDS]; 1869 unsigned int prefix_requirement; 1870 }; 1871 1872 /* Upper case letters in the instruction names here are macros. 1873 'A' => print 'b' if no (suitable) register operand or suffix_always is true 1874 'B' => print 'b' if suffix_always is true 1875 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 1876 size prefix 1877 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 1878 suffix_always is true 1879 'E' => print 'e' if 32-bit form of jcxz 1880 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 1881 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 1882 'H' => print ",pt" or ",pn" branch hint 1883 'I' unused. 1884 'J' unused. 1885 'K' => print 'd' or 'q' if rex prefix is present. 1886 'L' => print 'l' or 'q' if suffix_always is true 1887 'M' => print 'r' if intel_mnemonic is false. 1888 'N' => print 'n' if instruction has no wait "prefix" 1889 'O' => print 'd' or 'o' (or 'q' in Intel mode) 1890 'P' => behave as 'T' except with register operand outside of suffix_always 1891 mode 1892 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or 1893 suffix_always is true 1894 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 1895 'S' => print 'w', 'l' or 'q' if suffix_always is true 1896 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size 1897 prefix or if suffix_always is true. 1898 'U' unused. 1899 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings. 1900 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 1901 'X' => print 's', 'd' depending on data16 prefix (for XMM) 1902 'Y' => no output, mark EVEX.aaa != 0 as bad. 1903 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. 1904 '!' => change condition from true to false or from false to true. 1905 '%' => add 1 upper case letter to the macro. 1906 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size 1907 prefix or suffix_always is true (lcall/ljmp). 1908 '@' => in 64bit mode for Intel64 ISA or if instruction 1909 has no operand sizing prefix, print 'q' if suffix_always is true or 1910 nothing otherwise; behave as 'P' in all other cases 1911 1912 2 upper case letter macros: 1913 "CC" => print condition code 1914 "XY" => print 'x' or 'y' if suffix_always is true or no register 1915 operands and no broadcast. 1916 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no 1917 register operands and no broadcast. 1918 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) 1919 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding 1920 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16) 1921 "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding 1922 (for BF16) 1923 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding 1924 "XV" => print "{vex} " pseudo prefix 1925 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is 1926 is used by an EVEX-encoded (AVX512VL) instruction. 1927 "ME" => Similar to "XE", but only print "{evex} " when there is no 1928 memory operand. 1929 "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} " 1930 pseudo prefix when instructions without NF, EGPR and VVVV, 1931 "NE" => don't print "{evex} " pseudo prefix for some special instructions 1932 in MAP4. 1933 "ZU" => print 'zu' if EVEX.ZU=1. 1934 "SC" => print suffix SCC for SCC insns 1935 "YK" keep unused, to avoid ambiguity with the combined use of Y and K. 1936 "YX" keep unused, to avoid ambiguity with the combined use of Y and X. 1937 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond 1938 being false, or no operand at all in 64bit mode, or if suffix_always 1939 is true. 1940 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise 1941 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise 1942 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise 1943 "DQ" => print 'd' or 'q' depending on the VEX.W bit 1944 "DF" => print default flag value for SCC insns 1945 "BW" => print 'b' or 'w' depending on the VEX.W bit 1946 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has 1947 an operand size prefix, or suffix_always is true. print 1948 'q' if rex prefix is present. 1949 1950 Many of the above letters print nothing in Intel mode. See "putop" 1951 for the details. 1952 1953 Braces '{' and '}', and vertical bars '|', indicate alternative 1954 mnemonic strings for AT&T and Intel. */ 1955 1956 static const struct dis386 dis386[] = { 1957 /* 00 */ 1958 { "addB", { Ebh1, Gb }, 0 }, 1959 { "addS", { Evh1, Gv }, 0 }, 1960 { "addB", { Gb, EbS }, 0 }, 1961 { "addS", { Gv, EvS }, 0 }, 1962 { "addB", { AL, Ib }, 0 }, 1963 { "addS", { eAX, Iv }, 0 }, 1964 { X86_64_TABLE (X86_64_06) }, 1965 { X86_64_TABLE (X86_64_07) }, 1966 /* 08 */ 1967 { "orB", { Ebh1, Gb }, 0 }, 1968 { "orS", { Evh1, Gv }, 0 }, 1969 { "orB", { Gb, EbS }, 0 }, 1970 { "orS", { Gv, EvS }, 0 }, 1971 { "orB", { AL, Ib }, 0 }, 1972 { "orS", { eAX, Iv }, 0 }, 1973 { X86_64_TABLE (X86_64_0E) }, 1974 { Bad_Opcode }, /* 0x0f extended opcode escape */ 1975 /* 10 */ 1976 { "adcB", { Ebh1, Gb }, 0 }, 1977 { "adcS", { Evh1, Gv }, 0 }, 1978 { "adcB", { Gb, EbS }, 0 }, 1979 { "adcS", { Gv, EvS }, 0 }, 1980 { "adcB", { AL, Ib }, 0 }, 1981 { "adcS", { eAX, Iv }, 0 }, 1982 { X86_64_TABLE (X86_64_16) }, 1983 { X86_64_TABLE (X86_64_17) }, 1984 /* 18 */ 1985 { "sbbB", { Ebh1, Gb }, 0 }, 1986 { "sbbS", { Evh1, Gv }, 0 }, 1987 { "sbbB", { Gb, EbS }, 0 }, 1988 { "sbbS", { Gv, EvS }, 0 }, 1989 { "sbbB", { AL, Ib }, 0 }, 1990 { "sbbS", { eAX, Iv }, 0 }, 1991 { X86_64_TABLE (X86_64_1E) }, 1992 { X86_64_TABLE (X86_64_1F) }, 1993 /* 20 */ 1994 { "andB", { Ebh1, Gb }, 0 }, 1995 { "andS", { Evh1, Gv }, 0 }, 1996 { "andB", { Gb, EbS }, 0 }, 1997 { "andS", { Gv, EvS }, 0 }, 1998 { "andB", { AL, Ib }, 0 }, 1999 { "andS", { eAX, Iv }, 0 }, 2000 { Bad_Opcode }, /* SEG ES prefix */ 2001 { X86_64_TABLE (X86_64_27) }, 2002 /* 28 */ 2003 { "subB", { Ebh1, Gb }, 0 }, 2004 { "subS", { Evh1, Gv }, 0 }, 2005 { "subB", { Gb, EbS }, 0 }, 2006 { "subS", { Gv, EvS }, 0 }, 2007 { "subB", { AL, Ib }, 0 }, 2008 { "subS", { eAX, Iv }, 0 }, 2009 { Bad_Opcode }, /* SEG CS prefix */ 2010 { X86_64_TABLE (X86_64_2F) }, 2011 /* 30 */ 2012 { "xorB", { Ebh1, Gb }, 0 }, 2013 { "xorS", { Evh1, Gv }, 0 }, 2014 { "xorB", { Gb, EbS }, 0 }, 2015 { "xorS", { Gv, EvS }, 0 }, 2016 { "xorB", { AL, Ib }, 0 }, 2017 { "xorS", { eAX, Iv }, 0 }, 2018 { Bad_Opcode }, /* SEG SS prefix */ 2019 { X86_64_TABLE (X86_64_37) }, 2020 /* 38 */ 2021 { "cmpB", { Eb, Gb }, 0 }, 2022 { "cmpS", { Ev, Gv }, 0 }, 2023 { "cmpB", { Gb, EbS }, 0 }, 2024 { "cmpS", { Gv, EvS }, 0 }, 2025 { "cmpB", { AL, Ib }, 0 }, 2026 { "cmpS", { eAX, Iv }, 0 }, 2027 { Bad_Opcode }, /* SEG DS prefix */ 2028 { X86_64_TABLE (X86_64_3F) }, 2029 /* 40 */ 2030 { "inc{S|}", { RMeAX }, 0 }, 2031 { "inc{S|}", { RMeCX }, 0 }, 2032 { "inc{S|}", { RMeDX }, 0 }, 2033 { "inc{S|}", { RMeBX }, 0 }, 2034 { "inc{S|}", { RMeSP }, 0 }, 2035 { "inc{S|}", { RMeBP }, 0 }, 2036 { "inc{S|}", { RMeSI }, 0 }, 2037 { "inc{S|}", { RMeDI }, 0 }, 2038 /* 48 */ 2039 { "dec{S|}", { RMeAX }, 0 }, 2040 { "dec{S|}", { RMeCX }, 0 }, 2041 { "dec{S|}", { RMeDX }, 0 }, 2042 { "dec{S|}", { RMeBX }, 0 }, 2043 { "dec{S|}", { RMeSP }, 0 }, 2044 { "dec{S|}", { RMeBP }, 0 }, 2045 { "dec{S|}", { RMeSI }, 0 }, 2046 { "dec{S|}", { RMeDI }, 0 }, 2047 /* 50 */ 2048 { "push!P", { RMrAX }, 0 }, 2049 { "push!P", { RMrCX }, 0 }, 2050 { "push!P", { RMrDX }, 0 }, 2051 { "push!P", { RMrBX }, 0 }, 2052 { "push!P", { RMrSP }, 0 }, 2053 { "push!P", { RMrBP }, 0 }, 2054 { "push!P", { RMrSI }, 0 }, 2055 { "push!P", { RMrDI }, 0 }, 2056 /* 58 */ 2057 { "pop!P", { RMrAX }, 0 }, 2058 { "pop!P", { RMrCX }, 0 }, 2059 { "pop!P", { RMrDX }, 0 }, 2060 { "pop!P", { RMrBX }, 0 }, 2061 { "pop!P", { RMrSP }, 0 }, 2062 { "pop!P", { RMrBP }, 0 }, 2063 { "pop!P", { RMrSI }, 0 }, 2064 { "pop!P", { RMrDI }, 0 }, 2065 /* 60 */ 2066 { X86_64_TABLE (X86_64_60) }, 2067 { X86_64_TABLE (X86_64_61) }, 2068 { X86_64_TABLE (X86_64_62) }, 2069 { X86_64_TABLE (X86_64_63) }, 2070 { Bad_Opcode }, /* seg fs */ 2071 { Bad_Opcode }, /* seg gs */ 2072 { Bad_Opcode }, /* op size prefix */ 2073 { Bad_Opcode }, /* adr size prefix */ 2074 /* 68 */ 2075 { "pushP", { sIv }, 0 }, 2076 { "imulS", { Gv, Ev, Iv }, 0 }, 2077 { "pushP", { sIbT }, 0 }, 2078 { "imulS", { Gv, Ev, sIb }, 0 }, 2079 { "ins{b|}", { Ybr, indirDX }, 0 }, 2080 { X86_64_TABLE (X86_64_6D) }, 2081 { "outs{b|}", { indirDXr, Xb }, 0 }, 2082 { X86_64_TABLE (X86_64_6F) }, 2083 /* 70 */ 2084 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2085 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2086 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2087 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2088 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2089 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2090 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2091 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2092 /* 78 */ 2093 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2094 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2095 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2096 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2097 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2098 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2099 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2100 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2101 /* 80 */ 2102 { REG_TABLE (REG_80) }, 2103 { REG_TABLE (REG_81) }, 2104 { X86_64_TABLE (X86_64_82) }, 2105 { REG_TABLE (REG_83) }, 2106 { "testB", { Eb, Gb }, 0 }, 2107 { "testS", { Ev, Gv }, 0 }, 2108 { "xchgB", { Ebh2, Gb }, 0 }, 2109 { "xchgS", { Evh2, Gv }, 0 }, 2110 /* 88 */ 2111 { "movB", { Ebh3, Gb }, 0 }, 2112 { "movS", { Evh3, Gv }, 0 }, 2113 { "movB", { Gb, EbS }, 0 }, 2114 { "movS", { Gv, EvS }, 0 }, 2115 { "movD", { Sv, Sw }, 0 }, 2116 { "leaS", { Gv, M }, 0 }, 2117 { "movD", { Sw, Sv }, 0 }, 2118 { REG_TABLE (REG_8F) }, 2119 /* 90 */ 2120 { PREFIX_TABLE (PREFIX_90) }, 2121 { "xchgS", { RMeCX, eAX }, 0 }, 2122 { "xchgS", { RMeDX, eAX }, 0 }, 2123 { "xchgS", { RMeBX, eAX }, 0 }, 2124 { "xchgS", { RMeSP, eAX }, 0 }, 2125 { "xchgS", { RMeBP, eAX }, 0 }, 2126 { "xchgS", { RMeSI, eAX }, 0 }, 2127 { "xchgS", { RMeDI, eAX }, 0 }, 2128 /* 98 */ 2129 { "cW{t|}R", { XX }, 0 }, 2130 { "cR{t|}O", { XX }, 0 }, 2131 { X86_64_TABLE (X86_64_9A) }, 2132 { Bad_Opcode }, /* fwait */ 2133 { "pushfP", { XX }, 0 }, 2134 { "popfP", { XX }, 0 }, 2135 { "sahf", { XX }, 0 }, 2136 { "lahf", { XX }, 0 }, 2137 /* a0 */ 2138 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL }, 2139 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL }, 2140 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL }, 2141 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL }, 2142 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL }, 2143 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL }, 2144 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL }, 2145 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL }, 2146 /* a8 */ 2147 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, 2148 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL }, 2149 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL }, 2150 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL }, 2151 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL }, 2152 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL }, 2153 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL }, 2154 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL }, 2155 /* b0 */ 2156 { "movB", { RMAL, Ib }, 0 }, 2157 { "movB", { RMCL, Ib }, 0 }, 2158 { "movB", { RMDL, Ib }, 0 }, 2159 { "movB", { RMBL, Ib }, 0 }, 2160 { "movB", { RMAH, Ib }, 0 }, 2161 { "movB", { RMCH, Ib }, 0 }, 2162 { "movB", { RMDH, Ib }, 0 }, 2163 { "movB", { RMBH, Ib }, 0 }, 2164 /* b8 */ 2165 { "mov%LV", { RMeAX, Iv64 }, 0 }, 2166 { "mov%LV", { RMeCX, Iv64 }, 0 }, 2167 { "mov%LV", { RMeDX, Iv64 }, 0 }, 2168 { "mov%LV", { RMeBX, Iv64 }, 0 }, 2169 { "mov%LV", { RMeSP, Iv64 }, 0 }, 2170 { "mov%LV", { RMeBP, Iv64 }, 0 }, 2171 { "mov%LV", { RMeSI, Iv64 }, 0 }, 2172 { "mov%LV", { RMeDI, Iv64 }, 0 }, 2173 /* c0 */ 2174 { REG_TABLE (REG_C0) }, 2175 { REG_TABLE (REG_C1) }, 2176 { X86_64_TABLE (X86_64_C2) }, 2177 { X86_64_TABLE (X86_64_C3) }, 2178 { X86_64_TABLE (X86_64_C4) }, 2179 { X86_64_TABLE (X86_64_C5) }, 2180 { REG_TABLE (REG_C6) }, 2181 { REG_TABLE (REG_C7) }, 2182 /* c8 */ 2183 { "enterP", { Iw, Ib }, 0 }, 2184 { "leaveP", { XX }, 0 }, 2185 { "{l|}ret{|f}%LP", { Iw }, 0 }, 2186 { "{l|}ret{|f}%LP", { XX }, 0 }, 2187 { "int3", { XX }, 0 }, 2188 { "int", { Ib }, 0 }, 2189 { X86_64_TABLE (X86_64_CE) }, 2190 { "iret%LP", { XX }, 0 }, 2191 /* d0 */ 2192 { REG_TABLE (REG_D0) }, 2193 { REG_TABLE (REG_D1) }, 2194 { REG_TABLE (REG_D2) }, 2195 { REG_TABLE (REG_D3) }, 2196 { X86_64_TABLE (X86_64_D4) }, 2197 { X86_64_TABLE (X86_64_D5) }, 2198 { X86_64_TABLE (X86_64_D6) }, 2199 { "xlat", { DSBX }, 0 }, 2200 /* d8 */ 2201 { FLOAT }, 2202 { FLOAT }, 2203 { FLOAT }, 2204 { FLOAT }, 2205 { FLOAT }, 2206 { FLOAT }, 2207 { FLOAT }, 2208 { FLOAT }, 2209 /* e0 */ 2210 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2211 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2212 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2213 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL }, 2214 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL }, 2215 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL }, 2216 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL }, 2217 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL }, 2218 /* e8 */ 2219 { X86_64_TABLE (X86_64_E8) }, 2220 { X86_64_TABLE (X86_64_E9) }, 2221 { X86_64_TABLE (X86_64_EA) }, 2222 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL }, 2223 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL }, 2224 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL }, 2225 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL }, 2226 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL }, 2227 /* f0 */ 2228 { Bad_Opcode }, /* lock prefix */ 2229 { "int1", { XX }, 0 }, 2230 { Bad_Opcode }, /* repne */ 2231 { Bad_Opcode }, /* repz */ 2232 { "hlt", { XX }, 0 }, 2233 { "cmc", { XX }, 0 }, 2234 { REG_TABLE (REG_F6) }, 2235 { REG_TABLE (REG_F7) }, 2236 /* f8 */ 2237 { "clc", { XX }, 0 }, 2238 { "stc", { XX }, 0 }, 2239 { "cli", { XX }, 0 }, 2240 { "sti", { XX }, 0 }, 2241 { "cld", { XX }, 0 }, 2242 { "std", { XX }, 0 }, 2243 { REG_TABLE (REG_FE) }, 2244 { REG_TABLE (REG_FF) }, 2245 }; 2246 2247 static const struct dis386 dis386_twobyte[] = { 2248 /* 00 */ 2249 { REG_TABLE (REG_0F00 ) }, 2250 { REG_TABLE (REG_0F01 ) }, 2251 { "larS", { Gv, Sv }, 0 }, 2252 { "lslS", { Gv, Sv }, 0 }, 2253 { Bad_Opcode }, 2254 { "syscall", { XX }, 0 }, 2255 { "clts", { XX }, 0 }, 2256 { "sysret%LQ", { XX }, 0 }, 2257 /* 08 */ 2258 { "invd", { XX }, 0 }, 2259 { PREFIX_TABLE (PREFIX_0F09) }, 2260 { Bad_Opcode }, 2261 { "ud2", { XX }, 0 }, 2262 { Bad_Opcode }, 2263 { REG_TABLE (REG_0F0D) }, 2264 { "femms", { XX }, 0 }, 2265 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ 2266 /* 10 */ 2267 { PREFIX_TABLE (PREFIX_0F10) }, 2268 { PREFIX_TABLE (PREFIX_0F11) }, 2269 { PREFIX_TABLE (PREFIX_0F12) }, 2270 { "movlpX", { Mq, XM }, PREFIX_OPCODE }, 2271 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, 2272 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, 2273 { PREFIX_TABLE (PREFIX_0F16) }, 2274 { "movhpX", { Mq, XM }, PREFIX_OPCODE }, 2275 /* 18 */ 2276 { REG_TABLE (REG_0F18) }, 2277 { "nopQ", { Ev }, 0 }, 2278 { PREFIX_TABLE (PREFIX_0F1A) }, 2279 { PREFIX_TABLE (PREFIX_0F1B) }, 2280 { PREFIX_TABLE (PREFIX_0F1C) }, 2281 { "nopQ", { Ev }, 0 }, 2282 { PREFIX_TABLE (PREFIX_0F1E) }, 2283 { "nopQ", { Ev }, 0 }, 2284 /* 20 */ 2285 { "movZ", { Em, Cm }, 0 }, 2286 { "movZ", { Em, Dm }, 0 }, 2287 { "movZ", { Cm, Em }, 0 }, 2288 { "movZ", { Dm, Em }, 0 }, 2289 { X86_64_TABLE (X86_64_0F24) }, 2290 { Bad_Opcode }, 2291 { X86_64_TABLE (X86_64_0F26) }, 2292 { Bad_Opcode }, 2293 /* 28 */ 2294 { "movapX", { XM, EXx }, PREFIX_OPCODE }, 2295 { "movapX", { EXxS, XM }, PREFIX_OPCODE }, 2296 { PREFIX_TABLE (PREFIX_0F2A) }, 2297 { PREFIX_TABLE (PREFIX_0F2B) }, 2298 { PREFIX_TABLE (PREFIX_0F2C) }, 2299 { PREFIX_TABLE (PREFIX_0F2D) }, 2300 { PREFIX_TABLE (PREFIX_0F2E) }, 2301 { PREFIX_TABLE (PREFIX_0F2F) }, 2302 /* 30 */ 2303 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL }, 2304 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL }, 2305 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL }, 2306 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL }, 2307 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL }, 2308 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL }, 2309 { Bad_Opcode }, 2310 { "getsec", { XX }, PREFIX_REX2_ILLEGAL }, 2311 /* 38 */ 2312 { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, 2313 { Bad_Opcode }, 2314 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, 2315 { Bad_Opcode }, 2316 { Bad_Opcode }, 2317 { Bad_Opcode }, 2318 { Bad_Opcode }, 2319 { Bad_Opcode }, 2320 /* 40 */ 2321 { "cmovoS", { Gv, Ev }, 0 }, 2322 { "cmovnoS", { Gv, Ev }, 0 }, 2323 { "cmovbS", { Gv, Ev }, 0 }, 2324 { "cmovaeS", { Gv, Ev }, 0 }, 2325 { "cmoveS", { Gv, Ev }, 0 }, 2326 { "cmovneS", { Gv, Ev }, 0 }, 2327 { "cmovbeS", { Gv, Ev }, 0 }, 2328 { "cmovaS", { Gv, Ev }, 0 }, 2329 /* 48 */ 2330 { "cmovsS", { Gv, Ev }, 0 }, 2331 { "cmovnsS", { Gv, Ev }, 0 }, 2332 { "cmovpS", { Gv, Ev }, 0 }, 2333 { "cmovnpS", { Gv, Ev }, 0 }, 2334 { "cmovlS", { Gv, Ev }, 0 }, 2335 { "cmovgeS", { Gv, Ev }, 0 }, 2336 { "cmovleS", { Gv, Ev }, 0 }, 2337 { "cmovgS", { Gv, Ev }, 0 }, 2338 /* 50 */ 2339 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE }, 2340 { PREFIX_TABLE (PREFIX_0F51) }, 2341 { PREFIX_TABLE (PREFIX_0F52) }, 2342 { PREFIX_TABLE (PREFIX_0F53) }, 2343 { "andpX", { XM, EXx }, PREFIX_OPCODE }, 2344 { "andnpX", { XM, EXx }, PREFIX_OPCODE }, 2345 { "orpX", { XM, EXx }, PREFIX_OPCODE }, 2346 { "xorpX", { XM, EXx }, PREFIX_OPCODE }, 2347 /* 58 */ 2348 { PREFIX_TABLE (PREFIX_0F58) }, 2349 { PREFIX_TABLE (PREFIX_0F59) }, 2350 { PREFIX_TABLE (PREFIX_0F5A) }, 2351 { PREFIX_TABLE (PREFIX_0F5B) }, 2352 { PREFIX_TABLE (PREFIX_0F5C) }, 2353 { PREFIX_TABLE (PREFIX_0F5D) }, 2354 { PREFIX_TABLE (PREFIX_0F5E) }, 2355 { PREFIX_TABLE (PREFIX_0F5F) }, 2356 /* 60 */ 2357 { PREFIX_TABLE (PREFIX_0F60) }, 2358 { PREFIX_TABLE (PREFIX_0F61) }, 2359 { PREFIX_TABLE (PREFIX_0F62) }, 2360 { "packsswb", { MX, EM }, PREFIX_OPCODE }, 2361 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, 2362 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, 2363 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, 2364 { "packuswb", { MX, EM }, PREFIX_OPCODE }, 2365 /* 68 */ 2366 { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, 2367 { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, 2368 { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, 2369 { "packssdw", { MX, EM }, PREFIX_OPCODE }, 2370 { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, 2371 { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, 2372 { "movK", { MX, Edq }, PREFIX_OPCODE }, 2373 { PREFIX_TABLE (PREFIX_0F6F) }, 2374 /* 70 */ 2375 { PREFIX_TABLE (PREFIX_0F70) }, 2376 { REG_TABLE (REG_0F71) }, 2377 { REG_TABLE (REG_0F72) }, 2378 { REG_TABLE (REG_0F73) }, 2379 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, 2380 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, 2381 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, 2382 { "emms", { XX }, PREFIX_OPCODE }, 2383 /* 78 */ 2384 { PREFIX_TABLE (PREFIX_0F78) }, 2385 { PREFIX_TABLE (PREFIX_0F79) }, 2386 { Bad_Opcode }, 2387 { Bad_Opcode }, 2388 { PREFIX_TABLE (PREFIX_0F7C) }, 2389 { PREFIX_TABLE (PREFIX_0F7D) }, 2390 { PREFIX_TABLE (PREFIX_0F7E) }, 2391 { PREFIX_TABLE (PREFIX_0F7F) }, 2392 /* 80 */ 2393 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2394 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2395 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2396 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2397 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2398 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2399 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2400 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2401 /* 88 */ 2402 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2403 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2404 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2405 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2406 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2407 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2408 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2409 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL }, 2410 /* 90 */ 2411 { "seto", { Eb }, 0 }, 2412 { "setno", { Eb }, 0 }, 2413 { "setb", { Eb }, 0 }, 2414 { "setae", { Eb }, 0 }, 2415 { "sete", { Eb }, 0 }, 2416 { "setne", { Eb }, 0 }, 2417 { "setbe", { Eb }, 0 }, 2418 { "seta", { Eb }, 0 }, 2419 /* 98 */ 2420 { "sets", { Eb }, 0 }, 2421 { "setns", { Eb }, 0 }, 2422 { "setp", { Eb }, 0 }, 2423 { "setnp", { Eb }, 0 }, 2424 { "setl", { Eb }, 0 }, 2425 { "setge", { Eb }, 0 }, 2426 { "setle", { Eb }, 0 }, 2427 { "setg", { Eb }, 0 }, 2428 /* a0 */ 2429 { "pushP", { fs }, 0 }, 2430 { "popP", { fs }, 0 }, 2431 { "cpuid", { XX }, 0 }, 2432 { "btS", { Ev, Gv }, 0 }, 2433 { "shldS", { Ev, Gv, Ib }, 0 }, 2434 { "shldS", { Ev, Gv, CL }, 0 }, 2435 { REG_TABLE (REG_0FA6) }, 2436 { REG_TABLE (REG_0FA7) }, 2437 /* a8 */ 2438 { "pushP", { gs }, 0 }, 2439 { "popP", { gs }, 0 }, 2440 { "rsm", { XX }, 0 }, 2441 { "btsS", { Evh1, Gv }, 0 }, 2442 { "shrdS", { Ev, Gv, Ib }, 0 }, 2443 { "shrdS", { Ev, Gv, CL }, 0 }, 2444 { REG_TABLE (REG_0FAE) }, 2445 { "imulS", { Gv, Ev }, 0 }, 2446 /* b0 */ 2447 { "cmpxchgB", { Ebh1, Gb }, 0 }, 2448 { "cmpxchgS", { Evh1, Gv }, 0 }, 2449 { "lssS", { Gv, Mp }, 0 }, 2450 { "btrS", { Evh1, Gv }, 0 }, 2451 { "lfsS", { Gv, Mp }, 0 }, 2452 { "lgsS", { Gv, Mp }, 0 }, 2453 { "movz{bR|x}", { Gv, Eb }, 0 }, 2454 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ 2455 /* b8 */ 2456 { PREFIX_TABLE (PREFIX_0FB8) }, 2457 { "ud1S", { Gv, Ev }, 0 }, 2458 { REG_TABLE (REG_0FBA) }, 2459 { "btcS", { Evh1, Gv }, 0 }, 2460 { PREFIX_TABLE (PREFIX_0FBC) }, 2461 { PREFIX_TABLE (PREFIX_0FBD) }, 2462 { "movs{bR|x}", { Gv, Eb }, 0 }, 2463 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ 2464 /* c0 */ 2465 { "xaddB", { Ebh1, Gb }, 0 }, 2466 { "xaddS", { Evh1, Gv }, 0 }, 2467 { PREFIX_TABLE (PREFIX_0FC2) }, 2468 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE }, 2469 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE }, 2470 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE }, 2471 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, 2472 { REG_TABLE (REG_0FC7) }, 2473 /* c8 */ 2474 { "bswap", { RMeAX }, 0 }, 2475 { "bswap", { RMeCX }, 0 }, 2476 { "bswap", { RMeDX }, 0 }, 2477 { "bswap", { RMeBX }, 0 }, 2478 { "bswap", { RMeSP }, 0 }, 2479 { "bswap", { RMeBP }, 0 }, 2480 { "bswap", { RMeSI }, 0 }, 2481 { "bswap", { RMeDI }, 0 }, 2482 /* d0 */ 2483 { PREFIX_TABLE (PREFIX_0FD0) }, 2484 { "psrlw", { MX, EM }, PREFIX_OPCODE }, 2485 { "psrld", { MX, EM }, PREFIX_OPCODE }, 2486 { "psrlq", { MX, EM }, PREFIX_OPCODE }, 2487 { "paddq", { MX, EM }, PREFIX_OPCODE }, 2488 { "pmullw", { MX, EM }, PREFIX_OPCODE }, 2489 { PREFIX_TABLE (PREFIX_0FD6) }, 2490 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE }, 2491 /* d8 */ 2492 { "psubusb", { MX, EM }, PREFIX_OPCODE }, 2493 { "psubusw", { MX, EM }, PREFIX_OPCODE }, 2494 { "pminub", { MX, EM }, PREFIX_OPCODE }, 2495 { "pand", { MX, EM }, PREFIX_OPCODE }, 2496 { "paddusb", { MX, EM }, PREFIX_OPCODE }, 2497 { "paddusw", { MX, EM }, PREFIX_OPCODE }, 2498 { "pmaxub", { MX, EM }, PREFIX_OPCODE }, 2499 { "pandn", { MX, EM }, PREFIX_OPCODE }, 2500 /* e0 */ 2501 { "pavgb", { MX, EM }, PREFIX_OPCODE }, 2502 { "psraw", { MX, EM }, PREFIX_OPCODE }, 2503 { "psrad", { MX, EM }, PREFIX_OPCODE }, 2504 { "pavgw", { MX, EM }, PREFIX_OPCODE }, 2505 { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, 2506 { "pmulhw", { MX, EM }, PREFIX_OPCODE }, 2507 { PREFIX_TABLE (PREFIX_0FE6) }, 2508 { PREFIX_TABLE (PREFIX_0FE7) }, 2509 /* e8 */ 2510 { "psubsb", { MX, EM }, PREFIX_OPCODE }, 2511 { "psubsw", { MX, EM }, PREFIX_OPCODE }, 2512 { "pminsw", { MX, EM }, PREFIX_OPCODE }, 2513 { "por", { MX, EM }, PREFIX_OPCODE }, 2514 { "paddsb", { MX, EM }, PREFIX_OPCODE }, 2515 { "paddsw", { MX, EM }, PREFIX_OPCODE }, 2516 { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, 2517 { "pxor", { MX, EM }, PREFIX_OPCODE }, 2518 /* f0 */ 2519 { PREFIX_TABLE (PREFIX_0FF0) }, 2520 { "psllw", { MX, EM }, PREFIX_OPCODE }, 2521 { "pslld", { MX, EM }, PREFIX_OPCODE }, 2522 { "psllq", { MX, EM }, PREFIX_OPCODE }, 2523 { "pmuludq", { MX, EM }, PREFIX_OPCODE }, 2524 { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, 2525 { "psadbw", { MX, EM }, PREFIX_OPCODE }, 2526 { PREFIX_TABLE (PREFIX_0FF7) }, 2527 /* f8 */ 2528 { "psubb", { MX, EM }, PREFIX_OPCODE }, 2529 { "psubw", { MX, EM }, PREFIX_OPCODE }, 2530 { "psubd", { MX, EM }, PREFIX_OPCODE }, 2531 { "psubq", { MX, EM }, PREFIX_OPCODE }, 2532 { "paddb", { MX, EM }, PREFIX_OPCODE }, 2533 { "paddw", { MX, EM }, PREFIX_OPCODE }, 2534 { "paddd", { MX, EM }, PREFIX_OPCODE }, 2535 { "ud0S", { Gv, Ev }, 0 }, 2536 }; 2537 2538 static const bool onebyte_has_modrm[256] = { 2539 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2540 /* ------------------------------- */ 2541 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 2542 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 2543 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 2544 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 2545 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 2546 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 2547 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 2548 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 2549 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 2550 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 2551 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 2552 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 2553 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 2554 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 2555 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 2556 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 2557 /* ------------------------------- */ 2558 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2559 }; 2560 2561 static const bool twobyte_has_modrm[256] = { 2562 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2563 /* ------------------------------- */ 2564 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 2565 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 2566 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 2567 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 2568 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 2569 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 2570 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 2571 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 2572 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 2573 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 2574 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 2575 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ 2576 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 2577 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 2578 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 2579 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ 2580 /* ------------------------------- */ 2581 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2582 }; 2583 2584 2585 struct op 2586 { 2587 const char *name; 2588 unsigned int len; 2589 }; 2590 2591 /* If we are accessing mod/rm/reg without need_modrm set, then the 2592 values are stale. Hitting this abort likely indicates that you 2593 need to update onebyte_has_modrm or twobyte_has_modrm. */ 2594 #define MODRM_CHECK if (!ins->need_modrm) abort () 2595 2596 static const char intel_index16[][6] = { 2597 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 2598 }; 2599 2600 static const char att_names64[][8] = { 2601 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 2602 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 2603 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", 2604 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", 2605 }; 2606 static const char att_names32[][8] = { 2607 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 2608 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d", 2609 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d", 2610 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d", 2611 }; 2612 static const char att_names16[][8] = { 2613 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 2614 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w", 2615 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w", 2616 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w", 2617 }; 2618 static const char att_names8[][8] = { 2619 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 2620 }; 2621 static const char att_names8rex[][8] = { 2622 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 2623 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b", 2624 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b", 2625 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b", 2626 }; 2627 static const char att_names_seg[][4] = { 2628 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 2629 }; 2630 static const char att_index64[] = "%riz"; 2631 static const char att_index32[] = "%eiz"; 2632 static const char att_index16[][8] = { 2633 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 2634 }; 2635 2636 static const char att_names_mm[][8] = { 2637 "%mm0", "%mm1", "%mm2", "%mm3", 2638 "%mm4", "%mm5", "%mm6", "%mm7" 2639 }; 2640 2641 static const char att_names_bnd[][8] = { 2642 "%bnd0", "%bnd1", "%bnd2", "%bnd3" 2643 }; 2644 2645 static const char att_names_xmm[][8] = { 2646 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 2647 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 2648 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 2649 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 2650 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 2651 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 2652 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 2653 "%xmm28", "%xmm29", "%xmm30", "%xmm31" 2654 }; 2655 2656 static const char att_names_ymm[][8] = { 2657 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 2658 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 2659 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 2660 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 2661 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 2662 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 2663 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 2664 "%ymm28", "%ymm29", "%ymm30", "%ymm31" 2665 }; 2666 2667 static const char att_names_zmm[][8] = { 2668 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 2669 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 2670 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 2671 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 2672 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 2673 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 2674 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 2675 "%zmm28", "%zmm29", "%zmm30", "%zmm31" 2676 }; 2677 2678 static const char att_names_tmm[][8] = { 2679 "%tmm0", "%tmm1", "%tmm2", "%tmm3", 2680 "%tmm4", "%tmm5", "%tmm6", "%tmm7" 2681 }; 2682 2683 static const char att_names_mask[][8] = { 2684 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 2685 }; 2686 2687 static const char *const names_rounding[] = 2688 { 2689 "{rn-", 2690 "{rd-", 2691 "{ru-", 2692 "{rz-" 2693 }; 2694 2695 static const struct dis386 reg_table[][8] = { 2696 /* REG_80 */ 2697 { 2698 { "addA", { Ebh1, Ib }, 0 }, 2699 { "orA", { Ebh1, Ib }, 0 }, 2700 { "adcA", { Ebh1, Ib }, 0 }, 2701 { "sbbA", { Ebh1, Ib }, 0 }, 2702 { "andA", { Ebh1, Ib }, 0 }, 2703 { "subA", { Ebh1, Ib }, 0 }, 2704 { "xorA", { Ebh1, Ib }, 0 }, 2705 { "cmpA", { Eb, Ib }, 0 }, 2706 }, 2707 /* REG_81 */ 2708 { 2709 { "addQ", { Evh1, Iv }, 0 }, 2710 { "orQ", { Evh1, Iv }, 0 }, 2711 { "adcQ", { Evh1, Iv }, 0 }, 2712 { "sbbQ", { Evh1, Iv }, 0 }, 2713 { "andQ", { Evh1, Iv }, 0 }, 2714 { "subQ", { Evh1, Iv }, 0 }, 2715 { "xorQ", { Evh1, Iv }, 0 }, 2716 { "cmpQ", { Ev, Iv }, 0 }, 2717 }, 2718 /* REG_83 */ 2719 { 2720 { "addQ", { Evh1, sIb }, 0 }, 2721 { "orQ", { Evh1, sIb }, 0 }, 2722 { "adcQ", { Evh1, sIb }, 0 }, 2723 { "sbbQ", { Evh1, sIb }, 0 }, 2724 { "andQ", { Evh1, sIb }, 0 }, 2725 { "subQ", { Evh1, sIb }, 0 }, 2726 { "xorQ", { Evh1, sIb }, 0 }, 2727 { "cmpQ", { Ev, sIb }, 0 }, 2728 }, 2729 /* REG_8F */ 2730 { 2731 { "pop{P|}", { stackEv }, 0 }, 2732 { XOP_8F_TABLE () }, 2733 { Bad_Opcode }, 2734 { Bad_Opcode }, 2735 { Bad_Opcode }, 2736 { XOP_8F_TABLE () }, 2737 }, 2738 /* REG_C0 */ 2739 { 2740 { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX }, 2741 { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX }, 2742 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX }, 2743 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX }, 2744 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, 2745 { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX }, 2746 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX }, 2747 { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX }, 2748 }, 2749 /* REG_C1 */ 2750 { 2751 { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2752 { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2753 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2754 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2755 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2756 { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2757 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2758 { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA }, 2759 }, 2760 /* REG_C6 */ 2761 { 2762 { "movA", { Ebh3, Ib }, 0 }, 2763 { Bad_Opcode }, 2764 { Bad_Opcode }, 2765 { Bad_Opcode }, 2766 { Bad_Opcode }, 2767 { Bad_Opcode }, 2768 { Bad_Opcode }, 2769 { RM_TABLE (RM_C6_REG_7) }, 2770 }, 2771 /* REG_C7 */ 2772 { 2773 { "movQ", { Evh3, Iv }, 0 }, 2774 { Bad_Opcode }, 2775 { Bad_Opcode }, 2776 { Bad_Opcode }, 2777 { Bad_Opcode }, 2778 { Bad_Opcode }, 2779 { Bad_Opcode }, 2780 { RM_TABLE (RM_C7_REG_7) }, 2781 }, 2782 /* REG_D0 */ 2783 { 2784 { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX }, 2785 { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX }, 2786 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX }, 2787 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX }, 2788 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, 2789 { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX }, 2790 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX }, 2791 { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX }, 2792 }, 2793 /* REG_D1 */ 2794 { 2795 { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2796 { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2797 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2798 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2799 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2800 { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2801 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2802 { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA }, 2803 }, 2804 /* REG_D2 */ 2805 { 2806 { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX }, 2807 { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX }, 2808 { "rclA", { VexGb, Eb, CL }, NO_PREFIX }, 2809 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX }, 2810 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, 2811 { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX }, 2812 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX }, 2813 { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX }, 2814 }, 2815 /* REG_D3 */ 2816 { 2817 { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2818 { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2819 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2820 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2821 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2822 { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2823 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2824 { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA }, 2825 }, 2826 /* REG_F6 */ 2827 { 2828 { "testA", { Eb, Ib }, 0 }, 2829 { "testA", { Eb, Ib }, 0 }, 2830 { "notA", { Ebh1 }, 0 }, 2831 { "negA", { Ebh1 }, 0 }, 2832 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ 2833 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ 2834 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ 2835 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ 2836 }, 2837 /* REG_F7 */ 2838 { 2839 { "testQ", { Ev, Iv }, 0 }, 2840 { "testQ", { Ev, Iv }, 0 }, 2841 { "notQ", { Evh1 }, 0 }, 2842 { "negQ", { Evh1 }, 0 }, 2843 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ 2844 { "imulQ", { Ev }, 0 }, 2845 { "divQ", { Ev }, 0 }, 2846 { "idivQ", { Ev }, 0 }, 2847 }, 2848 /* REG_FE */ 2849 { 2850 { "incA", { Ebh1 }, 0 }, 2851 { "decA", { Ebh1 }, 0 }, 2852 }, 2853 /* REG_FF */ 2854 { 2855 { "incQ", { Evh1 }, 0 }, 2856 { "decQ", { Evh1 }, 0 }, 2857 { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, 2858 { "{l|}call^", { indirEp }, 0 }, 2859 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, 2860 { "{l|}jmp^", { indirEp }, 0 }, 2861 { "push{P|}", { stackEv }, 0 }, 2862 { Bad_Opcode }, 2863 }, 2864 /* REG_0F00 */ 2865 { 2866 { "sldtD", { Sv }, 0 }, 2867 { "strD", { Sv }, 0 }, 2868 { "lldtD", { Sv }, 0 }, 2869 { "ltrD", { Sv }, 0 }, 2870 { "verrD", { Sv }, 0 }, 2871 { "verwD", { Sv }, 0 }, 2872 { X86_64_TABLE (X86_64_0F00_REG_6) }, 2873 { Bad_Opcode }, 2874 }, 2875 /* REG_0F01 */ 2876 { 2877 { MOD_TABLE (MOD_0F01_REG_0) }, 2878 { MOD_TABLE (MOD_0F01_REG_1) }, 2879 { MOD_TABLE (MOD_0F01_REG_2) }, 2880 { MOD_TABLE (MOD_0F01_REG_3) }, 2881 { "smswD", { Sv }, 0 }, 2882 { MOD_TABLE (MOD_0F01_REG_5) }, 2883 { "lmsw", { Ew }, 0 }, 2884 { MOD_TABLE (MOD_0F01_REG_7) }, 2885 }, 2886 /* REG_0F0D */ 2887 { 2888 { "prefetch", { Mb }, 0 }, 2889 { "prefetchw", { Mb }, 0 }, 2890 { "prefetchwt1", { Mb }, 0 }, 2891 { "prefetch", { Mb }, 0 }, 2892 { "prefetch", { Mb }, 0 }, 2893 { "prefetch", { Mb }, 0 }, 2894 { "prefetch", { Mb }, 0 }, 2895 { "prefetch", { Mb }, 0 }, 2896 }, 2897 /* REG_0F18 */ 2898 { 2899 { MOD_TABLE (MOD_0F18_REG_0) }, 2900 { MOD_TABLE (MOD_0F18_REG_1) }, 2901 { MOD_TABLE (MOD_0F18_REG_2) }, 2902 { MOD_TABLE (MOD_0F18_REG_3) }, 2903 { MOD_TABLE (MOD_0F18_REG_4) }, 2904 { "nopQ", { Ev }, 0 }, 2905 { MOD_TABLE (MOD_0F18_REG_6) }, 2906 { MOD_TABLE (MOD_0F18_REG_7) }, 2907 }, 2908 /* REG_0F1C_P_0_MOD_0 */ 2909 { 2910 { "cldemote", { Mb }, 0 }, 2911 { "nopQ", { Ev }, 0 }, 2912 { "nopQ", { Ev }, 0 }, 2913 { "nopQ", { Ev }, 0 }, 2914 { "nopQ", { Ev }, 0 }, 2915 { "nopQ", { Ev }, 0 }, 2916 { "nopQ", { Ev }, 0 }, 2917 { "nopQ", { Ev }, 0 }, 2918 }, 2919 /* REG_0F1E_P_1_MOD_3 */ 2920 { 2921 { "nopQ", { Ev }, PREFIX_IGNORED }, 2922 { "rdsspK", { Edq }, 0 }, 2923 { "nopQ", { Ev }, PREFIX_IGNORED }, 2924 { "nopQ", { Ev }, PREFIX_IGNORED }, 2925 { "nopQ", { Ev }, PREFIX_IGNORED }, 2926 { "nopQ", { Ev }, PREFIX_IGNORED }, 2927 { "nopQ", { Ev }, PREFIX_IGNORED }, 2928 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, 2929 }, 2930 /* REG_0F38D8_PREFIX_1 */ 2931 { 2932 { "aesencwide128kl", { M }, 0 }, 2933 { "aesdecwide128kl", { M }, 0 }, 2934 { "aesencwide256kl", { M }, 0 }, 2935 { "aesdecwide256kl", { M }, 0 }, 2936 }, 2937 /* REG_0F3A0F_P_1 */ 2938 { 2939 { RM_TABLE (RM_0F3A0F_P_1_R_0) }, 2940 }, 2941 /* REG_0F71 */ 2942 { 2943 { Bad_Opcode }, 2944 { Bad_Opcode }, 2945 { "psrlw", { Nq, Ib }, PREFIX_OPCODE }, 2946 { Bad_Opcode }, 2947 { "psraw", { Nq, Ib }, PREFIX_OPCODE }, 2948 { Bad_Opcode }, 2949 { "psllw", { Nq, Ib }, PREFIX_OPCODE }, 2950 }, 2951 /* REG_0F72 */ 2952 { 2953 { Bad_Opcode }, 2954 { Bad_Opcode }, 2955 { "psrld", { Nq, Ib }, PREFIX_OPCODE }, 2956 { Bad_Opcode }, 2957 { "psrad", { Nq, Ib }, PREFIX_OPCODE }, 2958 { Bad_Opcode }, 2959 { "pslld", { Nq, Ib }, PREFIX_OPCODE }, 2960 }, 2961 /* REG_0F73 */ 2962 { 2963 { Bad_Opcode }, 2964 { Bad_Opcode }, 2965 { "psrlq", { Nq, Ib }, PREFIX_OPCODE }, 2966 { "psrldq", { Ux, Ib }, PREFIX_DATA }, 2967 { Bad_Opcode }, 2968 { Bad_Opcode }, 2969 { "psllq", { Nq, Ib }, PREFIX_OPCODE }, 2970 { "pslldq", { Ux, Ib }, PREFIX_DATA }, 2971 }, 2972 /* REG_0FA6 */ 2973 { 2974 { PREFIX_TABLE (PREFIX_0FA6_REG_0) }, 2975 { "xsha1", { { OP_0f07, 0 } }, 0 }, 2976 { "xsha256", { { OP_0f07, 0 } }, 0 }, 2977 { "xsha384", { { OP_0f07, 0 } }, 0 }, 2978 { "xsha512", { { OP_0f07, 0 } }, 0 }, 2979 { PREFIX_TABLE (PREFIX_0FA6_REG_5) }, 2980 { "montmul2", { { OP_0f07, 0 } }, 0 }, 2981 { "xmodexp", { { OP_0f07, 0 } }, 0 }, 2982 }, 2983 /* REG_0FA7 */ 2984 { 2985 { "xstore-rng", { { OP_0f07, 0 } }, 0 }, 2986 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, 2987 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, 2988 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, 2989 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, 2990 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, 2991 { PREFIX_TABLE (PREFIX_0FA7_REG_6) }, 2992 { "xrng2", { { OP_0f07, 0 } }, 0 }, 2993 }, 2994 /* REG_0FAE */ 2995 { 2996 { MOD_TABLE (MOD_0FAE_REG_0) }, 2997 { MOD_TABLE (MOD_0FAE_REG_1) }, 2998 { MOD_TABLE (MOD_0FAE_REG_2) }, 2999 { MOD_TABLE (MOD_0FAE_REG_3) }, 3000 { MOD_TABLE (MOD_0FAE_REG_4) }, 3001 { MOD_TABLE (MOD_0FAE_REG_5) }, 3002 { MOD_TABLE (MOD_0FAE_REG_6) }, 3003 { MOD_TABLE (MOD_0FAE_REG_7) }, 3004 }, 3005 /* REG_0FBA */ 3006 { 3007 { Bad_Opcode }, 3008 { Bad_Opcode }, 3009 { Bad_Opcode }, 3010 { Bad_Opcode }, 3011 { "btQ", { Ev, Ib }, 0 }, 3012 { "btsQ", { Evh1, Ib }, 0 }, 3013 { "btrQ", { Evh1, Ib }, 0 }, 3014 { "btcQ", { Evh1, Ib }, 0 }, 3015 }, 3016 /* REG_0FC7 */ 3017 { 3018 { Bad_Opcode }, 3019 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, 3020 { Bad_Opcode }, 3021 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 3022 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 3023 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 3024 { MOD_TABLE (MOD_0FC7_REG_6) }, 3025 { MOD_TABLE (MOD_0FC7_REG_7) }, 3026 }, 3027 /* REG_VEX_0F71 */ 3028 { 3029 { Bad_Opcode }, 3030 { Bad_Opcode }, 3031 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA }, 3032 { Bad_Opcode }, 3033 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA }, 3034 { Bad_Opcode }, 3035 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA }, 3036 }, 3037 /* REG_VEX_0F72 */ 3038 { 3039 { Bad_Opcode }, 3040 { Bad_Opcode }, 3041 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA }, 3042 { Bad_Opcode }, 3043 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA }, 3044 { Bad_Opcode }, 3045 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA }, 3046 }, 3047 /* REG_VEX_0F73 */ 3048 { 3049 { Bad_Opcode }, 3050 { Bad_Opcode }, 3051 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA }, 3052 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA }, 3053 { Bad_Opcode }, 3054 { Bad_Opcode }, 3055 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA }, 3056 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA }, 3057 }, 3058 /* REG_VEX_0FAE */ 3059 { 3060 { Bad_Opcode }, 3061 { Bad_Opcode }, 3062 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) }, 3063 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) }, 3064 }, 3065 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */ 3066 { 3067 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) }, 3068 }, 3069 /* REG_VEX_0F38F3_L_0_P_0 */ 3070 { 3071 { Bad_Opcode }, 3072 { "%NFblsrS", { VexGdq, Edq }, 0 }, 3073 { "%NFblsmskS", { VexGdq, Edq }, 0 }, 3074 { "%NFblsiS", { VexGdq, Edq }, 0 }, 3075 }, 3076 /* REG_VEX_MAP7_F6_L_0_W_0 */ 3077 { 3078 { X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) }, 3079 }, 3080 /* REG_VEX_MAP7_F8_L_0_W_0 */ 3081 { 3082 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) }, 3083 }, 3084 /* REG_XOP_09_01_L_0 */ 3085 { 3086 { Bad_Opcode }, 3087 { "blcfill", { VexGdq, Edq }, 0 }, 3088 { "blsfill", { VexGdq, Edq }, 0 }, 3089 { "blcs", { VexGdq, Edq }, 0 }, 3090 { "tzmsk", { VexGdq, Edq }, 0 }, 3091 { "blcic", { VexGdq, Edq }, 0 }, 3092 { "blsic", { VexGdq, Edq }, 0 }, 3093 { "t1mskc", { VexGdq, Edq }, 0 }, 3094 }, 3095 /* REG_XOP_09_02_L_0 */ 3096 { 3097 { Bad_Opcode }, 3098 { "blcmsk", { VexGdq, Edq }, 0 }, 3099 { Bad_Opcode }, 3100 { Bad_Opcode }, 3101 { Bad_Opcode }, 3102 { Bad_Opcode }, 3103 { "blci", { VexGdq, Edq }, 0 }, 3104 }, 3105 /* REG_XOP_09_12_L_0 */ 3106 { 3107 { "llwpcb", { Rdq }, 0 }, 3108 { "slwpcb", { Rdq }, 0 }, 3109 }, 3110 /* REG_XOP_0A_12_L_0 */ 3111 { 3112 { "lwpins", { VexGdq, Ed, Id }, 0 }, 3113 { "lwpval", { VexGdq, Ed, Id }, 0 }, 3114 }, 3115 3116 #include "i386-dis-evex-reg.h" 3117 }; 3118 3119 static const struct dis386 prefix_table[][4] = { 3120 /* PREFIX_90 */ 3121 { 3122 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, 3123 { "pause", { XX }, 0 }, 3124 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, 3125 { NULL, { { NULL, 0 } }, PREFIX_IGNORED } 3126 }, 3127 3128 /* PREFIX_0F00_REG_6_X86_64 */ 3129 { 3130 { Bad_Opcode }, 3131 { Bad_Opcode }, 3132 { Bad_Opcode }, 3133 { "lkgsD", { Sv }, 0 }, 3134 }, 3135 3136 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ 3137 { 3138 { "wrmsrns", { Skip_MODRM }, 0 }, 3139 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, 3140 { Bad_Opcode }, 3141 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, 3142 }, 3143 3144 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */ 3145 { 3146 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) }, 3147 }, 3148 3149 /* PREFIX_0F01_REG_1_RM_2 */ 3150 { 3151 { "clac", { Skip_MODRM }, 0 }, 3152 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) }, 3153 { Bad_Opcode }, 3154 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)}, 3155 }, 3156 3157 /* PREFIX_0F01_REG_1_RM_4 */ 3158 { 3159 { Bad_Opcode }, 3160 { Bad_Opcode }, 3161 { "tdcall", { Skip_MODRM }, 0 }, 3162 { Bad_Opcode }, 3163 }, 3164 3165 /* PREFIX_0F01_REG_1_RM_5 */ 3166 { 3167 { Bad_Opcode }, 3168 { Bad_Opcode }, 3169 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, 3170 { Bad_Opcode }, 3171 }, 3172 3173 /* PREFIX_0F01_REG_1_RM_6 */ 3174 { 3175 { Bad_Opcode }, 3176 { Bad_Opcode }, 3177 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, 3178 { Bad_Opcode }, 3179 }, 3180 3181 /* PREFIX_0F01_REG_1_RM_7 */ 3182 { 3183 { "encls", { Skip_MODRM }, 0 }, 3184 { Bad_Opcode }, 3185 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, 3186 { Bad_Opcode }, 3187 }, 3188 3189 /* PREFIX_0F01_REG_3_RM_1 */ 3190 { 3191 { "vmmcall", { Skip_MODRM }, 0 }, 3192 { "vmgexit", { Skip_MODRM }, 0 }, 3193 { Bad_Opcode }, 3194 { "vmgexit", { Skip_MODRM }, 0 }, 3195 }, 3196 3197 /* PREFIX_0F01_REG_5_MOD_0 */ 3198 { 3199 { Bad_Opcode }, 3200 { "rstorssp", { Mq }, PREFIX_OPCODE }, 3201 }, 3202 3203 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ 3204 { 3205 { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, 3206 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, 3207 { Bad_Opcode }, 3208 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, 3209 }, 3210 3211 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ 3212 { 3213 { Bad_Opcode }, 3214 { Bad_Opcode }, 3215 { Bad_Opcode }, 3216 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, 3217 }, 3218 3219 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ 3220 { 3221 { Bad_Opcode }, 3222 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, 3223 }, 3224 3225 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */ 3226 { 3227 { Bad_Opcode }, 3228 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) }, 3229 }, 3230 3231 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */ 3232 { 3233 { Bad_Opcode }, 3234 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) }, 3235 }, 3236 3237 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */ 3238 { 3239 { "rdpkru", { Skip_MODRM }, 0 }, 3240 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) }, 3241 }, 3242 3243 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */ 3244 { 3245 { "wrpkru", { Skip_MODRM }, 0 }, 3246 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) }, 3247 }, 3248 3249 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ 3250 { 3251 { "monitorx", { { OP_Monitor, 0 } }, 0 }, 3252 { "mcommit", { Skip_MODRM }, 0 }, 3253 }, 3254 3255 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */ 3256 { 3257 { "rdpru", { Skip_MODRM }, 0 }, 3258 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) }, 3259 { Bad_Opcode }, 3260 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3) }, 3261 }, 3262 3263 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ 3264 { 3265 { "invlpgb", { Skip_MODRM }, 0 }, 3266 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) }, 3267 { Bad_Opcode }, 3268 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) }, 3269 }, 3270 3271 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ 3272 { 3273 { "tlbsync", { Skip_MODRM }, 0 }, 3274 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) }, 3275 { Bad_Opcode }, 3276 { "pvalidate", { Skip_MODRM }, 0 }, 3277 }, 3278 3279 /* PREFIX_0F09 */ 3280 { 3281 { "wbinvd", { XX }, 0 }, 3282 { "wbnoinvd", { XX }, 0 }, 3283 }, 3284 3285 /* PREFIX_0F10 */ 3286 { 3287 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, 3288 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 }, 3289 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, 3290 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 }, 3291 }, 3292 3293 /* PREFIX_0F11 */ 3294 { 3295 { "%XEVmovupX", { EXxS, XM }, 0 }, 3296 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 }, 3297 { "%XEVmovupX", { EXxS, XM }, 0 }, 3298 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 }, 3299 }, 3300 3301 /* PREFIX_0F12 */ 3302 { 3303 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 3304 { "movsldup", { XM, EXx }, 0 }, 3305 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, 3306 { "movddup", { XM, EXq }, 0 }, 3307 }, 3308 3309 /* PREFIX_0F16 */ 3310 { 3311 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 3312 { "movshdup", { XM, EXx }, 0 }, 3313 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, 3314 }, 3315 3316 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */ 3317 { 3318 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 }, 3319 { "nopQ", { Ev }, 0 }, 3320 { "nopQ", { Ev }, 0 }, 3321 { "nopQ", { Ev }, 0 }, 3322 }, 3323 3324 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */ 3325 { 3326 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 }, 3327 { "nopQ", { Ev }, 0 }, 3328 { "nopQ", { Ev }, 0 }, 3329 { "nopQ", { Ev }, 0 }, 3330 }, 3331 3332 /* PREFIX_0F1A */ 3333 { 3334 { MOD_TABLE (MOD_0F1A_PREFIX_0) }, 3335 { "bndcl", { Gbnd, Ev_bnd }, 0 }, 3336 { "bndmov", { Gbnd, Ebnd }, 0 }, 3337 { "bndcu", { Gbnd, Ev_bnd }, 0 }, 3338 }, 3339 3340 /* PREFIX_0F1B */ 3341 { 3342 { MOD_TABLE (MOD_0F1B_PREFIX_0) }, 3343 { MOD_TABLE (MOD_0F1B_PREFIX_1) }, 3344 { "bndmov", { EbndS, Gbnd }, 0 }, 3345 { "bndcn", { Gbnd, Ev_bnd }, 0 }, 3346 }, 3347 3348 /* PREFIX_0F1C */ 3349 { 3350 { MOD_TABLE (MOD_0F1C_PREFIX_0) }, 3351 { "nopQ", { Ev }, PREFIX_IGNORED }, 3352 { "nopQ", { Ev }, 0 }, 3353 { "nopQ", { Ev }, PREFIX_IGNORED }, 3354 }, 3355 3356 /* PREFIX_0F1E */ 3357 { 3358 { "nopQ", { Ev }, 0 }, 3359 { MOD_TABLE (MOD_0F1E_PREFIX_1) }, 3360 { "nopQ", { Ev }, 0 }, 3361 { NULL, { XX }, PREFIX_IGNORED }, 3362 }, 3363 3364 /* PREFIX_0F2A */ 3365 { 3366 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, 3367 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, 3368 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, 3369 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, 3370 }, 3371 3372 /* PREFIX_0F2B */ 3373 { 3374 { "movntps", { Mx, XM }, 0 }, 3375 { "movntss", { Md, XM }, 0 }, 3376 { "movntpd", { Mx, XM }, 0 }, 3377 { "movntsd", { Mq, XM }, 0 }, 3378 }, 3379 3380 /* PREFIX_0F2C */ 3381 { 3382 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3383 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, 3384 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3385 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, 3386 }, 3387 3388 /* PREFIX_0F2D */ 3389 { 3390 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3391 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, 3392 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3393 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, 3394 }, 3395 3396 /* PREFIX_0F2E */ 3397 { 3398 { "VucomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, 3399 { Bad_Opcode }, 3400 { "VucomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, 3401 }, 3402 3403 /* PREFIX_0F2F */ 3404 { 3405 { "VcomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, 3406 { Bad_Opcode }, 3407 { "VcomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, 3408 }, 3409 3410 /* PREFIX_0F51 */ 3411 { 3412 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, 3413 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3414 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, 3415 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3416 }, 3417 3418 /* PREFIX_0F52 */ 3419 { 3420 { "Vrsqrtps", { XM, EXx }, 0 }, 3421 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 }, 3422 }, 3423 3424 /* PREFIX_0F53 */ 3425 { 3426 { "Vrcpps", { XM, EXx }, 0 }, 3427 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 }, 3428 }, 3429 3430 /* PREFIX_0F58 */ 3431 { 3432 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3433 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3434 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3435 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3436 }, 3437 3438 /* PREFIX_0F59 */ 3439 { 3440 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3441 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3442 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3443 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3444 }, 3445 3446 /* PREFIX_0F5A */ 3447 { 3448 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, 3449 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3450 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, 3451 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3452 }, 3453 3454 /* PREFIX_0F5B */ 3455 { 3456 { "Vcvtdq2ps", { XM, EXx }, 0 }, 3457 { "Vcvttps2dq", { XM, EXx }, 0 }, 3458 { "Vcvtps2dq", { XM, EXx }, 0 }, 3459 }, 3460 3461 /* PREFIX_0F5C */ 3462 { 3463 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3464 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3465 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3466 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3467 }, 3468 3469 /* PREFIX_0F5D */ 3470 { 3471 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3472 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3473 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3474 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, 3475 }, 3476 3477 /* PREFIX_0F5E */ 3478 { 3479 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3480 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, 3481 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, 3482 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, 3483 }, 3484 3485 /* PREFIX_0F5F */ 3486 { 3487 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3488 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, 3489 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, 3490 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, 3491 }, 3492 3493 /* PREFIX_0F60 */ 3494 { 3495 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, 3496 { Bad_Opcode }, 3497 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, 3498 }, 3499 3500 /* PREFIX_0F61 */ 3501 { 3502 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, 3503 { Bad_Opcode }, 3504 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, 3505 }, 3506 3507 /* PREFIX_0F62 */ 3508 { 3509 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, 3510 { Bad_Opcode }, 3511 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, 3512 }, 3513 3514 /* PREFIX_0F6F */ 3515 { 3516 { "movq", { MX, EM }, PREFIX_OPCODE }, 3517 { "movdqu", { XM, EXx }, PREFIX_OPCODE }, 3518 { "movdqa", { XM, EXx }, PREFIX_OPCODE }, 3519 }, 3520 3521 /* PREFIX_0F70 */ 3522 { 3523 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, 3524 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3525 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, 3526 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3527 }, 3528 3529 /* PREFIX_0F78 */ 3530 { 3531 {"vmread", { Em, Gm }, 0 }, 3532 { Bad_Opcode }, 3533 {"extrq", { Uxmm, Ib, Ib }, 0 }, 3534 {"insertq", { XM, Uxmm, Ib, Ib }, 0 }, 3535 }, 3536 3537 /* PREFIX_0F79 */ 3538 { 3539 {"vmwrite", { Gm, Em }, 0 }, 3540 { Bad_Opcode }, 3541 {"extrq", { XM, Uxmm }, 0 }, 3542 {"insertq", { XM, Uxmm }, 0 }, 3543 }, 3544 3545 /* PREFIX_0F7C */ 3546 { 3547 { Bad_Opcode }, 3548 { Bad_Opcode }, 3549 { "Vhaddpd", { XM, Vex, EXx }, 0 }, 3550 { "Vhaddps", { XM, Vex, EXx }, 0 }, 3551 }, 3552 3553 /* PREFIX_0F7D */ 3554 { 3555 { Bad_Opcode }, 3556 { Bad_Opcode }, 3557 { "Vhsubpd", { XM, Vex, EXx }, 0 }, 3558 { "Vhsubps", { XM, Vex, EXx }, 0 }, 3559 }, 3560 3561 /* PREFIX_0F7E */ 3562 { 3563 { "movK", { Edq, MX }, PREFIX_OPCODE }, 3564 { "movq", { XM, EXq }, PREFIX_OPCODE }, 3565 { "movK", { Edq, XM }, PREFIX_OPCODE }, 3566 }, 3567 3568 /* PREFIX_0F7F */ 3569 { 3570 { "movq", { EMS, MX }, PREFIX_OPCODE }, 3571 { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, 3572 { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, 3573 }, 3574 3575 /* PREFIX_0FA6_REG_0 */ 3576 { 3577 { Bad_Opcode }, 3578 { "montmul", { { MONTMUL_Fixup, 0 } }, 0}, 3579 { Bad_Opcode }, 3580 { "sm2", { Skip_MODRM }, 0 }, 3581 }, 3582 3583 /* PREFIX_0FA6_REG_5 */ 3584 { 3585 { Bad_Opcode }, 3586 { "sm3", { Skip_MODRM }, 0 }, 3587 }, 3588 3589 /* PREFIX_0FA7_REG_6 */ 3590 { 3591 { Bad_Opcode }, 3592 { "sm4", { Skip_MODRM }, 0 }, 3593 }, 3594 3595 /* PREFIX_0FAE_REG_0_MOD_3 */ 3596 { 3597 { Bad_Opcode }, 3598 { "rdfsbase", { Ev }, 0 }, 3599 }, 3600 3601 /* PREFIX_0FAE_REG_1_MOD_3 */ 3602 { 3603 { Bad_Opcode }, 3604 { "rdgsbase", { Ev }, 0 }, 3605 }, 3606 3607 /* PREFIX_0FAE_REG_2_MOD_3 */ 3608 { 3609 { Bad_Opcode }, 3610 { "wrfsbase", { Ev }, 0 }, 3611 }, 3612 3613 /* PREFIX_0FAE_REG_3_MOD_3 */ 3614 { 3615 { Bad_Opcode }, 3616 { "wrgsbase", { Ev }, 0 }, 3617 }, 3618 3619 /* PREFIX_0FAE_REG_4_MOD_0 */ 3620 { 3621 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL }, 3622 { "ptwrite{%LQ|}", { Edq }, 0 }, 3623 }, 3624 3625 /* PREFIX_0FAE_REG_4_MOD_3 */ 3626 { 3627 { Bad_Opcode }, 3628 { "ptwrite{%LQ|}", { Edq }, 0 }, 3629 }, 3630 3631 /* PREFIX_0FAE_REG_5_MOD_3 */ 3632 { 3633 { "lfence", { Skip_MODRM }, 0 }, 3634 { "incsspK", { Edq }, PREFIX_OPCODE }, 3635 }, 3636 3637 /* PREFIX_0FAE_REG_6_MOD_0 */ 3638 { 3639 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, 3640 { "clrssbsy", { Mq }, PREFIX_OPCODE }, 3641 { "clwb", { Mb }, PREFIX_OPCODE }, 3642 }, 3643 3644 /* PREFIX_0FAE_REG_6_MOD_3 */ 3645 { 3646 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, 3647 { "umonitor", { Eva }, PREFIX_OPCODE }, 3648 { "tpause", { Edq }, PREFIX_OPCODE }, 3649 { "umwait", { Edq }, PREFIX_OPCODE }, 3650 }, 3651 3652 /* PREFIX_0FAE_REG_7_MOD_0 */ 3653 { 3654 { "clflush", { Mb }, 0 }, 3655 { Bad_Opcode }, 3656 { "clflushopt", { Mb }, 0 }, 3657 }, 3658 3659 /* PREFIX_0FB8 */ 3660 { 3661 { Bad_Opcode }, 3662 { "popcntS", { Gv, Ev }, 0 }, 3663 }, 3664 3665 /* PREFIX_0FBC */ 3666 { 3667 { "bsfS", { Gv, Ev }, 0 }, 3668 { "tzcntS", { Gv, Ev }, 0 }, 3669 { "bsfS", { Gv, Ev }, 0 }, 3670 }, 3671 3672 /* PREFIX_0FBD */ 3673 { 3674 { "bsrS", { Gv, Ev }, 0 }, 3675 { "lzcntS", { Gv, Ev }, 0 }, 3676 { "bsrS", { Gv, Ev }, 0 }, 3677 }, 3678 3679 /* PREFIX_0FC2 */ 3680 { 3681 { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, 3682 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 }, 3683 { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, 3684 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 }, 3685 }, 3686 3687 /* PREFIX_0FC7_REG_6_MOD_0 */ 3688 { 3689 { "vmptrld",{ Mq }, 0 }, 3690 { "vmxon", { Mq }, 0 }, 3691 { "vmclear",{ Mq }, 0 }, 3692 }, 3693 3694 /* PREFIX_0FC7_REG_6_MOD_3 */ 3695 { 3696 { "rdrand", { Ev }, 0 }, 3697 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) }, 3698 { "rdrand", { Ev }, 0 } 3699 }, 3700 3701 /* PREFIX_0FC7_REG_7_MOD_3 */ 3702 { 3703 { "rdseed", { Ev }, 0 }, 3704 { "rdpid", { Em }, 0 }, 3705 { "rdseed", { Ev }, 0 }, 3706 }, 3707 3708 /* PREFIX_0FD0 */ 3709 { 3710 { Bad_Opcode }, 3711 { Bad_Opcode }, 3712 { "VaddsubpX", { XM, Vex, EXx }, 0 }, 3713 { "VaddsubpX", { XM, Vex, EXx }, 0 }, 3714 }, 3715 3716 /* PREFIX_0FD6 */ 3717 { 3718 { Bad_Opcode }, 3719 { "movq2dq",{ XM, Nq }, 0 }, 3720 { "movq", { EXqS, XM }, 0 }, 3721 { "movdq2q",{ MX, Ux }, 0 }, 3722 }, 3723 3724 /* PREFIX_0FE6 */ 3725 { 3726 { Bad_Opcode }, 3727 { "Vcvtdq2pd", { XM, EXxmmq }, 0 }, 3728 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 }, 3729 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 }, 3730 }, 3731 3732 /* PREFIX_0FE7 */ 3733 { 3734 { "movntq", { Mq, MX }, 0 }, 3735 { Bad_Opcode }, 3736 { "movntdq", { Mx, XM }, 0 }, 3737 }, 3738 3739 /* PREFIX_0FF0 */ 3740 { 3741 { Bad_Opcode }, 3742 { Bad_Opcode }, 3743 { Bad_Opcode }, 3744 { "Vlddqu", { XM, M }, 0 }, 3745 }, 3746 3747 /* PREFIX_0FF7 */ 3748 { 3749 { "maskmovq", { MX, Nq }, PREFIX_OPCODE }, 3750 { Bad_Opcode }, 3751 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE }, 3752 }, 3753 3754 /* PREFIX_0F38D8 */ 3755 { 3756 { Bad_Opcode }, 3757 { REG_TABLE (REG_0F38D8_PREFIX_1) }, 3758 }, 3759 3760 /* PREFIX_0F38DC */ 3761 { 3762 { Bad_Opcode }, 3763 { MOD_TABLE (MOD_0F38DC_PREFIX_1) }, 3764 { "aesenc", { XM, EXx }, 0 }, 3765 }, 3766 3767 /* PREFIX_0F38DD */ 3768 { 3769 { Bad_Opcode }, 3770 { "aesdec128kl", { XM, M }, 0 }, 3771 { "aesenclast", { XM, EXx }, 0 }, 3772 }, 3773 3774 /* PREFIX_0F38DE */ 3775 { 3776 { Bad_Opcode }, 3777 { "aesenc256kl", { XM, M }, 0 }, 3778 { "aesdec", { XM, EXx }, 0 }, 3779 }, 3780 3781 /* PREFIX_0F38DF */ 3782 { 3783 { Bad_Opcode }, 3784 { "aesdec256kl", { XM, M }, 0 }, 3785 { "aesdeclast", { XM, EXx }, 0 }, 3786 }, 3787 3788 /* PREFIX_0F38F0 */ 3789 { 3790 { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, 3791 { Bad_Opcode }, 3792 { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, 3793 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, 3794 }, 3795 3796 /* PREFIX_0F38F1 */ 3797 { 3798 { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, 3799 { Bad_Opcode }, 3800 { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, 3801 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, 3802 }, 3803 3804 /* PREFIX_0F38F6 */ 3805 { 3806 { "wrssK", { M, Gdq }, 0 }, 3807 { "adoxL", { VexGdq, Gdq, Edq }, 0 }, 3808 { "adcxL", { VexGdq, Gdq, Edq }, 0 }, 3809 { Bad_Opcode }, 3810 }, 3811 3812 /* PREFIX_0F38F8_M_0 */ 3813 { 3814 { Bad_Opcode }, 3815 { "enqcmds", { Gva, M }, 0 }, 3816 { "movdir64b", { Gva, M }, 0 }, 3817 { "enqcmd", { Gva, M }, 0 }, 3818 }, 3819 3820 /* PREFIX_0F38F8_M_1_X86_64 */ 3821 { 3822 { Bad_Opcode }, 3823 { "uwrmsr", { Gq, Rq }, 0 }, 3824 { Bad_Opcode }, 3825 { "urdmsr", { Rq, Gq }, 0 }, 3826 }, 3827 3828 /* PREFIX_0F38FA */ 3829 { 3830 { Bad_Opcode }, 3831 { "encodekey128", { Gd, Rd }, 0 }, 3832 }, 3833 3834 /* PREFIX_0F38FB */ 3835 { 3836 { Bad_Opcode }, 3837 { "encodekey256", { Gd, Rd }, 0 }, 3838 }, 3839 3840 /* PREFIX_0F38FC */ 3841 { 3842 { "aadd", { Mdq, Gdq }, 0 }, 3843 { "axor", { Mdq, Gdq }, 0 }, 3844 { "aand", { Mdq, Gdq }, 0 }, 3845 { "aor", { Mdq, Gdq }, 0 }, 3846 }, 3847 3848 /* PREFIX_0F3A0F */ 3849 { 3850 { Bad_Opcode }, 3851 { REG_TABLE (REG_0F3A0F_P_1) }, 3852 }, 3853 3854 /* PREFIX_VEX_0F12 */ 3855 { 3856 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) }, 3857 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 }, 3858 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, 3859 { "%XEvmov%XDdup", { XM, EXymmq }, 0 }, 3860 }, 3861 3862 /* PREFIX_VEX_0F16 */ 3863 { 3864 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) }, 3865 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 }, 3866 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, 3867 }, 3868 3869 /* PREFIX_VEX_0F2A */ 3870 { 3871 { Bad_Opcode }, 3872 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 }, 3873 { Bad_Opcode }, 3874 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, 3875 }, 3876 3877 /* PREFIX_VEX_0F2C */ 3878 { 3879 { Bad_Opcode }, 3880 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 }, 3881 { Bad_Opcode }, 3882 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 }, 3883 }, 3884 3885 /* PREFIX_VEX_0F2D */ 3886 { 3887 { Bad_Opcode }, 3888 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 }, 3889 { Bad_Opcode }, 3890 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 }, 3891 }, 3892 3893 /* PREFIX_VEX_0F41_L_1_W_0 */ 3894 { 3895 { "kandw", { MaskG, MaskVex, MaskR }, 0 }, 3896 { Bad_Opcode }, 3897 { "kandb", { MaskG, MaskVex, MaskR }, 0 }, 3898 }, 3899 3900 /* PREFIX_VEX_0F41_L_1_W_1 */ 3901 { 3902 { "kandq", { MaskG, MaskVex, MaskR }, 0 }, 3903 { Bad_Opcode }, 3904 { "kandd", { MaskG, MaskVex, MaskR }, 0 }, 3905 }, 3906 3907 /* PREFIX_VEX_0F42_L_1_W_0 */ 3908 { 3909 { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, 3910 { Bad_Opcode }, 3911 { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, 3912 }, 3913 3914 /* PREFIX_VEX_0F42_L_1_W_1 */ 3915 { 3916 { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, 3917 { Bad_Opcode }, 3918 { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, 3919 }, 3920 3921 /* PREFIX_VEX_0F44_L_0_W_0 */ 3922 { 3923 { "knotw", { MaskG, MaskR }, 0 }, 3924 { Bad_Opcode }, 3925 { "knotb", { MaskG, MaskR }, 0 }, 3926 }, 3927 3928 /* PREFIX_VEX_0F44_L_0_W_1 */ 3929 { 3930 { "knotq", { MaskG, MaskR }, 0 }, 3931 { Bad_Opcode }, 3932 { "knotd", { MaskG, MaskR }, 0 }, 3933 }, 3934 3935 /* PREFIX_VEX_0F45_L_1_W_0 */ 3936 { 3937 { "korw", { MaskG, MaskVex, MaskR }, 0 }, 3938 { Bad_Opcode }, 3939 { "korb", { MaskG, MaskVex, MaskR }, 0 }, 3940 }, 3941 3942 /* PREFIX_VEX_0F45_L_1_W_1 */ 3943 { 3944 { "korq", { MaskG, MaskVex, MaskR }, 0 }, 3945 { Bad_Opcode }, 3946 { "kord", { MaskG, MaskVex, MaskR }, 0 }, 3947 }, 3948 3949 /* PREFIX_VEX_0F46_L_1_W_0 */ 3950 { 3951 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, 3952 { Bad_Opcode }, 3953 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, 3954 }, 3955 3956 /* PREFIX_VEX_0F46_L_1_W_1 */ 3957 { 3958 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, 3959 { Bad_Opcode }, 3960 { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, 3961 }, 3962 3963 /* PREFIX_VEX_0F47_L_1_W_0 */ 3964 { 3965 { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, 3966 { Bad_Opcode }, 3967 { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, 3968 }, 3969 3970 /* PREFIX_VEX_0F47_L_1_W_1 */ 3971 { 3972 { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, 3973 { Bad_Opcode }, 3974 { "kxord", { MaskG, MaskVex, MaskR }, 0 }, 3975 }, 3976 3977 /* PREFIX_VEX_0F4A_L_1_W_0 */ 3978 { 3979 { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, 3980 { Bad_Opcode }, 3981 { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, 3982 }, 3983 3984 /* PREFIX_VEX_0F4A_L_1_W_1 */ 3985 { 3986 { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, 3987 { Bad_Opcode }, 3988 { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, 3989 }, 3990 3991 /* PREFIX_VEX_0F4B_L_1_W_0 */ 3992 { 3993 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, 3994 { Bad_Opcode }, 3995 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, 3996 }, 3997 3998 /* PREFIX_VEX_0F4B_L_1_W_1 */ 3999 { 4000 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, 4001 }, 4002 4003 /* PREFIX_VEX_0F6F */ 4004 { 4005 { Bad_Opcode }, 4006 { "vmovdqu", { XM, EXx }, 0 }, 4007 { "vmovdqa", { XM, EXx }, 0 }, 4008 }, 4009 4010 /* PREFIX_VEX_0F70 */ 4011 { 4012 { Bad_Opcode }, 4013 { "vpshufhw", { XM, EXx, Ib }, 0 }, 4014 { "vpshufd", { XM, EXx, Ib }, 0 }, 4015 { "vpshuflw", { XM, EXx, Ib }, 0 }, 4016 }, 4017 4018 /* PREFIX_VEX_0F7E */ 4019 { 4020 { Bad_Opcode }, 4021 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, 4022 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, 4023 }, 4024 4025 /* PREFIX_VEX_0F7F */ 4026 { 4027 { Bad_Opcode }, 4028 { "vmovdqu", { EXxS, XM }, 0 }, 4029 { "vmovdqa", { EXxS, XM }, 0 }, 4030 }, 4031 4032 /* PREFIX_VEX_0F90_L_0_W_0 */ 4033 { 4034 { "%XEkmovw", { MaskG, MaskE }, 0 }, 4035 { Bad_Opcode }, 4036 { "%XEkmovb", { MaskG, MaskBDE }, 0 }, 4037 }, 4038 4039 /* PREFIX_VEX_0F90_L_0_W_1 */ 4040 { 4041 { "%XEkmovq", { MaskG, MaskE }, 0 }, 4042 { Bad_Opcode }, 4043 { "%XEkmovd", { MaskG, MaskBDE }, 0 }, 4044 }, 4045 4046 /* PREFIX_VEX_0F91_L_0_W_0 */ 4047 { 4048 { "%XEkmovw", { Mw, MaskG }, 0 }, 4049 { Bad_Opcode }, 4050 { "%XEkmovb", { Mb, MaskG }, 0 }, 4051 }, 4052 4053 /* PREFIX_VEX_0F91_L_0_W_1 */ 4054 { 4055 { "%XEkmovq", { Mq, MaskG }, 0 }, 4056 { Bad_Opcode }, 4057 { "%XEkmovd", { Md, MaskG }, 0 }, 4058 }, 4059 4060 /* PREFIX_VEX_0F92_L_0_W_0 */ 4061 { 4062 { "%XEkmovw", { MaskG, Rdq }, 0 }, 4063 { Bad_Opcode }, 4064 { "%XEkmovb", { MaskG, Rdq }, 0 }, 4065 { "%XEkmovd", { MaskG, Rdq }, 0 }, 4066 }, 4067 4068 /* PREFIX_VEX_0F92_L_0_W_1 */ 4069 { 4070 { Bad_Opcode }, 4071 { Bad_Opcode }, 4072 { Bad_Opcode }, 4073 { "%XEkmovK", { MaskG, Rdq }, 0 }, 4074 }, 4075 4076 /* PREFIX_VEX_0F93_L_0_W_0 */ 4077 { 4078 { "%XEkmovw", { Gdq, MaskR }, 0 }, 4079 { Bad_Opcode }, 4080 { "%XEkmovb", { Gdq, MaskR }, 0 }, 4081 { "%XEkmovd", { Gdq, MaskR }, 0 }, 4082 }, 4083 4084 /* PREFIX_VEX_0F93_L_0_W_1 */ 4085 { 4086 { Bad_Opcode }, 4087 { Bad_Opcode }, 4088 { Bad_Opcode }, 4089 { "%XEkmovK", { Gdq, MaskR }, 0 }, 4090 }, 4091 4092 /* PREFIX_VEX_0F98_L_0_W_0 */ 4093 { 4094 { "kortestw", { MaskG, MaskR }, 0 }, 4095 { Bad_Opcode }, 4096 { "kortestb", { MaskG, MaskR }, 0 }, 4097 }, 4098 4099 /* PREFIX_VEX_0F98_L_0_W_1 */ 4100 { 4101 { "kortestq", { MaskG, MaskR }, 0 }, 4102 { Bad_Opcode }, 4103 { "kortestd", { MaskG, MaskR }, 0 }, 4104 }, 4105 4106 /* PREFIX_VEX_0F99_L_0_W_0 */ 4107 { 4108 { "ktestw", { MaskG, MaskR }, 0 }, 4109 { Bad_Opcode }, 4110 { "ktestb", { MaskG, MaskR }, 0 }, 4111 }, 4112 4113 /* PREFIX_VEX_0F99_L_0_W_1 */ 4114 { 4115 { "ktestq", { MaskG, MaskR }, 0 }, 4116 { Bad_Opcode }, 4117 { "ktestd", { MaskG, MaskR }, 0 }, 4118 }, 4119 4120 /* PREFIX_VEX_0F3848_X86_64_L_0_W_0 */ 4121 { 4122 { "ttmmultf32ps", { TMM, Rtmm, VexTmm }, 0 }, 4123 { Bad_Opcode }, 4124 { "tmmultf32ps", { TMM, Rtmm, VexTmm }, 0 }, 4125 }, 4126 4127 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */ 4128 { 4129 { "ldtilecfg", { M }, 0 }, 4130 { Bad_Opcode }, 4131 { "sttilecfg", { M }, 0 }, 4132 }, 4133 4134 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */ 4135 { 4136 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) }, 4137 { Bad_Opcode }, 4138 { Bad_Opcode }, 4139 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) }, 4140 }, 4141 4142 /* PREFIX_VEX_0F384A_X86_64_W_0_L_0 */ 4143 { 4144 { Bad_Opcode }, 4145 { Bad_Opcode }, 4146 { "tileloaddrst1", { TMM, MVexSIBMEM }, 0 }, 4147 { "tileloaddrs", { TMM, MVexSIBMEM }, 0 }, 4148 }, 4149 4150 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */ 4151 { 4152 { Bad_Opcode }, 4153 { "tilestored", { MVexSIBMEM, TMM }, 0 }, 4154 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, 4155 { "tileloadd", { TMM, MVexSIBMEM }, 0 }, 4156 }, 4157 4158 /* PREFIX_VEX_0F3850_W_0 */ 4159 { 4160 { "%XEvpdpbuud", { XM, Vex, EXx }, 0 }, 4161 { "%XEvpdpbsud", { XM, Vex, EXx }, 0 }, 4162 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 }, 4163 { "%XEvpdpbssd", { XM, Vex, EXx }, 0 }, 4164 }, 4165 4166 /* PREFIX_VEX_0F3851_W_0 */ 4167 { 4168 { "%XEvpdpbuuds", { XM, Vex, EXx }, 0 }, 4169 { "%XEvpdpbsuds", { XM, Vex, EXx }, 0 }, 4170 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 }, 4171 { "%XEvpdpbssds", { XM, Vex, EXx }, 0 }, 4172 }, 4173 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */ 4174 { 4175 { Bad_Opcode }, 4176 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 }, 4177 { Bad_Opcode }, 4178 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4179 }, 4180 4181 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */ 4182 { 4183 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 }, 4184 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 }, 4185 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 }, 4186 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 }, 4187 }, 4188 4189 /* PREFIX_VEX_0F385F_X86_64_L_0_W_0 */ 4190 { 4191 { Bad_Opcode }, 4192 { "ttransposed", { TMM, Rtmm }, 0 }, 4193 }, 4194 4195 /* PREFIX_VEX_0F386B_X86_64_L_0_W_0 */ 4196 { 4197 { "tconjtcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4198 { "ttcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4199 { "tconjtfp16", { TMM, Rtmm }, 0 }, 4200 { "ttcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4201 }, 4202 4203 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */ 4204 { 4205 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4206 { "ttdpbf16ps", { TMM, Rtmm, VexTmm }, 0 }, 4207 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4208 { "ttdpfp16ps", { TMM, Rtmm, VexTmm }, 0 }, 4209 }, 4210 4211 /* PREFIX_VEX_0F386E_X86_64_L_0_W_0 */ 4212 { 4213 { "t2rpntlvwz0", { TMM, MVexSIBMEM }, 0 }, 4214 { Bad_Opcode }, 4215 { "t2rpntlvwz1", { TMM, MVexSIBMEM }, 0 }, 4216 }, 4217 4218 /* PREFIX_VEX_0F386F_X86_64_L_0_W_0 */ 4219 { 4220 { "t2rpntlvwz0t1", { TMM, MVexSIBMEM }, 0 }, 4221 { Bad_Opcode }, 4222 { "t2rpntlvwz1t1", { TMM, MVexSIBMEM }, 0 }, 4223 }, 4224 4225 /* PREFIX_VEX_0F3872 */ 4226 { 4227 { Bad_Opcode }, 4228 { VEX_W_TABLE (VEX_W_0F3872_P_1) }, 4229 }, 4230 4231 /* PREFIX_VEX_0F38B0_W_0 */ 4232 { 4233 { "vcvtneoph2ps", { XM, Mx }, 0 }, 4234 { "vcvtneebf162ps", { XM, Mx }, 0 }, 4235 { "vcvtneeph2ps", { XM, Mx }, 0 }, 4236 { "vcvtneobf162ps", { XM, Mx }, 0 }, 4237 }, 4238 4239 /* PREFIX_VEX_0F38B1_W_0 */ 4240 { 4241 { Bad_Opcode }, 4242 { "vbcstnebf162ps", { XM, Mw }, 0 }, 4243 { "vbcstnesh2ps", { XM, Mw }, 0 }, 4244 }, 4245 4246 /* PREFIX_VEX_0F38D2_W_0 */ 4247 { 4248 { "%XEvpdpwuud", { XM, Vex, EXx }, 0 }, 4249 { "%XEvpdpwsud", { XM, Vex, EXx }, 0 }, 4250 { "%XEvpdpwusd", { XM, Vex, EXx }, 0 }, 4251 }, 4252 4253 /* PREFIX_VEX_0F38D3_W_0 */ 4254 { 4255 { "%XEvpdpwuuds", { XM, Vex, EXx }, 0 }, 4256 { "%XEvpdpwsuds", { XM, Vex, EXx }, 0 }, 4257 { "%XEvpdpwusds", { XM, Vex, EXx }, 0 }, 4258 }, 4259 4260 /* PREFIX_VEX_0F38CB */ 4261 { 4262 { Bad_Opcode }, 4263 { Bad_Opcode }, 4264 { Bad_Opcode }, 4265 { VEX_W_TABLE (VEX_W_0F38CB_P_3) }, 4266 }, 4267 4268 /* PREFIX_VEX_0F38CC */ 4269 { 4270 { Bad_Opcode }, 4271 { Bad_Opcode }, 4272 { Bad_Opcode }, 4273 { VEX_W_TABLE (VEX_W_0F38CC_P_3) }, 4274 }, 4275 4276 /* PREFIX_VEX_0F38CD */ 4277 { 4278 { Bad_Opcode }, 4279 { Bad_Opcode }, 4280 { Bad_Opcode }, 4281 { VEX_W_TABLE (VEX_W_0F38CD_P_3) }, 4282 }, 4283 4284 /* PREFIX_VEX_0F38DA_W_0 */ 4285 { 4286 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) }, 4287 { "%XEvsm4key4", { XM, Vex, EXx }, 0 }, 4288 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) }, 4289 { "%XEvsm4rnds4", { XM, Vex, EXx }, 0 }, 4290 }, 4291 4292 /* PREFIX_VEX_0F38F2_L_0 */ 4293 { 4294 { "%NFandnS", { Gdq, VexGdq, Edq }, 0 }, 4295 }, 4296 4297 /* PREFIX_VEX_0F38F3_L_0 */ 4298 { 4299 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) }, 4300 }, 4301 4302 /* PREFIX_VEX_0F38F5_L_0 */ 4303 { 4304 { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 }, 4305 { "%XEpextS", { Gdq, VexGdq, Edq }, 0 }, 4306 { Bad_Opcode }, 4307 { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 }, 4308 }, 4309 4310 /* PREFIX_VEX_0F38F6_L_0 */ 4311 { 4312 { Bad_Opcode }, 4313 { Bad_Opcode }, 4314 { Bad_Opcode }, 4315 { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 }, 4316 }, 4317 4318 /* PREFIX_VEX_0F38F7_L_0 */ 4319 { 4320 { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 }, 4321 { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 }, 4322 { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 }, 4323 { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 }, 4324 }, 4325 4326 /* PREFIX_VEX_0F3AF0_L_0 */ 4327 { 4328 { Bad_Opcode }, 4329 { Bad_Opcode }, 4330 { Bad_Opcode }, 4331 { "%XErorxS", { Gdq, Edq, Ib }, 0 }, 4332 }, 4333 4334 /* PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0 */ 4335 { 4336 { "t2rpntlvwz0rs", { TMM, MVexSIBMEM }, 0 }, 4337 { Bad_Opcode }, 4338 { "t2rpntlvwz1rs", { TMM, MVexSIBMEM }, 0 }, 4339 }, 4340 4341 /* PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0 */ 4342 { 4343 { "t2rpntlvwz0rst1", { TMM, MVexSIBMEM }, 0 }, 4344 { Bad_Opcode }, 4345 { "t2rpntlvwz1rst1", { TMM, MVexSIBMEM }, 0 }, 4346 }, 4347 4348 /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */ 4349 { 4350 { "tdpbf8ps", { TMM, Rtmm, VexTmm }, 0 }, 4351 { "tdphbf8ps", { TMM, Rtmm, VexTmm }, 0 }, 4352 { "tdphf8ps", { TMM, Rtmm, VexTmm }, 0 }, 4353 { "tdpbhf8ps", { TMM, Rtmm, VexTmm }, 0 }, 4354 }, 4355 4356 /* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */ 4357 { 4358 { Bad_Opcode }, 4359 { "wrmsrns", { Skip_MODRM, Id, Rq }, 0 }, 4360 { Bad_Opcode }, 4361 { "rdmsr", { Rq, Id }, 0 }, 4362 }, 4363 4364 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */ 4365 { 4366 { Bad_Opcode }, 4367 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 }, 4368 { Bad_Opcode }, 4369 { "urdmsr", { Rq, Id }, 0 }, 4370 }, 4371 4372 #include "i386-dis-evex-prefix.h" 4373 }; 4374 4375 static const struct dis386 x86_64_table[][2] = { 4376 /* X86_64_06 */ 4377 { 4378 { "pushP", { es }, 0 }, 4379 }, 4380 4381 /* X86_64_07 */ 4382 { 4383 { "popP", { es }, 0 }, 4384 }, 4385 4386 /* X86_64_0E */ 4387 { 4388 { "pushP", { cs }, 0 }, 4389 }, 4390 4391 /* X86_64_16 */ 4392 { 4393 { "pushP", { ss }, 0 }, 4394 }, 4395 4396 /* X86_64_17 */ 4397 { 4398 { "popP", { ss }, 0 }, 4399 }, 4400 4401 /* X86_64_1E */ 4402 { 4403 { "pushP", { ds }, 0 }, 4404 }, 4405 4406 /* X86_64_1F */ 4407 { 4408 { "popP", { ds }, 0 }, 4409 }, 4410 4411 /* X86_64_27 */ 4412 { 4413 { "daa", { XX }, 0 }, 4414 }, 4415 4416 /* X86_64_2F */ 4417 { 4418 { "das", { XX }, 0 }, 4419 }, 4420 4421 /* X86_64_37 */ 4422 { 4423 { "aaa", { XX }, 0 }, 4424 }, 4425 4426 /* X86_64_3F */ 4427 { 4428 { "aas", { XX }, 0 }, 4429 }, 4430 4431 /* X86_64_60 */ 4432 { 4433 { "pushaP", { XX }, 0 }, 4434 }, 4435 4436 /* X86_64_61 */ 4437 { 4438 { "popaP", { XX }, 0 }, 4439 }, 4440 4441 /* X86_64_62 */ 4442 { 4443 { MOD_TABLE (MOD_62_32BIT) }, 4444 { EVEX_TABLE () }, 4445 }, 4446 4447 /* X86_64_63 */ 4448 { 4449 { "arplS", { Sv, Gv }, 0 }, 4450 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 }, 4451 }, 4452 4453 /* X86_64_6D */ 4454 { 4455 { "ins{R|}", { Yzr, indirDX }, 0 }, 4456 { "ins{G|}", { Yzr, indirDX }, 0 }, 4457 }, 4458 4459 /* X86_64_6F */ 4460 { 4461 { "outs{R|}", { indirDXr, Xz }, 0 }, 4462 { "outs{G|}", { indirDXr, Xz }, 0 }, 4463 }, 4464 4465 /* X86_64_82 */ 4466 { 4467 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ 4468 { REG_TABLE (REG_80) }, 4469 }, 4470 4471 /* X86_64_9A */ 4472 { 4473 { "{l|}call{P|}", { Ap }, 0 }, 4474 }, 4475 4476 /* X86_64_C2 */ 4477 { 4478 { "retP", { Iw, BND }, 0 }, 4479 { "ret@", { Iw, BND }, 0 }, 4480 }, 4481 4482 /* X86_64_C3 */ 4483 { 4484 { "retP", { BND }, 0 }, 4485 { "ret@", { BND }, 0 }, 4486 }, 4487 4488 /* X86_64_C4 */ 4489 { 4490 { MOD_TABLE (MOD_C4_32BIT) }, 4491 { VEX_C4_TABLE () }, 4492 }, 4493 4494 /* X86_64_C5 */ 4495 { 4496 { MOD_TABLE (MOD_C5_32BIT) }, 4497 { VEX_C5_TABLE () }, 4498 }, 4499 4500 /* X86_64_CE */ 4501 { 4502 { "into", { XX }, 0 }, 4503 }, 4504 4505 /* X86_64_D4 */ 4506 { 4507 { "aam", { Ib }, 0 }, 4508 }, 4509 4510 /* X86_64_D5 */ 4511 { 4512 { "aad", { Ib }, 0 }, 4513 }, 4514 4515 /* X86_64_D6 */ 4516 { 4517 { Bad_Opcode }, 4518 { "udb", { XX }, 0 }, 4519 }, 4520 4521 /* X86_64_E8 */ 4522 { 4523 { "callP", { Jv, BND }, 0 }, 4524 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL } 4525 }, 4526 4527 /* X86_64_E9 */ 4528 { 4529 { "jmpP", { Jv, BND }, 0 }, 4530 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL } 4531 }, 4532 4533 /* X86_64_EA */ 4534 { 4535 { "{l|}jmp{P|}", { Ap }, 0 }, 4536 }, 4537 4538 /* X86_64_0F00_REG_6 */ 4539 { 4540 { Bad_Opcode }, 4541 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) }, 4542 }, 4543 4544 /* X86_64_0F01_REG_0 */ 4545 { 4546 { "sgdt{Q|Q}", { M }, 0 }, 4547 { "sgdt", { M }, 0 }, 4548 }, 4549 4550 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ 4551 { 4552 { Bad_Opcode }, 4553 { "wrmsrlist", { Skip_MODRM }, 0 }, 4554 }, 4555 4556 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ 4557 { 4558 { Bad_Opcode }, 4559 { "rdmsrlist", { Skip_MODRM }, 0 }, 4560 }, 4561 4562 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */ 4563 { 4564 { Bad_Opcode }, 4565 { "pbndkb", { Skip_MODRM }, 0 }, 4566 }, 4567 4568 /* X86_64_0F01_REG_1 */ 4569 { 4570 { "sidt{Q|Q}", { M }, 0 }, 4571 { "sidt", { M }, 0 }, 4572 }, 4573 4574 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */ 4575 { 4576 { Bad_Opcode }, 4577 { "eretu", { Skip_MODRM }, 0 }, 4578 }, 4579 4580 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */ 4581 { 4582 { Bad_Opcode }, 4583 { "erets", { Skip_MODRM }, 0 }, 4584 }, 4585 4586 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ 4587 { 4588 { Bad_Opcode }, 4589 { "seamret", { Skip_MODRM }, 0 }, 4590 }, 4591 4592 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ 4593 { 4594 { Bad_Opcode }, 4595 { "seamops", { Skip_MODRM }, 0 }, 4596 }, 4597 4598 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ 4599 { 4600 { Bad_Opcode }, 4601 { "seamcall", { Skip_MODRM }, 0 }, 4602 }, 4603 4604 /* X86_64_0F01_REG_2 */ 4605 { 4606 { "lgdt{Q|Q}", { M }, 0 }, 4607 { "lgdt", { M }, 0 }, 4608 }, 4609 4610 /* X86_64_0F01_REG_3 */ 4611 { 4612 { "lidt{Q|Q}", { M }, 0 }, 4613 { "lidt", { M }, 0 }, 4614 }, 4615 4616 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */ 4617 { 4618 { Bad_Opcode }, 4619 { "uiret", { Skip_MODRM }, 0 }, 4620 }, 4621 4622 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */ 4623 { 4624 { Bad_Opcode }, 4625 { "testui", { Skip_MODRM }, 0 }, 4626 }, 4627 4628 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */ 4629 { 4630 { Bad_Opcode }, 4631 { "clui", { Skip_MODRM }, 0 }, 4632 }, 4633 4634 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */ 4635 { 4636 { Bad_Opcode }, 4637 { "stui", { Skip_MODRM }, 0 }, 4638 }, 4639 4640 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */ 4641 { 4642 { Bad_Opcode }, 4643 { "rmpquery", { Skip_MODRM }, 0 }, 4644 }, 4645 4646 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ 4647 { 4648 { Bad_Opcode }, 4649 { "rmpread", { DSCX, RMrAX, Skip_MODRM }, 0 }, 4650 }, 4651 4652 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ 4653 { 4654 { Bad_Opcode }, 4655 { "rmpadjust", { Skip_MODRM }, 0 }, 4656 }, 4657 4658 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ 4659 { 4660 { Bad_Opcode }, 4661 { "rmpupdate", { RMrAX, DSCX, Skip_MODRM }, 0 }, 4662 }, 4663 4664 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ 4665 { 4666 { Bad_Opcode }, 4667 { "psmash", { Skip_MODRM }, 0 }, 4668 }, 4669 4670 /* X86_64_0F18_REG_6_MOD_0 */ 4671 { 4672 { "nopQ", { Ev }, 0 }, 4673 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) }, 4674 }, 4675 4676 /* X86_64_0F18_REG_7_MOD_0 */ 4677 { 4678 { "nopQ", { Ev }, 0 }, 4679 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) }, 4680 }, 4681 4682 { 4683 /* X86_64_0F24 */ 4684 { "movZ", { Em, Td }, 0 }, 4685 }, 4686 4687 { 4688 /* X86_64_0F26 */ 4689 { "movZ", { Td, Em }, 0 }, 4690 }, 4691 4692 { 4693 /* X86_64_0F388A */ 4694 { Bad_Opcode }, 4695 { "movrsB", { Gb, Mb }, PREFIX_OPCODE }, 4696 }, 4697 4698 { 4699 /* X86_64_0F388B */ 4700 { Bad_Opcode }, 4701 { "movrsS", { Gv, Mv }, PREFIX_OPCODE }, 4702 }, 4703 4704 { 4705 /* X86_64_0F38F8_M_1 */ 4706 { Bad_Opcode }, 4707 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) }, 4708 }, 4709 4710 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ 4711 { 4712 { Bad_Opcode }, 4713 { "senduipi", { Eq }, 0 }, 4714 }, 4715 4716 /* X86_64_VEX_0F3848 */ 4717 { 4718 { Bad_Opcode }, 4719 { VEX_LEN_TABLE (VEX_LEN_0F3848_X86_64) }, 4720 }, 4721 4722 /* X86_64_VEX_0F3849 */ 4723 { 4724 { Bad_Opcode }, 4725 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, 4726 }, 4727 4728 /* X86_64_VEX_0F384A */ 4729 { 4730 { Bad_Opcode }, 4731 { VEX_W_TABLE (VEX_W_0F384A_X86_64) }, 4732 }, 4733 4734 /* X86_64_VEX_0F384B */ 4735 { 4736 { Bad_Opcode }, 4737 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) }, 4738 }, 4739 4740 /* X86_64_VEX_0F385C */ 4741 { 4742 { Bad_Opcode }, 4743 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) }, 4744 }, 4745 4746 /* X86_64_VEX_0F385E */ 4747 { 4748 { Bad_Opcode }, 4749 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) }, 4750 }, 4751 4752 /* X86_64_VEX_0F385F */ 4753 { 4754 { Bad_Opcode }, 4755 { VEX_LEN_TABLE (VEX_LEN_0F385F_X86_64) }, 4756 }, 4757 4758 /* X86_64_VEX_0F386B */ 4759 { 4760 { Bad_Opcode }, 4761 { VEX_LEN_TABLE (VEX_LEN_0F386B_X86_64) }, 4762 }, 4763 4764 /* X86_64_VEX_0F386C */ 4765 { 4766 { Bad_Opcode }, 4767 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) }, 4768 }, 4769 4770 /* X86_64_VEX_0F386E */ 4771 { 4772 { Bad_Opcode }, 4773 { VEX_LEN_TABLE (VEX_LEN_0F386E_X86_64) }, 4774 }, 4775 4776 /* X86_64_VEX_0F386F */ 4777 { 4778 { Bad_Opcode }, 4779 { VEX_LEN_TABLE (VEX_LEN_0F386F_X86_64) }, 4780 }, 4781 4782 /* X86_64_VEX_0F38Ex */ 4783 { 4784 { Bad_Opcode }, 4785 { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, 4786 }, 4787 4788 /* X86_64_VEX_MAP5_F8 */ 4789 { 4790 { Bad_Opcode }, 4791 { VEX_LEN_TABLE (VEX_LEN_MAP5_F8_X86_64) }, 4792 }, 4793 4794 /* X86_64_VEX_MAP5_F9 */ 4795 { 4796 { Bad_Opcode }, 4797 { VEX_LEN_TABLE (VEX_LEN_MAP5_F9_X86_64) }, 4798 }, 4799 4800 /* X86_64_VEX_MAP5_FD */ 4801 { 4802 { Bad_Opcode }, 4803 { VEX_LEN_TABLE (VEX_LEN_MAP5_FD_X86_64) }, 4804 }, 4805 4806 /* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */ 4807 { 4808 { Bad_Opcode }, 4809 { PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) }, 4810 }, 4811 4812 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */ 4813 { 4814 { Bad_Opcode }, 4815 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) }, 4816 }, 4817 4818 #include "i386-dis-evex-x86-64.h" 4819 }; 4820 4821 static const struct dis386 three_byte_table[][256] = { 4822 4823 /* THREE_BYTE_0F38 */ 4824 { 4825 /* 00 */ 4826 { "pshufb", { MX, EM }, PREFIX_OPCODE }, 4827 { "phaddw", { MX, EM }, PREFIX_OPCODE }, 4828 { "phaddd", { MX, EM }, PREFIX_OPCODE }, 4829 { "phaddsw", { MX, EM }, PREFIX_OPCODE }, 4830 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, 4831 { "phsubw", { MX, EM }, PREFIX_OPCODE }, 4832 { "phsubd", { MX, EM }, PREFIX_OPCODE }, 4833 { "phsubsw", { MX, EM }, PREFIX_OPCODE }, 4834 /* 08 */ 4835 { "psignb", { MX, EM }, PREFIX_OPCODE }, 4836 { "psignw", { MX, EM }, PREFIX_OPCODE }, 4837 { "psignd", { MX, EM }, PREFIX_OPCODE }, 4838 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, 4839 { Bad_Opcode }, 4840 { Bad_Opcode }, 4841 { Bad_Opcode }, 4842 { Bad_Opcode }, 4843 /* 10 */ 4844 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, 4845 { Bad_Opcode }, 4846 { Bad_Opcode }, 4847 { Bad_Opcode }, 4848 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, 4849 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, 4850 { Bad_Opcode }, 4851 { "ptest", { XM, EXx }, PREFIX_DATA }, 4852 /* 18 */ 4853 { Bad_Opcode }, 4854 { Bad_Opcode }, 4855 { Bad_Opcode }, 4856 { Bad_Opcode }, 4857 { "pabsb", { MX, EM }, PREFIX_OPCODE }, 4858 { "pabsw", { MX, EM }, PREFIX_OPCODE }, 4859 { "pabsd", { MX, EM }, PREFIX_OPCODE }, 4860 { Bad_Opcode }, 4861 /* 20 */ 4862 { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, 4863 { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, 4864 { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, 4865 { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, 4866 { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, 4867 { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, 4868 { Bad_Opcode }, 4869 { Bad_Opcode }, 4870 /* 28 */ 4871 { "pmuldq", { XM, EXx }, PREFIX_DATA }, 4872 { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, 4873 { "movntdqa", { XM, Mx }, PREFIX_DATA }, 4874 { "packusdw", { XM, EXx }, PREFIX_DATA }, 4875 { Bad_Opcode }, 4876 { Bad_Opcode }, 4877 { Bad_Opcode }, 4878 { Bad_Opcode }, 4879 /* 30 */ 4880 { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, 4881 { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, 4882 { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, 4883 { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, 4884 { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, 4885 { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, 4886 { Bad_Opcode }, 4887 { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, 4888 /* 38 */ 4889 { "pminsb", { XM, EXx }, PREFIX_DATA }, 4890 { "pminsd", { XM, EXx }, PREFIX_DATA }, 4891 { "pminuw", { XM, EXx }, PREFIX_DATA }, 4892 { "pminud", { XM, EXx }, PREFIX_DATA }, 4893 { "pmaxsb", { XM, EXx }, PREFIX_DATA }, 4894 { "pmaxsd", { XM, EXx }, PREFIX_DATA }, 4895 { "pmaxuw", { XM, EXx }, PREFIX_DATA }, 4896 { "pmaxud", { XM, EXx }, PREFIX_DATA }, 4897 /* 40 */ 4898 { "pmulld", { XM, EXx }, PREFIX_DATA }, 4899 { "phminposuw", { XM, EXx }, PREFIX_DATA }, 4900 { Bad_Opcode }, 4901 { Bad_Opcode }, 4902 { Bad_Opcode }, 4903 { Bad_Opcode }, 4904 { Bad_Opcode }, 4905 { Bad_Opcode }, 4906 /* 48 */ 4907 { Bad_Opcode }, 4908 { Bad_Opcode }, 4909 { Bad_Opcode }, 4910 { Bad_Opcode }, 4911 { Bad_Opcode }, 4912 { Bad_Opcode }, 4913 { Bad_Opcode }, 4914 { Bad_Opcode }, 4915 /* 50 */ 4916 { Bad_Opcode }, 4917 { Bad_Opcode }, 4918 { Bad_Opcode }, 4919 { Bad_Opcode }, 4920 { Bad_Opcode }, 4921 { Bad_Opcode }, 4922 { Bad_Opcode }, 4923 { Bad_Opcode }, 4924 /* 58 */ 4925 { Bad_Opcode }, 4926 { Bad_Opcode }, 4927 { Bad_Opcode }, 4928 { Bad_Opcode }, 4929 { Bad_Opcode }, 4930 { Bad_Opcode }, 4931 { Bad_Opcode }, 4932 { Bad_Opcode }, 4933 /* 60 */ 4934 { Bad_Opcode }, 4935 { Bad_Opcode }, 4936 { Bad_Opcode }, 4937 { Bad_Opcode }, 4938 { Bad_Opcode }, 4939 { Bad_Opcode }, 4940 { Bad_Opcode }, 4941 { Bad_Opcode }, 4942 /* 68 */ 4943 { Bad_Opcode }, 4944 { Bad_Opcode }, 4945 { Bad_Opcode }, 4946 { Bad_Opcode }, 4947 { Bad_Opcode }, 4948 { Bad_Opcode }, 4949 { Bad_Opcode }, 4950 { Bad_Opcode }, 4951 /* 70 */ 4952 { Bad_Opcode }, 4953 { Bad_Opcode }, 4954 { Bad_Opcode }, 4955 { Bad_Opcode }, 4956 { Bad_Opcode }, 4957 { Bad_Opcode }, 4958 { Bad_Opcode }, 4959 { Bad_Opcode }, 4960 /* 78 */ 4961 { Bad_Opcode }, 4962 { Bad_Opcode }, 4963 { Bad_Opcode }, 4964 { Bad_Opcode }, 4965 { Bad_Opcode }, 4966 { Bad_Opcode }, 4967 { Bad_Opcode }, 4968 { Bad_Opcode }, 4969 /* 80 */ 4970 { "invept", { Gm, Mo }, PREFIX_DATA }, 4971 { "invvpid", { Gm, Mo }, PREFIX_DATA }, 4972 { "invpcid", { Gm, M }, PREFIX_DATA }, 4973 { Bad_Opcode }, 4974 { Bad_Opcode }, 4975 { Bad_Opcode }, 4976 { Bad_Opcode }, 4977 { Bad_Opcode }, 4978 /* 88 */ 4979 { Bad_Opcode }, 4980 { Bad_Opcode }, 4981 { X86_64_TABLE (X86_64_0F388A) }, 4982 { X86_64_TABLE (X86_64_0F388B) }, 4983 { Bad_Opcode }, 4984 { Bad_Opcode }, 4985 { Bad_Opcode }, 4986 { Bad_Opcode }, 4987 /* 90 */ 4988 { Bad_Opcode }, 4989 { Bad_Opcode }, 4990 { Bad_Opcode }, 4991 { Bad_Opcode }, 4992 { Bad_Opcode }, 4993 { Bad_Opcode }, 4994 { Bad_Opcode }, 4995 { Bad_Opcode }, 4996 /* 98 */ 4997 { Bad_Opcode }, 4998 { Bad_Opcode }, 4999 { Bad_Opcode }, 5000 { Bad_Opcode }, 5001 { Bad_Opcode }, 5002 { Bad_Opcode }, 5003 { Bad_Opcode }, 5004 { Bad_Opcode }, 5005 /* a0 */ 5006 { Bad_Opcode }, 5007 { Bad_Opcode }, 5008 { Bad_Opcode }, 5009 { Bad_Opcode }, 5010 { Bad_Opcode }, 5011 { Bad_Opcode }, 5012 { Bad_Opcode }, 5013 { Bad_Opcode }, 5014 /* a8 */ 5015 { Bad_Opcode }, 5016 { Bad_Opcode }, 5017 { Bad_Opcode }, 5018 { Bad_Opcode }, 5019 { Bad_Opcode }, 5020 { Bad_Opcode }, 5021 { Bad_Opcode }, 5022 { Bad_Opcode }, 5023 /* b0 */ 5024 { Bad_Opcode }, 5025 { Bad_Opcode }, 5026 { Bad_Opcode }, 5027 { Bad_Opcode }, 5028 { Bad_Opcode }, 5029 { Bad_Opcode }, 5030 { Bad_Opcode }, 5031 { Bad_Opcode }, 5032 /* b8 */ 5033 { Bad_Opcode }, 5034 { Bad_Opcode }, 5035 { Bad_Opcode }, 5036 { Bad_Opcode }, 5037 { Bad_Opcode }, 5038 { Bad_Opcode }, 5039 { Bad_Opcode }, 5040 { Bad_Opcode }, 5041 /* c0 */ 5042 { Bad_Opcode }, 5043 { Bad_Opcode }, 5044 { Bad_Opcode }, 5045 { Bad_Opcode }, 5046 { Bad_Opcode }, 5047 { Bad_Opcode }, 5048 { Bad_Opcode }, 5049 { Bad_Opcode }, 5050 /* c8 */ 5051 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, 5052 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, 5053 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, 5054 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, 5055 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, 5056 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, 5057 { Bad_Opcode }, 5058 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, 5059 /* d0 */ 5060 { Bad_Opcode }, 5061 { Bad_Opcode }, 5062 { Bad_Opcode }, 5063 { Bad_Opcode }, 5064 { Bad_Opcode }, 5065 { Bad_Opcode }, 5066 { Bad_Opcode }, 5067 { Bad_Opcode }, 5068 /* d8 */ 5069 { PREFIX_TABLE (PREFIX_0F38D8) }, 5070 { Bad_Opcode }, 5071 { Bad_Opcode }, 5072 { "aesimc", { XM, EXx }, PREFIX_DATA }, 5073 { PREFIX_TABLE (PREFIX_0F38DC) }, 5074 { PREFIX_TABLE (PREFIX_0F38DD) }, 5075 { PREFIX_TABLE (PREFIX_0F38DE) }, 5076 { PREFIX_TABLE (PREFIX_0F38DF) }, 5077 /* e0 */ 5078 { Bad_Opcode }, 5079 { Bad_Opcode }, 5080 { Bad_Opcode }, 5081 { Bad_Opcode }, 5082 { Bad_Opcode }, 5083 { Bad_Opcode }, 5084 { Bad_Opcode }, 5085 { Bad_Opcode }, 5086 /* e8 */ 5087 { Bad_Opcode }, 5088 { Bad_Opcode }, 5089 { Bad_Opcode }, 5090 { Bad_Opcode }, 5091 { Bad_Opcode }, 5092 { Bad_Opcode }, 5093 { Bad_Opcode }, 5094 { Bad_Opcode }, 5095 /* f0 */ 5096 { PREFIX_TABLE (PREFIX_0F38F0) }, 5097 { PREFIX_TABLE (PREFIX_0F38F1) }, 5098 { Bad_Opcode }, 5099 { Bad_Opcode }, 5100 { Bad_Opcode }, 5101 { "wrussK", { M, Gdq }, PREFIX_DATA }, 5102 { PREFIX_TABLE (PREFIX_0F38F6) }, 5103 { Bad_Opcode }, 5104 /* f8 */ 5105 { MOD_TABLE (MOD_0F38F8) }, 5106 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, 5107 { PREFIX_TABLE (PREFIX_0F38FA) }, 5108 { PREFIX_TABLE (PREFIX_0F38FB) }, 5109 { PREFIX_TABLE (PREFIX_0F38FC) }, 5110 { Bad_Opcode }, 5111 { Bad_Opcode }, 5112 { Bad_Opcode }, 5113 }, 5114 /* THREE_BYTE_0F3A */ 5115 { 5116 /* 00 */ 5117 { Bad_Opcode }, 5118 { Bad_Opcode }, 5119 { Bad_Opcode }, 5120 { Bad_Opcode }, 5121 { Bad_Opcode }, 5122 { Bad_Opcode }, 5123 { Bad_Opcode }, 5124 { Bad_Opcode }, 5125 /* 08 */ 5126 { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, 5127 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, 5128 { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, 5129 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, 5130 { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, 5131 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, 5132 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, 5133 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, 5134 /* 10 */ 5135 { Bad_Opcode }, 5136 { Bad_Opcode }, 5137 { Bad_Opcode }, 5138 { Bad_Opcode }, 5139 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA }, 5140 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA }, 5141 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, 5142 { "extractps", { Ed, XM, Ib }, PREFIX_DATA }, 5143 /* 18 */ 5144 { Bad_Opcode }, 5145 { Bad_Opcode }, 5146 { Bad_Opcode }, 5147 { Bad_Opcode }, 5148 { Bad_Opcode }, 5149 { Bad_Opcode }, 5150 { Bad_Opcode }, 5151 { Bad_Opcode }, 5152 /* 20 */ 5153 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA }, 5154 { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, 5155 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, 5156 { Bad_Opcode }, 5157 { Bad_Opcode }, 5158 { Bad_Opcode }, 5159 { Bad_Opcode }, 5160 { Bad_Opcode }, 5161 /* 28 */ 5162 { Bad_Opcode }, 5163 { Bad_Opcode }, 5164 { Bad_Opcode }, 5165 { Bad_Opcode }, 5166 { Bad_Opcode }, 5167 { Bad_Opcode }, 5168 { Bad_Opcode }, 5169 { Bad_Opcode }, 5170 /* 30 */ 5171 { Bad_Opcode }, 5172 { Bad_Opcode }, 5173 { Bad_Opcode }, 5174 { Bad_Opcode }, 5175 { Bad_Opcode }, 5176 { Bad_Opcode }, 5177 { Bad_Opcode }, 5178 { Bad_Opcode }, 5179 /* 38 */ 5180 { Bad_Opcode }, 5181 { Bad_Opcode }, 5182 { Bad_Opcode }, 5183 { Bad_Opcode }, 5184 { Bad_Opcode }, 5185 { Bad_Opcode }, 5186 { Bad_Opcode }, 5187 { Bad_Opcode }, 5188 /* 40 */ 5189 { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, 5190 { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, 5191 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, 5192 { Bad_Opcode }, 5193 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, 5194 { Bad_Opcode }, 5195 { Bad_Opcode }, 5196 { Bad_Opcode }, 5197 /* 48 */ 5198 { Bad_Opcode }, 5199 { Bad_Opcode }, 5200 { Bad_Opcode }, 5201 { Bad_Opcode }, 5202 { Bad_Opcode }, 5203 { Bad_Opcode }, 5204 { Bad_Opcode }, 5205 { Bad_Opcode }, 5206 /* 50 */ 5207 { Bad_Opcode }, 5208 { Bad_Opcode }, 5209 { Bad_Opcode }, 5210 { Bad_Opcode }, 5211 { Bad_Opcode }, 5212 { Bad_Opcode }, 5213 { Bad_Opcode }, 5214 { Bad_Opcode }, 5215 /* 58 */ 5216 { Bad_Opcode }, 5217 { Bad_Opcode }, 5218 { Bad_Opcode }, 5219 { Bad_Opcode }, 5220 { Bad_Opcode }, 5221 { Bad_Opcode }, 5222 { Bad_Opcode }, 5223 { Bad_Opcode }, 5224 /* 60 */ 5225 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 5226 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 5227 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, 5228 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, 5229 { Bad_Opcode }, 5230 { Bad_Opcode }, 5231 { Bad_Opcode }, 5232 { Bad_Opcode }, 5233 /* 68 */ 5234 { Bad_Opcode }, 5235 { Bad_Opcode }, 5236 { Bad_Opcode }, 5237 { Bad_Opcode }, 5238 { Bad_Opcode }, 5239 { Bad_Opcode }, 5240 { Bad_Opcode }, 5241 { Bad_Opcode }, 5242 /* 70 */ 5243 { Bad_Opcode }, 5244 { Bad_Opcode }, 5245 { Bad_Opcode }, 5246 { Bad_Opcode }, 5247 { Bad_Opcode }, 5248 { Bad_Opcode }, 5249 { Bad_Opcode }, 5250 { Bad_Opcode }, 5251 /* 78 */ 5252 { Bad_Opcode }, 5253 { Bad_Opcode }, 5254 { Bad_Opcode }, 5255 { Bad_Opcode }, 5256 { Bad_Opcode }, 5257 { Bad_Opcode }, 5258 { Bad_Opcode }, 5259 { Bad_Opcode }, 5260 /* 80 */ 5261 { Bad_Opcode }, 5262 { Bad_Opcode }, 5263 { Bad_Opcode }, 5264 { Bad_Opcode }, 5265 { Bad_Opcode }, 5266 { Bad_Opcode }, 5267 { Bad_Opcode }, 5268 { Bad_Opcode }, 5269 /* 88 */ 5270 { Bad_Opcode }, 5271 { Bad_Opcode }, 5272 { Bad_Opcode }, 5273 { Bad_Opcode }, 5274 { Bad_Opcode }, 5275 { Bad_Opcode }, 5276 { Bad_Opcode }, 5277 { Bad_Opcode }, 5278 /* 90 */ 5279 { Bad_Opcode }, 5280 { Bad_Opcode }, 5281 { Bad_Opcode }, 5282 { Bad_Opcode }, 5283 { Bad_Opcode }, 5284 { Bad_Opcode }, 5285 { Bad_Opcode }, 5286 { Bad_Opcode }, 5287 /* 98 */ 5288 { Bad_Opcode }, 5289 { Bad_Opcode }, 5290 { Bad_Opcode }, 5291 { Bad_Opcode }, 5292 { Bad_Opcode }, 5293 { Bad_Opcode }, 5294 { Bad_Opcode }, 5295 { Bad_Opcode }, 5296 /* a0 */ 5297 { Bad_Opcode }, 5298 { Bad_Opcode }, 5299 { Bad_Opcode }, 5300 { Bad_Opcode }, 5301 { Bad_Opcode }, 5302 { Bad_Opcode }, 5303 { Bad_Opcode }, 5304 { Bad_Opcode }, 5305 /* a8 */ 5306 { Bad_Opcode }, 5307 { Bad_Opcode }, 5308 { Bad_Opcode }, 5309 { Bad_Opcode }, 5310 { Bad_Opcode }, 5311 { Bad_Opcode }, 5312 { Bad_Opcode }, 5313 { Bad_Opcode }, 5314 /* b0 */ 5315 { Bad_Opcode }, 5316 { Bad_Opcode }, 5317 { Bad_Opcode }, 5318 { Bad_Opcode }, 5319 { Bad_Opcode }, 5320 { Bad_Opcode }, 5321 { Bad_Opcode }, 5322 { Bad_Opcode }, 5323 /* b8 */ 5324 { Bad_Opcode }, 5325 { Bad_Opcode }, 5326 { Bad_Opcode }, 5327 { Bad_Opcode }, 5328 { Bad_Opcode }, 5329 { Bad_Opcode }, 5330 { Bad_Opcode }, 5331 { Bad_Opcode }, 5332 /* c0 */ 5333 { Bad_Opcode }, 5334 { Bad_Opcode }, 5335 { Bad_Opcode }, 5336 { Bad_Opcode }, 5337 { Bad_Opcode }, 5338 { Bad_Opcode }, 5339 { Bad_Opcode }, 5340 { Bad_Opcode }, 5341 /* c8 */ 5342 { Bad_Opcode }, 5343 { Bad_Opcode }, 5344 { Bad_Opcode }, 5345 { Bad_Opcode }, 5346 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, 5347 { Bad_Opcode }, 5348 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, 5349 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, 5350 /* d0 */ 5351 { Bad_Opcode }, 5352 { Bad_Opcode }, 5353 { Bad_Opcode }, 5354 { Bad_Opcode }, 5355 { Bad_Opcode }, 5356 { Bad_Opcode }, 5357 { Bad_Opcode }, 5358 { Bad_Opcode }, 5359 /* d8 */ 5360 { Bad_Opcode }, 5361 { Bad_Opcode }, 5362 { Bad_Opcode }, 5363 { Bad_Opcode }, 5364 { Bad_Opcode }, 5365 { Bad_Opcode }, 5366 { Bad_Opcode }, 5367 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, 5368 /* e0 */ 5369 { Bad_Opcode }, 5370 { Bad_Opcode }, 5371 { Bad_Opcode }, 5372 { Bad_Opcode }, 5373 { Bad_Opcode }, 5374 { Bad_Opcode }, 5375 { Bad_Opcode }, 5376 { Bad_Opcode }, 5377 /* e8 */ 5378 { Bad_Opcode }, 5379 { Bad_Opcode }, 5380 { Bad_Opcode }, 5381 { Bad_Opcode }, 5382 { Bad_Opcode }, 5383 { Bad_Opcode }, 5384 { Bad_Opcode }, 5385 { Bad_Opcode }, 5386 /* f0 */ 5387 { PREFIX_TABLE (PREFIX_0F3A0F) }, 5388 { Bad_Opcode }, 5389 { Bad_Opcode }, 5390 { Bad_Opcode }, 5391 { Bad_Opcode }, 5392 { Bad_Opcode }, 5393 { Bad_Opcode }, 5394 { Bad_Opcode }, 5395 /* f8 */ 5396 { Bad_Opcode }, 5397 { Bad_Opcode }, 5398 { Bad_Opcode }, 5399 { Bad_Opcode }, 5400 { Bad_Opcode }, 5401 { Bad_Opcode }, 5402 { Bad_Opcode }, 5403 { Bad_Opcode }, 5404 }, 5405 }; 5406 5407 static const struct dis386 xop_table[][256] = { 5408 /* XOP_08 */ 5409 { 5410 /* 00 */ 5411 { Bad_Opcode }, 5412 { Bad_Opcode }, 5413 { Bad_Opcode }, 5414 { Bad_Opcode }, 5415 { Bad_Opcode }, 5416 { Bad_Opcode }, 5417 { Bad_Opcode }, 5418 { Bad_Opcode }, 5419 /* 08 */ 5420 { Bad_Opcode }, 5421 { Bad_Opcode }, 5422 { Bad_Opcode }, 5423 { Bad_Opcode }, 5424 { Bad_Opcode }, 5425 { Bad_Opcode }, 5426 { Bad_Opcode }, 5427 { Bad_Opcode }, 5428 /* 10 */ 5429 { Bad_Opcode }, 5430 { Bad_Opcode }, 5431 { Bad_Opcode }, 5432 { Bad_Opcode }, 5433 { Bad_Opcode }, 5434 { Bad_Opcode }, 5435 { Bad_Opcode }, 5436 { Bad_Opcode }, 5437 /* 18 */ 5438 { Bad_Opcode }, 5439 { Bad_Opcode }, 5440 { Bad_Opcode }, 5441 { Bad_Opcode }, 5442 { Bad_Opcode }, 5443 { Bad_Opcode }, 5444 { Bad_Opcode }, 5445 { Bad_Opcode }, 5446 /* 20 */ 5447 { Bad_Opcode }, 5448 { Bad_Opcode }, 5449 { Bad_Opcode }, 5450 { Bad_Opcode }, 5451 { Bad_Opcode }, 5452 { Bad_Opcode }, 5453 { Bad_Opcode }, 5454 { Bad_Opcode }, 5455 /* 28 */ 5456 { Bad_Opcode }, 5457 { Bad_Opcode }, 5458 { Bad_Opcode }, 5459 { Bad_Opcode }, 5460 { Bad_Opcode }, 5461 { Bad_Opcode }, 5462 { Bad_Opcode }, 5463 { Bad_Opcode }, 5464 /* 30 */ 5465 { Bad_Opcode }, 5466 { Bad_Opcode }, 5467 { Bad_Opcode }, 5468 { Bad_Opcode }, 5469 { Bad_Opcode }, 5470 { Bad_Opcode }, 5471 { Bad_Opcode }, 5472 { Bad_Opcode }, 5473 /* 38 */ 5474 { Bad_Opcode }, 5475 { Bad_Opcode }, 5476 { Bad_Opcode }, 5477 { Bad_Opcode }, 5478 { Bad_Opcode }, 5479 { Bad_Opcode }, 5480 { Bad_Opcode }, 5481 { Bad_Opcode }, 5482 /* 40 */ 5483 { Bad_Opcode }, 5484 { Bad_Opcode }, 5485 { Bad_Opcode }, 5486 { Bad_Opcode }, 5487 { Bad_Opcode }, 5488 { Bad_Opcode }, 5489 { Bad_Opcode }, 5490 { Bad_Opcode }, 5491 /* 48 */ 5492 { Bad_Opcode }, 5493 { Bad_Opcode }, 5494 { Bad_Opcode }, 5495 { Bad_Opcode }, 5496 { Bad_Opcode }, 5497 { Bad_Opcode }, 5498 { Bad_Opcode }, 5499 { Bad_Opcode }, 5500 /* 50 */ 5501 { Bad_Opcode }, 5502 { Bad_Opcode }, 5503 { Bad_Opcode }, 5504 { Bad_Opcode }, 5505 { Bad_Opcode }, 5506 { Bad_Opcode }, 5507 { Bad_Opcode }, 5508 { Bad_Opcode }, 5509 /* 58 */ 5510 { Bad_Opcode }, 5511 { Bad_Opcode }, 5512 { Bad_Opcode }, 5513 { Bad_Opcode }, 5514 { Bad_Opcode }, 5515 { Bad_Opcode }, 5516 { Bad_Opcode }, 5517 { Bad_Opcode }, 5518 /* 60 */ 5519 { Bad_Opcode }, 5520 { Bad_Opcode }, 5521 { Bad_Opcode }, 5522 { Bad_Opcode }, 5523 { Bad_Opcode }, 5524 { Bad_Opcode }, 5525 { Bad_Opcode }, 5526 { Bad_Opcode }, 5527 /* 68 */ 5528 { Bad_Opcode }, 5529 { Bad_Opcode }, 5530 { Bad_Opcode }, 5531 { Bad_Opcode }, 5532 { Bad_Opcode }, 5533 { Bad_Opcode }, 5534 { Bad_Opcode }, 5535 { Bad_Opcode }, 5536 /* 70 */ 5537 { Bad_Opcode }, 5538 { Bad_Opcode }, 5539 { Bad_Opcode }, 5540 { Bad_Opcode }, 5541 { Bad_Opcode }, 5542 { Bad_Opcode }, 5543 { Bad_Opcode }, 5544 { Bad_Opcode }, 5545 /* 78 */ 5546 { Bad_Opcode }, 5547 { Bad_Opcode }, 5548 { Bad_Opcode }, 5549 { Bad_Opcode }, 5550 { Bad_Opcode }, 5551 { Bad_Opcode }, 5552 { Bad_Opcode }, 5553 { Bad_Opcode }, 5554 /* 80 */ 5555 { Bad_Opcode }, 5556 { Bad_Opcode }, 5557 { Bad_Opcode }, 5558 { Bad_Opcode }, 5559 { Bad_Opcode }, 5560 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) }, 5561 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) }, 5562 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) }, 5563 /* 88 */ 5564 { Bad_Opcode }, 5565 { Bad_Opcode }, 5566 { Bad_Opcode }, 5567 { Bad_Opcode }, 5568 { Bad_Opcode }, 5569 { Bad_Opcode }, 5570 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) }, 5571 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) }, 5572 /* 90 */ 5573 { Bad_Opcode }, 5574 { Bad_Opcode }, 5575 { Bad_Opcode }, 5576 { Bad_Opcode }, 5577 { Bad_Opcode }, 5578 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) }, 5579 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) }, 5580 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) }, 5581 /* 98 */ 5582 { Bad_Opcode }, 5583 { Bad_Opcode }, 5584 { Bad_Opcode }, 5585 { Bad_Opcode }, 5586 { Bad_Opcode }, 5587 { Bad_Opcode }, 5588 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) }, 5589 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) }, 5590 /* a0 */ 5591 { Bad_Opcode }, 5592 { Bad_Opcode }, 5593 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, 5594 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) }, 5595 { Bad_Opcode }, 5596 { Bad_Opcode }, 5597 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) }, 5598 { Bad_Opcode }, 5599 /* a8 */ 5600 { Bad_Opcode }, 5601 { Bad_Opcode }, 5602 { Bad_Opcode }, 5603 { Bad_Opcode }, 5604 { Bad_Opcode }, 5605 { Bad_Opcode }, 5606 { Bad_Opcode }, 5607 { Bad_Opcode }, 5608 /* b0 */ 5609 { Bad_Opcode }, 5610 { Bad_Opcode }, 5611 { Bad_Opcode }, 5612 { Bad_Opcode }, 5613 { Bad_Opcode }, 5614 { Bad_Opcode }, 5615 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) }, 5616 { Bad_Opcode }, 5617 /* b8 */ 5618 { Bad_Opcode }, 5619 { Bad_Opcode }, 5620 { Bad_Opcode }, 5621 { Bad_Opcode }, 5622 { Bad_Opcode }, 5623 { Bad_Opcode }, 5624 { Bad_Opcode }, 5625 { Bad_Opcode }, 5626 /* c0 */ 5627 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) }, 5628 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) }, 5629 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) }, 5630 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) }, 5631 { Bad_Opcode }, 5632 { Bad_Opcode }, 5633 { Bad_Opcode }, 5634 { Bad_Opcode }, 5635 /* c8 */ 5636 { Bad_Opcode }, 5637 { Bad_Opcode }, 5638 { Bad_Opcode }, 5639 { Bad_Opcode }, 5640 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) }, 5641 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) }, 5642 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) }, 5643 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) }, 5644 /* d0 */ 5645 { Bad_Opcode }, 5646 { Bad_Opcode }, 5647 { Bad_Opcode }, 5648 { Bad_Opcode }, 5649 { Bad_Opcode }, 5650 { Bad_Opcode }, 5651 { Bad_Opcode }, 5652 { Bad_Opcode }, 5653 /* d8 */ 5654 { Bad_Opcode }, 5655 { Bad_Opcode }, 5656 { Bad_Opcode }, 5657 { Bad_Opcode }, 5658 { Bad_Opcode }, 5659 { Bad_Opcode }, 5660 { Bad_Opcode }, 5661 { Bad_Opcode }, 5662 /* e0 */ 5663 { Bad_Opcode }, 5664 { Bad_Opcode }, 5665 { Bad_Opcode }, 5666 { Bad_Opcode }, 5667 { Bad_Opcode }, 5668 { Bad_Opcode }, 5669 { Bad_Opcode }, 5670 { Bad_Opcode }, 5671 /* e8 */ 5672 { Bad_Opcode }, 5673 { Bad_Opcode }, 5674 { Bad_Opcode }, 5675 { Bad_Opcode }, 5676 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) }, 5677 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) }, 5678 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) }, 5679 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) }, 5680 /* f0 */ 5681 { Bad_Opcode }, 5682 { Bad_Opcode }, 5683 { Bad_Opcode }, 5684 { Bad_Opcode }, 5685 { Bad_Opcode }, 5686 { Bad_Opcode }, 5687 { Bad_Opcode }, 5688 { Bad_Opcode }, 5689 /* f8 */ 5690 { Bad_Opcode }, 5691 { Bad_Opcode }, 5692 { Bad_Opcode }, 5693 { Bad_Opcode }, 5694 { Bad_Opcode }, 5695 { Bad_Opcode }, 5696 { Bad_Opcode }, 5697 { Bad_Opcode }, 5698 }, 5699 /* XOP_09 */ 5700 { 5701 /* 00 */ 5702 { Bad_Opcode }, 5703 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) }, 5704 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) }, 5705 { Bad_Opcode }, 5706 { Bad_Opcode }, 5707 { Bad_Opcode }, 5708 { Bad_Opcode }, 5709 { Bad_Opcode }, 5710 /* 08 */ 5711 { Bad_Opcode }, 5712 { Bad_Opcode }, 5713 { Bad_Opcode }, 5714 { Bad_Opcode }, 5715 { Bad_Opcode }, 5716 { Bad_Opcode }, 5717 { Bad_Opcode }, 5718 { Bad_Opcode }, 5719 /* 10 */ 5720 { Bad_Opcode }, 5721 { Bad_Opcode }, 5722 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) }, 5723 { Bad_Opcode }, 5724 { Bad_Opcode }, 5725 { Bad_Opcode }, 5726 { Bad_Opcode }, 5727 { Bad_Opcode }, 5728 /* 18 */ 5729 { Bad_Opcode }, 5730 { Bad_Opcode }, 5731 { Bad_Opcode }, 5732 { Bad_Opcode }, 5733 { Bad_Opcode }, 5734 { Bad_Opcode }, 5735 { Bad_Opcode }, 5736 { Bad_Opcode }, 5737 /* 20 */ 5738 { Bad_Opcode }, 5739 { Bad_Opcode }, 5740 { Bad_Opcode }, 5741 { Bad_Opcode }, 5742 { Bad_Opcode }, 5743 { Bad_Opcode }, 5744 { Bad_Opcode }, 5745 { Bad_Opcode }, 5746 /* 28 */ 5747 { Bad_Opcode }, 5748 { Bad_Opcode }, 5749 { Bad_Opcode }, 5750 { Bad_Opcode }, 5751 { Bad_Opcode }, 5752 { Bad_Opcode }, 5753 { Bad_Opcode }, 5754 { Bad_Opcode }, 5755 /* 30 */ 5756 { Bad_Opcode }, 5757 { Bad_Opcode }, 5758 { Bad_Opcode }, 5759 { Bad_Opcode }, 5760 { Bad_Opcode }, 5761 { Bad_Opcode }, 5762 { Bad_Opcode }, 5763 { Bad_Opcode }, 5764 /* 38 */ 5765 { Bad_Opcode }, 5766 { Bad_Opcode }, 5767 { Bad_Opcode }, 5768 { Bad_Opcode }, 5769 { Bad_Opcode }, 5770 { Bad_Opcode }, 5771 { Bad_Opcode }, 5772 { Bad_Opcode }, 5773 /* 40 */ 5774 { Bad_Opcode }, 5775 { Bad_Opcode }, 5776 { Bad_Opcode }, 5777 { Bad_Opcode }, 5778 { Bad_Opcode }, 5779 { Bad_Opcode }, 5780 { Bad_Opcode }, 5781 { Bad_Opcode }, 5782 /* 48 */ 5783 { Bad_Opcode }, 5784 { Bad_Opcode }, 5785 { Bad_Opcode }, 5786 { Bad_Opcode }, 5787 { Bad_Opcode }, 5788 { Bad_Opcode }, 5789 { Bad_Opcode }, 5790 { Bad_Opcode }, 5791 /* 50 */ 5792 { Bad_Opcode }, 5793 { Bad_Opcode }, 5794 { Bad_Opcode }, 5795 { Bad_Opcode }, 5796 { Bad_Opcode }, 5797 { Bad_Opcode }, 5798 { Bad_Opcode }, 5799 { Bad_Opcode }, 5800 /* 58 */ 5801 { Bad_Opcode }, 5802 { Bad_Opcode }, 5803 { Bad_Opcode }, 5804 { Bad_Opcode }, 5805 { Bad_Opcode }, 5806 { Bad_Opcode }, 5807 { Bad_Opcode }, 5808 { Bad_Opcode }, 5809 /* 60 */ 5810 { Bad_Opcode }, 5811 { Bad_Opcode }, 5812 { Bad_Opcode }, 5813 { Bad_Opcode }, 5814 { Bad_Opcode }, 5815 { Bad_Opcode }, 5816 { Bad_Opcode }, 5817 { Bad_Opcode }, 5818 /* 68 */ 5819 { Bad_Opcode }, 5820 { Bad_Opcode }, 5821 { Bad_Opcode }, 5822 { Bad_Opcode }, 5823 { Bad_Opcode }, 5824 { Bad_Opcode }, 5825 { Bad_Opcode }, 5826 { Bad_Opcode }, 5827 /* 70 */ 5828 { Bad_Opcode }, 5829 { Bad_Opcode }, 5830 { Bad_Opcode }, 5831 { Bad_Opcode }, 5832 { Bad_Opcode }, 5833 { Bad_Opcode }, 5834 { Bad_Opcode }, 5835 { Bad_Opcode }, 5836 /* 78 */ 5837 { Bad_Opcode }, 5838 { Bad_Opcode }, 5839 { Bad_Opcode }, 5840 { Bad_Opcode }, 5841 { Bad_Opcode }, 5842 { Bad_Opcode }, 5843 { Bad_Opcode }, 5844 { Bad_Opcode }, 5845 /* 80 */ 5846 { VEX_W_TABLE (VEX_W_XOP_09_80) }, 5847 { VEX_W_TABLE (VEX_W_XOP_09_81) }, 5848 { VEX_W_TABLE (VEX_W_XOP_09_82) }, 5849 { VEX_W_TABLE (VEX_W_XOP_09_83) }, 5850 { Bad_Opcode }, 5851 { Bad_Opcode }, 5852 { Bad_Opcode }, 5853 { Bad_Opcode }, 5854 /* 88 */ 5855 { Bad_Opcode }, 5856 { Bad_Opcode }, 5857 { Bad_Opcode }, 5858 { Bad_Opcode }, 5859 { Bad_Opcode }, 5860 { Bad_Opcode }, 5861 { Bad_Opcode }, 5862 { Bad_Opcode }, 5863 /* 90 */ 5864 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) }, 5865 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) }, 5866 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) }, 5867 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) }, 5868 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) }, 5869 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) }, 5870 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) }, 5871 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) }, 5872 /* 98 */ 5873 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) }, 5874 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) }, 5875 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) }, 5876 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) }, 5877 { Bad_Opcode }, 5878 { Bad_Opcode }, 5879 { Bad_Opcode }, 5880 { Bad_Opcode }, 5881 /* a0 */ 5882 { Bad_Opcode }, 5883 { Bad_Opcode }, 5884 { Bad_Opcode }, 5885 { Bad_Opcode }, 5886 { Bad_Opcode }, 5887 { Bad_Opcode }, 5888 { Bad_Opcode }, 5889 { Bad_Opcode }, 5890 /* a8 */ 5891 { Bad_Opcode }, 5892 { Bad_Opcode }, 5893 { Bad_Opcode }, 5894 { Bad_Opcode }, 5895 { Bad_Opcode }, 5896 { Bad_Opcode }, 5897 { Bad_Opcode }, 5898 { Bad_Opcode }, 5899 /* b0 */ 5900 { Bad_Opcode }, 5901 { Bad_Opcode }, 5902 { Bad_Opcode }, 5903 { Bad_Opcode }, 5904 { Bad_Opcode }, 5905 { Bad_Opcode }, 5906 { Bad_Opcode }, 5907 { Bad_Opcode }, 5908 /* b8 */ 5909 { Bad_Opcode }, 5910 { Bad_Opcode }, 5911 { Bad_Opcode }, 5912 { Bad_Opcode }, 5913 { Bad_Opcode }, 5914 { Bad_Opcode }, 5915 { Bad_Opcode }, 5916 { Bad_Opcode }, 5917 /* c0 */ 5918 { Bad_Opcode }, 5919 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) }, 5920 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) }, 5921 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) }, 5922 { Bad_Opcode }, 5923 { Bad_Opcode }, 5924 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) }, 5925 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) }, 5926 /* c8 */ 5927 { Bad_Opcode }, 5928 { Bad_Opcode }, 5929 { Bad_Opcode }, 5930 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) }, 5931 { Bad_Opcode }, 5932 { Bad_Opcode }, 5933 { Bad_Opcode }, 5934 { Bad_Opcode }, 5935 /* d0 */ 5936 { Bad_Opcode }, 5937 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) }, 5938 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) }, 5939 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) }, 5940 { Bad_Opcode }, 5941 { Bad_Opcode }, 5942 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) }, 5943 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) }, 5944 /* d8 */ 5945 { Bad_Opcode }, 5946 { Bad_Opcode }, 5947 { Bad_Opcode }, 5948 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) }, 5949 { Bad_Opcode }, 5950 { Bad_Opcode }, 5951 { Bad_Opcode }, 5952 { Bad_Opcode }, 5953 /* e0 */ 5954 { Bad_Opcode }, 5955 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) }, 5956 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) }, 5957 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) }, 5958 { Bad_Opcode }, 5959 { Bad_Opcode }, 5960 { Bad_Opcode }, 5961 { Bad_Opcode }, 5962 /* e8 */ 5963 { Bad_Opcode }, 5964 { Bad_Opcode }, 5965 { Bad_Opcode }, 5966 { Bad_Opcode }, 5967 { Bad_Opcode }, 5968 { Bad_Opcode }, 5969 { Bad_Opcode }, 5970 { Bad_Opcode }, 5971 /* f0 */ 5972 { Bad_Opcode }, 5973 { Bad_Opcode }, 5974 { Bad_Opcode }, 5975 { Bad_Opcode }, 5976 { Bad_Opcode }, 5977 { Bad_Opcode }, 5978 { Bad_Opcode }, 5979 { Bad_Opcode }, 5980 /* f8 */ 5981 { Bad_Opcode }, 5982 { Bad_Opcode }, 5983 { Bad_Opcode }, 5984 { Bad_Opcode }, 5985 { Bad_Opcode }, 5986 { Bad_Opcode }, 5987 { Bad_Opcode }, 5988 { Bad_Opcode }, 5989 }, 5990 /* XOP_0A */ 5991 { 5992 /* 00 */ 5993 { Bad_Opcode }, 5994 { Bad_Opcode }, 5995 { Bad_Opcode }, 5996 { Bad_Opcode }, 5997 { Bad_Opcode }, 5998 { Bad_Opcode }, 5999 { Bad_Opcode }, 6000 { Bad_Opcode }, 6001 /* 08 */ 6002 { Bad_Opcode }, 6003 { Bad_Opcode }, 6004 { Bad_Opcode }, 6005 { Bad_Opcode }, 6006 { Bad_Opcode }, 6007 { Bad_Opcode }, 6008 { Bad_Opcode }, 6009 { Bad_Opcode }, 6010 /* 10 */ 6011 { "bextrS", { Gdq, Edq, Id }, 0 }, 6012 { Bad_Opcode }, 6013 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) }, 6014 { Bad_Opcode }, 6015 { Bad_Opcode }, 6016 { Bad_Opcode }, 6017 { Bad_Opcode }, 6018 { Bad_Opcode }, 6019 /* 18 */ 6020 { Bad_Opcode }, 6021 { Bad_Opcode }, 6022 { Bad_Opcode }, 6023 { Bad_Opcode }, 6024 { Bad_Opcode }, 6025 { Bad_Opcode }, 6026 { Bad_Opcode }, 6027 { Bad_Opcode }, 6028 /* 20 */ 6029 { Bad_Opcode }, 6030 { Bad_Opcode }, 6031 { Bad_Opcode }, 6032 { Bad_Opcode }, 6033 { Bad_Opcode }, 6034 { Bad_Opcode }, 6035 { Bad_Opcode }, 6036 { Bad_Opcode }, 6037 /* 28 */ 6038 { Bad_Opcode }, 6039 { Bad_Opcode }, 6040 { Bad_Opcode }, 6041 { Bad_Opcode }, 6042 { Bad_Opcode }, 6043 { Bad_Opcode }, 6044 { Bad_Opcode }, 6045 { Bad_Opcode }, 6046 /* 30 */ 6047 { Bad_Opcode }, 6048 { Bad_Opcode }, 6049 { Bad_Opcode }, 6050 { Bad_Opcode }, 6051 { Bad_Opcode }, 6052 { Bad_Opcode }, 6053 { Bad_Opcode }, 6054 { Bad_Opcode }, 6055 /* 38 */ 6056 { Bad_Opcode }, 6057 { Bad_Opcode }, 6058 { Bad_Opcode }, 6059 { Bad_Opcode }, 6060 { Bad_Opcode }, 6061 { Bad_Opcode }, 6062 { Bad_Opcode }, 6063 { Bad_Opcode }, 6064 /* 40 */ 6065 { Bad_Opcode }, 6066 { Bad_Opcode }, 6067 { Bad_Opcode }, 6068 { Bad_Opcode }, 6069 { Bad_Opcode }, 6070 { Bad_Opcode }, 6071 { Bad_Opcode }, 6072 { Bad_Opcode }, 6073 /* 48 */ 6074 { Bad_Opcode }, 6075 { Bad_Opcode }, 6076 { Bad_Opcode }, 6077 { Bad_Opcode }, 6078 { Bad_Opcode }, 6079 { Bad_Opcode }, 6080 { Bad_Opcode }, 6081 { Bad_Opcode }, 6082 /* 50 */ 6083 { Bad_Opcode }, 6084 { Bad_Opcode }, 6085 { Bad_Opcode }, 6086 { Bad_Opcode }, 6087 { Bad_Opcode }, 6088 { Bad_Opcode }, 6089 { Bad_Opcode }, 6090 { Bad_Opcode }, 6091 /* 58 */ 6092 { Bad_Opcode }, 6093 { Bad_Opcode }, 6094 { Bad_Opcode }, 6095 { Bad_Opcode }, 6096 { Bad_Opcode }, 6097 { Bad_Opcode }, 6098 { Bad_Opcode }, 6099 { Bad_Opcode }, 6100 /* 60 */ 6101 { Bad_Opcode }, 6102 { Bad_Opcode }, 6103 { Bad_Opcode }, 6104 { Bad_Opcode }, 6105 { Bad_Opcode }, 6106 { Bad_Opcode }, 6107 { Bad_Opcode }, 6108 { Bad_Opcode }, 6109 /* 68 */ 6110 { Bad_Opcode }, 6111 { Bad_Opcode }, 6112 { Bad_Opcode }, 6113 { Bad_Opcode }, 6114 { Bad_Opcode }, 6115 { Bad_Opcode }, 6116 { Bad_Opcode }, 6117 { Bad_Opcode }, 6118 /* 70 */ 6119 { Bad_Opcode }, 6120 { Bad_Opcode }, 6121 { Bad_Opcode }, 6122 { Bad_Opcode }, 6123 { Bad_Opcode }, 6124 { Bad_Opcode }, 6125 { Bad_Opcode }, 6126 { Bad_Opcode }, 6127 /* 78 */ 6128 { Bad_Opcode }, 6129 { Bad_Opcode }, 6130 { Bad_Opcode }, 6131 { Bad_Opcode }, 6132 { Bad_Opcode }, 6133 { Bad_Opcode }, 6134 { Bad_Opcode }, 6135 { Bad_Opcode }, 6136 /* 80 */ 6137 { Bad_Opcode }, 6138 { Bad_Opcode }, 6139 { Bad_Opcode }, 6140 { Bad_Opcode }, 6141 { Bad_Opcode }, 6142 { Bad_Opcode }, 6143 { Bad_Opcode }, 6144 { Bad_Opcode }, 6145 /* 88 */ 6146 { Bad_Opcode }, 6147 { Bad_Opcode }, 6148 { Bad_Opcode }, 6149 { Bad_Opcode }, 6150 { Bad_Opcode }, 6151 { Bad_Opcode }, 6152 { Bad_Opcode }, 6153 { Bad_Opcode }, 6154 /* 90 */ 6155 { Bad_Opcode }, 6156 { Bad_Opcode }, 6157 { Bad_Opcode }, 6158 { Bad_Opcode }, 6159 { Bad_Opcode }, 6160 { Bad_Opcode }, 6161 { Bad_Opcode }, 6162 { Bad_Opcode }, 6163 /* 98 */ 6164 { Bad_Opcode }, 6165 { Bad_Opcode }, 6166 { Bad_Opcode }, 6167 { Bad_Opcode }, 6168 { Bad_Opcode }, 6169 { Bad_Opcode }, 6170 { Bad_Opcode }, 6171 { Bad_Opcode }, 6172 /* a0 */ 6173 { Bad_Opcode }, 6174 { Bad_Opcode }, 6175 { Bad_Opcode }, 6176 { Bad_Opcode }, 6177 { Bad_Opcode }, 6178 { Bad_Opcode }, 6179 { Bad_Opcode }, 6180 { Bad_Opcode }, 6181 /* a8 */ 6182 { Bad_Opcode }, 6183 { Bad_Opcode }, 6184 { Bad_Opcode }, 6185 { Bad_Opcode }, 6186 { Bad_Opcode }, 6187 { Bad_Opcode }, 6188 { Bad_Opcode }, 6189 { Bad_Opcode }, 6190 /* b0 */ 6191 { Bad_Opcode }, 6192 { Bad_Opcode }, 6193 { Bad_Opcode }, 6194 { Bad_Opcode }, 6195 { Bad_Opcode }, 6196 { Bad_Opcode }, 6197 { Bad_Opcode }, 6198 { Bad_Opcode }, 6199 /* b8 */ 6200 { Bad_Opcode }, 6201 { Bad_Opcode }, 6202 { Bad_Opcode }, 6203 { Bad_Opcode }, 6204 { Bad_Opcode }, 6205 { Bad_Opcode }, 6206 { Bad_Opcode }, 6207 { Bad_Opcode }, 6208 /* c0 */ 6209 { Bad_Opcode }, 6210 { Bad_Opcode }, 6211 { Bad_Opcode }, 6212 { Bad_Opcode }, 6213 { Bad_Opcode }, 6214 { Bad_Opcode }, 6215 { Bad_Opcode }, 6216 { Bad_Opcode }, 6217 /* c8 */ 6218 { Bad_Opcode }, 6219 { Bad_Opcode }, 6220 { Bad_Opcode }, 6221 { Bad_Opcode }, 6222 { Bad_Opcode }, 6223 { Bad_Opcode }, 6224 { Bad_Opcode }, 6225 { Bad_Opcode }, 6226 /* d0 */ 6227 { Bad_Opcode }, 6228 { Bad_Opcode }, 6229 { Bad_Opcode }, 6230 { Bad_Opcode }, 6231 { Bad_Opcode }, 6232 { Bad_Opcode }, 6233 { Bad_Opcode }, 6234 { Bad_Opcode }, 6235 /* d8 */ 6236 { Bad_Opcode }, 6237 { Bad_Opcode }, 6238 { Bad_Opcode }, 6239 { Bad_Opcode }, 6240 { Bad_Opcode }, 6241 { Bad_Opcode }, 6242 { Bad_Opcode }, 6243 { Bad_Opcode }, 6244 /* e0 */ 6245 { Bad_Opcode }, 6246 { Bad_Opcode }, 6247 { Bad_Opcode }, 6248 { Bad_Opcode }, 6249 { Bad_Opcode }, 6250 { Bad_Opcode }, 6251 { Bad_Opcode }, 6252 { Bad_Opcode }, 6253 /* e8 */ 6254 { Bad_Opcode }, 6255 { Bad_Opcode }, 6256 { Bad_Opcode }, 6257 { Bad_Opcode }, 6258 { Bad_Opcode }, 6259 { Bad_Opcode }, 6260 { Bad_Opcode }, 6261 { Bad_Opcode }, 6262 /* f0 */ 6263 { Bad_Opcode }, 6264 { Bad_Opcode }, 6265 { Bad_Opcode }, 6266 { Bad_Opcode }, 6267 { Bad_Opcode }, 6268 { Bad_Opcode }, 6269 { Bad_Opcode }, 6270 { Bad_Opcode }, 6271 /* f8 */ 6272 { Bad_Opcode }, 6273 { Bad_Opcode }, 6274 { Bad_Opcode }, 6275 { Bad_Opcode }, 6276 { Bad_Opcode }, 6277 { Bad_Opcode }, 6278 { Bad_Opcode }, 6279 { Bad_Opcode }, 6280 }, 6281 }; 6282 6283 static const struct dis386 vex_table[][256] = { 6284 /* VEX_0F */ 6285 { 6286 /* 00 */ 6287 { Bad_Opcode }, 6288 { Bad_Opcode }, 6289 { Bad_Opcode }, 6290 { Bad_Opcode }, 6291 { Bad_Opcode }, 6292 { Bad_Opcode }, 6293 { Bad_Opcode }, 6294 { Bad_Opcode }, 6295 /* 08 */ 6296 { Bad_Opcode }, 6297 { Bad_Opcode }, 6298 { Bad_Opcode }, 6299 { Bad_Opcode }, 6300 { Bad_Opcode }, 6301 { Bad_Opcode }, 6302 { Bad_Opcode }, 6303 { Bad_Opcode }, 6304 /* 10 */ 6305 { PREFIX_TABLE (PREFIX_0F10) }, 6306 { PREFIX_TABLE (PREFIX_0F11) }, 6307 { PREFIX_TABLE (PREFIX_VEX_0F12) }, 6308 { VEX_LEN_TABLE (VEX_LEN_0F13) }, 6309 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6310 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6311 { PREFIX_TABLE (PREFIX_VEX_0F16) }, 6312 { VEX_LEN_TABLE (VEX_LEN_0F17) }, 6313 /* 18 */ 6314 { Bad_Opcode }, 6315 { Bad_Opcode }, 6316 { Bad_Opcode }, 6317 { Bad_Opcode }, 6318 { Bad_Opcode }, 6319 { Bad_Opcode }, 6320 { Bad_Opcode }, 6321 { Bad_Opcode }, 6322 /* 20 */ 6323 { Bad_Opcode }, 6324 { Bad_Opcode }, 6325 { Bad_Opcode }, 6326 { Bad_Opcode }, 6327 { Bad_Opcode }, 6328 { Bad_Opcode }, 6329 { Bad_Opcode }, 6330 { Bad_Opcode }, 6331 /* 28 */ 6332 { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, 6333 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, 6334 { PREFIX_TABLE (PREFIX_VEX_0F2A) }, 6335 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, 6336 { PREFIX_TABLE (PREFIX_VEX_0F2C) }, 6337 { PREFIX_TABLE (PREFIX_VEX_0F2D) }, 6338 { PREFIX_TABLE (PREFIX_0F2E) }, 6339 { PREFIX_TABLE (PREFIX_0F2F) }, 6340 /* 30 */ 6341 { Bad_Opcode }, 6342 { Bad_Opcode }, 6343 { Bad_Opcode }, 6344 { Bad_Opcode }, 6345 { Bad_Opcode }, 6346 { Bad_Opcode }, 6347 { Bad_Opcode }, 6348 { Bad_Opcode }, 6349 /* 38 */ 6350 { Bad_Opcode }, 6351 { Bad_Opcode }, 6352 { Bad_Opcode }, 6353 { Bad_Opcode }, 6354 { Bad_Opcode }, 6355 { Bad_Opcode }, 6356 { Bad_Opcode }, 6357 { Bad_Opcode }, 6358 /* 40 */ 6359 { Bad_Opcode }, 6360 { VEX_LEN_TABLE (VEX_LEN_0F41) }, 6361 { VEX_LEN_TABLE (VEX_LEN_0F42) }, 6362 { Bad_Opcode }, 6363 { VEX_LEN_TABLE (VEX_LEN_0F44) }, 6364 { VEX_LEN_TABLE (VEX_LEN_0F45) }, 6365 { VEX_LEN_TABLE (VEX_LEN_0F46) }, 6366 { VEX_LEN_TABLE (VEX_LEN_0F47) }, 6367 /* 48 */ 6368 { Bad_Opcode }, 6369 { Bad_Opcode }, 6370 { VEX_LEN_TABLE (VEX_LEN_0F4A) }, 6371 { VEX_LEN_TABLE (VEX_LEN_0F4B) }, 6372 { Bad_Opcode }, 6373 { Bad_Opcode }, 6374 { Bad_Opcode }, 6375 { Bad_Opcode }, 6376 /* 50 */ 6377 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE }, 6378 { PREFIX_TABLE (PREFIX_0F51) }, 6379 { PREFIX_TABLE (PREFIX_0F52) }, 6380 { PREFIX_TABLE (PREFIX_0F53) }, 6381 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6382 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6383 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6384 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, 6385 /* 58 */ 6386 { PREFIX_TABLE (PREFIX_0F58) }, 6387 { PREFIX_TABLE (PREFIX_0F59) }, 6388 { PREFIX_TABLE (PREFIX_0F5A) }, 6389 { PREFIX_TABLE (PREFIX_0F5B) }, 6390 { PREFIX_TABLE (PREFIX_0F5C) }, 6391 { PREFIX_TABLE (PREFIX_0F5D) }, 6392 { PREFIX_TABLE (PREFIX_0F5E) }, 6393 { PREFIX_TABLE (PREFIX_0F5F) }, 6394 /* 60 */ 6395 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, 6396 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, 6397 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, 6398 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, 6399 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, 6400 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, 6401 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, 6402 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, 6403 /* 68 */ 6404 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, 6405 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, 6406 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, 6407 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, 6408 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, 6409 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, 6410 { VEX_LEN_TABLE (VEX_LEN_0F6E) }, 6411 { PREFIX_TABLE (PREFIX_VEX_0F6F) }, 6412 /* 70 */ 6413 { PREFIX_TABLE (PREFIX_VEX_0F70) }, 6414 { REG_TABLE (REG_VEX_0F71) }, 6415 { REG_TABLE (REG_VEX_0F72) }, 6416 { REG_TABLE (REG_VEX_0F73) }, 6417 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, 6418 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, 6419 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, 6420 { VEX_LEN_TABLE (VEX_LEN_0F77) }, 6421 /* 78 */ 6422 { Bad_Opcode }, 6423 { Bad_Opcode }, 6424 { Bad_Opcode }, 6425 { Bad_Opcode }, 6426 { PREFIX_TABLE (PREFIX_0F7C) }, 6427 { PREFIX_TABLE (PREFIX_0F7D) }, 6428 { PREFIX_TABLE (PREFIX_VEX_0F7E) }, 6429 { PREFIX_TABLE (PREFIX_VEX_0F7F) }, 6430 /* 80 */ 6431 { Bad_Opcode }, 6432 { Bad_Opcode }, 6433 { Bad_Opcode }, 6434 { Bad_Opcode }, 6435 { Bad_Opcode }, 6436 { Bad_Opcode }, 6437 { Bad_Opcode }, 6438 { Bad_Opcode }, 6439 /* 88 */ 6440 { Bad_Opcode }, 6441 { Bad_Opcode }, 6442 { Bad_Opcode }, 6443 { Bad_Opcode }, 6444 { Bad_Opcode }, 6445 { Bad_Opcode }, 6446 { Bad_Opcode }, 6447 { Bad_Opcode }, 6448 /* 90 */ 6449 { VEX_LEN_TABLE (VEX_LEN_0F90) }, 6450 { VEX_LEN_TABLE (VEX_LEN_0F91) }, 6451 { VEX_LEN_TABLE (VEX_LEN_0F92) }, 6452 { VEX_LEN_TABLE (VEX_LEN_0F93) }, 6453 { Bad_Opcode }, 6454 { Bad_Opcode }, 6455 { Bad_Opcode }, 6456 { Bad_Opcode }, 6457 /* 98 */ 6458 { VEX_LEN_TABLE (VEX_LEN_0F98) }, 6459 { VEX_LEN_TABLE (VEX_LEN_0F99) }, 6460 { Bad_Opcode }, 6461 { Bad_Opcode }, 6462 { Bad_Opcode }, 6463 { Bad_Opcode }, 6464 { Bad_Opcode }, 6465 { Bad_Opcode }, 6466 /* a0 */ 6467 { Bad_Opcode }, 6468 { Bad_Opcode }, 6469 { Bad_Opcode }, 6470 { Bad_Opcode }, 6471 { Bad_Opcode }, 6472 { Bad_Opcode }, 6473 { Bad_Opcode }, 6474 { Bad_Opcode }, 6475 /* a8 */ 6476 { Bad_Opcode }, 6477 { Bad_Opcode }, 6478 { Bad_Opcode }, 6479 { Bad_Opcode }, 6480 { Bad_Opcode }, 6481 { Bad_Opcode }, 6482 { REG_TABLE (REG_VEX_0FAE) }, 6483 { Bad_Opcode }, 6484 /* b0 */ 6485 { Bad_Opcode }, 6486 { Bad_Opcode }, 6487 { Bad_Opcode }, 6488 { Bad_Opcode }, 6489 { Bad_Opcode }, 6490 { Bad_Opcode }, 6491 { Bad_Opcode }, 6492 { Bad_Opcode }, 6493 /* b8 */ 6494 { Bad_Opcode }, 6495 { Bad_Opcode }, 6496 { Bad_Opcode }, 6497 { Bad_Opcode }, 6498 { Bad_Opcode }, 6499 { Bad_Opcode }, 6500 { Bad_Opcode }, 6501 { Bad_Opcode }, 6502 /* c0 */ 6503 { Bad_Opcode }, 6504 { Bad_Opcode }, 6505 { PREFIX_TABLE (PREFIX_0FC2) }, 6506 { Bad_Opcode }, 6507 { VEX_LEN_TABLE (VEX_LEN_0FC4) }, 6508 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA }, 6509 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, 6510 { Bad_Opcode }, 6511 /* c8 */ 6512 { Bad_Opcode }, 6513 { Bad_Opcode }, 6514 { Bad_Opcode }, 6515 { Bad_Opcode }, 6516 { Bad_Opcode }, 6517 { Bad_Opcode }, 6518 { Bad_Opcode }, 6519 { Bad_Opcode }, 6520 /* d0 */ 6521 { PREFIX_TABLE (PREFIX_0FD0) }, 6522 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6523 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, 6524 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, 6525 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, 6526 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, 6527 { VEX_LEN_TABLE (VEX_LEN_0FD6) }, 6528 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA }, 6529 /* d8 */ 6530 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, 6531 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, 6532 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, 6533 { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, 6534 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, 6535 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, 6536 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, 6537 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, 6538 /* e0 */ 6539 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, 6540 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6541 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, 6542 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, 6543 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, 6544 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, 6545 { PREFIX_TABLE (PREFIX_0FE6) }, 6546 { "vmovntdq", { Mx, XM }, PREFIX_DATA }, 6547 /* e8 */ 6548 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, 6549 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6550 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, 6551 { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, 6552 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, 6553 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, 6554 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, 6555 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, 6556 /* f0 */ 6557 { PREFIX_TABLE (PREFIX_0FF0) }, 6558 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, 6559 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, 6560 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, 6561 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, 6562 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, 6563 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, 6564 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA }, 6565 /* f8 */ 6566 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, 6567 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, 6568 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, 6569 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, 6570 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, 6571 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, 6572 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, 6573 { Bad_Opcode }, 6574 }, 6575 /* VEX_0F38 */ 6576 { 6577 /* 00 */ 6578 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, 6579 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, 6580 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, 6581 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, 6582 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6583 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, 6584 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, 6585 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, 6586 /* 08 */ 6587 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, 6588 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, 6589 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, 6590 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, 6591 { VEX_W_TABLE (VEX_W_0F380C) }, 6592 { VEX_W_TABLE (VEX_W_0F380D) }, 6593 { VEX_W_TABLE (VEX_W_0F380E) }, 6594 { VEX_W_TABLE (VEX_W_0F380F) }, 6595 /* 10 */ 6596 { Bad_Opcode }, 6597 { Bad_Opcode }, 6598 { Bad_Opcode }, 6599 { VEX_W_TABLE (VEX_W_0F3813) }, 6600 { Bad_Opcode }, 6601 { Bad_Opcode }, 6602 { VEX_LEN_TABLE (VEX_LEN_0F3816) }, 6603 { "vptest", { XM, EXx }, PREFIX_DATA }, 6604 /* 18 */ 6605 { VEX_W_TABLE (VEX_W_0F3818) }, 6606 { VEX_LEN_TABLE (VEX_LEN_0F3819) }, 6607 { VEX_LEN_TABLE (VEX_LEN_0F381A) }, 6608 { Bad_Opcode }, 6609 { "vpabsb", { XM, EXx }, PREFIX_DATA }, 6610 { "vpabsw", { XM, EXx }, PREFIX_DATA }, 6611 { "vpabsd", { XM, EXx }, PREFIX_DATA }, 6612 { Bad_Opcode }, 6613 /* 20 */ 6614 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, 6615 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, 6616 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, 6617 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, 6618 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, 6619 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, 6620 { Bad_Opcode }, 6621 { Bad_Opcode }, 6622 /* 28 */ 6623 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, 6624 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, 6625 { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, 6626 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, 6627 { VEX_W_TABLE (VEX_W_0F382C) }, 6628 { VEX_W_TABLE (VEX_W_0F382D) }, 6629 { VEX_W_TABLE (VEX_W_0F382E) }, 6630 { VEX_W_TABLE (VEX_W_0F382F) }, 6631 /* 30 */ 6632 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, 6633 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, 6634 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, 6635 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, 6636 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, 6637 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, 6638 { VEX_LEN_TABLE (VEX_LEN_0F3836) }, 6639 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, 6640 /* 38 */ 6641 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, 6642 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, 6643 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, 6644 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, 6645 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, 6646 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, 6647 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, 6648 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, 6649 /* 40 */ 6650 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, 6651 { VEX_LEN_TABLE (VEX_LEN_0F3841) }, 6652 { Bad_Opcode }, 6653 { Bad_Opcode }, 6654 { Bad_Opcode }, 6655 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, 6656 { VEX_W_TABLE (VEX_W_0F3846) }, 6657 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, 6658 /* 48 */ 6659 { X86_64_TABLE (X86_64_VEX_0F3848) }, 6660 { X86_64_TABLE (X86_64_VEX_0F3849) }, 6661 { X86_64_TABLE (X86_64_VEX_0F384A) }, 6662 { X86_64_TABLE (X86_64_VEX_0F384B) }, 6663 { Bad_Opcode }, 6664 { Bad_Opcode }, 6665 { Bad_Opcode }, 6666 { Bad_Opcode }, 6667 /* 50 */ 6668 { VEX_W_TABLE (VEX_W_0F3850) }, 6669 { VEX_W_TABLE (VEX_W_0F3851) }, 6670 { VEX_W_TABLE (VEX_W_0F3852) }, 6671 { VEX_W_TABLE (VEX_W_0F3853) }, 6672 { Bad_Opcode }, 6673 { Bad_Opcode }, 6674 { Bad_Opcode }, 6675 { Bad_Opcode }, 6676 /* 58 */ 6677 { VEX_W_TABLE (VEX_W_0F3858) }, 6678 { VEX_W_TABLE (VEX_W_0F3859) }, 6679 { VEX_LEN_TABLE (VEX_LEN_0F385A) }, 6680 { Bad_Opcode }, 6681 { X86_64_TABLE (X86_64_VEX_0F385C) }, 6682 { Bad_Opcode }, 6683 { X86_64_TABLE (X86_64_VEX_0F385E) }, 6684 { X86_64_TABLE (X86_64_VEX_0F385F) }, 6685 /* 60 */ 6686 { Bad_Opcode }, 6687 { Bad_Opcode }, 6688 { Bad_Opcode }, 6689 { Bad_Opcode }, 6690 { Bad_Opcode }, 6691 { Bad_Opcode }, 6692 { Bad_Opcode }, 6693 { Bad_Opcode }, 6694 /* 68 */ 6695 { Bad_Opcode }, 6696 { Bad_Opcode }, 6697 { Bad_Opcode }, 6698 { X86_64_TABLE (X86_64_VEX_0F386B) }, 6699 { X86_64_TABLE (X86_64_VEX_0F386C) }, 6700 { Bad_Opcode }, 6701 { X86_64_TABLE (X86_64_VEX_0F386E) }, 6702 { X86_64_TABLE (X86_64_VEX_0F386F) }, 6703 /* 70 */ 6704 { Bad_Opcode }, 6705 { Bad_Opcode }, 6706 { PREFIX_TABLE (PREFIX_VEX_0F3872) }, 6707 { Bad_Opcode }, 6708 { Bad_Opcode }, 6709 { Bad_Opcode }, 6710 { Bad_Opcode }, 6711 { Bad_Opcode }, 6712 /* 78 */ 6713 { VEX_W_TABLE (VEX_W_0F3878) }, 6714 { VEX_W_TABLE (VEX_W_0F3879) }, 6715 { Bad_Opcode }, 6716 { Bad_Opcode }, 6717 { Bad_Opcode }, 6718 { Bad_Opcode }, 6719 { Bad_Opcode }, 6720 { Bad_Opcode }, 6721 /* 80 */ 6722 { Bad_Opcode }, 6723 { Bad_Opcode }, 6724 { Bad_Opcode }, 6725 { Bad_Opcode }, 6726 { Bad_Opcode }, 6727 { Bad_Opcode }, 6728 { Bad_Opcode }, 6729 { Bad_Opcode }, 6730 /* 88 */ 6731 { Bad_Opcode }, 6732 { Bad_Opcode }, 6733 { Bad_Opcode }, 6734 { Bad_Opcode }, 6735 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, 6736 { Bad_Opcode }, 6737 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, 6738 { Bad_Opcode }, 6739 /* 90 */ 6740 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, 6741 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, 6742 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, 6743 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, 6744 { Bad_Opcode }, 6745 { Bad_Opcode }, 6746 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6747 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6748 /* 98 */ 6749 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6750 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6751 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6752 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6753 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6754 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6755 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6756 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6757 /* a0 */ 6758 { Bad_Opcode }, 6759 { Bad_Opcode }, 6760 { Bad_Opcode }, 6761 { Bad_Opcode }, 6762 { Bad_Opcode }, 6763 { Bad_Opcode }, 6764 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6765 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6766 /* a8 */ 6767 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6768 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6769 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6770 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6771 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6772 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6773 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6774 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6775 /* b0 */ 6776 { VEX_W_TABLE (VEX_W_0F38B0) }, 6777 { VEX_W_TABLE (VEX_W_0F38B1) }, 6778 { Bad_Opcode }, 6779 { Bad_Opcode }, 6780 { VEX_W_TABLE (VEX_W_0F38B4) }, 6781 { VEX_W_TABLE (VEX_W_0F38B5) }, 6782 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6783 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6784 /* b8 */ 6785 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6786 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6787 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6788 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6789 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6790 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6791 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, 6792 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, 6793 /* c0 */ 6794 { Bad_Opcode }, 6795 { Bad_Opcode }, 6796 { Bad_Opcode }, 6797 { Bad_Opcode }, 6798 { Bad_Opcode }, 6799 { Bad_Opcode }, 6800 { Bad_Opcode }, 6801 { Bad_Opcode }, 6802 /* c8 */ 6803 { Bad_Opcode }, 6804 { Bad_Opcode }, 6805 { Bad_Opcode }, 6806 { PREFIX_TABLE (PREFIX_VEX_0F38CB) }, 6807 { PREFIX_TABLE (PREFIX_VEX_0F38CC) }, 6808 { PREFIX_TABLE (PREFIX_VEX_0F38CD) }, 6809 { Bad_Opcode }, 6810 { VEX_W_TABLE (VEX_W_0F38CF) }, 6811 /* d0 */ 6812 { Bad_Opcode }, 6813 { Bad_Opcode }, 6814 { VEX_W_TABLE (VEX_W_0F38D2) }, 6815 { VEX_W_TABLE (VEX_W_0F38D3) }, 6816 { Bad_Opcode }, 6817 { Bad_Opcode }, 6818 { Bad_Opcode }, 6819 { Bad_Opcode }, 6820 /* d8 */ 6821 { Bad_Opcode }, 6822 { Bad_Opcode }, 6823 { VEX_W_TABLE (VEX_W_0F38DA) }, 6824 { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, 6825 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, 6826 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, 6827 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, 6828 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, 6829 /* e0 */ 6830 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6831 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6832 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6833 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6834 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6835 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6836 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6837 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6838 /* e8 */ 6839 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6840 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6841 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6842 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6843 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6844 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6845 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6846 { X86_64_TABLE (X86_64_VEX_0F38Ex) }, 6847 /* f0 */ 6848 { Bad_Opcode }, 6849 { Bad_Opcode }, 6850 { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, 6851 { VEX_LEN_TABLE (VEX_LEN_0F38F3) }, 6852 { Bad_Opcode }, 6853 { VEX_LEN_TABLE (VEX_LEN_0F38F5) }, 6854 { VEX_LEN_TABLE (VEX_LEN_0F38F6) }, 6855 { VEX_LEN_TABLE (VEX_LEN_0F38F7) }, 6856 /* f8 */ 6857 { Bad_Opcode }, 6858 { Bad_Opcode }, 6859 { Bad_Opcode }, 6860 { Bad_Opcode }, 6861 { Bad_Opcode }, 6862 { Bad_Opcode }, 6863 { Bad_Opcode }, 6864 { Bad_Opcode }, 6865 }, 6866 /* VEX_0F3A */ 6867 { 6868 /* 00 */ 6869 { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, 6870 { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, 6871 { VEX_W_TABLE (VEX_W_0F3A02) }, 6872 { Bad_Opcode }, 6873 { VEX_W_TABLE (VEX_W_0F3A04) }, 6874 { VEX_W_TABLE (VEX_W_0F3A05) }, 6875 { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, 6876 { Bad_Opcode }, 6877 /* 08 */ 6878 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, 6879 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, 6880 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA }, 6881 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA }, 6882 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6883 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6884 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6885 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6886 /* 10 */ 6887 { Bad_Opcode }, 6888 { Bad_Opcode }, 6889 { Bad_Opcode }, 6890 { Bad_Opcode }, 6891 { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, 6892 { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, 6893 { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, 6894 { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, 6895 /* 18 */ 6896 { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, 6897 { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, 6898 { Bad_Opcode }, 6899 { Bad_Opcode }, 6900 { Bad_Opcode }, 6901 { VEX_W_TABLE (VEX_W_0F3A1D) }, 6902 { Bad_Opcode }, 6903 { Bad_Opcode }, 6904 /* 20 */ 6905 { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, 6906 { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, 6907 { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, 6908 { Bad_Opcode }, 6909 { Bad_Opcode }, 6910 { Bad_Opcode }, 6911 { Bad_Opcode }, 6912 { Bad_Opcode }, 6913 /* 28 */ 6914 { Bad_Opcode }, 6915 { Bad_Opcode }, 6916 { Bad_Opcode }, 6917 { Bad_Opcode }, 6918 { Bad_Opcode }, 6919 { Bad_Opcode }, 6920 { Bad_Opcode }, 6921 { Bad_Opcode }, 6922 /* 30 */ 6923 { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, 6924 { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, 6925 { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, 6926 { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, 6927 { Bad_Opcode }, 6928 { Bad_Opcode }, 6929 { Bad_Opcode }, 6930 { Bad_Opcode }, 6931 /* 38 */ 6932 { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, 6933 { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, 6934 { Bad_Opcode }, 6935 { Bad_Opcode }, 6936 { Bad_Opcode }, 6937 { Bad_Opcode }, 6938 { Bad_Opcode }, 6939 { Bad_Opcode }, 6940 /* 40 */ 6941 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6942 { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, 6943 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 6944 { Bad_Opcode }, 6945 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, 6946 { Bad_Opcode }, 6947 { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, 6948 { Bad_Opcode }, 6949 /* 48 */ 6950 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, 6951 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, 6952 { VEX_W_TABLE (VEX_W_0F3A4A) }, 6953 { VEX_W_TABLE (VEX_W_0F3A4B) }, 6954 { VEX_W_TABLE (VEX_W_0F3A4C) }, 6955 { Bad_Opcode }, 6956 { Bad_Opcode }, 6957 { Bad_Opcode }, 6958 /* 50 */ 6959 { Bad_Opcode }, 6960 { Bad_Opcode }, 6961 { Bad_Opcode }, 6962 { Bad_Opcode }, 6963 { Bad_Opcode }, 6964 { Bad_Opcode }, 6965 { Bad_Opcode }, 6966 { Bad_Opcode }, 6967 /* 58 */ 6968 { Bad_Opcode }, 6969 { Bad_Opcode }, 6970 { Bad_Opcode }, 6971 { Bad_Opcode }, 6972 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6973 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6974 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6975 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6976 /* 60 */ 6977 { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, 6978 { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, 6979 { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, 6980 { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, 6981 { Bad_Opcode }, 6982 { Bad_Opcode }, 6983 { Bad_Opcode }, 6984 { Bad_Opcode }, 6985 /* 68 */ 6986 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6987 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6988 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6989 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6990 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6991 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 6992 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 6993 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 6994 /* 70 */ 6995 { Bad_Opcode }, 6996 { Bad_Opcode }, 6997 { Bad_Opcode }, 6998 { Bad_Opcode }, 6999 { Bad_Opcode }, 7000 { Bad_Opcode }, 7001 { Bad_Opcode }, 7002 { Bad_Opcode }, 7003 /* 78 */ 7004 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7005 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7006 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 7007 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 7008 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7009 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 7010 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, 7011 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, 7012 /* 80 */ 7013 { Bad_Opcode }, 7014 { Bad_Opcode }, 7015 { Bad_Opcode }, 7016 { Bad_Opcode }, 7017 { Bad_Opcode }, 7018 { Bad_Opcode }, 7019 { Bad_Opcode }, 7020 { Bad_Opcode }, 7021 /* 88 */ 7022 { Bad_Opcode }, 7023 { Bad_Opcode }, 7024 { Bad_Opcode }, 7025 { Bad_Opcode }, 7026 { Bad_Opcode }, 7027 { Bad_Opcode }, 7028 { Bad_Opcode }, 7029 { Bad_Opcode }, 7030 /* 90 */ 7031 { Bad_Opcode }, 7032 { Bad_Opcode }, 7033 { Bad_Opcode }, 7034 { Bad_Opcode }, 7035 { Bad_Opcode }, 7036 { Bad_Opcode }, 7037 { Bad_Opcode }, 7038 { Bad_Opcode }, 7039 /* 98 */ 7040 { Bad_Opcode }, 7041 { Bad_Opcode }, 7042 { Bad_Opcode }, 7043 { Bad_Opcode }, 7044 { Bad_Opcode }, 7045 { Bad_Opcode }, 7046 { Bad_Opcode }, 7047 { Bad_Opcode }, 7048 /* a0 */ 7049 { Bad_Opcode }, 7050 { Bad_Opcode }, 7051 { Bad_Opcode }, 7052 { Bad_Opcode }, 7053 { Bad_Opcode }, 7054 { Bad_Opcode }, 7055 { Bad_Opcode }, 7056 { Bad_Opcode }, 7057 /* a8 */ 7058 { Bad_Opcode }, 7059 { Bad_Opcode }, 7060 { Bad_Opcode }, 7061 { Bad_Opcode }, 7062 { Bad_Opcode }, 7063 { Bad_Opcode }, 7064 { Bad_Opcode }, 7065 { Bad_Opcode }, 7066 /* b0 */ 7067 { Bad_Opcode }, 7068 { Bad_Opcode }, 7069 { Bad_Opcode }, 7070 { Bad_Opcode }, 7071 { Bad_Opcode }, 7072 { Bad_Opcode }, 7073 { Bad_Opcode }, 7074 { Bad_Opcode }, 7075 /* b8 */ 7076 { Bad_Opcode }, 7077 { Bad_Opcode }, 7078 { Bad_Opcode }, 7079 { Bad_Opcode }, 7080 { Bad_Opcode }, 7081 { Bad_Opcode }, 7082 { Bad_Opcode }, 7083 { Bad_Opcode }, 7084 /* c0 */ 7085 { Bad_Opcode }, 7086 { Bad_Opcode }, 7087 { Bad_Opcode }, 7088 { Bad_Opcode }, 7089 { Bad_Opcode }, 7090 { Bad_Opcode }, 7091 { Bad_Opcode }, 7092 { Bad_Opcode }, 7093 /* c8 */ 7094 { Bad_Opcode }, 7095 { Bad_Opcode }, 7096 { Bad_Opcode }, 7097 { Bad_Opcode }, 7098 { Bad_Opcode }, 7099 { Bad_Opcode }, 7100 { VEX_W_TABLE (VEX_W_0F3ACE) }, 7101 { VEX_W_TABLE (VEX_W_0F3ACF) }, 7102 /* d0 */ 7103 { Bad_Opcode }, 7104 { Bad_Opcode }, 7105 { Bad_Opcode }, 7106 { Bad_Opcode }, 7107 { Bad_Opcode }, 7108 { Bad_Opcode }, 7109 { Bad_Opcode }, 7110 { Bad_Opcode }, 7111 /* d8 */ 7112 { Bad_Opcode }, 7113 { Bad_Opcode }, 7114 { Bad_Opcode }, 7115 { Bad_Opcode }, 7116 { Bad_Opcode }, 7117 { Bad_Opcode }, 7118 { VEX_W_TABLE (VEX_W_0F3ADE) }, 7119 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, 7120 /* e0 */ 7121 { Bad_Opcode }, 7122 { Bad_Opcode }, 7123 { Bad_Opcode }, 7124 { Bad_Opcode }, 7125 { Bad_Opcode }, 7126 { Bad_Opcode }, 7127 { Bad_Opcode }, 7128 { Bad_Opcode }, 7129 /* e8 */ 7130 { Bad_Opcode }, 7131 { Bad_Opcode }, 7132 { Bad_Opcode }, 7133 { Bad_Opcode }, 7134 { Bad_Opcode }, 7135 { Bad_Opcode }, 7136 { Bad_Opcode }, 7137 { Bad_Opcode }, 7138 /* f0 */ 7139 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, 7140 { Bad_Opcode }, 7141 { Bad_Opcode }, 7142 { Bad_Opcode }, 7143 { Bad_Opcode }, 7144 { Bad_Opcode }, 7145 { Bad_Opcode }, 7146 { Bad_Opcode }, 7147 /* f8 */ 7148 { Bad_Opcode }, 7149 { Bad_Opcode }, 7150 { Bad_Opcode }, 7151 { Bad_Opcode }, 7152 { Bad_Opcode }, 7153 { Bad_Opcode }, 7154 { Bad_Opcode }, 7155 { Bad_Opcode }, 7156 }, 7157 }; 7158 7159 #include "i386-dis-evex.h" 7160 7161 static const struct dis386 vex_len_table[][2] = { 7162 /* VEX_LEN_0F12_P_0 */ 7163 { 7164 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 7165 }, 7166 7167 /* VEX_LEN_0F12_P_2 */ 7168 { 7169 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, 7170 }, 7171 7172 /* VEX_LEN_0F13 */ 7173 { 7174 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE }, 7175 }, 7176 7177 /* VEX_LEN_0F16_P_0 */ 7178 { 7179 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 7180 }, 7181 7182 /* VEX_LEN_0F16_P_2 */ 7183 { 7184 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, 7185 }, 7186 7187 /* VEX_LEN_0F17 */ 7188 { 7189 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE }, 7190 }, 7191 7192 /* VEX_LEN_0F41 */ 7193 { 7194 { Bad_Opcode }, 7195 { VEX_W_TABLE (VEX_W_0F41_L_1) }, 7196 }, 7197 7198 /* VEX_LEN_0F42 */ 7199 { 7200 { Bad_Opcode }, 7201 { VEX_W_TABLE (VEX_W_0F42_L_1) }, 7202 }, 7203 7204 /* VEX_LEN_0F44 */ 7205 { 7206 { VEX_W_TABLE (VEX_W_0F44_L_0) }, 7207 }, 7208 7209 /* VEX_LEN_0F45 */ 7210 { 7211 { Bad_Opcode }, 7212 { VEX_W_TABLE (VEX_W_0F45_L_1) }, 7213 }, 7214 7215 /* VEX_LEN_0F46 */ 7216 { 7217 { Bad_Opcode }, 7218 { VEX_W_TABLE (VEX_W_0F46_L_1) }, 7219 }, 7220 7221 /* VEX_LEN_0F47 */ 7222 { 7223 { Bad_Opcode }, 7224 { VEX_W_TABLE (VEX_W_0F47_L_1) }, 7225 }, 7226 7227 /* VEX_LEN_0F4A */ 7228 { 7229 { Bad_Opcode }, 7230 { VEX_W_TABLE (VEX_W_0F4A_L_1) }, 7231 }, 7232 7233 /* VEX_LEN_0F4B */ 7234 { 7235 { Bad_Opcode }, 7236 { VEX_W_TABLE (VEX_W_0F4B_L_1) }, 7237 }, 7238 7239 /* VEX_LEN_0F6E */ 7240 { 7241 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA }, 7242 }, 7243 7244 /* VEX_LEN_0F77 */ 7245 { 7246 { "vzeroupper", { XX }, 0 }, 7247 { "vzeroall", { XX }, 0 }, 7248 }, 7249 7250 /* VEX_LEN_0F7E_P_1 */ 7251 { 7252 { "%XEvmovqY", { XMScalar, EXq }, 0 }, 7253 }, 7254 7255 /* VEX_LEN_0F7E_P_2 */ 7256 { 7257 { "%XEvmovK", { Edq, XMScalar }, 0 }, 7258 }, 7259 7260 /* VEX_LEN_0F90 */ 7261 { 7262 { VEX_W_TABLE (VEX_W_0F90_L_0) }, 7263 }, 7264 7265 /* VEX_LEN_0F91 */ 7266 { 7267 { VEX_W_TABLE (VEX_W_0F91_L_0) }, 7268 }, 7269 7270 /* VEX_LEN_0F92 */ 7271 { 7272 { VEX_W_TABLE (VEX_W_0F92_L_0) }, 7273 }, 7274 7275 /* VEX_LEN_0F93 */ 7276 { 7277 { VEX_W_TABLE (VEX_W_0F93_L_0) }, 7278 }, 7279 7280 /* VEX_LEN_0F98 */ 7281 { 7282 { VEX_W_TABLE (VEX_W_0F98_L_0) }, 7283 }, 7284 7285 /* VEX_LEN_0F99 */ 7286 { 7287 { VEX_W_TABLE (VEX_W_0F99_L_0) }, 7288 }, 7289 7290 /* VEX_LEN_0FAE_R_2 */ 7291 { 7292 { "vldmxcsr", { Md }, 0 }, 7293 }, 7294 7295 /* VEX_LEN_0FAE_R_3 */ 7296 { 7297 { "vstmxcsr", { Md }, 0 }, 7298 }, 7299 7300 /* VEX_LEN_0FC4 */ 7301 { 7302 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA }, 7303 }, 7304 7305 /* VEX_LEN_0FD6 */ 7306 { 7307 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA }, 7308 }, 7309 7310 /* VEX_LEN_0F3816 */ 7311 { 7312 { Bad_Opcode }, 7313 { VEX_W_TABLE (VEX_W_0F3816_L_1) }, 7314 }, 7315 7316 /* VEX_LEN_0F3819 */ 7317 { 7318 { Bad_Opcode }, 7319 { VEX_W_TABLE (VEX_W_0F3819_L_1) }, 7320 }, 7321 7322 /* VEX_LEN_0F381A */ 7323 { 7324 { Bad_Opcode }, 7325 { VEX_W_TABLE (VEX_W_0F381A_L_1) }, 7326 }, 7327 7328 /* VEX_LEN_0F3836 */ 7329 { 7330 { Bad_Opcode }, 7331 { VEX_W_TABLE (VEX_W_0F3836) }, 7332 }, 7333 7334 /* VEX_LEN_0F3841 */ 7335 { 7336 { "vphminposuw", { XM, EXx }, PREFIX_DATA }, 7337 }, 7338 7339 /* VEX_LEN_0F3848_X86_64 */ 7340 { 7341 { VEX_W_TABLE (VEX_W_0F3848_X86_64_L_0) }, 7342 }, 7343 7344 /* VEX_LEN_0F3849_X86_64 */ 7345 { 7346 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, 7347 }, 7348 7349 /* VEX_LEN_0F384A_X86_64_W_0 */ 7350 { 7351 { PREFIX_TABLE (PREFIX_VEX_0F384A_X86_64_W_0_L_0) }, 7352 }, 7353 7354 /* VEX_LEN_0F384B_X86_64 */ 7355 { 7356 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, 7357 }, 7358 7359 /* VEX_LEN_0F385A */ 7360 { 7361 { Bad_Opcode }, 7362 { VEX_W_TABLE (VEX_W_0F385A_L_0) }, 7363 }, 7364 7365 /* VEX_LEN_0F385C_X86_64 */ 7366 { 7367 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) }, 7368 }, 7369 7370 /* VEX_LEN_0F385E_X86_64 */ 7371 { 7372 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) }, 7373 }, 7374 7375 /* VEX_LEN_0F385F_X86_64 */ 7376 { 7377 { VEX_W_TABLE (VEX_W_0F385F_X86_64_L_0) }, 7378 }, 7379 7380 /* VEX_LEN_0F386B_X86_64 */ 7381 { 7382 { VEX_W_TABLE (VEX_W_0F386B_X86_64_L_0) }, 7383 }, 7384 7385 /* VEX_LEN_0F386C_X86_64 */ 7386 { 7387 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) }, 7388 }, 7389 7390 /* VEX_LEN_0F386E_X86_64 */ 7391 { 7392 { VEX_W_TABLE (VEX_W_0F386E_X86_64_L_0) }, 7393 }, 7394 7395 /* VEX_LEN_0F386F_X86_64 */ 7396 { 7397 { VEX_W_TABLE (VEX_W_0F386F_X86_64_L_0) }, 7398 }, 7399 7400 /* VEX_LEN_0F38CB_P_3_W_0 */ 7401 { 7402 { Bad_Opcode }, 7403 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 }, 7404 }, 7405 7406 /* VEX_LEN_0F38CC_P_3_W_0 */ 7407 { 7408 { Bad_Opcode }, 7409 { "vsha512msg1", { XM, Rxmmq }, 0 }, 7410 }, 7411 7412 /* VEX_LEN_0F38CD_P_3_W_0 */ 7413 { 7414 { Bad_Opcode }, 7415 { "vsha512msg2", { XM, Rymm }, 0 }, 7416 }, 7417 7418 /* VEX_LEN_0F38DA_W_0_P_0 */ 7419 { 7420 { "vsm3msg1", { XM, Vex, EXxmm }, 0 }, 7421 }, 7422 7423 /* VEX_LEN_0F38DA_W_0_P_2 */ 7424 { 7425 { "vsm3msg2", { XM, Vex, EXxmm }, 0 }, 7426 }, 7427 7428 /* VEX_LEN_0F38DB */ 7429 { 7430 { "vaesimc", { XM, EXx }, PREFIX_DATA }, 7431 }, 7432 7433 /* VEX_LEN_0F38F2 */ 7434 { 7435 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) }, 7436 }, 7437 7438 /* VEX_LEN_0F38F3 */ 7439 { 7440 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) }, 7441 }, 7442 7443 /* VEX_LEN_0F38F5 */ 7444 { 7445 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) }, 7446 }, 7447 7448 /* VEX_LEN_0F38F6 */ 7449 { 7450 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) }, 7451 }, 7452 7453 /* VEX_LEN_0F38F7 */ 7454 { 7455 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) }, 7456 }, 7457 7458 /* VEX_LEN_0F3A00 */ 7459 { 7460 { Bad_Opcode }, 7461 { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, 7462 }, 7463 7464 /* VEX_LEN_0F3A01 */ 7465 { 7466 { Bad_Opcode }, 7467 { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, 7468 }, 7469 7470 /* VEX_LEN_0F3A06 */ 7471 { 7472 { Bad_Opcode }, 7473 { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, 7474 }, 7475 7476 /* VEX_LEN_0F3A14 */ 7477 { 7478 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA }, 7479 }, 7480 7481 /* VEX_LEN_0F3A15 */ 7482 { 7483 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA }, 7484 }, 7485 7486 /* VEX_LEN_0F3A16 */ 7487 { 7488 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA }, 7489 }, 7490 7491 /* VEX_LEN_0F3A17 */ 7492 { 7493 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA }, 7494 }, 7495 7496 /* VEX_LEN_0F3A18 */ 7497 { 7498 { Bad_Opcode }, 7499 { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, 7500 }, 7501 7502 /* VEX_LEN_0F3A19 */ 7503 { 7504 { Bad_Opcode }, 7505 { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, 7506 }, 7507 7508 /* VEX_LEN_0F3A20 */ 7509 { 7510 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA }, 7511 }, 7512 7513 /* VEX_LEN_0F3A21 */ 7514 { 7515 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA }, 7516 }, 7517 7518 /* VEX_LEN_0F3A22 */ 7519 { 7520 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, 7521 }, 7522 7523 /* VEX_LEN_0F3A30 */ 7524 { 7525 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7526 }, 7527 7528 /* VEX_LEN_0F3A31 */ 7529 { 7530 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7531 }, 7532 7533 /* VEX_LEN_0F3A32 */ 7534 { 7535 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7536 }, 7537 7538 /* VEX_LEN_0F3A33 */ 7539 { 7540 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, 7541 }, 7542 7543 /* VEX_LEN_0F3A38 */ 7544 { 7545 { Bad_Opcode }, 7546 { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, 7547 }, 7548 7549 /* VEX_LEN_0F3A39 */ 7550 { 7551 { Bad_Opcode }, 7552 { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, 7553 }, 7554 7555 /* VEX_LEN_0F3A41 */ 7556 { 7557 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 7558 }, 7559 7560 /* VEX_LEN_0F3A46 */ 7561 { 7562 { Bad_Opcode }, 7563 { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, 7564 }, 7565 7566 /* VEX_LEN_0F3A60 */ 7567 { 7568 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 7569 }, 7570 7571 /* VEX_LEN_0F3A61 */ 7572 { 7573 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, 7574 }, 7575 7576 /* VEX_LEN_0F3A62 */ 7577 { 7578 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, 7579 }, 7580 7581 /* VEX_LEN_0F3A63 */ 7582 { 7583 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, 7584 }, 7585 7586 /* VEX_LEN_0F3ADE_W_0 */ 7587 { 7588 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 7589 }, 7590 7591 /* VEX_LEN_0F3ADF */ 7592 { 7593 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, 7594 }, 7595 7596 /* VEX_LEN_0F3AF0 */ 7597 { 7598 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, 7599 }, 7600 7601 /* VEX_LEN_MAP5_F8_X86_64 */ 7602 { 7603 { VEX_W_TABLE (VEX_W_MAP5_F8_X86_64_L_0) }, 7604 }, 7605 7606 /* VEX_LEN_MAP5_F9_X86_64 */ 7607 { 7608 { VEX_W_TABLE (VEX_W_MAP5_F9_X86_64_L_0) }, 7609 }, 7610 7611 /* VEX_LEN_MAP5_FD_X86_64 */ 7612 { 7613 { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) }, 7614 }, 7615 7616 /* VEX_LEN_MAP7_F6 */ 7617 { 7618 { VEX_W_TABLE (VEX_W_MAP7_F6_L_0) }, 7619 }, 7620 7621 /* VEX_LEN_MAP7_F8 */ 7622 { 7623 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) }, 7624 }, 7625 7626 /* VEX_LEN_XOP_08_85 */ 7627 { 7628 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, 7629 }, 7630 7631 /* VEX_LEN_XOP_08_86 */ 7632 { 7633 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) }, 7634 }, 7635 7636 /* VEX_LEN_XOP_08_87 */ 7637 { 7638 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) }, 7639 }, 7640 7641 /* VEX_LEN_XOP_08_8E */ 7642 { 7643 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) }, 7644 }, 7645 7646 /* VEX_LEN_XOP_08_8F */ 7647 { 7648 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) }, 7649 }, 7650 7651 /* VEX_LEN_XOP_08_95 */ 7652 { 7653 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) }, 7654 }, 7655 7656 /* VEX_LEN_XOP_08_96 */ 7657 { 7658 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) }, 7659 }, 7660 7661 /* VEX_LEN_XOP_08_97 */ 7662 { 7663 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) }, 7664 }, 7665 7666 /* VEX_LEN_XOP_08_9E */ 7667 { 7668 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) }, 7669 }, 7670 7671 /* VEX_LEN_XOP_08_9F */ 7672 { 7673 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) }, 7674 }, 7675 7676 /* VEX_LEN_XOP_08_A3 */ 7677 { 7678 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, 7679 }, 7680 7681 /* VEX_LEN_XOP_08_A6 */ 7682 { 7683 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) }, 7684 }, 7685 7686 /* VEX_LEN_XOP_08_B6 */ 7687 { 7688 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) }, 7689 }, 7690 7691 /* VEX_LEN_XOP_08_C0 */ 7692 { 7693 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) }, 7694 }, 7695 7696 /* VEX_LEN_XOP_08_C1 */ 7697 { 7698 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) }, 7699 }, 7700 7701 /* VEX_LEN_XOP_08_C2 */ 7702 { 7703 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) }, 7704 }, 7705 7706 /* VEX_LEN_XOP_08_C3 */ 7707 { 7708 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) }, 7709 }, 7710 7711 /* VEX_LEN_XOP_08_CC */ 7712 { 7713 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) }, 7714 }, 7715 7716 /* VEX_LEN_XOP_08_CD */ 7717 { 7718 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) }, 7719 }, 7720 7721 /* VEX_LEN_XOP_08_CE */ 7722 { 7723 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) }, 7724 }, 7725 7726 /* VEX_LEN_XOP_08_CF */ 7727 { 7728 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) }, 7729 }, 7730 7731 /* VEX_LEN_XOP_08_EC */ 7732 { 7733 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) }, 7734 }, 7735 7736 /* VEX_LEN_XOP_08_ED */ 7737 { 7738 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) }, 7739 }, 7740 7741 /* VEX_LEN_XOP_08_EE */ 7742 { 7743 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) }, 7744 }, 7745 7746 /* VEX_LEN_XOP_08_EF */ 7747 { 7748 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) }, 7749 }, 7750 7751 /* VEX_LEN_XOP_09_01 */ 7752 { 7753 { REG_TABLE (REG_XOP_09_01_L_0) }, 7754 }, 7755 7756 /* VEX_LEN_XOP_09_02 */ 7757 { 7758 { REG_TABLE (REG_XOP_09_02_L_0) }, 7759 }, 7760 7761 /* VEX_LEN_XOP_09_12 */ 7762 { 7763 { REG_TABLE (REG_XOP_09_12_L_0) }, 7764 }, 7765 7766 /* VEX_LEN_XOP_09_82_W_0 */ 7767 { 7768 { "vfrczss", { XM, EXd }, 0 }, 7769 }, 7770 7771 /* VEX_LEN_XOP_09_83_W_0 */ 7772 { 7773 { "vfrczsd", { XM, EXq }, 0 }, 7774 }, 7775 7776 /* VEX_LEN_XOP_09_90 */ 7777 { 7778 { "vprotb", { XM, EXx, VexW }, 0 }, 7779 }, 7780 7781 /* VEX_LEN_XOP_09_91 */ 7782 { 7783 { "vprotw", { XM, EXx, VexW }, 0 }, 7784 }, 7785 7786 /* VEX_LEN_XOP_09_92 */ 7787 { 7788 { "vprotd", { XM, EXx, VexW }, 0 }, 7789 }, 7790 7791 /* VEX_LEN_XOP_09_93 */ 7792 { 7793 { "vprotq", { XM, EXx, VexW }, 0 }, 7794 }, 7795 7796 /* VEX_LEN_XOP_09_94 */ 7797 { 7798 { "vpshlb", { XM, EXx, VexW }, 0 }, 7799 }, 7800 7801 /* VEX_LEN_XOP_09_95 */ 7802 { 7803 { "vpshlw", { XM, EXx, VexW }, 0 }, 7804 }, 7805 7806 /* VEX_LEN_XOP_09_96 */ 7807 { 7808 { "vpshld", { XM, EXx, VexW }, 0 }, 7809 }, 7810 7811 /* VEX_LEN_XOP_09_97 */ 7812 { 7813 { "vpshlq", { XM, EXx, VexW }, 0 }, 7814 }, 7815 7816 /* VEX_LEN_XOP_09_98 */ 7817 { 7818 { "vpshab", { XM, EXx, VexW }, 0 }, 7819 }, 7820 7821 /* VEX_LEN_XOP_09_99 */ 7822 { 7823 { "vpshaw", { XM, EXx, VexW }, 0 }, 7824 }, 7825 7826 /* VEX_LEN_XOP_09_9A */ 7827 { 7828 { "vpshad", { XM, EXx, VexW }, 0 }, 7829 }, 7830 7831 /* VEX_LEN_XOP_09_9B */ 7832 { 7833 { "vpshaq", { XM, EXx, VexW }, 0 }, 7834 }, 7835 7836 /* VEX_LEN_XOP_09_C1 */ 7837 { 7838 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) }, 7839 }, 7840 7841 /* VEX_LEN_XOP_09_C2 */ 7842 { 7843 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) }, 7844 }, 7845 7846 /* VEX_LEN_XOP_09_C3 */ 7847 { 7848 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) }, 7849 }, 7850 7851 /* VEX_LEN_XOP_09_C6 */ 7852 { 7853 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) }, 7854 }, 7855 7856 /* VEX_LEN_XOP_09_C7 */ 7857 { 7858 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) }, 7859 }, 7860 7861 /* VEX_LEN_XOP_09_CB */ 7862 { 7863 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) }, 7864 }, 7865 7866 /* VEX_LEN_XOP_09_D1 */ 7867 { 7868 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) }, 7869 }, 7870 7871 /* VEX_LEN_XOP_09_D2 */ 7872 { 7873 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) }, 7874 }, 7875 7876 /* VEX_LEN_XOP_09_D3 */ 7877 { 7878 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) }, 7879 }, 7880 7881 /* VEX_LEN_XOP_09_D6 */ 7882 { 7883 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) }, 7884 }, 7885 7886 /* VEX_LEN_XOP_09_D7 */ 7887 { 7888 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) }, 7889 }, 7890 7891 /* VEX_LEN_XOP_09_DB */ 7892 { 7893 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) }, 7894 }, 7895 7896 /* VEX_LEN_XOP_09_E1 */ 7897 { 7898 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) }, 7899 }, 7900 7901 /* VEX_LEN_XOP_09_E2 */ 7902 { 7903 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) }, 7904 }, 7905 7906 /* VEX_LEN_XOP_09_E3 */ 7907 { 7908 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) }, 7909 }, 7910 7911 /* VEX_LEN_XOP_0A_12 */ 7912 { 7913 { REG_TABLE (REG_XOP_0A_12_L_0) }, 7914 }, 7915 }; 7916 7917 #include "i386-dis-evex-len.h" 7918 7919 static const struct dis386 vex_w_table[][2] = { 7920 { 7921 /* VEX_W_0F41_L_1_M_1 */ 7922 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) }, 7923 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) }, 7924 }, 7925 { 7926 /* VEX_W_0F42_L_1_M_1 */ 7927 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) }, 7928 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) }, 7929 }, 7930 { 7931 /* VEX_W_0F44_L_0_M_1 */ 7932 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) }, 7933 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) }, 7934 }, 7935 { 7936 /* VEX_W_0F45_L_1_M_1 */ 7937 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) }, 7938 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) }, 7939 }, 7940 { 7941 /* VEX_W_0F46_L_1_M_1 */ 7942 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) }, 7943 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) }, 7944 }, 7945 { 7946 /* VEX_W_0F47_L_1_M_1 */ 7947 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) }, 7948 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) }, 7949 }, 7950 { 7951 /* VEX_W_0F4A_L_1_M_1 */ 7952 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) }, 7953 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) }, 7954 }, 7955 { 7956 /* VEX_W_0F4B_L_1_M_1 */ 7957 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) }, 7958 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) }, 7959 }, 7960 { 7961 /* VEX_W_0F90_L_0 */ 7962 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) }, 7963 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) }, 7964 }, 7965 { 7966 /* VEX_W_0F91_L_0_M_0 */ 7967 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) }, 7968 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) }, 7969 }, 7970 { 7971 /* VEX_W_0F92_L_0_M_1 */ 7972 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) }, 7973 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) }, 7974 }, 7975 { 7976 /* VEX_W_0F93_L_0_M_1 */ 7977 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) }, 7978 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) }, 7979 }, 7980 { 7981 /* VEX_W_0F98_L_0_M_1 */ 7982 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) }, 7983 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) }, 7984 }, 7985 { 7986 /* VEX_W_0F99_L_0_M_1 */ 7987 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) }, 7988 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) }, 7989 }, 7990 { 7991 /* VEX_W_0F380C */ 7992 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA }, 7993 }, 7994 { 7995 /* VEX_W_0F380D */ 7996 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, 7997 }, 7998 { 7999 /* VEX_W_0F380E */ 8000 { "vtestps", { XM, EXx }, PREFIX_DATA }, 8001 }, 8002 { 8003 /* VEX_W_0F380F */ 8004 { "vtestpd", { XM, EXx }, PREFIX_DATA }, 8005 }, 8006 { 8007 /* VEX_W_0F3813 */ 8008 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, 8009 }, 8010 { 8011 /* VEX_W_0F3816_L_1 */ 8012 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, 8013 }, 8014 { 8015 /* VEX_W_0F3818 */ 8016 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA }, 8017 }, 8018 { 8019 /* VEX_W_0F3819_L_1 */ 8020 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA }, 8021 }, 8022 { 8023 /* VEX_W_0F381A_L_1 */ 8024 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, 8025 }, 8026 { 8027 /* VEX_W_0F382C */ 8028 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, 8029 }, 8030 { 8031 /* VEX_W_0F382D */ 8032 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, 8033 }, 8034 { 8035 /* VEX_W_0F382E */ 8036 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, 8037 }, 8038 { 8039 /* VEX_W_0F382F */ 8040 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, 8041 }, 8042 { 8043 /* VEX_W_0F3836 */ 8044 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, 8045 }, 8046 { 8047 /* VEX_W_0F3846 */ 8048 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, 8049 }, 8050 { 8051 /* VEX_W_0F3848_X86_64_L_0 */ 8052 { PREFIX_TABLE (PREFIX_VEX_0F3848_X86_64_L_0_W_0) }, 8053 }, 8054 { 8055 /* VEX_W_0F3849_X86_64_L_0 */ 8056 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) }, 8057 }, 8058 { 8059 /* VEX_W_0F384A_X86_64 */ 8060 { VEX_LEN_TABLE (VEX_LEN_0F384A_X86_64_W_0) }, 8061 }, 8062 { 8063 /* VEX_W_0F384B_X86_64_L_0 */ 8064 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) }, 8065 }, 8066 { 8067 /* VEX_W_0F3850 */ 8068 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, 8069 }, 8070 { 8071 /* VEX_W_0F3851 */ 8072 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, 8073 }, 8074 { 8075 /* VEX_W_0F3852 */ 8076 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA }, 8077 }, 8078 { 8079 /* VEX_W_0F3853 */ 8080 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA }, 8081 }, 8082 { 8083 /* VEX_W_0F3858 */ 8084 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA }, 8085 }, 8086 { 8087 /* VEX_W_0F3859 */ 8088 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA }, 8089 }, 8090 { 8091 /* VEX_W_0F385A_L_0 */ 8092 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, 8093 }, 8094 { 8095 /* VEX_W_0F385C_X86_64_L_0 */ 8096 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) }, 8097 }, 8098 { 8099 /* VEX_W_0F385E_X86_64_L_0 */ 8100 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) }, 8101 }, 8102 { 8103 /* VEX_W_0F385F_X86_64_L_0 */ 8104 { PREFIX_TABLE (PREFIX_VEX_0F385F_X86_64_L_0_W_0) }, 8105 }, 8106 { 8107 /* VEX_W_0F386B_X86_64_L_0 */ 8108 { PREFIX_TABLE (PREFIX_VEX_0F386B_X86_64_L_0_W_0) }, 8109 }, 8110 { 8111 /* VEX_W_0F386C_X86_64_L_0 */ 8112 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) }, 8113 }, 8114 { 8115 /* VEX_W_0F386E_X86_64_L_0 */ 8116 { PREFIX_TABLE (PREFIX_VEX_0F386E_X86_64_L_0_W_0) }, 8117 }, 8118 { 8119 /* VEX_W_0F386F_X86_64_L_0 */ 8120 { PREFIX_TABLE (PREFIX_VEX_0F386F_X86_64_L_0_W_0) }, 8121 }, 8122 { 8123 /* VEX_W_0F3872_P_1 */ 8124 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 }, 8125 }, 8126 { 8127 /* VEX_W_0F3878 */ 8128 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA }, 8129 }, 8130 { 8131 /* VEX_W_0F3879 */ 8132 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, 8133 }, 8134 { 8135 /* VEX_W_0F38B0 */ 8136 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) }, 8137 }, 8138 { 8139 /* VEX_W_0F38B1 */ 8140 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) }, 8141 }, 8142 { 8143 /* VEX_W_0F38B4 */ 8144 { Bad_Opcode }, 8145 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, 8146 }, 8147 { 8148 /* VEX_W_0F38B5 */ 8149 { Bad_Opcode }, 8150 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, 8151 }, 8152 { 8153 /* VEX_W_0F38CB_P_3 */ 8154 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) }, 8155 }, 8156 { 8157 /* VEX_W_0F38CC_P_3 */ 8158 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) }, 8159 }, 8160 { 8161 /* VEX_W_0F38CD_P_3 */ 8162 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) }, 8163 }, 8164 { 8165 /* VEX_W_0F38CF */ 8166 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, 8167 }, 8168 { 8169 /* VEX_W_0F38D2 */ 8170 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) }, 8171 }, 8172 { 8173 /* VEX_W_0F38D3 */ 8174 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) }, 8175 }, 8176 { 8177 /* VEX_W_0F38DA */ 8178 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) }, 8179 }, 8180 { 8181 /* VEX_W_0F3A00_L_1 */ 8182 { Bad_Opcode }, 8183 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA }, 8184 }, 8185 { 8186 /* VEX_W_0F3A01_L_1 */ 8187 { Bad_Opcode }, 8188 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA }, 8189 }, 8190 { 8191 /* VEX_W_0F3A02 */ 8192 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 8193 }, 8194 { 8195 /* VEX_W_0F3A04 */ 8196 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA }, 8197 }, 8198 { 8199 /* VEX_W_0F3A05 */ 8200 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, 8201 }, 8202 { 8203 /* VEX_W_0F3A06_L_1 */ 8204 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 8205 }, 8206 { 8207 /* VEX_W_0F3A18_L_1 */ 8208 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 8209 }, 8210 { 8211 /* VEX_W_0F3A19_L_1 */ 8212 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, 8213 }, 8214 { 8215 /* VEX_W_0F3A1D */ 8216 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, 8217 }, 8218 { 8219 /* VEX_W_0F3A38_L_1 */ 8220 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, 8221 }, 8222 { 8223 /* VEX_W_0F3A39_L_1 */ 8224 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, 8225 }, 8226 { 8227 /* VEX_W_0F3A46_L_1 */ 8228 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 8229 }, 8230 { 8231 /* VEX_W_0F3A4A */ 8232 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 8233 }, 8234 { 8235 /* VEX_W_0F3A4B */ 8236 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 8237 }, 8238 { 8239 /* VEX_W_0F3A4C */ 8240 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, 8241 }, 8242 { 8243 /* VEX_W_0F3ACE */ 8244 { Bad_Opcode }, 8245 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 8246 }, 8247 { 8248 /* VEX_W_0F3ACF */ 8249 { Bad_Opcode }, 8250 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, 8251 }, 8252 { 8253 /* VEX_W_0F3ADE */ 8254 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, 8255 }, 8256 { 8257 /* VEX_W_MAP5_F8_X86_64 */ 8258 { PREFIX_TABLE (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0) }, 8259 }, 8260 { 8261 /* VEX_W_MAP5_F9_X86_64 */ 8262 { PREFIX_TABLE (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0) }, 8263 }, 8264 { 8265 /* VEX_W_MAP5_FD_X86_64 */ 8266 { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) }, 8267 }, 8268 { 8269 /* VEX_W_MAP7_F6_L_0 */ 8270 { REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) }, 8271 }, 8272 { 8273 /* VEX_W_MAP7_F8_L_0 */ 8274 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) }, 8275 }, 8276 /* VEX_W_XOP_08_85_L_0 */ 8277 { 8278 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, 8279 }, 8280 /* VEX_W_XOP_08_86_L_0 */ 8281 { 8282 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8283 }, 8284 /* VEX_W_XOP_08_87_L_0 */ 8285 { 8286 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, 8287 }, 8288 /* VEX_W_XOP_08_8E_L_0 */ 8289 { 8290 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8291 }, 8292 /* VEX_W_XOP_08_8F_L_0 */ 8293 { 8294 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, 8295 }, 8296 /* VEX_W_XOP_08_95_L_0 */ 8297 { 8298 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, 8299 }, 8300 /* VEX_W_XOP_08_96_L_0 */ 8301 { 8302 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8303 }, 8304 /* VEX_W_XOP_08_97_L_0 */ 8305 { 8306 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, 8307 }, 8308 /* VEX_W_XOP_08_9E_L_0 */ 8309 { 8310 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8311 }, 8312 /* VEX_W_XOP_08_9F_L_0 */ 8313 { 8314 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, 8315 }, 8316 /* VEX_W_XOP_08_A6_L_0 */ 8317 { 8318 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8319 }, 8320 /* VEX_W_XOP_08_B6_L_0 */ 8321 { 8322 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, 8323 }, 8324 /* VEX_W_XOP_08_C0_L_0 */ 8325 { 8326 { "vprotb", { XM, EXx, Ib }, 0 }, 8327 }, 8328 /* VEX_W_XOP_08_C1_L_0 */ 8329 { 8330 { "vprotw", { XM, EXx, Ib }, 0 }, 8331 }, 8332 /* VEX_W_XOP_08_C2_L_0 */ 8333 { 8334 { "vprotd", { XM, EXx, Ib }, 0 }, 8335 }, 8336 /* VEX_W_XOP_08_C3_L_0 */ 8337 { 8338 { "vprotq", { XM, EXx, Ib }, 0 }, 8339 }, 8340 /* VEX_W_XOP_08_CC_L_0 */ 8341 { 8342 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, 8343 }, 8344 /* VEX_W_XOP_08_CD_L_0 */ 8345 { 8346 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, 8347 }, 8348 /* VEX_W_XOP_08_CE_L_0 */ 8349 { 8350 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, 8351 }, 8352 /* VEX_W_XOP_08_CF_L_0 */ 8353 { 8354 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, 8355 }, 8356 /* VEX_W_XOP_08_EC_L_0 */ 8357 { 8358 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, 8359 }, 8360 /* VEX_W_XOP_08_ED_L_0 */ 8361 { 8362 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, 8363 }, 8364 /* VEX_W_XOP_08_EE_L_0 */ 8365 { 8366 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, 8367 }, 8368 /* VEX_W_XOP_08_EF_L_0 */ 8369 { 8370 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, 8371 }, 8372 /* VEX_W_XOP_09_80 */ 8373 { 8374 { "vfrczps", { XM, EXx }, 0 }, 8375 }, 8376 /* VEX_W_XOP_09_81 */ 8377 { 8378 { "vfrczpd", { XM, EXx }, 0 }, 8379 }, 8380 /* VEX_W_XOP_09_82 */ 8381 { 8382 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) }, 8383 }, 8384 /* VEX_W_XOP_09_83 */ 8385 { 8386 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) }, 8387 }, 8388 /* VEX_W_XOP_09_C1_L_0 */ 8389 { 8390 { "vphaddbw", { XM, EXxmm }, 0 }, 8391 }, 8392 /* VEX_W_XOP_09_C2_L_0 */ 8393 { 8394 { "vphaddbd", { XM, EXxmm }, 0 }, 8395 }, 8396 /* VEX_W_XOP_09_C3_L_0 */ 8397 { 8398 { "vphaddbq", { XM, EXxmm }, 0 }, 8399 }, 8400 /* VEX_W_XOP_09_C6_L_0 */ 8401 { 8402 { "vphaddwd", { XM, EXxmm }, 0 }, 8403 }, 8404 /* VEX_W_XOP_09_C7_L_0 */ 8405 { 8406 { "vphaddwq", { XM, EXxmm }, 0 }, 8407 }, 8408 /* VEX_W_XOP_09_CB_L_0 */ 8409 { 8410 { "vphadddq", { XM, EXxmm }, 0 }, 8411 }, 8412 /* VEX_W_XOP_09_D1_L_0 */ 8413 { 8414 { "vphaddubw", { XM, EXxmm }, 0 }, 8415 }, 8416 /* VEX_W_XOP_09_D2_L_0 */ 8417 { 8418 { "vphaddubd", { XM, EXxmm }, 0 }, 8419 }, 8420 /* VEX_W_XOP_09_D3_L_0 */ 8421 { 8422 { "vphaddubq", { XM, EXxmm }, 0 }, 8423 }, 8424 /* VEX_W_XOP_09_D6_L_0 */ 8425 { 8426 { "vphadduwd", { XM, EXxmm }, 0 }, 8427 }, 8428 /* VEX_W_XOP_09_D7_L_0 */ 8429 { 8430 { "vphadduwq", { XM, EXxmm }, 0 }, 8431 }, 8432 /* VEX_W_XOP_09_DB_L_0 */ 8433 { 8434 { "vphaddudq", { XM, EXxmm }, 0 }, 8435 }, 8436 /* VEX_W_XOP_09_E1_L_0 */ 8437 { 8438 { "vphsubbw", { XM, EXxmm }, 0 }, 8439 }, 8440 /* VEX_W_XOP_09_E2_L_0 */ 8441 { 8442 { "vphsubwd", { XM, EXxmm }, 0 }, 8443 }, 8444 /* VEX_W_XOP_09_E3_L_0 */ 8445 { 8446 { "vphsubdq", { XM, EXxmm }, 0 }, 8447 }, 8448 8449 #include "i386-dis-evex-w.h" 8450 }; 8451 8452 static const struct dis386 mod_table[][2] = { 8453 { 8454 /* MOD_62_32BIT */ 8455 { "bound{S|}", { Gv, Ma }, 0 }, 8456 { EVEX_TABLE () }, 8457 }, 8458 { 8459 /* MOD_C4_32BIT */ 8460 { "lesS", { Gv, Mp }, 0 }, 8461 { VEX_C4_TABLE () }, 8462 }, 8463 { 8464 /* MOD_C5_32BIT */ 8465 { "ldsS", { Gv, Mp }, 0 }, 8466 { VEX_C5_TABLE () }, 8467 }, 8468 { 8469 /* MOD_0F01_REG_0 */ 8470 { X86_64_TABLE (X86_64_0F01_REG_0) }, 8471 { RM_TABLE (RM_0F01_REG_0) }, 8472 }, 8473 { 8474 /* MOD_0F01_REG_1 */ 8475 { X86_64_TABLE (X86_64_0F01_REG_1) }, 8476 { RM_TABLE (RM_0F01_REG_1) }, 8477 }, 8478 { 8479 /* MOD_0F01_REG_2 */ 8480 { X86_64_TABLE (X86_64_0F01_REG_2) }, 8481 { RM_TABLE (RM_0F01_REG_2) }, 8482 }, 8483 { 8484 /* MOD_0F01_REG_3 */ 8485 { X86_64_TABLE (X86_64_0F01_REG_3) }, 8486 { RM_TABLE (RM_0F01_REG_3) }, 8487 }, 8488 { 8489 /* MOD_0F01_REG_5 */ 8490 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, 8491 { RM_TABLE (RM_0F01_REG_5_MOD_3) }, 8492 }, 8493 { 8494 /* MOD_0F01_REG_7 */ 8495 { "invlpg", { Mb }, 0 }, 8496 { RM_TABLE (RM_0F01_REG_7_MOD_3) }, 8497 }, 8498 { 8499 /* MOD_0F12_PREFIX_0 */ 8500 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 }, 8501 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 }, 8502 }, 8503 { 8504 /* MOD_0F16_PREFIX_0 */ 8505 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 }, 8506 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 }, 8507 }, 8508 { 8509 /* MOD_0F18_REG_0 */ 8510 { "prefetchnta", { Mb }, 0 }, 8511 { "nopQ", { Ev }, 0 }, 8512 }, 8513 { 8514 /* MOD_0F18_REG_1 */ 8515 { "prefetcht0", { Mb }, 0 }, 8516 { "nopQ", { Ev }, 0 }, 8517 }, 8518 { 8519 /* MOD_0F18_REG_2 */ 8520 { "prefetcht1", { Mb }, 0 }, 8521 { "nopQ", { Ev }, 0 }, 8522 }, 8523 { 8524 /* MOD_0F18_REG_3 */ 8525 { "prefetcht2", { Mb }, 0 }, 8526 { "nopQ", { Ev }, 0 }, 8527 }, 8528 { 8529 /* MOD_0F18_REG_4 */ 8530 { "prefetchrst2", { Mb }, 0 }, 8531 { "nopQ", { Ev }, 0 }, 8532 }, 8533 { 8534 /* MOD_0F18_REG_6 */ 8535 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) }, 8536 { "nopQ", { Ev }, 0 }, 8537 }, 8538 { 8539 /* MOD_0F18_REG_7 */ 8540 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) }, 8541 { "nopQ", { Ev }, 0 }, 8542 }, 8543 { 8544 /* MOD_0F1A_PREFIX_0 */ 8545 { "bndldx", { Gbnd, Mv_bnd }, 0 }, 8546 { "nopQ", { Ev }, 0 }, 8547 }, 8548 { 8549 /* MOD_0F1B_PREFIX_0 */ 8550 { "bndstx", { Mv_bnd, Gbnd }, 0 }, 8551 { "nopQ", { Ev }, 0 }, 8552 }, 8553 { 8554 /* MOD_0F1B_PREFIX_1 */ 8555 { "bndmk", { Gbnd, Mv_bnd }, 0 }, 8556 { "nopQ", { Ev }, PREFIX_IGNORED }, 8557 }, 8558 { 8559 /* MOD_0F1C_PREFIX_0 */ 8560 { REG_TABLE (REG_0F1C_P_0_MOD_0) }, 8561 { "nopQ", { Ev }, 0 }, 8562 }, 8563 { 8564 /* MOD_0F1E_PREFIX_1 */ 8565 { "nopQ", { Ev }, PREFIX_IGNORED }, 8566 { REG_TABLE (REG_0F1E_P_1_MOD_3) }, 8567 }, 8568 { 8569 /* MOD_0FAE_REG_0 */ 8570 { "fxsave", { FXSAVE }, 0 }, 8571 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, 8572 }, 8573 { 8574 /* MOD_0FAE_REG_1 */ 8575 { "fxrstor", { FXSAVE }, 0 }, 8576 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, 8577 }, 8578 { 8579 /* MOD_0FAE_REG_2 */ 8580 { "ldmxcsr", { Md }, 0 }, 8581 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, 8582 }, 8583 { 8584 /* MOD_0FAE_REG_3 */ 8585 { "stmxcsr", { Md }, 0 }, 8586 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, 8587 }, 8588 { 8589 /* MOD_0FAE_REG_4 */ 8590 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, 8591 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, 8592 }, 8593 { 8594 /* MOD_0FAE_REG_5 */ 8595 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL }, 8596 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, 8597 }, 8598 { 8599 /* MOD_0FAE_REG_6 */ 8600 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, 8601 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, 8602 }, 8603 { 8604 /* MOD_0FAE_REG_7 */ 8605 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, 8606 { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, 8607 }, 8608 { 8609 /* MOD_0FC7_REG_6 */ 8610 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, 8611 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } 8612 }, 8613 { 8614 /* MOD_0FC7_REG_7 */ 8615 { "vmptrst", { Mq }, 0 }, 8616 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } 8617 }, 8618 { 8619 /* MOD_0F38DC_PREFIX_1 */ 8620 { "aesenc128kl", { XM, M }, 0 }, 8621 { "loadiwkey", { XM, EXx }, 0 }, 8622 }, 8623 /* MOD_0F38F8 */ 8624 { 8625 { PREFIX_TABLE (PREFIX_0F38F8_M_0) }, 8626 { X86_64_TABLE (X86_64_0F38F8_M_1) }, 8627 }, 8628 { 8629 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ 8630 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, 8631 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) }, 8632 }, 8633 8634 #include "i386-dis-evex-mod.h" 8635 }; 8636 8637 static const struct dis386 rm_table[][8] = { 8638 { 8639 /* RM_C6_REG_7 */ 8640 { "xabort", { Skip_MODRM, Ib }, 0 }, 8641 }, 8642 { 8643 /* RM_C7_REG_7 */ 8644 { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, 8645 }, 8646 { 8647 /* RM_0F01_REG_0 */ 8648 { "enclv", { Skip_MODRM }, 0 }, 8649 { "vmcall", { Skip_MODRM }, 0 }, 8650 { "vmlaunch", { Skip_MODRM }, 0 }, 8651 { "vmresume", { Skip_MODRM }, 0 }, 8652 { "vmxoff", { Skip_MODRM }, 0 }, 8653 { "pconfig", { Skip_MODRM }, 0 }, 8654 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, 8655 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) }, 8656 }, 8657 { 8658 /* RM_0F01_REG_1 */ 8659 { "monitor", { { OP_Monitor, 0 } }, 0 }, 8660 { "mwait", { { OP_Mwait, 0 } }, 0 }, 8661 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) }, 8662 { "stac", { Skip_MODRM }, 0 }, 8663 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, 8664 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, 8665 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, 8666 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, 8667 }, 8668 { 8669 /* RM_0F01_REG_2 */ 8670 { "xgetbv", { Skip_MODRM }, 0 }, 8671 { "xsetbv", { Skip_MODRM }, 0 }, 8672 { Bad_Opcode }, 8673 { Bad_Opcode }, 8674 { "vmfunc", { Skip_MODRM }, 0 }, 8675 { "xend", { Skip_MODRM }, 0 }, 8676 { "xtest", { Skip_MODRM }, 0 }, 8677 { "enclu", { Skip_MODRM }, 0 }, 8678 }, 8679 { 8680 /* RM_0F01_REG_3 */ 8681 { "vmrun", { Skip_MODRM }, 0 }, 8682 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, 8683 { "vmload", { Skip_MODRM }, 0 }, 8684 { "vmsave", { Skip_MODRM }, 0 }, 8685 { "stgi", { Skip_MODRM }, 0 }, 8686 { "clgi", { Skip_MODRM }, 0 }, 8687 { "skinit", { Skip_MODRM }, 0 }, 8688 { "invlpga", { Skip_MODRM }, 0 }, 8689 }, 8690 { 8691 /* RM_0F01_REG_5_MOD_3 */ 8692 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, 8693 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, 8694 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, 8695 { Bad_Opcode }, 8696 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) }, 8697 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) }, 8698 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) }, 8699 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) }, 8700 }, 8701 { 8702 /* RM_0F01_REG_7_MOD_3 */ 8703 { "swapgs", { Skip_MODRM }, 0 }, 8704 { "rdtscp", { Skip_MODRM }, 0 }, 8705 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, 8706 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, 8707 { "clzero", { Skip_MODRM }, 0 }, 8708 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) }, 8709 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, 8710 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, 8711 }, 8712 { 8713 /* RM_0F1E_P_1_MOD_3_REG_7 */ 8714 { "nopQ", { Ev }, PREFIX_IGNORED }, 8715 { "nopQ", { Ev }, PREFIX_IGNORED }, 8716 { "endbr64", { Skip_MODRM }, 0 }, 8717 { "endbr32", { Skip_MODRM }, 0 }, 8718 { "nopQ", { Ev }, PREFIX_IGNORED }, 8719 { "nopQ", { Ev }, PREFIX_IGNORED }, 8720 { "nopQ", { Ev }, PREFIX_IGNORED }, 8721 { "nopQ", { Ev }, PREFIX_IGNORED }, 8722 }, 8723 { 8724 /* RM_0FAE_REG_6_MOD_3 */ 8725 { "mfence", { Skip_MODRM }, 0 }, 8726 }, 8727 { 8728 /* RM_0FAE_REG_7_MOD_3 */ 8729 { "sfence", { Skip_MODRM }, 0 }, 8730 }, 8731 { 8732 /* RM_0F3A0F_P_1_R_0 */ 8733 { "hreset", { Skip_MODRM, Ib }, 0 }, 8734 }, 8735 { 8736 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */ 8737 { "tilerelease", { Skip_MODRM }, 0 }, 8738 }, 8739 { 8740 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */ 8741 { "tilezero", { TMM, Skip_MODRM }, 0 }, 8742 }, 8743 }; 8744 8745 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") 8746 8747 /* The values used here must be non-zero, fit in 'unsigned char', and not be 8748 in conflict with actual prefix opcodes. */ 8749 #define REP_PREFIX 0x01 8750 #define XACQUIRE_PREFIX 0x02 8751 #define XRELEASE_PREFIX 0x03 8752 #define BND_PREFIX 0x04 8753 #define NOTRACK_PREFIX 0x05 8754 8755 static enum { 8756 ckp_okay, 8757 ckp_bogus, 8758 ckp_fetch_error, 8759 } 8760 ckprefix (instr_info *ins) 8761 { 8762 int i, length; 8763 uint8_t newrex; 8764 8765 i = 0; 8766 length = 0; 8767 /* The maximum instruction length is 15bytes. */ 8768 while (length < MAX_CODE_LENGTH - 1) 8769 { 8770 if (!fetch_code (ins->info, ins->codep + 1)) 8771 return ckp_fetch_error; 8772 newrex = 0; 8773 switch (*ins->codep) 8774 { 8775 /* REX prefixes family. */ 8776 case 0x40: 8777 case 0x41: 8778 case 0x42: 8779 case 0x43: 8780 case 0x44: 8781 case 0x45: 8782 case 0x46: 8783 case 0x47: 8784 case 0x48: 8785 case 0x49: 8786 case 0x4a: 8787 case 0x4b: 8788 case 0x4c: 8789 case 0x4d: 8790 case 0x4e: 8791 case 0x4f: 8792 if (ins->address_mode == mode_64bit) 8793 newrex = *ins->codep; 8794 else 8795 return ckp_okay; 8796 ins->last_rex_prefix = i; 8797 break; 8798 /* REX2 must be the last prefix. */ 8799 case REX2_OPCODE: 8800 if (ins->address_mode == mode_64bit) 8801 { 8802 if (ins->last_rex_prefix >= 0) 8803 return ckp_bogus; 8804 8805 ins->codep++; 8806 if (!fetch_code (ins->info, ins->codep + 1)) 8807 return ckp_fetch_error; 8808 ins->rex2_payload = *ins->codep; 8809 ins->rex2 = ins->rex2_payload >> 4; 8810 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE; 8811 ins->codep++; 8812 ins->last_rex2_prefix = i; 8813 ins->all_prefixes[i] = REX2_OPCODE; 8814 } 8815 return ckp_okay; 8816 case 0xf3: 8817 ins->prefixes |= PREFIX_REPZ; 8818 ins->last_repz_prefix = i; 8819 break; 8820 case 0xf2: 8821 ins->prefixes |= PREFIX_REPNZ; 8822 ins->last_repnz_prefix = i; 8823 break; 8824 case 0xf0: 8825 ins->prefixes |= PREFIX_LOCK; 8826 ins->last_lock_prefix = i; 8827 break; 8828 case 0x2e: 8829 ins->prefixes |= PREFIX_CS; 8830 ins->last_seg_prefix = i; 8831 if (ins->address_mode != mode_64bit) 8832 ins->active_seg_prefix = PREFIX_CS; 8833 break; 8834 case 0x36: 8835 ins->prefixes |= PREFIX_SS; 8836 ins->last_seg_prefix = i; 8837 if (ins->address_mode != mode_64bit) 8838 ins->active_seg_prefix = PREFIX_SS; 8839 break; 8840 case 0x3e: 8841 ins->prefixes |= PREFIX_DS; 8842 ins->last_seg_prefix = i; 8843 if (ins->address_mode != mode_64bit) 8844 ins->active_seg_prefix = PREFIX_DS; 8845 break; 8846 case 0x26: 8847 ins->prefixes |= PREFIX_ES; 8848 ins->last_seg_prefix = i; 8849 if (ins->address_mode != mode_64bit) 8850 ins->active_seg_prefix = PREFIX_ES; 8851 break; 8852 case 0x64: 8853 ins->prefixes |= PREFIX_FS; 8854 ins->last_seg_prefix = i; 8855 ins->active_seg_prefix = PREFIX_FS; 8856 break; 8857 case 0x65: 8858 ins->prefixes |= PREFIX_GS; 8859 ins->last_seg_prefix = i; 8860 ins->active_seg_prefix = PREFIX_GS; 8861 break; 8862 case 0x66: 8863 ins->prefixes |= PREFIX_DATA; 8864 ins->last_data_prefix = i; 8865 break; 8866 case 0x67: 8867 ins->prefixes |= PREFIX_ADDR; 8868 ins->last_addr_prefix = i; 8869 break; 8870 case FWAIT_OPCODE: 8871 /* fwait is really an instruction. If there are prefixes 8872 before the fwait, they belong to the fwait, *not* to the 8873 following instruction. */ 8874 ins->fwait_prefix = i; 8875 if (ins->prefixes || ins->rex) 8876 { 8877 ins->prefixes |= PREFIX_FWAIT; 8878 ins->codep++; 8879 /* This ensures that the previous REX prefixes are noticed 8880 as unused prefixes, as in the return case below. */ 8881 return ins->rex ? ckp_bogus : ckp_okay; 8882 } 8883 ins->prefixes = PREFIX_FWAIT; 8884 break; 8885 default: 8886 return ckp_okay; 8887 } 8888 /* Rex is ignored when followed by another prefix. */ 8889 if (ins->rex) 8890 return ckp_bogus; 8891 if (*ins->codep != FWAIT_OPCODE) 8892 ins->all_prefixes[i++] = *ins->codep; 8893 ins->rex = newrex; 8894 ins->codep++; 8895 length++; 8896 } 8897 return ckp_bogus; 8898 } 8899 8900 /* Return the name of the prefix byte PREF, or NULL if PREF is not a 8901 prefix byte. */ 8902 8903 static const char * 8904 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag) 8905 { 8906 static const char *rexes [16] = 8907 { 8908 "rex", /* 0x40 */ 8909 "rex.B", /* 0x41 */ 8910 "rex.X", /* 0x42 */ 8911 "rex.XB", /* 0x43 */ 8912 "rex.R", /* 0x44 */ 8913 "rex.RB", /* 0x45 */ 8914 "rex.RX", /* 0x46 */ 8915 "rex.RXB", /* 0x47 */ 8916 "rex.W", /* 0x48 */ 8917 "rex.WB", /* 0x49 */ 8918 "rex.WX", /* 0x4a */ 8919 "rex.WXB", /* 0x4b */ 8920 "rex.WR", /* 0x4c */ 8921 "rex.WRB", /* 0x4d */ 8922 "rex.WRX", /* 0x4e */ 8923 "rex.WRXB", /* 0x4f */ 8924 }; 8925 8926 switch (pref) 8927 { 8928 /* REX prefixes family. */ 8929 case 0x40: 8930 case 0x41: 8931 case 0x42: 8932 case 0x43: 8933 case 0x44: 8934 case 0x45: 8935 case 0x46: 8936 case 0x47: 8937 case 0x48: 8938 case 0x49: 8939 case 0x4a: 8940 case 0x4b: 8941 case 0x4c: 8942 case 0x4d: 8943 case 0x4e: 8944 case 0x4f: 8945 return rexes [pref - 0x40]; 8946 case 0xf3: 8947 return "repz"; 8948 case 0xf2: 8949 return "repnz"; 8950 case 0xf0: 8951 return "lock"; 8952 case 0x2e: 8953 return "cs"; 8954 case 0x36: 8955 return "ss"; 8956 case 0x3e: 8957 return "ds"; 8958 case 0x26: 8959 return "es"; 8960 case 0x64: 8961 return "fs"; 8962 case 0x65: 8963 return "gs"; 8964 case 0x66: 8965 return (sizeflag & DFLAG) ? "data16" : "data32"; 8966 case 0x67: 8967 if (mode == mode_64bit) 8968 return (sizeflag & AFLAG) ? "addr32" : "addr64"; 8969 else 8970 return (sizeflag & AFLAG) ? "addr16" : "addr32"; 8971 case FWAIT_OPCODE: 8972 return "fwait"; 8973 case REP_PREFIX: 8974 return "rep"; 8975 case XACQUIRE_PREFIX: 8976 return "xacquire"; 8977 case XRELEASE_PREFIX: 8978 return "xrelease"; 8979 case BND_PREFIX: 8980 return "bnd"; 8981 case NOTRACK_PREFIX: 8982 return "notrack"; 8983 case REX2_OPCODE: 8984 return "rex2"; 8985 default: 8986 return NULL; 8987 } 8988 } 8989 8990 void 8991 print_i386_disassembler_options (FILE *stream) 8992 { 8993 fprintf (stream, _("\n\ 8994 The following i386/x86-64 specific disassembler options are supported for use\n\ 8995 with the -M switch (multiple options should be separated by commas):\n")); 8996 8997 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); 8998 fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); 8999 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); 9000 fprintf (stream, _(" att Display instruction in AT&T syntax\n")); 9001 fprintf (stream, _(" intel Display instruction in Intel syntax\n")); 9002 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n" 9003 " Display instruction with AT&T mnemonic\n")); 9004 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n" 9005 " Display instruction with Intel mnemonic\n")); 9006 fprintf (stream, _(" addr64 Assume 64bit address size\n")); 9007 fprintf (stream, _(" addr32 Assume 32bit address size\n")); 9008 fprintf (stream, _(" addr16 Assume 16bit address size\n")); 9009 fprintf (stream, _(" data32 Assume 32bit data size\n")); 9010 fprintf (stream, _(" data16 Assume 16bit data size\n")); 9011 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); 9012 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); 9013 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); 9014 } 9015 9016 /* Bad opcode. */ 9017 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; 9018 9019 /* Fetch error indicator. */ 9020 static const struct dis386 err_opcode = { NULL, { XX }, 0 }; 9021 9022 static const struct dis386 map5_f8_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F8) }; 9023 static const struct dis386 map5_f9_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F9) }; 9024 static const struct dis386 map5_fd_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_FD) }; 9025 static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) }; 9026 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) }; 9027 9028 /* Get a pointer to struct dis386 with a valid name. */ 9029 9030 static const struct dis386 * 9031 get_valid_dis386 (const struct dis386 *dp, instr_info *ins) 9032 { 9033 int vindex, vex_table_index; 9034 9035 if (dp->name != NULL) 9036 return dp; 9037 9038 switch (dp->op[0].bytemode) 9039 { 9040 case USE_REG_TABLE: 9041 dp = ®_table[dp->op[1].bytemode][ins->modrm.reg]; 9042 break; 9043 9044 case USE_MOD_TABLE: 9045 vindex = ins->modrm.mod == 0x3 ? 1 : 0; 9046 dp = &mod_table[dp->op[1].bytemode][vindex]; 9047 break; 9048 9049 case USE_RM_TABLE: 9050 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm]; 9051 break; 9052 9053 case USE_PREFIX_TABLE: 9054 use_prefix_table: 9055 if (ins->need_vex) 9056 { 9057 /* The prefix in VEX is implicit. */ 9058 switch (ins->vex.prefix) 9059 { 9060 case 0: 9061 vindex = 0; 9062 break; 9063 case REPE_PREFIX_OPCODE: 9064 vindex = 1; 9065 break; 9066 case DATA_PREFIX_OPCODE: 9067 vindex = 2; 9068 break; 9069 case REPNE_PREFIX_OPCODE: 9070 vindex = 3; 9071 break; 9072 default: 9073 abort (); 9074 break; 9075 } 9076 } 9077 else 9078 { 9079 int last_prefix = -1; 9080 int prefix = 0; 9081 vindex = 0; 9082 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. 9083 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the 9084 last one wins. */ 9085 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) 9086 { 9087 if (ins->last_repz_prefix > ins->last_repnz_prefix) 9088 { 9089 vindex = 1; 9090 prefix = PREFIX_REPZ; 9091 last_prefix = ins->last_repz_prefix; 9092 } 9093 else 9094 { 9095 vindex = 3; 9096 prefix = PREFIX_REPNZ; 9097 last_prefix = ins->last_repnz_prefix; 9098 } 9099 9100 /* Check if prefix should be ignored. */ 9101 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement 9102 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) 9103 & prefix) != 0 9104 && !prefix_table[dp->op[1].bytemode][vindex].name) 9105 vindex = 0; 9106 } 9107 9108 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0) 9109 { 9110 vindex = 2; 9111 prefix = PREFIX_DATA; 9112 last_prefix = ins->last_data_prefix; 9113 } 9114 9115 if (vindex != 0) 9116 { 9117 ins->used_prefixes |= prefix; 9118 ins->all_prefixes[last_prefix] = 0; 9119 } 9120 } 9121 dp = &prefix_table[dp->op[1].bytemode][vindex]; 9122 break; 9123 9124 case USE_X86_64_EVEX_FROM_VEX_TABLE: 9125 case USE_X86_64_EVEX_PFX_TABLE: 9126 case USE_X86_64_EVEX_W_TABLE: 9127 case USE_X86_64_EVEX_MEM_W_TABLE: 9128 ins->evex_type = evex_from_vex; 9129 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z, 9130 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */ 9131 if (ins->address_mode != mode_64bit 9132 || (ins->vex.mask_register_specifier & 0x3) != 0 9133 || ins->vex.ll != 0 9134 || ins->vex.zeroing != 0 9135 || ins->vex.b) 9136 return &bad_opcode; 9137 9138 if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE) 9139 goto use_prefix_table; 9140 if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE) 9141 goto use_vex_w_table; 9142 if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE) 9143 { 9144 if (ins->modrm.mod == 3) 9145 return &bad_opcode; 9146 goto use_vex_w_table; 9147 } 9148 9149 /* Fall through. */ 9150 case USE_X86_64_TABLE: 9151 vindex = ins->address_mode == mode_64bit ? 1 : 0; 9152 dp = &x86_64_table[dp->op[1].bytemode][vindex]; 9153 break; 9154 9155 case USE_3BYTE_TABLE: 9156 if (ins->last_rex2_prefix >= 0) 9157 return &err_opcode; 9158 if (!fetch_code (ins->info, ins->codep + 2)) 9159 return &err_opcode; 9160 vindex = *ins->codep++; 9161 dp = &three_byte_table[dp->op[1].bytemode][vindex]; 9162 ins->end_codep = ins->codep; 9163 if (!fetch_modrm (ins)) 9164 return &err_opcode; 9165 break; 9166 9167 case USE_VEX_LEN_TABLE: 9168 if (!ins->need_vex) 9169 abort (); 9170 9171 switch (ins->vex.length) 9172 { 9173 case 128: 9174 vindex = 0; 9175 break; 9176 case 512: 9177 /* This allows re-using in particular table entries where only 9178 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */ 9179 if (ins->vex.evex) 9180 { 9181 case 256: 9182 vindex = 1; 9183 break; 9184 } 9185 /* Fall through. */ 9186 default: 9187 abort (); 9188 break; 9189 } 9190 9191 dp = &vex_len_table[dp->op[1].bytemode][vindex]; 9192 break; 9193 9194 case USE_EVEX_LEN_TABLE: 9195 if (!ins->vex.evex) 9196 abort (); 9197 9198 switch (ins->vex.length) 9199 { 9200 case 128: 9201 vindex = 0; 9202 break; 9203 case 256: 9204 vindex = 1; 9205 break; 9206 case 512: 9207 vindex = 2; 9208 break; 9209 default: 9210 abort (); 9211 break; 9212 } 9213 9214 dp = &evex_len_table[dp->op[1].bytemode][vindex]; 9215 break; 9216 9217 case USE_XOP_8F_TABLE: 9218 if (!fetch_code (ins->info, ins->codep + 3)) 9219 return &err_opcode; 9220 ins->rex = ~(*ins->codep >> 5) & 0x7; 9221 9222 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ 9223 switch ((*ins->codep & 0x1f)) 9224 { 9225 default: 9226 dp = &bad_opcode; 9227 return dp; 9228 case 0x8: 9229 vex_table_index = XOP_08; 9230 break; 9231 case 0x9: 9232 vex_table_index = XOP_09; 9233 break; 9234 case 0xa: 9235 vex_table_index = XOP_0A; 9236 break; 9237 } 9238 ins->codep++; 9239 ins->vex.w = *ins->codep & 0x80; 9240 if (ins->vex.w && ins->address_mode == mode_64bit) 9241 ins->rex |= REX_W; 9242 9243 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9244 if (ins->address_mode != mode_64bit) 9245 { 9246 /* In 16/32-bit mode REX_B is silently ignored. */ 9247 ins->rex &= ~REX_B; 9248 } 9249 9250 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 9251 switch ((*ins->codep & 0x3)) 9252 { 9253 case 0: 9254 break; 9255 case 1: 9256 ins->vex.prefix = DATA_PREFIX_OPCODE; 9257 break; 9258 case 2: 9259 ins->vex.prefix = REPE_PREFIX_OPCODE; 9260 break; 9261 case 3: 9262 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9263 break; 9264 } 9265 ins->need_vex = 3; 9266 ins->codep++; 9267 vindex = *ins->codep++; 9268 dp = &xop_table[vex_table_index][vindex]; 9269 9270 ins->end_codep = ins->codep; 9271 if (!fetch_modrm (ins)) 9272 return &err_opcode; 9273 9274 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid 9275 having to decode the bits for every otherwise valid encoding. */ 9276 if (ins->vex.prefix) 9277 return &bad_opcode; 9278 break; 9279 9280 case USE_VEX_C4_TABLE: 9281 /* VEX prefix. */ 9282 if (!fetch_code (ins->info, ins->codep + 3)) 9283 return &err_opcode; 9284 ins->rex = ~(*ins->codep >> 5) & 0x7; 9285 switch ((*ins->codep & 0x1f)) 9286 { 9287 default: 9288 dp = &bad_opcode; 9289 return dp; 9290 case 0x1: 9291 vex_table_index = VEX_0F; 9292 break; 9293 case 0x2: 9294 vex_table_index = VEX_0F38; 9295 break; 9296 case 0x3: 9297 vex_table_index = VEX_0F3A; 9298 break; 9299 case 0x5: 9300 vex_table_index = VEX_MAP5; 9301 break; 9302 case 0x7: 9303 vex_table_index = VEX_MAP7; 9304 break; 9305 } 9306 ins->codep++; 9307 ins->vex.w = *ins->codep & 0x80; 9308 if (ins->address_mode == mode_64bit) 9309 { 9310 if (ins->vex.w) 9311 ins->rex |= REX_W; 9312 } 9313 else 9314 { 9315 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit 9316 is ignored, other REX bits are 0 and the highest bit in 9317 VEX.vvvv is also ignored (but we mustn't clear it here). */ 9318 ins->rex = 0; 9319 } 9320 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9321 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 9322 switch ((*ins->codep & 0x3)) 9323 { 9324 case 0: 9325 break; 9326 case 1: 9327 ins->vex.prefix = DATA_PREFIX_OPCODE; 9328 break; 9329 case 2: 9330 ins->vex.prefix = REPE_PREFIX_OPCODE; 9331 break; 9332 case 3: 9333 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9334 break; 9335 } 9336 ins->need_vex = 3; 9337 ins->codep++; 9338 vindex = *ins->codep++; 9339 ins->condition_code = vindex & 0xf; 9340 if (vex_table_index != VEX_MAP7 && vex_table_index != VEX_MAP5) 9341 dp = &vex_table[vex_table_index][vindex]; 9342 else if (vindex == 0xf6) 9343 dp = &map7_f6_opcode; 9344 else if (vindex == 0xf8) 9345 { 9346 if (vex_table_index == VEX_MAP5) 9347 dp = &map5_f8_opcode; 9348 else 9349 dp = &map7_f8_opcode; 9350 } 9351 else if (vindex == 0xf9) 9352 dp = &map5_f9_opcode; 9353 else if (vindex == 0xfd) 9354 dp = &map5_fd_opcode; 9355 else 9356 dp = &bad_opcode; 9357 ins->end_codep = ins->codep; 9358 /* There is no MODRM byte for VEX0F 77. */ 9359 if ((vex_table_index != VEX_0F || vindex != 0x77) 9360 && !fetch_modrm (ins)) 9361 return &err_opcode; 9362 break; 9363 9364 case USE_VEX_C5_TABLE: 9365 /* VEX prefix. */ 9366 if (!fetch_code (ins->info, ins->codep + 2)) 9367 return &err_opcode; 9368 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R; 9369 9370 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in 9371 VEX.vvvv is 1. */ 9372 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9373 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; 9374 switch ((*ins->codep & 0x3)) 9375 { 9376 case 0: 9377 break; 9378 case 1: 9379 ins->vex.prefix = DATA_PREFIX_OPCODE; 9380 break; 9381 case 2: 9382 ins->vex.prefix = REPE_PREFIX_OPCODE; 9383 break; 9384 case 3: 9385 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9386 break; 9387 } 9388 ins->need_vex = 2; 9389 ins->codep++; 9390 vindex = *ins->codep++; 9391 dp = &vex_table[VEX_0F][vindex]; 9392 ins->end_codep = ins->codep; 9393 /* There is no MODRM byte for VEX 77. */ 9394 if (vindex != 0x77 && !fetch_modrm (ins)) 9395 return &err_opcode; 9396 break; 9397 9398 case USE_VEX_W_TABLE: 9399 use_vex_w_table: 9400 if (!ins->need_vex) 9401 abort (); 9402 9403 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w]; 9404 break; 9405 9406 case USE_EVEX_TABLE: 9407 ins->two_source_ops = false; 9408 /* EVEX prefix. */ 9409 ins->vex.evex = true; 9410 if (!fetch_code (ins->info, ins->codep + 4)) 9411 return &err_opcode; 9412 /* The first byte after 0x62. */ 9413 if (*ins->codep & 0x8) 9414 ins->rex2 |= REX_B; 9415 if (!(*ins->codep & 0x10)) 9416 ins->rex2 |= REX_R; 9417 9418 ins->rex = ~(*ins->codep >> 5) & 0x7; 9419 switch (*ins->codep & 0x7) 9420 { 9421 default: 9422 return &bad_opcode; 9423 case 0x1: 9424 vex_table_index = EVEX_0F; 9425 break; 9426 case 0x2: 9427 vex_table_index = EVEX_0F38; 9428 break; 9429 case 0x3: 9430 vex_table_index = EVEX_0F3A; 9431 break; 9432 case 0x4: 9433 vex_table_index = EVEX_MAP4; 9434 ins->evex_type = evex_from_legacy; 9435 if (ins->address_mode != mode_64bit) 9436 return &bad_opcode; 9437 ins->rex |= REX_OPCODE; 9438 break; 9439 case 0x5: 9440 vex_table_index = EVEX_MAP5; 9441 break; 9442 case 0x6: 9443 vex_table_index = EVEX_MAP6; 9444 break; 9445 case 0x7: 9446 vex_table_index = EVEX_MAP7; 9447 break; 9448 } 9449 9450 /* The second byte after 0x62. */ 9451 ins->codep++; 9452 ins->vex.w = *ins->codep & 0x80; 9453 if (ins->vex.w && ins->address_mode == mode_64bit) 9454 ins->rex |= REX_W; 9455 9456 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; 9457 9458 if (!(*ins->codep & 0x4)) 9459 ins->rex2 |= REX_X; 9460 9461 switch ((*ins->codep & 0x3)) 9462 { 9463 case 0: 9464 break; 9465 case 1: 9466 ins->vex.prefix = DATA_PREFIX_OPCODE; 9467 break; 9468 case 2: 9469 ins->vex.prefix = REPE_PREFIX_OPCODE; 9470 break; 9471 case 3: 9472 ins->vex.prefix = REPNE_PREFIX_OPCODE; 9473 break; 9474 } 9475 9476 /* The third byte after 0x62. */ 9477 ins->codep++; 9478 9479 /* Remember the static rounding bits. */ 9480 ins->vex.ll = (*ins->codep >> 5) & 3; 9481 ins->vex.b = *ins->codep & 0x10; 9482 9483 ins->vex.v = *ins->codep & 0x8; 9484 ins->vex.mask_register_specifier = *ins->codep & 0x7; 9485 ins->vex.scc = *ins->codep & 0xf; 9486 ins->vex.zeroing = *ins->codep & 0x80; 9487 /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared 9488 when it's an evex_default one. */ 9489 ins->vex.nf = *ins->codep & 0x4; 9490 9491 if (ins->address_mode != mode_64bit) 9492 { 9493 /* Report bad for !evex_default and when two fixed values of evex 9494 change. */ 9495 if (ins->evex_type != evex_default 9496 || (ins->rex2 & (REX_B | REX_X))) 9497 return &bad_opcode; 9498 /* In 16/32-bit mode silently ignore following bits. */ 9499 ins->rex &= ~REX_B; 9500 ins->rex2 &= ~REX_R; 9501 } 9502 9503 ins->need_vex = 4; 9504 9505 ins->codep++; 9506 vindex = *ins->codep++; 9507 ins->condition_code = vindex & 0xf; 9508 if (vex_table_index != EVEX_MAP7) 9509 dp = &evex_table[vex_table_index][vindex]; 9510 else if (vindex == 0xf8) 9511 dp = &map7_f8_opcode; 9512 else if (vindex == 0xf6) 9513 dp = &map7_f6_opcode; 9514 else 9515 dp = &bad_opcode; 9516 ins->end_codep = ins->codep; 9517 if (!fetch_modrm (ins)) 9518 return &err_opcode; 9519 9520 if (ins->modrm.mod == 3 && (ins->rex2 & REX_X)) 9521 return &bad_opcode; 9522 9523 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00, 9524 which has the same encoding as vex.length == 128 and they can share 9525 the same processing with vex.length in OP_VEX. */ 9526 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy) 9527 ins->vex.length = 512; 9528 else 9529 { 9530 switch (ins->vex.ll) 9531 { 9532 case 0x0: 9533 ins->vex.length = 128; 9534 break; 9535 case 0x1: 9536 ins->vex.length = 256; 9537 break; 9538 case 0x2: 9539 ins->vex.length = 512; 9540 break; 9541 default: 9542 return &bad_opcode; 9543 } 9544 } 9545 break; 9546 9547 case 0: 9548 dp = &bad_opcode; 9549 break; 9550 9551 default: 9552 abort (); 9553 } 9554 9555 if (dp->name != NULL) 9556 return dp; 9557 else 9558 return get_valid_dis386 (dp, ins); 9559 } 9560 9561 static bool 9562 get_sib (instr_info *ins, int sizeflag) 9563 { 9564 /* If modrm.mod == 3, operand must be register. */ 9565 if (ins->need_modrm 9566 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 9567 && ins->modrm.mod != 3 9568 && ins->modrm.rm == 4) 9569 { 9570 if (!fetch_code (ins->info, ins->codep + 2)) 9571 return false; 9572 ins->sib.index = (ins->codep[1] >> 3) & 7; 9573 ins->sib.scale = (ins->codep[1] >> 6) & 3; 9574 ins->sib.base = ins->codep[1] & 7; 9575 ins->has_sib = true; 9576 } 9577 else 9578 ins->has_sib = false; 9579 9580 return true; 9581 } 9582 9583 /* Like oappend_with_style (below) but always with text style. */ 9584 9585 static void 9586 oappend (instr_info *ins, const char *s) 9587 { 9588 oappend_with_style (ins, s, dis_style_text); 9589 } 9590 9591 /* Like oappend (above), but S is a string starting with '%'. In 9592 Intel syntax, the '%' is elided. */ 9593 9594 static void 9595 oappend_register (instr_info *ins, const char *s) 9596 { 9597 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register); 9598 } 9599 9600 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT. 9601 STYLE is the default style to use in the fprintf_styled_func calls, 9602 however, FMT might include embedded style markers (see oappend_style), 9603 these embedded markers are not printed, but instead change the style 9604 used in the next fprintf_styled_func call. */ 9605 9606 static void ATTRIBUTE_PRINTF_3 9607 i386_dis_printf (const disassemble_info *info, enum disassembler_style style, 9608 const char *fmt, ...) 9609 { 9610 va_list ap; 9611 enum disassembler_style curr_style = style; 9612 const char *start, *curr; 9613 char staging_area[50]; 9614 9615 va_start (ap, fmt); 9616 /* In particular print_insn()'s processing of op_txt[] can hand rather long 9617 strings here. Bypass vsnprintf() in such cases to avoid capacity issues 9618 with the staging area. */ 9619 if (strcmp (fmt, "%s")) 9620 { 9621 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap); 9622 9623 va_end (ap); 9624 9625 if (res < 0) 9626 return; 9627 9628 if ((size_t) res >= sizeof (staging_area)) 9629 abort (); 9630 9631 start = curr = staging_area; 9632 } 9633 else 9634 { 9635 start = curr = va_arg (ap, const char *); 9636 va_end (ap); 9637 } 9638 9639 do 9640 { 9641 if (*curr == '\0' 9642 || (*curr == STYLE_MARKER_CHAR 9643 && ISXDIGIT (*(curr + 1)) 9644 && *(curr + 2) == STYLE_MARKER_CHAR)) 9645 { 9646 /* Output content between our START position and CURR. */ 9647 int len = curr - start; 9648 int n = (*info->fprintf_styled_func) (info->stream, curr_style, 9649 "%.*s", len, start); 9650 if (n < 0) 9651 break; 9652 9653 if (*curr == '\0') 9654 break; 9655 9656 /* Skip over the initial STYLE_MARKER_CHAR. */ 9657 ++curr; 9658 9659 /* Update the CURR_STYLE. As there are less than 16 styles, it 9660 is possible, that if the input is corrupted in some way, that 9661 we might set CURR_STYLE to an invalid value. Don't worry 9662 though, we check for this situation. */ 9663 if (*curr >= '0' && *curr <= '9') 9664 curr_style = (enum disassembler_style) (*curr - '0'); 9665 else if (*curr >= 'a' && *curr <= 'f') 9666 curr_style = (enum disassembler_style) (*curr - 'a' + 10); 9667 else 9668 curr_style = dis_style_text; 9669 9670 /* Check for an invalid style having been selected. This should 9671 never happen, but it doesn't hurt to be a little paranoid. */ 9672 if (curr_style > dis_style_comment_start) 9673 curr_style = dis_style_text; 9674 9675 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */ 9676 curr += 2; 9677 9678 /* Reset the START to after the style marker. */ 9679 start = curr; 9680 } 9681 else 9682 ++curr; 9683 } 9684 while (true); 9685 } 9686 9687 static int 9688 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) 9689 { 9690 const struct dis386 *dp; 9691 int i; 9692 int ret; 9693 char *op_txt[MAX_OPERANDS]; 9694 int needcomma; 9695 bool intel_swap_2_3; 9696 int sizeflag, orig_sizeflag; 9697 const char *p; 9698 struct dis_private priv; 9699 int prefix_length; 9700 int op_count; 9701 instr_info ins = { 9702 .info = info, 9703 .intel_syntax = intel_syntax >= 0 9704 ? intel_syntax 9705 : (info->mach & bfd_mach_i386_intel_syntax) != 0, 9706 .intel_mnemonic = !SYSV386_COMPAT, 9707 .op_index[0 ... MAX_OPERANDS - 1] = -1, 9708 .start_pc = pc, 9709 .start_codep = priv.the_buffer, 9710 .codep = priv.the_buffer, 9711 .obufp = ins.obuf, 9712 .last_lock_prefix = -1, 9713 .last_repz_prefix = -1, 9714 .last_repnz_prefix = -1, 9715 .last_data_prefix = -1, 9716 .last_addr_prefix = -1, 9717 .last_rex_prefix = -1, 9718 .last_rex2_prefix = -1, 9719 .last_seg_prefix = -1, 9720 .fwait_prefix = -1, 9721 }; 9722 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE]; 9723 9724 priv.orig_sizeflag = AFLAG | DFLAG; 9725 if ((info->mach & bfd_mach_i386_i386) != 0) 9726 ins.address_mode = mode_32bit; 9727 else if (info->mach == bfd_mach_i386_i8086) 9728 { 9729 ins.address_mode = mode_16bit; 9730 priv.orig_sizeflag = 0; 9731 } 9732 else 9733 ins.address_mode = mode_64bit; 9734 9735 for (p = info->disassembler_options; p != NULL;) 9736 { 9737 if (startswith (p, "amd64")) 9738 ins.isa64 = amd64; 9739 else if (startswith (p, "intel64")) 9740 ins.isa64 = intel64; 9741 else if (startswith (p, "x86-64")) 9742 { 9743 ins.address_mode = mode_64bit; 9744 priv.orig_sizeflag |= AFLAG | DFLAG; 9745 } 9746 else if (startswith (p, "i386")) 9747 { 9748 ins.address_mode = mode_32bit; 9749 priv.orig_sizeflag |= AFLAG | DFLAG; 9750 } 9751 else if (startswith (p, "i8086")) 9752 { 9753 ins.address_mode = mode_16bit; 9754 priv.orig_sizeflag &= ~(AFLAG | DFLAG); 9755 } 9756 else if (startswith (p, "intel")) 9757 { 9758 if (startswith (p + 5, "-mnemonic")) 9759 ins.intel_mnemonic = true; 9760 else 9761 ins.intel_syntax = 1; 9762 } 9763 else if (startswith (p, "att")) 9764 { 9765 ins.intel_syntax = 0; 9766 if (startswith (p + 3, "-mnemonic")) 9767 ins.intel_mnemonic = false; 9768 } 9769 else if (startswith (p, "addr")) 9770 { 9771 if (ins.address_mode == mode_64bit) 9772 { 9773 if (p[4] == '3' && p[5] == '2') 9774 priv.orig_sizeflag &= ~AFLAG; 9775 else if (p[4] == '6' && p[5] == '4') 9776 priv.orig_sizeflag |= AFLAG; 9777 } 9778 else 9779 { 9780 if (p[4] == '1' && p[5] == '6') 9781 priv.orig_sizeflag &= ~AFLAG; 9782 else if (p[4] == '3' && p[5] == '2') 9783 priv.orig_sizeflag |= AFLAG; 9784 } 9785 } 9786 else if (startswith (p, "data")) 9787 { 9788 if (p[4] == '1' && p[5] == '6') 9789 priv.orig_sizeflag &= ~DFLAG; 9790 else if (p[4] == '3' && p[5] == '2') 9791 priv.orig_sizeflag |= DFLAG; 9792 } 9793 else if (startswith (p, "suffix")) 9794 priv.orig_sizeflag |= SUFFIX_ALWAYS; 9795 9796 p = strchr (p, ','); 9797 if (p != NULL) 9798 p++; 9799 } 9800 9801 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8) 9802 { 9803 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled")); 9804 return -1; 9805 } 9806 9807 if (ins.intel_syntax) 9808 { 9809 ins.open_char = '['; 9810 ins.close_char = ']'; 9811 ins.separator_char = '+'; 9812 ins.scale_char = '*'; 9813 } 9814 else 9815 { 9816 ins.open_char = '('; 9817 ins.close_char = ')'; 9818 ins.separator_char = ','; 9819 ins.scale_char = ','; 9820 } 9821 9822 /* The output looks better if we put 7 bytes on a line, since that 9823 puts most long word instructions on a single line. */ 9824 info->bytes_per_line = 7; 9825 9826 info->private_data = &priv; 9827 priv.fetched = 0; 9828 priv.insn_start = pc; 9829 9830 for (i = 0; i < MAX_OPERANDS; ++i) 9831 { 9832 op_out[i][0] = 0; 9833 ins.op_out[i] = op_out[i]; 9834 } 9835 9836 sizeflag = priv.orig_sizeflag; 9837 9838 switch (ckprefix (&ins)) 9839 { 9840 case ckp_okay: 9841 break; 9842 9843 case ckp_bogus: 9844 /* Too many prefixes or unused REX prefixes. */ 9845 for (i = 0; 9846 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i]; 9847 i++) 9848 i386_dis_printf (info, dis_style_mnemonic, "%s%s", 9849 (i == 0 ? "" : " "), 9850 prefix_name (ins.address_mode, ins.all_prefixes[i], 9851 sizeflag)); 9852 ret = i; 9853 goto out; 9854 9855 case ckp_fetch_error: 9856 goto fetch_error_out; 9857 } 9858 9859 ins.nr_prefixes = ins.codep - ins.start_codep; 9860 9861 if (!fetch_code (info, ins.codep + 1)) 9862 { 9863 fetch_error_out: 9864 ret = fetch_error (&ins); 9865 goto out; 9866 } 9867 9868 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8); 9869 9870 if ((ins.prefixes & PREFIX_FWAIT) 9871 && (*ins.codep < 0xd8 || *ins.codep > 0xdf)) 9872 { 9873 /* Handle ins.prefixes before fwait. */ 9874 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i]; 9875 i++) 9876 i386_dis_printf (info, dis_style_mnemonic, "%s ", 9877 prefix_name (ins.address_mode, ins.all_prefixes[i], 9878 sizeflag)); 9879 i386_dis_printf (info, dis_style_mnemonic, "fwait"); 9880 ret = i + 1; 9881 goto out; 9882 } 9883 9884 /* REX2.M in rex2 prefix represents map0 or map1. */ 9885 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M)) 9886 { 9887 if (!ins.rex2) 9888 { 9889 ins.codep++; 9890 if (!fetch_code (info, ins.codep + 1)) 9891 goto fetch_error_out; 9892 } 9893 9894 dp = &dis386_twobyte[*ins.codep]; 9895 ins.need_modrm = twobyte_has_modrm[*ins.codep]; 9896 } 9897 else 9898 { 9899 dp = &dis386[*ins.codep]; 9900 ins.need_modrm = onebyte_has_modrm[*ins.codep]; 9901 } 9902 ins.condition_code = *ins.codep & 0xf; 9903 ins.codep++; 9904 9905 /* Save sizeflag for printing the extra ins.prefixes later before updating 9906 it for mnemonic and operand processing. The prefix names depend 9907 only on the address mode. */ 9908 orig_sizeflag = sizeflag; 9909 if (ins.prefixes & PREFIX_ADDR) 9910 sizeflag ^= AFLAG; 9911 if ((ins.prefixes & PREFIX_DATA)) 9912 sizeflag ^= DFLAG; 9913 9914 ins.end_codep = ins.codep; 9915 if (ins.need_modrm && !fetch_modrm (&ins)) 9916 goto fetch_error_out; 9917 9918 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) 9919 { 9920 if (!get_sib (&ins, sizeflag) 9921 || !dofloat (&ins, sizeflag)) 9922 goto fetch_error_out; 9923 } 9924 else 9925 { 9926 dp = get_valid_dis386 (dp, &ins); 9927 if (dp == &err_opcode) 9928 goto fetch_error_out; 9929 9930 /* For APX instructions promoted from legacy maps 0/1, embedded prefix 9931 is interpreted as the operand size override. */ 9932 if (ins.evex_type == evex_from_legacy 9933 && ins.vex.prefix == DATA_PREFIX_OPCODE) 9934 sizeflag ^= DFLAG; 9935 9936 if(ins.evex_type == evex_default) 9937 ins.vex.nf = false; 9938 else 9939 /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest 9940 are cleared separately.) in mask_register_specifier and keep the low 9941 2 bits of mask_register_specifier to report errors for invalid cases 9942 . */ 9943 ins.vex.mask_register_specifier &= 0x3; 9944 9945 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) 9946 { 9947 if (!get_sib (&ins, sizeflag)) 9948 goto fetch_error_out; 9949 for (i = 0; i < MAX_OPERANDS; ++i) 9950 { 9951 ins.obufp = ins.op_out[i]; 9952 ins.op_ad = MAX_OPERANDS - 1 - i; 9953 if (dp->op[i].rtn 9954 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag)) 9955 goto fetch_error_out; 9956 /* For EVEX instruction after the last operand masking 9957 should be printed. */ 9958 if (i == 0 && ins.vex.evex) 9959 { 9960 /* Don't print {%k0}. */ 9961 if (ins.vex.mask_register_specifier) 9962 { 9963 const char *reg_name 9964 = att_names_mask[ins.vex.mask_register_specifier]; 9965 9966 oappend (&ins, "{"); 9967 oappend_register (&ins, reg_name); 9968 oappend (&ins, "}"); 9969 9970 if (ins.vex.zeroing) 9971 oappend (&ins, "{z}"); 9972 } 9973 else if (ins.vex.zeroing) 9974 { 9975 oappend (&ins, "{bad}"); 9976 continue; 9977 } 9978 9979 /* Instructions with a mask register destination allow for 9980 zeroing-masking only (if any masking at all), which is 9981 _not_ expressed by EVEX.z. */ 9982 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode) 9983 ins.illegal_masking = true; 9984 9985 /* S/G insns require a mask and don't allow 9986 zeroing-masking. */ 9987 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode 9988 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode) 9989 && (ins.vex.mask_register_specifier == 0 9990 || ins.vex.zeroing)) 9991 ins.illegal_masking = true; 9992 9993 if (ins.illegal_masking) 9994 oappend (&ins, "/(bad)"); 9995 } 9996 } 9997 /* vex.nf is cleared after being consumed. */ 9998 if (ins.vex.nf) 9999 oappend (&ins, "{bad-nf}"); 10000 10001 /* Check whether rounding control was enabled for an insn not 10002 supporting it, when evex.b is not treated as evex.nd. */ 10003 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default 10004 && !(ins.evex_used & EVEX_b_used)) 10005 { 10006 for (i = 0; i < MAX_OPERANDS; ++i) 10007 { 10008 ins.obufp = ins.op_out[i]; 10009 if (*ins.obufp) 10010 continue; 10011 oappend (&ins, names_rounding[ins.vex.ll]); 10012 oappend (&ins, "bad}"); 10013 break; 10014 } 10015 } 10016 } 10017 } 10018 10019 /* Clear instruction information. */ 10020 info->insn_info_valid = 0; 10021 info->branch_delay_insns = 0; 10022 info->data_size = 0; 10023 info->insn_type = dis_noninsn; 10024 info->target = 0; 10025 info->target2 = 0; 10026 10027 /* Reset jump operation indicator. */ 10028 ins.op_is_jump = false; 10029 { 10030 int jump_detection = 0; 10031 10032 /* Extract flags. */ 10033 for (i = 0; i < MAX_OPERANDS; ++i) 10034 { 10035 if ((dp->op[i].rtn == OP_J) 10036 || (dp->op[i].rtn == OP_indirE)) 10037 jump_detection |= 1; 10038 else if ((dp->op[i].rtn == BND_Fixup) 10039 || (!dp->op[i].rtn && !dp->op[i].bytemode)) 10040 jump_detection |= 2; 10041 else if ((dp->op[i].bytemode == cond_jump_mode) 10042 || (dp->op[i].bytemode == loop_jcxz_mode)) 10043 jump_detection |= 4; 10044 } 10045 10046 /* Determine if this is a jump or branch. */ 10047 if ((jump_detection & 0x3) == 0x3) 10048 { 10049 ins.op_is_jump = true; 10050 if (jump_detection & 0x4) 10051 info->insn_type = dis_condbranch; 10052 else 10053 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4)) 10054 ? dis_jsr : dis_branch; 10055 } 10056 } 10057 /* The purpose of placing the check here is to wait for the EVEX prefix for 10058 conditional CMP and TEST to be consumed and cleared, and then make a 10059 unified judgment. Because they are both in map4, we can not distinguish 10060 EVEX prefix for conditional CMP and TEST from others during the 10061 EVEX prefix stage of parsing. */ 10062 if (ins.evex_type == evex_from_legacy) 10063 { 10064 /* EVEX from legacy instructions, when the EVEX.ND bit is 0, 10065 all bits of EVEX.vvvv and EVEX.V' must be 1. */ 10066 if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v)) 10067 { 10068 i386_dis_printf (info, dis_style_text, "(bad)"); 10069 ret = ins.end_codep - priv.the_buffer; 10070 goto out; 10071 } 10072 10073 /* EVEX from legacy instructions require that EVEX.z, EVEX.LL and the 10074 lower 2 bits of EVEX.aaa must be 0. */ 10075 if ((ins.vex.mask_register_specifier & 0x3) != 0 10076 || ins.vex.ll != 0 || ins.vex.zeroing != 0) 10077 { 10078 i386_dis_printf (info, dis_style_text, "(bad)"); 10079 ret = ins.end_codep - priv.the_buffer; 10080 goto out; 10081 } 10082 } 10083 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which 10084 are all 0s in inverted form. */ 10085 if (ins.need_vex && ins.vex.register_specifier != 0) 10086 { 10087 i386_dis_printf (info, dis_style_text, "(bad)"); 10088 ret = ins.end_codep - priv.the_buffer; 10089 goto out; 10090 } 10091 10092 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL) 10093 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0) 10094 { 10095 i386_dis_printf (info, dis_style_text, "(bad)"); 10096 ret = ins.end_codep - priv.the_buffer; 10097 goto out; 10098 } 10099 10100 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL) 10101 { 10102 case PREFIX_DATA: 10103 /* If only the data prefix is marked as mandatory, its absence renders 10104 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ 10105 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA)) 10106 { 10107 i386_dis_printf (info, dis_style_text, "(bad)"); 10108 ret = ins.end_codep - priv.the_buffer; 10109 goto out; 10110 } 10111 ins.used_prefixes |= PREFIX_DATA; 10112 /* Fall through. */ 10113 case PREFIX_OPCODE: 10114 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is 10115 unused, opcode is invalid. Since the PREFIX_DATA prefix may be 10116 used by putop and MMX/SSE operand and may be overridden by the 10117 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix 10118 separately. */ 10119 if (((ins.need_vex 10120 ? ins.vex.prefix == REPE_PREFIX_OPCODE 10121 || ins.vex.prefix == REPNE_PREFIX_OPCODE 10122 : (ins.prefixes 10123 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) 10124 && (ins.used_prefixes 10125 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) 10126 || (((ins.need_vex 10127 ? ins.vex.prefix == DATA_PREFIX_OPCODE 10128 : ((ins.prefixes 10129 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) 10130 == PREFIX_DATA)) 10131 && (ins.used_prefixes & PREFIX_DATA) == 0)) 10132 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA 10133 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA))) 10134 { 10135 i386_dis_printf (info, dis_style_text, "(bad)"); 10136 ret = ins.end_codep - priv.the_buffer; 10137 goto out; 10138 } 10139 break; 10140 10141 case PREFIX_IGNORED: 10142 /* Zap data size and rep prefixes from used_prefixes and reinstate their 10143 origins in all_prefixes. */ 10144 ins.used_prefixes &= ~PREFIX_OPCODE; 10145 if (ins.last_data_prefix >= 0) 10146 ins.all_prefixes[ins.last_data_prefix] = 0x66; 10147 if (ins.last_repz_prefix >= 0) 10148 ins.all_prefixes[ins.last_repz_prefix] = 0xf3; 10149 if (ins.last_repnz_prefix >= 0) 10150 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2; 10151 break; 10152 10153 case PREFIX_NP_OR_DATA: 10154 if (ins.vex.prefix == REPE_PREFIX_OPCODE 10155 || ins.vex.prefix == REPNE_PREFIX_OPCODE) 10156 { 10157 i386_dis_printf (info, dis_style_text, "(bad)"); 10158 ret = ins.end_codep - priv.the_buffer; 10159 goto out; 10160 } 10161 break; 10162 10163 case NO_PREFIX: 10164 if (ins.vex.prefix) 10165 { 10166 i386_dis_printf (info, dis_style_text, "(bad)"); 10167 ret = ins.end_codep - priv.the_buffer; 10168 goto out; 10169 } 10170 break; 10171 } 10172 10173 /* Check if the REX prefix is used. */ 10174 if ((ins.rex ^ ins.rex_used) == 0 10175 && !ins.need_vex && ins.last_rex_prefix >= 0) 10176 ins.all_prefixes[ins.last_rex_prefix] = 0; 10177 10178 /* Check if the REX2 prefix is used. */ 10179 if (ins.last_rex2_prefix >= 0 10180 && ((ins.rex2 & REX2_SPECIAL) 10181 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0 10182 && (ins.rex ^ ins.rex_used) == 0 10183 && (ins.rex2 & 7)))) 10184 ins.all_prefixes[ins.last_rex2_prefix] = 0; 10185 10186 /* Check if the SEG prefix is used. */ 10187 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES 10188 | PREFIX_FS | PREFIX_GS)) != 0 10189 && (ins.used_prefixes & ins.active_seg_prefix) != 0) 10190 ins.all_prefixes[ins.last_seg_prefix] = 0; 10191 10192 /* Check if the ADDR prefix is used. */ 10193 if ((ins.prefixes & PREFIX_ADDR) != 0 10194 && (ins.used_prefixes & PREFIX_ADDR) != 0) 10195 ins.all_prefixes[ins.last_addr_prefix] = 0; 10196 10197 /* Check if the DATA prefix is used. */ 10198 if ((ins.prefixes & PREFIX_DATA) != 0 10199 && (ins.used_prefixes & PREFIX_DATA) != 0 10200 && !ins.need_vex) 10201 ins.all_prefixes[ins.last_data_prefix] = 0; 10202 10203 /* Print the extra ins.prefixes. */ 10204 prefix_length = 0; 10205 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++) 10206 if (ins.all_prefixes[i]) 10207 { 10208 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i], 10209 orig_sizeflag); 10210 10211 if (name == NULL) 10212 abort (); 10213 prefix_length += strlen (name) + 1; 10214 if (ins.all_prefixes[i] == REX2_OPCODE) 10215 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name, 10216 (unsigned int) ins.rex2_payload); 10217 else 10218 i386_dis_printf (info, dis_style_mnemonic, "%s ", name); 10219 } 10220 10221 /* Check maximum code length. */ 10222 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH) 10223 { 10224 i386_dis_printf (info, dis_style_text, "(bad)"); 10225 ret = MAX_CODE_LENGTH; 10226 goto out; 10227 } 10228 10229 /* Calculate the number of operands this instruction has. */ 10230 op_count = 0; 10231 for (i = 0; i < MAX_OPERANDS; ++i) 10232 if (*ins.op_out[i] != '\0') 10233 ++op_count; 10234 10235 /* Calculate the number of spaces to print after the mnemonic. */ 10236 ins.obufp = ins.mnemonicendp; 10237 if (op_count > 0) 10238 { 10239 i = strlen (ins.obuf) + prefix_length; 10240 if (i < 7) 10241 i = 7 - i; 10242 else 10243 i = 1; 10244 } 10245 else 10246 i = 0; 10247 10248 /* Print the instruction mnemonic along with any trailing whitespace. */ 10249 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, ""); 10250 10251 /* The enter and bound instructions are printed with operands in the same 10252 order as the intel book; everything else is printed in reverse order. */ 10253 intel_swap_2_3 = false; 10254 if (ins.intel_syntax || ins.two_source_ops) 10255 { 10256 for (i = 0; i < MAX_OPERANDS; ++i) 10257 op_txt[i] = ins.op_out[i]; 10258 10259 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding 10260 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) 10261 { 10262 op_txt[2] = ins.op_out[3]; 10263 op_txt[3] = ins.op_out[2]; 10264 intel_swap_2_3 = true; 10265 } 10266 10267 for (i = 0; i < (MAX_OPERANDS >> 1); ++i) 10268 { 10269 bool riprel; 10270 10271 ins.op_ad = ins.op_index[i]; 10272 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i]; 10273 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad; 10274 riprel = ins.op_riprel[i]; 10275 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i]; 10276 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel; 10277 } 10278 } 10279 else 10280 { 10281 for (i = 0; i < MAX_OPERANDS; ++i) 10282 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i]; 10283 } 10284 10285 needcomma = 0; 10286 for (i = 0; i < MAX_OPERANDS; ++i) 10287 if (*op_txt[i]) 10288 { 10289 /* In Intel syntax embedded rounding / SAE are not separate operands. 10290 Instead they're attached to the prior register operand. Simply 10291 suppress emission of the comma to achieve that effect. */ 10292 switch (i & -(ins.intel_syntax && dp)) 10293 { 10294 case 2: 10295 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3) 10296 needcomma = 0; 10297 break; 10298 case 3: 10299 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3) 10300 needcomma = 0; 10301 break; 10302 } 10303 if (needcomma) 10304 i386_dis_printf (info, dis_style_text, ","); 10305 if (ins.op_index[i] != -1 && !ins.op_riprel[i]) 10306 { 10307 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]]; 10308 10309 if (ins.op_is_jump) 10310 { 10311 info->insn_info_valid = 1; 10312 info->branch_delay_insns = 0; 10313 info->data_size = 0; 10314 info->target = target; 10315 info->target2 = 0; 10316 } 10317 (*info->print_address_func) (target, info); 10318 } 10319 else 10320 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]); 10321 needcomma = 1; 10322 } 10323 10324 for (i = 0; i < MAX_OPERANDS; i++) 10325 if (ins.op_index[i] != -1 && ins.op_riprel[i]) 10326 { 10327 i386_dis_printf (info, dis_style_comment_start, " # "); 10328 (*info->print_address_func) 10329 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep) 10330 + ins.op_address[ins.op_index[i]]), 10331 info); 10332 break; 10333 } 10334 ret = ins.codep - priv.the_buffer; 10335 out: 10336 info->private_data = NULL; 10337 return ret; 10338 } 10339 10340 /* Here for backwards compatibility. When gdb stops using 10341 print_insn_i386_att and print_insn_i386_intel these functions can 10342 disappear, and print_insn_i386 be merged into print_insn. */ 10343 int 10344 print_insn_i386_att (bfd_vma pc, disassemble_info *info) 10345 { 10346 return print_insn (pc, info, 0); 10347 } 10348 10349 int 10350 print_insn_i386_intel (bfd_vma pc, disassemble_info *info) 10351 { 10352 return print_insn (pc, info, 1); 10353 } 10354 10355 int 10356 print_insn_i386 (bfd_vma pc, disassemble_info *info) 10357 { 10358 return print_insn (pc, info, -1); 10359 } 10360 10361 static const char *float_mem[] = { 10362 /* d8 */ 10363 "fadd{s|}", 10364 "fmul{s|}", 10365 "fcom{s|}", 10366 "fcomp{s|}", 10367 "fsub{s|}", 10368 "fsubr{s|}", 10369 "fdiv{s|}", 10370 "fdivr{s|}", 10371 /* d9 */ 10372 "fld{s|}", 10373 "(bad)", 10374 "fst{s|}", 10375 "fstp{s|}", 10376 "fldenv{C|C}", 10377 "fldcw", 10378 "fNstenv{C|C}", 10379 "fNstcw", 10380 /* da */ 10381 "fiadd{l|}", 10382 "fimul{l|}", 10383 "ficom{l|}", 10384 "ficomp{l|}", 10385 "fisub{l|}", 10386 "fisubr{l|}", 10387 "fidiv{l|}", 10388 "fidivr{l|}", 10389 /* db */ 10390 "fild{l|}", 10391 "fisttp{l|}", 10392 "fist{l|}", 10393 "fistp{l|}", 10394 "(bad)", 10395 "fld{t|}", 10396 "(bad)", 10397 "fstp{t|}", 10398 /* dc */ 10399 "fadd{l|}", 10400 "fmul{l|}", 10401 "fcom{l|}", 10402 "fcomp{l|}", 10403 "fsub{l|}", 10404 "fsubr{l|}", 10405 "fdiv{l|}", 10406 "fdivr{l|}", 10407 /* dd */ 10408 "fld{l|}", 10409 "fisttp{ll|}", 10410 "fst{l||}", 10411 "fstp{l|}", 10412 "frstor{C|C}", 10413 "(bad)", 10414 "fNsave{C|C}", 10415 "fNstsw", 10416 /* de */ 10417 "fiadd{s|}", 10418 "fimul{s|}", 10419 "ficom{s|}", 10420 "ficomp{s|}", 10421 "fisub{s|}", 10422 "fisubr{s|}", 10423 "fidiv{s|}", 10424 "fidivr{s|}", 10425 /* df */ 10426 "fild{s|}", 10427 "fisttp{s|}", 10428 "fist{s|}", 10429 "fistp{s|}", 10430 "fbld", 10431 "fild{ll|}", 10432 "fbstp", 10433 "fistp{ll|}", 10434 }; 10435 10436 static const unsigned char float_mem_mode[] = { 10437 /* d8 */ 10438 d_mode, 10439 d_mode, 10440 d_mode, 10441 d_mode, 10442 d_mode, 10443 d_mode, 10444 d_mode, 10445 d_mode, 10446 /* d9 */ 10447 d_mode, 10448 0, 10449 d_mode, 10450 d_mode, 10451 0, 10452 w_mode, 10453 0, 10454 w_mode, 10455 /* da */ 10456 d_mode, 10457 d_mode, 10458 d_mode, 10459 d_mode, 10460 d_mode, 10461 d_mode, 10462 d_mode, 10463 d_mode, 10464 /* db */ 10465 d_mode, 10466 d_mode, 10467 d_mode, 10468 d_mode, 10469 0, 10470 t_mode, 10471 0, 10472 t_mode, 10473 /* dc */ 10474 q_mode, 10475 q_mode, 10476 q_mode, 10477 q_mode, 10478 q_mode, 10479 q_mode, 10480 q_mode, 10481 q_mode, 10482 /* dd */ 10483 q_mode, 10484 q_mode, 10485 q_mode, 10486 q_mode, 10487 0, 10488 0, 10489 0, 10490 w_mode, 10491 /* de */ 10492 w_mode, 10493 w_mode, 10494 w_mode, 10495 w_mode, 10496 w_mode, 10497 w_mode, 10498 w_mode, 10499 w_mode, 10500 /* df */ 10501 w_mode, 10502 w_mode, 10503 w_mode, 10504 w_mode, 10505 t_mode, 10506 q_mode, 10507 t_mode, 10508 q_mode 10509 }; 10510 10511 #define ST { OP_ST, 0 } 10512 #define STi { OP_STi, 0 } 10513 10514 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 10515 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 10516 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 10517 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 10518 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 10519 #define FGRPda_5 NULL, { { NULL, 6 } }, 0 10520 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 10521 #define FGRPde_3 NULL, { { NULL, 8 } }, 0 10522 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 10523 10524 static const struct dis386 float_reg[][8] = { 10525 /* d8 */ 10526 { 10527 { "fadd", { ST, STi }, 0 }, 10528 { "fmul", { ST, STi }, 0 }, 10529 { "fcom", { STi }, 0 }, 10530 { "fcomp", { STi }, 0 }, 10531 { "fsub", { ST, STi }, 0 }, 10532 { "fsubr", { ST, STi }, 0 }, 10533 { "fdiv", { ST, STi }, 0 }, 10534 { "fdivr", { ST, STi }, 0 }, 10535 }, 10536 /* d9 */ 10537 { 10538 { "fld", { STi }, 0 }, 10539 { "fxch", { STi }, 0 }, 10540 { FGRPd9_2 }, 10541 { Bad_Opcode }, 10542 { FGRPd9_4 }, 10543 { FGRPd9_5 }, 10544 { FGRPd9_6 }, 10545 { FGRPd9_7 }, 10546 }, 10547 /* da */ 10548 { 10549 { "fcmovb", { ST, STi }, 0 }, 10550 { "fcmove", { ST, STi }, 0 }, 10551 { "fcmovbe",{ ST, STi }, 0 }, 10552 { "fcmovu", { ST, STi }, 0 }, 10553 { Bad_Opcode }, 10554 { FGRPda_5 }, 10555 { Bad_Opcode }, 10556 { Bad_Opcode }, 10557 }, 10558 /* db */ 10559 { 10560 { "fcmovnb",{ ST, STi }, 0 }, 10561 { "fcmovne",{ ST, STi }, 0 }, 10562 { "fcmovnbe",{ ST, STi }, 0 }, 10563 { "fcmovnu",{ ST, STi }, 0 }, 10564 { FGRPdb_4 }, 10565 { "fucomi", { ST, STi }, 0 }, 10566 { "fcomi", { ST, STi }, 0 }, 10567 { Bad_Opcode }, 10568 }, 10569 /* dc */ 10570 { 10571 { "fadd", { STi, ST }, 0 }, 10572 { "fmul", { STi, ST }, 0 }, 10573 { Bad_Opcode }, 10574 { Bad_Opcode }, 10575 { "fsub{!M|r}", { STi, ST }, 0 }, 10576 { "fsub{M|}", { STi, ST }, 0 }, 10577 { "fdiv{!M|r}", { STi, ST }, 0 }, 10578 { "fdiv{M|}", { STi, ST }, 0 }, 10579 }, 10580 /* dd */ 10581 { 10582 { "ffree", { STi }, 0 }, 10583 { Bad_Opcode }, 10584 { "fst", { STi }, 0 }, 10585 { "fstp", { STi }, 0 }, 10586 { "fucom", { STi }, 0 }, 10587 { "fucomp", { STi }, 0 }, 10588 { Bad_Opcode }, 10589 { Bad_Opcode }, 10590 }, 10591 /* de */ 10592 { 10593 { "faddp", { STi, ST }, 0 }, 10594 { "fmulp", { STi, ST }, 0 }, 10595 { Bad_Opcode }, 10596 { FGRPde_3 }, 10597 { "fsub{!M|r}p", { STi, ST }, 0 }, 10598 { "fsub{M|}p", { STi, ST }, 0 }, 10599 { "fdiv{!M|r}p", { STi, ST }, 0 }, 10600 { "fdiv{M|}p", { STi, ST }, 0 }, 10601 }, 10602 /* df */ 10603 { 10604 { "ffreep", { STi }, 0 }, 10605 { Bad_Opcode }, 10606 { Bad_Opcode }, 10607 { Bad_Opcode }, 10608 { FGRPdf_4 }, 10609 { "fucomip", { ST, STi }, 0 }, 10610 { "fcomip", { ST, STi }, 0 }, 10611 { Bad_Opcode }, 10612 }, 10613 }; 10614 10615 static const char *const fgrps[][8] = { 10616 /* Bad opcode 0 */ 10617 { 10618 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10619 }, 10620 10621 /* d9_2 1 */ 10622 { 10623 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10624 }, 10625 10626 /* d9_4 2 */ 10627 { 10628 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", 10629 }, 10630 10631 /* d9_5 3 */ 10632 { 10633 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", 10634 }, 10635 10636 /* d9_6 4 */ 10637 { 10638 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", 10639 }, 10640 10641 /* d9_7 5 */ 10642 { 10643 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", 10644 }, 10645 10646 /* da_5 6 */ 10647 { 10648 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10649 }, 10650 10651 /* db_4 7 */ 10652 { 10653 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", 10654 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", 10655 }, 10656 10657 /* de_3 8 */ 10658 { 10659 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10660 }, 10661 10662 /* df_4 9 */ 10663 { 10664 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10665 }, 10666 }; 10667 10668 static const char *const oszc_flags[16] = { 10669 " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}", 10670 " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}", 10671 " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}", 10672 " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}" 10673 }; 10674 10675 static const char *const scc_suffix[16] = { 10676 "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f", 10677 "l", "ge", "le", "g" 10678 }; 10679 10680 static void 10681 swap_operand (instr_info *ins) 10682 { 10683 char *p = ins->mnemonicendp; 10684 10685 if (p[-1] == '}') 10686 { 10687 while (*--p != '{') 10688 { 10689 if (p <= ins->obuf + 2) 10690 abort (); 10691 } 10692 if (p[-1] == ' ') 10693 --p; 10694 } 10695 memmove (p + 2, p, ins->mnemonicendp - p + 1); 10696 p[0] = '.'; 10697 p[1] = 's'; 10698 ins->mnemonicendp += 2; 10699 } 10700 10701 static bool 10702 dofloat (instr_info *ins, int sizeflag) 10703 { 10704 const struct dis386 *dp; 10705 unsigned char floatop = ins->codep[-1]; 10706 10707 if (ins->modrm.mod != 3) 10708 { 10709 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg; 10710 10711 putop (ins, float_mem[fp_indx], sizeflag); 10712 ins->obufp = ins->op_out[0]; 10713 ins->op_ad = 2; 10714 return OP_E (ins, float_mem_mode[fp_indx], sizeflag); 10715 } 10716 /* Skip mod/rm byte. */ 10717 MODRM_CHECK; 10718 ins->codep++; 10719 10720 dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; 10721 if (dp->name == NULL) 10722 { 10723 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag); 10724 10725 /* Instruction fnstsw is only one with strange arg. */ 10726 if (floatop == 0xdf && ins->codep[-1] == 0xe0) 10727 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax); 10728 } 10729 else 10730 { 10731 putop (ins, dp->name, sizeflag); 10732 10733 ins->obufp = ins->op_out[0]; 10734 ins->op_ad = 2; 10735 if (dp->op[0].rtn 10736 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag)) 10737 return false; 10738 10739 ins->obufp = ins->op_out[1]; 10740 ins->op_ad = 1; 10741 if (dp->op[1].rtn 10742 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag)) 10743 return false; 10744 } 10745 return true; 10746 } 10747 10748 static bool 10749 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 10750 int sizeflag ATTRIBUTE_UNUSED) 10751 { 10752 oappend_register (ins, "%st"); 10753 return true; 10754 } 10755 10756 static bool 10757 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 10758 int sizeflag ATTRIBUTE_UNUSED) 10759 { 10760 char scratch[8]; 10761 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm); 10762 10763 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 10764 abort (); 10765 oappend_register (ins, scratch); 10766 return true; 10767 } 10768 10769 /* Capital letters in template are macros. */ 10770 static int 10771 putop (instr_info *ins, const char *in_template, int sizeflag) 10772 { 10773 const char *p; 10774 int alt = 0; 10775 int cond = 1; 10776 unsigned int l = 0, len = 0; 10777 char last[4]; 10778 bool evex_printed = false; 10779 10780 /* We don't want to add any prefix or suffix to (bad), so return early. */ 10781 if (!strncmp (in_template, "(bad)", 5)) 10782 { 10783 oappend (ins, "(bad)"); 10784 *ins->obufp = 0; 10785 ins->mnemonicendp = ins->obufp; 10786 return 0; 10787 } 10788 10789 for (p = in_template; *p; p++) 10790 { 10791 if (len > l) 10792 { 10793 if (l >= sizeof (last) || !ISUPPER (*p)) 10794 abort (); 10795 last[l++] = *p; 10796 continue; 10797 } 10798 switch (*p) 10799 { 10800 default: 10801 if (ins->evex_type == evex_from_legacy && !ins->vex.nd 10802 && !(ins->rex2 & 7) && !evex_printed) 10803 { 10804 oappend (ins, "{evex} "); 10805 evex_printed = true; 10806 } 10807 *ins->obufp++ = *p; 10808 break; 10809 case '%': 10810 len++; 10811 break; 10812 case '!': 10813 cond = 0; 10814 break; 10815 case '{': 10816 if (ins->intel_syntax) 10817 { 10818 while (*++p != '|') 10819 if (*p == '}' || *p == '\0') 10820 abort (); 10821 alt = 1; 10822 } 10823 break; 10824 case '|': 10825 while (*++p != '}') 10826 { 10827 if (*p == '\0') 10828 abort (); 10829 } 10830 break; 10831 case '}': 10832 alt = 0; 10833 break; 10834 case 'A': 10835 if (ins->intel_syntax) 10836 break; 10837 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) 10838 || (sizeflag & SUFFIX_ALWAYS)) 10839 *ins->obufp++ = 'b'; 10840 break; 10841 case 'B': 10842 if (l == 0) 10843 { 10844 case_B: 10845 if (ins->intel_syntax) 10846 break; 10847 if (sizeflag & SUFFIX_ALWAYS) 10848 *ins->obufp++ = 'b'; 10849 } 10850 else if (l == 1 && last[0] == 'L') 10851 { 10852 if (ins->address_mode == mode_64bit 10853 && !(ins->prefixes & PREFIX_ADDR)) 10854 { 10855 *ins->obufp++ = 'a'; 10856 *ins->obufp++ = 'b'; 10857 *ins->obufp++ = 's'; 10858 } 10859 10860 goto case_B; 10861 } 10862 else if (l && last[0] == 'X') 10863 { 10864 if (!ins->vex.w) 10865 oappend (ins, "bf16"); 10866 else 10867 oappend (ins, "{bad}"); 10868 } 10869 else 10870 abort (); 10871 break; 10872 case 'C': 10873 if (l == 1 && last[0] == 'C') 10874 { 10875 /* Condition code (taken from the map-0 Jcc entries). */ 10876 for (const char *q = dis386[0x70 | ins->condition_code].name + 1; 10877 ISLOWER(*q); ++q) 10878 *ins->obufp++ = *q; 10879 break; 10880 } 10881 else if (l == 1 && last[0] == 'S') 10882 { 10883 /* Add scc suffix. */ 10884 oappend (ins, scc_suffix[ins->vex.scc]); 10885 10886 /* For SCC insns, the ND bit is required to be set to 0. */ 10887 if (ins->vex.nd) 10888 oappend (ins, "(bad)"); 10889 10890 /* These bits have been consumed and should be cleared or restored 10891 to default values. */ 10892 ins->vex.v = 1; 10893 ins->vex.nf = false; 10894 ins->vex.mask_register_specifier = 0; 10895 break; 10896 } 10897 10898 if (l) 10899 abort (); 10900 if (ins->intel_syntax && !alt) 10901 break; 10902 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 10903 { 10904 if (sizeflag & DFLAG) 10905 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10906 else 10907 *ins->obufp++ = ins->intel_syntax ? 'w' : 's'; 10908 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10909 } 10910 break; 10911 case 'D': 10912 if (l == 1) 10913 { 10914 switch (last[0]) 10915 { 10916 case 'X': 10917 if (!ins->vex.evex || ins->vex.w) 10918 *ins->obufp++ = 'd'; 10919 else 10920 oappend (ins, "{bad}"); 10921 break; 10922 default: 10923 abort (); 10924 } 10925 break; 10926 } 10927 if (l) 10928 abort (); 10929 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 10930 break; 10931 USED_REX (REX_W); 10932 if (ins->modrm.mod == 3) 10933 { 10934 if (ins->rex & REX_W) 10935 *ins->obufp++ = 'q'; 10936 else 10937 { 10938 if (sizeflag & DFLAG) 10939 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 10940 else 10941 *ins->obufp++ = 'w'; 10942 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 10943 } 10944 } 10945 else 10946 *ins->obufp++ = 'w'; 10947 break; 10948 case 'E': 10949 if (l == 1) 10950 { 10951 switch (last[0]) 10952 { 10953 case 'M': 10954 if (ins->modrm.mod != 3) 10955 break; 10956 /* Fall through. */ 10957 case 'X': 10958 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 10959 || (ins->rex2 & 7) 10960 || (ins->modrm.mod == 3 && (ins->rex & REX_X)) 10961 || !ins->vex.v || ins->vex.mask_register_specifier) 10962 break; 10963 /* AVX512 extends a number of V*D insns to also have V*Q variants, 10964 merely distinguished by EVEX.W. Look for a use of the 10965 respective macro. */ 10966 if (ins->vex.w) 10967 { 10968 const char *pct = strchr (p + 1, '%'); 10969 10970 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q') 10971 break; 10972 } 10973 *ins->obufp++ = '{'; 10974 *ins->obufp++ = 'e'; 10975 *ins->obufp++ = 'v'; 10976 *ins->obufp++ = 'e'; 10977 *ins->obufp++ = 'x'; 10978 *ins->obufp++ = '}'; 10979 *ins->obufp++ = ' '; 10980 break; 10981 case 'N': 10982 /* Skip printing {evex} for some special instructions in MAP4. */ 10983 evex_printed = true; 10984 break; 10985 default: 10986 abort (); 10987 } 10988 break; 10989 } 10990 /* For jcxz/jecxz */ 10991 if (ins->address_mode == mode_64bit) 10992 { 10993 if (sizeflag & AFLAG) 10994 *ins->obufp++ = 'r'; 10995 else 10996 *ins->obufp++ = 'e'; 10997 } 10998 else 10999 if (sizeflag & AFLAG) 11000 *ins->obufp++ = 'e'; 11001 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 11002 break; 11003 case 'F': 11004 if (l == 0) 11005 { 11006 if (ins->intel_syntax) 11007 break; 11008 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) 11009 { 11010 if (sizeflag & AFLAG) 11011 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; 11012 else 11013 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w'; 11014 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 11015 } 11016 } 11017 else if (l == 1 && last[0] == 'C') 11018 { 11019 if (ins->vex.nd && !ins->vex.nf) 11020 break; 11021 *ins->obufp++ = 'c'; 11022 *ins->obufp++ = 'f'; 11023 /* Skip printing {evex} */ 11024 evex_printed = true; 11025 } 11026 else if (l == 1 && last[0] == 'N') 11027 { 11028 if (ins->vex.nf) 11029 { 11030 oappend (ins, "{nf} "); 11031 /* This bit needs to be cleared after it is consumed. */ 11032 ins->vex.nf = false; 11033 evex_printed = true; 11034 } 11035 else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7) 11036 && ins->vex.v) 11037 { 11038 oappend (ins, "{evex} "); 11039 evex_printed = true; 11040 } 11041 } 11042 else if (l == 1 && last[0] == 'D') 11043 { 11044 /* Get oszc flags value from register_specifier. */ 11045 int oszc_value = ~ins->vex.register_specifier & 0xf; 11046 11047 /* Add {dfv=of, sf, zf, cf} flags. */ 11048 oappend (ins, oszc_flags[oszc_value]); 11049 11050 /* These bits have been consumed and should be cleared. */ 11051 ins->vex.register_specifier = 0; 11052 } 11053 else 11054 abort (); 11055 break; 11056 case 'G': 11057 if (ins->intel_syntax || (ins->obufp[-1] != 's' 11058 && !(sizeflag & SUFFIX_ALWAYS))) 11059 break; 11060 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 11061 *ins->obufp++ = 'l'; 11062 else 11063 *ins->obufp++ = 'w'; 11064 if (!(ins->rex & REX_W)) 11065 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11066 break; 11067 case 'H': 11068 if (l == 0) 11069 { 11070 if (ins->intel_syntax) 11071 break; 11072 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS 11073 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) 11074 { 11075 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS); 11076 *ins->obufp++ = ','; 11077 *ins->obufp++ = 'p'; 11078 11079 /* Set active_seg_prefix even if not set in 64-bit mode 11080 because here it is a valid branch hint. */ 11081 if (ins->prefixes & PREFIX_DS) 11082 { 11083 ins->active_seg_prefix = PREFIX_DS; 11084 *ins->obufp++ = 't'; 11085 } 11086 else 11087 { 11088 ins->active_seg_prefix = PREFIX_CS; 11089 *ins->obufp++ = 'n'; 11090 } 11091 } 11092 } 11093 else if (l == 1 && last[0] == 'X') 11094 { 11095 if (!ins->vex.w) 11096 *ins->obufp++ = 'h'; 11097 else 11098 oappend (ins, "{bad}"); 11099 } 11100 else 11101 abort (); 11102 break; 11103 case 'K': 11104 USED_REX (REX_W); 11105 if (ins->rex & REX_W) 11106 *ins->obufp++ = 'q'; 11107 else 11108 *ins->obufp++ = 'd'; 11109 break; 11110 case 'L': 11111 if (ins->intel_syntax) 11112 break; 11113 if (sizeflag & SUFFIX_ALWAYS) 11114 { 11115 if (ins->rex & REX_W) 11116 *ins->obufp++ = 'q'; 11117 else 11118 *ins->obufp++ = 'l'; 11119 } 11120 break; 11121 case 'M': 11122 if (ins->intel_mnemonic != cond) 11123 *ins->obufp++ = 'r'; 11124 break; 11125 case 'N': 11126 if ((ins->prefixes & PREFIX_FWAIT) == 0) 11127 *ins->obufp++ = 'n'; 11128 else 11129 ins->used_prefixes |= PREFIX_FWAIT; 11130 break; 11131 case 'O': 11132 USED_REX (REX_W); 11133 if (ins->rex & REX_W) 11134 *ins->obufp++ = 'o'; 11135 else if (ins->intel_syntax && (sizeflag & DFLAG)) 11136 *ins->obufp++ = 'q'; 11137 else 11138 *ins->obufp++ = 'd'; 11139 if (!(ins->rex & REX_W)) 11140 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11141 break; 11142 case '@': 11143 if (ins->address_mode == mode_64bit 11144 && (ins->isa64 == intel64 || (ins->rex & REX_W) 11145 || !(ins->prefixes & PREFIX_DATA))) 11146 { 11147 if (sizeflag & SUFFIX_ALWAYS) 11148 *ins->obufp++ = 'q'; 11149 break; 11150 } 11151 /* Fall through. */ 11152 case 'P': 11153 if (l == 0) 11154 { 11155 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W)) 11156 { 11157 /* For pushp and popp, p is printed and do not print {rex2} 11158 for them. */ 11159 *ins->obufp++ = 'p'; 11160 ins->rex2 |= REX2_SPECIAL; 11161 break; 11162 } 11163 11164 /* For "!P" print nothing else in Intel syntax. */ 11165 if (!cond && ins->intel_syntax) 11166 break; 11167 11168 if ((ins->modrm.mod == 3 || !cond) 11169 && !(sizeflag & SUFFIX_ALWAYS)) 11170 break; 11171 /* Fall through. */ 11172 case 'T': 11173 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA)) 11174 || ((sizeflag & SUFFIX_ALWAYS) 11175 && ins->address_mode != mode_64bit)) 11176 { 11177 *ins->obufp++ = (sizeflag & DFLAG) 11178 ? ins->intel_syntax ? 'd' : 'l' : 'w'; 11179 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11180 } 11181 else if (sizeflag & SUFFIX_ALWAYS) 11182 *ins->obufp++ = 'q'; 11183 } 11184 else if (l == 1 && last[0] == 'L') 11185 { 11186 if ((ins->prefixes & PREFIX_DATA) 11187 || (ins->rex & REX_W) 11188 || (sizeflag & SUFFIX_ALWAYS)) 11189 { 11190 USED_REX (REX_W); 11191 if (ins->rex & REX_W) 11192 *ins->obufp++ = 'q'; 11193 else 11194 { 11195 if (sizeflag & DFLAG) 11196 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 11197 else 11198 *ins->obufp++ = 'w'; 11199 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11200 } 11201 } 11202 } 11203 else 11204 abort (); 11205 break; 11206 case 'Q': 11207 if (l == 0) 11208 { 11209 if (ins->intel_syntax && !alt) 11210 break; 11211 USED_REX (REX_W); 11212 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd) 11213 || (sizeflag & SUFFIX_ALWAYS)) 11214 { 11215 if (ins->rex & REX_W) 11216 *ins->obufp++ = 'q'; 11217 else 11218 { 11219 if (sizeflag & DFLAG) 11220 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; 11221 else 11222 *ins->obufp++ = 'w'; 11223 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11224 } 11225 } 11226 } 11227 else if (l == 1 && last[0] == 'D') 11228 *ins->obufp++ = ins->vex.w ? 'q' : 'd'; 11229 else if (l == 1 && last[0] == 'L') 11230 { 11231 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) 11232 : ins->address_mode != mode_64bit) 11233 break; 11234 if ((ins->rex & REX_W)) 11235 { 11236 USED_REX (REX_W); 11237 *ins->obufp++ = 'q'; 11238 } 11239 else if ((ins->address_mode == mode_64bit && cond) 11240 || (sizeflag & SUFFIX_ALWAYS)) 11241 *ins->obufp++ = ins->intel_syntax? 'd' : 'l'; 11242 } 11243 else 11244 abort (); 11245 break; 11246 case 'R': 11247 USED_REX (REX_W); 11248 if (ins->rex & REX_W) 11249 *ins->obufp++ = 'q'; 11250 else if (sizeflag & DFLAG) 11251 { 11252 if (ins->intel_syntax) 11253 *ins->obufp++ = 'd'; 11254 else 11255 *ins->obufp++ = 'l'; 11256 } 11257 else 11258 *ins->obufp++ = 'w'; 11259 if (ins->intel_syntax && !p[1] 11260 && ((ins->rex & REX_W) || (sizeflag & DFLAG))) 11261 *ins->obufp++ = 'e'; 11262 if (!(ins->rex & REX_W)) 11263 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11264 break; 11265 case 'S': 11266 if (l == 0) 11267 { 11268 case_S: 11269 if (ins->intel_syntax) 11270 break; 11271 if (sizeflag & SUFFIX_ALWAYS) 11272 { 11273 if (ins->rex & REX_W) 11274 *ins->obufp++ = 'q'; 11275 else 11276 { 11277 if (sizeflag & DFLAG) 11278 *ins->obufp++ = 'l'; 11279 else 11280 *ins->obufp++ = 'w'; 11281 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11282 } 11283 } 11284 break; 11285 } 11286 if (l != 1) 11287 abort (); 11288 switch (last[0]) 11289 { 11290 case 'L': 11291 if (ins->address_mode == mode_64bit 11292 && !(ins->prefixes & PREFIX_ADDR)) 11293 { 11294 *ins->obufp++ = 'a'; 11295 *ins->obufp++ = 'b'; 11296 *ins->obufp++ = 's'; 11297 } 11298 11299 goto case_S; 11300 case 'X': 11301 if (!ins->vex.evex || !ins->vex.w) 11302 *ins->obufp++ = 's'; 11303 else 11304 oappend (ins, "{bad}"); 11305 break; 11306 default: 11307 abort (); 11308 } 11309 break; 11310 case 'U': 11311 if (l == 1 && (last[0] == 'Z')) 11312 { 11313 /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is 11314 used to control whether its destination register has its upper 11315 bits zeroed. */ 11316 if (ins->vex.nd) 11317 oappend (ins, "zu"); 11318 } 11319 else 11320 abort (); 11321 break; 11322 case 'V': 11323 if (l == 0) 11324 { 11325 if (ins->need_vex) 11326 *ins->obufp++ = 'v'; 11327 } 11328 else if (l == 1) 11329 { 11330 switch (last[0]) 11331 { 11332 case 'X': 11333 if (ins->vex.evex) 11334 break; 11335 *ins->obufp++ = '{'; 11336 *ins->obufp++ = 'v'; 11337 *ins->obufp++ = 'e'; 11338 *ins->obufp++ = 'x'; 11339 *ins->obufp++ = '}'; 11340 *ins->obufp++ = ' '; 11341 break; 11342 case 'L': 11343 if (ins->rex & REX_W) 11344 { 11345 *ins->obufp++ = 'a'; 11346 *ins->obufp++ = 'b'; 11347 *ins->obufp++ = 's'; 11348 } 11349 goto case_S; 11350 default: 11351 abort (); 11352 } 11353 } 11354 else 11355 abort (); 11356 break; 11357 case 'W': 11358 if (l == 0) 11359 { 11360 /* operand size flag for cwtl, cbtw */ 11361 USED_REX (REX_W); 11362 if (ins->rex & REX_W) 11363 { 11364 if (ins->intel_syntax) 11365 *ins->obufp++ = 'd'; 11366 else 11367 *ins->obufp++ = 'l'; 11368 } 11369 else if (sizeflag & DFLAG) 11370 *ins->obufp++ = 'w'; 11371 else 11372 *ins->obufp++ = 'b'; 11373 if (!(ins->rex & REX_W)) 11374 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11375 } 11376 else if (l == 1) 11377 { 11378 if (!ins->need_vex) 11379 abort (); 11380 if (last[0] == 'X') 11381 *ins->obufp++ = ins->vex.w ? 'd': 's'; 11382 else if (last[0] == 'B') 11383 *ins->obufp++ = ins->vex.w ? 'w': 'b'; 11384 else 11385 abort (); 11386 } 11387 else 11388 abort (); 11389 break; 11390 case 'X': 11391 if (l != 0) 11392 abort (); 11393 if (ins->need_vex 11394 ? ins->vex.prefix == DATA_PREFIX_OPCODE 11395 : ins->prefixes & PREFIX_DATA) 11396 { 11397 *ins->obufp++ = 'd'; 11398 ins->used_prefixes |= PREFIX_DATA; 11399 } 11400 else 11401 *ins->obufp++ = 's'; 11402 break; 11403 case 'Y': 11404 if (l == 0) 11405 { 11406 if (ins->vex.mask_register_specifier) 11407 ins->illegal_masking = true; 11408 } 11409 else if (l == 1 && last[0] == 'X') 11410 { 11411 if (!ins->need_vex) 11412 break; 11413 if (ins->intel_syntax 11414 || ((ins->modrm.mod == 3 || ins->vex.b) 11415 && !(sizeflag & SUFFIX_ALWAYS))) 11416 break; 11417 switch (ins->vex.length) 11418 { 11419 case 128: 11420 *ins->obufp++ = 'x'; 11421 break; 11422 case 256: 11423 *ins->obufp++ = 'y'; 11424 break; 11425 case 512: 11426 if (!ins->vex.evex) 11427 default: 11428 abort (); 11429 } 11430 } 11431 else 11432 abort (); 11433 break; 11434 case 'Z': 11435 if (l == 0) 11436 { 11437 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ 11438 ins->modrm.mod = 3; 11439 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 11440 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; 11441 } 11442 else if (l == 1 && last[0] == 'X') 11443 { 11444 if (!ins->vex.evex) 11445 abort (); 11446 if (ins->intel_syntax 11447 || ((ins->modrm.mod == 3 || ins->vex.b) 11448 && !(sizeflag & SUFFIX_ALWAYS))) 11449 break; 11450 switch (ins->vex.length) 11451 { 11452 case 128: 11453 *ins->obufp++ = 'x'; 11454 break; 11455 case 256: 11456 *ins->obufp++ = 'y'; 11457 break; 11458 case 512: 11459 *ins->obufp++ = 'z'; 11460 break; 11461 default: 11462 abort (); 11463 } 11464 } 11465 else 11466 abort (); 11467 break; 11468 case '^': 11469 if (ins->intel_syntax) 11470 break; 11471 if (ins->isa64 == intel64 && (ins->rex & REX_W)) 11472 { 11473 USED_REX (REX_W); 11474 *ins->obufp++ = 'q'; 11475 break; 11476 } 11477 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 11478 { 11479 if (sizeflag & DFLAG) 11480 *ins->obufp++ = 'l'; 11481 else 11482 *ins->obufp++ = 'w'; 11483 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11484 } 11485 break; 11486 } 11487 11488 if (len == l) 11489 len = l = 0; 11490 } 11491 *ins->obufp = 0; 11492 ins->mnemonicendp = ins->obufp; 11493 return 0; 11494 } 11495 11496 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that 11497 the buffer pointed to by INS->obufp has space. A style marker is made 11498 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex 11499 digit, followed by another STYLE_MARKER_CHAR. This function assumes 11500 that the number of styles is not greater than 16. */ 11501 11502 static void 11503 oappend_insert_style (instr_info *ins, enum disassembler_style style) 11504 { 11505 unsigned num = (unsigned) style; 11506 11507 /* We currently assume that STYLE can be encoded as a single hex 11508 character. If more styles are added then this might start to fail, 11509 and we'll need to expand this code. */ 11510 if (num > 0xf) 11511 abort (); 11512 11513 *ins->obufp++ = STYLE_MARKER_CHAR; 11514 *ins->obufp++ = (num < 10 ? ('0' + num) 11515 : ((num < 16) ? ('a' + (num - 10)) : '0')); 11516 *ins->obufp++ = STYLE_MARKER_CHAR; 11517 11518 /* This final null character is not strictly necessary, after inserting a 11519 style marker we should always be inserting some additional content. 11520 However, having the buffer null terminated doesn't cost much, and make 11521 it easier to debug what's going on. Also, if we do ever forget to add 11522 any additional content after this style marker, then the buffer will 11523 still be well formed. */ 11524 *ins->obufp = '\0'; 11525 } 11526 11527 static void 11528 oappend_with_style (instr_info *ins, const char *s, 11529 enum disassembler_style style) 11530 { 11531 oappend_insert_style (ins, style); 11532 ins->obufp = stpcpy (ins->obufp, s); 11533 } 11534 11535 /* Add a single character C to the buffer pointer to by INS->obufp, marking 11536 the style for the character as STYLE. */ 11537 11538 static void 11539 oappend_char_with_style (instr_info *ins, const char c, 11540 enum disassembler_style style) 11541 { 11542 oappend_insert_style (ins, style); 11543 *ins->obufp++ = c; 11544 *ins->obufp = '\0'; 11545 } 11546 11547 /* Like oappend_char_with_style, but always uses dis_style_text. */ 11548 11549 static void 11550 oappend_char (instr_info *ins, const char c) 11551 { 11552 oappend_char_with_style (ins, c, dis_style_text); 11553 } 11554 11555 static void 11556 append_seg (instr_info *ins) 11557 { 11558 /* Only print the active segment register. */ 11559 if (!ins->active_seg_prefix) 11560 return; 11561 11562 ins->used_prefixes |= ins->active_seg_prefix; 11563 switch (ins->active_seg_prefix) 11564 { 11565 case PREFIX_CS: 11566 oappend_register (ins, att_names_seg[1]); 11567 break; 11568 case PREFIX_DS: 11569 oappend_register (ins, att_names_seg[3]); 11570 break; 11571 case PREFIX_SS: 11572 oappend_register (ins, att_names_seg[2]); 11573 break; 11574 case PREFIX_ES: 11575 oappend_register (ins, att_names_seg[0]); 11576 break; 11577 case PREFIX_FS: 11578 oappend_register (ins, att_names_seg[4]); 11579 break; 11580 case PREFIX_GS: 11581 oappend_register (ins, att_names_seg[5]); 11582 break; 11583 default: 11584 break; 11585 } 11586 oappend_char (ins, ':'); 11587 } 11588 11589 static void 11590 print_operand_value (instr_info *ins, bfd_vma disp, 11591 enum disassembler_style style) 11592 { 11593 char tmp[30]; 11594 11595 if (ins->address_mode != mode_64bit) 11596 disp &= 0xffffffff; 11597 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp); 11598 oappend_with_style (ins, tmp, style); 11599 } 11600 11601 /* Like oappend, but called for immediate operands. */ 11602 11603 static void 11604 oappend_immediate (instr_info *ins, bfd_vma imm) 11605 { 11606 if (!ins->intel_syntax) 11607 oappend_char_with_style (ins, '$', dis_style_immediate); 11608 print_operand_value (ins, imm, dis_style_immediate); 11609 } 11610 11611 /* Put DISP in BUF as signed hex number. */ 11612 11613 static void 11614 print_displacement (instr_info *ins, bfd_signed_vma val) 11615 { 11616 char tmp[30]; 11617 11618 if (val < 0) 11619 { 11620 oappend_char_with_style (ins, '-', dis_style_address_offset); 11621 val = (bfd_vma) 0 - val; 11622 11623 /* Check for possible overflow. */ 11624 if (val < 0) 11625 { 11626 switch (ins->address_mode) 11627 { 11628 case mode_64bit: 11629 oappend_with_style (ins, "0x8000000000000000", 11630 dis_style_address_offset); 11631 break; 11632 case mode_32bit: 11633 oappend_with_style (ins, "0x80000000", 11634 dis_style_address_offset); 11635 break; 11636 case mode_16bit: 11637 oappend_with_style (ins, "0x8000", 11638 dis_style_address_offset); 11639 break; 11640 } 11641 return; 11642 } 11643 } 11644 11645 sprintf (tmp, "0x%" PRIx64, (int64_t) val); 11646 oappend_with_style (ins, tmp, dis_style_address_offset); 11647 } 11648 11649 static void 11650 intel_operand_size (instr_info *ins, int bytemode, int sizeflag) 11651 { 11652 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */ 11653 if (ins->vex.b && ins->evex_type == evex_default) 11654 { 11655 if (!ins->vex.no_broadcast) 11656 switch (bytemode) 11657 { 11658 case x_mode: 11659 case evex_half_bcst_xmmq_mode: 11660 if (ins->vex.w) 11661 oappend (ins, "QWORD BCST "); 11662 else 11663 oappend (ins, "DWORD BCST "); 11664 break; 11665 case xh_mode: 11666 case evex_half_bcst_xmmqh_mode: 11667 case evex_half_bcst_xmmqdh_mode: 11668 oappend (ins, "WORD BCST "); 11669 break; 11670 default: 11671 ins->vex.no_broadcast = true; 11672 break; 11673 } 11674 return; 11675 } 11676 switch (bytemode) 11677 { 11678 case b_mode: 11679 case b_swap_mode: 11680 case db_mode: 11681 oappend (ins, "BYTE PTR "); 11682 break; 11683 case w_mode: 11684 case w_swap_mode: 11685 case dw_mode: 11686 oappend (ins, "WORD PTR "); 11687 break; 11688 case indir_v_mode: 11689 if (ins->address_mode == mode_64bit && ins->isa64 == intel64) 11690 { 11691 oappend (ins, "QWORD PTR "); 11692 break; 11693 } 11694 /* Fall through. */ 11695 case stack_v_mode: 11696 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) 11697 || (ins->rex & REX_W))) 11698 { 11699 oappend (ins, "QWORD PTR "); 11700 break; 11701 } 11702 /* Fall through. */ 11703 case v_mode: 11704 case v_swap_mode: 11705 case dq_mode: 11706 USED_REX (REX_W); 11707 if (ins->rex & REX_W) 11708 oappend (ins, "QWORD PTR "); 11709 else if (bytemode == dq_mode) 11710 oappend (ins, "DWORD PTR "); 11711 else 11712 { 11713 if (sizeflag & DFLAG) 11714 oappend (ins, "DWORD PTR "); 11715 else 11716 oappend (ins, "WORD PTR "); 11717 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11718 } 11719 break; 11720 case z_mode: 11721 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 11722 *ins->obufp++ = 'D'; 11723 oappend (ins, "WORD PTR "); 11724 if (!(ins->rex & REX_W)) 11725 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11726 break; 11727 case a_mode: 11728 if (sizeflag & DFLAG) 11729 oappend (ins, "QWORD PTR "); 11730 else 11731 oappend (ins, "DWORD PTR "); 11732 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11733 break; 11734 case movsxd_mode: 11735 if (!(sizeflag & DFLAG) && ins->isa64 == intel64) 11736 oappend (ins, "WORD PTR "); 11737 else 11738 oappend (ins, "DWORD PTR "); 11739 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11740 break; 11741 case d_mode: 11742 case d_swap_mode: 11743 oappend (ins, "DWORD PTR "); 11744 break; 11745 case q_mode: 11746 case q_swap_mode: 11747 oappend (ins, "QWORD PTR "); 11748 break; 11749 case m_mode: 11750 if (ins->address_mode == mode_64bit) 11751 oappend (ins, "QWORD PTR "); 11752 else 11753 oappend (ins, "DWORD PTR "); 11754 break; 11755 case f_mode: 11756 if (sizeflag & DFLAG) 11757 oappend (ins, "FWORD PTR "); 11758 else 11759 oappend (ins, "DWORD PTR "); 11760 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11761 break; 11762 case t_mode: 11763 oappend (ins, "TBYTE PTR "); 11764 break; 11765 case x_mode: 11766 case xh_mode: 11767 case x_swap_mode: 11768 case evex_x_gscat_mode: 11769 case evex_x_nobcst_mode: 11770 case bw_unit_mode: 11771 if (ins->need_vex) 11772 { 11773 switch (ins->vex.length) 11774 { 11775 case 128: 11776 oappend (ins, "XMMWORD PTR "); 11777 break; 11778 case 256: 11779 oappend (ins, "YMMWORD PTR "); 11780 break; 11781 case 512: 11782 oappend (ins, "ZMMWORD PTR "); 11783 break; 11784 default: 11785 abort (); 11786 } 11787 } 11788 else 11789 oappend (ins, "XMMWORD PTR "); 11790 break; 11791 case xmm_mode: 11792 oappend (ins, "XMMWORD PTR "); 11793 break; 11794 case ymm_mode: 11795 oappend (ins, "YMMWORD PTR "); 11796 break; 11797 case xmmq_mode: 11798 case evex_half_bcst_xmmqh_mode: 11799 case evex_half_bcst_xmmq_mode: 11800 switch (ins->vex.length) 11801 { 11802 case 0: 11803 case 128: 11804 oappend (ins, "QWORD PTR "); 11805 break; 11806 case 256: 11807 oappend (ins, "XMMWORD PTR "); 11808 break; 11809 case 512: 11810 oappend (ins, "YMMWORD PTR "); 11811 break; 11812 default: 11813 abort (); 11814 } 11815 break; 11816 case xmmdw_mode: 11817 if (!ins->need_vex) 11818 abort (); 11819 11820 switch (ins->vex.length) 11821 { 11822 case 128: 11823 oappend (ins, "WORD PTR "); 11824 break; 11825 case 256: 11826 oappend (ins, "DWORD PTR "); 11827 break; 11828 case 512: 11829 oappend (ins, "QWORD PTR "); 11830 break; 11831 default: 11832 abort (); 11833 } 11834 break; 11835 case xmmqd_mode: 11836 case evex_half_bcst_xmmqdh_mode: 11837 if (!ins->need_vex) 11838 abort (); 11839 11840 switch (ins->vex.length) 11841 { 11842 case 128: 11843 oappend (ins, "DWORD PTR "); 11844 break; 11845 case 256: 11846 oappend (ins, "QWORD PTR "); 11847 break; 11848 case 512: 11849 oappend (ins, "XMMWORD PTR "); 11850 break; 11851 default: 11852 abort (); 11853 } 11854 break; 11855 case ymmq_mode: 11856 if (!ins->need_vex) 11857 abort (); 11858 11859 switch (ins->vex.length) 11860 { 11861 case 128: 11862 oappend (ins, "QWORD PTR "); 11863 break; 11864 case 256: 11865 oappend (ins, "YMMWORD PTR "); 11866 break; 11867 case 512: 11868 oappend (ins, "ZMMWORD PTR "); 11869 break; 11870 default: 11871 abort (); 11872 } 11873 break; 11874 case o_mode: 11875 oappend (ins, "OWORD PTR "); 11876 break; 11877 case vex_vsib_d_w_dq_mode: 11878 case vex_vsib_q_w_dq_mode: 11879 if (!ins->need_vex) 11880 abort (); 11881 if (ins->vex.w) 11882 oappend (ins, "QWORD PTR "); 11883 else 11884 oappend (ins, "DWORD PTR "); 11885 break; 11886 case mask_bd_mode: 11887 if (!ins->need_vex || ins->vex.length != 128) 11888 abort (); 11889 if (ins->vex.w) 11890 oappend (ins, "DWORD PTR "); 11891 else 11892 oappend (ins, "BYTE PTR "); 11893 break; 11894 case mask_mode: 11895 if (!ins->need_vex) 11896 abort (); 11897 if (ins->vex.w) 11898 oappend (ins, "QWORD PTR "); 11899 else 11900 oappend (ins, "WORD PTR "); 11901 break; 11902 case v_bnd_mode: 11903 case v_bndmk_mode: 11904 default: 11905 break; 11906 } 11907 } 11908 11909 static void 11910 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, 11911 int bytemode, int sizeflag) 11912 { 11913 const char (*names)[8]; 11914 11915 /* Masking is invalid for insns with GPR destination. Set the flag uniformly, 11916 as the consumer will inspect it only for the destination operand. */ 11917 if (bytemode != mask_mode && ins->vex.mask_register_specifier) 11918 ins->illegal_masking = true; 11919 11920 USED_REX (rexmask); 11921 if (ins->rex & rexmask) 11922 reg += 8; 11923 if (ins->rex2 & rexmask) 11924 reg += 16; 11925 11926 switch (bytemode) 11927 { 11928 case b_mode: 11929 case b_swap_mode: 11930 if (reg & 4) 11931 USED_REX (0); 11932 if (ins->rex || ins->rex2) 11933 names = att_names8rex; 11934 else 11935 names = att_names8; 11936 break; 11937 case w_mode: 11938 names = att_names16; 11939 break; 11940 case d_mode: 11941 case dw_mode: 11942 case db_mode: 11943 names = att_names32; 11944 break; 11945 case q_mode: 11946 names = att_names64; 11947 break; 11948 case m_mode: 11949 case v_bnd_mode: 11950 names = ins->address_mode == mode_64bit ? att_names64 : att_names32; 11951 break; 11952 case bnd_mode: 11953 case bnd_swap_mode: 11954 if (reg > 0x3) 11955 { 11956 oappend (ins, "(bad)"); 11957 return; 11958 } 11959 names = att_names_bnd; 11960 break; 11961 case indir_v_mode: 11962 if (ins->address_mode == mode_64bit && ins->isa64 == intel64) 11963 { 11964 names = att_names64; 11965 break; 11966 } 11967 /* Fall through. */ 11968 case stack_v_mode: 11969 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) 11970 || (ins->rex & REX_W))) 11971 { 11972 names = att_names64; 11973 break; 11974 } 11975 bytemode = v_mode; 11976 /* Fall through. */ 11977 case v_mode: 11978 case v_swap_mode: 11979 case dq_mode: 11980 USED_REX (REX_W); 11981 if (ins->rex & REX_W) 11982 names = att_names64; 11983 else if (bytemode != v_mode && bytemode != v_swap_mode) 11984 names = att_names32; 11985 else 11986 { 11987 if (sizeflag & DFLAG) 11988 names = att_names32; 11989 else 11990 names = att_names16; 11991 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 11992 } 11993 break; 11994 case movsxd_mode: 11995 if (!(sizeflag & DFLAG) && ins->isa64 == intel64) 11996 names = att_names16; 11997 else 11998 names = att_names32; 11999 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12000 break; 12001 case va_mode: 12002 names = (ins->address_mode == mode_64bit 12003 ? att_names64 : att_names32); 12004 if (!(ins->prefixes & PREFIX_ADDR)) 12005 names = (ins->address_mode == mode_16bit 12006 ? att_names16 : names); 12007 else 12008 { 12009 /* Remove "addr16/addr32". */ 12010 ins->all_prefixes[ins->last_addr_prefix] = 0; 12011 names = (ins->address_mode != mode_32bit 12012 ? att_names32 : att_names16); 12013 ins->used_prefixes |= PREFIX_ADDR; 12014 } 12015 break; 12016 case mask_bd_mode: 12017 case mask_mode: 12018 if (reg > 0x7) 12019 { 12020 oappend (ins, "(bad)"); 12021 return; 12022 } 12023 names = att_names_mask; 12024 break; 12025 case 0: 12026 return; 12027 default: 12028 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12029 return; 12030 } 12031 oappend_register (ins, names[reg]); 12032 } 12033 12034 static bool 12035 get8s (instr_info *ins, bfd_vma *res) 12036 { 12037 if (!fetch_code (ins->info, ins->codep + 1)) 12038 return false; 12039 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80; 12040 return true; 12041 } 12042 12043 static bool 12044 get16 (instr_info *ins, bfd_vma *res) 12045 { 12046 if (!fetch_code (ins->info, ins->codep + 2)) 12047 return false; 12048 *res = *ins->codep++; 12049 *res |= (bfd_vma) *ins->codep++ << 8; 12050 return true; 12051 } 12052 12053 static bool 12054 get16s (instr_info *ins, bfd_vma *res) 12055 { 12056 if (!get16 (ins, res)) 12057 return false; 12058 *res = (*res ^ 0x8000) - 0x8000; 12059 return true; 12060 } 12061 12062 static bool 12063 get32 (instr_info *ins, bfd_vma *res) 12064 { 12065 if (!fetch_code (ins->info, ins->codep + 4)) 12066 return false; 12067 *res = *ins->codep++; 12068 *res |= (bfd_vma) *ins->codep++ << 8; 12069 *res |= (bfd_vma) *ins->codep++ << 16; 12070 *res |= (bfd_vma) *ins->codep++ << 24; 12071 return true; 12072 } 12073 12074 static bool 12075 get32s (instr_info *ins, bfd_vma *res) 12076 { 12077 if (!get32 (ins, res)) 12078 return false; 12079 12080 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); 12081 12082 return true; 12083 } 12084 12085 static bool 12086 get64 (instr_info *ins, uint64_t *res) 12087 { 12088 unsigned int a; 12089 unsigned int b; 12090 12091 if (!fetch_code (ins->info, ins->codep + 8)) 12092 return false; 12093 a = *ins->codep++; 12094 a |= (unsigned int) *ins->codep++ << 8; 12095 a |= (unsigned int) *ins->codep++ << 16; 12096 a |= (unsigned int) *ins->codep++ << 24; 12097 b = *ins->codep++; 12098 b |= (unsigned int) *ins->codep++ << 8; 12099 b |= (unsigned int) *ins->codep++ << 16; 12100 b |= (unsigned int) *ins->codep++ << 24; 12101 *res = a + ((uint64_t) b << 32); 12102 return true; 12103 } 12104 12105 static void 12106 set_op (instr_info *ins, bfd_vma op, bool riprel) 12107 { 12108 ins->op_index[ins->op_ad] = ins->op_ad; 12109 if (ins->address_mode == mode_64bit) 12110 ins->op_address[ins->op_ad] = op; 12111 else /* Mask to get a 32-bit address. */ 12112 ins->op_address[ins->op_ad] = op & 0xffffffff; 12113 ins->op_riprel[ins->op_ad] = riprel; 12114 } 12115 12116 static bool 12117 BadOp (instr_info *ins) 12118 { 12119 /* Throw away prefixes and 1st. opcode byte. */ 12120 struct dis_private *priv = ins->info->private_data; 12121 12122 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1; 12123 ins->obufp = stpcpy (ins->obufp, "(bad)"); 12124 return true; 12125 } 12126 12127 static bool 12128 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 12129 int sizeflag ATTRIBUTE_UNUSED) 12130 { 12131 if (ins->modrm.mod != 3) 12132 return BadOp (ins); 12133 12134 /* Skip mod/rm byte. */ 12135 MODRM_CHECK; 12136 ins->codep++; 12137 ins->has_skipped_modrm = true; 12138 return true; 12139 } 12140 12141 static bool 12142 OP_E_memory (instr_info *ins, int bytemode, int sizeflag) 12143 { 12144 int add = (ins->rex & REX_B) ? 8 : 0; 12145 int riprel = 0; 12146 int shift; 12147 12148 add += (ins->rex2 & REX_B) ? 16 : 0; 12149 12150 /* Handles EVEX other than APX EVEX-promoted instructions. */ 12151 if (ins->vex.evex && ins->evex_type == evex_default) 12152 { 12153 12154 /* Zeroing-masking is invalid for memory destinations. Set the flag 12155 uniformly, as the consumer will inspect it only for the destination 12156 operand. */ 12157 if (ins->vex.zeroing) 12158 ins->illegal_masking = true; 12159 12160 switch (bytemode) 12161 { 12162 case dw_mode: 12163 case w_mode: 12164 case w_swap_mode: 12165 shift = 1; 12166 break; 12167 case db_mode: 12168 case b_mode: 12169 shift = 0; 12170 break; 12171 case dq_mode: 12172 if (ins->address_mode != mode_64bit) 12173 { 12174 case d_mode: 12175 case d_swap_mode: 12176 shift = 2; 12177 break; 12178 } 12179 /* fall through */ 12180 case vex_vsib_d_w_dq_mode: 12181 case vex_vsib_q_w_dq_mode: 12182 case evex_x_gscat_mode: 12183 shift = ins->vex.w ? 3 : 2; 12184 break; 12185 case xh_mode: 12186 case evex_half_bcst_xmmqh_mode: 12187 case evex_half_bcst_xmmqdh_mode: 12188 if (ins->vex.b) 12189 { 12190 shift = ins->vex.w ? 2 : 1; 12191 break; 12192 } 12193 /* Fall through. */ 12194 case x_mode: 12195 case evex_half_bcst_xmmq_mode: 12196 if (ins->vex.b) 12197 { 12198 shift = ins->vex.w ? 3 : 2; 12199 break; 12200 } 12201 /* Fall through. */ 12202 case xmmqd_mode: 12203 case xmmdw_mode: 12204 case xmmq_mode: 12205 case ymmq_mode: 12206 case evex_x_nobcst_mode: 12207 case x_swap_mode: 12208 switch (ins->vex.length) 12209 { 12210 case 128: 12211 shift = 4; 12212 break; 12213 case 256: 12214 shift = 5; 12215 break; 12216 case 512: 12217 shift = 6; 12218 break; 12219 default: 12220 abort (); 12221 } 12222 /* Make necessary corrections to shift for modes that need it. */ 12223 if (bytemode == xmmq_mode 12224 || bytemode == evex_half_bcst_xmmqh_mode 12225 || bytemode == evex_half_bcst_xmmq_mode 12226 || (bytemode == ymmq_mode && ins->vex.length == 128)) 12227 shift -= 1; 12228 else if (bytemode == xmmqd_mode 12229 || bytemode == evex_half_bcst_xmmqdh_mode) 12230 shift -= 2; 12231 else if (bytemode == xmmdw_mode) 12232 shift -= 3; 12233 break; 12234 case ymm_mode: 12235 shift = 5; 12236 break; 12237 case xmm_mode: 12238 shift = 4; 12239 break; 12240 case q_mode: 12241 case q_swap_mode: 12242 shift = 3; 12243 break; 12244 case bw_unit_mode: 12245 shift = ins->vex.w ? 1 : 0; 12246 break; 12247 default: 12248 abort (); 12249 } 12250 } 12251 else 12252 shift = 0; 12253 12254 USED_REX (REX_B); 12255 if (ins->intel_syntax) 12256 intel_operand_size (ins, bytemode, sizeflag); 12257 append_seg (ins); 12258 12259 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 12260 { 12261 /* 32/64 bit address mode */ 12262 bfd_vma disp = 0; 12263 int havedisp; 12264 int havebase; 12265 int needindex; 12266 int needaddr32; 12267 int base, rbase; 12268 int vindex = 0; 12269 int scale = 0; 12270 int addr32flag = !((sizeflag & AFLAG) 12271 || bytemode == v_bnd_mode 12272 || bytemode == v_bndmk_mode 12273 || bytemode == bnd_mode 12274 || bytemode == bnd_swap_mode); 12275 bool check_gather = false; 12276 const char (*indexes)[8] = NULL; 12277 12278 havebase = 1; 12279 base = ins->modrm.rm; 12280 12281 if (base == 4) 12282 { 12283 vindex = ins->sib.index; 12284 USED_REX (REX_X); 12285 if (ins->rex & REX_X) 12286 vindex += 8; 12287 switch (bytemode) 12288 { 12289 case vex_vsib_d_w_dq_mode: 12290 case vex_vsib_q_w_dq_mode: 12291 if (!ins->need_vex) 12292 abort (); 12293 if (ins->vex.evex) 12294 { 12295 /* S/G EVEX insns require EVEX.X4 not to be set. */ 12296 if (ins->rex2 & REX_X) 12297 { 12298 oappend (ins, "(bad)"); 12299 return true; 12300 } 12301 12302 if (!ins->vex.v) 12303 vindex += 16; 12304 check_gather = ins->obufp == ins->op_out[1]; 12305 } 12306 12307 switch (ins->vex.length) 12308 { 12309 case 128: 12310 indexes = att_names_xmm; 12311 break; 12312 case 256: 12313 if (!ins->vex.w 12314 || bytemode == vex_vsib_q_w_dq_mode) 12315 indexes = att_names_ymm; 12316 else 12317 indexes = att_names_xmm; 12318 break; 12319 case 512: 12320 if (!ins->vex.w 12321 || bytemode == vex_vsib_q_w_dq_mode) 12322 indexes = att_names_zmm; 12323 else 12324 indexes = att_names_ymm; 12325 break; 12326 default: 12327 abort (); 12328 } 12329 break; 12330 default: 12331 if (ins->rex2 & REX_X) 12332 vindex += 16; 12333 12334 if (vindex != 4) 12335 indexes = ins->address_mode == mode_64bit && !addr32flag 12336 ? att_names64 : att_names32; 12337 break; 12338 } 12339 scale = ins->sib.scale; 12340 base = ins->sib.base; 12341 ins->codep++; 12342 } 12343 else 12344 { 12345 /* Check for mandatory SIB. */ 12346 if (bytemode == vex_vsib_d_w_dq_mode 12347 || bytemode == vex_vsib_q_w_dq_mode 12348 || bytemode == vex_sibmem_mode) 12349 { 12350 oappend (ins, "(bad)"); 12351 return true; 12352 } 12353 } 12354 rbase = base + add; 12355 12356 switch (ins->modrm.mod) 12357 { 12358 case 0: 12359 if (base == 5) 12360 { 12361 havebase = 0; 12362 if (ins->address_mode == mode_64bit && !ins->has_sib) 12363 riprel = 1; 12364 if (!get32s (ins, &disp)) 12365 return false; 12366 if (riprel && bytemode == v_bndmk_mode) 12367 { 12368 oappend (ins, "(bad)"); 12369 return true; 12370 } 12371 } 12372 break; 12373 case 1: 12374 if (!get8s (ins, &disp)) 12375 return false; 12376 if (ins->vex.evex && shift > 0) 12377 disp <<= shift; 12378 break; 12379 case 2: 12380 if (!get32s (ins, &disp)) 12381 return false; 12382 break; 12383 } 12384 12385 needindex = 0; 12386 needaddr32 = 0; 12387 if (ins->has_sib 12388 && !havebase 12389 && !indexes 12390 && ins->address_mode != mode_16bit) 12391 { 12392 if (ins->address_mode == mode_64bit) 12393 { 12394 if (addr32flag) 12395 { 12396 /* Without base nor index registers, zero-extend the 12397 lower 32-bit displacement to 64 bits. */ 12398 disp &= 0xffffffff; 12399 needindex = 1; 12400 } 12401 needaddr32 = 1; 12402 } 12403 else 12404 { 12405 /* In 32-bit mode, we need index register to tell [offset] 12406 from [eiz*1 + offset]. */ 12407 needindex = 1; 12408 } 12409 } 12410 12411 havedisp = (havebase 12412 || needindex 12413 || (ins->has_sib && (indexes || scale != 0))); 12414 12415 if (!ins->intel_syntax) 12416 if (ins->modrm.mod != 0 || base == 5) 12417 { 12418 if (havedisp || riprel) 12419 print_displacement (ins, disp); 12420 else 12421 print_operand_value (ins, disp, dis_style_address_offset); 12422 if (riprel) 12423 { 12424 set_op (ins, disp, true); 12425 oappend_char (ins, '('); 12426 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip", 12427 dis_style_register); 12428 oappend_char (ins, ')'); 12429 } 12430 } 12431 12432 if ((havebase || indexes || needindex || needaddr32 || riprel) 12433 && (ins->address_mode != mode_64bit 12434 || ((bytemode != v_bnd_mode) 12435 && (bytemode != v_bndmk_mode) 12436 && (bytemode != bnd_mode) 12437 && (bytemode != bnd_swap_mode)))) 12438 ins->used_prefixes |= PREFIX_ADDR; 12439 12440 if (havedisp || (ins->intel_syntax && riprel)) 12441 { 12442 oappend_char (ins, ins->open_char); 12443 if (ins->intel_syntax && riprel) 12444 { 12445 set_op (ins, disp, true); 12446 oappend_with_style (ins, !addr32flag ? "rip" : "eip", 12447 dis_style_register); 12448 } 12449 if (havebase) 12450 oappend_register 12451 (ins, 12452 (ins->address_mode == mode_64bit && !addr32flag 12453 ? att_names64 : att_names32)[rbase]); 12454 if (ins->has_sib) 12455 { 12456 /* ESP/RSP won't allow index. If base isn't ESP/RSP, 12457 print index to tell base + index from base. */ 12458 if (scale != 0 12459 || needindex 12460 || indexes 12461 || (havebase && base != ESP_REG_NUM)) 12462 { 12463 if (!ins->intel_syntax || havebase) 12464 oappend_char (ins, ins->separator_char); 12465 if (indexes) 12466 { 12467 if (ins->address_mode == mode_64bit || vindex < 16) 12468 oappend_register (ins, indexes[vindex]); 12469 else 12470 oappend (ins, "(bad)"); 12471 } 12472 else 12473 oappend_register (ins, 12474 ins->address_mode == mode_64bit 12475 && !addr32flag 12476 ? att_index64 12477 : att_index32); 12478 12479 oappend_char (ins, ins->scale_char); 12480 oappend_char_with_style (ins, '0' + (1 << scale), 12481 dis_style_immediate); 12482 } 12483 } 12484 if (ins->intel_syntax 12485 && (disp || ins->modrm.mod != 0 || base == 5)) 12486 { 12487 if (!havedisp || (bfd_signed_vma) disp >= 0) 12488 oappend_char (ins, '+'); 12489 if (havedisp) 12490 print_displacement (ins, disp); 12491 else 12492 print_operand_value (ins, disp, dis_style_address_offset); 12493 } 12494 12495 oappend_char (ins, ins->close_char); 12496 12497 if (check_gather) 12498 { 12499 /* Both XMM/YMM/ZMM registers must be distinct. */ 12500 int modrm_reg = ins->modrm.reg; 12501 12502 if (ins->rex & REX_R) 12503 modrm_reg += 8; 12504 if (ins->rex2 & REX_R) 12505 modrm_reg += 16; 12506 if (vindex == modrm_reg) 12507 oappend (ins, "/(bad)"); 12508 } 12509 } 12510 else if (ins->intel_syntax) 12511 { 12512 if (ins->modrm.mod != 0 || base == 5) 12513 { 12514 if (!ins->active_seg_prefix) 12515 { 12516 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12517 oappend (ins, ":"); 12518 } 12519 print_operand_value (ins, disp, dis_style_text); 12520 } 12521 } 12522 } 12523 else if (bytemode == v_bnd_mode 12524 || bytemode == v_bndmk_mode 12525 || bytemode == bnd_mode 12526 || bytemode == bnd_swap_mode 12527 || bytemode == vex_vsib_d_w_dq_mode 12528 || bytemode == vex_vsib_q_w_dq_mode) 12529 { 12530 oappend (ins, "(bad)"); 12531 return true; 12532 } 12533 else 12534 { 12535 /* 16 bit address mode */ 12536 bfd_vma disp = 0; 12537 12538 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR; 12539 switch (ins->modrm.mod) 12540 { 12541 case 0: 12542 if (ins->modrm.rm == 6) 12543 { 12544 case 2: 12545 if (!get16s (ins, &disp)) 12546 return false; 12547 } 12548 break; 12549 case 1: 12550 if (!get8s (ins, &disp)) 12551 return false; 12552 if (ins->vex.evex && shift > 0) 12553 disp <<= shift; 12554 break; 12555 } 12556 12557 if (!ins->intel_syntax) 12558 if (ins->modrm.mod != 0 || ins->modrm.rm == 6) 12559 print_displacement (ins, disp); 12560 12561 if (ins->modrm.mod != 0 || ins->modrm.rm != 6) 12562 { 12563 oappend_char (ins, ins->open_char); 12564 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm] 12565 : att_index16[ins->modrm.rm]); 12566 if (ins->intel_syntax 12567 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6)) 12568 { 12569 if ((bfd_signed_vma) disp >= 0) 12570 oappend_char (ins, '+'); 12571 print_displacement (ins, disp); 12572 } 12573 12574 oappend_char (ins, ins->close_char); 12575 } 12576 else if (ins->intel_syntax) 12577 { 12578 if (!ins->active_seg_prefix) 12579 { 12580 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 12581 oappend (ins, ":"); 12582 } 12583 print_operand_value (ins, disp & 0xffff, dis_style_text); 12584 } 12585 } 12586 if (ins->vex.b && ins->evex_type == evex_default) 12587 { 12588 ins->evex_used |= EVEX_b_used; 12589 12590 /* Broadcast can only ever be valid for memory sources. */ 12591 if (ins->obufp == ins->op_out[0]) 12592 ins->vex.no_broadcast = true; 12593 12594 if (!ins->vex.no_broadcast 12595 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used))) 12596 { 12597 if (bytemode == xh_mode) 12598 { 12599 switch (ins->vex.length) 12600 { 12601 case 128: 12602 oappend (ins, "{1to8}"); 12603 break; 12604 case 256: 12605 oappend (ins, "{1to16}"); 12606 break; 12607 case 512: 12608 oappend (ins, "{1to32}"); 12609 break; 12610 default: 12611 abort (); 12612 } 12613 } 12614 else if (bytemode == q_mode 12615 || bytemode == ymmq_mode) 12616 ins->vex.no_broadcast = true; 12617 else if (ins->vex.w 12618 || bytemode == evex_half_bcst_xmmqdh_mode 12619 || bytemode == evex_half_bcst_xmmq_mode) 12620 { 12621 switch (ins->vex.length) 12622 { 12623 case 128: 12624 oappend (ins, "{1to2}"); 12625 break; 12626 case 256: 12627 oappend (ins, "{1to4}"); 12628 break; 12629 case 512: 12630 oappend (ins, "{1to8}"); 12631 break; 12632 default: 12633 abort (); 12634 } 12635 } 12636 else if (bytemode == x_mode 12637 || bytemode == evex_half_bcst_xmmqh_mode) 12638 { 12639 switch (ins->vex.length) 12640 { 12641 case 128: 12642 oappend (ins, "{1to4}"); 12643 break; 12644 case 256: 12645 oappend (ins, "{1to8}"); 12646 break; 12647 case 512: 12648 oappend (ins, "{1to16}"); 12649 break; 12650 default: 12651 abort (); 12652 } 12653 } 12654 else 12655 ins->vex.no_broadcast = true; 12656 } 12657 if (ins->vex.no_broadcast) 12658 oappend (ins, "{bad}"); 12659 } 12660 12661 return true; 12662 } 12663 12664 static bool 12665 OP_E (instr_info *ins, int bytemode, int sizeflag) 12666 { 12667 /* Skip mod/rm byte. */ 12668 MODRM_CHECK; 12669 if (!ins->has_skipped_modrm) 12670 { 12671 ins->codep++; 12672 ins->has_skipped_modrm = true; 12673 } 12674 12675 if (ins->modrm.mod == 3) 12676 { 12677 if ((sizeflag & SUFFIX_ALWAYS) 12678 && (bytemode == b_swap_mode 12679 || bytemode == bnd_swap_mode 12680 || bytemode == v_swap_mode)) 12681 swap_operand (ins); 12682 12683 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag); 12684 return true; 12685 } 12686 12687 /* Masking is invalid for insns with GPR-like memory destination. Set the 12688 flag uniformly, as the consumer will inspect it only for the destination 12689 operand. */ 12690 if (ins->vex.mask_register_specifier) 12691 ins->illegal_masking = true; 12692 12693 return OP_E_memory (ins, bytemode, sizeflag); 12694 } 12695 12696 static bool 12697 OP_indirE (instr_info *ins, int bytemode, int sizeflag) 12698 { 12699 if (ins->modrm.mod == 3 && bytemode == f_mode) 12700 /* bad lcall/ljmp */ 12701 return BadOp (ins); 12702 if (!ins->intel_syntax) 12703 oappend (ins, "*"); 12704 return OP_E (ins, bytemode, sizeflag); 12705 } 12706 12707 static bool 12708 OP_G (instr_info *ins, int bytemode, int sizeflag) 12709 { 12710 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); 12711 return true; 12712 } 12713 12714 static bool 12715 OP_REG (instr_info *ins, int code, int sizeflag) 12716 { 12717 const char *s; 12718 int add = 0; 12719 12720 switch (code) 12721 { 12722 case es_reg: case ss_reg: case cs_reg: 12723 case ds_reg: case fs_reg: case gs_reg: 12724 oappend_register (ins, att_names_seg[code - es_reg]); 12725 return true; 12726 } 12727 12728 USED_REX (REX_B); 12729 if (ins->rex & REX_B) 12730 add = 8; 12731 if (ins->rex2 & REX_B) 12732 add += 16; 12733 12734 switch (code) 12735 { 12736 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 12737 case sp_reg: case bp_reg: case si_reg: case di_reg: 12738 s = att_names16[code - ax_reg + add]; 12739 break; 12740 case ah_reg: case ch_reg: case dh_reg: case bh_reg: 12741 USED_REX (0); 12742 /* Fall through. */ 12743 case al_reg: case cl_reg: case dl_reg: case bl_reg: 12744 if (ins->rex) 12745 s = att_names8rex[code - al_reg + add]; 12746 else 12747 s = att_names8[code - al_reg]; 12748 break; 12749 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: 12750 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: 12751 if (ins->address_mode == mode_64bit 12752 && ((sizeflag & DFLAG) || (ins->rex & REX_W))) 12753 { 12754 s = att_names64[code - rAX_reg + add]; 12755 break; 12756 } 12757 code += eAX_reg - rAX_reg; 12758 /* Fall through. */ 12759 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 12760 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 12761 USED_REX (REX_W); 12762 if (ins->rex & REX_W) 12763 s = att_names64[code - eAX_reg + add]; 12764 else 12765 { 12766 if (sizeflag & DFLAG) 12767 s = att_names32[code - eAX_reg + add]; 12768 else 12769 s = att_names16[code - eAX_reg + add]; 12770 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12771 } 12772 break; 12773 default: 12774 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12775 return true; 12776 } 12777 oappend_register (ins, s); 12778 return true; 12779 } 12780 12781 static bool 12782 OP_IMREG (instr_info *ins, int code, int sizeflag) 12783 { 12784 const char *s; 12785 12786 switch (code) 12787 { 12788 case indir_dx_reg: 12789 if (!ins->intel_syntax) 12790 { 12791 oappend (ins, "(%dx)"); 12792 return true; 12793 } 12794 s = att_names16[dx_reg - ax_reg]; 12795 break; 12796 case al_reg: case cl_reg: 12797 s = att_names8[code - al_reg]; 12798 break; 12799 case eAX_reg: 12800 USED_REX (REX_W); 12801 if (ins->rex & REX_W) 12802 { 12803 s = *att_names64; 12804 break; 12805 } 12806 /* Fall through. */ 12807 case z_mode_ax_reg: 12808 if ((ins->rex & REX_W) || (sizeflag & DFLAG)) 12809 s = *att_names32; 12810 else 12811 s = *att_names16; 12812 if (!(ins->rex & REX_W)) 12813 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12814 break; 12815 default: 12816 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12817 return true; 12818 } 12819 oappend_register (ins, s); 12820 return true; 12821 } 12822 12823 static bool 12824 OP_I (instr_info *ins, int bytemode, int sizeflag) 12825 { 12826 bfd_vma op; 12827 12828 switch (bytemode) 12829 { 12830 case b_mode: 12831 if (!fetch_code (ins->info, ins->codep + 1)) 12832 return false; 12833 op = *ins->codep++; 12834 break; 12835 case v_mode: 12836 USED_REX (REX_W); 12837 if (ins->rex & REX_W) 12838 { 12839 if (!get32s (ins, &op)) 12840 return false; 12841 } 12842 else 12843 { 12844 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12845 if (sizeflag & DFLAG) 12846 { 12847 case d_mode: 12848 if (!get32 (ins, &op)) 12849 return false; 12850 } 12851 else 12852 { 12853 /* Fall through. */ 12854 case w_mode: 12855 if (!get16 (ins, &op)) 12856 return false; 12857 } 12858 } 12859 break; 12860 case const_1_mode: 12861 if (ins->intel_syntax) 12862 oappend_with_style (ins, "1", dis_style_immediate); 12863 else 12864 oappend_with_style (ins, "$1", dis_style_immediate); 12865 return true; 12866 default: 12867 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12868 return true; 12869 } 12870 12871 oappend_immediate (ins, op); 12872 return true; 12873 } 12874 12875 static bool 12876 OP_I64 (instr_info *ins, int bytemode, int sizeflag) 12877 { 12878 uint64_t op; 12879 12880 if (bytemode != v_mode || ins->address_mode != mode_64bit 12881 || !(ins->rex & REX_W)) 12882 return OP_I (ins, bytemode, sizeflag); 12883 12884 USED_REX (REX_W); 12885 12886 if (!get64 (ins, &op)) 12887 return false; 12888 12889 oappend_immediate (ins, op); 12890 return true; 12891 } 12892 12893 static bool 12894 OP_sI (instr_info *ins, int bytemode, int sizeflag) 12895 { 12896 bfd_vma op; 12897 12898 switch (bytemode) 12899 { 12900 case b_mode: 12901 case b_T_mode: 12902 if (!get8s (ins, &op)) 12903 return false; 12904 if (bytemode == b_T_mode) 12905 { 12906 if (ins->address_mode != mode_64bit 12907 || !((sizeflag & DFLAG) || (ins->rex & REX_W))) 12908 { 12909 /* The operand-size prefix is overridden by a REX prefix. */ 12910 if ((sizeflag & DFLAG) || (ins->rex & REX_W)) 12911 op &= 0xffffffff; 12912 else 12913 op &= 0xffff; 12914 } 12915 } 12916 else 12917 { 12918 if (!(ins->rex & REX_W)) 12919 { 12920 if (sizeflag & DFLAG) 12921 op &= 0xffffffff; 12922 else 12923 op &= 0xffff; 12924 } 12925 } 12926 break; 12927 case v_mode: 12928 /* The operand-size prefix is overridden by a REX prefix. */ 12929 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W)) 12930 { 12931 if (!get16 (ins, &op)) 12932 return false; 12933 } 12934 else if (!get32s (ins, &op)) 12935 return false; 12936 break; 12937 default: 12938 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12939 return true; 12940 } 12941 12942 oappend_immediate (ins, op); 12943 return true; 12944 } 12945 12946 static bool 12947 OP_J (instr_info *ins, int bytemode, int sizeflag) 12948 { 12949 bfd_vma disp; 12950 bfd_vma mask = -1; 12951 bfd_vma segment = 0; 12952 12953 switch (bytemode) 12954 { 12955 case b_mode: 12956 if (!get8s (ins, &disp)) 12957 return false; 12958 break; 12959 case v_mode: 12960 case dqw_mode: 12961 if ((sizeflag & DFLAG) 12962 || (ins->address_mode == mode_64bit 12963 && ((ins->isa64 == intel64 && bytemode != dqw_mode) 12964 || (ins->rex & REX_W)))) 12965 { 12966 if (!get32s (ins, &disp)) 12967 return false; 12968 } 12969 else 12970 { 12971 if (!get16s (ins, &disp)) 12972 return false; 12973 /* In 16bit mode, address is wrapped around at 64k within 12974 the same segment. Otherwise, a data16 prefix on a jump 12975 instruction means that the pc is masked to 16 bits after 12976 the displacement is added! */ 12977 mask = 0xffff; 12978 if ((ins->prefixes & PREFIX_DATA) == 0) 12979 segment = ((ins->start_pc + (ins->codep - ins->start_codep)) 12980 & ~((bfd_vma) 0xffff)); 12981 } 12982 if (ins->address_mode != mode_64bit 12983 || (ins->isa64 != intel64 && !(ins->rex & REX_W))) 12984 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 12985 break; 12986 default: 12987 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 12988 return true; 12989 } 12990 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask) 12991 | segment; 12992 set_op (ins, disp, false); 12993 print_operand_value (ins, disp, dis_style_text); 12994 return true; 12995 } 12996 12997 static bool 12998 OP_SEG (instr_info *ins, int bytemode, int sizeflag) 12999 { 13000 if (bytemode == w_mode) 13001 { 13002 oappend_register (ins, att_names_seg[ins->modrm.reg]); 13003 return true; 13004 } 13005 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag); 13006 } 13007 13008 static bool 13009 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag) 13010 { 13011 bfd_vma seg, offset; 13012 int res; 13013 char scratch[24]; 13014 13015 if (sizeflag & DFLAG) 13016 { 13017 if (!get32 (ins, &offset)) 13018 return false;; 13019 } 13020 else if (!get16 (ins, &offset)) 13021 return false; 13022 if (!get16 (ins, &seg)) 13023 return false;; 13024 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13025 13026 res = snprintf (scratch, ARRAY_SIZE (scratch), 13027 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x", 13028 (unsigned) seg, (unsigned) offset); 13029 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 13030 abort (); 13031 oappend (ins, scratch); 13032 return true; 13033 } 13034 13035 static bool 13036 OP_OFF (instr_info *ins, int bytemode, int sizeflag) 13037 { 13038 bfd_vma off; 13039 13040 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 13041 intel_operand_size (ins, bytemode, sizeflag); 13042 append_seg (ins); 13043 13044 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) 13045 { 13046 if (!get32 (ins, &off)) 13047 return false; 13048 } 13049 else 13050 { 13051 if (!get16 (ins, &off)) 13052 return false; 13053 } 13054 13055 if (ins->intel_syntax) 13056 { 13057 if (!ins->active_seg_prefix) 13058 { 13059 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 13060 oappend (ins, ":"); 13061 } 13062 } 13063 print_operand_value (ins, off, dis_style_address_offset); 13064 return true; 13065 } 13066 13067 static bool 13068 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag) 13069 { 13070 uint64_t off; 13071 13072 if (ins->address_mode != mode_64bit 13073 || (ins->prefixes & PREFIX_ADDR)) 13074 return OP_OFF (ins, bytemode, sizeflag); 13075 13076 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 13077 intel_operand_size (ins, bytemode, sizeflag); 13078 append_seg (ins); 13079 13080 if (!get64 (ins, &off)) 13081 return false; 13082 13083 if (ins->intel_syntax) 13084 { 13085 if (!ins->active_seg_prefix) 13086 { 13087 oappend_register (ins, att_names_seg[ds_reg - es_reg]); 13088 oappend (ins, ":"); 13089 } 13090 } 13091 print_operand_value (ins, off, dis_style_address_offset); 13092 return true; 13093 } 13094 13095 static void 13096 ptr_reg (instr_info *ins, int code, int sizeflag) 13097 { 13098 const char *s; 13099 13100 *ins->obufp++ = ins->open_char; 13101 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); 13102 if (ins->address_mode == mode_64bit) 13103 { 13104 if (!(sizeflag & AFLAG)) 13105 s = att_names32[code - eAX_reg]; 13106 else 13107 s = att_names64[code - eAX_reg]; 13108 } 13109 else if (sizeflag & AFLAG) 13110 s = att_names32[code - eAX_reg]; 13111 else 13112 s = att_names16[code - eAX_reg]; 13113 oappend_register (ins, s); 13114 oappend_char (ins, ins->close_char); 13115 } 13116 13117 static bool 13118 OP_ESreg (instr_info *ins, int code, int sizeflag) 13119 { 13120 if (ins->intel_syntax) 13121 { 13122 switch (ins->codep[-1]) 13123 { 13124 case 0x6d: /* insw/insl */ 13125 intel_operand_size (ins, z_mode, sizeflag); 13126 break; 13127 case 0xa5: /* movsw/movsl/movsq */ 13128 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 13129 case 0xab: /* stosw/stosl */ 13130 case 0xaf: /* scasw/scasl */ 13131 intel_operand_size (ins, v_mode, sizeflag); 13132 break; 13133 default: 13134 intel_operand_size (ins, b_mode, sizeflag); 13135 } 13136 } 13137 if (ins->address_mode != mode_64bit) 13138 { 13139 oappend_register (ins, att_names_seg[0]); 13140 oappend_char (ins, ':'); 13141 } 13142 ptr_reg (ins, code, sizeflag); 13143 return true; 13144 } 13145 13146 static bool 13147 OP_DSreg (instr_info *ins, int code, int sizeflag) 13148 { 13149 if (ins->intel_syntax) 13150 { 13151 switch (ins->codep[-1]) 13152 { 13153 case 0x01: /* rmpupdate/rmpread */ 13154 break; 13155 case 0x6f: /* outsw/outsl */ 13156 intel_operand_size (ins, z_mode, sizeflag); 13157 break; 13158 case 0xa5: /* movsw/movsl/movsq */ 13159 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 13160 case 0xad: /* lodsw/lodsl/lodsq */ 13161 intel_operand_size (ins, v_mode, sizeflag); 13162 break; 13163 default: 13164 intel_operand_size (ins, b_mode, sizeflag); 13165 } 13166 } 13167 /* Outside of 64-bit mode set ins->active_seg_prefix to PREFIX_DS if it 13168 is unset, so that the default segment register DS is printed. */ 13169 if (ins->address_mode != mode_64bit && !ins->active_seg_prefix) 13170 ins->active_seg_prefix = PREFIX_DS; 13171 append_seg (ins); 13172 ptr_reg (ins, code, sizeflag); 13173 return true; 13174 } 13175 13176 static bool 13177 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 13178 int sizeflag ATTRIBUTE_UNUSED) 13179 { 13180 int add, res; 13181 char scratch[8]; 13182 13183 if (ins->rex & REX_R) 13184 { 13185 USED_REX (REX_R); 13186 add = 8; 13187 } 13188 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK)) 13189 { 13190 ins->all_prefixes[ins->last_lock_prefix] = 0; 13191 ins->used_prefixes |= PREFIX_LOCK; 13192 add = 8; 13193 } 13194 else 13195 add = 0; 13196 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d", 13197 ins->modrm.reg + add); 13198 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 13199 abort (); 13200 oappend_register (ins, scratch); 13201 return true; 13202 } 13203 13204 static bool 13205 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 13206 int sizeflag ATTRIBUTE_UNUSED) 13207 { 13208 int add, res; 13209 char scratch[8]; 13210 13211 USED_REX (REX_R); 13212 if (ins->rex & REX_R) 13213 add = 8; 13214 else 13215 add = 0; 13216 res = snprintf (scratch, ARRAY_SIZE (scratch), 13217 ins->intel_syntax ? "dr%d" : "%%db%d", 13218 ins->modrm.reg + add); 13219 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 13220 abort (); 13221 oappend (ins, scratch); 13222 return true; 13223 } 13224 13225 static bool 13226 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED, 13227 int sizeflag ATTRIBUTE_UNUSED) 13228 { 13229 int res; 13230 char scratch[8]; 13231 13232 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg); 13233 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) 13234 abort (); 13235 oappend_register (ins, scratch); 13236 return true; 13237 } 13238 13239 static bool 13240 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13241 int sizeflag ATTRIBUTE_UNUSED) 13242 { 13243 int reg = ins->modrm.reg; 13244 const char (*names)[8]; 13245 13246 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13247 if (ins->prefixes & PREFIX_DATA) 13248 { 13249 names = att_names_xmm; 13250 USED_REX (REX_R); 13251 if (ins->rex & REX_R) 13252 reg += 8; 13253 } 13254 else 13255 names = att_names_mm; 13256 oappend_register (ins, names[reg]); 13257 return true; 13258 } 13259 13260 static void 13261 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode) 13262 { 13263 const char (*names)[8]; 13264 13265 if (bytemode == xmmq_mode 13266 || bytemode == evex_half_bcst_xmmqh_mode 13267 || bytemode == evex_half_bcst_xmmq_mode) 13268 { 13269 switch (ins->vex.length) 13270 { 13271 case 0: 13272 case 128: 13273 case 256: 13274 names = att_names_xmm; 13275 break; 13276 case 512: 13277 names = att_names_ymm; 13278 ins->evex_used |= EVEX_len_used; 13279 break; 13280 default: 13281 abort (); 13282 } 13283 } 13284 else if (bytemode == ymm_mode) 13285 names = att_names_ymm; 13286 else if (bytemode == tmm_mode) 13287 { 13288 if (reg >= 8) 13289 { 13290 oappend (ins, "(bad)"); 13291 return; 13292 } 13293 names = att_names_tmm; 13294 } 13295 else if (ins->need_vex 13296 && bytemode != xmm_mode 13297 && bytemode != scalar_mode 13298 && bytemode != xmmdw_mode 13299 && bytemode != xmmqd_mode 13300 && bytemode != evex_half_bcst_xmmqdh_mode 13301 && bytemode != w_swap_mode 13302 && bytemode != b_mode 13303 && bytemode != w_mode 13304 && bytemode != d_mode 13305 && bytemode != q_mode) 13306 { 13307 ins->evex_used |= EVEX_len_used; 13308 switch (ins->vex.length) 13309 { 13310 case 128: 13311 names = att_names_xmm; 13312 break; 13313 case 256: 13314 if (ins->vex.w 13315 || bytemode != vex_vsib_q_w_dq_mode) 13316 names = att_names_ymm; 13317 else 13318 names = att_names_xmm; 13319 break; 13320 case 512: 13321 if (ins->vex.w 13322 || bytemode != vex_vsib_q_w_dq_mode) 13323 names = att_names_zmm; 13324 else 13325 names = att_names_ymm; 13326 break; 13327 default: 13328 abort (); 13329 } 13330 } 13331 else 13332 names = att_names_xmm; 13333 oappend_register (ins, names[reg]); 13334 } 13335 13336 static bool 13337 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13338 { 13339 unsigned int reg = ins->modrm.reg; 13340 13341 USED_REX (REX_R); 13342 if (ins->rex & REX_R) 13343 reg += 8; 13344 if (ins->vex.evex) 13345 { 13346 if (ins->rex2 & REX_R) 13347 reg += 16; 13348 } 13349 13350 if (bytemode == tmm_mode) 13351 ins->modrm.reg = reg; 13352 else if (bytemode == scalar_mode) 13353 ins->vex.no_broadcast = true; 13354 13355 print_vector_reg (ins, reg, bytemode); 13356 return true; 13357 } 13358 13359 static bool 13360 OP_EM (instr_info *ins, int bytemode, int sizeflag) 13361 { 13362 int reg; 13363 const char (*names)[8]; 13364 13365 if (ins->modrm.mod != 3) 13366 { 13367 if (ins->intel_syntax 13368 && (bytemode == v_mode || bytemode == v_swap_mode)) 13369 { 13370 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; 13371 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13372 } 13373 return OP_E (ins, bytemode, sizeflag); 13374 } 13375 13376 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) 13377 swap_operand (ins); 13378 13379 /* Skip mod/rm byte. */ 13380 MODRM_CHECK; 13381 ins->codep++; 13382 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13383 reg = ins->modrm.rm; 13384 if (ins->prefixes & PREFIX_DATA) 13385 { 13386 names = att_names_xmm; 13387 USED_REX (REX_B); 13388 if (ins->rex & REX_B) 13389 reg += 8; 13390 } 13391 else 13392 names = att_names_mm; 13393 oappend_register (ins, names[reg]); 13394 return true; 13395 } 13396 13397 /* cvt* are the only instructions in sse2 which have 13398 both SSE and MMX operands and also have 0x66 prefix 13399 in their opcode. 0x66 was originally used to differentiate 13400 between SSE and MMX instruction(operands). So we have to handle the 13401 cvt* separately using OP_EMC and OP_MXC */ 13402 static bool 13403 OP_EMC (instr_info *ins, int bytemode, int sizeflag) 13404 { 13405 if (ins->modrm.mod != 3) 13406 { 13407 if (ins->intel_syntax && bytemode == v_mode) 13408 { 13409 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; 13410 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13411 } 13412 return OP_E (ins, bytemode, sizeflag); 13413 } 13414 13415 /* Skip mod/rm byte. */ 13416 MODRM_CHECK; 13417 ins->codep++; 13418 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13419 oappend_register (ins, att_names_mm[ins->modrm.rm]); 13420 return true; 13421 } 13422 13423 static bool 13424 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13425 int sizeflag ATTRIBUTE_UNUSED) 13426 { 13427 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 13428 oappend_register (ins, att_names_mm[ins->modrm.reg]); 13429 return true; 13430 } 13431 13432 static bool 13433 OP_EX (instr_info *ins, int bytemode, int sizeflag) 13434 { 13435 int reg; 13436 13437 /* Skip mod/rm byte. */ 13438 MODRM_CHECK; 13439 ins->codep++; 13440 13441 if (bytemode == dq_mode) 13442 bytemode = ins->vex.w ? q_mode : d_mode; 13443 13444 if (ins->modrm.mod != 3) 13445 return OP_E_memory (ins, bytemode, sizeflag); 13446 13447 reg = ins->modrm.rm; 13448 USED_REX (REX_B); 13449 if (ins->rex & REX_B) 13450 reg += 8; 13451 if (ins->vex.evex) 13452 { 13453 USED_REX (REX_X); 13454 if ((ins->rex & REX_X)) 13455 reg += 16; 13456 ins->rex2_used &= ~REX_B; 13457 } 13458 else if (ins->rex2 & REX_B) 13459 reg += 16; 13460 13461 if ((sizeflag & SUFFIX_ALWAYS) 13462 && (bytemode == x_swap_mode 13463 || bytemode == w_swap_mode 13464 || bytemode == d_swap_mode 13465 || bytemode == q_swap_mode)) 13466 swap_operand (ins); 13467 13468 if (bytemode == tmm_mode) 13469 ins->modrm.rm = reg; 13470 13471 print_vector_reg (ins, reg, bytemode); 13472 return true; 13473 } 13474 13475 static bool 13476 OP_R (instr_info *ins, int bytemode, int sizeflag) 13477 { 13478 if (ins->modrm.mod != 3) 13479 return BadOp (ins); 13480 13481 switch (bytemode) 13482 { 13483 case d_mode: 13484 case dq_mode: 13485 case q_mode: 13486 case mask_mode: 13487 return OP_E (ins, bytemode, sizeflag); 13488 case q_mm_mode: 13489 return OP_EM (ins, x_mode, sizeflag); 13490 case xmm_mode: 13491 if (ins->vex.length <= 128) 13492 break; 13493 return BadOp (ins); 13494 } 13495 13496 return OP_EX (ins, bytemode, sizeflag); 13497 } 13498 13499 static bool 13500 OP_M (instr_info *ins, int bytemode, int sizeflag) 13501 { 13502 /* Skip mod/rm byte. */ 13503 MODRM_CHECK; 13504 ins->codep++; 13505 13506 if (ins->modrm.mod == 3) 13507 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ 13508 return BadOp (ins); 13509 13510 if (bytemode == x_mode) 13511 ins->vex.no_broadcast = true; 13512 13513 return OP_E_memory (ins, bytemode, sizeflag); 13514 } 13515 13516 static bool 13517 OP_0f07 (instr_info *ins, int bytemode, int sizeflag) 13518 { 13519 if (ins->modrm.mod != 3 || ins->modrm.rm != 0) 13520 return BadOp (ins); 13521 return OP_E (ins, bytemode, sizeflag); 13522 } 13523 13524 /* montmul instruction need display repz and skip modrm */ 13525 13526 static bool 13527 MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 13528 { 13529 if (ins->modrm.mod != 3 || ins->modrm.rm != 0) 13530 return BadOp (ins); 13531 13532 /* The 0xf3 prefix should be displayed as "repz" for montmul. */ 13533 if (ins->prefixes & PREFIX_REPZ) 13534 ins->all_prefixes[ins->last_repz_prefix] = 0xf3; 13535 13536 /* Skip mod/rm byte. */ 13537 MODRM_CHECK; 13538 ins->codep++; 13539 return true; 13540 } 13541 13542 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 13543 32bit mode and "xchg %rax,%rax" in 64bit mode. */ 13544 13545 static bool 13546 NOP_Fixup (instr_info *ins, int opnd, int sizeflag) 13547 { 13548 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0) 13549 { 13550 ins->mnemonicendp = stpcpy (ins->obuf, "nop"); 13551 return true; 13552 } 13553 if (opnd == 0) 13554 return OP_REG (ins, eAX_reg, sizeflag); 13555 return OP_IMREG (ins, eAX_reg, sizeflag); 13556 } 13557 13558 static const char *const Suffix3DNow[] = { 13559 /* 00 */ NULL, NULL, NULL, NULL, 13560 /* 04 */ NULL, NULL, NULL, NULL, 13561 /* 08 */ NULL, NULL, NULL, NULL, 13562 /* 0C */ "pi2fw", "pi2fd", NULL, NULL, 13563 /* 10 */ NULL, NULL, NULL, NULL, 13564 /* 14 */ NULL, NULL, NULL, NULL, 13565 /* 18 */ NULL, NULL, NULL, NULL, 13566 /* 1C */ "pf2iw", "pf2id", NULL, NULL, 13567 /* 20 */ NULL, NULL, NULL, NULL, 13568 /* 24 */ NULL, NULL, NULL, NULL, 13569 /* 28 */ NULL, NULL, NULL, NULL, 13570 /* 2C */ NULL, NULL, NULL, NULL, 13571 /* 30 */ NULL, NULL, NULL, NULL, 13572 /* 34 */ NULL, NULL, NULL, NULL, 13573 /* 38 */ NULL, NULL, NULL, NULL, 13574 /* 3C */ NULL, NULL, NULL, NULL, 13575 /* 40 */ NULL, NULL, NULL, NULL, 13576 /* 44 */ NULL, NULL, NULL, NULL, 13577 /* 48 */ NULL, NULL, NULL, NULL, 13578 /* 4C */ NULL, NULL, NULL, NULL, 13579 /* 50 */ NULL, NULL, NULL, NULL, 13580 /* 54 */ NULL, NULL, NULL, NULL, 13581 /* 58 */ NULL, NULL, NULL, NULL, 13582 /* 5C */ NULL, NULL, NULL, NULL, 13583 /* 60 */ NULL, NULL, NULL, NULL, 13584 /* 64 */ NULL, NULL, NULL, NULL, 13585 /* 68 */ NULL, NULL, NULL, NULL, 13586 /* 6C */ NULL, NULL, NULL, NULL, 13587 /* 70 */ NULL, NULL, NULL, NULL, 13588 /* 74 */ NULL, NULL, NULL, NULL, 13589 /* 78 */ NULL, NULL, NULL, NULL, 13590 /* 7C */ NULL, NULL, NULL, NULL, 13591 /* 80 */ NULL, NULL, NULL, NULL, 13592 /* 84 */ NULL, NULL, NULL, NULL, 13593 /* 88 */ NULL, NULL, "pfnacc", NULL, 13594 /* 8C */ NULL, NULL, "pfpnacc", NULL, 13595 /* 90 */ "pfcmpge", NULL, NULL, NULL, 13596 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", 13597 /* 98 */ NULL, NULL, "pfsub", NULL, 13598 /* 9C */ NULL, NULL, "pfadd", NULL, 13599 /* A0 */ "pfcmpgt", NULL, NULL, NULL, 13600 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", 13601 /* A8 */ NULL, NULL, "pfsubr", NULL, 13602 /* AC */ NULL, NULL, "pfacc", NULL, 13603 /* B0 */ "pfcmpeq", NULL, NULL, NULL, 13604 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", 13605 /* B8 */ NULL, NULL, NULL, "pswapd", 13606 /* BC */ NULL, NULL, NULL, "pavgusb", 13607 /* C0 */ NULL, NULL, NULL, NULL, 13608 /* C4 */ NULL, NULL, NULL, NULL, 13609 /* C8 */ NULL, NULL, NULL, NULL, 13610 /* CC */ NULL, NULL, NULL, NULL, 13611 /* D0 */ NULL, NULL, NULL, NULL, 13612 /* D4 */ NULL, NULL, NULL, NULL, 13613 /* D8 */ NULL, NULL, NULL, NULL, 13614 /* DC */ NULL, NULL, NULL, NULL, 13615 /* E0 */ NULL, NULL, NULL, NULL, 13616 /* E4 */ NULL, NULL, NULL, NULL, 13617 /* E8 */ NULL, NULL, NULL, NULL, 13618 /* EC */ NULL, NULL, NULL, NULL, 13619 /* F0 */ NULL, NULL, NULL, NULL, 13620 /* F4 */ NULL, NULL, NULL, NULL, 13621 /* F8 */ NULL, NULL, NULL, NULL, 13622 /* FC */ NULL, NULL, NULL, NULL, 13623 }; 13624 13625 static bool 13626 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13627 int sizeflag ATTRIBUTE_UNUSED) 13628 { 13629 const char *mnemonic; 13630 13631 if (!fetch_code (ins->info, ins->codep + 1)) 13632 return false; 13633 /* AMD 3DNow! instructions are specified by an opcode suffix in the 13634 place where an 8-bit immediate would normally go. ie. the last 13635 byte of the instruction. */ 13636 ins->obufp = ins->mnemonicendp; 13637 mnemonic = Suffix3DNow[*ins->codep++]; 13638 if (mnemonic) 13639 ins->obufp = stpcpy (ins->obufp, mnemonic); 13640 else 13641 { 13642 /* Since a variable sized ins->modrm/ins->sib chunk is between the start 13643 of the opcode (0x0f0f) and the opcode suffix, we need to do 13644 all the ins->modrm processing first, and don't know until now that 13645 we have a bad opcode. This necessitates some cleaning up. */ 13646 ins->op_out[0][0] = '\0'; 13647 ins->op_out[1][0] = '\0'; 13648 BadOp (ins); 13649 } 13650 ins->mnemonicendp = ins->obufp; 13651 return true; 13652 } 13653 13654 static const struct op simd_cmp_op[] = 13655 { 13656 { STRING_COMMA_LEN ("eq") }, 13657 { STRING_COMMA_LEN ("lt") }, 13658 { STRING_COMMA_LEN ("le") }, 13659 { STRING_COMMA_LEN ("unord") }, 13660 { STRING_COMMA_LEN ("neq") }, 13661 { STRING_COMMA_LEN ("nlt") }, 13662 { STRING_COMMA_LEN ("nle") }, 13663 { STRING_COMMA_LEN ("ord") } 13664 }; 13665 13666 static const struct op vex_cmp_op[] = 13667 { 13668 { STRING_COMMA_LEN ("eq_uq") }, 13669 { STRING_COMMA_LEN ("nge") }, 13670 { STRING_COMMA_LEN ("ngt") }, 13671 { STRING_COMMA_LEN ("false") }, 13672 { STRING_COMMA_LEN ("neq_oq") }, 13673 { STRING_COMMA_LEN ("ge") }, 13674 { STRING_COMMA_LEN ("gt") }, 13675 { STRING_COMMA_LEN ("true") }, 13676 { STRING_COMMA_LEN ("eq_os") }, 13677 { STRING_COMMA_LEN ("lt_oq") }, 13678 { STRING_COMMA_LEN ("le_oq") }, 13679 { STRING_COMMA_LEN ("unord_s") }, 13680 { STRING_COMMA_LEN ("neq_us") }, 13681 { STRING_COMMA_LEN ("nlt_uq") }, 13682 { STRING_COMMA_LEN ("nle_uq") }, 13683 { STRING_COMMA_LEN ("ord_s") }, 13684 { STRING_COMMA_LEN ("eq_us") }, 13685 { STRING_COMMA_LEN ("nge_uq") }, 13686 { STRING_COMMA_LEN ("ngt_uq") }, 13687 { STRING_COMMA_LEN ("false_os") }, 13688 { STRING_COMMA_LEN ("neq_os") }, 13689 { STRING_COMMA_LEN ("ge_oq") }, 13690 { STRING_COMMA_LEN ("gt_oq") }, 13691 { STRING_COMMA_LEN ("true_us") }, 13692 }; 13693 13694 static bool 13695 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13696 int sizeflag ATTRIBUTE_UNUSED) 13697 { 13698 unsigned int cmp_type; 13699 13700 if (!fetch_code (ins->info, ins->codep + 1)) 13701 return false; 13702 cmp_type = *ins->codep++; 13703 if (cmp_type < ARRAY_SIZE (simd_cmp_op)) 13704 { 13705 char suffix[3]; 13706 char *p = ins->mnemonicendp - 2; 13707 suffix[0] = p[0]; 13708 suffix[1] = p[1]; 13709 suffix[2] = '\0'; 13710 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 13711 ins->mnemonicendp += simd_cmp_op[cmp_type].len; 13712 } 13713 else if (ins->need_vex 13714 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) 13715 { 13716 char suffix[3]; 13717 char *p = ins->mnemonicendp - 2; 13718 suffix[0] = p[0]; 13719 suffix[1] = p[1]; 13720 suffix[2] = '\0'; 13721 cmp_type -= ARRAY_SIZE (simd_cmp_op); 13722 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); 13723 ins->mnemonicendp += vex_cmp_op[cmp_type].len; 13724 } 13725 else 13726 { 13727 /* We have a reserved extension byte. Output it directly. */ 13728 oappend_immediate (ins, cmp_type); 13729 } 13730 return true; 13731 } 13732 13733 static bool 13734 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13735 { 13736 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ 13737 if (!ins->intel_syntax) 13738 { 13739 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax); 13740 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); 13741 if (bytemode == eBX_reg) 13742 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax); 13743 ins->two_source_ops = true; 13744 } 13745 /* Skip mod/rm byte. */ 13746 MODRM_CHECK; 13747 ins->codep++; 13748 return true; 13749 } 13750 13751 static bool 13752 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13753 int sizeflag ATTRIBUTE_UNUSED) 13754 { 13755 /* monitor %{e,r,}ax,%ecx,%edx" */ 13756 if (!ins->intel_syntax) 13757 { 13758 const char (*names)[8] = (ins->address_mode == mode_64bit 13759 ? att_names64 : att_names32); 13760 13761 if (ins->prefixes & PREFIX_ADDR) 13762 { 13763 /* Remove "addr16/addr32". */ 13764 ins->all_prefixes[ins->last_addr_prefix] = 0; 13765 names = (ins->address_mode != mode_32bit 13766 ? att_names32 : att_names16); 13767 ins->used_prefixes |= PREFIX_ADDR; 13768 } 13769 else if (ins->address_mode == mode_16bit) 13770 names = att_names16; 13771 strcpy (ins->op_out[0], names[0] + ins->intel_syntax); 13772 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); 13773 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax); 13774 ins->two_source_ops = true; 13775 } 13776 /* Skip mod/rm byte. */ 13777 MODRM_CHECK; 13778 ins->codep++; 13779 return true; 13780 } 13781 13782 static bool 13783 REP_Fixup (instr_info *ins, int bytemode, int sizeflag) 13784 { 13785 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, 13786 lods and stos. */ 13787 if (ins->prefixes & PREFIX_REPZ) 13788 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX; 13789 13790 switch (bytemode) 13791 { 13792 case al_reg: 13793 case eAX_reg: 13794 case indir_dx_reg: 13795 return OP_IMREG (ins, bytemode, sizeflag); 13796 case eDI_reg: 13797 return OP_ESreg (ins, bytemode, sizeflag); 13798 case eSI_reg: 13799 return OP_DSreg (ins, bytemode, sizeflag); 13800 default: 13801 abort (); 13802 break; 13803 } 13804 return true; 13805 } 13806 13807 static bool 13808 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13809 int sizeflag ATTRIBUTE_UNUSED) 13810 { 13811 if (ins->isa64 != amd64) 13812 return true; 13813 13814 ins->obufp = ins->obuf; 13815 BadOp (ins); 13816 ins->mnemonicendp = ins->obufp; 13817 ++ins->codep; 13818 return true; 13819 } 13820 13821 /* For BND-prefixed instructions 0xF2 prefix should be displayed as 13822 "bnd". */ 13823 13824 static bool 13825 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13826 int sizeflag ATTRIBUTE_UNUSED) 13827 { 13828 if (ins->prefixes & PREFIX_REPNZ) 13829 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX; 13830 return true; 13831 } 13832 13833 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as 13834 "notrack". */ 13835 13836 static bool 13837 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 13838 int sizeflag ATTRIBUTE_UNUSED) 13839 { 13840 /* Since active_seg_prefix is not set in 64-bit mode, check whether 13841 we've seen a PREFIX_DS. */ 13842 if ((ins->prefixes & PREFIX_DS) != 0 13843 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0)) 13844 { 13845 /* NOTRACK prefix is only valid on indirect branch instructions. 13846 NB: DATA prefix is unsupported for Intel64. */ 13847 ins->active_seg_prefix = 0; 13848 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX; 13849 } 13850 return true; 13851 } 13852 13853 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as 13854 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. 13855 */ 13856 13857 static bool 13858 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag) 13859 { 13860 if (ins->modrm.mod != 3 13861 && (ins->prefixes & PREFIX_LOCK) != 0) 13862 { 13863 if (ins->prefixes & PREFIX_REPZ) 13864 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13865 if (ins->prefixes & PREFIX_REPNZ) 13866 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13867 } 13868 13869 return OP_E (ins, bytemode, sizeflag); 13870 } 13871 13872 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as 13873 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. 13874 */ 13875 13876 static bool 13877 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag) 13878 { 13879 if (ins->modrm.mod != 3) 13880 { 13881 if (ins->prefixes & PREFIX_REPZ) 13882 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13883 if (ins->prefixes & PREFIX_REPNZ) 13884 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13885 } 13886 13887 return OP_E (ins, bytemode, sizeflag); 13888 } 13889 13890 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as 13891 "xrelease" for memory operand. No check for LOCK prefix. */ 13892 13893 static bool 13894 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag) 13895 { 13896 if (ins->modrm.mod != 3 13897 && ins->last_repz_prefix > ins->last_repnz_prefix 13898 && (ins->prefixes & PREFIX_REPZ) != 0) 13899 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13900 13901 return OP_E (ins, bytemode, sizeflag); 13902 } 13903 13904 static bool 13905 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag) 13906 { 13907 USED_REX (REX_W); 13908 if (ins->rex & REX_W) 13909 { 13910 /* Change cmpxchg8b to cmpxchg16b. */ 13911 char *p = ins->mnemonicendp - 2; 13912 ins->mnemonicendp = stpcpy (p, "16b"); 13913 bytemode = o_mode; 13914 } 13915 else if ((ins->prefixes & PREFIX_LOCK) != 0) 13916 { 13917 if (ins->prefixes & PREFIX_REPZ) 13918 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; 13919 if (ins->prefixes & PREFIX_REPNZ) 13920 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; 13921 } 13922 13923 return OP_M (ins, bytemode, sizeflag); 13924 } 13925 13926 static bool 13927 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED) 13928 { 13929 const char (*names)[8] = att_names_xmm; 13930 13931 if (ins->need_vex) 13932 { 13933 switch (ins->vex.length) 13934 { 13935 case 128: 13936 break; 13937 case 256: 13938 names = att_names_ymm; 13939 break; 13940 default: 13941 abort (); 13942 } 13943 } 13944 oappend_register (ins, names[reg]); 13945 return true; 13946 } 13947 13948 static bool 13949 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag) 13950 { 13951 /* Add proper suffix to "fxsave" and "fxrstor". */ 13952 USED_REX (REX_W); 13953 if (ins->rex & REX_W) 13954 { 13955 char *p = ins->mnemonicendp; 13956 *p++ = '6'; 13957 *p++ = '4'; 13958 *p = '\0'; 13959 ins->mnemonicendp = p; 13960 } 13961 return OP_M (ins, bytemode, sizeflag); 13962 } 13963 13964 /* Display the destination register operand for instructions with 13965 VEX. */ 13966 13967 static bool 13968 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 13969 { 13970 int reg, modrm_reg, sib_index = -1; 13971 const char (*names)[8]; 13972 13973 if (!ins->need_vex) 13974 return true; 13975 13976 if (ins->evex_type == evex_from_legacy) 13977 { 13978 ins->evex_used |= EVEX_b_used; 13979 if (!ins->vex.nd) 13980 return true; 13981 } 13982 13983 reg = ins->vex.register_specifier; 13984 ins->vex.register_specifier = 0; 13985 if (ins->address_mode != mode_64bit) 13986 { 13987 if (ins->vex.evex && !ins->vex.v) 13988 { 13989 oappend (ins, "(bad)"); 13990 return true; 13991 } 13992 13993 reg &= 7; 13994 } 13995 else if (ins->vex.evex && !ins->vex.v) 13996 reg += 16; 13997 13998 switch (bytemode) 13999 { 14000 case scalar_mode: 14001 oappend_register (ins, att_names_xmm[reg]); 14002 return true; 14003 14004 case vex_vsib_d_w_dq_mode: 14005 case vex_vsib_q_w_dq_mode: 14006 /* This must be the 3rd operand. */ 14007 if (ins->obufp != ins->op_out[2]) 14008 abort (); 14009 if (ins->vex.length == 128 14010 || (bytemode != vex_vsib_d_w_dq_mode 14011 && !ins->vex.w)) 14012 oappend_register (ins, att_names_xmm[reg]); 14013 else 14014 oappend_register (ins, att_names_ymm[reg]); 14015 14016 /* All 3 XMM/YMM registers must be distinct. */ 14017 modrm_reg = ins->modrm.reg; 14018 if (ins->rex & REX_R) 14019 modrm_reg += 8; 14020 14021 if (ins->has_sib && ins->modrm.rm == 4) 14022 { 14023 sib_index = ins->sib.index; 14024 if (ins->rex & REX_X) 14025 sib_index += 8; 14026 } 14027 14028 if (reg == modrm_reg || reg == sib_index) 14029 strcpy (ins->obufp, "/(bad)"); 14030 if (modrm_reg == sib_index || modrm_reg == reg) 14031 strcat (ins->op_out[0], "/(bad)"); 14032 if (sib_index == modrm_reg || sib_index == reg) 14033 strcat (ins->op_out[1], "/(bad)"); 14034 14035 return true; 14036 14037 case tmm_mode: 14038 /* All 3 TMM registers must be distinct. */ 14039 if (reg >= 8) 14040 oappend (ins, "(bad)"); 14041 else 14042 { 14043 /* This must be the 3rd operand. */ 14044 if (ins->obufp != ins->op_out[2]) 14045 abort (); 14046 oappend_register (ins, att_names_tmm[reg]); 14047 if (reg == ins->modrm.reg || reg == ins->modrm.rm) 14048 strcpy (ins->obufp, "/(bad)"); 14049 } 14050 14051 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg 14052 || ins->modrm.rm == reg) 14053 { 14054 if (ins->modrm.reg <= 8 14055 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg)) 14056 strcat (ins->op_out[0], "/(bad)"); 14057 if (ins->modrm.rm <= 8 14058 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg)) 14059 strcat (ins->op_out[1], "/(bad)"); 14060 } 14061 14062 return true; 14063 14064 case v_mode: 14065 case dq_mode: 14066 if (ins->rex & REX_W) 14067 oappend_register (ins, att_names64[reg]); 14068 else if (bytemode == v_mode 14069 && !(sizeflag & DFLAG)) 14070 oappend_register (ins, att_names16[reg]); 14071 else 14072 oappend_register (ins, att_names32[reg]); 14073 return true; 14074 14075 case b_mode: 14076 oappend_register (ins, att_names8rex[reg]); 14077 return true; 14078 14079 case q_mode: 14080 oappend_register (ins, att_names64[reg]); 14081 return true; 14082 } 14083 14084 switch (ins->vex.length) 14085 { 14086 case 128: 14087 switch (bytemode) 14088 { 14089 case x_mode: 14090 names = att_names_xmm; 14091 ins->evex_used |= EVEX_len_used; 14092 break; 14093 case mask_bd_mode: 14094 case mask_mode: 14095 if (reg > 0x7) 14096 { 14097 oappend (ins, "(bad)"); 14098 return true; 14099 } 14100 names = att_names_mask; 14101 break; 14102 default: 14103 abort (); 14104 return true; 14105 } 14106 break; 14107 case 256: 14108 switch (bytemode) 14109 { 14110 case x_mode: 14111 names = att_names_ymm; 14112 ins->evex_used |= EVEX_len_used; 14113 break; 14114 case mask_bd_mode: 14115 case mask_mode: 14116 if (reg <= 0x7) 14117 { 14118 names = att_names_mask; 14119 break; 14120 } 14121 /* Fall through. */ 14122 default: 14123 /* See PR binutils/20893 for a reproducer. */ 14124 oappend (ins, "(bad)"); 14125 return true; 14126 } 14127 break; 14128 case 512: 14129 names = att_names_zmm; 14130 ins->evex_used |= EVEX_len_used; 14131 break; 14132 default: 14133 abort (); 14134 break; 14135 } 14136 oappend_register (ins, names[reg]); 14137 return true; 14138 } 14139 14140 static bool 14141 OP_VexR (instr_info *ins, int bytemode, int sizeflag) 14142 { 14143 if (ins->modrm.mod == 3) 14144 return OP_VEX (ins, bytemode, sizeflag); 14145 return true; 14146 } 14147 14148 static bool 14149 OP_VexW (instr_info *ins, int bytemode, int sizeflag) 14150 { 14151 OP_VEX (ins, bytemode, sizeflag); 14152 14153 if (ins->vex.w) 14154 { 14155 /* Swap 2nd and 3rd operands. */ 14156 char *tmp = ins->op_out[2]; 14157 14158 ins->op_out[2] = ins->op_out[1]; 14159 ins->op_out[1] = tmp; 14160 } 14161 return true; 14162 } 14163 14164 static bool 14165 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14166 { 14167 int reg; 14168 const char (*names)[8] = att_names_xmm; 14169 14170 if (!fetch_code (ins->info, ins->codep + 1)) 14171 return false; 14172 reg = *ins->codep++; 14173 14174 if (bytemode != x_mode && bytemode != scalar_mode) 14175 abort (); 14176 14177 reg >>= 4; 14178 if (ins->address_mode != mode_64bit) 14179 reg &= 7; 14180 14181 if (bytemode == x_mode && ins->vex.length == 256) 14182 names = att_names_ymm; 14183 14184 oappend_register (ins, names[reg]); 14185 14186 if (ins->vex.w) 14187 { 14188 /* Swap 3rd and 4th operands. */ 14189 char *tmp = ins->op_out[3]; 14190 14191 ins->op_out[3] = ins->op_out[2]; 14192 ins->op_out[2] = tmp; 14193 } 14194 return true; 14195 } 14196 14197 static bool 14198 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 14199 int sizeflag ATTRIBUTE_UNUSED) 14200 { 14201 oappend_immediate (ins, ins->codep[-1] & 0xf); 14202 return true; 14203 } 14204 14205 static bool 14206 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 14207 int sizeflag ATTRIBUTE_UNUSED) 14208 { 14209 unsigned int cmp_type; 14210 14211 if (!ins->vex.evex) 14212 abort (); 14213 14214 if (!fetch_code (ins->info, ins->codep + 1)) 14215 return false; 14216 cmp_type = *ins->codep++; 14217 /* There are aliases for immediates 0, 1, 2, 4, 5, 6. 14218 If it's the case, print suffix, otherwise - print the immediate. */ 14219 if (cmp_type < ARRAY_SIZE (simd_cmp_op) 14220 && cmp_type != 3 14221 && cmp_type != 7) 14222 { 14223 char suffix[3]; 14224 char *p = ins->mnemonicendp - 2; 14225 14226 /* vpcmp* can have both one- and two-lettered suffix. */ 14227 if (p[0] == 'p') 14228 { 14229 p++; 14230 suffix[0] = p[0]; 14231 suffix[1] = '\0'; 14232 } 14233 else 14234 { 14235 suffix[0] = p[0]; 14236 suffix[1] = p[1]; 14237 suffix[2] = '\0'; 14238 } 14239 14240 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 14241 ins->mnemonicendp += simd_cmp_op[cmp_type].len; 14242 } 14243 else 14244 { 14245 /* We have a reserved extension byte. Output it directly. */ 14246 oappend_immediate (ins, cmp_type); 14247 } 14248 return true; 14249 } 14250 14251 static const struct op xop_cmp_op[] = 14252 { 14253 { STRING_COMMA_LEN ("lt") }, 14254 { STRING_COMMA_LEN ("le") }, 14255 { STRING_COMMA_LEN ("gt") }, 14256 { STRING_COMMA_LEN ("ge") }, 14257 { STRING_COMMA_LEN ("eq") }, 14258 { STRING_COMMA_LEN ("neq") }, 14259 { STRING_COMMA_LEN ("false") }, 14260 { STRING_COMMA_LEN ("true") } 14261 }; 14262 14263 static bool 14264 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 14265 int sizeflag ATTRIBUTE_UNUSED) 14266 { 14267 unsigned int cmp_type; 14268 14269 if (!fetch_code (ins->info, ins->codep + 1)) 14270 return false; 14271 cmp_type = *ins->codep++; 14272 if (cmp_type < ARRAY_SIZE (xop_cmp_op)) 14273 { 14274 char suffix[3]; 14275 char *p = ins->mnemonicendp - 2; 14276 14277 /* vpcom* can have both one- and two-lettered suffix. */ 14278 if (p[0] == 'm') 14279 { 14280 p++; 14281 suffix[0] = p[0]; 14282 suffix[1] = '\0'; 14283 } 14284 else 14285 { 14286 suffix[0] = p[0]; 14287 suffix[1] = p[1]; 14288 suffix[2] = '\0'; 14289 } 14290 14291 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); 14292 ins->mnemonicendp += xop_cmp_op[cmp_type].len; 14293 } 14294 else 14295 { 14296 /* We have a reserved extension byte. Output it directly. */ 14297 oappend_immediate (ins, cmp_type); 14298 } 14299 return true; 14300 } 14301 14302 static const struct op pclmul_op[] = 14303 { 14304 { STRING_COMMA_LEN ("lql") }, 14305 { STRING_COMMA_LEN ("hql") }, 14306 { STRING_COMMA_LEN ("lqh") }, 14307 { STRING_COMMA_LEN ("hqh") } 14308 }; 14309 14310 static bool 14311 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, 14312 int sizeflag ATTRIBUTE_UNUSED) 14313 { 14314 unsigned int pclmul_type; 14315 14316 if (!fetch_code (ins->info, ins->codep + 1)) 14317 return false; 14318 pclmul_type = *ins->codep++; 14319 switch (pclmul_type) 14320 { 14321 case 0x10: 14322 pclmul_type = 2; 14323 break; 14324 case 0x11: 14325 pclmul_type = 3; 14326 break; 14327 default: 14328 break; 14329 } 14330 if (pclmul_type < ARRAY_SIZE (pclmul_op)) 14331 { 14332 char suffix[4]; 14333 char *p = ins->mnemonicendp - 3; 14334 suffix[0] = p[0]; 14335 suffix[1] = p[1]; 14336 suffix[2] = p[2]; 14337 suffix[3] = '\0'; 14338 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); 14339 ins->mnemonicendp += pclmul_op[pclmul_type].len; 14340 } 14341 else 14342 { 14343 /* We have a reserved extension byte. Output it directly. */ 14344 oappend_immediate (ins, pclmul_type); 14345 } 14346 return true; 14347 } 14348 14349 static bool 14350 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag) 14351 { 14352 /* Add proper suffix to "movsxd". */ 14353 char *p = ins->mnemonicendp; 14354 14355 switch (bytemode) 14356 { 14357 case movsxd_mode: 14358 if (!ins->intel_syntax) 14359 { 14360 USED_REX (REX_W); 14361 if (ins->rex & REX_W) 14362 { 14363 *p++ = 'l'; 14364 *p++ = 'q'; 14365 break; 14366 } 14367 } 14368 14369 *p++ = 'x'; 14370 *p++ = 'd'; 14371 break; 14372 default: 14373 oappend (ins, INTERNAL_DISASSEMBLER_ERROR); 14374 break; 14375 } 14376 14377 ins->mnemonicendp = p; 14378 *p = '\0'; 14379 return OP_E (ins, bytemode, sizeflag); 14380 } 14381 14382 static bool 14383 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) 14384 { 14385 unsigned int reg = ins->vex.register_specifier; 14386 unsigned int modrm_reg = ins->modrm.reg; 14387 unsigned int modrm_rm = ins->modrm.rm; 14388 14389 /* Calc destination register number. */ 14390 if (ins->rex & REX_R) 14391 modrm_reg += 8; 14392 if (ins->rex2 & REX_R) 14393 modrm_reg += 16; 14394 14395 /* Calc src1 register number. */ 14396 if (ins->address_mode != mode_64bit) 14397 reg &= 7; 14398 else if (ins->vex.evex && !ins->vex.v) 14399 reg += 16; 14400 14401 /* Calc src2 register number. */ 14402 if (ins->modrm.mod == 3) 14403 { 14404 if (ins->rex & REX_B) 14405 modrm_rm += 8; 14406 if (ins->rex & REX_X) 14407 modrm_rm += 16; 14408 } 14409 14410 /* Destination and source registers must be distinct, output bad if 14411 dest == src1 or dest == src2. */ 14412 if (modrm_reg == reg 14413 || (ins->modrm.mod == 3 14414 && modrm_reg == modrm_rm)) 14415 { 14416 oappend (ins, "(bad)"); 14417 return true; 14418 } 14419 return OP_XMM (ins, bytemode, sizeflag); 14420 } 14421 14422 static bool 14423 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14424 { 14425 if (ins->modrm.mod != 3 || !ins->vex.b) 14426 return true; 14427 14428 ins->evex_used |= EVEX_b_used; 14429 switch (bytemode) 14430 { 14431 case evex_rounding_64_mode: 14432 if (ins->address_mode != mode_64bit || !ins->vex.w) 14433 return true; 14434 /* Fall through. */ 14435 case evex_rounding_mode: 14436 oappend (ins, names_rounding[ins->vex.ll]); 14437 break; 14438 case evex_sae_mode: 14439 oappend (ins, "{"); 14440 break; 14441 default: 14442 abort (); 14443 } 14444 oappend (ins, "sae}"); 14445 return true; 14446 } 14447 14448 static bool 14449 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) 14450 { 14451 if (ins->modrm.mod != 0 || ins->modrm.rm != 5) 14452 { 14453 if (ins->intel_syntax) 14454 { 14455 ins->mnemonicendp = stpcpy (ins->obuf, "nop "); 14456 } 14457 else 14458 { 14459 USED_REX (REX_W); 14460 if (ins->rex & REX_W) 14461 ins->mnemonicendp = stpcpy (ins->obuf, "nopq "); 14462 else 14463 { 14464 if (sizeflag & DFLAG) 14465 ins->mnemonicendp = stpcpy (ins->obuf, "nopl "); 14466 else 14467 ins->mnemonicendp = stpcpy (ins->obuf, "nopw "); 14468 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); 14469 } 14470 } 14471 bytemode = v_mode; 14472 } 14473 14474 return OP_M (ins, bytemode, sizeflag); 14475 } 14476 14477 static bool 14478 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag) 14479 { 14480 if (ins->modrm.mod != 3) 14481 return true; 14482 14483 unsigned int vvvv_reg = ins->vex.register_specifier 14484 | (!ins->vex.v << 4); 14485 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) 14486 + (ins->rex2 & REX_B ? 16 : 0); 14487 14488 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ 14489 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4 14490 || (!ins->modrm.reg 14491 && vvvv_reg == rm_reg)) 14492 { 14493 oappend (ins, "(bad)"); 14494 return true; 14495 } 14496 14497 return OP_VEX (ins, bytemode, sizeflag); 14498 } 14499 14500 static bool 14501 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag) 14502 { 14503 if (ins->last_rex2_prefix >= 0) 14504 { 14505 uint64_t op; 14506 14507 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0 14508 || (ins->rex & REX_W) != 0x0) 14509 { 14510 oappend (ins, "(bad)"); 14511 return true; 14512 } 14513 14514 if (bytemode == eAX_reg) 14515 return true; 14516 14517 if (!get64 (ins, &op)) 14518 return false; 14519 14520 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs"); 14521 ins->rex2 |= REX2_SPECIAL; 14522 oappend_immediate (ins, op); 14523 14524 return true; 14525 } 14526 14527 if (bytemode == eAX_reg) 14528 return OP_IMREG (ins, bytemode, sizeflag); 14529 return OP_OFF64 (ins, bytemode, sizeflag); 14530 } 14531 14532 static bool 14533 CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag) 14534 { 14535 /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the 14536 source and destination operands. */ 14537 bool dstmem = !ins->vex.nd && ins->vex.nf; 14538 14539 if (opnd == 0) 14540 { 14541 if (dstmem) 14542 return OP_E (ins, v_swap_mode, sizeflag); 14543 return OP_G (ins, v_mode, sizeflag); 14544 } 14545 14546 /* These bits have been consumed and should be cleared. */ 14547 ins->vex.nf = false; 14548 ins->vex.mask_register_specifier = 0; 14549 14550 if (dstmem) 14551 return OP_G (ins, v_mode, sizeflag); 14552 return OP_E (ins, v_mode, sizeflag); 14553 } 14554
Indexes created Mon Mar 23 00:23:30 UTC 2026