i386-dis.c revision 1.1.1.5
1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright (C) 1988-2015 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* 80386 instruction printer by Pace Willisson (pace (at) prep.ai.mit.edu) 23 July 1988 24 modified by John Hassey (hassey (at) dg-rtp.dg.com) 25 x86-64 support added by Jan Hubicka (jh (at) suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz). */ 27 28 /* The main tables describing the instructions is essentially a copy 29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 30 Programmers Manual. Usually, there is a capital letter, followed 31 by a small letter. The capital letter tell the addressing mode, 32 and the small letter tells about the operand size. Refer to 33 the Intel manual for details. */ 34 35 #include "sysdep.h" 36 #include "dis-asm.h" 37 #include "opintl.h" 38 #include "opcode/i386.h" 39 #include "libiberty.h" 40 41 #include <setjmp.h> 42 43 static int print_insn (bfd_vma, disassemble_info *); 44 static void dofloat (int); 45 static void OP_ST (int, int); 46 static void OP_STi (int, int); 47 static int putop (const char *, int); 48 static void oappend (const char *); 49 static void append_seg (void); 50 static void OP_indirE (int, int); 51 static void print_operand_value (char *, int, bfd_vma); 52 static void OP_E_register (int, int); 53 static void OP_E_memory (int, int); 54 static void print_displacement (char *, bfd_vma); 55 static void OP_E (int, int); 56 static void OP_G (int, int); 57 static bfd_vma get64 (void); 58 static bfd_signed_vma get32 (void); 59 static bfd_signed_vma get32s (void); 60 static int get16 (void); 61 static void set_op (bfd_vma, int); 62 static void OP_Skip_MODRM (int, int); 63 static void OP_REG (int, int); 64 static void OP_IMREG (int, int); 65 static void OP_I (int, int); 66 static void OP_I64 (int, int); 67 static void OP_sI (int, int); 68 static void OP_J (int, int); 69 static void OP_SEG (int, int); 70 static void OP_DIR (int, int); 71 static void OP_OFF (int, int); 72 static void OP_OFF64 (int, int); 73 static void ptr_reg (int, int); 74 static void OP_ESreg (int, int); 75 static void OP_DSreg (int, int); 76 static void OP_C (int, int); 77 static void OP_D (int, int); 78 static void OP_T (int, int); 79 static void OP_R (int, int); 80 static void OP_MMX (int, int); 81 static void OP_XMM (int, int); 82 static void OP_EM (int, int); 83 static void OP_EX (int, int); 84 static void OP_EMC (int,int); 85 static void OP_MXC (int,int); 86 static void OP_MS (int, int); 87 static void OP_XS (int, int); 88 static void OP_M (int, int); 89 static void OP_VEX (int, int); 90 static void OP_EX_Vex (int, int); 91 static void OP_EX_VexW (int, int); 92 static void OP_EX_VexImmW (int, int); 93 static void OP_XMM_Vex (int, int); 94 static void OP_XMM_VexW (int, int); 95 static void OP_Rounding (int, int); 96 static void OP_REG_VexI4 (int, int); 97 static void PCLMUL_Fixup (int, int); 98 static void VEXI4_Fixup (int, int); 99 static void VZERO_Fixup (int, int); 100 static void VCMP_Fixup (int, int); 101 static void VPCMP_Fixup (int, int); 102 static void OP_0f07 (int, int); 103 static void OP_Monitor (int, int); 104 static void OP_Mwait (int, int); 105 static void OP_Mwaitx (int, int); 106 static void NOP_Fixup1 (int, int); 107 static void NOP_Fixup2 (int, int); 108 static void OP_3DNowSuffix (int, int); 109 static void CMP_Fixup (int, int); 110 static void BadOp (void); 111 static void REP_Fixup (int, int); 112 static void BND_Fixup (int, int); 113 static void HLE_Fixup1 (int, int); 114 static void HLE_Fixup2 (int, int); 115 static void HLE_Fixup3 (int, int); 116 static void CMPXCHG8B_Fixup (int, int); 117 static void XMM_Fixup (int, int); 118 static void CRC32_Fixup (int, int); 119 static void FXSAVE_Fixup (int, int); 120 static void OP_LWPCB_E (int, int); 121 static void OP_LWP_E (int, int); 122 static void OP_Vex_2src_1 (int, int); 123 static void OP_Vex_2src_2 (int, int); 124 125 static void MOVBE_Fixup (int, int); 126 127 static void OP_Mask (int, int); 128 129 struct dis_private { 130 /* Points to first byte not fetched. */ 131 bfd_byte *max_fetched; 132 bfd_byte the_buffer[MAX_MNEM_SIZE]; 133 bfd_vma insn_start; 134 int orig_sizeflag; 135 OPCODES_SIGJMP_BUF bailout; 136 }; 137 138 enum address_mode 139 { 140 mode_16bit, 141 mode_32bit, 142 mode_64bit 143 }; 144 145 enum address_mode address_mode; 146 147 /* Flags for the prefixes for the current instruction. See below. */ 148 static int prefixes; 149 150 /* REX prefix the current instruction. See below. */ 151 static int rex; 152 /* Bits of REX we've already used. */ 153 static int rex_used; 154 /* REX bits in original REX prefix ignored. */ 155 static int rex_ignored; 156 /* Mark parts used in the REX prefix. When we are testing for 157 empty prefix (for 8bit register REX extension), just mask it 158 out. Otherwise test for REX bit is excuse for existence of REX 159 only in case value is nonzero. */ 160 #define USED_REX(value) \ 161 { \ 162 if (value) \ 163 { \ 164 if ((rex & value)) \ 165 rex_used |= (value) | REX_OPCODE; \ 166 } \ 167 else \ 168 rex_used |= REX_OPCODE; \ 169 } 170 171 /* Flags for prefixes which we somehow handled when printing the 172 current instruction. */ 173 static int used_prefixes; 174 175 /* Flags stored in PREFIXES. */ 176 #define PREFIX_REPZ 1 177 #define PREFIX_REPNZ 2 178 #define PREFIX_LOCK 4 179 #define PREFIX_CS 8 180 #define PREFIX_SS 0x10 181 #define PREFIX_DS 0x20 182 #define PREFIX_ES 0x40 183 #define PREFIX_FS 0x80 184 #define PREFIX_GS 0x100 185 #define PREFIX_DATA 0x200 186 #define PREFIX_ADDR 0x400 187 #define PREFIX_FWAIT 0x800 188 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps 191 on error. */ 192 #define FETCH_DATA(info, addr) \ 193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ 194 ? 1 : fetch_data ((info), (addr))) 195 196 static int 197 fetch_data (struct disassemble_info *info, bfd_byte *addr) 198 { 199 int status; 200 struct dis_private *priv = (struct dis_private *) info->private_data; 201 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 202 203 if (addr <= priv->the_buffer + MAX_MNEM_SIZE) 204 status = (*info->read_memory_func) (start, 205 priv->max_fetched, 206 addr - priv->max_fetched, 207 info); 208 else 209 status = -1; 210 if (status != 0) 211 { 212 /* If we did manage to read at least one byte, then 213 print_insn_i386 will do something sensible. Otherwise, print 214 an error. We do that here because this is where we know 215 STATUS. */ 216 if (priv->max_fetched == priv->the_buffer) 217 (*info->memory_error_func) (status, start, info); 218 OPCODES_SIGLONGJMP (priv->bailout, 1); 219 } 220 else 221 priv->max_fetched = addr; 222 return 1; 223 } 224 225 /* Possible values for prefix requirement. */ 226 #define PREFIX_IGNORED_SHIFT 16 227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) 228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) 229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) 230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) 231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) 232 233 /* Opcode prefixes. */ 234 #define PREFIX_OPCODE (PREFIX_REPZ \ 235 | PREFIX_REPNZ \ 236 | PREFIX_DATA) 237 238 /* Prefixes ignored. */ 239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ 240 | PREFIX_IGNORED_REPNZ \ 241 | PREFIX_IGNORED_DATA) 242 243 #define XX { NULL, 0 } 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0 245 246 #define Eb { OP_E, b_mode } 247 #define Ebnd { OP_E, bnd_mode } 248 #define EbS { OP_E, b_swap_mode } 249 #define Ev { OP_E, v_mode } 250 #define Ev_bnd { OP_E, v_bnd_mode } 251 #define EvS { OP_E, v_swap_mode } 252 #define Ed { OP_E, d_mode } 253 #define Edq { OP_E, dq_mode } 254 #define Edqw { OP_E, dqw_mode } 255 #define EdqwS { OP_E, dqw_swap_mode } 256 #define Edqb { OP_E, dqb_mode } 257 #define Edb { OP_E, db_mode } 258 #define Edw { OP_E, dw_mode } 259 #define Edqd { OP_E, dqd_mode } 260 #define Eq { OP_E, q_mode } 261 #define indirEv { OP_indirE, stack_v_mode } 262 #define indirEp { OP_indirE, f_mode } 263 #define stackEv { OP_E, stack_v_mode } 264 #define Em { OP_E, m_mode } 265 #define Ew { OP_E, w_mode } 266 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 267 #define Ma { OP_M, a_mode } 268 #define Mb { OP_M, b_mode } 269 #define Md { OP_M, d_mode } 270 #define Mo { OP_M, o_mode } 271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 272 #define Mq { OP_M, q_mode } 273 #define Mx { OP_M, x_mode } 274 #define Mxmm { OP_M, xmm_mode } 275 #define Gb { OP_G, b_mode } 276 #define Gbnd { OP_G, bnd_mode } 277 #define Gv { OP_G, v_mode } 278 #define Gd { OP_G, d_mode } 279 #define Gdq { OP_G, dq_mode } 280 #define Gm { OP_G, m_mode } 281 #define Gw { OP_G, w_mode } 282 #define Rd { OP_R, d_mode } 283 #define Rdq { OP_R, dq_mode } 284 #define Rm { OP_R, m_mode } 285 #define Ib { OP_I, b_mode } 286 #define sIb { OP_sI, b_mode } /* sign extened byte */ 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ 288 #define Iv { OP_I, v_mode } 289 #define sIv { OP_sI, v_mode } 290 #define Iq { OP_I, q_mode } 291 #define Iv64 { OP_I64, v_mode } 292 #define Iw { OP_I, w_mode } 293 #define I1 { OP_I, const_1_mode } 294 #define Jb { OP_J, b_mode } 295 #define Jv { OP_J, v_mode } 296 #define Cm { OP_C, m_mode } 297 #define Dm { OP_D, m_mode } 298 #define Td { OP_T, d_mode } 299 #define Skip_MODRM { OP_Skip_MODRM, 0 } 300 301 #define RMeAX { OP_REG, eAX_reg } 302 #define RMeBX { OP_REG, eBX_reg } 303 #define RMeCX { OP_REG, eCX_reg } 304 #define RMeDX { OP_REG, eDX_reg } 305 #define RMeSP { OP_REG, eSP_reg } 306 #define RMeBP { OP_REG, eBP_reg } 307 #define RMeSI { OP_REG, eSI_reg } 308 #define RMeDI { OP_REG, eDI_reg } 309 #define RMrAX { OP_REG, rAX_reg } 310 #define RMrBX { OP_REG, rBX_reg } 311 #define RMrCX { OP_REG, rCX_reg } 312 #define RMrDX { OP_REG, rDX_reg } 313 #define RMrSP { OP_REG, rSP_reg } 314 #define RMrBP { OP_REG, rBP_reg } 315 #define RMrSI { OP_REG, rSI_reg } 316 #define RMrDI { OP_REG, rDI_reg } 317 #define RMAL { OP_REG, al_reg } 318 #define RMCL { OP_REG, cl_reg } 319 #define RMDL { OP_REG, dl_reg } 320 #define RMBL { OP_REG, bl_reg } 321 #define RMAH { OP_REG, ah_reg } 322 #define RMCH { OP_REG, ch_reg } 323 #define RMDH { OP_REG, dh_reg } 324 #define RMBH { OP_REG, bh_reg } 325 #define RMAX { OP_REG, ax_reg } 326 #define RMDX { OP_REG, dx_reg } 327 328 #define eAX { OP_IMREG, eAX_reg } 329 #define eBX { OP_IMREG, eBX_reg } 330 #define eCX { OP_IMREG, eCX_reg } 331 #define eDX { OP_IMREG, eDX_reg } 332 #define eSP { OP_IMREG, eSP_reg } 333 #define eBP { OP_IMREG, eBP_reg } 334 #define eSI { OP_IMREG, eSI_reg } 335 #define eDI { OP_IMREG, eDI_reg } 336 #define AL { OP_IMREG, al_reg } 337 #define CL { OP_IMREG, cl_reg } 338 #define DL { OP_IMREG, dl_reg } 339 #define BL { OP_IMREG, bl_reg } 340 #define AH { OP_IMREG, ah_reg } 341 #define CH { OP_IMREG, ch_reg } 342 #define DH { OP_IMREG, dh_reg } 343 #define BH { OP_IMREG, bh_reg } 344 #define AX { OP_IMREG, ax_reg } 345 #define DX { OP_IMREG, dx_reg } 346 #define zAX { OP_IMREG, z_mode_ax_reg } 347 #define indirDX { OP_IMREG, indir_dx_reg } 348 349 #define Sw { OP_SEG, w_mode } 350 #define Sv { OP_SEG, v_mode } 351 #define Ap { OP_DIR, 0 } 352 #define Ob { OP_OFF64, b_mode } 353 #define Ov { OP_OFF64, v_mode } 354 #define Xb { OP_DSreg, eSI_reg } 355 #define Xv { OP_DSreg, eSI_reg } 356 #define Xz { OP_DSreg, eSI_reg } 357 #define Yb { OP_ESreg, eDI_reg } 358 #define Yv { OP_ESreg, eDI_reg } 359 #define DSBX { OP_DSreg, eBX_reg } 360 361 #define es { OP_REG, es_reg } 362 #define ss { OP_REG, ss_reg } 363 #define cs { OP_REG, cs_reg } 364 #define ds { OP_REG, ds_reg } 365 #define fs { OP_REG, fs_reg } 366 #define gs { OP_REG, gs_reg } 367 368 #define MX { OP_MMX, 0 } 369 #define XM { OP_XMM, 0 } 370 #define XMScalar { OP_XMM, scalar_mode } 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } 372 #define XMM { OP_XMM, xmm_mode } 373 #define XMxmmq { OP_XMM, xmmq_mode } 374 #define EM { OP_EM, v_mode } 375 #define EMS { OP_EM, v_swap_mode } 376 #define EMd { OP_EM, d_mode } 377 #define EMx { OP_EM, x_mode } 378 #define EXw { OP_EX, w_mode } 379 #define EXd { OP_EX, d_mode } 380 #define EXdScalar { OP_EX, d_scalar_mode } 381 #define EXdS { OP_EX, d_swap_mode } 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode } 383 #define EXq { OP_EX, q_mode } 384 #define EXqScalar { OP_EX, q_scalar_mode } 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode } 386 #define EXqS { OP_EX, q_swap_mode } 387 #define EXx { OP_EX, x_mode } 388 #define EXxS { OP_EX, x_swap_mode } 389 #define EXxmm { OP_EX, xmm_mode } 390 #define EXymm { OP_EX, ymm_mode } 391 #define EXxmmq { OP_EX, xmmq_mode } 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } 393 #define EXxmm_mb { OP_EX, xmm_mb_mode } 394 #define EXxmm_mw { OP_EX, xmm_mw_mode } 395 #define EXxmm_md { OP_EX, xmm_md_mode } 396 #define EXxmm_mq { OP_EX, xmm_mq_mode } 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode } 398 #define EXxmmdw { OP_EX, xmmdw_mode } 399 #define EXxmmqd { OP_EX, xmmqd_mode } 400 #define EXymmq { OP_EX, ymmq_mode } 401 #define EXVexWdq { OP_EX, vex_w_dq_mode } 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } 405 #define MS { OP_MS, v_mode } 406 #define XS { OP_XS, v_mode } 407 #define EMCq { OP_EMC, q_mode } 408 #define MXC { OP_MXC, 0 } 409 #define OPSUF { OP_3DNowSuffix, 0 } 410 #define CMP { CMP_Fixup, 0 } 411 #define XMM0 { XMM_Fixup, 0 } 412 #define FXSAVE { FXSAVE_Fixup, 0 } 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 } 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 } 415 416 #define Vex { OP_VEX, vex_mode } 417 #define VexScalar { OP_VEX, vex_scalar_mode } 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } 419 #define Vex128 { OP_VEX, vex128_mode } 420 #define Vex256 { OP_VEX, vex256_mode } 421 #define VexGdq { OP_VEX, dq_mode } 422 #define VexI4 { VEXI4_Fixup, 0} 423 #define EXdVex { OP_EX_Vex, d_mode } 424 #define EXdVexS { OP_EX_Vex, d_swap_mode } 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } 426 #define EXqVex { OP_EX_Vex, q_mode } 427 #define EXqVexS { OP_EX_Vex, q_swap_mode } 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } 429 #define EXVexW { OP_EX_VexW, x_mode } 430 #define EXdVexW { OP_EX_VexW, d_mode } 431 #define EXqVexW { OP_EX_VexW, q_mode } 432 #define EXVexImmW { OP_EX_VexImmW, x_mode } 433 #define XMVex { OP_XMM_Vex, 0 } 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode } 435 #define XMVexW { OP_XMM_VexW, 0 } 436 #define XMVexI4 { OP_REG_VexI4, x_mode } 437 #define PCLMUL { PCLMUL_Fixup, 0 } 438 #define VZERO { VZERO_Fixup, 0 } 439 #define VCMP { VCMP_Fixup, 0 } 440 #define VPCMP { VPCMP_Fixup, 0 } 441 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode } 443 #define EXxEVexS { OP_Rounding, evex_sae_mode } 444 445 #define XMask { OP_Mask, mask_mode } 446 #define MaskG { OP_G, mask_mode } 447 #define MaskE { OP_E, mask_mode } 448 #define MaskBDE { OP_E, mask_bd_mode } 449 #define MaskR { OP_R, mask_mode } 450 #define MaskVex { OP_VEX, mask_mode } 451 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } 456 457 /* Used handle "rep" prefix for string instructions. */ 458 #define Xbr { REP_Fixup, eSI_reg } 459 #define Xvr { REP_Fixup, eSI_reg } 460 #define Ybr { REP_Fixup, eDI_reg } 461 #define Yvr { REP_Fixup, eDI_reg } 462 #define Yzr { REP_Fixup, eDI_reg } 463 #define indirDXr { REP_Fixup, indir_dx_reg } 464 #define ALr { REP_Fixup, al_reg } 465 #define eAXr { REP_Fixup, eAX_reg } 466 467 /* Used handle HLE prefix for lockable instructions. */ 468 #define Ebh1 { HLE_Fixup1, b_mode } 469 #define Evh1 { HLE_Fixup1, v_mode } 470 #define Ebh2 { HLE_Fixup2, b_mode } 471 #define Evh2 { HLE_Fixup2, v_mode } 472 #define Ebh3 { HLE_Fixup3, b_mode } 473 #define Evh3 { HLE_Fixup3, v_mode } 474 475 #define BND { BND_Fixup, 0 } 476 477 #define cond_jump_flag { NULL, cond_jump_mode } 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 479 480 /* bits in sizeflag */ 481 #define SUFFIX_ALWAYS 4 482 #define AFLAG 2 483 #define DFLAG 1 484 485 enum 486 { 487 /* byte operand */ 488 b_mode = 1, 489 /* byte operand with operand swapped */ 490 b_swap_mode, 491 /* byte operand, sign extend like 'T' suffix */ 492 b_T_mode, 493 /* operand size depends on prefixes */ 494 v_mode, 495 /* operand size depends on prefixes with operand swapped */ 496 v_swap_mode, 497 /* word operand */ 498 w_mode, 499 /* double word operand */ 500 d_mode, 501 /* double word operand with operand swapped */ 502 d_swap_mode, 503 /* quad word operand */ 504 q_mode, 505 /* quad word operand with operand swapped */ 506 q_swap_mode, 507 /* ten-byte operand */ 508 t_mode, 509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 510 broadcast enabled. */ 511 x_mode, 512 /* Similar to x_mode, but with different EVEX mem shifts. */ 513 evex_x_gscat_mode, 514 /* Similar to x_mode, but with disabled broadcast. */ 515 evex_x_nobcst_mode, 516 /* Similar to x_mode, but with operands swapped and disabled broadcast 517 in EVEX. */ 518 x_swap_mode, 519 /* 16-byte XMM operand */ 520 xmm_mode, 521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 522 memory operand (depending on vector length). Broadcast isn't 523 allowed. */ 524 xmmq_mode, 525 /* Same as xmmq_mode, but broadcast is allowed. */ 526 evex_half_bcst_xmmq_mode, 527 /* XMM register or byte memory operand */ 528 xmm_mb_mode, 529 /* XMM register or word memory operand */ 530 xmm_mw_mode, 531 /* XMM register or double word memory operand */ 532 xmm_md_mode, 533 /* XMM register or quad word memory operand */ 534 xmm_mq_mode, 535 /* XMM register or double/quad word memory operand, depending on 536 VEX.W. */ 537 xmm_mdq_mode, 538 /* 16-byte XMM, word, double word or quad word operand. */ 539 xmmdw_mode, 540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */ 541 xmmqd_mode, 542 /* 32-byte YMM operand */ 543 ymm_mode, 544 /* quad word, ymmword or zmmword memory operand. */ 545 ymmq_mode, 546 /* 32-byte YMM or 16-byte word operand */ 547 ymmxmm_mode, 548 /* d_mode in 32bit, q_mode in 64bit mode. */ 549 m_mode, 550 /* pair of v_mode operands */ 551 a_mode, 552 cond_jump_mode, 553 loop_jcxz_mode, 554 v_bnd_mode, 555 /* operand size depends on REX prefixes. */ 556 dq_mode, 557 /* registers like dq_mode, memory like w_mode. */ 558 dqw_mode, 559 dqw_swap_mode, 560 bnd_mode, 561 /* 4- or 6-byte pointer operand */ 562 f_mode, 563 const_1_mode, 564 /* v_mode for stack-related opcodes. */ 565 stack_v_mode, 566 /* non-quad operand size depends on prefixes */ 567 z_mode, 568 /* 16-byte operand */ 569 o_mode, 570 /* registers like dq_mode, memory like b_mode. */ 571 dqb_mode, 572 /* registers like d_mode, memory like b_mode. */ 573 db_mode, 574 /* registers like d_mode, memory like w_mode. */ 575 dw_mode, 576 /* registers like dq_mode, memory like d_mode. */ 577 dqd_mode, 578 /* normal vex mode */ 579 vex_mode, 580 /* 128bit vex mode */ 581 vex128_mode, 582 /* 256bit vex mode */ 583 vex256_mode, 584 /* operand size depends on the VEX.W bit. */ 585 vex_w_dq_mode, 586 587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */ 588 vex_vsib_d_w_dq_mode, 589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ 590 vex_vsib_d_w_d_mode, 591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */ 592 vex_vsib_q_w_dq_mode, 593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ 594 vex_vsib_q_w_d_mode, 595 596 /* scalar, ignore vector length. */ 597 scalar_mode, 598 /* like d_mode, ignore vector length. */ 599 d_scalar_mode, 600 /* like d_swap_mode, ignore vector length. */ 601 d_scalar_swap_mode, 602 /* like q_mode, ignore vector length. */ 603 q_scalar_mode, 604 /* like q_swap_mode, ignore vector length. */ 605 q_scalar_swap_mode, 606 /* like vex_mode, ignore vector length. */ 607 vex_scalar_mode, 608 /* like vex_w_dq_mode, ignore vector length. */ 609 vex_scalar_w_dq_mode, 610 611 /* Static rounding. */ 612 evex_rounding_mode, 613 /* Supress all exceptions. */ 614 evex_sae_mode, 615 616 /* Mask register operand. */ 617 mask_mode, 618 /* Mask register operand. */ 619 mask_bd_mode, 620 621 es_reg, 622 cs_reg, 623 ss_reg, 624 ds_reg, 625 fs_reg, 626 gs_reg, 627 628 eAX_reg, 629 eCX_reg, 630 eDX_reg, 631 eBX_reg, 632 eSP_reg, 633 eBP_reg, 634 eSI_reg, 635 eDI_reg, 636 637 al_reg, 638 cl_reg, 639 dl_reg, 640 bl_reg, 641 ah_reg, 642 ch_reg, 643 dh_reg, 644 bh_reg, 645 646 ax_reg, 647 cx_reg, 648 dx_reg, 649 bx_reg, 650 sp_reg, 651 bp_reg, 652 si_reg, 653 di_reg, 654 655 rAX_reg, 656 rCX_reg, 657 rDX_reg, 658 rBX_reg, 659 rSP_reg, 660 rBP_reg, 661 rSI_reg, 662 rDI_reg, 663 664 z_mode_ax_reg, 665 indir_dx_reg 666 }; 667 668 enum 669 { 670 FLOATCODE = 1, 671 USE_REG_TABLE, 672 USE_MOD_TABLE, 673 USE_RM_TABLE, 674 USE_PREFIX_TABLE, 675 USE_X86_64_TABLE, 676 USE_3BYTE_TABLE, 677 USE_XOP_8F_TABLE, 678 USE_VEX_C4_TABLE, 679 USE_VEX_C5_TABLE, 680 USE_VEX_LEN_TABLE, 681 USE_VEX_W_TABLE, 682 USE_EVEX_TABLE 683 }; 684 685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 686 687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P 689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) 696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) 697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) 698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) 699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) 701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) 702 703 enum 704 { 705 REG_80 = 0, 706 REG_81, 707 REG_82, 708 REG_8F, 709 REG_C0, 710 REG_C1, 711 REG_C6, 712 REG_C7, 713 REG_D0, 714 REG_D1, 715 REG_D2, 716 REG_D3, 717 REG_F6, 718 REG_F7, 719 REG_FE, 720 REG_FF, 721 REG_0F00, 722 REG_0F01, 723 REG_0F0D, 724 REG_0F18, 725 REG_0F71, 726 REG_0F72, 727 REG_0F73, 728 REG_0FA6, 729 REG_0FA7, 730 REG_0FAE, 731 REG_0FBA, 732 REG_0FC7, 733 REG_VEX_0F71, 734 REG_VEX_0F72, 735 REG_VEX_0F73, 736 REG_VEX_0FAE, 737 REG_VEX_0F38F3, 738 REG_XOP_LWPCB, 739 REG_XOP_LWP, 740 REG_XOP_TBM_01, 741 REG_XOP_TBM_02, 742 743 REG_EVEX_0F71, 744 REG_EVEX_0F72, 745 REG_EVEX_0F73, 746 REG_EVEX_0F38C6, 747 REG_EVEX_0F38C7 748 }; 749 750 enum 751 { 752 MOD_8D = 0, 753 MOD_C6_REG_7, 754 MOD_C7_REG_7, 755 MOD_FF_REG_3, 756 MOD_FF_REG_5, 757 MOD_0F01_REG_0, 758 MOD_0F01_REG_1, 759 MOD_0F01_REG_2, 760 MOD_0F01_REG_3, 761 MOD_0F01_REG_7, 762 MOD_0F12_PREFIX_0, 763 MOD_0F13, 764 MOD_0F16_PREFIX_0, 765 MOD_0F17, 766 MOD_0F18_REG_0, 767 MOD_0F18_REG_1, 768 MOD_0F18_REG_2, 769 MOD_0F18_REG_3, 770 MOD_0F18_REG_4, 771 MOD_0F18_REG_5, 772 MOD_0F18_REG_6, 773 MOD_0F18_REG_7, 774 MOD_0F1A_PREFIX_0, 775 MOD_0F1B_PREFIX_0, 776 MOD_0F1B_PREFIX_1, 777 MOD_0F24, 778 MOD_0F26, 779 MOD_0F2B_PREFIX_0, 780 MOD_0F2B_PREFIX_1, 781 MOD_0F2B_PREFIX_2, 782 MOD_0F2B_PREFIX_3, 783 MOD_0F51, 784 MOD_0F71_REG_2, 785 MOD_0F71_REG_4, 786 MOD_0F71_REG_6, 787 MOD_0F72_REG_2, 788 MOD_0F72_REG_4, 789 MOD_0F72_REG_6, 790 MOD_0F73_REG_2, 791 MOD_0F73_REG_3, 792 MOD_0F73_REG_6, 793 MOD_0F73_REG_7, 794 MOD_0FAE_REG_0, 795 MOD_0FAE_REG_1, 796 MOD_0FAE_REG_2, 797 MOD_0FAE_REG_3, 798 MOD_0FAE_REG_4, 799 MOD_0FAE_REG_5, 800 MOD_0FAE_REG_6, 801 MOD_0FAE_REG_7, 802 MOD_0FB2, 803 MOD_0FB4, 804 MOD_0FB5, 805 MOD_0FC7_REG_3, 806 MOD_0FC7_REG_4, 807 MOD_0FC7_REG_5, 808 MOD_0FC7_REG_6, 809 MOD_0FC7_REG_7, 810 MOD_0FD7, 811 MOD_0FE7_PREFIX_2, 812 MOD_0FF0_PREFIX_3, 813 MOD_0F382A_PREFIX_2, 814 MOD_62_32BIT, 815 MOD_C4_32BIT, 816 MOD_C5_32BIT, 817 MOD_VEX_0F12_PREFIX_0, 818 MOD_VEX_0F13, 819 MOD_VEX_0F16_PREFIX_0, 820 MOD_VEX_0F17, 821 MOD_VEX_0F2B, 822 MOD_VEX_0F50, 823 MOD_VEX_0F71_REG_2, 824 MOD_VEX_0F71_REG_4, 825 MOD_VEX_0F71_REG_6, 826 MOD_VEX_0F72_REG_2, 827 MOD_VEX_0F72_REG_4, 828 MOD_VEX_0F72_REG_6, 829 MOD_VEX_0F73_REG_2, 830 MOD_VEX_0F73_REG_3, 831 MOD_VEX_0F73_REG_6, 832 MOD_VEX_0F73_REG_7, 833 MOD_VEX_0FAE_REG_2, 834 MOD_VEX_0FAE_REG_3, 835 MOD_VEX_0FD7_PREFIX_2, 836 MOD_VEX_0FE7_PREFIX_2, 837 MOD_VEX_0FF0_PREFIX_3, 838 MOD_VEX_0F381A_PREFIX_2, 839 MOD_VEX_0F382A_PREFIX_2, 840 MOD_VEX_0F382C_PREFIX_2, 841 MOD_VEX_0F382D_PREFIX_2, 842 MOD_VEX_0F382E_PREFIX_2, 843 MOD_VEX_0F382F_PREFIX_2, 844 MOD_VEX_0F385A_PREFIX_2, 845 MOD_VEX_0F388C_PREFIX_2, 846 MOD_VEX_0F388E_PREFIX_2, 847 848 MOD_EVEX_0F10_PREFIX_1, 849 MOD_EVEX_0F10_PREFIX_3, 850 MOD_EVEX_0F11_PREFIX_1, 851 MOD_EVEX_0F11_PREFIX_3, 852 MOD_EVEX_0F12_PREFIX_0, 853 MOD_EVEX_0F16_PREFIX_0, 854 MOD_EVEX_0F38C6_REG_1, 855 MOD_EVEX_0F38C6_REG_2, 856 MOD_EVEX_0F38C6_REG_5, 857 MOD_EVEX_0F38C6_REG_6, 858 MOD_EVEX_0F38C7_REG_1, 859 MOD_EVEX_0F38C7_REG_2, 860 MOD_EVEX_0F38C7_REG_5, 861 MOD_EVEX_0F38C7_REG_6 862 }; 863 864 enum 865 { 866 RM_C6_REG_7 = 0, 867 RM_C7_REG_7, 868 RM_0F01_REG_0, 869 RM_0F01_REG_1, 870 RM_0F01_REG_2, 871 RM_0F01_REG_3, 872 RM_0F01_REG_7, 873 RM_0FAE_REG_5, 874 RM_0FAE_REG_6, 875 RM_0FAE_REG_7 876 }; 877 878 enum 879 { 880 PREFIX_90 = 0, 881 PREFIX_0F10, 882 PREFIX_0F11, 883 PREFIX_0F12, 884 PREFIX_0F16, 885 PREFIX_0F1A, 886 PREFIX_0F1B, 887 PREFIX_0F2A, 888 PREFIX_0F2B, 889 PREFIX_0F2C, 890 PREFIX_0F2D, 891 PREFIX_0F2E, 892 PREFIX_0F2F, 893 PREFIX_0F51, 894 PREFIX_0F52, 895 PREFIX_0F53, 896 PREFIX_0F58, 897 PREFIX_0F59, 898 PREFIX_0F5A, 899 PREFIX_0F5B, 900 PREFIX_0F5C, 901 PREFIX_0F5D, 902 PREFIX_0F5E, 903 PREFIX_0F5F, 904 PREFIX_0F60, 905 PREFIX_0F61, 906 PREFIX_0F62, 907 PREFIX_0F6C, 908 PREFIX_0F6D, 909 PREFIX_0F6F, 910 PREFIX_0F70, 911 PREFIX_0F73_REG_3, 912 PREFIX_0F73_REG_7, 913 PREFIX_0F78, 914 PREFIX_0F79, 915 PREFIX_0F7C, 916 PREFIX_0F7D, 917 PREFIX_0F7E, 918 PREFIX_0F7F, 919 PREFIX_0FAE_REG_0, 920 PREFIX_0FAE_REG_1, 921 PREFIX_0FAE_REG_2, 922 PREFIX_0FAE_REG_3, 923 PREFIX_0FAE_REG_6, 924 PREFIX_0FAE_REG_7, 925 PREFIX_RM_0_0FAE_REG_7, 926 PREFIX_0FB8, 927 PREFIX_0FBC, 928 PREFIX_0FBD, 929 PREFIX_0FC2, 930 PREFIX_0FC3, 931 PREFIX_MOD_0_0FC7_REG_6, 932 PREFIX_MOD_3_0FC7_REG_6, 933 PREFIX_MOD_3_0FC7_REG_7, 934 PREFIX_0FD0, 935 PREFIX_0FD6, 936 PREFIX_0FE6, 937 PREFIX_0FE7, 938 PREFIX_0FF0, 939 PREFIX_0FF7, 940 PREFIX_0F3810, 941 PREFIX_0F3814, 942 PREFIX_0F3815, 943 PREFIX_0F3817, 944 PREFIX_0F3820, 945 PREFIX_0F3821, 946 PREFIX_0F3822, 947 PREFIX_0F3823, 948 PREFIX_0F3824, 949 PREFIX_0F3825, 950 PREFIX_0F3828, 951 PREFIX_0F3829, 952 PREFIX_0F382A, 953 PREFIX_0F382B, 954 PREFIX_0F3830, 955 PREFIX_0F3831, 956 PREFIX_0F3832, 957 PREFIX_0F3833, 958 PREFIX_0F3834, 959 PREFIX_0F3835, 960 PREFIX_0F3837, 961 PREFIX_0F3838, 962 PREFIX_0F3839, 963 PREFIX_0F383A, 964 PREFIX_0F383B, 965 PREFIX_0F383C, 966 PREFIX_0F383D, 967 PREFIX_0F383E, 968 PREFIX_0F383F, 969 PREFIX_0F3840, 970 PREFIX_0F3841, 971 PREFIX_0F3880, 972 PREFIX_0F3881, 973 PREFIX_0F3882, 974 PREFIX_0F38C8, 975 PREFIX_0F38C9, 976 PREFIX_0F38CA, 977 PREFIX_0F38CB, 978 PREFIX_0F38CC, 979 PREFIX_0F38CD, 980 PREFIX_0F38DB, 981 PREFIX_0F38DC, 982 PREFIX_0F38DD, 983 PREFIX_0F38DE, 984 PREFIX_0F38DF, 985 PREFIX_0F38F0, 986 PREFIX_0F38F1, 987 PREFIX_0F38F6, 988 PREFIX_0F3A08, 989 PREFIX_0F3A09, 990 PREFIX_0F3A0A, 991 PREFIX_0F3A0B, 992 PREFIX_0F3A0C, 993 PREFIX_0F3A0D, 994 PREFIX_0F3A0E, 995 PREFIX_0F3A14, 996 PREFIX_0F3A15, 997 PREFIX_0F3A16, 998 PREFIX_0F3A17, 999 PREFIX_0F3A20, 1000 PREFIX_0F3A21, 1001 PREFIX_0F3A22, 1002 PREFIX_0F3A40, 1003 PREFIX_0F3A41, 1004 PREFIX_0F3A42, 1005 PREFIX_0F3A44, 1006 PREFIX_0F3A60, 1007 PREFIX_0F3A61, 1008 PREFIX_0F3A62, 1009 PREFIX_0F3A63, 1010 PREFIX_0F3ACC, 1011 PREFIX_0F3ADF, 1012 PREFIX_VEX_0F10, 1013 PREFIX_VEX_0F11, 1014 PREFIX_VEX_0F12, 1015 PREFIX_VEX_0F16, 1016 PREFIX_VEX_0F2A, 1017 PREFIX_VEX_0F2C, 1018 PREFIX_VEX_0F2D, 1019 PREFIX_VEX_0F2E, 1020 PREFIX_VEX_0F2F, 1021 PREFIX_VEX_0F41, 1022 PREFIX_VEX_0F42, 1023 PREFIX_VEX_0F44, 1024 PREFIX_VEX_0F45, 1025 PREFIX_VEX_0F46, 1026 PREFIX_VEX_0F47, 1027 PREFIX_VEX_0F4A, 1028 PREFIX_VEX_0F4B, 1029 PREFIX_VEX_0F51, 1030 PREFIX_VEX_0F52, 1031 PREFIX_VEX_0F53, 1032 PREFIX_VEX_0F58, 1033 PREFIX_VEX_0F59, 1034 PREFIX_VEX_0F5A, 1035 PREFIX_VEX_0F5B, 1036 PREFIX_VEX_0F5C, 1037 PREFIX_VEX_0F5D, 1038 PREFIX_VEX_0F5E, 1039 PREFIX_VEX_0F5F, 1040 PREFIX_VEX_0F60, 1041 PREFIX_VEX_0F61, 1042 PREFIX_VEX_0F62, 1043 PREFIX_VEX_0F63, 1044 PREFIX_VEX_0F64, 1045 PREFIX_VEX_0F65, 1046 PREFIX_VEX_0F66, 1047 PREFIX_VEX_0F67, 1048 PREFIX_VEX_0F68, 1049 PREFIX_VEX_0F69, 1050 PREFIX_VEX_0F6A, 1051 PREFIX_VEX_0F6B, 1052 PREFIX_VEX_0F6C, 1053 PREFIX_VEX_0F6D, 1054 PREFIX_VEX_0F6E, 1055 PREFIX_VEX_0F6F, 1056 PREFIX_VEX_0F70, 1057 PREFIX_VEX_0F71_REG_2, 1058 PREFIX_VEX_0F71_REG_4, 1059 PREFIX_VEX_0F71_REG_6, 1060 PREFIX_VEX_0F72_REG_2, 1061 PREFIX_VEX_0F72_REG_4, 1062 PREFIX_VEX_0F72_REG_6, 1063 PREFIX_VEX_0F73_REG_2, 1064 PREFIX_VEX_0F73_REG_3, 1065 PREFIX_VEX_0F73_REG_6, 1066 PREFIX_VEX_0F73_REG_7, 1067 PREFIX_VEX_0F74, 1068 PREFIX_VEX_0F75, 1069 PREFIX_VEX_0F76, 1070 PREFIX_VEX_0F77, 1071 PREFIX_VEX_0F7C, 1072 PREFIX_VEX_0F7D, 1073 PREFIX_VEX_0F7E, 1074 PREFIX_VEX_0F7F, 1075 PREFIX_VEX_0F90, 1076 PREFIX_VEX_0F91, 1077 PREFIX_VEX_0F92, 1078 PREFIX_VEX_0F93, 1079 PREFIX_VEX_0F98, 1080 PREFIX_VEX_0F99, 1081 PREFIX_VEX_0FC2, 1082 PREFIX_VEX_0FC4, 1083 PREFIX_VEX_0FC5, 1084 PREFIX_VEX_0FD0, 1085 PREFIX_VEX_0FD1, 1086 PREFIX_VEX_0FD2, 1087 PREFIX_VEX_0FD3, 1088 PREFIX_VEX_0FD4, 1089 PREFIX_VEX_0FD5, 1090 PREFIX_VEX_0FD6, 1091 PREFIX_VEX_0FD7, 1092 PREFIX_VEX_0FD8, 1093 PREFIX_VEX_0FD9, 1094 PREFIX_VEX_0FDA, 1095 PREFIX_VEX_0FDB, 1096 PREFIX_VEX_0FDC, 1097 PREFIX_VEX_0FDD, 1098 PREFIX_VEX_0FDE, 1099 PREFIX_VEX_0FDF, 1100 PREFIX_VEX_0FE0, 1101 PREFIX_VEX_0FE1, 1102 PREFIX_VEX_0FE2, 1103 PREFIX_VEX_0FE3, 1104 PREFIX_VEX_0FE4, 1105 PREFIX_VEX_0FE5, 1106 PREFIX_VEX_0FE6, 1107 PREFIX_VEX_0FE7, 1108 PREFIX_VEX_0FE8, 1109 PREFIX_VEX_0FE9, 1110 PREFIX_VEX_0FEA, 1111 PREFIX_VEX_0FEB, 1112 PREFIX_VEX_0FEC, 1113 PREFIX_VEX_0FED, 1114 PREFIX_VEX_0FEE, 1115 PREFIX_VEX_0FEF, 1116 PREFIX_VEX_0FF0, 1117 PREFIX_VEX_0FF1, 1118 PREFIX_VEX_0FF2, 1119 PREFIX_VEX_0FF3, 1120 PREFIX_VEX_0FF4, 1121 PREFIX_VEX_0FF5, 1122 PREFIX_VEX_0FF6, 1123 PREFIX_VEX_0FF7, 1124 PREFIX_VEX_0FF8, 1125 PREFIX_VEX_0FF9, 1126 PREFIX_VEX_0FFA, 1127 PREFIX_VEX_0FFB, 1128 PREFIX_VEX_0FFC, 1129 PREFIX_VEX_0FFD, 1130 PREFIX_VEX_0FFE, 1131 PREFIX_VEX_0F3800, 1132 PREFIX_VEX_0F3801, 1133 PREFIX_VEX_0F3802, 1134 PREFIX_VEX_0F3803, 1135 PREFIX_VEX_0F3804, 1136 PREFIX_VEX_0F3805, 1137 PREFIX_VEX_0F3806, 1138 PREFIX_VEX_0F3807, 1139 PREFIX_VEX_0F3808, 1140 PREFIX_VEX_0F3809, 1141 PREFIX_VEX_0F380A, 1142 PREFIX_VEX_0F380B, 1143 PREFIX_VEX_0F380C, 1144 PREFIX_VEX_0F380D, 1145 PREFIX_VEX_0F380E, 1146 PREFIX_VEX_0F380F, 1147 PREFIX_VEX_0F3813, 1148 PREFIX_VEX_0F3816, 1149 PREFIX_VEX_0F3817, 1150 PREFIX_VEX_0F3818, 1151 PREFIX_VEX_0F3819, 1152 PREFIX_VEX_0F381A, 1153 PREFIX_VEX_0F381C, 1154 PREFIX_VEX_0F381D, 1155 PREFIX_VEX_0F381E, 1156 PREFIX_VEX_0F3820, 1157 PREFIX_VEX_0F3821, 1158 PREFIX_VEX_0F3822, 1159 PREFIX_VEX_0F3823, 1160 PREFIX_VEX_0F3824, 1161 PREFIX_VEX_0F3825, 1162 PREFIX_VEX_0F3828, 1163 PREFIX_VEX_0F3829, 1164 PREFIX_VEX_0F382A, 1165 PREFIX_VEX_0F382B, 1166 PREFIX_VEX_0F382C, 1167 PREFIX_VEX_0F382D, 1168 PREFIX_VEX_0F382E, 1169 PREFIX_VEX_0F382F, 1170 PREFIX_VEX_0F3830, 1171 PREFIX_VEX_0F3831, 1172 PREFIX_VEX_0F3832, 1173 PREFIX_VEX_0F3833, 1174 PREFIX_VEX_0F3834, 1175 PREFIX_VEX_0F3835, 1176 PREFIX_VEX_0F3836, 1177 PREFIX_VEX_0F3837, 1178 PREFIX_VEX_0F3838, 1179 PREFIX_VEX_0F3839, 1180 PREFIX_VEX_0F383A, 1181 PREFIX_VEX_0F383B, 1182 PREFIX_VEX_0F383C, 1183 PREFIX_VEX_0F383D, 1184 PREFIX_VEX_0F383E, 1185 PREFIX_VEX_0F383F, 1186 PREFIX_VEX_0F3840, 1187 PREFIX_VEX_0F3841, 1188 PREFIX_VEX_0F3845, 1189 PREFIX_VEX_0F3846, 1190 PREFIX_VEX_0F3847, 1191 PREFIX_VEX_0F3858, 1192 PREFIX_VEX_0F3859, 1193 PREFIX_VEX_0F385A, 1194 PREFIX_VEX_0F3878, 1195 PREFIX_VEX_0F3879, 1196 PREFIX_VEX_0F388C, 1197 PREFIX_VEX_0F388E, 1198 PREFIX_VEX_0F3890, 1199 PREFIX_VEX_0F3891, 1200 PREFIX_VEX_0F3892, 1201 PREFIX_VEX_0F3893, 1202 PREFIX_VEX_0F3896, 1203 PREFIX_VEX_0F3897, 1204 PREFIX_VEX_0F3898, 1205 PREFIX_VEX_0F3899, 1206 PREFIX_VEX_0F389A, 1207 PREFIX_VEX_0F389B, 1208 PREFIX_VEX_0F389C, 1209 PREFIX_VEX_0F389D, 1210 PREFIX_VEX_0F389E, 1211 PREFIX_VEX_0F389F, 1212 PREFIX_VEX_0F38A6, 1213 PREFIX_VEX_0F38A7, 1214 PREFIX_VEX_0F38A8, 1215 PREFIX_VEX_0F38A9, 1216 PREFIX_VEX_0F38AA, 1217 PREFIX_VEX_0F38AB, 1218 PREFIX_VEX_0F38AC, 1219 PREFIX_VEX_0F38AD, 1220 PREFIX_VEX_0F38AE, 1221 PREFIX_VEX_0F38AF, 1222 PREFIX_VEX_0F38B6, 1223 PREFIX_VEX_0F38B7, 1224 PREFIX_VEX_0F38B8, 1225 PREFIX_VEX_0F38B9, 1226 PREFIX_VEX_0F38BA, 1227 PREFIX_VEX_0F38BB, 1228 PREFIX_VEX_0F38BC, 1229 PREFIX_VEX_0F38BD, 1230 PREFIX_VEX_0F38BE, 1231 PREFIX_VEX_0F38BF, 1232 PREFIX_VEX_0F38DB, 1233 PREFIX_VEX_0F38DC, 1234 PREFIX_VEX_0F38DD, 1235 PREFIX_VEX_0F38DE, 1236 PREFIX_VEX_0F38DF, 1237 PREFIX_VEX_0F38F2, 1238 PREFIX_VEX_0F38F3_REG_1, 1239 PREFIX_VEX_0F38F3_REG_2, 1240 PREFIX_VEX_0F38F3_REG_3, 1241 PREFIX_VEX_0F38F5, 1242 PREFIX_VEX_0F38F6, 1243 PREFIX_VEX_0F38F7, 1244 PREFIX_VEX_0F3A00, 1245 PREFIX_VEX_0F3A01, 1246 PREFIX_VEX_0F3A02, 1247 PREFIX_VEX_0F3A04, 1248 PREFIX_VEX_0F3A05, 1249 PREFIX_VEX_0F3A06, 1250 PREFIX_VEX_0F3A08, 1251 PREFIX_VEX_0F3A09, 1252 PREFIX_VEX_0F3A0A, 1253 PREFIX_VEX_0F3A0B, 1254 PREFIX_VEX_0F3A0C, 1255 PREFIX_VEX_0F3A0D, 1256 PREFIX_VEX_0F3A0E, 1257 PREFIX_VEX_0F3A0F, 1258 PREFIX_VEX_0F3A14, 1259 PREFIX_VEX_0F3A15, 1260 PREFIX_VEX_0F3A16, 1261 PREFIX_VEX_0F3A17, 1262 PREFIX_VEX_0F3A18, 1263 PREFIX_VEX_0F3A19, 1264 PREFIX_VEX_0F3A1D, 1265 PREFIX_VEX_0F3A20, 1266 PREFIX_VEX_0F3A21, 1267 PREFIX_VEX_0F3A22, 1268 PREFIX_VEX_0F3A30, 1269 PREFIX_VEX_0F3A31, 1270 PREFIX_VEX_0F3A32, 1271 PREFIX_VEX_0F3A33, 1272 PREFIX_VEX_0F3A38, 1273 PREFIX_VEX_0F3A39, 1274 PREFIX_VEX_0F3A40, 1275 PREFIX_VEX_0F3A41, 1276 PREFIX_VEX_0F3A42, 1277 PREFIX_VEX_0F3A44, 1278 PREFIX_VEX_0F3A46, 1279 PREFIX_VEX_0F3A48, 1280 PREFIX_VEX_0F3A49, 1281 PREFIX_VEX_0F3A4A, 1282 PREFIX_VEX_0F3A4B, 1283 PREFIX_VEX_0F3A4C, 1284 PREFIX_VEX_0F3A5C, 1285 PREFIX_VEX_0F3A5D, 1286 PREFIX_VEX_0F3A5E, 1287 PREFIX_VEX_0F3A5F, 1288 PREFIX_VEX_0F3A60, 1289 PREFIX_VEX_0F3A61, 1290 PREFIX_VEX_0F3A62, 1291 PREFIX_VEX_0F3A63, 1292 PREFIX_VEX_0F3A68, 1293 PREFIX_VEX_0F3A69, 1294 PREFIX_VEX_0F3A6A, 1295 PREFIX_VEX_0F3A6B, 1296 PREFIX_VEX_0F3A6C, 1297 PREFIX_VEX_0F3A6D, 1298 PREFIX_VEX_0F3A6E, 1299 PREFIX_VEX_0F3A6F, 1300 PREFIX_VEX_0F3A78, 1301 PREFIX_VEX_0F3A79, 1302 PREFIX_VEX_0F3A7A, 1303 PREFIX_VEX_0F3A7B, 1304 PREFIX_VEX_0F3A7C, 1305 PREFIX_VEX_0F3A7D, 1306 PREFIX_VEX_0F3A7E, 1307 PREFIX_VEX_0F3A7F, 1308 PREFIX_VEX_0F3ADF, 1309 PREFIX_VEX_0F3AF0, 1310 1311 PREFIX_EVEX_0F10, 1312 PREFIX_EVEX_0F11, 1313 PREFIX_EVEX_0F12, 1314 PREFIX_EVEX_0F13, 1315 PREFIX_EVEX_0F14, 1316 PREFIX_EVEX_0F15, 1317 PREFIX_EVEX_0F16, 1318 PREFIX_EVEX_0F17, 1319 PREFIX_EVEX_0F28, 1320 PREFIX_EVEX_0F29, 1321 PREFIX_EVEX_0F2A, 1322 PREFIX_EVEX_0F2B, 1323 PREFIX_EVEX_0F2C, 1324 PREFIX_EVEX_0F2D, 1325 PREFIX_EVEX_0F2E, 1326 PREFIX_EVEX_0F2F, 1327 PREFIX_EVEX_0F51, 1328 PREFIX_EVEX_0F54, 1329 PREFIX_EVEX_0F55, 1330 PREFIX_EVEX_0F56, 1331 PREFIX_EVEX_0F57, 1332 PREFIX_EVEX_0F58, 1333 PREFIX_EVEX_0F59, 1334 PREFIX_EVEX_0F5A, 1335 PREFIX_EVEX_0F5B, 1336 PREFIX_EVEX_0F5C, 1337 PREFIX_EVEX_0F5D, 1338 PREFIX_EVEX_0F5E, 1339 PREFIX_EVEX_0F5F, 1340 PREFIX_EVEX_0F60, 1341 PREFIX_EVEX_0F61, 1342 PREFIX_EVEX_0F62, 1343 PREFIX_EVEX_0F63, 1344 PREFIX_EVEX_0F64, 1345 PREFIX_EVEX_0F65, 1346 PREFIX_EVEX_0F66, 1347 PREFIX_EVEX_0F67, 1348 PREFIX_EVEX_0F68, 1349 PREFIX_EVEX_0F69, 1350 PREFIX_EVEX_0F6A, 1351 PREFIX_EVEX_0F6B, 1352 PREFIX_EVEX_0F6C, 1353 PREFIX_EVEX_0F6D, 1354 PREFIX_EVEX_0F6E, 1355 PREFIX_EVEX_0F6F, 1356 PREFIX_EVEX_0F70, 1357 PREFIX_EVEX_0F71_REG_2, 1358 PREFIX_EVEX_0F71_REG_4, 1359 PREFIX_EVEX_0F71_REG_6, 1360 PREFIX_EVEX_0F72_REG_0, 1361 PREFIX_EVEX_0F72_REG_1, 1362 PREFIX_EVEX_0F72_REG_2, 1363 PREFIX_EVEX_0F72_REG_4, 1364 PREFIX_EVEX_0F72_REG_6, 1365 PREFIX_EVEX_0F73_REG_2, 1366 PREFIX_EVEX_0F73_REG_3, 1367 PREFIX_EVEX_0F73_REG_6, 1368 PREFIX_EVEX_0F73_REG_7, 1369 PREFIX_EVEX_0F74, 1370 PREFIX_EVEX_0F75, 1371 PREFIX_EVEX_0F76, 1372 PREFIX_EVEX_0F78, 1373 PREFIX_EVEX_0F79, 1374 PREFIX_EVEX_0F7A, 1375 PREFIX_EVEX_0F7B, 1376 PREFIX_EVEX_0F7E, 1377 PREFIX_EVEX_0F7F, 1378 PREFIX_EVEX_0FC2, 1379 PREFIX_EVEX_0FC4, 1380 PREFIX_EVEX_0FC5, 1381 PREFIX_EVEX_0FC6, 1382 PREFIX_EVEX_0FD1, 1383 PREFIX_EVEX_0FD2, 1384 PREFIX_EVEX_0FD3, 1385 PREFIX_EVEX_0FD4, 1386 PREFIX_EVEX_0FD5, 1387 PREFIX_EVEX_0FD6, 1388 PREFIX_EVEX_0FD8, 1389 PREFIX_EVEX_0FD9, 1390 PREFIX_EVEX_0FDA, 1391 PREFIX_EVEX_0FDB, 1392 PREFIX_EVEX_0FDC, 1393 PREFIX_EVEX_0FDD, 1394 PREFIX_EVEX_0FDE, 1395 PREFIX_EVEX_0FDF, 1396 PREFIX_EVEX_0FE0, 1397 PREFIX_EVEX_0FE1, 1398 PREFIX_EVEX_0FE2, 1399 PREFIX_EVEX_0FE3, 1400 PREFIX_EVEX_0FE4, 1401 PREFIX_EVEX_0FE5, 1402 PREFIX_EVEX_0FE6, 1403 PREFIX_EVEX_0FE7, 1404 PREFIX_EVEX_0FE8, 1405 PREFIX_EVEX_0FE9, 1406 PREFIX_EVEX_0FEA, 1407 PREFIX_EVEX_0FEB, 1408 PREFIX_EVEX_0FEC, 1409 PREFIX_EVEX_0FED, 1410 PREFIX_EVEX_0FEE, 1411 PREFIX_EVEX_0FEF, 1412 PREFIX_EVEX_0FF1, 1413 PREFIX_EVEX_0FF2, 1414 PREFIX_EVEX_0FF3, 1415 PREFIX_EVEX_0FF4, 1416 PREFIX_EVEX_0FF5, 1417 PREFIX_EVEX_0FF6, 1418 PREFIX_EVEX_0FF8, 1419 PREFIX_EVEX_0FF9, 1420 PREFIX_EVEX_0FFA, 1421 PREFIX_EVEX_0FFB, 1422 PREFIX_EVEX_0FFC, 1423 PREFIX_EVEX_0FFD, 1424 PREFIX_EVEX_0FFE, 1425 PREFIX_EVEX_0F3800, 1426 PREFIX_EVEX_0F3804, 1427 PREFIX_EVEX_0F380B, 1428 PREFIX_EVEX_0F380C, 1429 PREFIX_EVEX_0F380D, 1430 PREFIX_EVEX_0F3810, 1431 PREFIX_EVEX_0F3811, 1432 PREFIX_EVEX_0F3812, 1433 PREFIX_EVEX_0F3813, 1434 PREFIX_EVEX_0F3814, 1435 PREFIX_EVEX_0F3815, 1436 PREFIX_EVEX_0F3816, 1437 PREFIX_EVEX_0F3818, 1438 PREFIX_EVEX_0F3819, 1439 PREFIX_EVEX_0F381A, 1440 PREFIX_EVEX_0F381B, 1441 PREFIX_EVEX_0F381C, 1442 PREFIX_EVEX_0F381D, 1443 PREFIX_EVEX_0F381E, 1444 PREFIX_EVEX_0F381F, 1445 PREFIX_EVEX_0F3820, 1446 PREFIX_EVEX_0F3821, 1447 PREFIX_EVEX_0F3822, 1448 PREFIX_EVEX_0F3823, 1449 PREFIX_EVEX_0F3824, 1450 PREFIX_EVEX_0F3825, 1451 PREFIX_EVEX_0F3826, 1452 PREFIX_EVEX_0F3827, 1453 PREFIX_EVEX_0F3828, 1454 PREFIX_EVEX_0F3829, 1455 PREFIX_EVEX_0F382A, 1456 PREFIX_EVEX_0F382B, 1457 PREFIX_EVEX_0F382C, 1458 PREFIX_EVEX_0F382D, 1459 PREFIX_EVEX_0F3830, 1460 PREFIX_EVEX_0F3831, 1461 PREFIX_EVEX_0F3832, 1462 PREFIX_EVEX_0F3833, 1463 PREFIX_EVEX_0F3834, 1464 PREFIX_EVEX_0F3835, 1465 PREFIX_EVEX_0F3836, 1466 PREFIX_EVEX_0F3837, 1467 PREFIX_EVEX_0F3838, 1468 PREFIX_EVEX_0F3839, 1469 PREFIX_EVEX_0F383A, 1470 PREFIX_EVEX_0F383B, 1471 PREFIX_EVEX_0F383C, 1472 PREFIX_EVEX_0F383D, 1473 PREFIX_EVEX_0F383E, 1474 PREFIX_EVEX_0F383F, 1475 PREFIX_EVEX_0F3840, 1476 PREFIX_EVEX_0F3842, 1477 PREFIX_EVEX_0F3843, 1478 PREFIX_EVEX_0F3844, 1479 PREFIX_EVEX_0F3845, 1480 PREFIX_EVEX_0F3846, 1481 PREFIX_EVEX_0F3847, 1482 PREFIX_EVEX_0F384C, 1483 PREFIX_EVEX_0F384D, 1484 PREFIX_EVEX_0F384E, 1485 PREFIX_EVEX_0F384F, 1486 PREFIX_EVEX_0F3858, 1487 PREFIX_EVEX_0F3859, 1488 PREFIX_EVEX_0F385A, 1489 PREFIX_EVEX_0F385B, 1490 PREFIX_EVEX_0F3864, 1491 PREFIX_EVEX_0F3865, 1492 PREFIX_EVEX_0F3866, 1493 PREFIX_EVEX_0F3875, 1494 PREFIX_EVEX_0F3876, 1495 PREFIX_EVEX_0F3877, 1496 PREFIX_EVEX_0F3878, 1497 PREFIX_EVEX_0F3879, 1498 PREFIX_EVEX_0F387A, 1499 PREFIX_EVEX_0F387B, 1500 PREFIX_EVEX_0F387C, 1501 PREFIX_EVEX_0F387D, 1502 PREFIX_EVEX_0F387E, 1503 PREFIX_EVEX_0F387F, 1504 PREFIX_EVEX_0F3883, 1505 PREFIX_EVEX_0F3888, 1506 PREFIX_EVEX_0F3889, 1507 PREFIX_EVEX_0F388A, 1508 PREFIX_EVEX_0F388B, 1509 PREFIX_EVEX_0F388D, 1510 PREFIX_EVEX_0F3890, 1511 PREFIX_EVEX_0F3891, 1512 PREFIX_EVEX_0F3892, 1513 PREFIX_EVEX_0F3893, 1514 PREFIX_EVEX_0F3896, 1515 PREFIX_EVEX_0F3897, 1516 PREFIX_EVEX_0F3898, 1517 PREFIX_EVEX_0F3899, 1518 PREFIX_EVEX_0F389A, 1519 PREFIX_EVEX_0F389B, 1520 PREFIX_EVEX_0F389C, 1521 PREFIX_EVEX_0F389D, 1522 PREFIX_EVEX_0F389E, 1523 PREFIX_EVEX_0F389F, 1524 PREFIX_EVEX_0F38A0, 1525 PREFIX_EVEX_0F38A1, 1526 PREFIX_EVEX_0F38A2, 1527 PREFIX_EVEX_0F38A3, 1528 PREFIX_EVEX_0F38A6, 1529 PREFIX_EVEX_0F38A7, 1530 PREFIX_EVEX_0F38A8, 1531 PREFIX_EVEX_0F38A9, 1532 PREFIX_EVEX_0F38AA, 1533 PREFIX_EVEX_0F38AB, 1534 PREFIX_EVEX_0F38AC, 1535 PREFIX_EVEX_0F38AD, 1536 PREFIX_EVEX_0F38AE, 1537 PREFIX_EVEX_0F38AF, 1538 PREFIX_EVEX_0F38B4, 1539 PREFIX_EVEX_0F38B5, 1540 PREFIX_EVEX_0F38B6, 1541 PREFIX_EVEX_0F38B7, 1542 PREFIX_EVEX_0F38B8, 1543 PREFIX_EVEX_0F38B9, 1544 PREFIX_EVEX_0F38BA, 1545 PREFIX_EVEX_0F38BB, 1546 PREFIX_EVEX_0F38BC, 1547 PREFIX_EVEX_0F38BD, 1548 PREFIX_EVEX_0F38BE, 1549 PREFIX_EVEX_0F38BF, 1550 PREFIX_EVEX_0F38C4, 1551 PREFIX_EVEX_0F38C6_REG_1, 1552 PREFIX_EVEX_0F38C6_REG_2, 1553 PREFIX_EVEX_0F38C6_REG_5, 1554 PREFIX_EVEX_0F38C6_REG_6, 1555 PREFIX_EVEX_0F38C7_REG_1, 1556 PREFIX_EVEX_0F38C7_REG_2, 1557 PREFIX_EVEX_0F38C7_REG_5, 1558 PREFIX_EVEX_0F38C7_REG_6, 1559 PREFIX_EVEX_0F38C8, 1560 PREFIX_EVEX_0F38CA, 1561 PREFIX_EVEX_0F38CB, 1562 PREFIX_EVEX_0F38CC, 1563 PREFIX_EVEX_0F38CD, 1564 1565 PREFIX_EVEX_0F3A00, 1566 PREFIX_EVEX_0F3A01, 1567 PREFIX_EVEX_0F3A03, 1568 PREFIX_EVEX_0F3A04, 1569 PREFIX_EVEX_0F3A05, 1570 PREFIX_EVEX_0F3A08, 1571 PREFIX_EVEX_0F3A09, 1572 PREFIX_EVEX_0F3A0A, 1573 PREFIX_EVEX_0F3A0B, 1574 PREFIX_EVEX_0F3A0F, 1575 PREFIX_EVEX_0F3A14, 1576 PREFIX_EVEX_0F3A15, 1577 PREFIX_EVEX_0F3A16, 1578 PREFIX_EVEX_0F3A17, 1579 PREFIX_EVEX_0F3A18, 1580 PREFIX_EVEX_0F3A19, 1581 PREFIX_EVEX_0F3A1A, 1582 PREFIX_EVEX_0F3A1B, 1583 PREFIX_EVEX_0F3A1D, 1584 PREFIX_EVEX_0F3A1E, 1585 PREFIX_EVEX_0F3A1F, 1586 PREFIX_EVEX_0F3A20, 1587 PREFIX_EVEX_0F3A21, 1588 PREFIX_EVEX_0F3A22, 1589 PREFIX_EVEX_0F3A23, 1590 PREFIX_EVEX_0F3A25, 1591 PREFIX_EVEX_0F3A26, 1592 PREFIX_EVEX_0F3A27, 1593 PREFIX_EVEX_0F3A38, 1594 PREFIX_EVEX_0F3A39, 1595 PREFIX_EVEX_0F3A3A, 1596 PREFIX_EVEX_0F3A3B, 1597 PREFIX_EVEX_0F3A3E, 1598 PREFIX_EVEX_0F3A3F, 1599 PREFIX_EVEX_0F3A42, 1600 PREFIX_EVEX_0F3A43, 1601 PREFIX_EVEX_0F3A50, 1602 PREFIX_EVEX_0F3A51, 1603 PREFIX_EVEX_0F3A54, 1604 PREFIX_EVEX_0F3A55, 1605 PREFIX_EVEX_0F3A56, 1606 PREFIX_EVEX_0F3A57, 1607 PREFIX_EVEX_0F3A66, 1608 PREFIX_EVEX_0F3A67 1609 }; 1610 1611 enum 1612 { 1613 X86_64_06 = 0, 1614 X86_64_07, 1615 X86_64_0D, 1616 X86_64_16, 1617 X86_64_17, 1618 X86_64_1E, 1619 X86_64_1F, 1620 X86_64_27, 1621 X86_64_2F, 1622 X86_64_37, 1623 X86_64_3F, 1624 X86_64_60, 1625 X86_64_61, 1626 X86_64_62, 1627 X86_64_63, 1628 X86_64_6D, 1629 X86_64_6F, 1630 X86_64_9A, 1631 X86_64_C4, 1632 X86_64_C5, 1633 X86_64_CE, 1634 X86_64_D4, 1635 X86_64_D5, 1636 X86_64_E8, 1637 X86_64_E9, 1638 X86_64_EA, 1639 X86_64_0F01_REG_0, 1640 X86_64_0F01_REG_1, 1641 X86_64_0F01_REG_2, 1642 X86_64_0F01_REG_3 1643 }; 1644 1645 enum 1646 { 1647 THREE_BYTE_0F38 = 0, 1648 THREE_BYTE_0F3A, 1649 THREE_BYTE_0F7A 1650 }; 1651 1652 enum 1653 { 1654 XOP_08 = 0, 1655 XOP_09, 1656 XOP_0A 1657 }; 1658 1659 enum 1660 { 1661 VEX_0F = 0, 1662 VEX_0F38, 1663 VEX_0F3A 1664 }; 1665 1666 enum 1667 { 1668 EVEX_0F = 0, 1669 EVEX_0F38, 1670 EVEX_0F3A 1671 }; 1672 1673 enum 1674 { 1675 VEX_LEN_0F10_P_1 = 0, 1676 VEX_LEN_0F10_P_3, 1677 VEX_LEN_0F11_P_1, 1678 VEX_LEN_0F11_P_3, 1679 VEX_LEN_0F12_P_0_M_0, 1680 VEX_LEN_0F12_P_0_M_1, 1681 VEX_LEN_0F12_P_2, 1682 VEX_LEN_0F13_M_0, 1683 VEX_LEN_0F16_P_0_M_0, 1684 VEX_LEN_0F16_P_0_M_1, 1685 VEX_LEN_0F16_P_2, 1686 VEX_LEN_0F17_M_0, 1687 VEX_LEN_0F2A_P_1, 1688 VEX_LEN_0F2A_P_3, 1689 VEX_LEN_0F2C_P_1, 1690 VEX_LEN_0F2C_P_3, 1691 VEX_LEN_0F2D_P_1, 1692 VEX_LEN_0F2D_P_3, 1693 VEX_LEN_0F2E_P_0, 1694 VEX_LEN_0F2E_P_2, 1695 VEX_LEN_0F2F_P_0, 1696 VEX_LEN_0F2F_P_2, 1697 VEX_LEN_0F41_P_0, 1698 VEX_LEN_0F41_P_2, 1699 VEX_LEN_0F42_P_0, 1700 VEX_LEN_0F42_P_2, 1701 VEX_LEN_0F44_P_0, 1702 VEX_LEN_0F44_P_2, 1703 VEX_LEN_0F45_P_0, 1704 VEX_LEN_0F45_P_2, 1705 VEX_LEN_0F46_P_0, 1706 VEX_LEN_0F46_P_2, 1707 VEX_LEN_0F47_P_0, 1708 VEX_LEN_0F47_P_2, 1709 VEX_LEN_0F4A_P_0, 1710 VEX_LEN_0F4A_P_2, 1711 VEX_LEN_0F4B_P_0, 1712 VEX_LEN_0F4B_P_2, 1713 VEX_LEN_0F51_P_1, 1714 VEX_LEN_0F51_P_3, 1715 VEX_LEN_0F52_P_1, 1716 VEX_LEN_0F53_P_1, 1717 VEX_LEN_0F58_P_1, 1718 VEX_LEN_0F58_P_3, 1719 VEX_LEN_0F59_P_1, 1720 VEX_LEN_0F59_P_3, 1721 VEX_LEN_0F5A_P_1, 1722 VEX_LEN_0F5A_P_3, 1723 VEX_LEN_0F5C_P_1, 1724 VEX_LEN_0F5C_P_3, 1725 VEX_LEN_0F5D_P_1, 1726 VEX_LEN_0F5D_P_3, 1727 VEX_LEN_0F5E_P_1, 1728 VEX_LEN_0F5E_P_3, 1729 VEX_LEN_0F5F_P_1, 1730 VEX_LEN_0F5F_P_3, 1731 VEX_LEN_0F6E_P_2, 1732 VEX_LEN_0F7E_P_1, 1733 VEX_LEN_0F7E_P_2, 1734 VEX_LEN_0F90_P_0, 1735 VEX_LEN_0F90_P_2, 1736 VEX_LEN_0F91_P_0, 1737 VEX_LEN_0F91_P_2, 1738 VEX_LEN_0F92_P_0, 1739 VEX_LEN_0F92_P_2, 1740 VEX_LEN_0F92_P_3, 1741 VEX_LEN_0F93_P_0, 1742 VEX_LEN_0F93_P_2, 1743 VEX_LEN_0F93_P_3, 1744 VEX_LEN_0F98_P_0, 1745 VEX_LEN_0F98_P_2, 1746 VEX_LEN_0F99_P_0, 1747 VEX_LEN_0F99_P_2, 1748 VEX_LEN_0FAE_R_2_M_0, 1749 VEX_LEN_0FAE_R_3_M_0, 1750 VEX_LEN_0FC2_P_1, 1751 VEX_LEN_0FC2_P_3, 1752 VEX_LEN_0FC4_P_2, 1753 VEX_LEN_0FC5_P_2, 1754 VEX_LEN_0FD6_P_2, 1755 VEX_LEN_0FF7_P_2, 1756 VEX_LEN_0F3816_P_2, 1757 VEX_LEN_0F3819_P_2, 1758 VEX_LEN_0F381A_P_2_M_0, 1759 VEX_LEN_0F3836_P_2, 1760 VEX_LEN_0F3841_P_2, 1761 VEX_LEN_0F385A_P_2_M_0, 1762 VEX_LEN_0F38DB_P_2, 1763 VEX_LEN_0F38DC_P_2, 1764 VEX_LEN_0F38DD_P_2, 1765 VEX_LEN_0F38DE_P_2, 1766 VEX_LEN_0F38DF_P_2, 1767 VEX_LEN_0F38F2_P_0, 1768 VEX_LEN_0F38F3_R_1_P_0, 1769 VEX_LEN_0F38F3_R_2_P_0, 1770 VEX_LEN_0F38F3_R_3_P_0, 1771 VEX_LEN_0F38F5_P_0, 1772 VEX_LEN_0F38F5_P_1, 1773 VEX_LEN_0F38F5_P_3, 1774 VEX_LEN_0F38F6_P_3, 1775 VEX_LEN_0F38F7_P_0, 1776 VEX_LEN_0F38F7_P_1, 1777 VEX_LEN_0F38F7_P_2, 1778 VEX_LEN_0F38F7_P_3, 1779 VEX_LEN_0F3A00_P_2, 1780 VEX_LEN_0F3A01_P_2, 1781 VEX_LEN_0F3A06_P_2, 1782 VEX_LEN_0F3A0A_P_2, 1783 VEX_LEN_0F3A0B_P_2, 1784 VEX_LEN_0F3A14_P_2, 1785 VEX_LEN_0F3A15_P_2, 1786 VEX_LEN_0F3A16_P_2, 1787 VEX_LEN_0F3A17_P_2, 1788 VEX_LEN_0F3A18_P_2, 1789 VEX_LEN_0F3A19_P_2, 1790 VEX_LEN_0F3A20_P_2, 1791 VEX_LEN_0F3A21_P_2, 1792 VEX_LEN_0F3A22_P_2, 1793 VEX_LEN_0F3A30_P_2, 1794 VEX_LEN_0F3A31_P_2, 1795 VEX_LEN_0F3A32_P_2, 1796 VEX_LEN_0F3A33_P_2, 1797 VEX_LEN_0F3A38_P_2, 1798 VEX_LEN_0F3A39_P_2, 1799 VEX_LEN_0F3A41_P_2, 1800 VEX_LEN_0F3A44_P_2, 1801 VEX_LEN_0F3A46_P_2, 1802 VEX_LEN_0F3A60_P_2, 1803 VEX_LEN_0F3A61_P_2, 1804 VEX_LEN_0F3A62_P_2, 1805 VEX_LEN_0F3A63_P_2, 1806 VEX_LEN_0F3A6A_P_2, 1807 VEX_LEN_0F3A6B_P_2, 1808 VEX_LEN_0F3A6E_P_2, 1809 VEX_LEN_0F3A6F_P_2, 1810 VEX_LEN_0F3A7A_P_2, 1811 VEX_LEN_0F3A7B_P_2, 1812 VEX_LEN_0F3A7E_P_2, 1813 VEX_LEN_0F3A7F_P_2, 1814 VEX_LEN_0F3ADF_P_2, 1815 VEX_LEN_0F3AF0_P_3, 1816 VEX_LEN_0FXOP_08_CC, 1817 VEX_LEN_0FXOP_08_CD, 1818 VEX_LEN_0FXOP_08_CE, 1819 VEX_LEN_0FXOP_08_CF, 1820 VEX_LEN_0FXOP_08_EC, 1821 VEX_LEN_0FXOP_08_ED, 1822 VEX_LEN_0FXOP_08_EE, 1823 VEX_LEN_0FXOP_08_EF, 1824 VEX_LEN_0FXOP_09_80, 1825 VEX_LEN_0FXOP_09_81 1826 }; 1827 1828 enum 1829 { 1830 VEX_W_0F10_P_0 = 0, 1831 VEX_W_0F10_P_1, 1832 VEX_W_0F10_P_2, 1833 VEX_W_0F10_P_3, 1834 VEX_W_0F11_P_0, 1835 VEX_W_0F11_P_1, 1836 VEX_W_0F11_P_2, 1837 VEX_W_0F11_P_3, 1838 VEX_W_0F12_P_0_M_0, 1839 VEX_W_0F12_P_0_M_1, 1840 VEX_W_0F12_P_1, 1841 VEX_W_0F12_P_2, 1842 VEX_W_0F12_P_3, 1843 VEX_W_0F13_M_0, 1844 VEX_W_0F14, 1845 VEX_W_0F15, 1846 VEX_W_0F16_P_0_M_0, 1847 VEX_W_0F16_P_0_M_1, 1848 VEX_W_0F16_P_1, 1849 VEX_W_0F16_P_2, 1850 VEX_W_0F17_M_0, 1851 VEX_W_0F28, 1852 VEX_W_0F29, 1853 VEX_W_0F2B_M_0, 1854 VEX_W_0F2E_P_0, 1855 VEX_W_0F2E_P_2, 1856 VEX_W_0F2F_P_0, 1857 VEX_W_0F2F_P_2, 1858 VEX_W_0F41_P_0_LEN_1, 1859 VEX_W_0F41_P_2_LEN_1, 1860 VEX_W_0F42_P_0_LEN_1, 1861 VEX_W_0F42_P_2_LEN_1, 1862 VEX_W_0F44_P_0_LEN_0, 1863 VEX_W_0F44_P_2_LEN_0, 1864 VEX_W_0F45_P_0_LEN_1, 1865 VEX_W_0F45_P_2_LEN_1, 1866 VEX_W_0F46_P_0_LEN_1, 1867 VEX_W_0F46_P_2_LEN_1, 1868 VEX_W_0F47_P_0_LEN_1, 1869 VEX_W_0F47_P_2_LEN_1, 1870 VEX_W_0F4A_P_0_LEN_1, 1871 VEX_W_0F4A_P_2_LEN_1, 1872 VEX_W_0F4B_P_0_LEN_1, 1873 VEX_W_0F4B_P_2_LEN_1, 1874 VEX_W_0F50_M_0, 1875 VEX_W_0F51_P_0, 1876 VEX_W_0F51_P_1, 1877 VEX_W_0F51_P_2, 1878 VEX_W_0F51_P_3, 1879 VEX_W_0F52_P_0, 1880 VEX_W_0F52_P_1, 1881 VEX_W_0F53_P_0, 1882 VEX_W_0F53_P_1, 1883 VEX_W_0F58_P_0, 1884 VEX_W_0F58_P_1, 1885 VEX_W_0F58_P_2, 1886 VEX_W_0F58_P_3, 1887 VEX_W_0F59_P_0, 1888 VEX_W_0F59_P_1, 1889 VEX_W_0F59_P_2, 1890 VEX_W_0F59_P_3, 1891 VEX_W_0F5A_P_0, 1892 VEX_W_0F5A_P_1, 1893 VEX_W_0F5A_P_3, 1894 VEX_W_0F5B_P_0, 1895 VEX_W_0F5B_P_1, 1896 VEX_W_0F5B_P_2, 1897 VEX_W_0F5C_P_0, 1898 VEX_W_0F5C_P_1, 1899 VEX_W_0F5C_P_2, 1900 VEX_W_0F5C_P_3, 1901 VEX_W_0F5D_P_0, 1902 VEX_W_0F5D_P_1, 1903 VEX_W_0F5D_P_2, 1904 VEX_W_0F5D_P_3, 1905 VEX_W_0F5E_P_0, 1906 VEX_W_0F5E_P_1, 1907 VEX_W_0F5E_P_2, 1908 VEX_W_0F5E_P_3, 1909 VEX_W_0F5F_P_0, 1910 VEX_W_0F5F_P_1, 1911 VEX_W_0F5F_P_2, 1912 VEX_W_0F5F_P_3, 1913 VEX_W_0F60_P_2, 1914 VEX_W_0F61_P_2, 1915 VEX_W_0F62_P_2, 1916 VEX_W_0F63_P_2, 1917 VEX_W_0F64_P_2, 1918 VEX_W_0F65_P_2, 1919 VEX_W_0F66_P_2, 1920 VEX_W_0F67_P_2, 1921 VEX_W_0F68_P_2, 1922 VEX_W_0F69_P_2, 1923 VEX_W_0F6A_P_2, 1924 VEX_W_0F6B_P_2, 1925 VEX_W_0F6C_P_2, 1926 VEX_W_0F6D_P_2, 1927 VEX_W_0F6F_P_1, 1928 VEX_W_0F6F_P_2, 1929 VEX_W_0F70_P_1, 1930 VEX_W_0F70_P_2, 1931 VEX_W_0F70_P_3, 1932 VEX_W_0F71_R_2_P_2, 1933 VEX_W_0F71_R_4_P_2, 1934 VEX_W_0F71_R_6_P_2, 1935 VEX_W_0F72_R_2_P_2, 1936 VEX_W_0F72_R_4_P_2, 1937 VEX_W_0F72_R_6_P_2, 1938 VEX_W_0F73_R_2_P_2, 1939 VEX_W_0F73_R_3_P_2, 1940 VEX_W_0F73_R_6_P_2, 1941 VEX_W_0F73_R_7_P_2, 1942 VEX_W_0F74_P_2, 1943 VEX_W_0F75_P_2, 1944 VEX_W_0F76_P_2, 1945 VEX_W_0F77_P_0, 1946 VEX_W_0F7C_P_2, 1947 VEX_W_0F7C_P_3, 1948 VEX_W_0F7D_P_2, 1949 VEX_W_0F7D_P_3, 1950 VEX_W_0F7E_P_1, 1951 VEX_W_0F7F_P_1, 1952 VEX_W_0F7F_P_2, 1953 VEX_W_0F90_P_0_LEN_0, 1954 VEX_W_0F90_P_2_LEN_0, 1955 VEX_W_0F91_P_0_LEN_0, 1956 VEX_W_0F91_P_2_LEN_0, 1957 VEX_W_0F92_P_0_LEN_0, 1958 VEX_W_0F92_P_2_LEN_0, 1959 VEX_W_0F92_P_3_LEN_0, 1960 VEX_W_0F93_P_0_LEN_0, 1961 VEX_W_0F93_P_2_LEN_0, 1962 VEX_W_0F93_P_3_LEN_0, 1963 VEX_W_0F98_P_0_LEN_0, 1964 VEX_W_0F98_P_2_LEN_0, 1965 VEX_W_0F99_P_0_LEN_0, 1966 VEX_W_0F99_P_2_LEN_0, 1967 VEX_W_0FAE_R_2_M_0, 1968 VEX_W_0FAE_R_3_M_0, 1969 VEX_W_0FC2_P_0, 1970 VEX_W_0FC2_P_1, 1971 VEX_W_0FC2_P_2, 1972 VEX_W_0FC2_P_3, 1973 VEX_W_0FC4_P_2, 1974 VEX_W_0FC5_P_2, 1975 VEX_W_0FD0_P_2, 1976 VEX_W_0FD0_P_3, 1977 VEX_W_0FD1_P_2, 1978 VEX_W_0FD2_P_2, 1979 VEX_W_0FD3_P_2, 1980 VEX_W_0FD4_P_2, 1981 VEX_W_0FD5_P_2, 1982 VEX_W_0FD6_P_2, 1983 VEX_W_0FD7_P_2_M_1, 1984 VEX_W_0FD8_P_2, 1985 VEX_W_0FD9_P_2, 1986 VEX_W_0FDA_P_2, 1987 VEX_W_0FDB_P_2, 1988 VEX_W_0FDC_P_2, 1989 VEX_W_0FDD_P_2, 1990 VEX_W_0FDE_P_2, 1991 VEX_W_0FDF_P_2, 1992 VEX_W_0FE0_P_2, 1993 VEX_W_0FE1_P_2, 1994 VEX_W_0FE2_P_2, 1995 VEX_W_0FE3_P_2, 1996 VEX_W_0FE4_P_2, 1997 VEX_W_0FE5_P_2, 1998 VEX_W_0FE6_P_1, 1999 VEX_W_0FE6_P_2, 2000 VEX_W_0FE6_P_3, 2001 VEX_W_0FE7_P_2_M_0, 2002 VEX_W_0FE8_P_2, 2003 VEX_W_0FE9_P_2, 2004 VEX_W_0FEA_P_2, 2005 VEX_W_0FEB_P_2, 2006 VEX_W_0FEC_P_2, 2007 VEX_W_0FED_P_2, 2008 VEX_W_0FEE_P_2, 2009 VEX_W_0FEF_P_2, 2010 VEX_W_0FF0_P_3_M_0, 2011 VEX_W_0FF1_P_2, 2012 VEX_W_0FF2_P_2, 2013 VEX_W_0FF3_P_2, 2014 VEX_W_0FF4_P_2, 2015 VEX_W_0FF5_P_2, 2016 VEX_W_0FF6_P_2, 2017 VEX_W_0FF7_P_2, 2018 VEX_W_0FF8_P_2, 2019 VEX_W_0FF9_P_2, 2020 VEX_W_0FFA_P_2, 2021 VEX_W_0FFB_P_2, 2022 VEX_W_0FFC_P_2, 2023 VEX_W_0FFD_P_2, 2024 VEX_W_0FFE_P_2, 2025 VEX_W_0F3800_P_2, 2026 VEX_W_0F3801_P_2, 2027 VEX_W_0F3802_P_2, 2028 VEX_W_0F3803_P_2, 2029 VEX_W_0F3804_P_2, 2030 VEX_W_0F3805_P_2, 2031 VEX_W_0F3806_P_2, 2032 VEX_W_0F3807_P_2, 2033 VEX_W_0F3808_P_2, 2034 VEX_W_0F3809_P_2, 2035 VEX_W_0F380A_P_2, 2036 VEX_W_0F380B_P_2, 2037 VEX_W_0F380C_P_2, 2038 VEX_W_0F380D_P_2, 2039 VEX_W_0F380E_P_2, 2040 VEX_W_0F380F_P_2, 2041 VEX_W_0F3816_P_2, 2042 VEX_W_0F3817_P_2, 2043 VEX_W_0F3818_P_2, 2044 VEX_W_0F3819_P_2, 2045 VEX_W_0F381A_P_2_M_0, 2046 VEX_W_0F381C_P_2, 2047 VEX_W_0F381D_P_2, 2048 VEX_W_0F381E_P_2, 2049 VEX_W_0F3820_P_2, 2050 VEX_W_0F3821_P_2, 2051 VEX_W_0F3822_P_2, 2052 VEX_W_0F3823_P_2, 2053 VEX_W_0F3824_P_2, 2054 VEX_W_0F3825_P_2, 2055 VEX_W_0F3828_P_2, 2056 VEX_W_0F3829_P_2, 2057 VEX_W_0F382A_P_2_M_0, 2058 VEX_W_0F382B_P_2, 2059 VEX_W_0F382C_P_2_M_0, 2060 VEX_W_0F382D_P_2_M_0, 2061 VEX_W_0F382E_P_2_M_0, 2062 VEX_W_0F382F_P_2_M_0, 2063 VEX_W_0F3830_P_2, 2064 VEX_W_0F3831_P_2, 2065 VEX_W_0F3832_P_2, 2066 VEX_W_0F3833_P_2, 2067 VEX_W_0F3834_P_2, 2068 VEX_W_0F3835_P_2, 2069 VEX_W_0F3836_P_2, 2070 VEX_W_0F3837_P_2, 2071 VEX_W_0F3838_P_2, 2072 VEX_W_0F3839_P_2, 2073 VEX_W_0F383A_P_2, 2074 VEX_W_0F383B_P_2, 2075 VEX_W_0F383C_P_2, 2076 VEX_W_0F383D_P_2, 2077 VEX_W_0F383E_P_2, 2078 VEX_W_0F383F_P_2, 2079 VEX_W_0F3840_P_2, 2080 VEX_W_0F3841_P_2, 2081 VEX_W_0F3846_P_2, 2082 VEX_W_0F3858_P_2, 2083 VEX_W_0F3859_P_2, 2084 VEX_W_0F385A_P_2_M_0, 2085 VEX_W_0F3878_P_2, 2086 VEX_W_0F3879_P_2, 2087 VEX_W_0F38DB_P_2, 2088 VEX_W_0F38DC_P_2, 2089 VEX_W_0F38DD_P_2, 2090 VEX_W_0F38DE_P_2, 2091 VEX_W_0F38DF_P_2, 2092 VEX_W_0F3A00_P_2, 2093 VEX_W_0F3A01_P_2, 2094 VEX_W_0F3A02_P_2, 2095 VEX_W_0F3A04_P_2, 2096 VEX_W_0F3A05_P_2, 2097 VEX_W_0F3A06_P_2, 2098 VEX_W_0F3A08_P_2, 2099 VEX_W_0F3A09_P_2, 2100 VEX_W_0F3A0A_P_2, 2101 VEX_W_0F3A0B_P_2, 2102 VEX_W_0F3A0C_P_2, 2103 VEX_W_0F3A0D_P_2, 2104 VEX_W_0F3A0E_P_2, 2105 VEX_W_0F3A0F_P_2, 2106 VEX_W_0F3A14_P_2, 2107 VEX_W_0F3A15_P_2, 2108 VEX_W_0F3A18_P_2, 2109 VEX_W_0F3A19_P_2, 2110 VEX_W_0F3A20_P_2, 2111 VEX_W_0F3A21_P_2, 2112 VEX_W_0F3A30_P_2_LEN_0, 2113 VEX_W_0F3A31_P_2_LEN_0, 2114 VEX_W_0F3A32_P_2_LEN_0, 2115 VEX_W_0F3A33_P_2_LEN_0, 2116 VEX_W_0F3A38_P_2, 2117 VEX_W_0F3A39_P_2, 2118 VEX_W_0F3A40_P_2, 2119 VEX_W_0F3A41_P_2, 2120 VEX_W_0F3A42_P_2, 2121 VEX_W_0F3A44_P_2, 2122 VEX_W_0F3A46_P_2, 2123 VEX_W_0F3A48_P_2, 2124 VEX_W_0F3A49_P_2, 2125 VEX_W_0F3A4A_P_2, 2126 VEX_W_0F3A4B_P_2, 2127 VEX_W_0F3A4C_P_2, 2128 VEX_W_0F3A60_P_2, 2129 VEX_W_0F3A61_P_2, 2130 VEX_W_0F3A62_P_2, 2131 VEX_W_0F3A63_P_2, 2132 VEX_W_0F3ADF_P_2, 2133 2134 EVEX_W_0F10_P_0, 2135 EVEX_W_0F10_P_1_M_0, 2136 EVEX_W_0F10_P_1_M_1, 2137 EVEX_W_0F10_P_2, 2138 EVEX_W_0F10_P_3_M_0, 2139 EVEX_W_0F10_P_3_M_1, 2140 EVEX_W_0F11_P_0, 2141 EVEX_W_0F11_P_1_M_0, 2142 EVEX_W_0F11_P_1_M_1, 2143 EVEX_W_0F11_P_2, 2144 EVEX_W_0F11_P_3_M_0, 2145 EVEX_W_0F11_P_3_M_1, 2146 EVEX_W_0F12_P_0_M_0, 2147 EVEX_W_0F12_P_0_M_1, 2148 EVEX_W_0F12_P_1, 2149 EVEX_W_0F12_P_2, 2150 EVEX_W_0F12_P_3, 2151 EVEX_W_0F13_P_0, 2152 EVEX_W_0F13_P_2, 2153 EVEX_W_0F14_P_0, 2154 EVEX_W_0F14_P_2, 2155 EVEX_W_0F15_P_0, 2156 EVEX_W_0F15_P_2, 2157 EVEX_W_0F16_P_0_M_0, 2158 EVEX_W_0F16_P_0_M_1, 2159 EVEX_W_0F16_P_1, 2160 EVEX_W_0F16_P_2, 2161 EVEX_W_0F17_P_0, 2162 EVEX_W_0F17_P_2, 2163 EVEX_W_0F28_P_0, 2164 EVEX_W_0F28_P_2, 2165 EVEX_W_0F29_P_0, 2166 EVEX_W_0F29_P_2, 2167 EVEX_W_0F2A_P_1, 2168 EVEX_W_0F2A_P_3, 2169 EVEX_W_0F2B_P_0, 2170 EVEX_W_0F2B_P_2, 2171 EVEX_W_0F2E_P_0, 2172 EVEX_W_0F2E_P_2, 2173 EVEX_W_0F2F_P_0, 2174 EVEX_W_0F2F_P_2, 2175 EVEX_W_0F51_P_0, 2176 EVEX_W_0F51_P_1, 2177 EVEX_W_0F51_P_2, 2178 EVEX_W_0F51_P_3, 2179 EVEX_W_0F54_P_0, 2180 EVEX_W_0F54_P_2, 2181 EVEX_W_0F55_P_0, 2182 EVEX_W_0F55_P_2, 2183 EVEX_W_0F56_P_0, 2184 EVEX_W_0F56_P_2, 2185 EVEX_W_0F57_P_0, 2186 EVEX_W_0F57_P_2, 2187 EVEX_W_0F58_P_0, 2188 EVEX_W_0F58_P_1, 2189 EVEX_W_0F58_P_2, 2190 EVEX_W_0F58_P_3, 2191 EVEX_W_0F59_P_0, 2192 EVEX_W_0F59_P_1, 2193 EVEX_W_0F59_P_2, 2194 EVEX_W_0F59_P_3, 2195 EVEX_W_0F5A_P_0, 2196 EVEX_W_0F5A_P_1, 2197 EVEX_W_0F5A_P_2, 2198 EVEX_W_0F5A_P_3, 2199 EVEX_W_0F5B_P_0, 2200 EVEX_W_0F5B_P_1, 2201 EVEX_W_0F5B_P_2, 2202 EVEX_W_0F5C_P_0, 2203 EVEX_W_0F5C_P_1, 2204 EVEX_W_0F5C_P_2, 2205 EVEX_W_0F5C_P_3, 2206 EVEX_W_0F5D_P_0, 2207 EVEX_W_0F5D_P_1, 2208 EVEX_W_0F5D_P_2, 2209 EVEX_W_0F5D_P_3, 2210 EVEX_W_0F5E_P_0, 2211 EVEX_W_0F5E_P_1, 2212 EVEX_W_0F5E_P_2, 2213 EVEX_W_0F5E_P_3, 2214 EVEX_W_0F5F_P_0, 2215 EVEX_W_0F5F_P_1, 2216 EVEX_W_0F5F_P_2, 2217 EVEX_W_0F5F_P_3, 2218 EVEX_W_0F62_P_2, 2219 EVEX_W_0F66_P_2, 2220 EVEX_W_0F6A_P_2, 2221 EVEX_W_0F6B_P_2, 2222 EVEX_W_0F6C_P_2, 2223 EVEX_W_0F6D_P_2, 2224 EVEX_W_0F6E_P_2, 2225 EVEX_W_0F6F_P_1, 2226 EVEX_W_0F6F_P_2, 2227 EVEX_W_0F6F_P_3, 2228 EVEX_W_0F70_P_2, 2229 EVEX_W_0F72_R_2_P_2, 2230 EVEX_W_0F72_R_6_P_2, 2231 EVEX_W_0F73_R_2_P_2, 2232 EVEX_W_0F73_R_6_P_2, 2233 EVEX_W_0F76_P_2, 2234 EVEX_W_0F78_P_0, 2235 EVEX_W_0F78_P_2, 2236 EVEX_W_0F79_P_0, 2237 EVEX_W_0F79_P_2, 2238 EVEX_W_0F7A_P_1, 2239 EVEX_W_0F7A_P_2, 2240 EVEX_W_0F7A_P_3, 2241 EVEX_W_0F7B_P_1, 2242 EVEX_W_0F7B_P_2, 2243 EVEX_W_0F7B_P_3, 2244 EVEX_W_0F7E_P_1, 2245 EVEX_W_0F7E_P_2, 2246 EVEX_W_0F7F_P_1, 2247 EVEX_W_0F7F_P_2, 2248 EVEX_W_0F7F_P_3, 2249 EVEX_W_0FC2_P_0, 2250 EVEX_W_0FC2_P_1, 2251 EVEX_W_0FC2_P_2, 2252 EVEX_W_0FC2_P_3, 2253 EVEX_W_0FC6_P_0, 2254 EVEX_W_0FC6_P_2, 2255 EVEX_W_0FD2_P_2, 2256 EVEX_W_0FD3_P_2, 2257 EVEX_W_0FD4_P_2, 2258 EVEX_W_0FD6_P_2, 2259 EVEX_W_0FE6_P_1, 2260 EVEX_W_0FE6_P_2, 2261 EVEX_W_0FE6_P_3, 2262 EVEX_W_0FE7_P_2, 2263 EVEX_W_0FF2_P_2, 2264 EVEX_W_0FF3_P_2, 2265 EVEX_W_0FF4_P_2, 2266 EVEX_W_0FFA_P_2, 2267 EVEX_W_0FFB_P_2, 2268 EVEX_W_0FFE_P_2, 2269 EVEX_W_0F380C_P_2, 2270 EVEX_W_0F380D_P_2, 2271 EVEX_W_0F3810_P_1, 2272 EVEX_W_0F3810_P_2, 2273 EVEX_W_0F3811_P_1, 2274 EVEX_W_0F3811_P_2, 2275 EVEX_W_0F3812_P_1, 2276 EVEX_W_0F3812_P_2, 2277 EVEX_W_0F3813_P_1, 2278 EVEX_W_0F3813_P_2, 2279 EVEX_W_0F3814_P_1, 2280 EVEX_W_0F3815_P_1, 2281 EVEX_W_0F3818_P_2, 2282 EVEX_W_0F3819_P_2, 2283 EVEX_W_0F381A_P_2, 2284 EVEX_W_0F381B_P_2, 2285 EVEX_W_0F381E_P_2, 2286 EVEX_W_0F381F_P_2, 2287 EVEX_W_0F3820_P_1, 2288 EVEX_W_0F3821_P_1, 2289 EVEX_W_0F3822_P_1, 2290 EVEX_W_0F3823_P_1, 2291 EVEX_W_0F3824_P_1, 2292 EVEX_W_0F3825_P_1, 2293 EVEX_W_0F3825_P_2, 2294 EVEX_W_0F3826_P_1, 2295 EVEX_W_0F3826_P_2, 2296 EVEX_W_0F3828_P_1, 2297 EVEX_W_0F3828_P_2, 2298 EVEX_W_0F3829_P_1, 2299 EVEX_W_0F3829_P_2, 2300 EVEX_W_0F382A_P_1, 2301 EVEX_W_0F382A_P_2, 2302 EVEX_W_0F382B_P_2, 2303 EVEX_W_0F3830_P_1, 2304 EVEX_W_0F3831_P_1, 2305 EVEX_W_0F3832_P_1, 2306 EVEX_W_0F3833_P_1, 2307 EVEX_W_0F3834_P_1, 2308 EVEX_W_0F3835_P_1, 2309 EVEX_W_0F3835_P_2, 2310 EVEX_W_0F3837_P_2, 2311 EVEX_W_0F3838_P_1, 2312 EVEX_W_0F3839_P_1, 2313 EVEX_W_0F383A_P_1, 2314 EVEX_W_0F3840_P_2, 2315 EVEX_W_0F3858_P_2, 2316 EVEX_W_0F3859_P_2, 2317 EVEX_W_0F385A_P_2, 2318 EVEX_W_0F385B_P_2, 2319 EVEX_W_0F3866_P_2, 2320 EVEX_W_0F3875_P_2, 2321 EVEX_W_0F3878_P_2, 2322 EVEX_W_0F3879_P_2, 2323 EVEX_W_0F387A_P_2, 2324 EVEX_W_0F387B_P_2, 2325 EVEX_W_0F387D_P_2, 2326 EVEX_W_0F3883_P_2, 2327 EVEX_W_0F388D_P_2, 2328 EVEX_W_0F3891_P_2, 2329 EVEX_W_0F3893_P_2, 2330 EVEX_W_0F38A1_P_2, 2331 EVEX_W_0F38A3_P_2, 2332 EVEX_W_0F38C7_R_1_P_2, 2333 EVEX_W_0F38C7_R_2_P_2, 2334 EVEX_W_0F38C7_R_5_P_2, 2335 EVEX_W_0F38C7_R_6_P_2, 2336 2337 EVEX_W_0F3A00_P_2, 2338 EVEX_W_0F3A01_P_2, 2339 EVEX_W_0F3A04_P_2, 2340 EVEX_W_0F3A05_P_2, 2341 EVEX_W_0F3A08_P_2, 2342 EVEX_W_0F3A09_P_2, 2343 EVEX_W_0F3A0A_P_2, 2344 EVEX_W_0F3A0B_P_2, 2345 EVEX_W_0F3A16_P_2, 2346 EVEX_W_0F3A18_P_2, 2347 EVEX_W_0F3A19_P_2, 2348 EVEX_W_0F3A1A_P_2, 2349 EVEX_W_0F3A1B_P_2, 2350 EVEX_W_0F3A1D_P_2, 2351 EVEX_W_0F3A21_P_2, 2352 EVEX_W_0F3A22_P_2, 2353 EVEX_W_0F3A23_P_2, 2354 EVEX_W_0F3A38_P_2, 2355 EVEX_W_0F3A39_P_2, 2356 EVEX_W_0F3A3A_P_2, 2357 EVEX_W_0F3A3B_P_2, 2358 EVEX_W_0F3A3E_P_2, 2359 EVEX_W_0F3A3F_P_2, 2360 EVEX_W_0F3A42_P_2, 2361 EVEX_W_0F3A43_P_2, 2362 EVEX_W_0F3A50_P_2, 2363 EVEX_W_0F3A51_P_2, 2364 EVEX_W_0F3A56_P_2, 2365 EVEX_W_0F3A57_P_2, 2366 EVEX_W_0F3A66_P_2, 2367 EVEX_W_0F3A67_P_2 2368 }; 2369 2370 typedef void (*op_rtn) (int bytemode, int sizeflag); 2371 2372 struct dis386 { 2373 const char *name; 2374 struct 2375 { 2376 op_rtn rtn; 2377 int bytemode; 2378 } op[MAX_OPERANDS]; 2379 unsigned int prefix_requirement; 2380 }; 2381 2382 /* Upper case letters in the instruction names here are macros. 2383 'A' => print 'b' if no register operands or suffix_always is true 2384 'B' => print 'b' if suffix_always is true 2385 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 2386 size prefix 2387 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 2388 suffix_always is true 2389 'E' => print 'e' if 32-bit form of jcxz 2390 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 2391 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 2392 'H' => print ",pt" or ",pn" branch hint 2393 'I' => honor following macro letter even in Intel mode (implemented only 2394 for some of the macro letters) 2395 'J' => print 'l' 2396 'K' => print 'd' or 'q' if rex prefix is present. 2397 'L' => print 'l' if suffix_always is true 2398 'M' => print 'r' if intel_mnemonic is false. 2399 'N' => print 'n' if instruction has no wait "prefix" 2400 'O' => print 'd' or 'o' (or 'q' in Intel mode) 2401 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, 2402 or suffix_always is true. print 'q' if rex prefix is present. 2403 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always 2404 is true 2405 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 2406 'S' => print 'w', 'l' or 'q' if suffix_always is true 2407 'T' => print 'q' in 64bit mode if instruction has no operand size 2408 prefix and behave as 'P' otherwise 2409 'U' => print 'q' in 64bit mode if instruction has no operand size 2410 prefix and behave as 'Q' otherwise 2411 'V' => print 'q' in 64bit mode if instruction has no operand size 2412 prefix and behave as 'S' otherwise 2413 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 2414 'X' => print 's', 'd' depending on data16 prefix (for XMM) 2415 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and 2416 suffix_always is true. 2417 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise 2418 '!' => change condition from true to false or from false to true. 2419 '%' => add 1 upper case letter to the macro. 2420 '^' => print 'w' or 'l' depending on operand size prefix or 2421 suffix_always is true (lcall/ljmp). 2422 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending 2423 on operand size prefix. 2424 2425 2 upper case letter macros: 2426 "XY" => print 'x' or 'y' if suffix_always is true or no register 2427 operands and no broadcast. 2428 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no 2429 register operands and no broadcast. 2430 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) 2431 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand 2432 or suffix_always is true 2433 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise 2434 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise 2435 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise 2436 "LW" => print 'd', 'q' depending on the VEX.W bit 2437 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has 2438 an operand size prefix, or suffix_always is true. print 2439 'q' if rex prefix is present. 2440 2441 Many of the above letters print nothing in Intel mode. See "putop" 2442 for the details. 2443 2444 Braces '{' and '}', and vertical bars '|', indicate alternative 2445 mnemonic strings for AT&T and Intel. */ 2446 2447 static const struct dis386 dis386[] = { 2448 /* 00 */ 2449 { "addB", { Ebh1, Gb }, 0 }, 2450 { "addS", { Evh1, Gv }, 0 }, 2451 { "addB", { Gb, EbS }, 0 }, 2452 { "addS", { Gv, EvS }, 0 }, 2453 { "addB", { AL, Ib }, 0 }, 2454 { "addS", { eAX, Iv }, 0 }, 2455 { X86_64_TABLE (X86_64_06) }, 2456 { X86_64_TABLE (X86_64_07) }, 2457 /* 08 */ 2458 { "orB", { Ebh1, Gb }, 0 }, 2459 { "orS", { Evh1, Gv }, 0 }, 2460 { "orB", { Gb, EbS }, 0 }, 2461 { "orS", { Gv, EvS }, 0 }, 2462 { "orB", { AL, Ib }, 0 }, 2463 { "orS", { eAX, Iv }, 0 }, 2464 { X86_64_TABLE (X86_64_0D) }, 2465 { Bad_Opcode }, /* 0x0f extended opcode escape */ 2466 /* 10 */ 2467 { "adcB", { Ebh1, Gb }, 0 }, 2468 { "adcS", { Evh1, Gv }, 0 }, 2469 { "adcB", { Gb, EbS }, 0 }, 2470 { "adcS", { Gv, EvS }, 0 }, 2471 { "adcB", { AL, Ib }, 0 }, 2472 { "adcS", { eAX, Iv }, 0 }, 2473 { X86_64_TABLE (X86_64_16) }, 2474 { X86_64_TABLE (X86_64_17) }, 2475 /* 18 */ 2476 { "sbbB", { Ebh1, Gb }, 0 }, 2477 { "sbbS", { Evh1, Gv }, 0 }, 2478 { "sbbB", { Gb, EbS }, 0 }, 2479 { "sbbS", { Gv, EvS }, 0 }, 2480 { "sbbB", { AL, Ib }, 0 }, 2481 { "sbbS", { eAX, Iv }, 0 }, 2482 { X86_64_TABLE (X86_64_1E) }, 2483 { X86_64_TABLE (X86_64_1F) }, 2484 /* 20 */ 2485 { "andB", { Ebh1, Gb }, 0 }, 2486 { "andS", { Evh1, Gv }, 0 }, 2487 { "andB", { Gb, EbS }, 0 }, 2488 { "andS", { Gv, EvS }, 0 }, 2489 { "andB", { AL, Ib }, 0 }, 2490 { "andS", { eAX, Iv }, 0 }, 2491 { Bad_Opcode }, /* SEG ES prefix */ 2492 { X86_64_TABLE (X86_64_27) }, 2493 /* 28 */ 2494 { "subB", { Ebh1, Gb }, 0 }, 2495 { "subS", { Evh1, Gv }, 0 }, 2496 { "subB", { Gb, EbS }, 0 }, 2497 { "subS", { Gv, EvS }, 0 }, 2498 { "subB", { AL, Ib }, 0 }, 2499 { "subS", { eAX, Iv }, 0 }, 2500 { Bad_Opcode }, /* SEG CS prefix */ 2501 { X86_64_TABLE (X86_64_2F) }, 2502 /* 30 */ 2503 { "xorB", { Ebh1, Gb }, 0 }, 2504 { "xorS", { Evh1, Gv }, 0 }, 2505 { "xorB", { Gb, EbS }, 0 }, 2506 { "xorS", { Gv, EvS }, 0 }, 2507 { "xorB", { AL, Ib }, 0 }, 2508 { "xorS", { eAX, Iv }, 0 }, 2509 { Bad_Opcode }, /* SEG SS prefix */ 2510 { X86_64_TABLE (X86_64_37) }, 2511 /* 38 */ 2512 { "cmpB", { Eb, Gb }, 0 }, 2513 { "cmpS", { Ev, Gv }, 0 }, 2514 { "cmpB", { Gb, EbS }, 0 }, 2515 { "cmpS", { Gv, EvS }, 0 }, 2516 { "cmpB", { AL, Ib }, 0 }, 2517 { "cmpS", { eAX, Iv }, 0 }, 2518 { Bad_Opcode }, /* SEG DS prefix */ 2519 { X86_64_TABLE (X86_64_3F) }, 2520 /* 40 */ 2521 { "inc{S|}", { RMeAX }, 0 }, 2522 { "inc{S|}", { RMeCX }, 0 }, 2523 { "inc{S|}", { RMeDX }, 0 }, 2524 { "inc{S|}", { RMeBX }, 0 }, 2525 { "inc{S|}", { RMeSP }, 0 }, 2526 { "inc{S|}", { RMeBP }, 0 }, 2527 { "inc{S|}", { RMeSI }, 0 }, 2528 { "inc{S|}", { RMeDI }, 0 }, 2529 /* 48 */ 2530 { "dec{S|}", { RMeAX }, 0 }, 2531 { "dec{S|}", { RMeCX }, 0 }, 2532 { "dec{S|}", { RMeDX }, 0 }, 2533 { "dec{S|}", { RMeBX }, 0 }, 2534 { "dec{S|}", { RMeSP }, 0 }, 2535 { "dec{S|}", { RMeBP }, 0 }, 2536 { "dec{S|}", { RMeSI }, 0 }, 2537 { "dec{S|}", { RMeDI }, 0 }, 2538 /* 50 */ 2539 { "pushV", { RMrAX }, 0 }, 2540 { "pushV", { RMrCX }, 0 }, 2541 { "pushV", { RMrDX }, 0 }, 2542 { "pushV", { RMrBX }, 0 }, 2543 { "pushV", { RMrSP }, 0 }, 2544 { "pushV", { RMrBP }, 0 }, 2545 { "pushV", { RMrSI }, 0 }, 2546 { "pushV", { RMrDI }, 0 }, 2547 /* 58 */ 2548 { "popV", { RMrAX }, 0 }, 2549 { "popV", { RMrCX }, 0 }, 2550 { "popV", { RMrDX }, 0 }, 2551 { "popV", { RMrBX }, 0 }, 2552 { "popV", { RMrSP }, 0 }, 2553 { "popV", { RMrBP }, 0 }, 2554 { "popV", { RMrSI }, 0 }, 2555 { "popV", { RMrDI }, 0 }, 2556 /* 60 */ 2557 { X86_64_TABLE (X86_64_60) }, 2558 { X86_64_TABLE (X86_64_61) }, 2559 { X86_64_TABLE (X86_64_62) }, 2560 { X86_64_TABLE (X86_64_63) }, 2561 { Bad_Opcode }, /* seg fs */ 2562 { Bad_Opcode }, /* seg gs */ 2563 { Bad_Opcode }, /* op size prefix */ 2564 { Bad_Opcode }, /* adr size prefix */ 2565 /* 68 */ 2566 { "pushT", { sIv }, 0 }, 2567 { "imulS", { Gv, Ev, Iv }, 0 }, 2568 { "pushT", { sIbT }, 0 }, 2569 { "imulS", { Gv, Ev, sIb }, 0 }, 2570 { "ins{b|}", { Ybr, indirDX }, 0 }, 2571 { X86_64_TABLE (X86_64_6D) }, 2572 { "outs{b|}", { indirDXr, Xb }, 0 }, 2573 { X86_64_TABLE (X86_64_6F) }, 2574 /* 70 */ 2575 { "joH", { Jb, BND, cond_jump_flag }, 0 }, 2576 { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, 2577 { "jbH", { Jb, BND, cond_jump_flag }, 0 }, 2578 { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, 2579 { "jeH", { Jb, BND, cond_jump_flag }, 0 }, 2580 { "jneH", { Jb, BND, cond_jump_flag }, 0 }, 2581 { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, 2582 { "jaH", { Jb, BND, cond_jump_flag }, 0 }, 2583 /* 78 */ 2584 { "jsH", { Jb, BND, cond_jump_flag }, 0 }, 2585 { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, 2586 { "jpH", { Jb, BND, cond_jump_flag }, 0 }, 2587 { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, 2588 { "jlH", { Jb, BND, cond_jump_flag }, 0 }, 2589 { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, 2590 { "jleH", { Jb, BND, cond_jump_flag }, 0 }, 2591 { "jgH", { Jb, BND, cond_jump_flag }, 0 }, 2592 /* 80 */ 2593 { REG_TABLE (REG_80) }, 2594 { REG_TABLE (REG_81) }, 2595 { Bad_Opcode }, 2596 { REG_TABLE (REG_82) }, 2597 { "testB", { Eb, Gb }, 0 }, 2598 { "testS", { Ev, Gv }, 0 }, 2599 { "xchgB", { Ebh2, Gb }, 0 }, 2600 { "xchgS", { Evh2, Gv }, 0 }, 2601 /* 88 */ 2602 { "movB", { Ebh3, Gb }, 0 }, 2603 { "movS", { Evh3, Gv }, 0 }, 2604 { "movB", { Gb, EbS }, 0 }, 2605 { "movS", { Gv, EvS }, 0 }, 2606 { "movD", { Sv, Sw }, 0 }, 2607 { MOD_TABLE (MOD_8D) }, 2608 { "movD", { Sw, Sv }, 0 }, 2609 { REG_TABLE (REG_8F) }, 2610 /* 90 */ 2611 { PREFIX_TABLE (PREFIX_90) }, 2612 { "xchgS", { RMeCX, eAX }, 0 }, 2613 { "xchgS", { RMeDX, eAX }, 0 }, 2614 { "xchgS", { RMeBX, eAX }, 0 }, 2615 { "xchgS", { RMeSP, eAX }, 0 }, 2616 { "xchgS", { RMeBP, eAX }, 0 }, 2617 { "xchgS", { RMeSI, eAX }, 0 }, 2618 { "xchgS", { RMeDI, eAX }, 0 }, 2619 /* 98 */ 2620 { "cW{t|}R", { XX }, 0 }, 2621 { "cR{t|}O", { XX }, 0 }, 2622 { X86_64_TABLE (X86_64_9A) }, 2623 { Bad_Opcode }, /* fwait */ 2624 { "pushfT", { XX }, 0 }, 2625 { "popfT", { XX }, 0 }, 2626 { "sahf", { XX }, 0 }, 2627 { "lahf", { XX }, 0 }, 2628 /* a0 */ 2629 { "mov%LB", { AL, Ob }, 0 }, 2630 { "mov%LS", { eAX, Ov }, 0 }, 2631 { "mov%LB", { Ob, AL }, 0 }, 2632 { "mov%LS", { Ov, eAX }, 0 }, 2633 { "movs{b|}", { Ybr, Xb }, 0 }, 2634 { "movs{R|}", { Yvr, Xv }, 0 }, 2635 { "cmps{b|}", { Xb, Yb }, 0 }, 2636 { "cmps{R|}", { Xv, Yv }, 0 }, 2637 /* a8 */ 2638 { "testB", { AL, Ib }, 0 }, 2639 { "testS", { eAX, Iv }, 0 }, 2640 { "stosB", { Ybr, AL }, 0 }, 2641 { "stosS", { Yvr, eAX }, 0 }, 2642 { "lodsB", { ALr, Xb }, 0 }, 2643 { "lodsS", { eAXr, Xv }, 0 }, 2644 { "scasB", { AL, Yb }, 0 }, 2645 { "scasS", { eAX, Yv }, 0 }, 2646 /* b0 */ 2647 { "movB", { RMAL, Ib }, 0 }, 2648 { "movB", { RMCL, Ib }, 0 }, 2649 { "movB", { RMDL, Ib }, 0 }, 2650 { "movB", { RMBL, Ib }, 0 }, 2651 { "movB", { RMAH, Ib }, 0 }, 2652 { "movB", { RMCH, Ib }, 0 }, 2653 { "movB", { RMDH, Ib }, 0 }, 2654 { "movB", { RMBH, Ib }, 0 }, 2655 /* b8 */ 2656 { "mov%LV", { RMeAX, Iv64 }, 0 }, 2657 { "mov%LV", { RMeCX, Iv64 }, 0 }, 2658 { "mov%LV", { RMeDX, Iv64 }, 0 }, 2659 { "mov%LV", { RMeBX, Iv64 }, 0 }, 2660 { "mov%LV", { RMeSP, Iv64 }, 0 }, 2661 { "mov%LV", { RMeBP, Iv64 }, 0 }, 2662 { "mov%LV", { RMeSI, Iv64 }, 0 }, 2663 { "mov%LV", { RMeDI, Iv64 }, 0 }, 2664 /* c0 */ 2665 { REG_TABLE (REG_C0) }, 2666 { REG_TABLE (REG_C1) }, 2667 { "retT", { Iw, BND }, 0 }, 2668 { "retT", { BND }, 0 }, 2669 { X86_64_TABLE (X86_64_C4) }, 2670 { X86_64_TABLE (X86_64_C5) }, 2671 { REG_TABLE (REG_C6) }, 2672 { REG_TABLE (REG_C7) }, 2673 /* c8 */ 2674 { "enterT", { Iw, Ib }, 0 }, 2675 { "leaveT", { XX }, 0 }, 2676 { "Jret{|f}P", { Iw }, 0 }, 2677 { "Jret{|f}P", { XX }, 0 }, 2678 { "int3", { XX }, 0 }, 2679 { "int", { Ib }, 0 }, 2680 { X86_64_TABLE (X86_64_CE) }, 2681 { "iret%LP", { XX }, 0 }, 2682 /* d0 */ 2683 { REG_TABLE (REG_D0) }, 2684 { REG_TABLE (REG_D1) }, 2685 { REG_TABLE (REG_D2) }, 2686 { REG_TABLE (REG_D3) }, 2687 { X86_64_TABLE (X86_64_D4) }, 2688 { X86_64_TABLE (X86_64_D5) }, 2689 { Bad_Opcode }, 2690 { "xlat", { DSBX }, 0 }, 2691 /* d8 */ 2692 { FLOAT }, 2693 { FLOAT }, 2694 { FLOAT }, 2695 { FLOAT }, 2696 { FLOAT }, 2697 { FLOAT }, 2698 { FLOAT }, 2699 { FLOAT }, 2700 /* e0 */ 2701 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, 2702 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, 2703 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, 2704 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, 2705 { "inB", { AL, Ib }, 0 }, 2706 { "inG", { zAX, Ib }, 0 }, 2707 { "outB", { Ib, AL }, 0 }, 2708 { "outG", { Ib, zAX }, 0 }, 2709 /* e8 */ 2710 { X86_64_TABLE (X86_64_E8) }, 2711 { X86_64_TABLE (X86_64_E9) }, 2712 { X86_64_TABLE (X86_64_EA) }, 2713 { "jmp", { Jb, BND }, 0 }, 2714 { "inB", { AL, indirDX }, 0 }, 2715 { "inG", { zAX, indirDX }, 0 }, 2716 { "outB", { indirDX, AL }, 0 }, 2717 { "outG", { indirDX, zAX }, 0 }, 2718 /* f0 */ 2719 { Bad_Opcode }, /* lock prefix */ 2720 { "icebp", { XX }, 0 }, 2721 { Bad_Opcode }, /* repne */ 2722 { Bad_Opcode }, /* repz */ 2723 { "hlt", { XX }, 0 }, 2724 { "cmc", { XX }, 0 }, 2725 { REG_TABLE (REG_F6) }, 2726 { REG_TABLE (REG_F7) }, 2727 /* f8 */ 2728 { "clc", { XX }, 0 }, 2729 { "stc", { XX }, 0 }, 2730 { "cli", { XX }, 0 }, 2731 { "sti", { XX }, 0 }, 2732 { "cld", { XX }, 0 }, 2733 { "std", { XX }, 0 }, 2734 { REG_TABLE (REG_FE) }, 2735 { REG_TABLE (REG_FF) }, 2736 }; 2737 2738 static const struct dis386 dis386_twobyte[] = { 2739 /* 00 */ 2740 { REG_TABLE (REG_0F00 ) }, 2741 { REG_TABLE (REG_0F01 ) }, 2742 { "larS", { Gv, Ew }, 0 }, 2743 { "lslS", { Gv, Ew }, 0 }, 2744 { Bad_Opcode }, 2745 { "syscall", { XX }, 0 }, 2746 { "clts", { XX }, 0 }, 2747 { "sysret%LP", { XX }, 0 }, 2748 /* 08 */ 2749 { "invd", { XX }, 0 }, 2750 { "wbinvd", { XX }, 0 }, 2751 { Bad_Opcode }, 2752 { "ud2", { XX }, 0 }, 2753 { Bad_Opcode }, 2754 { REG_TABLE (REG_0F0D) }, 2755 { "femms", { XX }, 0 }, 2756 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ 2757 /* 10 */ 2758 { PREFIX_TABLE (PREFIX_0F10) }, 2759 { PREFIX_TABLE (PREFIX_0F11) }, 2760 { PREFIX_TABLE (PREFIX_0F12) }, 2761 { MOD_TABLE (MOD_0F13) }, 2762 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, 2763 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, 2764 { PREFIX_TABLE (PREFIX_0F16) }, 2765 { MOD_TABLE (MOD_0F17) }, 2766 /* 18 */ 2767 { REG_TABLE (REG_0F18) }, 2768 { "nopQ", { Ev }, 0 }, 2769 { PREFIX_TABLE (PREFIX_0F1A) }, 2770 { PREFIX_TABLE (PREFIX_0F1B) }, 2771 { "nopQ", { Ev }, 0 }, 2772 { "nopQ", { Ev }, 0 }, 2773 { "nopQ", { Ev }, 0 }, 2774 { "nopQ", { Ev }, 0 }, 2775 /* 20 */ 2776 { "movZ", { Rm, Cm }, 0 }, 2777 { "movZ", { Rm, Dm }, 0 }, 2778 { "movZ", { Cm, Rm }, 0 }, 2779 { "movZ", { Dm, Rm }, 0 }, 2780 { MOD_TABLE (MOD_0F24) }, 2781 { Bad_Opcode }, 2782 { MOD_TABLE (MOD_0F26) }, 2783 { Bad_Opcode }, 2784 /* 28 */ 2785 { "movapX", { XM, EXx }, PREFIX_OPCODE }, 2786 { "movapX", { EXxS, XM }, PREFIX_OPCODE }, 2787 { PREFIX_TABLE (PREFIX_0F2A) }, 2788 { PREFIX_TABLE (PREFIX_0F2B) }, 2789 { PREFIX_TABLE (PREFIX_0F2C) }, 2790 { PREFIX_TABLE (PREFIX_0F2D) }, 2791 { PREFIX_TABLE (PREFIX_0F2E) }, 2792 { PREFIX_TABLE (PREFIX_0F2F) }, 2793 /* 30 */ 2794 { "wrmsr", { XX }, 0 }, 2795 { "rdtsc", { XX }, 0 }, 2796 { "rdmsr", { XX }, 0 }, 2797 { "rdpmc", { XX }, 0 }, 2798 { "sysenter", { XX }, 0 }, 2799 { "sysexit", { XX }, 0 }, 2800 { Bad_Opcode }, 2801 { "getsec", { XX }, 0 }, 2802 /* 38 */ 2803 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, 2804 { Bad_Opcode }, 2805 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, 2806 { Bad_Opcode }, 2807 { Bad_Opcode }, 2808 { Bad_Opcode }, 2809 { Bad_Opcode }, 2810 { Bad_Opcode }, 2811 /* 40 */ 2812 { "cmovoS", { Gv, Ev }, 0 }, 2813 { "cmovnoS", { Gv, Ev }, 0 }, 2814 { "cmovbS", { Gv, Ev }, 0 }, 2815 { "cmovaeS", { Gv, Ev }, 0 }, 2816 { "cmoveS", { Gv, Ev }, 0 }, 2817 { "cmovneS", { Gv, Ev }, 0 }, 2818 { "cmovbeS", { Gv, Ev }, 0 }, 2819 { "cmovaS", { Gv, Ev }, 0 }, 2820 /* 48 */ 2821 { "cmovsS", { Gv, Ev }, 0 }, 2822 { "cmovnsS", { Gv, Ev }, 0 }, 2823 { "cmovpS", { Gv, Ev }, 0 }, 2824 { "cmovnpS", { Gv, Ev }, 0 }, 2825 { "cmovlS", { Gv, Ev }, 0 }, 2826 { "cmovgeS", { Gv, Ev }, 0 }, 2827 { "cmovleS", { Gv, Ev }, 0 }, 2828 { "cmovgS", { Gv, Ev }, 0 }, 2829 /* 50 */ 2830 { MOD_TABLE (MOD_0F51) }, 2831 { PREFIX_TABLE (PREFIX_0F51) }, 2832 { PREFIX_TABLE (PREFIX_0F52) }, 2833 { PREFIX_TABLE (PREFIX_0F53) }, 2834 { "andpX", { XM, EXx }, PREFIX_OPCODE }, 2835 { "andnpX", { XM, EXx }, PREFIX_OPCODE }, 2836 { "orpX", { XM, EXx }, PREFIX_OPCODE }, 2837 { "xorpX", { XM, EXx }, PREFIX_OPCODE }, 2838 /* 58 */ 2839 { PREFIX_TABLE (PREFIX_0F58) }, 2840 { PREFIX_TABLE (PREFIX_0F59) }, 2841 { PREFIX_TABLE (PREFIX_0F5A) }, 2842 { PREFIX_TABLE (PREFIX_0F5B) }, 2843 { PREFIX_TABLE (PREFIX_0F5C) }, 2844 { PREFIX_TABLE (PREFIX_0F5D) }, 2845 { PREFIX_TABLE (PREFIX_0F5E) }, 2846 { PREFIX_TABLE (PREFIX_0F5F) }, 2847 /* 60 */ 2848 { PREFIX_TABLE (PREFIX_0F60) }, 2849 { PREFIX_TABLE (PREFIX_0F61) }, 2850 { PREFIX_TABLE (PREFIX_0F62) }, 2851 { "packsswb", { MX, EM }, PREFIX_OPCODE }, 2852 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, 2853 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, 2854 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, 2855 { "packuswb", { MX, EM }, PREFIX_OPCODE }, 2856 /* 68 */ 2857 { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, 2858 { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, 2859 { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, 2860 { "packssdw", { MX, EM }, PREFIX_OPCODE }, 2861 { PREFIX_TABLE (PREFIX_0F6C) }, 2862 { PREFIX_TABLE (PREFIX_0F6D) }, 2863 { "movK", { MX, Edq }, PREFIX_OPCODE }, 2864 { PREFIX_TABLE (PREFIX_0F6F) }, 2865 /* 70 */ 2866 { PREFIX_TABLE (PREFIX_0F70) }, 2867 { REG_TABLE (REG_0F71) }, 2868 { REG_TABLE (REG_0F72) }, 2869 { REG_TABLE (REG_0F73) }, 2870 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, 2871 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, 2872 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, 2873 { "emms", { XX }, PREFIX_OPCODE }, 2874 /* 78 */ 2875 { PREFIX_TABLE (PREFIX_0F78) }, 2876 { PREFIX_TABLE (PREFIX_0F79) }, 2877 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, 2878 { Bad_Opcode }, 2879 { PREFIX_TABLE (PREFIX_0F7C) }, 2880 { PREFIX_TABLE (PREFIX_0F7D) }, 2881 { PREFIX_TABLE (PREFIX_0F7E) }, 2882 { PREFIX_TABLE (PREFIX_0F7F) }, 2883 /* 80 */ 2884 { "joH", { Jv, BND, cond_jump_flag }, 0 }, 2885 { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, 2886 { "jbH", { Jv, BND, cond_jump_flag }, 0 }, 2887 { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, 2888 { "jeH", { Jv, BND, cond_jump_flag }, 0 }, 2889 { "jneH", { Jv, BND, cond_jump_flag }, 0 }, 2890 { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, 2891 { "jaH", { Jv, BND, cond_jump_flag }, 0 }, 2892 /* 88 */ 2893 { "jsH", { Jv, BND, cond_jump_flag }, 0 }, 2894 { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, 2895 { "jpH", { Jv, BND, cond_jump_flag }, 0 }, 2896 { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, 2897 { "jlH", { Jv, BND, cond_jump_flag }, 0 }, 2898 { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, 2899 { "jleH", { Jv, BND, cond_jump_flag }, 0 }, 2900 { "jgH", { Jv, BND, cond_jump_flag }, 0 }, 2901 /* 90 */ 2902 { "seto", { Eb }, 0 }, 2903 { "setno", { Eb }, 0 }, 2904 { "setb", { Eb }, 0 }, 2905 { "setae", { Eb }, 0 }, 2906 { "sete", { Eb }, 0 }, 2907 { "setne", { Eb }, 0 }, 2908 { "setbe", { Eb }, 0 }, 2909 { "seta", { Eb }, 0 }, 2910 /* 98 */ 2911 { "sets", { Eb }, 0 }, 2912 { "setns", { Eb }, 0 }, 2913 { "setp", { Eb }, 0 }, 2914 { "setnp", { Eb }, 0 }, 2915 { "setl", { Eb }, 0 }, 2916 { "setge", { Eb }, 0 }, 2917 { "setle", { Eb }, 0 }, 2918 { "setg", { Eb }, 0 }, 2919 /* a0 */ 2920 { "pushT", { fs }, 0 }, 2921 { "popT", { fs }, 0 }, 2922 { "cpuid", { XX }, 0 }, 2923 { "btS", { Ev, Gv }, 0 }, 2924 { "shldS", { Ev, Gv, Ib }, 0 }, 2925 { "shldS", { Ev, Gv, CL }, 0 }, 2926 { REG_TABLE (REG_0FA6) }, 2927 { REG_TABLE (REG_0FA7) }, 2928 /* a8 */ 2929 { "pushT", { gs }, 0 }, 2930 { "popT", { gs }, 0 }, 2931 { "rsm", { XX }, 0 }, 2932 { "btsS", { Evh1, Gv }, 0 }, 2933 { "shrdS", { Ev, Gv, Ib }, 0 }, 2934 { "shrdS", { Ev, Gv, CL }, 0 }, 2935 { REG_TABLE (REG_0FAE) }, 2936 { "imulS", { Gv, Ev }, 0 }, 2937 /* b0 */ 2938 { "cmpxchgB", { Ebh1, Gb }, 0 }, 2939 { "cmpxchgS", { Evh1, Gv }, 0 }, 2940 { MOD_TABLE (MOD_0FB2) }, 2941 { "btrS", { Evh1, Gv }, 0 }, 2942 { MOD_TABLE (MOD_0FB4) }, 2943 { MOD_TABLE (MOD_0FB5) }, 2944 { "movz{bR|x}", { Gv, Eb }, 0 }, 2945 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ 2946 /* b8 */ 2947 { PREFIX_TABLE (PREFIX_0FB8) }, 2948 { "ud1", { XX }, 0 }, 2949 { REG_TABLE (REG_0FBA) }, 2950 { "btcS", { Evh1, Gv }, 0 }, 2951 { PREFIX_TABLE (PREFIX_0FBC) }, 2952 { PREFIX_TABLE (PREFIX_0FBD) }, 2953 { "movs{bR|x}", { Gv, Eb }, 0 }, 2954 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ 2955 /* c0 */ 2956 { "xaddB", { Ebh1, Gb }, 0 }, 2957 { "xaddS", { Evh1, Gv }, 0 }, 2958 { PREFIX_TABLE (PREFIX_0FC2) }, 2959 { PREFIX_TABLE (PREFIX_0FC3) }, 2960 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, 2961 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, 2962 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, 2963 { REG_TABLE (REG_0FC7) }, 2964 /* c8 */ 2965 { "bswap", { RMeAX }, 0 }, 2966 { "bswap", { RMeCX }, 0 }, 2967 { "bswap", { RMeDX }, 0 }, 2968 { "bswap", { RMeBX }, 0 }, 2969 { "bswap", { RMeSP }, 0 }, 2970 { "bswap", { RMeBP }, 0 }, 2971 { "bswap", { RMeSI }, 0 }, 2972 { "bswap", { RMeDI }, 0 }, 2973 /* d0 */ 2974 { PREFIX_TABLE (PREFIX_0FD0) }, 2975 { "psrlw", { MX, EM }, PREFIX_OPCODE }, 2976 { "psrld", { MX, EM }, PREFIX_OPCODE }, 2977 { "psrlq", { MX, EM }, PREFIX_OPCODE }, 2978 { "paddq", { MX, EM }, PREFIX_OPCODE }, 2979 { "pmullw", { MX, EM }, PREFIX_OPCODE }, 2980 { PREFIX_TABLE (PREFIX_0FD6) }, 2981 { MOD_TABLE (MOD_0FD7) }, 2982 /* d8 */ 2983 { "psubusb", { MX, EM }, PREFIX_OPCODE }, 2984 { "psubusw", { MX, EM }, PREFIX_OPCODE }, 2985 { "pminub", { MX, EM }, PREFIX_OPCODE }, 2986 { "pand", { MX, EM }, PREFIX_OPCODE }, 2987 { "paddusb", { MX, EM }, PREFIX_OPCODE }, 2988 { "paddusw", { MX, EM }, PREFIX_OPCODE }, 2989 { "pmaxub", { MX, EM }, PREFIX_OPCODE }, 2990 { "pandn", { MX, EM }, PREFIX_OPCODE }, 2991 /* e0 */ 2992 { "pavgb", { MX, EM }, PREFIX_OPCODE }, 2993 { "psraw", { MX, EM }, PREFIX_OPCODE }, 2994 { "psrad", { MX, EM }, PREFIX_OPCODE }, 2995 { "pavgw", { MX, EM }, PREFIX_OPCODE }, 2996 { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, 2997 { "pmulhw", { MX, EM }, PREFIX_OPCODE }, 2998 { PREFIX_TABLE (PREFIX_0FE6) }, 2999 { PREFIX_TABLE (PREFIX_0FE7) }, 3000 /* e8 */ 3001 { "psubsb", { MX, EM }, PREFIX_OPCODE }, 3002 { "psubsw", { MX, EM }, PREFIX_OPCODE }, 3003 { "pminsw", { MX, EM }, PREFIX_OPCODE }, 3004 { "por", { MX, EM }, PREFIX_OPCODE }, 3005 { "paddsb", { MX, EM }, PREFIX_OPCODE }, 3006 { "paddsw", { MX, EM }, PREFIX_OPCODE }, 3007 { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, 3008 { "pxor", { MX, EM }, PREFIX_OPCODE }, 3009 /* f0 */ 3010 { PREFIX_TABLE (PREFIX_0FF0) }, 3011 { "psllw", { MX, EM }, PREFIX_OPCODE }, 3012 { "pslld", { MX, EM }, PREFIX_OPCODE }, 3013 { "psllq", { MX, EM }, PREFIX_OPCODE }, 3014 { "pmuludq", { MX, EM }, PREFIX_OPCODE }, 3015 { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, 3016 { "psadbw", { MX, EM }, PREFIX_OPCODE }, 3017 { PREFIX_TABLE (PREFIX_0FF7) }, 3018 /* f8 */ 3019 { "psubb", { MX, EM }, PREFIX_OPCODE }, 3020 { "psubw", { MX, EM }, PREFIX_OPCODE }, 3021 { "psubd", { MX, EM }, PREFIX_OPCODE }, 3022 { "psubq", { MX, EM }, PREFIX_OPCODE }, 3023 { "paddb", { MX, EM }, PREFIX_OPCODE }, 3024 { "paddw", { MX, EM }, PREFIX_OPCODE }, 3025 { "paddd", { MX, EM }, PREFIX_OPCODE }, 3026 { Bad_Opcode }, 3027 }; 3028 3029 static const unsigned char onebyte_has_modrm[256] = { 3030 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3031 /* ------------------------------- */ 3032 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 3033 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 3034 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 3035 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 3036 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 3037 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 3038 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 3039 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 3040 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 3041 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 3042 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 3043 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 3044 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 3045 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 3046 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 3047 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 3048 /* ------------------------------- */ 3049 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3050 }; 3051 3052 static const unsigned char twobyte_has_modrm[256] = { 3053 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3054 /* ------------------------------- */ 3055 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 3056 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 3057 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 3058 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 3059 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 3060 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 3061 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 3062 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 3063 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 3064 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 3065 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 3066 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 3067 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 3068 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 3069 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 3070 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 3071 /* ------------------------------- */ 3072 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3073 }; 3074 3075 static char obuf[100]; 3076 static char *obufp; 3077 static char *mnemonicendp; 3078 static char scratchbuf[100]; 3079 static unsigned char *start_codep; 3080 static unsigned char *insn_codep; 3081 static unsigned char *codep; 3082 static unsigned char *end_codep; 3083 static int last_lock_prefix; 3084 static int last_repz_prefix; 3085 static int last_repnz_prefix; 3086 static int last_data_prefix; 3087 static int last_addr_prefix; 3088 static int last_rex_prefix; 3089 static int last_seg_prefix; 3090 static int fwait_prefix; 3091 /* The active segment register prefix. */ 3092 static int active_seg_prefix; 3093 #define MAX_CODE_LENGTH 15 3094 /* We can up to 14 prefixes since the maximum instruction length is 3095 15bytes. */ 3096 static int all_prefixes[MAX_CODE_LENGTH - 1]; 3097 static disassemble_info *the_info; 3098 static struct 3099 { 3100 int mod; 3101 int reg; 3102 int rm; 3103 } 3104 modrm; 3105 static unsigned char need_modrm; 3106 static struct 3107 { 3108 int scale; 3109 int index; 3110 int base; 3111 } 3112 sib; 3113 static struct 3114 { 3115 int register_specifier; 3116 int length; 3117 int prefix; 3118 int w; 3119 int evex; 3120 int r; 3121 int v; 3122 int mask_register_specifier; 3123 int zeroing; 3124 int ll; 3125 int b; 3126 } 3127 vex; 3128 static unsigned char need_vex; 3129 static unsigned char need_vex_reg; 3130 static unsigned char vex_w_done; 3131 3132 struct op 3133 { 3134 const char *name; 3135 unsigned int len; 3136 }; 3137 3138 /* If we are accessing mod/rm/reg without need_modrm set, then the 3139 values are stale. Hitting this abort likely indicates that you 3140 need to update onebyte_has_modrm or twobyte_has_modrm. */ 3141 #define MODRM_CHECK if (!need_modrm) abort () 3142 3143 static const char **names64; 3144 static const char **names32; 3145 static const char **names16; 3146 static const char **names8; 3147 static const char **names8rex; 3148 static const char **names_seg; 3149 static const char *index64; 3150 static const char *index32; 3151 static const char **index16; 3152 static const char **names_bnd; 3153 3154 static const char *intel_names64[] = { 3155 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 3156 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3157 }; 3158 static const char *intel_names32[] = { 3159 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", 3160 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 3161 }; 3162 static const char *intel_names16[] = { 3163 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", 3164 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 3165 }; 3166 static const char *intel_names8[] = { 3167 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", 3168 }; 3169 static const char *intel_names8rex[] = { 3170 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", 3171 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" 3172 }; 3173 static const char *intel_names_seg[] = { 3174 "es", "cs", "ss", "ds", "fs", "gs", "?", "?", 3175 }; 3176 static const char *intel_index64 = "riz"; 3177 static const char *intel_index32 = "eiz"; 3178 static const char *intel_index16[] = { 3179 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 3180 }; 3181 3182 static const char *att_names64[] = { 3183 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 3184 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 3185 }; 3186 static const char *att_names32[] = { 3187 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 3188 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 3189 }; 3190 static const char *att_names16[] = { 3191 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 3192 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 3193 }; 3194 static const char *att_names8[] = { 3195 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 3196 }; 3197 static const char *att_names8rex[] = { 3198 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 3199 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 3200 }; 3201 static const char *att_names_seg[] = { 3202 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 3203 }; 3204 static const char *att_index64 = "%riz"; 3205 static const char *att_index32 = "%eiz"; 3206 static const char *att_index16[] = { 3207 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 3208 }; 3209 3210 static const char **names_mm; 3211 static const char *intel_names_mm[] = { 3212 "mm0", "mm1", "mm2", "mm3", 3213 "mm4", "mm5", "mm6", "mm7" 3214 }; 3215 static const char *att_names_mm[] = { 3216 "%mm0", "%mm1", "%mm2", "%mm3", 3217 "%mm4", "%mm5", "%mm6", "%mm7" 3218 }; 3219 3220 static const char *intel_names_bnd[] = { 3221 "bnd0", "bnd1", "bnd2", "bnd3" 3222 }; 3223 3224 static const char *att_names_bnd[] = { 3225 "%bnd0", "%bnd1", "%bnd2", "%bnd3" 3226 }; 3227 3228 static const char **names_xmm; 3229 static const char *intel_names_xmm[] = { 3230 "xmm0", "xmm1", "xmm2", "xmm3", 3231 "xmm4", "xmm5", "xmm6", "xmm7", 3232 "xmm8", "xmm9", "xmm10", "xmm11", 3233 "xmm12", "xmm13", "xmm14", "xmm15", 3234 "xmm16", "xmm17", "xmm18", "xmm19", 3235 "xmm20", "xmm21", "xmm22", "xmm23", 3236 "xmm24", "xmm25", "xmm26", "xmm27", 3237 "xmm28", "xmm29", "xmm30", "xmm31" 3238 }; 3239 static const char *att_names_xmm[] = { 3240 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 3241 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 3242 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 3243 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 3244 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 3245 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 3246 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 3247 "%xmm28", "%xmm29", "%xmm30", "%xmm31" 3248 }; 3249 3250 static const char **names_ymm; 3251 static const char *intel_names_ymm[] = { 3252 "ymm0", "ymm1", "ymm2", "ymm3", 3253 "ymm4", "ymm5", "ymm6", "ymm7", 3254 "ymm8", "ymm9", "ymm10", "ymm11", 3255 "ymm12", "ymm13", "ymm14", "ymm15", 3256 "ymm16", "ymm17", "ymm18", "ymm19", 3257 "ymm20", "ymm21", "ymm22", "ymm23", 3258 "ymm24", "ymm25", "ymm26", "ymm27", 3259 "ymm28", "ymm29", "ymm30", "ymm31" 3260 }; 3261 static const char *att_names_ymm[] = { 3262 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 3263 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 3264 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 3265 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 3266 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 3267 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 3268 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 3269 "%ymm28", "%ymm29", "%ymm30", "%ymm31" 3270 }; 3271 3272 static const char **names_zmm; 3273 static const char *intel_names_zmm[] = { 3274 "zmm0", "zmm1", "zmm2", "zmm3", 3275 "zmm4", "zmm5", "zmm6", "zmm7", 3276 "zmm8", "zmm9", "zmm10", "zmm11", 3277 "zmm12", "zmm13", "zmm14", "zmm15", 3278 "zmm16", "zmm17", "zmm18", "zmm19", 3279 "zmm20", "zmm21", "zmm22", "zmm23", 3280 "zmm24", "zmm25", "zmm26", "zmm27", 3281 "zmm28", "zmm29", "zmm30", "zmm31" 3282 }; 3283 static const char *att_names_zmm[] = { 3284 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 3285 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 3286 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 3287 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 3288 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 3289 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 3290 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 3291 "%zmm28", "%zmm29", "%zmm30", "%zmm31" 3292 }; 3293 3294 static const char **names_mask; 3295 static const char *intel_names_mask[] = { 3296 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" 3297 }; 3298 static const char *att_names_mask[] = { 3299 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 3300 }; 3301 3302 static const char *names_rounding[] = 3303 { 3304 "{rn-sae}", 3305 "{rd-sae}", 3306 "{ru-sae}", 3307 "{rz-sae}" 3308 }; 3309 3310 static const struct dis386 reg_table[][8] = { 3311 /* REG_80 */ 3312 { 3313 { "addA", { Ebh1, Ib }, 0 }, 3314 { "orA", { Ebh1, Ib }, 0 }, 3315 { "adcA", { Ebh1, Ib }, 0 }, 3316 { "sbbA", { Ebh1, Ib }, 0 }, 3317 { "andA", { Ebh1, Ib }, 0 }, 3318 { "subA", { Ebh1, Ib }, 0 }, 3319 { "xorA", { Ebh1, Ib }, 0 }, 3320 { "cmpA", { Eb, Ib }, 0 }, 3321 }, 3322 /* REG_81 */ 3323 { 3324 { "addQ", { Evh1, Iv }, 0 }, 3325 { "orQ", { Evh1, Iv }, 0 }, 3326 { "adcQ", { Evh1, Iv }, 0 }, 3327 { "sbbQ", { Evh1, Iv }, 0 }, 3328 { "andQ", { Evh1, Iv }, 0 }, 3329 { "subQ", { Evh1, Iv }, 0 }, 3330 { "xorQ", { Evh1, Iv }, 0 }, 3331 { "cmpQ", { Ev, Iv }, 0 }, 3332 }, 3333 /* REG_82 */ 3334 { 3335 { "addQ", { Evh1, sIb }, 0 }, 3336 { "orQ", { Evh1, sIb }, 0 }, 3337 { "adcQ", { Evh1, sIb }, 0 }, 3338 { "sbbQ", { Evh1, sIb }, 0 }, 3339 { "andQ", { Evh1, sIb }, 0 }, 3340 { "subQ", { Evh1, sIb }, 0 }, 3341 { "xorQ", { Evh1, sIb }, 0 }, 3342 { "cmpQ", { Ev, sIb }, 0 }, 3343 }, 3344 /* REG_8F */ 3345 { 3346 { "popU", { stackEv }, 0 }, 3347 { XOP_8F_TABLE (XOP_09) }, 3348 { Bad_Opcode }, 3349 { Bad_Opcode }, 3350 { Bad_Opcode }, 3351 { XOP_8F_TABLE (XOP_09) }, 3352 }, 3353 /* REG_C0 */ 3354 { 3355 { "rolA", { Eb, Ib }, 0 }, 3356 { "rorA", { Eb, Ib }, 0 }, 3357 { "rclA", { Eb, Ib }, 0 }, 3358 { "rcrA", { Eb, Ib }, 0 }, 3359 { "shlA", { Eb, Ib }, 0 }, 3360 { "shrA", { Eb, Ib }, 0 }, 3361 { Bad_Opcode }, 3362 { "sarA", { Eb, Ib }, 0 }, 3363 }, 3364 /* REG_C1 */ 3365 { 3366 { "rolQ", { Ev, Ib }, 0 }, 3367 { "rorQ", { Ev, Ib }, 0 }, 3368 { "rclQ", { Ev, Ib }, 0 }, 3369 { "rcrQ", { Ev, Ib }, 0 }, 3370 { "shlQ", { Ev, Ib }, 0 }, 3371 { "shrQ", { Ev, Ib }, 0 }, 3372 { Bad_Opcode }, 3373 { "sarQ", { Ev, Ib }, 0 }, 3374 }, 3375 /* REG_C6 */ 3376 { 3377 { "movA", { Ebh3, Ib }, 0 }, 3378 { Bad_Opcode }, 3379 { Bad_Opcode }, 3380 { Bad_Opcode }, 3381 { Bad_Opcode }, 3382 { Bad_Opcode }, 3383 { Bad_Opcode }, 3384 { MOD_TABLE (MOD_C6_REG_7) }, 3385 }, 3386 /* REG_C7 */ 3387 { 3388 { "movQ", { Evh3, Iv }, 0 }, 3389 { Bad_Opcode }, 3390 { Bad_Opcode }, 3391 { Bad_Opcode }, 3392 { Bad_Opcode }, 3393 { Bad_Opcode }, 3394 { Bad_Opcode }, 3395 { MOD_TABLE (MOD_C7_REG_7) }, 3396 }, 3397 /* REG_D0 */ 3398 { 3399 { "rolA", { Eb, I1 }, 0 }, 3400 { "rorA", { Eb, I1 }, 0 }, 3401 { "rclA", { Eb, I1 }, 0 }, 3402 { "rcrA", { Eb, I1 }, 0 }, 3403 { "shlA", { Eb, I1 }, 0 }, 3404 { "shrA", { Eb, I1 }, 0 }, 3405 { Bad_Opcode }, 3406 { "sarA", { Eb, I1 }, 0 }, 3407 }, 3408 /* REG_D1 */ 3409 { 3410 { "rolQ", { Ev, I1 }, 0 }, 3411 { "rorQ", { Ev, I1 }, 0 }, 3412 { "rclQ", { Ev, I1 }, 0 }, 3413 { "rcrQ", { Ev, I1 }, 0 }, 3414 { "shlQ", { Ev, I1 }, 0 }, 3415 { "shrQ", { Ev, I1 }, 0 }, 3416 { Bad_Opcode }, 3417 { "sarQ", { Ev, I1 }, 0 }, 3418 }, 3419 /* REG_D2 */ 3420 { 3421 { "rolA", { Eb, CL }, 0 }, 3422 { "rorA", { Eb, CL }, 0 }, 3423 { "rclA", { Eb, CL }, 0 }, 3424 { "rcrA", { Eb, CL }, 0 }, 3425 { "shlA", { Eb, CL }, 0 }, 3426 { "shrA", { Eb, CL }, 0 }, 3427 { Bad_Opcode }, 3428 { "sarA", { Eb, CL }, 0 }, 3429 }, 3430 /* REG_D3 */ 3431 { 3432 { "rolQ", { Ev, CL }, 0 }, 3433 { "rorQ", { Ev, CL }, 0 }, 3434 { "rclQ", { Ev, CL }, 0 }, 3435 { "rcrQ", { Ev, CL }, 0 }, 3436 { "shlQ", { Ev, CL }, 0 }, 3437 { "shrQ", { Ev, CL }, 0 }, 3438 { Bad_Opcode }, 3439 { "sarQ", { Ev, CL }, 0 }, 3440 }, 3441 /* REG_F6 */ 3442 { 3443 { "testA", { Eb, Ib }, 0 }, 3444 { Bad_Opcode }, 3445 { "notA", { Ebh1 }, 0 }, 3446 { "negA", { Ebh1 }, 0 }, 3447 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ 3448 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ 3449 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ 3450 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ 3451 }, 3452 /* REG_F7 */ 3453 { 3454 { "testQ", { Ev, Iv }, 0 }, 3455 { Bad_Opcode }, 3456 { "notQ", { Evh1 }, 0 }, 3457 { "negQ", { Evh1 }, 0 }, 3458 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ 3459 { "imulQ", { Ev }, 0 }, 3460 { "divQ", { Ev }, 0 }, 3461 { "idivQ", { Ev }, 0 }, 3462 }, 3463 /* REG_FE */ 3464 { 3465 { "incA", { Ebh1 }, 0 }, 3466 { "decA", { Ebh1 }, 0 }, 3467 }, 3468 /* REG_FF */ 3469 { 3470 { "incQ", { Evh1 }, 0 }, 3471 { "decQ", { Evh1 }, 0 }, 3472 { "call{T|}", { indirEv, BND }, 0 }, 3473 { MOD_TABLE (MOD_FF_REG_3) }, 3474 { "jmp{T|}", { indirEv, BND }, 0 }, 3475 { MOD_TABLE (MOD_FF_REG_5) }, 3476 { "pushU", { stackEv }, 0 }, 3477 { Bad_Opcode }, 3478 }, 3479 /* REG_0F00 */ 3480 { 3481 { "sldtD", { Sv }, 0 }, 3482 { "strD", { Sv }, 0 }, 3483 { "lldt", { Ew }, 0 }, 3484 { "ltr", { Ew }, 0 }, 3485 { "verr", { Ew }, 0 }, 3486 { "verw", { Ew }, 0 }, 3487 { Bad_Opcode }, 3488 { Bad_Opcode }, 3489 }, 3490 /* REG_0F01 */ 3491 { 3492 { MOD_TABLE (MOD_0F01_REG_0) }, 3493 { MOD_TABLE (MOD_0F01_REG_1) }, 3494 { MOD_TABLE (MOD_0F01_REG_2) }, 3495 { MOD_TABLE (MOD_0F01_REG_3) }, 3496 { "smswD", { Sv }, 0 }, 3497 { Bad_Opcode }, 3498 { "lmsw", { Ew }, 0 }, 3499 { MOD_TABLE (MOD_0F01_REG_7) }, 3500 }, 3501 /* REG_0F0D */ 3502 { 3503 { "prefetch", { Mb }, 0 }, 3504 { "prefetchw", { Mb }, 0 }, 3505 { "prefetchwt1", { Mb }, 0 }, 3506 { "prefetch", { Mb }, 0 }, 3507 { "prefetch", { Mb }, 0 }, 3508 { "prefetch", { Mb }, 0 }, 3509 { "prefetch", { Mb }, 0 }, 3510 { "prefetch", { Mb }, 0 }, 3511 }, 3512 /* REG_0F18 */ 3513 { 3514 { MOD_TABLE (MOD_0F18_REG_0) }, 3515 { MOD_TABLE (MOD_0F18_REG_1) }, 3516 { MOD_TABLE (MOD_0F18_REG_2) }, 3517 { MOD_TABLE (MOD_0F18_REG_3) }, 3518 { MOD_TABLE (MOD_0F18_REG_4) }, 3519 { MOD_TABLE (MOD_0F18_REG_5) }, 3520 { MOD_TABLE (MOD_0F18_REG_6) }, 3521 { MOD_TABLE (MOD_0F18_REG_7) }, 3522 }, 3523 /* REG_0F71 */ 3524 { 3525 { Bad_Opcode }, 3526 { Bad_Opcode }, 3527 { MOD_TABLE (MOD_0F71_REG_2) }, 3528 { Bad_Opcode }, 3529 { MOD_TABLE (MOD_0F71_REG_4) }, 3530 { Bad_Opcode }, 3531 { MOD_TABLE (MOD_0F71_REG_6) }, 3532 }, 3533 /* REG_0F72 */ 3534 { 3535 { Bad_Opcode }, 3536 { Bad_Opcode }, 3537 { MOD_TABLE (MOD_0F72_REG_2) }, 3538 { Bad_Opcode }, 3539 { MOD_TABLE (MOD_0F72_REG_4) }, 3540 { Bad_Opcode }, 3541 { MOD_TABLE (MOD_0F72_REG_6) }, 3542 }, 3543 /* REG_0F73 */ 3544 { 3545 { Bad_Opcode }, 3546 { Bad_Opcode }, 3547 { MOD_TABLE (MOD_0F73_REG_2) }, 3548 { MOD_TABLE (MOD_0F73_REG_3) }, 3549 { Bad_Opcode }, 3550 { Bad_Opcode }, 3551 { MOD_TABLE (MOD_0F73_REG_6) }, 3552 { MOD_TABLE (MOD_0F73_REG_7) }, 3553 }, 3554 /* REG_0FA6 */ 3555 { 3556 { "montmul", { { OP_0f07, 0 } }, 0 }, 3557 { "xsha1", { { OP_0f07, 0 } }, 0 }, 3558 { "xsha256", { { OP_0f07, 0 } }, 0 }, 3559 }, 3560 /* REG_0FA7 */ 3561 { 3562 { "xstore-rng", { { OP_0f07, 0 } }, 0 }, 3563 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, 3564 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, 3565 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, 3566 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, 3567 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, 3568 }, 3569 /* REG_0FAE */ 3570 { 3571 { MOD_TABLE (MOD_0FAE_REG_0) }, 3572 { MOD_TABLE (MOD_0FAE_REG_1) }, 3573 { MOD_TABLE (MOD_0FAE_REG_2) }, 3574 { MOD_TABLE (MOD_0FAE_REG_3) }, 3575 { MOD_TABLE (MOD_0FAE_REG_4) }, 3576 { MOD_TABLE (MOD_0FAE_REG_5) }, 3577 { MOD_TABLE (MOD_0FAE_REG_6) }, 3578 { MOD_TABLE (MOD_0FAE_REG_7) }, 3579 }, 3580 /* REG_0FBA */ 3581 { 3582 { Bad_Opcode }, 3583 { Bad_Opcode }, 3584 { Bad_Opcode }, 3585 { Bad_Opcode }, 3586 { "btQ", { Ev, Ib }, 0 }, 3587 { "btsQ", { Evh1, Ib }, 0 }, 3588 { "btrQ", { Evh1, Ib }, 0 }, 3589 { "btcQ", { Evh1, Ib }, 0 }, 3590 }, 3591 /* REG_0FC7 */ 3592 { 3593 { Bad_Opcode }, 3594 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, 3595 { Bad_Opcode }, 3596 { MOD_TABLE (MOD_0FC7_REG_3) }, 3597 { MOD_TABLE (MOD_0FC7_REG_4) }, 3598 { MOD_TABLE (MOD_0FC7_REG_5) }, 3599 { MOD_TABLE (MOD_0FC7_REG_6) }, 3600 { MOD_TABLE (MOD_0FC7_REG_7) }, 3601 }, 3602 /* REG_VEX_0F71 */ 3603 { 3604 { Bad_Opcode }, 3605 { Bad_Opcode }, 3606 { MOD_TABLE (MOD_VEX_0F71_REG_2) }, 3607 { Bad_Opcode }, 3608 { MOD_TABLE (MOD_VEX_0F71_REG_4) }, 3609 { Bad_Opcode }, 3610 { MOD_TABLE (MOD_VEX_0F71_REG_6) }, 3611 }, 3612 /* REG_VEX_0F72 */ 3613 { 3614 { Bad_Opcode }, 3615 { Bad_Opcode }, 3616 { MOD_TABLE (MOD_VEX_0F72_REG_2) }, 3617 { Bad_Opcode }, 3618 { MOD_TABLE (MOD_VEX_0F72_REG_4) }, 3619 { Bad_Opcode }, 3620 { MOD_TABLE (MOD_VEX_0F72_REG_6) }, 3621 }, 3622 /* REG_VEX_0F73 */ 3623 { 3624 { Bad_Opcode }, 3625 { Bad_Opcode }, 3626 { MOD_TABLE (MOD_VEX_0F73_REG_2) }, 3627 { MOD_TABLE (MOD_VEX_0F73_REG_3) }, 3628 { Bad_Opcode }, 3629 { Bad_Opcode }, 3630 { MOD_TABLE (MOD_VEX_0F73_REG_6) }, 3631 { MOD_TABLE (MOD_VEX_0F73_REG_7) }, 3632 }, 3633 /* REG_VEX_0FAE */ 3634 { 3635 { Bad_Opcode }, 3636 { Bad_Opcode }, 3637 { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, 3638 { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, 3639 }, 3640 /* REG_VEX_0F38F3 */ 3641 { 3642 { Bad_Opcode }, 3643 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, 3644 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, 3645 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, 3646 }, 3647 /* REG_XOP_LWPCB */ 3648 { 3649 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, 3650 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, 3651 }, 3652 /* REG_XOP_LWP */ 3653 { 3654 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, 3655 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, 3656 }, 3657 /* REG_XOP_TBM_01 */ 3658 { 3659 { Bad_Opcode }, 3660 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, 3661 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, 3662 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, 3663 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, 3664 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, 3665 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, 3666 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, 3667 }, 3668 /* REG_XOP_TBM_02 */ 3669 { 3670 { Bad_Opcode }, 3671 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, 3672 { Bad_Opcode }, 3673 { Bad_Opcode }, 3674 { Bad_Opcode }, 3675 { Bad_Opcode }, 3676 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, 3677 }, 3678 #define NEED_REG_TABLE 3679 #include "i386-dis-evex.h" 3680 #undef NEED_REG_TABLE 3681 }; 3682 3683 static const struct dis386 prefix_table[][4] = { 3684 /* PREFIX_90 */ 3685 { 3686 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, 3687 { "pause", { XX }, 0 }, 3688 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, 3689 { NULL, { { NULL, 0 } }, PREFIX_IGNORED } 3690 }, 3691 3692 /* PREFIX_0F10 */ 3693 { 3694 { "movups", { XM, EXx }, PREFIX_OPCODE }, 3695 { "movss", { XM, EXd }, PREFIX_OPCODE }, 3696 { "movupd", { XM, EXx }, PREFIX_OPCODE }, 3697 { "movsd", { XM, EXq }, PREFIX_OPCODE }, 3698 }, 3699 3700 /* PREFIX_0F11 */ 3701 { 3702 { "movups", { EXxS, XM }, PREFIX_OPCODE }, 3703 { "movss", { EXdS, XM }, PREFIX_OPCODE }, 3704 { "movupd", { EXxS, XM }, PREFIX_OPCODE }, 3705 { "movsd", { EXqS, XM }, PREFIX_OPCODE }, 3706 }, 3707 3708 /* PREFIX_0F12 */ 3709 { 3710 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 3711 { "movsldup", { XM, EXx }, PREFIX_OPCODE }, 3712 { "movlpd", { XM, EXq }, PREFIX_OPCODE }, 3713 { "movddup", { XM, EXq }, PREFIX_OPCODE }, 3714 }, 3715 3716 /* PREFIX_0F16 */ 3717 { 3718 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 3719 { "movshdup", { XM, EXx }, PREFIX_OPCODE }, 3720 { "movhpd", { XM, EXq }, PREFIX_OPCODE }, 3721 }, 3722 3723 /* PREFIX_0F1A */ 3724 { 3725 { MOD_TABLE (MOD_0F1A_PREFIX_0) }, 3726 { "bndcl", { Gbnd, Ev_bnd }, 0 }, 3727 { "bndmov", { Gbnd, Ebnd }, 0 }, 3728 { "bndcu", { Gbnd, Ev_bnd }, 0 }, 3729 }, 3730 3731 /* PREFIX_0F1B */ 3732 { 3733 { MOD_TABLE (MOD_0F1B_PREFIX_0) }, 3734 { MOD_TABLE (MOD_0F1B_PREFIX_1) }, 3735 { "bndmov", { Ebnd, Gbnd }, 0 }, 3736 { "bndcn", { Gbnd, Ev_bnd }, 0 }, 3737 }, 3738 3739 /* PREFIX_0F2A */ 3740 { 3741 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, 3742 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, 3743 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, 3744 { "cvtsi2sd%LQ", { XM, Ev }, 0 }, 3745 }, 3746 3747 /* PREFIX_0F2B */ 3748 { 3749 { MOD_TABLE (MOD_0F2B_PREFIX_0) }, 3750 { MOD_TABLE (MOD_0F2B_PREFIX_1) }, 3751 { MOD_TABLE (MOD_0F2B_PREFIX_2) }, 3752 { MOD_TABLE (MOD_0F2B_PREFIX_3) }, 3753 }, 3754 3755 /* PREFIX_0F2C */ 3756 { 3757 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3758 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, 3759 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3760 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, 3761 }, 3762 3763 /* PREFIX_0F2D */ 3764 { 3765 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, 3766 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, 3767 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, 3768 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, 3769 }, 3770 3771 /* PREFIX_0F2E */ 3772 { 3773 { "ucomiss",{ XM, EXd }, 0 }, 3774 { Bad_Opcode }, 3775 { "ucomisd",{ XM, EXq }, 0 }, 3776 }, 3777 3778 /* PREFIX_0F2F */ 3779 { 3780 { "comiss", { XM, EXd }, 0 }, 3781 { Bad_Opcode }, 3782 { "comisd", { XM, EXq }, 0 }, 3783 }, 3784 3785 /* PREFIX_0F51 */ 3786 { 3787 { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, 3788 { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, 3789 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, 3790 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, 3791 }, 3792 3793 /* PREFIX_0F52 */ 3794 { 3795 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, 3796 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, 3797 }, 3798 3799 /* PREFIX_0F53 */ 3800 { 3801 { "rcpps", { XM, EXx }, PREFIX_OPCODE }, 3802 { "rcpss", { XM, EXd }, PREFIX_OPCODE }, 3803 }, 3804 3805 /* PREFIX_0F58 */ 3806 { 3807 { "addps", { XM, EXx }, PREFIX_OPCODE }, 3808 { "addss", { XM, EXd }, PREFIX_OPCODE }, 3809 { "addpd", { XM, EXx }, PREFIX_OPCODE }, 3810 { "addsd", { XM, EXq }, PREFIX_OPCODE }, 3811 }, 3812 3813 /* PREFIX_0F59 */ 3814 { 3815 { "mulps", { XM, EXx }, PREFIX_OPCODE }, 3816 { "mulss", { XM, EXd }, PREFIX_OPCODE }, 3817 { "mulpd", { XM, EXx }, PREFIX_OPCODE }, 3818 { "mulsd", { XM, EXq }, PREFIX_OPCODE }, 3819 }, 3820 3821 /* PREFIX_0F5A */ 3822 { 3823 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, 3824 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, 3825 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, 3826 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, 3827 }, 3828 3829 /* PREFIX_0F5B */ 3830 { 3831 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, 3832 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, 3833 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, 3834 }, 3835 3836 /* PREFIX_0F5C */ 3837 { 3838 { "subps", { XM, EXx }, PREFIX_OPCODE }, 3839 { "subss", { XM, EXd }, PREFIX_OPCODE }, 3840 { "subpd", { XM, EXx }, PREFIX_OPCODE }, 3841 { "subsd", { XM, EXq }, PREFIX_OPCODE }, 3842 }, 3843 3844 /* PREFIX_0F5D */ 3845 { 3846 { "minps", { XM, EXx }, PREFIX_OPCODE }, 3847 { "minss", { XM, EXd }, PREFIX_OPCODE }, 3848 { "minpd", { XM, EXx }, PREFIX_OPCODE }, 3849 { "minsd", { XM, EXq }, PREFIX_OPCODE }, 3850 }, 3851 3852 /* PREFIX_0F5E */ 3853 { 3854 { "divps", { XM, EXx }, PREFIX_OPCODE }, 3855 { "divss", { XM, EXd }, PREFIX_OPCODE }, 3856 { "divpd", { XM, EXx }, PREFIX_OPCODE }, 3857 { "divsd", { XM, EXq }, PREFIX_OPCODE }, 3858 }, 3859 3860 /* PREFIX_0F5F */ 3861 { 3862 { "maxps", { XM, EXx }, PREFIX_OPCODE }, 3863 { "maxss", { XM, EXd }, PREFIX_OPCODE }, 3864 { "maxpd", { XM, EXx }, PREFIX_OPCODE }, 3865 { "maxsd", { XM, EXq }, PREFIX_OPCODE }, 3866 }, 3867 3868 /* PREFIX_0F60 */ 3869 { 3870 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, 3871 { Bad_Opcode }, 3872 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, 3873 }, 3874 3875 /* PREFIX_0F61 */ 3876 { 3877 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, 3878 { Bad_Opcode }, 3879 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, 3880 }, 3881 3882 /* PREFIX_0F62 */ 3883 { 3884 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, 3885 { Bad_Opcode }, 3886 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, 3887 }, 3888 3889 /* PREFIX_0F6C */ 3890 { 3891 { Bad_Opcode }, 3892 { Bad_Opcode }, 3893 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, 3894 }, 3895 3896 /* PREFIX_0F6D */ 3897 { 3898 { Bad_Opcode }, 3899 { Bad_Opcode }, 3900 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, 3901 }, 3902 3903 /* PREFIX_0F6F */ 3904 { 3905 { "movq", { MX, EM }, PREFIX_OPCODE }, 3906 { "movdqu", { XM, EXx }, PREFIX_OPCODE }, 3907 { "movdqa", { XM, EXx }, PREFIX_OPCODE }, 3908 }, 3909 3910 /* PREFIX_0F70 */ 3911 { 3912 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, 3913 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3914 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, 3915 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, 3916 }, 3917 3918 /* PREFIX_0F73_REG_3 */ 3919 { 3920 { Bad_Opcode }, 3921 { Bad_Opcode }, 3922 { "psrldq", { XS, Ib }, 0 }, 3923 }, 3924 3925 /* PREFIX_0F73_REG_7 */ 3926 { 3927 { Bad_Opcode }, 3928 { Bad_Opcode }, 3929 { "pslldq", { XS, Ib }, 0 }, 3930 }, 3931 3932 /* PREFIX_0F78 */ 3933 { 3934 {"vmread", { Em, Gm }, 0 }, 3935 { Bad_Opcode }, 3936 {"extrq", { XS, Ib, Ib }, 0 }, 3937 {"insertq", { XM, XS, Ib, Ib }, 0 }, 3938 }, 3939 3940 /* PREFIX_0F79 */ 3941 { 3942 {"vmwrite", { Gm, Em }, 0 }, 3943 { Bad_Opcode }, 3944 {"extrq", { XM, XS }, 0 }, 3945 {"insertq", { XM, XS }, 0 }, 3946 }, 3947 3948 /* PREFIX_0F7C */ 3949 { 3950 { Bad_Opcode }, 3951 { Bad_Opcode }, 3952 { "haddpd", { XM, EXx }, PREFIX_OPCODE }, 3953 { "haddps", { XM, EXx }, PREFIX_OPCODE }, 3954 }, 3955 3956 /* PREFIX_0F7D */ 3957 { 3958 { Bad_Opcode }, 3959 { Bad_Opcode }, 3960 { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, 3961 { "hsubps", { XM, EXx }, PREFIX_OPCODE }, 3962 }, 3963 3964 /* PREFIX_0F7E */ 3965 { 3966 { "movK", { Edq, MX }, PREFIX_OPCODE }, 3967 { "movq", { XM, EXq }, PREFIX_OPCODE }, 3968 { "movK", { Edq, XM }, PREFIX_OPCODE }, 3969 }, 3970 3971 /* PREFIX_0F7F */ 3972 { 3973 { "movq", { EMS, MX }, PREFIX_OPCODE }, 3974 { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, 3975 { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, 3976 }, 3977 3978 /* PREFIX_0FAE_REG_0 */ 3979 { 3980 { Bad_Opcode }, 3981 { "rdfsbase", { Ev }, 0 }, 3982 }, 3983 3984 /* PREFIX_0FAE_REG_1 */ 3985 { 3986 { Bad_Opcode }, 3987 { "rdgsbase", { Ev }, 0 }, 3988 }, 3989 3990 /* PREFIX_0FAE_REG_2 */ 3991 { 3992 { Bad_Opcode }, 3993 { "wrfsbase", { Ev }, 0 }, 3994 }, 3995 3996 /* PREFIX_0FAE_REG_3 */ 3997 { 3998 { Bad_Opcode }, 3999 { "wrgsbase", { Ev }, 0 }, 4000 }, 4001 4002 /* PREFIX_0FAE_REG_6 */ 4003 { 4004 { "xsaveopt", { FXSAVE }, 0 }, 4005 { Bad_Opcode }, 4006 { "clwb", { Mb }, 0 }, 4007 }, 4008 4009 /* PREFIX_0FAE_REG_7 */ 4010 { 4011 { "clflush", { Mb }, 0 }, 4012 { Bad_Opcode }, 4013 { "clflushopt", { Mb }, 0 }, 4014 }, 4015 4016 /* PREFIX_RM_0_0FAE_REG_7 */ 4017 { 4018 { "sfence", { Skip_MODRM }, 0 }, 4019 { Bad_Opcode }, 4020 { "pcommit", { Skip_MODRM }, 0 }, 4021 }, 4022 4023 /* PREFIX_0FB8 */ 4024 { 4025 { Bad_Opcode }, 4026 { "popcntS", { Gv, Ev }, 0 }, 4027 }, 4028 4029 /* PREFIX_0FBC */ 4030 { 4031 { "bsfS", { Gv, Ev }, 0 }, 4032 { "tzcntS", { Gv, Ev }, 0 }, 4033 { "bsfS", { Gv, Ev }, 0 }, 4034 }, 4035 4036 /* PREFIX_0FBD */ 4037 { 4038 { "bsrS", { Gv, Ev }, 0 }, 4039 { "lzcntS", { Gv, Ev }, 0 }, 4040 { "bsrS", { Gv, Ev }, 0 }, 4041 }, 4042 4043 /* PREFIX_0FC2 */ 4044 { 4045 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, 4046 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, 4047 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, 4048 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, 4049 }, 4050 4051 /* PREFIX_0FC3 */ 4052 { 4053 { "movntiS", { Ma, Gv }, PREFIX_OPCODE }, 4054 }, 4055 4056 /* PREFIX_MOD_0_0FC7_REG_6 */ 4057 { 4058 { "vmptrld",{ Mq }, 0 }, 4059 { "vmxon", { Mq }, 0 }, 4060 { "vmclear",{ Mq }, 0 }, 4061 }, 4062 4063 /* PREFIX_MOD_3_0FC7_REG_6 */ 4064 { 4065 { "rdrand", { Ev }, 0 }, 4066 { Bad_Opcode }, 4067 { "rdrand", { Ev }, 0 } 4068 }, 4069 4070 /* PREFIX_MOD_3_0FC7_REG_7 */ 4071 { 4072 { "rdseed", { Ev }, 0 }, 4073 { Bad_Opcode }, 4074 { "rdseed", { Ev }, 0 }, 4075 }, 4076 4077 /* PREFIX_0FD0 */ 4078 { 4079 { Bad_Opcode }, 4080 { Bad_Opcode }, 4081 { "addsubpd", { XM, EXx }, 0 }, 4082 { "addsubps", { XM, EXx }, 0 }, 4083 }, 4084 4085 /* PREFIX_0FD6 */ 4086 { 4087 { Bad_Opcode }, 4088 { "movq2dq",{ XM, MS }, 0 }, 4089 { "movq", { EXqS, XM }, 0 }, 4090 { "movdq2q",{ MX, XS }, 0 }, 4091 }, 4092 4093 /* PREFIX_0FE6 */ 4094 { 4095 { Bad_Opcode }, 4096 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, 4097 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, 4098 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, 4099 }, 4100 4101 /* PREFIX_0FE7 */ 4102 { 4103 { "movntq", { Mq, MX }, PREFIX_OPCODE }, 4104 { Bad_Opcode }, 4105 { MOD_TABLE (MOD_0FE7_PREFIX_2) }, 4106 }, 4107 4108 /* PREFIX_0FF0 */ 4109 { 4110 { Bad_Opcode }, 4111 { Bad_Opcode }, 4112 { Bad_Opcode }, 4113 { MOD_TABLE (MOD_0FF0_PREFIX_3) }, 4114 }, 4115 4116 /* PREFIX_0FF7 */ 4117 { 4118 { "maskmovq", { MX, MS }, PREFIX_OPCODE }, 4119 { Bad_Opcode }, 4120 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, 4121 }, 4122 4123 /* PREFIX_0F3810 */ 4124 { 4125 { Bad_Opcode }, 4126 { Bad_Opcode }, 4127 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, 4128 }, 4129 4130 /* PREFIX_0F3814 */ 4131 { 4132 { Bad_Opcode }, 4133 { Bad_Opcode }, 4134 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, 4135 }, 4136 4137 /* PREFIX_0F3815 */ 4138 { 4139 { Bad_Opcode }, 4140 { Bad_Opcode }, 4141 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, 4142 }, 4143 4144 /* PREFIX_0F3817 */ 4145 { 4146 { Bad_Opcode }, 4147 { Bad_Opcode }, 4148 { "ptest", { XM, EXx }, PREFIX_OPCODE }, 4149 }, 4150 4151 /* PREFIX_0F3820 */ 4152 { 4153 { Bad_Opcode }, 4154 { Bad_Opcode }, 4155 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, 4156 }, 4157 4158 /* PREFIX_0F3821 */ 4159 { 4160 { Bad_Opcode }, 4161 { Bad_Opcode }, 4162 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, 4163 }, 4164 4165 /* PREFIX_0F3822 */ 4166 { 4167 { Bad_Opcode }, 4168 { Bad_Opcode }, 4169 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, 4170 }, 4171 4172 /* PREFIX_0F3823 */ 4173 { 4174 { Bad_Opcode }, 4175 { Bad_Opcode }, 4176 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, 4177 }, 4178 4179 /* PREFIX_0F3824 */ 4180 { 4181 { Bad_Opcode }, 4182 { Bad_Opcode }, 4183 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, 4184 }, 4185 4186 /* PREFIX_0F3825 */ 4187 { 4188 { Bad_Opcode }, 4189 { Bad_Opcode }, 4190 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, 4191 }, 4192 4193 /* PREFIX_0F3828 */ 4194 { 4195 { Bad_Opcode }, 4196 { Bad_Opcode }, 4197 { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, 4198 }, 4199 4200 /* PREFIX_0F3829 */ 4201 { 4202 { Bad_Opcode }, 4203 { Bad_Opcode }, 4204 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, 4205 }, 4206 4207 /* PREFIX_0F382A */ 4208 { 4209 { Bad_Opcode }, 4210 { Bad_Opcode }, 4211 { MOD_TABLE (MOD_0F382A_PREFIX_2) }, 4212 }, 4213 4214 /* PREFIX_0F382B */ 4215 { 4216 { Bad_Opcode }, 4217 { Bad_Opcode }, 4218 { "packusdw", { XM, EXx }, PREFIX_OPCODE }, 4219 }, 4220 4221 /* PREFIX_0F3830 */ 4222 { 4223 { Bad_Opcode }, 4224 { Bad_Opcode }, 4225 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, 4226 }, 4227 4228 /* PREFIX_0F3831 */ 4229 { 4230 { Bad_Opcode }, 4231 { Bad_Opcode }, 4232 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, 4233 }, 4234 4235 /* PREFIX_0F3832 */ 4236 { 4237 { Bad_Opcode }, 4238 { Bad_Opcode }, 4239 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, 4240 }, 4241 4242 /* PREFIX_0F3833 */ 4243 { 4244 { Bad_Opcode }, 4245 { Bad_Opcode }, 4246 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, 4247 }, 4248 4249 /* PREFIX_0F3834 */ 4250 { 4251 { Bad_Opcode }, 4252 { Bad_Opcode }, 4253 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, 4254 }, 4255 4256 /* PREFIX_0F3835 */ 4257 { 4258 { Bad_Opcode }, 4259 { Bad_Opcode }, 4260 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, 4261 }, 4262 4263 /* PREFIX_0F3837 */ 4264 { 4265 { Bad_Opcode }, 4266 { Bad_Opcode }, 4267 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, 4268 }, 4269 4270 /* PREFIX_0F3838 */ 4271 { 4272 { Bad_Opcode }, 4273 { Bad_Opcode }, 4274 { "pminsb", { XM, EXx }, PREFIX_OPCODE }, 4275 }, 4276 4277 /* PREFIX_0F3839 */ 4278 { 4279 { Bad_Opcode }, 4280 { Bad_Opcode }, 4281 { "pminsd", { XM, EXx }, PREFIX_OPCODE }, 4282 }, 4283 4284 /* PREFIX_0F383A */ 4285 { 4286 { Bad_Opcode }, 4287 { Bad_Opcode }, 4288 { "pminuw", { XM, EXx }, PREFIX_OPCODE }, 4289 }, 4290 4291 /* PREFIX_0F383B */ 4292 { 4293 { Bad_Opcode }, 4294 { Bad_Opcode }, 4295 { "pminud", { XM, EXx }, PREFIX_OPCODE }, 4296 }, 4297 4298 /* PREFIX_0F383C */ 4299 { 4300 { Bad_Opcode }, 4301 { Bad_Opcode }, 4302 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, 4303 }, 4304 4305 /* PREFIX_0F383D */ 4306 { 4307 { Bad_Opcode }, 4308 { Bad_Opcode }, 4309 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, 4310 }, 4311 4312 /* PREFIX_0F383E */ 4313 { 4314 { Bad_Opcode }, 4315 { Bad_Opcode }, 4316 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, 4317 }, 4318 4319 /* PREFIX_0F383F */ 4320 { 4321 { Bad_Opcode }, 4322 { Bad_Opcode }, 4323 { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, 4324 }, 4325 4326 /* PREFIX_0F3840 */ 4327 { 4328 { Bad_Opcode }, 4329 { Bad_Opcode }, 4330 { "pmulld", { XM, EXx }, PREFIX_OPCODE }, 4331 }, 4332 4333 /* PREFIX_0F3841 */ 4334 { 4335 { Bad_Opcode }, 4336 { Bad_Opcode }, 4337 { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, 4338 }, 4339 4340 /* PREFIX_0F3880 */ 4341 { 4342 { Bad_Opcode }, 4343 { Bad_Opcode }, 4344 { "invept", { Gm, Mo }, PREFIX_OPCODE }, 4345 }, 4346 4347 /* PREFIX_0F3881 */ 4348 { 4349 { Bad_Opcode }, 4350 { Bad_Opcode }, 4351 { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, 4352 }, 4353 4354 /* PREFIX_0F3882 */ 4355 { 4356 { Bad_Opcode }, 4357 { Bad_Opcode }, 4358 { "invpcid", { Gm, M }, PREFIX_OPCODE }, 4359 }, 4360 4361 /* PREFIX_0F38C8 */ 4362 { 4363 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, 4364 }, 4365 4366 /* PREFIX_0F38C9 */ 4367 { 4368 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, 4369 }, 4370 4371 /* PREFIX_0F38CA */ 4372 { 4373 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, 4374 }, 4375 4376 /* PREFIX_0F38CB */ 4377 { 4378 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, 4379 }, 4380 4381 /* PREFIX_0F38CC */ 4382 { 4383 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, 4384 }, 4385 4386 /* PREFIX_0F38CD */ 4387 { 4388 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, 4389 }, 4390 4391 /* PREFIX_0F38DB */ 4392 { 4393 { Bad_Opcode }, 4394 { Bad_Opcode }, 4395 { "aesimc", { XM, EXx }, PREFIX_OPCODE }, 4396 }, 4397 4398 /* PREFIX_0F38DC */ 4399 { 4400 { Bad_Opcode }, 4401 { Bad_Opcode }, 4402 { "aesenc", { XM, EXx }, PREFIX_OPCODE }, 4403 }, 4404 4405 /* PREFIX_0F38DD */ 4406 { 4407 { Bad_Opcode }, 4408 { Bad_Opcode }, 4409 { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, 4410 }, 4411 4412 /* PREFIX_0F38DE */ 4413 { 4414 { Bad_Opcode }, 4415 { Bad_Opcode }, 4416 { "aesdec", { XM, EXx }, PREFIX_OPCODE }, 4417 }, 4418 4419 /* PREFIX_0F38DF */ 4420 { 4421 { Bad_Opcode }, 4422 { Bad_Opcode }, 4423 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, 4424 }, 4425 4426 /* PREFIX_0F38F0 */ 4427 { 4428 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, 4429 { Bad_Opcode }, 4430 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, 4431 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, 4432 }, 4433 4434 /* PREFIX_0F38F1 */ 4435 { 4436 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, 4437 { Bad_Opcode }, 4438 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, 4439 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, 4440 }, 4441 4442 /* PREFIX_0F38F6 */ 4443 { 4444 { Bad_Opcode }, 4445 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, 4446 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, 4447 { Bad_Opcode }, 4448 }, 4449 4450 /* PREFIX_0F3A08 */ 4451 { 4452 { Bad_Opcode }, 4453 { Bad_Opcode }, 4454 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, 4455 }, 4456 4457 /* PREFIX_0F3A09 */ 4458 { 4459 { Bad_Opcode }, 4460 { Bad_Opcode }, 4461 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, 4462 }, 4463 4464 /* PREFIX_0F3A0A */ 4465 { 4466 { Bad_Opcode }, 4467 { Bad_Opcode }, 4468 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, 4469 }, 4470 4471 /* PREFIX_0F3A0B */ 4472 { 4473 { Bad_Opcode }, 4474 { Bad_Opcode }, 4475 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, 4476 }, 4477 4478 /* PREFIX_0F3A0C */ 4479 { 4480 { Bad_Opcode }, 4481 { Bad_Opcode }, 4482 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, 4483 }, 4484 4485 /* PREFIX_0F3A0D */ 4486 { 4487 { Bad_Opcode }, 4488 { Bad_Opcode }, 4489 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, 4490 }, 4491 4492 /* PREFIX_0F3A0E */ 4493 { 4494 { Bad_Opcode }, 4495 { Bad_Opcode }, 4496 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, 4497 }, 4498 4499 /* PREFIX_0F3A14 */ 4500 { 4501 { Bad_Opcode }, 4502 { Bad_Opcode }, 4503 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, 4504 }, 4505 4506 /* PREFIX_0F3A15 */ 4507 { 4508 { Bad_Opcode }, 4509 { Bad_Opcode }, 4510 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, 4511 }, 4512 4513 /* PREFIX_0F3A16 */ 4514 { 4515 { Bad_Opcode }, 4516 { Bad_Opcode }, 4517 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, 4518 }, 4519 4520 /* PREFIX_0F3A17 */ 4521 { 4522 { Bad_Opcode }, 4523 { Bad_Opcode }, 4524 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, 4525 }, 4526 4527 /* PREFIX_0F3A20 */ 4528 { 4529 { Bad_Opcode }, 4530 { Bad_Opcode }, 4531 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, 4532 }, 4533 4534 /* PREFIX_0F3A21 */ 4535 { 4536 { Bad_Opcode }, 4537 { Bad_Opcode }, 4538 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, 4539 }, 4540 4541 /* PREFIX_0F3A22 */ 4542 { 4543 { Bad_Opcode }, 4544 { Bad_Opcode }, 4545 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, 4546 }, 4547 4548 /* PREFIX_0F3A40 */ 4549 { 4550 { Bad_Opcode }, 4551 { Bad_Opcode }, 4552 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, 4553 }, 4554 4555 /* PREFIX_0F3A41 */ 4556 { 4557 { Bad_Opcode }, 4558 { Bad_Opcode }, 4559 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, 4560 }, 4561 4562 /* PREFIX_0F3A42 */ 4563 { 4564 { Bad_Opcode }, 4565 { Bad_Opcode }, 4566 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, 4567 }, 4568 4569 /* PREFIX_0F3A44 */ 4570 { 4571 { Bad_Opcode }, 4572 { Bad_Opcode }, 4573 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, 4574 }, 4575 4576 /* PREFIX_0F3A60 */ 4577 { 4578 { Bad_Opcode }, 4579 { Bad_Opcode }, 4580 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, 4581 }, 4582 4583 /* PREFIX_0F3A61 */ 4584 { 4585 { Bad_Opcode }, 4586 { Bad_Opcode }, 4587 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, 4588 }, 4589 4590 /* PREFIX_0F3A62 */ 4591 { 4592 { Bad_Opcode }, 4593 { Bad_Opcode }, 4594 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, 4595 }, 4596 4597 /* PREFIX_0F3A63 */ 4598 { 4599 { Bad_Opcode }, 4600 { Bad_Opcode }, 4601 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, 4602 }, 4603 4604 /* PREFIX_0F3ACC */ 4605 { 4606 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, 4607 }, 4608 4609 /* PREFIX_0F3ADF */ 4610 { 4611 { Bad_Opcode }, 4612 { Bad_Opcode }, 4613 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, 4614 }, 4615 4616 /* PREFIX_VEX_0F10 */ 4617 { 4618 { VEX_W_TABLE (VEX_W_0F10_P_0) }, 4619 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, 4620 { VEX_W_TABLE (VEX_W_0F10_P_2) }, 4621 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, 4622 }, 4623 4624 /* PREFIX_VEX_0F11 */ 4625 { 4626 { VEX_W_TABLE (VEX_W_0F11_P_0) }, 4627 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, 4628 { VEX_W_TABLE (VEX_W_0F11_P_2) }, 4629 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, 4630 }, 4631 4632 /* PREFIX_VEX_0F12 */ 4633 { 4634 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, 4635 { VEX_W_TABLE (VEX_W_0F12_P_1) }, 4636 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, 4637 { VEX_W_TABLE (VEX_W_0F12_P_3) }, 4638 }, 4639 4640 /* PREFIX_VEX_0F16 */ 4641 { 4642 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, 4643 { VEX_W_TABLE (VEX_W_0F16_P_1) }, 4644 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, 4645 }, 4646 4647 /* PREFIX_VEX_0F2A */ 4648 { 4649 { Bad_Opcode }, 4650 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, 4651 { Bad_Opcode }, 4652 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, 4653 }, 4654 4655 /* PREFIX_VEX_0F2C */ 4656 { 4657 { Bad_Opcode }, 4658 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, 4659 { Bad_Opcode }, 4660 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, 4661 }, 4662 4663 /* PREFIX_VEX_0F2D */ 4664 { 4665 { Bad_Opcode }, 4666 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, 4667 { Bad_Opcode }, 4668 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, 4669 }, 4670 4671 /* PREFIX_VEX_0F2E */ 4672 { 4673 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, 4674 { Bad_Opcode }, 4675 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, 4676 }, 4677 4678 /* PREFIX_VEX_0F2F */ 4679 { 4680 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, 4681 { Bad_Opcode }, 4682 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, 4683 }, 4684 4685 /* PREFIX_VEX_0F41 */ 4686 { 4687 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, 4688 { Bad_Opcode }, 4689 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, 4690 }, 4691 4692 /* PREFIX_VEX_0F42 */ 4693 { 4694 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, 4695 { Bad_Opcode }, 4696 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, 4697 }, 4698 4699 /* PREFIX_VEX_0F44 */ 4700 { 4701 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, 4702 { Bad_Opcode }, 4703 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, 4704 }, 4705 4706 /* PREFIX_VEX_0F45 */ 4707 { 4708 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, 4709 { Bad_Opcode }, 4710 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, 4711 }, 4712 4713 /* PREFIX_VEX_0F46 */ 4714 { 4715 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, 4716 { Bad_Opcode }, 4717 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, 4718 }, 4719 4720 /* PREFIX_VEX_0F47 */ 4721 { 4722 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, 4723 { Bad_Opcode }, 4724 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, 4725 }, 4726 4727 /* PREFIX_VEX_0F4A */ 4728 { 4729 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, 4730 { Bad_Opcode }, 4731 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, 4732 }, 4733 4734 /* PREFIX_VEX_0F4B */ 4735 { 4736 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, 4737 { Bad_Opcode }, 4738 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, 4739 }, 4740 4741 /* PREFIX_VEX_0F51 */ 4742 { 4743 { VEX_W_TABLE (VEX_W_0F51_P_0) }, 4744 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, 4745 { VEX_W_TABLE (VEX_W_0F51_P_2) }, 4746 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, 4747 }, 4748 4749 /* PREFIX_VEX_0F52 */ 4750 { 4751 { VEX_W_TABLE (VEX_W_0F52_P_0) }, 4752 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, 4753 }, 4754 4755 /* PREFIX_VEX_0F53 */ 4756 { 4757 { VEX_W_TABLE (VEX_W_0F53_P_0) }, 4758 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, 4759 }, 4760 4761 /* PREFIX_VEX_0F58 */ 4762 { 4763 { VEX_W_TABLE (VEX_W_0F58_P_0) }, 4764 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, 4765 { VEX_W_TABLE (VEX_W_0F58_P_2) }, 4766 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, 4767 }, 4768 4769 /* PREFIX_VEX_0F59 */ 4770 { 4771 { VEX_W_TABLE (VEX_W_0F59_P_0) }, 4772 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, 4773 { VEX_W_TABLE (VEX_W_0F59_P_2) }, 4774 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, 4775 }, 4776 4777 /* PREFIX_VEX_0F5A */ 4778 { 4779 { VEX_W_TABLE (VEX_W_0F5A_P_0) }, 4780 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, 4781 { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, 4782 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, 4783 }, 4784 4785 /* PREFIX_VEX_0F5B */ 4786 { 4787 { VEX_W_TABLE (VEX_W_0F5B_P_0) }, 4788 { VEX_W_TABLE (VEX_W_0F5B_P_1) }, 4789 { VEX_W_TABLE (VEX_W_0F5B_P_2) }, 4790 }, 4791 4792 /* PREFIX_VEX_0F5C */ 4793 { 4794 { VEX_W_TABLE (VEX_W_0F5C_P_0) }, 4795 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, 4796 { VEX_W_TABLE (VEX_W_0F5C_P_2) }, 4797 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, 4798 }, 4799 4800 /* PREFIX_VEX_0F5D */ 4801 { 4802 { VEX_W_TABLE (VEX_W_0F5D_P_0) }, 4803 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, 4804 { VEX_W_TABLE (VEX_W_0F5D_P_2) }, 4805 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, 4806 }, 4807 4808 /* PREFIX_VEX_0F5E */ 4809 { 4810 { VEX_W_TABLE (VEX_W_0F5E_P_0) }, 4811 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, 4812 { VEX_W_TABLE (VEX_W_0F5E_P_2) }, 4813 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, 4814 }, 4815 4816 /* PREFIX_VEX_0F5F */ 4817 { 4818 { VEX_W_TABLE (VEX_W_0F5F_P_0) }, 4819 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, 4820 { VEX_W_TABLE (VEX_W_0F5F_P_2) }, 4821 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, 4822 }, 4823 4824 /* PREFIX_VEX_0F60 */ 4825 { 4826 { Bad_Opcode }, 4827 { Bad_Opcode }, 4828 { VEX_W_TABLE (VEX_W_0F60_P_2) }, 4829 }, 4830 4831 /* PREFIX_VEX_0F61 */ 4832 { 4833 { Bad_Opcode }, 4834 { Bad_Opcode }, 4835 { VEX_W_TABLE (VEX_W_0F61_P_2) }, 4836 }, 4837 4838 /* PREFIX_VEX_0F62 */ 4839 { 4840 { Bad_Opcode }, 4841 { Bad_Opcode }, 4842 { VEX_W_TABLE (VEX_W_0F62_P_2) }, 4843 }, 4844 4845 /* PREFIX_VEX_0F63 */ 4846 { 4847 { Bad_Opcode }, 4848 { Bad_Opcode }, 4849 { VEX_W_TABLE (VEX_W_0F63_P_2) }, 4850 }, 4851 4852 /* PREFIX_VEX_0F64 */ 4853 { 4854 { Bad_Opcode }, 4855 { Bad_Opcode }, 4856 { VEX_W_TABLE (VEX_W_0F64_P_2) }, 4857 }, 4858 4859 /* PREFIX_VEX_0F65 */ 4860 { 4861 { Bad_Opcode }, 4862 { Bad_Opcode }, 4863 { VEX_W_TABLE (VEX_W_0F65_P_2) }, 4864 }, 4865 4866 /* PREFIX_VEX_0F66 */ 4867 { 4868 { Bad_Opcode }, 4869 { Bad_Opcode }, 4870 { VEX_W_TABLE (VEX_W_0F66_P_2) }, 4871 }, 4872 4873 /* PREFIX_VEX_0F67 */ 4874 { 4875 { Bad_Opcode }, 4876 { Bad_Opcode }, 4877 { VEX_W_TABLE (VEX_W_0F67_P_2) }, 4878 }, 4879 4880 /* PREFIX_VEX_0F68 */ 4881 { 4882 { Bad_Opcode }, 4883 { Bad_Opcode }, 4884 { VEX_W_TABLE (VEX_W_0F68_P_2) }, 4885 }, 4886 4887 /* PREFIX_VEX_0F69 */ 4888 { 4889 { Bad_Opcode }, 4890 { Bad_Opcode }, 4891 { VEX_W_TABLE (VEX_W_0F69_P_2) }, 4892 }, 4893 4894 /* PREFIX_VEX_0F6A */ 4895 { 4896 { Bad_Opcode }, 4897 { Bad_Opcode }, 4898 { VEX_W_TABLE (VEX_W_0F6A_P_2) }, 4899 }, 4900 4901 /* PREFIX_VEX_0F6B */ 4902 { 4903 { Bad_Opcode }, 4904 { Bad_Opcode }, 4905 { VEX_W_TABLE (VEX_W_0F6B_P_2) }, 4906 }, 4907 4908 /* PREFIX_VEX_0F6C */ 4909 { 4910 { Bad_Opcode }, 4911 { Bad_Opcode }, 4912 { VEX_W_TABLE (VEX_W_0F6C_P_2) }, 4913 }, 4914 4915 /* PREFIX_VEX_0F6D */ 4916 { 4917 { Bad_Opcode }, 4918 { Bad_Opcode }, 4919 { VEX_W_TABLE (VEX_W_0F6D_P_2) }, 4920 }, 4921 4922 /* PREFIX_VEX_0F6E */ 4923 { 4924 { Bad_Opcode }, 4925 { Bad_Opcode }, 4926 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, 4927 }, 4928 4929 /* PREFIX_VEX_0F6F */ 4930 { 4931 { Bad_Opcode }, 4932 { VEX_W_TABLE (VEX_W_0F6F_P_1) }, 4933 { VEX_W_TABLE (VEX_W_0F6F_P_2) }, 4934 }, 4935 4936 /* PREFIX_VEX_0F70 */ 4937 { 4938 { Bad_Opcode }, 4939 { VEX_W_TABLE (VEX_W_0F70_P_1) }, 4940 { VEX_W_TABLE (VEX_W_0F70_P_2) }, 4941 { VEX_W_TABLE (VEX_W_0F70_P_3) }, 4942 }, 4943 4944 /* PREFIX_VEX_0F71_REG_2 */ 4945 { 4946 { Bad_Opcode }, 4947 { Bad_Opcode }, 4948 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, 4949 }, 4950 4951 /* PREFIX_VEX_0F71_REG_4 */ 4952 { 4953 { Bad_Opcode }, 4954 { Bad_Opcode }, 4955 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, 4956 }, 4957 4958 /* PREFIX_VEX_0F71_REG_6 */ 4959 { 4960 { Bad_Opcode }, 4961 { Bad_Opcode }, 4962 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, 4963 }, 4964 4965 /* PREFIX_VEX_0F72_REG_2 */ 4966 { 4967 { Bad_Opcode }, 4968 { Bad_Opcode }, 4969 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, 4970 }, 4971 4972 /* PREFIX_VEX_0F72_REG_4 */ 4973 { 4974 { Bad_Opcode }, 4975 { Bad_Opcode }, 4976 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, 4977 }, 4978 4979 /* PREFIX_VEX_0F72_REG_6 */ 4980 { 4981 { Bad_Opcode }, 4982 { Bad_Opcode }, 4983 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, 4984 }, 4985 4986 /* PREFIX_VEX_0F73_REG_2 */ 4987 { 4988 { Bad_Opcode }, 4989 { Bad_Opcode }, 4990 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, 4991 }, 4992 4993 /* PREFIX_VEX_0F73_REG_3 */ 4994 { 4995 { Bad_Opcode }, 4996 { Bad_Opcode }, 4997 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, 4998 }, 4999 5000 /* PREFIX_VEX_0F73_REG_6 */ 5001 { 5002 { Bad_Opcode }, 5003 { Bad_Opcode }, 5004 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, 5005 }, 5006 5007 /* PREFIX_VEX_0F73_REG_7 */ 5008 { 5009 { Bad_Opcode }, 5010 { Bad_Opcode }, 5011 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, 5012 }, 5013 5014 /* PREFIX_VEX_0F74 */ 5015 { 5016 { Bad_Opcode }, 5017 { Bad_Opcode }, 5018 { VEX_W_TABLE (VEX_W_0F74_P_2) }, 5019 }, 5020 5021 /* PREFIX_VEX_0F75 */ 5022 { 5023 { Bad_Opcode }, 5024 { Bad_Opcode }, 5025 { VEX_W_TABLE (VEX_W_0F75_P_2) }, 5026 }, 5027 5028 /* PREFIX_VEX_0F76 */ 5029 { 5030 { Bad_Opcode }, 5031 { Bad_Opcode }, 5032 { VEX_W_TABLE (VEX_W_0F76_P_2) }, 5033 }, 5034 5035 /* PREFIX_VEX_0F77 */ 5036 { 5037 { VEX_W_TABLE (VEX_W_0F77_P_0) }, 5038 }, 5039 5040 /* PREFIX_VEX_0F7C */ 5041 { 5042 { Bad_Opcode }, 5043 { Bad_Opcode }, 5044 { VEX_W_TABLE (VEX_W_0F7C_P_2) }, 5045 { VEX_W_TABLE (VEX_W_0F7C_P_3) }, 5046 }, 5047 5048 /* PREFIX_VEX_0F7D */ 5049 { 5050 { Bad_Opcode }, 5051 { Bad_Opcode }, 5052 { VEX_W_TABLE (VEX_W_0F7D_P_2) }, 5053 { VEX_W_TABLE (VEX_W_0F7D_P_3) }, 5054 }, 5055 5056 /* PREFIX_VEX_0F7E */ 5057 { 5058 { Bad_Opcode }, 5059 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, 5060 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, 5061 }, 5062 5063 /* PREFIX_VEX_0F7F */ 5064 { 5065 { Bad_Opcode }, 5066 { VEX_W_TABLE (VEX_W_0F7F_P_1) }, 5067 { VEX_W_TABLE (VEX_W_0F7F_P_2) }, 5068 }, 5069 5070 /* PREFIX_VEX_0F90 */ 5071 { 5072 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, 5073 { Bad_Opcode }, 5074 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, 5075 }, 5076 5077 /* PREFIX_VEX_0F91 */ 5078 { 5079 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, 5080 { Bad_Opcode }, 5081 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, 5082 }, 5083 5084 /* PREFIX_VEX_0F92 */ 5085 { 5086 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, 5087 { Bad_Opcode }, 5088 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, 5089 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, 5090 }, 5091 5092 /* PREFIX_VEX_0F93 */ 5093 { 5094 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, 5095 { Bad_Opcode }, 5096 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, 5097 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, 5098 }, 5099 5100 /* PREFIX_VEX_0F98 */ 5101 { 5102 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, 5103 { Bad_Opcode }, 5104 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, 5105 }, 5106 5107 /* PREFIX_VEX_0F99 */ 5108 { 5109 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, 5110 { Bad_Opcode }, 5111 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, 5112 }, 5113 5114 /* PREFIX_VEX_0FC2 */ 5115 { 5116 { VEX_W_TABLE (VEX_W_0FC2_P_0) }, 5117 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, 5118 { VEX_W_TABLE (VEX_W_0FC2_P_2) }, 5119 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, 5120 }, 5121 5122 /* PREFIX_VEX_0FC4 */ 5123 { 5124 { Bad_Opcode }, 5125 { Bad_Opcode }, 5126 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, 5127 }, 5128 5129 /* PREFIX_VEX_0FC5 */ 5130 { 5131 { Bad_Opcode }, 5132 { Bad_Opcode }, 5133 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, 5134 }, 5135 5136 /* PREFIX_VEX_0FD0 */ 5137 { 5138 { Bad_Opcode }, 5139 { Bad_Opcode }, 5140 { VEX_W_TABLE (VEX_W_0FD0_P_2) }, 5141 { VEX_W_TABLE (VEX_W_0FD0_P_3) }, 5142 }, 5143 5144 /* PREFIX_VEX_0FD1 */ 5145 { 5146 { Bad_Opcode }, 5147 { Bad_Opcode }, 5148 { VEX_W_TABLE (VEX_W_0FD1_P_2) }, 5149 }, 5150 5151 /* PREFIX_VEX_0FD2 */ 5152 { 5153 { Bad_Opcode }, 5154 { Bad_Opcode }, 5155 { VEX_W_TABLE (VEX_W_0FD2_P_2) }, 5156 }, 5157 5158 /* PREFIX_VEX_0FD3 */ 5159 { 5160 { Bad_Opcode }, 5161 { Bad_Opcode }, 5162 { VEX_W_TABLE (VEX_W_0FD3_P_2) }, 5163 }, 5164 5165 /* PREFIX_VEX_0FD4 */ 5166 { 5167 { Bad_Opcode }, 5168 { Bad_Opcode }, 5169 { VEX_W_TABLE (VEX_W_0FD4_P_2) }, 5170 }, 5171 5172 /* PREFIX_VEX_0FD5 */ 5173 { 5174 { Bad_Opcode }, 5175 { Bad_Opcode }, 5176 { VEX_W_TABLE (VEX_W_0FD5_P_2) }, 5177 }, 5178 5179 /* PREFIX_VEX_0FD6 */ 5180 { 5181 { Bad_Opcode }, 5182 { Bad_Opcode }, 5183 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, 5184 }, 5185 5186 /* PREFIX_VEX_0FD7 */ 5187 { 5188 { Bad_Opcode }, 5189 { Bad_Opcode }, 5190 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, 5191 }, 5192 5193 /* PREFIX_VEX_0FD8 */ 5194 { 5195 { Bad_Opcode }, 5196 { Bad_Opcode }, 5197 { VEX_W_TABLE (VEX_W_0FD8_P_2) }, 5198 }, 5199 5200 /* PREFIX_VEX_0FD9 */ 5201 { 5202 { Bad_Opcode }, 5203 { Bad_Opcode }, 5204 { VEX_W_TABLE (VEX_W_0FD9_P_2) }, 5205 }, 5206 5207 /* PREFIX_VEX_0FDA */ 5208 { 5209 { Bad_Opcode }, 5210 { Bad_Opcode }, 5211 { VEX_W_TABLE (VEX_W_0FDA_P_2) }, 5212 }, 5213 5214 /* PREFIX_VEX_0FDB */ 5215 { 5216 { Bad_Opcode }, 5217 { Bad_Opcode }, 5218 { VEX_W_TABLE (VEX_W_0FDB_P_2) }, 5219 }, 5220 5221 /* PREFIX_VEX_0FDC */ 5222 { 5223 { Bad_Opcode }, 5224 { Bad_Opcode }, 5225 { VEX_W_TABLE (VEX_W_0FDC_P_2) }, 5226 }, 5227 5228 /* PREFIX_VEX_0FDD */ 5229 { 5230 { Bad_Opcode }, 5231 { Bad_Opcode }, 5232 { VEX_W_TABLE (VEX_W_0FDD_P_2) }, 5233 }, 5234 5235 /* PREFIX_VEX_0FDE */ 5236 { 5237 { Bad_Opcode }, 5238 { Bad_Opcode }, 5239 { VEX_W_TABLE (VEX_W_0FDE_P_2) }, 5240 }, 5241 5242 /* PREFIX_VEX_0FDF */ 5243 { 5244 { Bad_Opcode }, 5245 { Bad_Opcode }, 5246 { VEX_W_TABLE (VEX_W_0FDF_P_2) }, 5247 }, 5248 5249 /* PREFIX_VEX_0FE0 */ 5250 { 5251 { Bad_Opcode }, 5252 { Bad_Opcode }, 5253 { VEX_W_TABLE (VEX_W_0FE0_P_2) }, 5254 }, 5255 5256 /* PREFIX_VEX_0FE1 */ 5257 { 5258 { Bad_Opcode }, 5259 { Bad_Opcode }, 5260 { VEX_W_TABLE (VEX_W_0FE1_P_2) }, 5261 }, 5262 5263 /* PREFIX_VEX_0FE2 */ 5264 { 5265 { Bad_Opcode }, 5266 { Bad_Opcode }, 5267 { VEX_W_TABLE (VEX_W_0FE2_P_2) }, 5268 }, 5269 5270 /* PREFIX_VEX_0FE3 */ 5271 { 5272 { Bad_Opcode }, 5273 { Bad_Opcode }, 5274 { VEX_W_TABLE (VEX_W_0FE3_P_2) }, 5275 }, 5276 5277 /* PREFIX_VEX_0FE4 */ 5278 { 5279 { Bad_Opcode }, 5280 { Bad_Opcode }, 5281 { VEX_W_TABLE (VEX_W_0FE4_P_2) }, 5282 }, 5283 5284 /* PREFIX_VEX_0FE5 */ 5285 { 5286 { Bad_Opcode }, 5287 { Bad_Opcode }, 5288 { VEX_W_TABLE (VEX_W_0FE5_P_2) }, 5289 }, 5290 5291 /* PREFIX_VEX_0FE6 */ 5292 { 5293 { Bad_Opcode }, 5294 { VEX_W_TABLE (VEX_W_0FE6_P_1) }, 5295 { VEX_W_TABLE (VEX_W_0FE6_P_2) }, 5296 { VEX_W_TABLE (VEX_W_0FE6_P_3) }, 5297 }, 5298 5299 /* PREFIX_VEX_0FE7 */ 5300 { 5301 { Bad_Opcode }, 5302 { Bad_Opcode }, 5303 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, 5304 }, 5305 5306 /* PREFIX_VEX_0FE8 */ 5307 { 5308 { Bad_Opcode }, 5309 { Bad_Opcode }, 5310 { VEX_W_TABLE (VEX_W_0FE8_P_2) }, 5311 }, 5312 5313 /* PREFIX_VEX_0FE9 */ 5314 { 5315 { Bad_Opcode }, 5316 { Bad_Opcode }, 5317 { VEX_W_TABLE (VEX_W_0FE9_P_2) }, 5318 }, 5319 5320 /* PREFIX_VEX_0FEA */ 5321 { 5322 { Bad_Opcode }, 5323 { Bad_Opcode }, 5324 { VEX_W_TABLE (VEX_W_0FEA_P_2) }, 5325 }, 5326 5327 /* PREFIX_VEX_0FEB */ 5328 { 5329 { Bad_Opcode }, 5330 { Bad_Opcode }, 5331 { VEX_W_TABLE (VEX_W_0FEB_P_2) }, 5332 }, 5333 5334 /* PREFIX_VEX_0FEC */ 5335 { 5336 { Bad_Opcode }, 5337 { Bad_Opcode }, 5338 { VEX_W_TABLE (VEX_W_0FEC_P_2) }, 5339 }, 5340 5341 /* PREFIX_VEX_0FED */ 5342 { 5343 { Bad_Opcode }, 5344 { Bad_Opcode }, 5345 { VEX_W_TABLE (VEX_W_0FED_P_2) }, 5346 }, 5347 5348 /* PREFIX_VEX_0FEE */ 5349 { 5350 { Bad_Opcode }, 5351 { Bad_Opcode }, 5352 { VEX_W_TABLE (VEX_W_0FEE_P_2) }, 5353 }, 5354 5355 /* PREFIX_VEX_0FEF */ 5356 { 5357 { Bad_Opcode }, 5358 { Bad_Opcode }, 5359 { VEX_W_TABLE (VEX_W_0FEF_P_2) }, 5360 }, 5361 5362 /* PREFIX_VEX_0FF0 */ 5363 { 5364 { Bad_Opcode }, 5365 { Bad_Opcode }, 5366 { Bad_Opcode }, 5367 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, 5368 }, 5369 5370 /* PREFIX_VEX_0FF1 */ 5371 { 5372 { Bad_Opcode }, 5373 { Bad_Opcode }, 5374 { VEX_W_TABLE (VEX_W_0FF1_P_2) }, 5375 }, 5376 5377 /* PREFIX_VEX_0FF2 */ 5378 { 5379 { Bad_Opcode }, 5380 { Bad_Opcode }, 5381 { VEX_W_TABLE (VEX_W_0FF2_P_2) }, 5382 }, 5383 5384 /* PREFIX_VEX_0FF3 */ 5385 { 5386 { Bad_Opcode }, 5387 { Bad_Opcode }, 5388 { VEX_W_TABLE (VEX_W_0FF3_P_2) }, 5389 }, 5390 5391 /* PREFIX_VEX_0FF4 */ 5392 { 5393 { Bad_Opcode }, 5394 { Bad_Opcode }, 5395 { VEX_W_TABLE (VEX_W_0FF4_P_2) }, 5396 }, 5397 5398 /* PREFIX_VEX_0FF5 */ 5399 { 5400 { Bad_Opcode }, 5401 { Bad_Opcode }, 5402 { VEX_W_TABLE (VEX_W_0FF5_P_2) }, 5403 }, 5404 5405 /* PREFIX_VEX_0FF6 */ 5406 { 5407 { Bad_Opcode }, 5408 { Bad_Opcode }, 5409 { VEX_W_TABLE (VEX_W_0FF6_P_2) }, 5410 }, 5411 5412 /* PREFIX_VEX_0FF7 */ 5413 { 5414 { Bad_Opcode }, 5415 { Bad_Opcode }, 5416 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, 5417 }, 5418 5419 /* PREFIX_VEX_0FF8 */ 5420 { 5421 { Bad_Opcode }, 5422 { Bad_Opcode }, 5423 { VEX_W_TABLE (VEX_W_0FF8_P_2) }, 5424 }, 5425 5426 /* PREFIX_VEX_0FF9 */ 5427 { 5428 { Bad_Opcode }, 5429 { Bad_Opcode }, 5430 { VEX_W_TABLE (VEX_W_0FF9_P_2) }, 5431 }, 5432 5433 /* PREFIX_VEX_0FFA */ 5434 { 5435 { Bad_Opcode }, 5436 { Bad_Opcode }, 5437 { VEX_W_TABLE (VEX_W_0FFA_P_2) }, 5438 }, 5439 5440 /* PREFIX_VEX_0FFB */ 5441 { 5442 { Bad_Opcode }, 5443 { Bad_Opcode }, 5444 { VEX_W_TABLE (VEX_W_0FFB_P_2) }, 5445 }, 5446 5447 /* PREFIX_VEX_0FFC */ 5448 { 5449 { Bad_Opcode }, 5450 { Bad_Opcode }, 5451 { VEX_W_TABLE (VEX_W_0FFC_P_2) }, 5452 }, 5453 5454 /* PREFIX_VEX_0FFD */ 5455 { 5456 { Bad_Opcode }, 5457 { Bad_Opcode }, 5458 { VEX_W_TABLE (VEX_W_0FFD_P_2) }, 5459 }, 5460 5461 /* PREFIX_VEX_0FFE */ 5462 { 5463 { Bad_Opcode }, 5464 { Bad_Opcode }, 5465 { VEX_W_TABLE (VEX_W_0FFE_P_2) }, 5466 }, 5467 5468 /* PREFIX_VEX_0F3800 */ 5469 { 5470 { Bad_Opcode }, 5471 { Bad_Opcode }, 5472 { VEX_W_TABLE (VEX_W_0F3800_P_2) }, 5473 }, 5474 5475 /* PREFIX_VEX_0F3801 */ 5476 { 5477 { Bad_Opcode }, 5478 { Bad_Opcode }, 5479 { VEX_W_TABLE (VEX_W_0F3801_P_2) }, 5480 }, 5481 5482 /* PREFIX_VEX_0F3802 */ 5483 { 5484 { Bad_Opcode }, 5485 { Bad_Opcode }, 5486 { VEX_W_TABLE (VEX_W_0F3802_P_2) }, 5487 }, 5488 5489 /* PREFIX_VEX_0F3803 */ 5490 { 5491 { Bad_Opcode }, 5492 { Bad_Opcode }, 5493 { VEX_W_TABLE (VEX_W_0F3803_P_2) }, 5494 }, 5495 5496 /* PREFIX_VEX_0F3804 */ 5497 { 5498 { Bad_Opcode }, 5499 { Bad_Opcode }, 5500 { VEX_W_TABLE (VEX_W_0F3804_P_2) }, 5501 }, 5502 5503 /* PREFIX_VEX_0F3805 */ 5504 { 5505 { Bad_Opcode }, 5506 { Bad_Opcode }, 5507 { VEX_W_TABLE (VEX_W_0F3805_P_2) }, 5508 }, 5509 5510 /* PREFIX_VEX_0F3806 */ 5511 { 5512 { Bad_Opcode }, 5513 { Bad_Opcode }, 5514 { VEX_W_TABLE (VEX_W_0F3806_P_2) }, 5515 }, 5516 5517 /* PREFIX_VEX_0F3807 */ 5518 { 5519 { Bad_Opcode }, 5520 { Bad_Opcode }, 5521 { VEX_W_TABLE (VEX_W_0F3807_P_2) }, 5522 }, 5523 5524 /* PREFIX_VEX_0F3808 */ 5525 { 5526 { Bad_Opcode }, 5527 { Bad_Opcode }, 5528 { VEX_W_TABLE (VEX_W_0F3808_P_2) }, 5529 }, 5530 5531 /* PREFIX_VEX_0F3809 */ 5532 { 5533 { Bad_Opcode }, 5534 { Bad_Opcode }, 5535 { VEX_W_TABLE (VEX_W_0F3809_P_2) }, 5536 }, 5537 5538 /* PREFIX_VEX_0F380A */ 5539 { 5540 { Bad_Opcode }, 5541 { Bad_Opcode }, 5542 { VEX_W_TABLE (VEX_W_0F380A_P_2) }, 5543 }, 5544 5545 /* PREFIX_VEX_0F380B */ 5546 { 5547 { Bad_Opcode }, 5548 { Bad_Opcode }, 5549 { VEX_W_TABLE (VEX_W_0F380B_P_2) }, 5550 }, 5551 5552 /* PREFIX_VEX_0F380C */ 5553 { 5554 { Bad_Opcode }, 5555 { Bad_Opcode }, 5556 { VEX_W_TABLE (VEX_W_0F380C_P_2) }, 5557 }, 5558 5559 /* PREFIX_VEX_0F380D */ 5560 { 5561 { Bad_Opcode }, 5562 { Bad_Opcode }, 5563 { VEX_W_TABLE (VEX_W_0F380D_P_2) }, 5564 }, 5565 5566 /* PREFIX_VEX_0F380E */ 5567 { 5568 { Bad_Opcode }, 5569 { Bad_Opcode }, 5570 { VEX_W_TABLE (VEX_W_0F380E_P_2) }, 5571 }, 5572 5573 /* PREFIX_VEX_0F380F */ 5574 { 5575 { Bad_Opcode }, 5576 { Bad_Opcode }, 5577 { VEX_W_TABLE (VEX_W_0F380F_P_2) }, 5578 }, 5579 5580 /* PREFIX_VEX_0F3813 */ 5581 { 5582 { Bad_Opcode }, 5583 { Bad_Opcode }, 5584 { "vcvtph2ps", { XM, EXxmmq }, 0 }, 5585 }, 5586 5587 /* PREFIX_VEX_0F3816 */ 5588 { 5589 { Bad_Opcode }, 5590 { Bad_Opcode }, 5591 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, 5592 }, 5593 5594 /* PREFIX_VEX_0F3817 */ 5595 { 5596 { Bad_Opcode }, 5597 { Bad_Opcode }, 5598 { VEX_W_TABLE (VEX_W_0F3817_P_2) }, 5599 }, 5600 5601 /* PREFIX_VEX_0F3818 */ 5602 { 5603 { Bad_Opcode }, 5604 { Bad_Opcode }, 5605 { VEX_W_TABLE (VEX_W_0F3818_P_2) }, 5606 }, 5607 5608 /* PREFIX_VEX_0F3819 */ 5609 { 5610 { Bad_Opcode }, 5611 { Bad_Opcode }, 5612 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, 5613 }, 5614 5615 /* PREFIX_VEX_0F381A */ 5616 { 5617 { Bad_Opcode }, 5618 { Bad_Opcode }, 5619 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, 5620 }, 5621 5622 /* PREFIX_VEX_0F381C */ 5623 { 5624 { Bad_Opcode }, 5625 { Bad_Opcode }, 5626 { VEX_W_TABLE (VEX_W_0F381C_P_2) }, 5627 }, 5628 5629 /* PREFIX_VEX_0F381D */ 5630 { 5631 { Bad_Opcode }, 5632 { Bad_Opcode }, 5633 { VEX_W_TABLE (VEX_W_0F381D_P_2) }, 5634 }, 5635 5636 /* PREFIX_VEX_0F381E */ 5637 { 5638 { Bad_Opcode }, 5639 { Bad_Opcode }, 5640 { VEX_W_TABLE (VEX_W_0F381E_P_2) }, 5641 }, 5642 5643 /* PREFIX_VEX_0F3820 */ 5644 { 5645 { Bad_Opcode }, 5646 { Bad_Opcode }, 5647 { VEX_W_TABLE (VEX_W_0F3820_P_2) }, 5648 }, 5649 5650 /* PREFIX_VEX_0F3821 */ 5651 { 5652 { Bad_Opcode }, 5653 { Bad_Opcode }, 5654 { VEX_W_TABLE (VEX_W_0F3821_P_2) }, 5655 }, 5656 5657 /* PREFIX_VEX_0F3822 */ 5658 { 5659 { Bad_Opcode }, 5660 { Bad_Opcode }, 5661 { VEX_W_TABLE (VEX_W_0F3822_P_2) }, 5662 }, 5663 5664 /* PREFIX_VEX_0F3823 */ 5665 { 5666 { Bad_Opcode }, 5667 { Bad_Opcode }, 5668 { VEX_W_TABLE (VEX_W_0F3823_P_2) }, 5669 }, 5670 5671 /* PREFIX_VEX_0F3824 */ 5672 { 5673 { Bad_Opcode }, 5674 { Bad_Opcode }, 5675 { VEX_W_TABLE (VEX_W_0F3824_P_2) }, 5676 }, 5677 5678 /* PREFIX_VEX_0F3825 */ 5679 { 5680 { Bad_Opcode }, 5681 { Bad_Opcode }, 5682 { VEX_W_TABLE (VEX_W_0F3825_P_2) }, 5683 }, 5684 5685 /* PREFIX_VEX_0F3828 */ 5686 { 5687 { Bad_Opcode }, 5688 { Bad_Opcode }, 5689 { VEX_W_TABLE (VEX_W_0F3828_P_2) }, 5690 }, 5691 5692 /* PREFIX_VEX_0F3829 */ 5693 { 5694 { Bad_Opcode }, 5695 { Bad_Opcode }, 5696 { VEX_W_TABLE (VEX_W_0F3829_P_2) }, 5697 }, 5698 5699 /* PREFIX_VEX_0F382A */ 5700 { 5701 { Bad_Opcode }, 5702 { Bad_Opcode }, 5703 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, 5704 }, 5705 5706 /* PREFIX_VEX_0F382B */ 5707 { 5708 { Bad_Opcode }, 5709 { Bad_Opcode }, 5710 { VEX_W_TABLE (VEX_W_0F382B_P_2) }, 5711 }, 5712 5713 /* PREFIX_VEX_0F382C */ 5714 { 5715 { Bad_Opcode }, 5716 { Bad_Opcode }, 5717 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, 5718 }, 5719 5720 /* PREFIX_VEX_0F382D */ 5721 { 5722 { Bad_Opcode }, 5723 { Bad_Opcode }, 5724 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, 5725 }, 5726 5727 /* PREFIX_VEX_0F382E */ 5728 { 5729 { Bad_Opcode }, 5730 { Bad_Opcode }, 5731 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, 5732 }, 5733 5734 /* PREFIX_VEX_0F382F */ 5735 { 5736 { Bad_Opcode }, 5737 { Bad_Opcode }, 5738 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, 5739 }, 5740 5741 /* PREFIX_VEX_0F3830 */ 5742 { 5743 { Bad_Opcode }, 5744 { Bad_Opcode }, 5745 { VEX_W_TABLE (VEX_W_0F3830_P_2) }, 5746 }, 5747 5748 /* PREFIX_VEX_0F3831 */ 5749 { 5750 { Bad_Opcode }, 5751 { Bad_Opcode }, 5752 { VEX_W_TABLE (VEX_W_0F3831_P_2) }, 5753 }, 5754 5755 /* PREFIX_VEX_0F3832 */ 5756 { 5757 { Bad_Opcode }, 5758 { Bad_Opcode }, 5759 { VEX_W_TABLE (VEX_W_0F3832_P_2) }, 5760 }, 5761 5762 /* PREFIX_VEX_0F3833 */ 5763 { 5764 { Bad_Opcode }, 5765 { Bad_Opcode }, 5766 { VEX_W_TABLE (VEX_W_0F3833_P_2) }, 5767 }, 5768 5769 /* PREFIX_VEX_0F3834 */ 5770 { 5771 { Bad_Opcode }, 5772 { Bad_Opcode }, 5773 { VEX_W_TABLE (VEX_W_0F3834_P_2) }, 5774 }, 5775 5776 /* PREFIX_VEX_0F3835 */ 5777 { 5778 { Bad_Opcode }, 5779 { Bad_Opcode }, 5780 { VEX_W_TABLE (VEX_W_0F3835_P_2) }, 5781 }, 5782 5783 /* PREFIX_VEX_0F3836 */ 5784 { 5785 { Bad_Opcode }, 5786 { Bad_Opcode }, 5787 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, 5788 }, 5789 5790 /* PREFIX_VEX_0F3837 */ 5791 { 5792 { Bad_Opcode }, 5793 { Bad_Opcode }, 5794 { VEX_W_TABLE (VEX_W_0F3837_P_2) }, 5795 }, 5796 5797 /* PREFIX_VEX_0F3838 */ 5798 { 5799 { Bad_Opcode }, 5800 { Bad_Opcode }, 5801 { VEX_W_TABLE (VEX_W_0F3838_P_2) }, 5802 }, 5803 5804 /* PREFIX_VEX_0F3839 */ 5805 { 5806 { Bad_Opcode }, 5807 { Bad_Opcode }, 5808 { VEX_W_TABLE (VEX_W_0F3839_P_2) }, 5809 }, 5810 5811 /* PREFIX_VEX_0F383A */ 5812 { 5813 { Bad_Opcode }, 5814 { Bad_Opcode }, 5815 { VEX_W_TABLE (VEX_W_0F383A_P_2) }, 5816 }, 5817 5818 /* PREFIX_VEX_0F383B */ 5819 { 5820 { Bad_Opcode }, 5821 { Bad_Opcode }, 5822 { VEX_W_TABLE (VEX_W_0F383B_P_2) }, 5823 }, 5824 5825 /* PREFIX_VEX_0F383C */ 5826 { 5827 { Bad_Opcode }, 5828 { Bad_Opcode }, 5829 { VEX_W_TABLE (VEX_W_0F383C_P_2) }, 5830 }, 5831 5832 /* PREFIX_VEX_0F383D */ 5833 { 5834 { Bad_Opcode }, 5835 { Bad_Opcode }, 5836 { VEX_W_TABLE (VEX_W_0F383D_P_2) }, 5837 }, 5838 5839 /* PREFIX_VEX_0F383E */ 5840 { 5841 { Bad_Opcode }, 5842 { Bad_Opcode }, 5843 { VEX_W_TABLE (VEX_W_0F383E_P_2) }, 5844 }, 5845 5846 /* PREFIX_VEX_0F383F */ 5847 { 5848 { Bad_Opcode }, 5849 { Bad_Opcode }, 5850 { VEX_W_TABLE (VEX_W_0F383F_P_2) }, 5851 }, 5852 5853 /* PREFIX_VEX_0F3840 */ 5854 { 5855 { Bad_Opcode }, 5856 { Bad_Opcode }, 5857 { VEX_W_TABLE (VEX_W_0F3840_P_2) }, 5858 }, 5859 5860 /* PREFIX_VEX_0F3841 */ 5861 { 5862 { Bad_Opcode }, 5863 { Bad_Opcode }, 5864 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, 5865 }, 5866 5867 /* PREFIX_VEX_0F3845 */ 5868 { 5869 { Bad_Opcode }, 5870 { Bad_Opcode }, 5871 { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, 5872 }, 5873 5874 /* PREFIX_VEX_0F3846 */ 5875 { 5876 { Bad_Opcode }, 5877 { Bad_Opcode }, 5878 { VEX_W_TABLE (VEX_W_0F3846_P_2) }, 5879 }, 5880 5881 /* PREFIX_VEX_0F3847 */ 5882 { 5883 { Bad_Opcode }, 5884 { Bad_Opcode }, 5885 { "vpsllv%LW", { XM, Vex, EXx }, 0 }, 5886 }, 5887 5888 /* PREFIX_VEX_0F3858 */ 5889 { 5890 { Bad_Opcode }, 5891 { Bad_Opcode }, 5892 { VEX_W_TABLE (VEX_W_0F3858_P_2) }, 5893 }, 5894 5895 /* PREFIX_VEX_0F3859 */ 5896 { 5897 { Bad_Opcode }, 5898 { Bad_Opcode }, 5899 { VEX_W_TABLE (VEX_W_0F3859_P_2) }, 5900 }, 5901 5902 /* PREFIX_VEX_0F385A */ 5903 { 5904 { Bad_Opcode }, 5905 { Bad_Opcode }, 5906 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, 5907 }, 5908 5909 /* PREFIX_VEX_0F3878 */ 5910 { 5911 { Bad_Opcode }, 5912 { Bad_Opcode }, 5913 { VEX_W_TABLE (VEX_W_0F3878_P_2) }, 5914 }, 5915 5916 /* PREFIX_VEX_0F3879 */ 5917 { 5918 { Bad_Opcode }, 5919 { Bad_Opcode }, 5920 { VEX_W_TABLE (VEX_W_0F3879_P_2) }, 5921 }, 5922 5923 /* PREFIX_VEX_0F388C */ 5924 { 5925 { Bad_Opcode }, 5926 { Bad_Opcode }, 5927 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, 5928 }, 5929 5930 /* PREFIX_VEX_0F388E */ 5931 { 5932 { Bad_Opcode }, 5933 { Bad_Opcode }, 5934 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, 5935 }, 5936 5937 /* PREFIX_VEX_0F3890 */ 5938 { 5939 { Bad_Opcode }, 5940 { Bad_Opcode }, 5941 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, 5942 }, 5943 5944 /* PREFIX_VEX_0F3891 */ 5945 { 5946 { Bad_Opcode }, 5947 { Bad_Opcode }, 5948 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, 5949 }, 5950 5951 /* PREFIX_VEX_0F3892 */ 5952 { 5953 { Bad_Opcode }, 5954 { Bad_Opcode }, 5955 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, 5956 }, 5957 5958 /* PREFIX_VEX_0F3893 */ 5959 { 5960 { Bad_Opcode }, 5961 { Bad_Opcode }, 5962 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, 5963 }, 5964 5965 /* PREFIX_VEX_0F3896 */ 5966 { 5967 { Bad_Opcode }, 5968 { Bad_Opcode }, 5969 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, 5970 }, 5971 5972 /* PREFIX_VEX_0F3897 */ 5973 { 5974 { Bad_Opcode }, 5975 { Bad_Opcode }, 5976 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, 5977 }, 5978 5979 /* PREFIX_VEX_0F3898 */ 5980 { 5981 { Bad_Opcode }, 5982 { Bad_Opcode }, 5983 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, 5984 }, 5985 5986 /* PREFIX_VEX_0F3899 */ 5987 { 5988 { Bad_Opcode }, 5989 { Bad_Opcode }, 5990 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 5991 }, 5992 5993 /* PREFIX_VEX_0F389A */ 5994 { 5995 { Bad_Opcode }, 5996 { Bad_Opcode }, 5997 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, 5998 }, 5999 6000 /* PREFIX_VEX_0F389B */ 6001 { 6002 { Bad_Opcode }, 6003 { Bad_Opcode }, 6004 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6005 }, 6006 6007 /* PREFIX_VEX_0F389C */ 6008 { 6009 { Bad_Opcode }, 6010 { Bad_Opcode }, 6011 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, 6012 }, 6013 6014 /* PREFIX_VEX_0F389D */ 6015 { 6016 { Bad_Opcode }, 6017 { Bad_Opcode }, 6018 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6019 }, 6020 6021 /* PREFIX_VEX_0F389E */ 6022 { 6023 { Bad_Opcode }, 6024 { Bad_Opcode }, 6025 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, 6026 }, 6027 6028 /* PREFIX_VEX_0F389F */ 6029 { 6030 { Bad_Opcode }, 6031 { Bad_Opcode }, 6032 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6033 }, 6034 6035 /* PREFIX_VEX_0F38A6 */ 6036 { 6037 { Bad_Opcode }, 6038 { Bad_Opcode }, 6039 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, 6040 { Bad_Opcode }, 6041 }, 6042 6043 /* PREFIX_VEX_0F38A7 */ 6044 { 6045 { Bad_Opcode }, 6046 { Bad_Opcode }, 6047 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, 6048 }, 6049 6050 /* PREFIX_VEX_0F38A8 */ 6051 { 6052 { Bad_Opcode }, 6053 { Bad_Opcode }, 6054 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, 6055 }, 6056 6057 /* PREFIX_VEX_0F38A9 */ 6058 { 6059 { Bad_Opcode }, 6060 { Bad_Opcode }, 6061 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6062 }, 6063 6064 /* PREFIX_VEX_0F38AA */ 6065 { 6066 { Bad_Opcode }, 6067 { Bad_Opcode }, 6068 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, 6069 }, 6070 6071 /* PREFIX_VEX_0F38AB */ 6072 { 6073 { Bad_Opcode }, 6074 { Bad_Opcode }, 6075 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6076 }, 6077 6078 /* PREFIX_VEX_0F38AC */ 6079 { 6080 { Bad_Opcode }, 6081 { Bad_Opcode }, 6082 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, 6083 }, 6084 6085 /* PREFIX_VEX_0F38AD */ 6086 { 6087 { Bad_Opcode }, 6088 { Bad_Opcode }, 6089 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6090 }, 6091 6092 /* PREFIX_VEX_0F38AE */ 6093 { 6094 { Bad_Opcode }, 6095 { Bad_Opcode }, 6096 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, 6097 }, 6098 6099 /* PREFIX_VEX_0F38AF */ 6100 { 6101 { Bad_Opcode }, 6102 { Bad_Opcode }, 6103 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6104 }, 6105 6106 /* PREFIX_VEX_0F38B6 */ 6107 { 6108 { Bad_Opcode }, 6109 { Bad_Opcode }, 6110 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, 6111 }, 6112 6113 /* PREFIX_VEX_0F38B7 */ 6114 { 6115 { Bad_Opcode }, 6116 { Bad_Opcode }, 6117 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, 6118 }, 6119 6120 /* PREFIX_VEX_0F38B8 */ 6121 { 6122 { Bad_Opcode }, 6123 { Bad_Opcode }, 6124 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, 6125 }, 6126 6127 /* PREFIX_VEX_0F38B9 */ 6128 { 6129 { Bad_Opcode }, 6130 { Bad_Opcode }, 6131 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6132 }, 6133 6134 /* PREFIX_VEX_0F38BA */ 6135 { 6136 { Bad_Opcode }, 6137 { Bad_Opcode }, 6138 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, 6139 }, 6140 6141 /* PREFIX_VEX_0F38BB */ 6142 { 6143 { Bad_Opcode }, 6144 { Bad_Opcode }, 6145 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6146 }, 6147 6148 /* PREFIX_VEX_0F38BC */ 6149 { 6150 { Bad_Opcode }, 6151 { Bad_Opcode }, 6152 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, 6153 }, 6154 6155 /* PREFIX_VEX_0F38BD */ 6156 { 6157 { Bad_Opcode }, 6158 { Bad_Opcode }, 6159 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6160 }, 6161 6162 /* PREFIX_VEX_0F38BE */ 6163 { 6164 { Bad_Opcode }, 6165 { Bad_Opcode }, 6166 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, 6167 }, 6168 6169 /* PREFIX_VEX_0F38BF */ 6170 { 6171 { Bad_Opcode }, 6172 { Bad_Opcode }, 6173 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, 6174 }, 6175 6176 /* PREFIX_VEX_0F38DB */ 6177 { 6178 { Bad_Opcode }, 6179 { Bad_Opcode }, 6180 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, 6181 }, 6182 6183 /* PREFIX_VEX_0F38DC */ 6184 { 6185 { Bad_Opcode }, 6186 { Bad_Opcode }, 6187 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, 6188 }, 6189 6190 /* PREFIX_VEX_0F38DD */ 6191 { 6192 { Bad_Opcode }, 6193 { Bad_Opcode }, 6194 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, 6195 }, 6196 6197 /* PREFIX_VEX_0F38DE */ 6198 { 6199 { Bad_Opcode }, 6200 { Bad_Opcode }, 6201 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, 6202 }, 6203 6204 /* PREFIX_VEX_0F38DF */ 6205 { 6206 { Bad_Opcode }, 6207 { Bad_Opcode }, 6208 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, 6209 }, 6210 6211 /* PREFIX_VEX_0F38F2 */ 6212 { 6213 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, 6214 }, 6215 6216 /* PREFIX_VEX_0F38F3_REG_1 */ 6217 { 6218 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, 6219 }, 6220 6221 /* PREFIX_VEX_0F38F3_REG_2 */ 6222 { 6223 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, 6224 }, 6225 6226 /* PREFIX_VEX_0F38F3_REG_3 */ 6227 { 6228 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, 6229 }, 6230 6231 /* PREFIX_VEX_0F38F5 */ 6232 { 6233 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, 6234 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, 6235 { Bad_Opcode }, 6236 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, 6237 }, 6238 6239 /* PREFIX_VEX_0F38F6 */ 6240 { 6241 { Bad_Opcode }, 6242 { Bad_Opcode }, 6243 { Bad_Opcode }, 6244 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, 6245 }, 6246 6247 /* PREFIX_VEX_0F38F7 */ 6248 { 6249 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, 6250 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, 6251 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, 6252 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, 6253 }, 6254 6255 /* PREFIX_VEX_0F3A00 */ 6256 { 6257 { Bad_Opcode }, 6258 { Bad_Opcode }, 6259 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, 6260 }, 6261 6262 /* PREFIX_VEX_0F3A01 */ 6263 { 6264 { Bad_Opcode }, 6265 { Bad_Opcode }, 6266 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, 6267 }, 6268 6269 /* PREFIX_VEX_0F3A02 */ 6270 { 6271 { Bad_Opcode }, 6272 { Bad_Opcode }, 6273 { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, 6274 }, 6275 6276 /* PREFIX_VEX_0F3A04 */ 6277 { 6278 { Bad_Opcode }, 6279 { Bad_Opcode }, 6280 { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, 6281 }, 6282 6283 /* PREFIX_VEX_0F3A05 */ 6284 { 6285 { Bad_Opcode }, 6286 { Bad_Opcode }, 6287 { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, 6288 }, 6289 6290 /* PREFIX_VEX_0F3A06 */ 6291 { 6292 { Bad_Opcode }, 6293 { Bad_Opcode }, 6294 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, 6295 }, 6296 6297 /* PREFIX_VEX_0F3A08 */ 6298 { 6299 { Bad_Opcode }, 6300 { Bad_Opcode }, 6301 { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, 6302 }, 6303 6304 /* PREFIX_VEX_0F3A09 */ 6305 { 6306 { Bad_Opcode }, 6307 { Bad_Opcode }, 6308 { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, 6309 }, 6310 6311 /* PREFIX_VEX_0F3A0A */ 6312 { 6313 { Bad_Opcode }, 6314 { Bad_Opcode }, 6315 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, 6316 }, 6317 6318 /* PREFIX_VEX_0F3A0B */ 6319 { 6320 { Bad_Opcode }, 6321 { Bad_Opcode }, 6322 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, 6323 }, 6324 6325 /* PREFIX_VEX_0F3A0C */ 6326 { 6327 { Bad_Opcode }, 6328 { Bad_Opcode }, 6329 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, 6330 }, 6331 6332 /* PREFIX_VEX_0F3A0D */ 6333 { 6334 { Bad_Opcode }, 6335 { Bad_Opcode }, 6336 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, 6337 }, 6338 6339 /* PREFIX_VEX_0F3A0E */ 6340 { 6341 { Bad_Opcode }, 6342 { Bad_Opcode }, 6343 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, 6344 }, 6345 6346 /* PREFIX_VEX_0F3A0F */ 6347 { 6348 { Bad_Opcode }, 6349 { Bad_Opcode }, 6350 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, 6351 }, 6352 6353 /* PREFIX_VEX_0F3A14 */ 6354 { 6355 { Bad_Opcode }, 6356 { Bad_Opcode }, 6357 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, 6358 }, 6359 6360 /* PREFIX_VEX_0F3A15 */ 6361 { 6362 { Bad_Opcode }, 6363 { Bad_Opcode }, 6364 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, 6365 }, 6366 6367 /* PREFIX_VEX_0F3A16 */ 6368 { 6369 { Bad_Opcode }, 6370 { Bad_Opcode }, 6371 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, 6372 }, 6373 6374 /* PREFIX_VEX_0F3A17 */ 6375 { 6376 { Bad_Opcode }, 6377 { Bad_Opcode }, 6378 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, 6379 }, 6380 6381 /* PREFIX_VEX_0F3A18 */ 6382 { 6383 { Bad_Opcode }, 6384 { Bad_Opcode }, 6385 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, 6386 }, 6387 6388 /* PREFIX_VEX_0F3A19 */ 6389 { 6390 { Bad_Opcode }, 6391 { Bad_Opcode }, 6392 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, 6393 }, 6394 6395 /* PREFIX_VEX_0F3A1D */ 6396 { 6397 { Bad_Opcode }, 6398 { Bad_Opcode }, 6399 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, 6400 }, 6401 6402 /* PREFIX_VEX_0F3A20 */ 6403 { 6404 { Bad_Opcode }, 6405 { Bad_Opcode }, 6406 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, 6407 }, 6408 6409 /* PREFIX_VEX_0F3A21 */ 6410 { 6411 { Bad_Opcode }, 6412 { Bad_Opcode }, 6413 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, 6414 }, 6415 6416 /* PREFIX_VEX_0F3A22 */ 6417 { 6418 { Bad_Opcode }, 6419 { Bad_Opcode }, 6420 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, 6421 }, 6422 6423 /* PREFIX_VEX_0F3A30 */ 6424 { 6425 { Bad_Opcode }, 6426 { Bad_Opcode }, 6427 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, 6428 }, 6429 6430 /* PREFIX_VEX_0F3A31 */ 6431 { 6432 { Bad_Opcode }, 6433 { Bad_Opcode }, 6434 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, 6435 }, 6436 6437 /* PREFIX_VEX_0F3A32 */ 6438 { 6439 { Bad_Opcode }, 6440 { Bad_Opcode }, 6441 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, 6442 }, 6443 6444 /* PREFIX_VEX_0F3A33 */ 6445 { 6446 { Bad_Opcode }, 6447 { Bad_Opcode }, 6448 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, 6449 }, 6450 6451 /* PREFIX_VEX_0F3A38 */ 6452 { 6453 { Bad_Opcode }, 6454 { Bad_Opcode }, 6455 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, 6456 }, 6457 6458 /* PREFIX_VEX_0F3A39 */ 6459 { 6460 { Bad_Opcode }, 6461 { Bad_Opcode }, 6462 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, 6463 }, 6464 6465 /* PREFIX_VEX_0F3A40 */ 6466 { 6467 { Bad_Opcode }, 6468 { Bad_Opcode }, 6469 { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, 6470 }, 6471 6472 /* PREFIX_VEX_0F3A41 */ 6473 { 6474 { Bad_Opcode }, 6475 { Bad_Opcode }, 6476 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, 6477 }, 6478 6479 /* PREFIX_VEX_0F3A42 */ 6480 { 6481 { Bad_Opcode }, 6482 { Bad_Opcode }, 6483 { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, 6484 }, 6485 6486 /* PREFIX_VEX_0F3A44 */ 6487 { 6488 { Bad_Opcode }, 6489 { Bad_Opcode }, 6490 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, 6491 }, 6492 6493 /* PREFIX_VEX_0F3A46 */ 6494 { 6495 { Bad_Opcode }, 6496 { Bad_Opcode }, 6497 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, 6498 }, 6499 6500 /* PREFIX_VEX_0F3A48 */ 6501 { 6502 { Bad_Opcode }, 6503 { Bad_Opcode }, 6504 { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, 6505 }, 6506 6507 /* PREFIX_VEX_0F3A49 */ 6508 { 6509 { Bad_Opcode }, 6510 { Bad_Opcode }, 6511 { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, 6512 }, 6513 6514 /* PREFIX_VEX_0F3A4A */ 6515 { 6516 { Bad_Opcode }, 6517 { Bad_Opcode }, 6518 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, 6519 }, 6520 6521 /* PREFIX_VEX_0F3A4B */ 6522 { 6523 { Bad_Opcode }, 6524 { Bad_Opcode }, 6525 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, 6526 }, 6527 6528 /* PREFIX_VEX_0F3A4C */ 6529 { 6530 { Bad_Opcode }, 6531 { Bad_Opcode }, 6532 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, 6533 }, 6534 6535 /* PREFIX_VEX_0F3A5C */ 6536 { 6537 { Bad_Opcode }, 6538 { Bad_Opcode }, 6539 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6540 }, 6541 6542 /* PREFIX_VEX_0F3A5D */ 6543 { 6544 { Bad_Opcode }, 6545 { Bad_Opcode }, 6546 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6547 }, 6548 6549 /* PREFIX_VEX_0F3A5E */ 6550 { 6551 { Bad_Opcode }, 6552 { Bad_Opcode }, 6553 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6554 }, 6555 6556 /* PREFIX_VEX_0F3A5F */ 6557 { 6558 { Bad_Opcode }, 6559 { Bad_Opcode }, 6560 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6561 }, 6562 6563 /* PREFIX_VEX_0F3A60 */ 6564 { 6565 { Bad_Opcode }, 6566 { Bad_Opcode }, 6567 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, 6568 { Bad_Opcode }, 6569 }, 6570 6571 /* PREFIX_VEX_0F3A61 */ 6572 { 6573 { Bad_Opcode }, 6574 { Bad_Opcode }, 6575 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, 6576 }, 6577 6578 /* PREFIX_VEX_0F3A62 */ 6579 { 6580 { Bad_Opcode }, 6581 { Bad_Opcode }, 6582 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, 6583 }, 6584 6585 /* PREFIX_VEX_0F3A63 */ 6586 { 6587 { Bad_Opcode }, 6588 { Bad_Opcode }, 6589 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, 6590 }, 6591 6592 /* PREFIX_VEX_0F3A68 */ 6593 { 6594 { Bad_Opcode }, 6595 { Bad_Opcode }, 6596 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6597 }, 6598 6599 /* PREFIX_VEX_0F3A69 */ 6600 { 6601 { Bad_Opcode }, 6602 { Bad_Opcode }, 6603 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6604 }, 6605 6606 /* PREFIX_VEX_0F3A6A */ 6607 { 6608 { Bad_Opcode }, 6609 { Bad_Opcode }, 6610 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, 6611 }, 6612 6613 /* PREFIX_VEX_0F3A6B */ 6614 { 6615 { Bad_Opcode }, 6616 { Bad_Opcode }, 6617 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, 6618 }, 6619 6620 /* PREFIX_VEX_0F3A6C */ 6621 { 6622 { Bad_Opcode }, 6623 { Bad_Opcode }, 6624 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6625 }, 6626 6627 /* PREFIX_VEX_0F3A6D */ 6628 { 6629 { Bad_Opcode }, 6630 { Bad_Opcode }, 6631 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6632 }, 6633 6634 /* PREFIX_VEX_0F3A6E */ 6635 { 6636 { Bad_Opcode }, 6637 { Bad_Opcode }, 6638 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, 6639 }, 6640 6641 /* PREFIX_VEX_0F3A6F */ 6642 { 6643 { Bad_Opcode }, 6644 { Bad_Opcode }, 6645 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, 6646 }, 6647 6648 /* PREFIX_VEX_0F3A78 */ 6649 { 6650 { Bad_Opcode }, 6651 { Bad_Opcode }, 6652 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6653 }, 6654 6655 /* PREFIX_VEX_0F3A79 */ 6656 { 6657 { Bad_Opcode }, 6658 { Bad_Opcode }, 6659 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6660 }, 6661 6662 /* PREFIX_VEX_0F3A7A */ 6663 { 6664 { Bad_Opcode }, 6665 { Bad_Opcode }, 6666 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, 6667 }, 6668 6669 /* PREFIX_VEX_0F3A7B */ 6670 { 6671 { Bad_Opcode }, 6672 { Bad_Opcode }, 6673 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, 6674 }, 6675 6676 /* PREFIX_VEX_0F3A7C */ 6677 { 6678 { Bad_Opcode }, 6679 { Bad_Opcode }, 6680 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6681 { Bad_Opcode }, 6682 }, 6683 6684 /* PREFIX_VEX_0F3A7D */ 6685 { 6686 { Bad_Opcode }, 6687 { Bad_Opcode }, 6688 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 6689 }, 6690 6691 /* PREFIX_VEX_0F3A7E */ 6692 { 6693 { Bad_Opcode }, 6694 { Bad_Opcode }, 6695 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, 6696 }, 6697 6698 /* PREFIX_VEX_0F3A7F */ 6699 { 6700 { Bad_Opcode }, 6701 { Bad_Opcode }, 6702 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, 6703 }, 6704 6705 /* PREFIX_VEX_0F3ADF */ 6706 { 6707 { Bad_Opcode }, 6708 { Bad_Opcode }, 6709 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, 6710 }, 6711 6712 /* PREFIX_VEX_0F3AF0 */ 6713 { 6714 { Bad_Opcode }, 6715 { Bad_Opcode }, 6716 { Bad_Opcode }, 6717 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, 6718 }, 6719 6720 #define NEED_PREFIX_TABLE 6721 #include "i386-dis-evex.h" 6722 #undef NEED_PREFIX_TABLE 6723 }; 6724 6725 static const struct dis386 x86_64_table[][2] = { 6726 /* X86_64_06 */ 6727 { 6728 { "pushP", { es }, 0 }, 6729 }, 6730 6731 /* X86_64_07 */ 6732 { 6733 { "popP", { es }, 0 }, 6734 }, 6735 6736 /* X86_64_0D */ 6737 { 6738 { "pushP", { cs }, 0 }, 6739 }, 6740 6741 /* X86_64_16 */ 6742 { 6743 { "pushP", { ss }, 0 }, 6744 }, 6745 6746 /* X86_64_17 */ 6747 { 6748 { "popP", { ss }, 0 }, 6749 }, 6750 6751 /* X86_64_1E */ 6752 { 6753 { "pushP", { ds }, 0 }, 6754 }, 6755 6756 /* X86_64_1F */ 6757 { 6758 { "popP", { ds }, 0 }, 6759 }, 6760 6761 /* X86_64_27 */ 6762 { 6763 { "daa", { XX }, 0 }, 6764 }, 6765 6766 /* X86_64_2F */ 6767 { 6768 { "das", { XX }, 0 }, 6769 }, 6770 6771 /* X86_64_37 */ 6772 { 6773 { "aaa", { XX }, 0 }, 6774 }, 6775 6776 /* X86_64_3F */ 6777 { 6778 { "aas", { XX }, 0 }, 6779 }, 6780 6781 /* X86_64_60 */ 6782 { 6783 { "pushaP", { XX }, 0 }, 6784 }, 6785 6786 /* X86_64_61 */ 6787 { 6788 { "popaP", { XX }, 0 }, 6789 }, 6790 6791 /* X86_64_62 */ 6792 { 6793 { MOD_TABLE (MOD_62_32BIT) }, 6794 { EVEX_TABLE (EVEX_0F) }, 6795 }, 6796 6797 /* X86_64_63 */ 6798 { 6799 { "arpl", { Ew, Gw }, 0 }, 6800 { "movs{lq|xd}", { Gv, Ed }, 0 }, 6801 }, 6802 6803 /* X86_64_6D */ 6804 { 6805 { "ins{R|}", { Yzr, indirDX }, 0 }, 6806 { "ins{G|}", { Yzr, indirDX }, 0 }, 6807 }, 6808 6809 /* X86_64_6F */ 6810 { 6811 { "outs{R|}", { indirDXr, Xz }, 0 }, 6812 { "outs{G|}", { indirDXr, Xz }, 0 }, 6813 }, 6814 6815 /* X86_64_9A */ 6816 { 6817 { "Jcall{T|}", { Ap }, 0 }, 6818 }, 6819 6820 /* X86_64_C4 */ 6821 { 6822 { MOD_TABLE (MOD_C4_32BIT) }, 6823 { VEX_C4_TABLE (VEX_0F) }, 6824 }, 6825 6826 /* X86_64_C5 */ 6827 { 6828 { MOD_TABLE (MOD_C5_32BIT) }, 6829 { VEX_C5_TABLE (VEX_0F) }, 6830 }, 6831 6832 /* X86_64_CE */ 6833 { 6834 { "into", { XX }, 0 }, 6835 }, 6836 6837 /* X86_64_D4 */ 6838 { 6839 { "aam", { Ib }, 0 }, 6840 }, 6841 6842 /* X86_64_D5 */ 6843 { 6844 { "aad", { Ib }, 0 }, 6845 }, 6846 6847 /* X86_64_E8 */ 6848 { 6849 { "callP", { Jv, BND }, 0 }, 6850 { "call@", { Jv, BND }, 0 } 6851 }, 6852 6853 /* X86_64_E9 */ 6854 { 6855 { "jmpP", { Jv, BND }, 0 }, 6856 { "jmp@", { Jv, BND }, 0 } 6857 }, 6858 6859 /* X86_64_EA */ 6860 { 6861 { "Jjmp{T|}", { Ap }, 0 }, 6862 }, 6863 6864 /* X86_64_0F01_REG_0 */ 6865 { 6866 { "sgdt{Q|IQ}", { M }, 0 }, 6867 { "sgdt", { M }, 0 }, 6868 }, 6869 6870 /* X86_64_0F01_REG_1 */ 6871 { 6872 { "sidt{Q|IQ}", { M }, 0 }, 6873 { "sidt", { M }, 0 }, 6874 }, 6875 6876 /* X86_64_0F01_REG_2 */ 6877 { 6878 { "lgdt{Q|Q}", { M }, 0 }, 6879 { "lgdt", { M }, 0 }, 6880 }, 6881 6882 /* X86_64_0F01_REG_3 */ 6883 { 6884 { "lidt{Q|Q}", { M }, 0 }, 6885 { "lidt", { M }, 0 }, 6886 }, 6887 }; 6888 6889 static const struct dis386 three_byte_table[][256] = { 6890 6891 /* THREE_BYTE_0F38 */ 6892 { 6893 /* 00 */ 6894 { "pshufb", { MX, EM }, PREFIX_OPCODE }, 6895 { "phaddw", { MX, EM }, PREFIX_OPCODE }, 6896 { "phaddd", { MX, EM }, PREFIX_OPCODE }, 6897 { "phaddsw", { MX, EM }, PREFIX_OPCODE }, 6898 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, 6899 { "phsubw", { MX, EM }, PREFIX_OPCODE }, 6900 { "phsubd", { MX, EM }, PREFIX_OPCODE }, 6901 { "phsubsw", { MX, EM }, PREFIX_OPCODE }, 6902 /* 08 */ 6903 { "psignb", { MX, EM }, PREFIX_OPCODE }, 6904 { "psignw", { MX, EM }, PREFIX_OPCODE }, 6905 { "psignd", { MX, EM }, PREFIX_OPCODE }, 6906 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, 6907 { Bad_Opcode }, 6908 { Bad_Opcode }, 6909 { Bad_Opcode }, 6910 { Bad_Opcode }, 6911 /* 10 */ 6912 { PREFIX_TABLE (PREFIX_0F3810) }, 6913 { Bad_Opcode }, 6914 { Bad_Opcode }, 6915 { Bad_Opcode }, 6916 { PREFIX_TABLE (PREFIX_0F3814) }, 6917 { PREFIX_TABLE (PREFIX_0F3815) }, 6918 { Bad_Opcode }, 6919 { PREFIX_TABLE (PREFIX_0F3817) }, 6920 /* 18 */ 6921 { Bad_Opcode }, 6922 { Bad_Opcode }, 6923 { Bad_Opcode }, 6924 { Bad_Opcode }, 6925 { "pabsb", { MX, EM }, PREFIX_OPCODE }, 6926 { "pabsw", { MX, EM }, PREFIX_OPCODE }, 6927 { "pabsd", { MX, EM }, PREFIX_OPCODE }, 6928 { Bad_Opcode }, 6929 /* 20 */ 6930 { PREFIX_TABLE (PREFIX_0F3820) }, 6931 { PREFIX_TABLE (PREFIX_0F3821) }, 6932 { PREFIX_TABLE (PREFIX_0F3822) }, 6933 { PREFIX_TABLE (PREFIX_0F3823) }, 6934 { PREFIX_TABLE (PREFIX_0F3824) }, 6935 { PREFIX_TABLE (PREFIX_0F3825) }, 6936 { Bad_Opcode }, 6937 { Bad_Opcode }, 6938 /* 28 */ 6939 { PREFIX_TABLE (PREFIX_0F3828) }, 6940 { PREFIX_TABLE (PREFIX_0F3829) }, 6941 { PREFIX_TABLE (PREFIX_0F382A) }, 6942 { PREFIX_TABLE (PREFIX_0F382B) }, 6943 { Bad_Opcode }, 6944 { Bad_Opcode }, 6945 { Bad_Opcode }, 6946 { Bad_Opcode }, 6947 /* 30 */ 6948 { PREFIX_TABLE (PREFIX_0F3830) }, 6949 { PREFIX_TABLE (PREFIX_0F3831) }, 6950 { PREFIX_TABLE (PREFIX_0F3832) }, 6951 { PREFIX_TABLE (PREFIX_0F3833) }, 6952 { PREFIX_TABLE (PREFIX_0F3834) }, 6953 { PREFIX_TABLE (PREFIX_0F3835) }, 6954 { Bad_Opcode }, 6955 { PREFIX_TABLE (PREFIX_0F3837) }, 6956 /* 38 */ 6957 { PREFIX_TABLE (PREFIX_0F3838) }, 6958 { PREFIX_TABLE (PREFIX_0F3839) }, 6959 { PREFIX_TABLE (PREFIX_0F383A) }, 6960 { PREFIX_TABLE (PREFIX_0F383B) }, 6961 { PREFIX_TABLE (PREFIX_0F383C) }, 6962 { PREFIX_TABLE (PREFIX_0F383D) }, 6963 { PREFIX_TABLE (PREFIX_0F383E) }, 6964 { PREFIX_TABLE (PREFIX_0F383F) }, 6965 /* 40 */ 6966 { PREFIX_TABLE (PREFIX_0F3840) }, 6967 { PREFIX_TABLE (PREFIX_0F3841) }, 6968 { Bad_Opcode }, 6969 { Bad_Opcode }, 6970 { Bad_Opcode }, 6971 { Bad_Opcode }, 6972 { Bad_Opcode }, 6973 { Bad_Opcode }, 6974 /* 48 */ 6975 { Bad_Opcode }, 6976 { Bad_Opcode }, 6977 { Bad_Opcode }, 6978 { Bad_Opcode }, 6979 { Bad_Opcode }, 6980 { Bad_Opcode }, 6981 { Bad_Opcode }, 6982 { Bad_Opcode }, 6983 /* 50 */ 6984 { Bad_Opcode }, 6985 { Bad_Opcode }, 6986 { Bad_Opcode }, 6987 { Bad_Opcode }, 6988 { Bad_Opcode }, 6989 { Bad_Opcode }, 6990 { Bad_Opcode }, 6991 { Bad_Opcode }, 6992 /* 58 */ 6993 { Bad_Opcode }, 6994 { Bad_Opcode }, 6995 { Bad_Opcode }, 6996 { Bad_Opcode }, 6997 { Bad_Opcode }, 6998 { Bad_Opcode }, 6999 { Bad_Opcode }, 7000 { Bad_Opcode }, 7001 /* 60 */ 7002 { Bad_Opcode }, 7003 { Bad_Opcode }, 7004 { Bad_Opcode }, 7005 { Bad_Opcode }, 7006 { Bad_Opcode }, 7007 { Bad_Opcode }, 7008 { Bad_Opcode }, 7009 { Bad_Opcode }, 7010 /* 68 */ 7011 { Bad_Opcode }, 7012 { Bad_Opcode }, 7013 { Bad_Opcode }, 7014 { Bad_Opcode }, 7015 { Bad_Opcode }, 7016 { Bad_Opcode }, 7017 { Bad_Opcode }, 7018 { Bad_Opcode }, 7019 /* 70 */ 7020 { Bad_Opcode }, 7021 { Bad_Opcode }, 7022 { Bad_Opcode }, 7023 { Bad_Opcode }, 7024 { Bad_Opcode }, 7025 { Bad_Opcode }, 7026 { Bad_Opcode }, 7027 { Bad_Opcode }, 7028 /* 78 */ 7029 { Bad_Opcode }, 7030 { Bad_Opcode }, 7031 { Bad_Opcode }, 7032 { Bad_Opcode }, 7033 { Bad_Opcode }, 7034 { Bad_Opcode }, 7035 { Bad_Opcode }, 7036 { Bad_Opcode }, 7037 /* 80 */ 7038 { PREFIX_TABLE (PREFIX_0F3880) }, 7039 { PREFIX_TABLE (PREFIX_0F3881) }, 7040 { PREFIX_TABLE (PREFIX_0F3882) }, 7041 { Bad_Opcode }, 7042 { Bad_Opcode }, 7043 { Bad_Opcode }, 7044 { Bad_Opcode }, 7045 { Bad_Opcode }, 7046 /* 88 */ 7047 { Bad_Opcode }, 7048 { Bad_Opcode }, 7049 { Bad_Opcode }, 7050 { Bad_Opcode }, 7051 { Bad_Opcode }, 7052 { Bad_Opcode }, 7053 { Bad_Opcode }, 7054 { Bad_Opcode }, 7055 /* 90 */ 7056 { Bad_Opcode }, 7057 { Bad_Opcode }, 7058 { Bad_Opcode }, 7059 { Bad_Opcode }, 7060 { Bad_Opcode }, 7061 { Bad_Opcode }, 7062 { Bad_Opcode }, 7063 { Bad_Opcode }, 7064 /* 98 */ 7065 { Bad_Opcode }, 7066 { Bad_Opcode }, 7067 { Bad_Opcode }, 7068 { Bad_Opcode }, 7069 { Bad_Opcode }, 7070 { Bad_Opcode }, 7071 { Bad_Opcode }, 7072 { Bad_Opcode }, 7073 /* a0 */ 7074 { Bad_Opcode }, 7075 { Bad_Opcode }, 7076 { Bad_Opcode }, 7077 { Bad_Opcode }, 7078 { Bad_Opcode }, 7079 { Bad_Opcode }, 7080 { Bad_Opcode }, 7081 { Bad_Opcode }, 7082 /* a8 */ 7083 { Bad_Opcode }, 7084 { Bad_Opcode }, 7085 { Bad_Opcode }, 7086 { Bad_Opcode }, 7087 { Bad_Opcode }, 7088 { Bad_Opcode }, 7089 { Bad_Opcode }, 7090 { Bad_Opcode }, 7091 /* b0 */ 7092 { Bad_Opcode }, 7093 { Bad_Opcode }, 7094 { Bad_Opcode }, 7095 { Bad_Opcode }, 7096 { Bad_Opcode }, 7097 { Bad_Opcode }, 7098 { Bad_Opcode }, 7099 { Bad_Opcode }, 7100 /* b8 */ 7101 { Bad_Opcode }, 7102 { Bad_Opcode }, 7103 { Bad_Opcode }, 7104 { Bad_Opcode }, 7105 { Bad_Opcode }, 7106 { Bad_Opcode }, 7107 { Bad_Opcode }, 7108 { Bad_Opcode }, 7109 /* c0 */ 7110 { Bad_Opcode }, 7111 { Bad_Opcode }, 7112 { Bad_Opcode }, 7113 { Bad_Opcode }, 7114 { Bad_Opcode }, 7115 { Bad_Opcode }, 7116 { Bad_Opcode }, 7117 { Bad_Opcode }, 7118 /* c8 */ 7119 { PREFIX_TABLE (PREFIX_0F38C8) }, 7120 { PREFIX_TABLE (PREFIX_0F38C9) }, 7121 { PREFIX_TABLE (PREFIX_0F38CA) }, 7122 { PREFIX_TABLE (PREFIX_0F38CB) }, 7123 { PREFIX_TABLE (PREFIX_0F38CC) }, 7124 { PREFIX_TABLE (PREFIX_0F38CD) }, 7125 { Bad_Opcode }, 7126 { Bad_Opcode }, 7127 /* d0 */ 7128 { Bad_Opcode }, 7129 { Bad_Opcode }, 7130 { Bad_Opcode }, 7131 { Bad_Opcode }, 7132 { Bad_Opcode }, 7133 { Bad_Opcode }, 7134 { Bad_Opcode }, 7135 { Bad_Opcode }, 7136 /* d8 */ 7137 { Bad_Opcode }, 7138 { Bad_Opcode }, 7139 { Bad_Opcode }, 7140 { PREFIX_TABLE (PREFIX_0F38DB) }, 7141 { PREFIX_TABLE (PREFIX_0F38DC) }, 7142 { PREFIX_TABLE (PREFIX_0F38DD) }, 7143 { PREFIX_TABLE (PREFIX_0F38DE) }, 7144 { PREFIX_TABLE (PREFIX_0F38DF) }, 7145 /* e0 */ 7146 { Bad_Opcode }, 7147 { Bad_Opcode }, 7148 { Bad_Opcode }, 7149 { Bad_Opcode }, 7150 { Bad_Opcode }, 7151 { Bad_Opcode }, 7152 { Bad_Opcode }, 7153 { Bad_Opcode }, 7154 /* e8 */ 7155 { Bad_Opcode }, 7156 { Bad_Opcode }, 7157 { Bad_Opcode }, 7158 { Bad_Opcode }, 7159 { Bad_Opcode }, 7160 { Bad_Opcode }, 7161 { Bad_Opcode }, 7162 { Bad_Opcode }, 7163 /* f0 */ 7164 { PREFIX_TABLE (PREFIX_0F38F0) }, 7165 { PREFIX_TABLE (PREFIX_0F38F1) }, 7166 { Bad_Opcode }, 7167 { Bad_Opcode }, 7168 { Bad_Opcode }, 7169 { Bad_Opcode }, 7170 { PREFIX_TABLE (PREFIX_0F38F6) }, 7171 { Bad_Opcode }, 7172 /* f8 */ 7173 { Bad_Opcode }, 7174 { Bad_Opcode }, 7175 { Bad_Opcode }, 7176 { Bad_Opcode }, 7177 { Bad_Opcode }, 7178 { Bad_Opcode }, 7179 { Bad_Opcode }, 7180 { Bad_Opcode }, 7181 }, 7182 /* THREE_BYTE_0F3A */ 7183 { 7184 /* 00 */ 7185 { Bad_Opcode }, 7186 { Bad_Opcode }, 7187 { Bad_Opcode }, 7188 { Bad_Opcode }, 7189 { Bad_Opcode }, 7190 { Bad_Opcode }, 7191 { Bad_Opcode }, 7192 { Bad_Opcode }, 7193 /* 08 */ 7194 { PREFIX_TABLE (PREFIX_0F3A08) }, 7195 { PREFIX_TABLE (PREFIX_0F3A09) }, 7196 { PREFIX_TABLE (PREFIX_0F3A0A) }, 7197 { PREFIX_TABLE (PREFIX_0F3A0B) }, 7198 { PREFIX_TABLE (PREFIX_0F3A0C) }, 7199 { PREFIX_TABLE (PREFIX_0F3A0D) }, 7200 { PREFIX_TABLE (PREFIX_0F3A0E) }, 7201 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, 7202 /* 10 */ 7203 { Bad_Opcode }, 7204 { Bad_Opcode }, 7205 { Bad_Opcode }, 7206 { Bad_Opcode }, 7207 { PREFIX_TABLE (PREFIX_0F3A14) }, 7208 { PREFIX_TABLE (PREFIX_0F3A15) }, 7209 { PREFIX_TABLE (PREFIX_0F3A16) }, 7210 { PREFIX_TABLE (PREFIX_0F3A17) }, 7211 /* 18 */ 7212 { Bad_Opcode }, 7213 { Bad_Opcode }, 7214 { Bad_Opcode }, 7215 { Bad_Opcode }, 7216 { Bad_Opcode }, 7217 { Bad_Opcode }, 7218 { Bad_Opcode }, 7219 { Bad_Opcode }, 7220 /* 20 */ 7221 { PREFIX_TABLE (PREFIX_0F3A20) }, 7222 { PREFIX_TABLE (PREFIX_0F3A21) }, 7223 { PREFIX_TABLE (PREFIX_0F3A22) }, 7224 { Bad_Opcode }, 7225 { Bad_Opcode }, 7226 { Bad_Opcode }, 7227 { Bad_Opcode }, 7228 { Bad_Opcode }, 7229 /* 28 */ 7230 { Bad_Opcode }, 7231 { Bad_Opcode }, 7232 { Bad_Opcode }, 7233 { Bad_Opcode }, 7234 { Bad_Opcode }, 7235 { Bad_Opcode }, 7236 { Bad_Opcode }, 7237 { Bad_Opcode }, 7238 /* 30 */ 7239 { Bad_Opcode }, 7240 { Bad_Opcode }, 7241 { Bad_Opcode }, 7242 { Bad_Opcode }, 7243 { Bad_Opcode }, 7244 { Bad_Opcode }, 7245 { Bad_Opcode }, 7246 { Bad_Opcode }, 7247 /* 38 */ 7248 { Bad_Opcode }, 7249 { Bad_Opcode }, 7250 { Bad_Opcode }, 7251 { Bad_Opcode }, 7252 { Bad_Opcode }, 7253 { Bad_Opcode }, 7254 { Bad_Opcode }, 7255 { Bad_Opcode }, 7256 /* 40 */ 7257 { PREFIX_TABLE (PREFIX_0F3A40) }, 7258 { PREFIX_TABLE (PREFIX_0F3A41) }, 7259 { PREFIX_TABLE (PREFIX_0F3A42) }, 7260 { Bad_Opcode }, 7261 { PREFIX_TABLE (PREFIX_0F3A44) }, 7262 { Bad_Opcode }, 7263 { Bad_Opcode }, 7264 { Bad_Opcode }, 7265 /* 48 */ 7266 { Bad_Opcode }, 7267 { Bad_Opcode }, 7268 { Bad_Opcode }, 7269 { Bad_Opcode }, 7270 { Bad_Opcode }, 7271 { Bad_Opcode }, 7272 { Bad_Opcode }, 7273 { Bad_Opcode }, 7274 /* 50 */ 7275 { Bad_Opcode }, 7276 { Bad_Opcode }, 7277 { Bad_Opcode }, 7278 { Bad_Opcode }, 7279 { Bad_Opcode }, 7280 { Bad_Opcode }, 7281 { Bad_Opcode }, 7282 { Bad_Opcode }, 7283 /* 58 */ 7284 { Bad_Opcode }, 7285 { Bad_Opcode }, 7286 { Bad_Opcode }, 7287 { Bad_Opcode }, 7288 { Bad_Opcode }, 7289 { Bad_Opcode }, 7290 { Bad_Opcode }, 7291 { Bad_Opcode }, 7292 /* 60 */ 7293 { PREFIX_TABLE (PREFIX_0F3A60) }, 7294 { PREFIX_TABLE (PREFIX_0F3A61) }, 7295 { PREFIX_TABLE (PREFIX_0F3A62) }, 7296 { PREFIX_TABLE (PREFIX_0F3A63) }, 7297 { Bad_Opcode }, 7298 { Bad_Opcode }, 7299 { Bad_Opcode }, 7300 { Bad_Opcode }, 7301 /* 68 */ 7302 { Bad_Opcode }, 7303 { Bad_Opcode }, 7304 { Bad_Opcode }, 7305 { Bad_Opcode }, 7306 { Bad_Opcode }, 7307 { Bad_Opcode }, 7308 { Bad_Opcode }, 7309 { Bad_Opcode }, 7310 /* 70 */ 7311 { Bad_Opcode }, 7312 { Bad_Opcode }, 7313 { Bad_Opcode }, 7314 { Bad_Opcode }, 7315 { Bad_Opcode }, 7316 { Bad_Opcode }, 7317 { Bad_Opcode }, 7318 { Bad_Opcode }, 7319 /* 78 */ 7320 { Bad_Opcode }, 7321 { Bad_Opcode }, 7322 { Bad_Opcode }, 7323 { Bad_Opcode }, 7324 { Bad_Opcode }, 7325 { Bad_Opcode }, 7326 { Bad_Opcode }, 7327 { Bad_Opcode }, 7328 /* 80 */ 7329 { Bad_Opcode }, 7330 { Bad_Opcode }, 7331 { Bad_Opcode }, 7332 { Bad_Opcode }, 7333 { Bad_Opcode }, 7334 { Bad_Opcode }, 7335 { Bad_Opcode }, 7336 { Bad_Opcode }, 7337 /* 88 */ 7338 { Bad_Opcode }, 7339 { Bad_Opcode }, 7340 { Bad_Opcode }, 7341 { Bad_Opcode }, 7342 { Bad_Opcode }, 7343 { Bad_Opcode }, 7344 { Bad_Opcode }, 7345 { Bad_Opcode }, 7346 /* 90 */ 7347 { Bad_Opcode }, 7348 { Bad_Opcode }, 7349 { Bad_Opcode }, 7350 { Bad_Opcode }, 7351 { Bad_Opcode }, 7352 { Bad_Opcode }, 7353 { Bad_Opcode }, 7354 { Bad_Opcode }, 7355 /* 98 */ 7356 { Bad_Opcode }, 7357 { Bad_Opcode }, 7358 { Bad_Opcode }, 7359 { Bad_Opcode }, 7360 { Bad_Opcode }, 7361 { Bad_Opcode }, 7362 { Bad_Opcode }, 7363 { Bad_Opcode }, 7364 /* a0 */ 7365 { Bad_Opcode }, 7366 { Bad_Opcode }, 7367 { Bad_Opcode }, 7368 { Bad_Opcode }, 7369 { Bad_Opcode }, 7370 { Bad_Opcode }, 7371 { Bad_Opcode }, 7372 { Bad_Opcode }, 7373 /* a8 */ 7374 { Bad_Opcode }, 7375 { Bad_Opcode }, 7376 { Bad_Opcode }, 7377 { Bad_Opcode }, 7378 { Bad_Opcode }, 7379 { Bad_Opcode }, 7380 { Bad_Opcode }, 7381 { Bad_Opcode }, 7382 /* b0 */ 7383 { Bad_Opcode }, 7384 { Bad_Opcode }, 7385 { Bad_Opcode }, 7386 { Bad_Opcode }, 7387 { Bad_Opcode }, 7388 { Bad_Opcode }, 7389 { Bad_Opcode }, 7390 { Bad_Opcode }, 7391 /* b8 */ 7392 { Bad_Opcode }, 7393 { Bad_Opcode }, 7394 { Bad_Opcode }, 7395 { Bad_Opcode }, 7396 { Bad_Opcode }, 7397 { Bad_Opcode }, 7398 { Bad_Opcode }, 7399 { Bad_Opcode }, 7400 /* c0 */ 7401 { Bad_Opcode }, 7402 { Bad_Opcode }, 7403 { Bad_Opcode }, 7404 { Bad_Opcode }, 7405 { Bad_Opcode }, 7406 { Bad_Opcode }, 7407 { Bad_Opcode }, 7408 { Bad_Opcode }, 7409 /* c8 */ 7410 { Bad_Opcode }, 7411 { Bad_Opcode }, 7412 { Bad_Opcode }, 7413 { Bad_Opcode }, 7414 { PREFIX_TABLE (PREFIX_0F3ACC) }, 7415 { Bad_Opcode }, 7416 { Bad_Opcode }, 7417 { Bad_Opcode }, 7418 /* d0 */ 7419 { Bad_Opcode }, 7420 { Bad_Opcode }, 7421 { Bad_Opcode }, 7422 { Bad_Opcode }, 7423 { Bad_Opcode }, 7424 { Bad_Opcode }, 7425 { Bad_Opcode }, 7426 { Bad_Opcode }, 7427 /* d8 */ 7428 { Bad_Opcode }, 7429 { Bad_Opcode }, 7430 { Bad_Opcode }, 7431 { Bad_Opcode }, 7432 { Bad_Opcode }, 7433 { Bad_Opcode }, 7434 { Bad_Opcode }, 7435 { PREFIX_TABLE (PREFIX_0F3ADF) }, 7436 /* e0 */ 7437 { Bad_Opcode }, 7438 { Bad_Opcode }, 7439 { Bad_Opcode }, 7440 { Bad_Opcode }, 7441 { Bad_Opcode }, 7442 { Bad_Opcode }, 7443 { Bad_Opcode }, 7444 { Bad_Opcode }, 7445 /* e8 */ 7446 { Bad_Opcode }, 7447 { Bad_Opcode }, 7448 { Bad_Opcode }, 7449 { Bad_Opcode }, 7450 { Bad_Opcode }, 7451 { Bad_Opcode }, 7452 { Bad_Opcode }, 7453 { Bad_Opcode }, 7454 /* f0 */ 7455 { Bad_Opcode }, 7456 { Bad_Opcode }, 7457 { Bad_Opcode }, 7458 { Bad_Opcode }, 7459 { Bad_Opcode }, 7460 { Bad_Opcode }, 7461 { Bad_Opcode }, 7462 { Bad_Opcode }, 7463 /* f8 */ 7464 { Bad_Opcode }, 7465 { Bad_Opcode }, 7466 { Bad_Opcode }, 7467 { Bad_Opcode }, 7468 { Bad_Opcode }, 7469 { Bad_Opcode }, 7470 { Bad_Opcode }, 7471 { Bad_Opcode }, 7472 }, 7473 7474 /* THREE_BYTE_0F7A */ 7475 { 7476 /* 00 */ 7477 { Bad_Opcode }, 7478 { Bad_Opcode }, 7479 { Bad_Opcode }, 7480 { Bad_Opcode }, 7481 { Bad_Opcode }, 7482 { Bad_Opcode }, 7483 { Bad_Opcode }, 7484 { Bad_Opcode }, 7485 /* 08 */ 7486 { Bad_Opcode }, 7487 { Bad_Opcode }, 7488 { Bad_Opcode }, 7489 { Bad_Opcode }, 7490 { Bad_Opcode }, 7491 { Bad_Opcode }, 7492 { Bad_Opcode }, 7493 { Bad_Opcode }, 7494 /* 10 */ 7495 { Bad_Opcode }, 7496 { Bad_Opcode }, 7497 { Bad_Opcode }, 7498 { Bad_Opcode }, 7499 { Bad_Opcode }, 7500 { Bad_Opcode }, 7501 { Bad_Opcode }, 7502 { Bad_Opcode }, 7503 /* 18 */ 7504 { Bad_Opcode }, 7505 { Bad_Opcode }, 7506 { Bad_Opcode }, 7507 { Bad_Opcode }, 7508 { Bad_Opcode }, 7509 { Bad_Opcode }, 7510 { Bad_Opcode }, 7511 { Bad_Opcode }, 7512 /* 20 */ 7513 { "ptest", { XX }, PREFIX_OPCODE }, 7514 { Bad_Opcode }, 7515 { Bad_Opcode }, 7516 { Bad_Opcode }, 7517 { Bad_Opcode }, 7518 { Bad_Opcode }, 7519 { Bad_Opcode }, 7520 { Bad_Opcode }, 7521 /* 28 */ 7522 { Bad_Opcode }, 7523 { Bad_Opcode }, 7524 { Bad_Opcode }, 7525 { Bad_Opcode }, 7526 { Bad_Opcode }, 7527 { Bad_Opcode }, 7528 { Bad_Opcode }, 7529 { Bad_Opcode }, 7530 /* 30 */ 7531 { Bad_Opcode }, 7532 { Bad_Opcode }, 7533 { Bad_Opcode }, 7534 { Bad_Opcode }, 7535 { Bad_Opcode }, 7536 { Bad_Opcode }, 7537 { Bad_Opcode }, 7538 { Bad_Opcode }, 7539 /* 38 */ 7540 { Bad_Opcode }, 7541 { Bad_Opcode }, 7542 { Bad_Opcode }, 7543 { Bad_Opcode }, 7544 { Bad_Opcode }, 7545 { Bad_Opcode }, 7546 { Bad_Opcode }, 7547 { Bad_Opcode }, 7548 /* 40 */ 7549 { Bad_Opcode }, 7550 { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, 7551 { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, 7552 { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, 7553 { Bad_Opcode }, 7554 { Bad_Opcode }, 7555 { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, 7556 { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, 7557 /* 48 */ 7558 { Bad_Opcode }, 7559 { Bad_Opcode }, 7560 { Bad_Opcode }, 7561 { "phadddq", { XM, EXq }, PREFIX_OPCODE }, 7562 { Bad_Opcode }, 7563 { Bad_Opcode }, 7564 { Bad_Opcode }, 7565 { Bad_Opcode }, 7566 /* 50 */ 7567 { Bad_Opcode }, 7568 { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, 7569 { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, 7570 { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, 7571 { Bad_Opcode }, 7572 { Bad_Opcode }, 7573 { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, 7574 { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, 7575 /* 58 */ 7576 { Bad_Opcode }, 7577 { Bad_Opcode }, 7578 { Bad_Opcode }, 7579 { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, 7580 { Bad_Opcode }, 7581 { Bad_Opcode }, 7582 { Bad_Opcode }, 7583 { Bad_Opcode }, 7584 /* 60 */ 7585 { Bad_Opcode }, 7586 { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, 7587 { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, 7588 { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, 7589 { Bad_Opcode }, 7590 { Bad_Opcode }, 7591 { Bad_Opcode }, 7592 { Bad_Opcode }, 7593 /* 68 */ 7594 { Bad_Opcode }, 7595 { Bad_Opcode }, 7596 { Bad_Opcode }, 7597 { Bad_Opcode }, 7598 { Bad_Opcode }, 7599 { Bad_Opcode }, 7600 { Bad_Opcode }, 7601 { Bad_Opcode }, 7602 /* 70 */ 7603 { Bad_Opcode }, 7604 { Bad_Opcode }, 7605 { Bad_Opcode }, 7606 { Bad_Opcode }, 7607 { Bad_Opcode }, 7608 { Bad_Opcode }, 7609 { Bad_Opcode }, 7610 { Bad_Opcode }, 7611 /* 78 */ 7612 { Bad_Opcode }, 7613 { Bad_Opcode }, 7614 { Bad_Opcode }, 7615 { Bad_Opcode }, 7616 { Bad_Opcode }, 7617 { Bad_Opcode }, 7618 { Bad_Opcode }, 7619 { Bad_Opcode }, 7620 /* 80 */ 7621 { Bad_Opcode }, 7622 { Bad_Opcode }, 7623 { Bad_Opcode }, 7624 { Bad_Opcode }, 7625 { Bad_Opcode }, 7626 { Bad_Opcode }, 7627 { Bad_Opcode }, 7628 { Bad_Opcode }, 7629 /* 88 */ 7630 { Bad_Opcode }, 7631 { Bad_Opcode }, 7632 { Bad_Opcode }, 7633 { Bad_Opcode }, 7634 { Bad_Opcode }, 7635 { Bad_Opcode }, 7636 { Bad_Opcode }, 7637 { Bad_Opcode }, 7638 /* 90 */ 7639 { Bad_Opcode }, 7640 { Bad_Opcode }, 7641 { Bad_Opcode }, 7642 { Bad_Opcode }, 7643 { Bad_Opcode }, 7644 { Bad_Opcode }, 7645 { Bad_Opcode }, 7646 { Bad_Opcode }, 7647 /* 98 */ 7648 { Bad_Opcode }, 7649 { Bad_Opcode }, 7650 { Bad_Opcode }, 7651 { Bad_Opcode }, 7652 { Bad_Opcode }, 7653 { Bad_Opcode }, 7654 { Bad_Opcode }, 7655 { Bad_Opcode }, 7656 /* a0 */ 7657 { Bad_Opcode }, 7658 { Bad_Opcode }, 7659 { Bad_Opcode }, 7660 { Bad_Opcode }, 7661 { Bad_Opcode }, 7662 { Bad_Opcode }, 7663 { Bad_Opcode }, 7664 { Bad_Opcode }, 7665 /* a8 */ 7666 { Bad_Opcode }, 7667 { Bad_Opcode }, 7668 { Bad_Opcode }, 7669 { Bad_Opcode }, 7670 { Bad_Opcode }, 7671 { Bad_Opcode }, 7672 { Bad_Opcode }, 7673 { Bad_Opcode }, 7674 /* b0 */ 7675 { Bad_Opcode }, 7676 { Bad_Opcode }, 7677 { Bad_Opcode }, 7678 { Bad_Opcode }, 7679 { Bad_Opcode }, 7680 { Bad_Opcode }, 7681 { Bad_Opcode }, 7682 { Bad_Opcode }, 7683 /* b8 */ 7684 { Bad_Opcode }, 7685 { Bad_Opcode }, 7686 { Bad_Opcode }, 7687 { Bad_Opcode }, 7688 { Bad_Opcode }, 7689 { Bad_Opcode }, 7690 { Bad_Opcode }, 7691 { Bad_Opcode }, 7692 /* c0 */ 7693 { Bad_Opcode }, 7694 { Bad_Opcode }, 7695 { Bad_Opcode }, 7696 { Bad_Opcode }, 7697 { Bad_Opcode }, 7698 { Bad_Opcode }, 7699 { Bad_Opcode }, 7700 { Bad_Opcode }, 7701 /* c8 */ 7702 { Bad_Opcode }, 7703 { Bad_Opcode }, 7704 { Bad_Opcode }, 7705 { Bad_Opcode }, 7706 { Bad_Opcode }, 7707 { Bad_Opcode }, 7708 { Bad_Opcode }, 7709 { Bad_Opcode }, 7710 /* d0 */ 7711 { Bad_Opcode }, 7712 { Bad_Opcode }, 7713 { Bad_Opcode }, 7714 { Bad_Opcode }, 7715 { Bad_Opcode }, 7716 { Bad_Opcode }, 7717 { Bad_Opcode }, 7718 { Bad_Opcode }, 7719 /* d8 */ 7720 { Bad_Opcode }, 7721 { Bad_Opcode }, 7722 { Bad_Opcode }, 7723 { Bad_Opcode }, 7724 { Bad_Opcode }, 7725 { Bad_Opcode }, 7726 { Bad_Opcode }, 7727 { Bad_Opcode }, 7728 /* e0 */ 7729 { Bad_Opcode }, 7730 { Bad_Opcode }, 7731 { Bad_Opcode }, 7732 { Bad_Opcode }, 7733 { Bad_Opcode }, 7734 { Bad_Opcode }, 7735 { Bad_Opcode }, 7736 { Bad_Opcode }, 7737 /* e8 */ 7738 { Bad_Opcode }, 7739 { Bad_Opcode }, 7740 { Bad_Opcode }, 7741 { Bad_Opcode }, 7742 { Bad_Opcode }, 7743 { Bad_Opcode }, 7744 { Bad_Opcode }, 7745 { Bad_Opcode }, 7746 /* f0 */ 7747 { Bad_Opcode }, 7748 { Bad_Opcode }, 7749 { Bad_Opcode }, 7750 { Bad_Opcode }, 7751 { Bad_Opcode }, 7752 { Bad_Opcode }, 7753 { Bad_Opcode }, 7754 { Bad_Opcode }, 7755 /* f8 */ 7756 { Bad_Opcode }, 7757 { Bad_Opcode }, 7758 { Bad_Opcode }, 7759 { Bad_Opcode }, 7760 { Bad_Opcode }, 7761 { Bad_Opcode }, 7762 { Bad_Opcode }, 7763 { Bad_Opcode }, 7764 }, 7765 }; 7766 7767 static const struct dis386 xop_table[][256] = { 7768 /* XOP_08 */ 7769 { 7770 /* 00 */ 7771 { Bad_Opcode }, 7772 { Bad_Opcode }, 7773 { Bad_Opcode }, 7774 { Bad_Opcode }, 7775 { Bad_Opcode }, 7776 { Bad_Opcode }, 7777 { Bad_Opcode }, 7778 { Bad_Opcode }, 7779 /* 08 */ 7780 { Bad_Opcode }, 7781 { Bad_Opcode }, 7782 { Bad_Opcode }, 7783 { Bad_Opcode }, 7784 { Bad_Opcode }, 7785 { Bad_Opcode }, 7786 { Bad_Opcode }, 7787 { Bad_Opcode }, 7788 /* 10 */ 7789 { Bad_Opcode }, 7790 { Bad_Opcode }, 7791 { Bad_Opcode }, 7792 { Bad_Opcode }, 7793 { Bad_Opcode }, 7794 { Bad_Opcode }, 7795 { Bad_Opcode }, 7796 { Bad_Opcode }, 7797 /* 18 */ 7798 { Bad_Opcode }, 7799 { Bad_Opcode }, 7800 { Bad_Opcode }, 7801 { Bad_Opcode }, 7802 { Bad_Opcode }, 7803 { Bad_Opcode }, 7804 { Bad_Opcode }, 7805 { Bad_Opcode }, 7806 /* 20 */ 7807 { Bad_Opcode }, 7808 { Bad_Opcode }, 7809 { Bad_Opcode }, 7810 { Bad_Opcode }, 7811 { Bad_Opcode }, 7812 { Bad_Opcode }, 7813 { Bad_Opcode }, 7814 { Bad_Opcode }, 7815 /* 28 */ 7816 { Bad_Opcode }, 7817 { Bad_Opcode }, 7818 { Bad_Opcode }, 7819 { Bad_Opcode }, 7820 { Bad_Opcode }, 7821 { Bad_Opcode }, 7822 { Bad_Opcode }, 7823 { Bad_Opcode }, 7824 /* 30 */ 7825 { Bad_Opcode }, 7826 { Bad_Opcode }, 7827 { Bad_Opcode }, 7828 { Bad_Opcode }, 7829 { Bad_Opcode }, 7830 { Bad_Opcode }, 7831 { Bad_Opcode }, 7832 { Bad_Opcode }, 7833 /* 38 */ 7834 { Bad_Opcode }, 7835 { Bad_Opcode }, 7836 { Bad_Opcode }, 7837 { Bad_Opcode }, 7838 { Bad_Opcode }, 7839 { Bad_Opcode }, 7840 { Bad_Opcode }, 7841 { Bad_Opcode }, 7842 /* 40 */ 7843 { Bad_Opcode }, 7844 { Bad_Opcode }, 7845 { Bad_Opcode }, 7846 { Bad_Opcode }, 7847 { Bad_Opcode }, 7848 { Bad_Opcode }, 7849 { Bad_Opcode }, 7850 { Bad_Opcode }, 7851 /* 48 */ 7852 { Bad_Opcode }, 7853 { Bad_Opcode }, 7854 { Bad_Opcode }, 7855 { Bad_Opcode }, 7856 { Bad_Opcode }, 7857 { Bad_Opcode }, 7858 { Bad_Opcode }, 7859 { Bad_Opcode }, 7860 /* 50 */ 7861 { Bad_Opcode }, 7862 { Bad_Opcode }, 7863 { Bad_Opcode }, 7864 { Bad_Opcode }, 7865 { Bad_Opcode }, 7866 { Bad_Opcode }, 7867 { Bad_Opcode }, 7868 { Bad_Opcode }, 7869 /* 58 */ 7870 { Bad_Opcode }, 7871 { Bad_Opcode }, 7872 { Bad_Opcode }, 7873 { Bad_Opcode }, 7874 { Bad_Opcode }, 7875 { Bad_Opcode }, 7876 { Bad_Opcode }, 7877 { Bad_Opcode }, 7878 /* 60 */ 7879 { Bad_Opcode }, 7880 { Bad_Opcode }, 7881 { Bad_Opcode }, 7882 { Bad_Opcode }, 7883 { Bad_Opcode }, 7884 { Bad_Opcode }, 7885 { Bad_Opcode }, 7886 { Bad_Opcode }, 7887 /* 68 */ 7888 { Bad_Opcode }, 7889 { Bad_Opcode }, 7890 { Bad_Opcode }, 7891 { Bad_Opcode }, 7892 { Bad_Opcode }, 7893 { Bad_Opcode }, 7894 { Bad_Opcode }, 7895 { Bad_Opcode }, 7896 /* 70 */ 7897 { Bad_Opcode }, 7898 { Bad_Opcode }, 7899 { Bad_Opcode }, 7900 { Bad_Opcode }, 7901 { Bad_Opcode }, 7902 { Bad_Opcode }, 7903 { Bad_Opcode }, 7904 { Bad_Opcode }, 7905 /* 78 */ 7906 { Bad_Opcode }, 7907 { Bad_Opcode }, 7908 { Bad_Opcode }, 7909 { Bad_Opcode }, 7910 { Bad_Opcode }, 7911 { Bad_Opcode }, 7912 { Bad_Opcode }, 7913 { Bad_Opcode }, 7914 /* 80 */ 7915 { Bad_Opcode }, 7916 { Bad_Opcode }, 7917 { Bad_Opcode }, 7918 { Bad_Opcode }, 7919 { Bad_Opcode }, 7920 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7921 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7922 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7923 /* 88 */ 7924 { Bad_Opcode }, 7925 { Bad_Opcode }, 7926 { Bad_Opcode }, 7927 { Bad_Opcode }, 7928 { Bad_Opcode }, 7929 { Bad_Opcode }, 7930 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7931 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7932 /* 90 */ 7933 { Bad_Opcode }, 7934 { Bad_Opcode }, 7935 { Bad_Opcode }, 7936 { Bad_Opcode }, 7937 { Bad_Opcode }, 7938 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7939 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7940 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7941 /* 98 */ 7942 { Bad_Opcode }, 7943 { Bad_Opcode }, 7944 { Bad_Opcode }, 7945 { Bad_Opcode }, 7946 { Bad_Opcode }, 7947 { Bad_Opcode }, 7948 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7949 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7950 /* a0 */ 7951 { Bad_Opcode }, 7952 { Bad_Opcode }, 7953 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7954 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7955 { Bad_Opcode }, 7956 { Bad_Opcode }, 7957 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7958 { Bad_Opcode }, 7959 /* a8 */ 7960 { Bad_Opcode }, 7961 { Bad_Opcode }, 7962 { Bad_Opcode }, 7963 { Bad_Opcode }, 7964 { Bad_Opcode }, 7965 { Bad_Opcode }, 7966 { Bad_Opcode }, 7967 { Bad_Opcode }, 7968 /* b0 */ 7969 { Bad_Opcode }, 7970 { Bad_Opcode }, 7971 { Bad_Opcode }, 7972 { Bad_Opcode }, 7973 { Bad_Opcode }, 7974 { Bad_Opcode }, 7975 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, 7976 { Bad_Opcode }, 7977 /* b8 */ 7978 { Bad_Opcode }, 7979 { Bad_Opcode }, 7980 { Bad_Opcode }, 7981 { Bad_Opcode }, 7982 { Bad_Opcode }, 7983 { Bad_Opcode }, 7984 { Bad_Opcode }, 7985 { Bad_Opcode }, 7986 /* c0 */ 7987 { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, 7988 { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, 7989 { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, 7990 { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, 7991 { Bad_Opcode }, 7992 { Bad_Opcode }, 7993 { Bad_Opcode }, 7994 { Bad_Opcode }, 7995 /* c8 */ 7996 { Bad_Opcode }, 7997 { Bad_Opcode }, 7998 { Bad_Opcode }, 7999 { Bad_Opcode }, 8000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, 8001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, 8002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, 8003 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, 8004 /* d0 */ 8005 { Bad_Opcode }, 8006 { Bad_Opcode }, 8007 { Bad_Opcode }, 8008 { Bad_Opcode }, 8009 { Bad_Opcode }, 8010 { Bad_Opcode }, 8011 { Bad_Opcode }, 8012 { Bad_Opcode }, 8013 /* d8 */ 8014 { Bad_Opcode }, 8015 { Bad_Opcode }, 8016 { Bad_Opcode }, 8017 { Bad_Opcode }, 8018 { Bad_Opcode }, 8019 { Bad_Opcode }, 8020 { Bad_Opcode }, 8021 { Bad_Opcode }, 8022 /* e0 */ 8023 { Bad_Opcode }, 8024 { Bad_Opcode }, 8025 { Bad_Opcode }, 8026 { Bad_Opcode }, 8027 { Bad_Opcode }, 8028 { Bad_Opcode }, 8029 { Bad_Opcode }, 8030 { Bad_Opcode }, 8031 /* e8 */ 8032 { Bad_Opcode }, 8033 { Bad_Opcode }, 8034 { Bad_Opcode }, 8035 { Bad_Opcode }, 8036 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, 8037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, 8038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, 8039 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, 8040 /* f0 */ 8041 { Bad_Opcode }, 8042 { Bad_Opcode }, 8043 { Bad_Opcode }, 8044 { Bad_Opcode }, 8045 { Bad_Opcode }, 8046 { Bad_Opcode }, 8047 { Bad_Opcode }, 8048 { Bad_Opcode }, 8049 /* f8 */ 8050 { Bad_Opcode }, 8051 { Bad_Opcode }, 8052 { Bad_Opcode }, 8053 { Bad_Opcode }, 8054 { Bad_Opcode }, 8055 { Bad_Opcode }, 8056 { Bad_Opcode }, 8057 { Bad_Opcode }, 8058 }, 8059 /* XOP_09 */ 8060 { 8061 /* 00 */ 8062 { Bad_Opcode }, 8063 { REG_TABLE (REG_XOP_TBM_01) }, 8064 { REG_TABLE (REG_XOP_TBM_02) }, 8065 { Bad_Opcode }, 8066 { Bad_Opcode }, 8067 { Bad_Opcode }, 8068 { Bad_Opcode }, 8069 { Bad_Opcode }, 8070 /* 08 */ 8071 { Bad_Opcode }, 8072 { Bad_Opcode }, 8073 { Bad_Opcode }, 8074 { Bad_Opcode }, 8075 { Bad_Opcode }, 8076 { Bad_Opcode }, 8077 { Bad_Opcode }, 8078 { Bad_Opcode }, 8079 /* 10 */ 8080 { Bad_Opcode }, 8081 { Bad_Opcode }, 8082 { REG_TABLE (REG_XOP_LWPCB) }, 8083 { Bad_Opcode }, 8084 { Bad_Opcode }, 8085 { Bad_Opcode }, 8086 { Bad_Opcode }, 8087 { Bad_Opcode }, 8088 /* 18 */ 8089 { Bad_Opcode }, 8090 { Bad_Opcode }, 8091 { Bad_Opcode }, 8092 { Bad_Opcode }, 8093 { Bad_Opcode }, 8094 { Bad_Opcode }, 8095 { Bad_Opcode }, 8096 { Bad_Opcode }, 8097 /* 20 */ 8098 { Bad_Opcode }, 8099 { Bad_Opcode }, 8100 { Bad_Opcode }, 8101 { Bad_Opcode }, 8102 { Bad_Opcode }, 8103 { Bad_Opcode }, 8104 { Bad_Opcode }, 8105 { Bad_Opcode }, 8106 /* 28 */ 8107 { Bad_Opcode }, 8108 { Bad_Opcode }, 8109 { Bad_Opcode }, 8110 { Bad_Opcode }, 8111 { Bad_Opcode }, 8112 { Bad_Opcode }, 8113 { Bad_Opcode }, 8114 { Bad_Opcode }, 8115 /* 30 */ 8116 { Bad_Opcode }, 8117 { Bad_Opcode }, 8118 { Bad_Opcode }, 8119 { Bad_Opcode }, 8120 { Bad_Opcode }, 8121 { Bad_Opcode }, 8122 { Bad_Opcode }, 8123 { Bad_Opcode }, 8124 /* 38 */ 8125 { Bad_Opcode }, 8126 { Bad_Opcode }, 8127 { Bad_Opcode }, 8128 { Bad_Opcode }, 8129 { Bad_Opcode }, 8130 { Bad_Opcode }, 8131 { Bad_Opcode }, 8132 { Bad_Opcode }, 8133 /* 40 */ 8134 { Bad_Opcode }, 8135 { Bad_Opcode }, 8136 { Bad_Opcode }, 8137 { Bad_Opcode }, 8138 { Bad_Opcode }, 8139 { Bad_Opcode }, 8140 { Bad_Opcode }, 8141 { Bad_Opcode }, 8142 /* 48 */ 8143 { Bad_Opcode }, 8144 { Bad_Opcode }, 8145 { Bad_Opcode }, 8146 { Bad_Opcode }, 8147 { Bad_Opcode }, 8148 { Bad_Opcode }, 8149 { Bad_Opcode }, 8150 { Bad_Opcode }, 8151 /* 50 */ 8152 { Bad_Opcode }, 8153 { Bad_Opcode }, 8154 { Bad_Opcode }, 8155 { Bad_Opcode }, 8156 { Bad_Opcode }, 8157 { Bad_Opcode }, 8158 { Bad_Opcode }, 8159 { Bad_Opcode }, 8160 /* 58 */ 8161 { Bad_Opcode }, 8162 { Bad_Opcode }, 8163 { Bad_Opcode }, 8164 { Bad_Opcode }, 8165 { Bad_Opcode }, 8166 { Bad_Opcode }, 8167 { Bad_Opcode }, 8168 { Bad_Opcode }, 8169 /* 60 */ 8170 { Bad_Opcode }, 8171 { Bad_Opcode }, 8172 { Bad_Opcode }, 8173 { Bad_Opcode }, 8174 { Bad_Opcode }, 8175 { Bad_Opcode }, 8176 { Bad_Opcode }, 8177 { Bad_Opcode }, 8178 /* 68 */ 8179 { Bad_Opcode }, 8180 { Bad_Opcode }, 8181 { Bad_Opcode }, 8182 { Bad_Opcode }, 8183 { Bad_Opcode }, 8184 { Bad_Opcode }, 8185 { Bad_Opcode }, 8186 { Bad_Opcode }, 8187 /* 70 */ 8188 { Bad_Opcode }, 8189 { Bad_Opcode }, 8190 { Bad_Opcode }, 8191 { Bad_Opcode }, 8192 { Bad_Opcode }, 8193 { Bad_Opcode }, 8194 { Bad_Opcode }, 8195 { Bad_Opcode }, 8196 /* 78 */ 8197 { Bad_Opcode }, 8198 { Bad_Opcode }, 8199 { Bad_Opcode }, 8200 { Bad_Opcode }, 8201 { Bad_Opcode }, 8202 { Bad_Opcode }, 8203 { Bad_Opcode }, 8204 { Bad_Opcode }, 8205 /* 80 */ 8206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, 8207 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, 8208 { "vfrczss", { XM, EXd }, 0 }, 8209 { "vfrczsd", { XM, EXq }, 0 }, 8210 { Bad_Opcode }, 8211 { Bad_Opcode }, 8212 { Bad_Opcode }, 8213 { Bad_Opcode }, 8214 /* 88 */ 8215 { Bad_Opcode }, 8216 { Bad_Opcode }, 8217 { Bad_Opcode }, 8218 { Bad_Opcode }, 8219 { Bad_Opcode }, 8220 { Bad_Opcode }, 8221 { Bad_Opcode }, 8222 { Bad_Opcode }, 8223 /* 90 */ 8224 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8225 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8226 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8227 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8228 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8229 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8230 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8231 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8232 /* 98 */ 8233 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8234 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8235 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8236 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, 8237 { Bad_Opcode }, 8238 { Bad_Opcode }, 8239 { Bad_Opcode }, 8240 { Bad_Opcode }, 8241 /* a0 */ 8242 { Bad_Opcode }, 8243 { Bad_Opcode }, 8244 { Bad_Opcode }, 8245 { Bad_Opcode }, 8246 { Bad_Opcode }, 8247 { Bad_Opcode }, 8248 { Bad_Opcode }, 8249 { Bad_Opcode }, 8250 /* a8 */ 8251 { Bad_Opcode }, 8252 { Bad_Opcode }, 8253 { Bad_Opcode }, 8254 { Bad_Opcode }, 8255 { Bad_Opcode }, 8256 { Bad_Opcode }, 8257 { Bad_Opcode }, 8258 { Bad_Opcode }, 8259 /* b0 */ 8260 { Bad_Opcode }, 8261 { Bad_Opcode }, 8262 { Bad_Opcode }, 8263 { Bad_Opcode }, 8264 { Bad_Opcode }, 8265 { Bad_Opcode }, 8266 { Bad_Opcode }, 8267 { Bad_Opcode }, 8268 /* b8 */ 8269 { Bad_Opcode }, 8270 { Bad_Opcode }, 8271 { Bad_Opcode }, 8272 { Bad_Opcode }, 8273 { Bad_Opcode }, 8274 { Bad_Opcode }, 8275 { Bad_Opcode }, 8276 { Bad_Opcode }, 8277 /* c0 */ 8278 { Bad_Opcode }, 8279 { "vphaddbw", { XM, EXxmm }, 0 }, 8280 { "vphaddbd", { XM, EXxmm }, 0 }, 8281 { "vphaddbq", { XM, EXxmm }, 0 }, 8282 { Bad_Opcode }, 8283 { Bad_Opcode }, 8284 { "vphaddwd", { XM, EXxmm }, 0 }, 8285 { "vphaddwq", { XM, EXxmm }, 0 }, 8286 /* c8 */ 8287 { Bad_Opcode }, 8288 { Bad_Opcode }, 8289 { Bad_Opcode }, 8290 { "vphadddq", { XM, EXxmm }, 0 }, 8291 { Bad_Opcode }, 8292 { Bad_Opcode }, 8293 { Bad_Opcode }, 8294 { Bad_Opcode }, 8295 /* d0 */ 8296 { Bad_Opcode }, 8297 { "vphaddubw", { XM, EXxmm }, 0 }, 8298 { "vphaddubd", { XM, EXxmm }, 0 }, 8299 { "vphaddubq", { XM, EXxmm }, 0 }, 8300 { Bad_Opcode }, 8301 { Bad_Opcode }, 8302 { "vphadduwd", { XM, EXxmm }, 0 }, 8303 { "vphadduwq", { XM, EXxmm }, 0 }, 8304 /* d8 */ 8305 { Bad_Opcode }, 8306 { Bad_Opcode }, 8307 { Bad_Opcode }, 8308 { "vphaddudq", { XM, EXxmm }, 0 }, 8309 { Bad_Opcode }, 8310 { Bad_Opcode }, 8311 { Bad_Opcode }, 8312 { Bad_Opcode }, 8313 /* e0 */ 8314 { Bad_Opcode }, 8315 { "vphsubbw", { XM, EXxmm }, 0 }, 8316 { "vphsubwd", { XM, EXxmm }, 0 }, 8317 { "vphsubdq", { XM, EXxmm }, 0 }, 8318 { Bad_Opcode }, 8319 { Bad_Opcode }, 8320 { Bad_Opcode }, 8321 { Bad_Opcode }, 8322 /* e8 */ 8323 { Bad_Opcode }, 8324 { Bad_Opcode }, 8325 { Bad_Opcode }, 8326 { Bad_Opcode }, 8327 { Bad_Opcode }, 8328 { Bad_Opcode }, 8329 { Bad_Opcode }, 8330 { Bad_Opcode }, 8331 /* f0 */ 8332 { Bad_Opcode }, 8333 { Bad_Opcode }, 8334 { Bad_Opcode }, 8335 { Bad_Opcode }, 8336 { Bad_Opcode }, 8337 { Bad_Opcode }, 8338 { Bad_Opcode }, 8339 { Bad_Opcode }, 8340 /* f8 */ 8341 { Bad_Opcode }, 8342 { Bad_Opcode }, 8343 { Bad_Opcode }, 8344 { Bad_Opcode }, 8345 { Bad_Opcode }, 8346 { Bad_Opcode }, 8347 { Bad_Opcode }, 8348 { Bad_Opcode }, 8349 }, 8350 /* XOP_0A */ 8351 { 8352 /* 00 */ 8353 { Bad_Opcode }, 8354 { Bad_Opcode }, 8355 { Bad_Opcode }, 8356 { Bad_Opcode }, 8357 { Bad_Opcode }, 8358 { Bad_Opcode }, 8359 { Bad_Opcode }, 8360 { Bad_Opcode }, 8361 /* 08 */ 8362 { Bad_Opcode }, 8363 { Bad_Opcode }, 8364 { Bad_Opcode }, 8365 { Bad_Opcode }, 8366 { Bad_Opcode }, 8367 { Bad_Opcode }, 8368 { Bad_Opcode }, 8369 { Bad_Opcode }, 8370 /* 10 */ 8371 { "bextr", { Gv, Ev, Iq }, 0 }, 8372 { Bad_Opcode }, 8373 { REG_TABLE (REG_XOP_LWP) }, 8374 { Bad_Opcode }, 8375 { Bad_Opcode }, 8376 { Bad_Opcode }, 8377 { Bad_Opcode }, 8378 { Bad_Opcode }, 8379 /* 18 */ 8380 { Bad_Opcode }, 8381 { Bad_Opcode }, 8382 { Bad_Opcode }, 8383 { Bad_Opcode }, 8384 { Bad_Opcode }, 8385 { Bad_Opcode }, 8386 { Bad_Opcode }, 8387 { Bad_Opcode }, 8388 /* 20 */ 8389 { Bad_Opcode }, 8390 { Bad_Opcode }, 8391 { Bad_Opcode }, 8392 { Bad_Opcode }, 8393 { Bad_Opcode }, 8394 { Bad_Opcode }, 8395 { Bad_Opcode }, 8396 { Bad_Opcode }, 8397 /* 28 */ 8398 { Bad_Opcode }, 8399 { Bad_Opcode }, 8400 { Bad_Opcode }, 8401 { Bad_Opcode }, 8402 { Bad_Opcode }, 8403 { Bad_Opcode }, 8404 { Bad_Opcode }, 8405 { Bad_Opcode }, 8406 /* 30 */ 8407 { Bad_Opcode }, 8408 { Bad_Opcode }, 8409 { Bad_Opcode }, 8410 { Bad_Opcode }, 8411 { Bad_Opcode }, 8412 { Bad_Opcode }, 8413 { Bad_Opcode }, 8414 { Bad_Opcode }, 8415 /* 38 */ 8416 { Bad_Opcode }, 8417 { Bad_Opcode }, 8418 { Bad_Opcode }, 8419 { Bad_Opcode }, 8420 { Bad_Opcode }, 8421 { Bad_Opcode }, 8422 { Bad_Opcode }, 8423 { Bad_Opcode }, 8424 /* 40 */ 8425 { Bad_Opcode }, 8426 { Bad_Opcode }, 8427 { Bad_Opcode }, 8428 { Bad_Opcode }, 8429 { Bad_Opcode }, 8430 { Bad_Opcode }, 8431 { Bad_Opcode }, 8432 { Bad_Opcode }, 8433 /* 48 */ 8434 { Bad_Opcode }, 8435 { Bad_Opcode }, 8436 { Bad_Opcode }, 8437 { Bad_Opcode }, 8438 { Bad_Opcode }, 8439 { Bad_Opcode }, 8440 { Bad_Opcode }, 8441 { Bad_Opcode }, 8442 /* 50 */ 8443 { Bad_Opcode }, 8444 { Bad_Opcode }, 8445 { Bad_Opcode }, 8446 { Bad_Opcode }, 8447 { Bad_Opcode }, 8448 { Bad_Opcode }, 8449 { Bad_Opcode }, 8450 { Bad_Opcode }, 8451 /* 58 */ 8452 { Bad_Opcode }, 8453 { Bad_Opcode }, 8454 { Bad_Opcode }, 8455 { Bad_Opcode }, 8456 { Bad_Opcode }, 8457 { Bad_Opcode }, 8458 { Bad_Opcode }, 8459 { Bad_Opcode }, 8460 /* 60 */ 8461 { Bad_Opcode }, 8462 { Bad_Opcode }, 8463 { Bad_Opcode }, 8464 { Bad_Opcode }, 8465 { Bad_Opcode }, 8466 { Bad_Opcode }, 8467 { Bad_Opcode }, 8468 { Bad_Opcode }, 8469 /* 68 */ 8470 { Bad_Opcode }, 8471 { Bad_Opcode }, 8472 { Bad_Opcode }, 8473 { Bad_Opcode }, 8474 { Bad_Opcode }, 8475 { Bad_Opcode }, 8476 { Bad_Opcode }, 8477 { Bad_Opcode }, 8478 /* 70 */ 8479 { Bad_Opcode }, 8480 { Bad_Opcode }, 8481 { Bad_Opcode }, 8482 { Bad_Opcode }, 8483 { Bad_Opcode }, 8484 { Bad_Opcode }, 8485 { Bad_Opcode }, 8486 { Bad_Opcode }, 8487 /* 78 */ 8488 { Bad_Opcode }, 8489 { Bad_Opcode }, 8490 { Bad_Opcode }, 8491 { Bad_Opcode }, 8492 { Bad_Opcode }, 8493 { Bad_Opcode }, 8494 { Bad_Opcode }, 8495 { Bad_Opcode }, 8496 /* 80 */ 8497 { Bad_Opcode }, 8498 { Bad_Opcode }, 8499 { Bad_Opcode }, 8500 { Bad_Opcode }, 8501 { Bad_Opcode }, 8502 { Bad_Opcode }, 8503 { Bad_Opcode }, 8504 { Bad_Opcode }, 8505 /* 88 */ 8506 { Bad_Opcode }, 8507 { Bad_Opcode }, 8508 { Bad_Opcode }, 8509 { Bad_Opcode }, 8510 { Bad_Opcode }, 8511 { Bad_Opcode }, 8512 { Bad_Opcode }, 8513 { Bad_Opcode }, 8514 /* 90 */ 8515 { Bad_Opcode }, 8516 { Bad_Opcode }, 8517 { Bad_Opcode }, 8518 { Bad_Opcode }, 8519 { Bad_Opcode }, 8520 { Bad_Opcode }, 8521 { Bad_Opcode }, 8522 { Bad_Opcode }, 8523 /* 98 */ 8524 { Bad_Opcode }, 8525 { Bad_Opcode }, 8526 { Bad_Opcode }, 8527 { Bad_Opcode }, 8528 { Bad_Opcode }, 8529 { Bad_Opcode }, 8530 { Bad_Opcode }, 8531 { Bad_Opcode }, 8532 /* a0 */ 8533 { Bad_Opcode }, 8534 { Bad_Opcode }, 8535 { Bad_Opcode }, 8536 { Bad_Opcode }, 8537 { Bad_Opcode }, 8538 { Bad_Opcode }, 8539 { Bad_Opcode }, 8540 { Bad_Opcode }, 8541 /* a8 */ 8542 { Bad_Opcode }, 8543 { Bad_Opcode }, 8544 { Bad_Opcode }, 8545 { Bad_Opcode }, 8546 { Bad_Opcode }, 8547 { Bad_Opcode }, 8548 { Bad_Opcode }, 8549 { Bad_Opcode }, 8550 /* b0 */ 8551 { Bad_Opcode }, 8552 { Bad_Opcode }, 8553 { Bad_Opcode }, 8554 { Bad_Opcode }, 8555 { Bad_Opcode }, 8556 { Bad_Opcode }, 8557 { Bad_Opcode }, 8558 { Bad_Opcode }, 8559 /* b8 */ 8560 { Bad_Opcode }, 8561 { Bad_Opcode }, 8562 { Bad_Opcode }, 8563 { Bad_Opcode }, 8564 { Bad_Opcode }, 8565 { Bad_Opcode }, 8566 { Bad_Opcode }, 8567 { Bad_Opcode }, 8568 /* c0 */ 8569 { Bad_Opcode }, 8570 { Bad_Opcode }, 8571 { Bad_Opcode }, 8572 { Bad_Opcode }, 8573 { Bad_Opcode }, 8574 { Bad_Opcode }, 8575 { Bad_Opcode }, 8576 { Bad_Opcode }, 8577 /* c8 */ 8578 { Bad_Opcode }, 8579 { Bad_Opcode }, 8580 { Bad_Opcode }, 8581 { Bad_Opcode }, 8582 { Bad_Opcode }, 8583 { Bad_Opcode }, 8584 { Bad_Opcode }, 8585 { Bad_Opcode }, 8586 /* d0 */ 8587 { Bad_Opcode }, 8588 { Bad_Opcode }, 8589 { Bad_Opcode }, 8590 { Bad_Opcode }, 8591 { Bad_Opcode }, 8592 { Bad_Opcode }, 8593 { Bad_Opcode }, 8594 { Bad_Opcode }, 8595 /* d8 */ 8596 { Bad_Opcode }, 8597 { Bad_Opcode }, 8598 { Bad_Opcode }, 8599 { Bad_Opcode }, 8600 { Bad_Opcode }, 8601 { Bad_Opcode }, 8602 { Bad_Opcode }, 8603 { Bad_Opcode }, 8604 /* e0 */ 8605 { Bad_Opcode }, 8606 { Bad_Opcode }, 8607 { Bad_Opcode }, 8608 { Bad_Opcode }, 8609 { Bad_Opcode }, 8610 { Bad_Opcode }, 8611 { Bad_Opcode }, 8612 { Bad_Opcode }, 8613 /* e8 */ 8614 { Bad_Opcode }, 8615 { Bad_Opcode }, 8616 { Bad_Opcode }, 8617 { Bad_Opcode }, 8618 { Bad_Opcode }, 8619 { Bad_Opcode }, 8620 { Bad_Opcode }, 8621 { Bad_Opcode }, 8622 /* f0 */ 8623 { Bad_Opcode }, 8624 { Bad_Opcode }, 8625 { Bad_Opcode }, 8626 { Bad_Opcode }, 8627 { Bad_Opcode }, 8628 { Bad_Opcode }, 8629 { Bad_Opcode }, 8630 { Bad_Opcode }, 8631 /* f8 */ 8632 { Bad_Opcode }, 8633 { Bad_Opcode }, 8634 { Bad_Opcode }, 8635 { Bad_Opcode }, 8636 { Bad_Opcode }, 8637 { Bad_Opcode }, 8638 { Bad_Opcode }, 8639 { Bad_Opcode }, 8640 }, 8641 }; 8642 8643 static const struct dis386 vex_table[][256] = { 8644 /* VEX_0F */ 8645 { 8646 /* 00 */ 8647 { Bad_Opcode }, 8648 { Bad_Opcode }, 8649 { Bad_Opcode }, 8650 { Bad_Opcode }, 8651 { Bad_Opcode }, 8652 { Bad_Opcode }, 8653 { Bad_Opcode }, 8654 { Bad_Opcode }, 8655 /* 08 */ 8656 { Bad_Opcode }, 8657 { Bad_Opcode }, 8658 { Bad_Opcode }, 8659 { Bad_Opcode }, 8660 { Bad_Opcode }, 8661 { Bad_Opcode }, 8662 { Bad_Opcode }, 8663 { Bad_Opcode }, 8664 /* 10 */ 8665 { PREFIX_TABLE (PREFIX_VEX_0F10) }, 8666 { PREFIX_TABLE (PREFIX_VEX_0F11) }, 8667 { PREFIX_TABLE (PREFIX_VEX_0F12) }, 8668 { MOD_TABLE (MOD_VEX_0F13) }, 8669 { VEX_W_TABLE (VEX_W_0F14) }, 8670 { VEX_W_TABLE (VEX_W_0F15) }, 8671 { PREFIX_TABLE (PREFIX_VEX_0F16) }, 8672 { MOD_TABLE (MOD_VEX_0F17) }, 8673 /* 18 */ 8674 { Bad_Opcode }, 8675 { Bad_Opcode }, 8676 { Bad_Opcode }, 8677 { Bad_Opcode }, 8678 { Bad_Opcode }, 8679 { Bad_Opcode }, 8680 { Bad_Opcode }, 8681 { Bad_Opcode }, 8682 /* 20 */ 8683 { Bad_Opcode }, 8684 { Bad_Opcode }, 8685 { Bad_Opcode }, 8686 { Bad_Opcode }, 8687 { Bad_Opcode }, 8688 { Bad_Opcode }, 8689 { Bad_Opcode }, 8690 { Bad_Opcode }, 8691 /* 28 */ 8692 { VEX_W_TABLE (VEX_W_0F28) }, 8693 { VEX_W_TABLE (VEX_W_0F29) }, 8694 { PREFIX_TABLE (PREFIX_VEX_0F2A) }, 8695 { MOD_TABLE (MOD_VEX_0F2B) }, 8696 { PREFIX_TABLE (PREFIX_VEX_0F2C) }, 8697 { PREFIX_TABLE (PREFIX_VEX_0F2D) }, 8698 { PREFIX_TABLE (PREFIX_VEX_0F2E) }, 8699 { PREFIX_TABLE (PREFIX_VEX_0F2F) }, 8700 /* 30 */ 8701 { Bad_Opcode }, 8702 { Bad_Opcode }, 8703 { Bad_Opcode }, 8704 { Bad_Opcode }, 8705 { Bad_Opcode }, 8706 { Bad_Opcode }, 8707 { Bad_Opcode }, 8708 { Bad_Opcode }, 8709 /* 38 */ 8710 { Bad_Opcode }, 8711 { Bad_Opcode }, 8712 { Bad_Opcode }, 8713 { Bad_Opcode }, 8714 { Bad_Opcode }, 8715 { Bad_Opcode }, 8716 { Bad_Opcode }, 8717 { Bad_Opcode }, 8718 /* 40 */ 8719 { Bad_Opcode }, 8720 { PREFIX_TABLE (PREFIX_VEX_0F41) }, 8721 { PREFIX_TABLE (PREFIX_VEX_0F42) }, 8722 { Bad_Opcode }, 8723 { PREFIX_TABLE (PREFIX_VEX_0F44) }, 8724 { PREFIX_TABLE (PREFIX_VEX_0F45) }, 8725 { PREFIX_TABLE (PREFIX_VEX_0F46) }, 8726 { PREFIX_TABLE (PREFIX_VEX_0F47) }, 8727 /* 48 */ 8728 { Bad_Opcode }, 8729 { Bad_Opcode }, 8730 { PREFIX_TABLE (PREFIX_VEX_0F4A) }, 8731 { PREFIX_TABLE (PREFIX_VEX_0F4B) }, 8732 { Bad_Opcode }, 8733 { Bad_Opcode }, 8734 { Bad_Opcode }, 8735 { Bad_Opcode }, 8736 /* 50 */ 8737 { MOD_TABLE (MOD_VEX_0F50) }, 8738 { PREFIX_TABLE (PREFIX_VEX_0F51) }, 8739 { PREFIX_TABLE (PREFIX_VEX_0F52) }, 8740 { PREFIX_TABLE (PREFIX_VEX_0F53) }, 8741 { "vandpX", { XM, Vex, EXx }, 0 }, 8742 { "vandnpX", { XM, Vex, EXx }, 0 }, 8743 { "vorpX", { XM, Vex, EXx }, 0 }, 8744 { "vxorpX", { XM, Vex, EXx }, 0 }, 8745 /* 58 */ 8746 { PREFIX_TABLE (PREFIX_VEX_0F58) }, 8747 { PREFIX_TABLE (PREFIX_VEX_0F59) }, 8748 { PREFIX_TABLE (PREFIX_VEX_0F5A) }, 8749 { PREFIX_TABLE (PREFIX_VEX_0F5B) }, 8750 { PREFIX_TABLE (PREFIX_VEX_0F5C) }, 8751 { PREFIX_TABLE (PREFIX_VEX_0F5D) }, 8752 { PREFIX_TABLE (PREFIX_VEX_0F5E) }, 8753 { PREFIX_TABLE (PREFIX_VEX_0F5F) }, 8754 /* 60 */ 8755 { PREFIX_TABLE (PREFIX_VEX_0F60) }, 8756 { PREFIX_TABLE (PREFIX_VEX_0F61) }, 8757 { PREFIX_TABLE (PREFIX_VEX_0F62) }, 8758 { PREFIX_TABLE (PREFIX_VEX_0F63) }, 8759 { PREFIX_TABLE (PREFIX_VEX_0F64) }, 8760 { PREFIX_TABLE (PREFIX_VEX_0F65) }, 8761 { PREFIX_TABLE (PREFIX_VEX_0F66) }, 8762 { PREFIX_TABLE (PREFIX_VEX_0F67) }, 8763 /* 68 */ 8764 { PREFIX_TABLE (PREFIX_VEX_0F68) }, 8765 { PREFIX_TABLE (PREFIX_VEX_0F69) }, 8766 { PREFIX_TABLE (PREFIX_VEX_0F6A) }, 8767 { PREFIX_TABLE (PREFIX_VEX_0F6B) }, 8768 { PREFIX_TABLE (PREFIX_VEX_0F6C) }, 8769 { PREFIX_TABLE (PREFIX_VEX_0F6D) }, 8770 { PREFIX_TABLE (PREFIX_VEX_0F6E) }, 8771 { PREFIX_TABLE (PREFIX_VEX_0F6F) }, 8772 /* 70 */ 8773 { PREFIX_TABLE (PREFIX_VEX_0F70) }, 8774 { REG_TABLE (REG_VEX_0F71) }, 8775 { REG_TABLE (REG_VEX_0F72) }, 8776 { REG_TABLE (REG_VEX_0F73) }, 8777 { PREFIX_TABLE (PREFIX_VEX_0F74) }, 8778 { PREFIX_TABLE (PREFIX_VEX_0F75) }, 8779 { PREFIX_TABLE (PREFIX_VEX_0F76) }, 8780 { PREFIX_TABLE (PREFIX_VEX_0F77) }, 8781 /* 78 */ 8782 { Bad_Opcode }, 8783 { Bad_Opcode }, 8784 { Bad_Opcode }, 8785 { Bad_Opcode }, 8786 { PREFIX_TABLE (PREFIX_VEX_0F7C) }, 8787 { PREFIX_TABLE (PREFIX_VEX_0F7D) }, 8788 { PREFIX_TABLE (PREFIX_VEX_0F7E) }, 8789 { PREFIX_TABLE (PREFIX_VEX_0F7F) }, 8790 /* 80 */ 8791 { Bad_Opcode }, 8792 { Bad_Opcode }, 8793 { Bad_Opcode }, 8794 { Bad_Opcode }, 8795 { Bad_Opcode }, 8796 { Bad_Opcode }, 8797 { Bad_Opcode }, 8798 { Bad_Opcode }, 8799 /* 88 */ 8800 { Bad_Opcode }, 8801 { Bad_Opcode }, 8802 { Bad_Opcode }, 8803 { Bad_Opcode }, 8804 { Bad_Opcode }, 8805 { Bad_Opcode }, 8806 { Bad_Opcode }, 8807 { Bad_Opcode }, 8808 /* 90 */ 8809 { PREFIX_TABLE (PREFIX_VEX_0F90) }, 8810 { PREFIX_TABLE (PREFIX_VEX_0F91) }, 8811 { PREFIX_TABLE (PREFIX_VEX_0F92) }, 8812 { PREFIX_TABLE (PREFIX_VEX_0F93) }, 8813 { Bad_Opcode }, 8814 { Bad_Opcode }, 8815 { Bad_Opcode }, 8816 { Bad_Opcode }, 8817 /* 98 */ 8818 { PREFIX_TABLE (PREFIX_VEX_0F98) }, 8819 { PREFIX_TABLE (PREFIX_VEX_0F99) }, 8820 { Bad_Opcode }, 8821 { Bad_Opcode }, 8822 { Bad_Opcode }, 8823 { Bad_Opcode }, 8824 { Bad_Opcode }, 8825 { Bad_Opcode }, 8826 /* a0 */ 8827 { Bad_Opcode }, 8828 { Bad_Opcode }, 8829 { Bad_Opcode }, 8830 { Bad_Opcode }, 8831 { Bad_Opcode }, 8832 { Bad_Opcode }, 8833 { Bad_Opcode }, 8834 { Bad_Opcode }, 8835 /* a8 */ 8836 { Bad_Opcode }, 8837 { Bad_Opcode }, 8838 { Bad_Opcode }, 8839 { Bad_Opcode }, 8840 { Bad_Opcode }, 8841 { Bad_Opcode }, 8842 { REG_TABLE (REG_VEX_0FAE) }, 8843 { Bad_Opcode }, 8844 /* b0 */ 8845 { Bad_Opcode }, 8846 { Bad_Opcode }, 8847 { Bad_Opcode }, 8848 { Bad_Opcode }, 8849 { Bad_Opcode }, 8850 { Bad_Opcode }, 8851 { Bad_Opcode }, 8852 { Bad_Opcode }, 8853 /* b8 */ 8854 { Bad_Opcode }, 8855 { Bad_Opcode }, 8856 { Bad_Opcode }, 8857 { Bad_Opcode }, 8858 { Bad_Opcode }, 8859 { Bad_Opcode }, 8860 { Bad_Opcode }, 8861 { Bad_Opcode }, 8862 /* c0 */ 8863 { Bad_Opcode }, 8864 { Bad_Opcode }, 8865 { PREFIX_TABLE (PREFIX_VEX_0FC2) }, 8866 { Bad_Opcode }, 8867 { PREFIX_TABLE (PREFIX_VEX_0FC4) }, 8868 { PREFIX_TABLE (PREFIX_VEX_0FC5) }, 8869 { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, 8870 { Bad_Opcode }, 8871 /* c8 */ 8872 { Bad_Opcode }, 8873 { Bad_Opcode }, 8874 { Bad_Opcode }, 8875 { Bad_Opcode }, 8876 { Bad_Opcode }, 8877 { Bad_Opcode }, 8878 { Bad_Opcode }, 8879 { Bad_Opcode }, 8880 /* d0 */ 8881 { PREFIX_TABLE (PREFIX_VEX_0FD0) }, 8882 { PREFIX_TABLE (PREFIX_VEX_0FD1) }, 8883 { PREFIX_TABLE (PREFIX_VEX_0FD2) }, 8884 { PREFIX_TABLE (PREFIX_VEX_0FD3) }, 8885 { PREFIX_TABLE (PREFIX_VEX_0FD4) }, 8886 { PREFIX_TABLE (PREFIX_VEX_0FD5) }, 8887 { PREFIX_TABLE (PREFIX_VEX_0FD6) }, 8888 { PREFIX_TABLE (PREFIX_VEX_0FD7) }, 8889 /* d8 */ 8890 { PREFIX_TABLE (PREFIX_VEX_0FD8) }, 8891 { PREFIX_TABLE (PREFIX_VEX_0FD9) }, 8892 { PREFIX_TABLE (PREFIX_VEX_0FDA) }, 8893 { PREFIX_TABLE (PREFIX_VEX_0FDB) }, 8894 { PREFIX_TABLE (PREFIX_VEX_0FDC) }, 8895 { PREFIX_TABLE (PREFIX_VEX_0FDD) }, 8896 { PREFIX_TABLE (PREFIX_VEX_0FDE) }, 8897 { PREFIX_TABLE (PREFIX_VEX_0FDF) }, 8898 /* e0 */ 8899 { PREFIX_TABLE (PREFIX_VEX_0FE0) }, 8900 { PREFIX_TABLE (PREFIX_VEX_0FE1) }, 8901 { PREFIX_TABLE (PREFIX_VEX_0FE2) }, 8902 { PREFIX_TABLE (PREFIX_VEX_0FE3) }, 8903 { PREFIX_TABLE (PREFIX_VEX_0FE4) }, 8904 { PREFIX_TABLE (PREFIX_VEX_0FE5) }, 8905 { PREFIX_TABLE (PREFIX_VEX_0FE6) }, 8906 { PREFIX_TABLE (PREFIX_VEX_0FE7) }, 8907 /* e8 */ 8908 { PREFIX_TABLE (PREFIX_VEX_0FE8) }, 8909 { PREFIX_TABLE (PREFIX_VEX_0FE9) }, 8910 { PREFIX_TABLE (PREFIX_VEX_0FEA) }, 8911 { PREFIX_TABLE (PREFIX_VEX_0FEB) }, 8912 { PREFIX_TABLE (PREFIX_VEX_0FEC) }, 8913 { PREFIX_TABLE (PREFIX_VEX_0FED) }, 8914 { PREFIX_TABLE (PREFIX_VEX_0FEE) }, 8915 { PREFIX_TABLE (PREFIX_VEX_0FEF) }, 8916 /* f0 */ 8917 { PREFIX_TABLE (PREFIX_VEX_0FF0) }, 8918 { PREFIX_TABLE (PREFIX_VEX_0FF1) }, 8919 { PREFIX_TABLE (PREFIX_VEX_0FF2) }, 8920 { PREFIX_TABLE (PREFIX_VEX_0FF3) }, 8921 { PREFIX_TABLE (PREFIX_VEX_0FF4) }, 8922 { PREFIX_TABLE (PREFIX_VEX_0FF5) }, 8923 { PREFIX_TABLE (PREFIX_VEX_0FF6) }, 8924 { PREFIX_TABLE (PREFIX_VEX_0FF7) }, 8925 /* f8 */ 8926 { PREFIX_TABLE (PREFIX_VEX_0FF8) }, 8927 { PREFIX_TABLE (PREFIX_VEX_0FF9) }, 8928 { PREFIX_TABLE (PREFIX_VEX_0FFA) }, 8929 { PREFIX_TABLE (PREFIX_VEX_0FFB) }, 8930 { PREFIX_TABLE (PREFIX_VEX_0FFC) }, 8931 { PREFIX_TABLE (PREFIX_VEX_0FFD) }, 8932 { PREFIX_TABLE (PREFIX_VEX_0FFE) }, 8933 { Bad_Opcode }, 8934 }, 8935 /* VEX_0F38 */ 8936 { 8937 /* 00 */ 8938 { PREFIX_TABLE (PREFIX_VEX_0F3800) }, 8939 { PREFIX_TABLE (PREFIX_VEX_0F3801) }, 8940 { PREFIX_TABLE (PREFIX_VEX_0F3802) }, 8941 { PREFIX_TABLE (PREFIX_VEX_0F3803) }, 8942 { PREFIX_TABLE (PREFIX_VEX_0F3804) }, 8943 { PREFIX_TABLE (PREFIX_VEX_0F3805) }, 8944 { PREFIX_TABLE (PREFIX_VEX_0F3806) }, 8945 { PREFIX_TABLE (PREFIX_VEX_0F3807) }, 8946 /* 08 */ 8947 { PREFIX_TABLE (PREFIX_VEX_0F3808) }, 8948 { PREFIX_TABLE (PREFIX_VEX_0F3809) }, 8949 { PREFIX_TABLE (PREFIX_VEX_0F380A) }, 8950 { PREFIX_TABLE (PREFIX_VEX_0F380B) }, 8951 { PREFIX_TABLE (PREFIX_VEX_0F380C) }, 8952 { PREFIX_TABLE (PREFIX_VEX_0F380D) }, 8953 { PREFIX_TABLE (PREFIX_VEX_0F380E) }, 8954 { PREFIX_TABLE (PREFIX_VEX_0F380F) }, 8955 /* 10 */ 8956 { Bad_Opcode }, 8957 { Bad_Opcode }, 8958 { Bad_Opcode }, 8959 { PREFIX_TABLE (PREFIX_VEX_0F3813) }, 8960 { Bad_Opcode }, 8961 { Bad_Opcode }, 8962 { PREFIX_TABLE (PREFIX_VEX_0F3816) }, 8963 { PREFIX_TABLE (PREFIX_VEX_0F3817) }, 8964 /* 18 */ 8965 { PREFIX_TABLE (PREFIX_VEX_0F3818) }, 8966 { PREFIX_TABLE (PREFIX_VEX_0F3819) }, 8967 { PREFIX_TABLE (PREFIX_VEX_0F381A) }, 8968 { Bad_Opcode }, 8969 { PREFIX_TABLE (PREFIX_VEX_0F381C) }, 8970 { PREFIX_TABLE (PREFIX_VEX_0F381D) }, 8971 { PREFIX_TABLE (PREFIX_VEX_0F381E) }, 8972 { Bad_Opcode }, 8973 /* 20 */ 8974 { PREFIX_TABLE (PREFIX_VEX_0F3820) }, 8975 { PREFIX_TABLE (PREFIX_VEX_0F3821) }, 8976 { PREFIX_TABLE (PREFIX_VEX_0F3822) }, 8977 { PREFIX_TABLE (PREFIX_VEX_0F3823) }, 8978 { PREFIX_TABLE (PREFIX_VEX_0F3824) }, 8979 { PREFIX_TABLE (PREFIX_VEX_0F3825) }, 8980 { Bad_Opcode }, 8981 { Bad_Opcode }, 8982 /* 28 */ 8983 { PREFIX_TABLE (PREFIX_VEX_0F3828) }, 8984 { PREFIX_TABLE (PREFIX_VEX_0F3829) }, 8985 { PREFIX_TABLE (PREFIX_VEX_0F382A) }, 8986 { PREFIX_TABLE (PREFIX_VEX_0F382B) }, 8987 { PREFIX_TABLE (PREFIX_VEX_0F382C) }, 8988 { PREFIX_TABLE (PREFIX_VEX_0F382D) }, 8989 { PREFIX_TABLE (PREFIX_VEX_0F382E) }, 8990 { PREFIX_TABLE (PREFIX_VEX_0F382F) }, 8991 /* 30 */ 8992 { PREFIX_TABLE (PREFIX_VEX_0F3830) }, 8993 { PREFIX_TABLE (PREFIX_VEX_0F3831) }, 8994 { PREFIX_TABLE (PREFIX_VEX_0F3832) }, 8995 { PREFIX_TABLE (PREFIX_VEX_0F3833) }, 8996 { PREFIX_TABLE (PREFIX_VEX_0F3834) }, 8997 { PREFIX_TABLE (PREFIX_VEX_0F3835) }, 8998 { PREFIX_TABLE (PREFIX_VEX_0F3836) }, 8999 { PREFIX_TABLE (PREFIX_VEX_0F3837) }, 9000 /* 38 */ 9001 { PREFIX_TABLE (PREFIX_VEX_0F3838) }, 9002 { PREFIX_TABLE (PREFIX_VEX_0F3839) }, 9003 { PREFIX_TABLE (PREFIX_VEX_0F383A) }, 9004 { PREFIX_TABLE (PREFIX_VEX_0F383B) }, 9005 { PREFIX_TABLE (PREFIX_VEX_0F383C) }, 9006 { PREFIX_TABLE (PREFIX_VEX_0F383D) }, 9007 { PREFIX_TABLE (PREFIX_VEX_0F383E) }, 9008 { PREFIX_TABLE (PREFIX_VEX_0F383F) }, 9009 /* 40 */ 9010 { PREFIX_TABLE (PREFIX_VEX_0F3840) }, 9011 { PREFIX_TABLE (PREFIX_VEX_0F3841) }, 9012 { Bad_Opcode }, 9013 { Bad_Opcode }, 9014 { Bad_Opcode }, 9015 { PREFIX_TABLE (PREFIX_VEX_0F3845) }, 9016 { PREFIX_TABLE (PREFIX_VEX_0F3846) }, 9017 { PREFIX_TABLE (PREFIX_VEX_0F3847) }, 9018 /* 48 */ 9019 { Bad_Opcode }, 9020 { Bad_Opcode }, 9021 { Bad_Opcode }, 9022 { Bad_Opcode }, 9023 { Bad_Opcode }, 9024 { Bad_Opcode }, 9025 { Bad_Opcode }, 9026 { Bad_Opcode }, 9027 /* 50 */ 9028 { Bad_Opcode }, 9029 { Bad_Opcode }, 9030 { Bad_Opcode }, 9031 { Bad_Opcode }, 9032 { Bad_Opcode }, 9033 { Bad_Opcode }, 9034 { Bad_Opcode }, 9035 { Bad_Opcode }, 9036 /* 58 */ 9037 { PREFIX_TABLE (PREFIX_VEX_0F3858) }, 9038 { PREFIX_TABLE (PREFIX_VEX_0F3859) }, 9039 { PREFIX_TABLE (PREFIX_VEX_0F385A) }, 9040 { Bad_Opcode }, 9041 { Bad_Opcode }, 9042 { Bad_Opcode }, 9043 { Bad_Opcode }, 9044 { Bad_Opcode }, 9045 /* 60 */ 9046 { Bad_Opcode }, 9047 { Bad_Opcode }, 9048 { Bad_Opcode }, 9049 { Bad_Opcode }, 9050 { Bad_Opcode }, 9051 { Bad_Opcode }, 9052 { Bad_Opcode }, 9053 { Bad_Opcode }, 9054 /* 68 */ 9055 { Bad_Opcode }, 9056 { Bad_Opcode }, 9057 { Bad_Opcode }, 9058 { Bad_Opcode }, 9059 { Bad_Opcode }, 9060 { Bad_Opcode }, 9061 { Bad_Opcode }, 9062 { Bad_Opcode }, 9063 /* 70 */ 9064 { Bad_Opcode }, 9065 { Bad_Opcode }, 9066 { Bad_Opcode }, 9067 { Bad_Opcode }, 9068 { Bad_Opcode }, 9069 { Bad_Opcode }, 9070 { Bad_Opcode }, 9071 { Bad_Opcode }, 9072 /* 78 */ 9073 { PREFIX_TABLE (PREFIX_VEX_0F3878) }, 9074 { PREFIX_TABLE (PREFIX_VEX_0F3879) }, 9075 { Bad_Opcode }, 9076 { Bad_Opcode }, 9077 { Bad_Opcode }, 9078 { Bad_Opcode }, 9079 { Bad_Opcode }, 9080 { Bad_Opcode }, 9081 /* 80 */ 9082 { Bad_Opcode }, 9083 { Bad_Opcode }, 9084 { Bad_Opcode }, 9085 { Bad_Opcode }, 9086 { Bad_Opcode }, 9087 { Bad_Opcode }, 9088 { Bad_Opcode }, 9089 { Bad_Opcode }, 9090 /* 88 */ 9091 { Bad_Opcode }, 9092 { Bad_Opcode }, 9093 { Bad_Opcode }, 9094 { Bad_Opcode }, 9095 { PREFIX_TABLE (PREFIX_VEX_0F388C) }, 9096 { Bad_Opcode }, 9097 { PREFIX_TABLE (PREFIX_VEX_0F388E) }, 9098 { Bad_Opcode }, 9099 /* 90 */ 9100 { PREFIX_TABLE (PREFIX_VEX_0F3890) }, 9101 { PREFIX_TABLE (PREFIX_VEX_0F3891) }, 9102 { PREFIX_TABLE (PREFIX_VEX_0F3892) }, 9103 { PREFIX_TABLE (PREFIX_VEX_0F3893) }, 9104 { Bad_Opcode }, 9105 { Bad_Opcode }, 9106 { PREFIX_TABLE (PREFIX_VEX_0F3896) }, 9107 { PREFIX_TABLE (PREFIX_VEX_0F3897) }, 9108 /* 98 */ 9109 { PREFIX_TABLE (PREFIX_VEX_0F3898) }, 9110 { PREFIX_TABLE (PREFIX_VEX_0F3899) }, 9111 { PREFIX_TABLE (PREFIX_VEX_0F389A) }, 9112 { PREFIX_TABLE (PREFIX_VEX_0F389B) }, 9113 { PREFIX_TABLE (PREFIX_VEX_0F389C) }, 9114 { PREFIX_TABLE (PREFIX_VEX_0F389D) }, 9115 { PREFIX_TABLE (PREFIX_VEX_0F389E) }, 9116 { PREFIX_TABLE (PREFIX_VEX_0F389F) }, 9117 /* a0 */ 9118 { Bad_Opcode }, 9119 { Bad_Opcode }, 9120 { Bad_Opcode }, 9121 { Bad_Opcode }, 9122 { Bad_Opcode }, 9123 { Bad_Opcode }, 9124 { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, 9125 { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, 9126 /* a8 */ 9127 { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, 9128 { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, 9129 { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, 9130 { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, 9131 { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, 9132 { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, 9133 { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, 9134 { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, 9135 /* b0 */ 9136 { Bad_Opcode }, 9137 { Bad_Opcode }, 9138 { Bad_Opcode }, 9139 { Bad_Opcode }, 9140 { Bad_Opcode }, 9141 { Bad_Opcode }, 9142 { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, 9143 { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, 9144 /* b8 */ 9145 { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, 9146 { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, 9147 { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, 9148 { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, 9149 { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, 9150 { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, 9151 { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, 9152 { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, 9153 /* c0 */ 9154 { Bad_Opcode }, 9155 { Bad_Opcode }, 9156 { Bad_Opcode }, 9157 { Bad_Opcode }, 9158 { Bad_Opcode }, 9159 { Bad_Opcode }, 9160 { Bad_Opcode }, 9161 { Bad_Opcode }, 9162 /* c8 */ 9163 { Bad_Opcode }, 9164 { Bad_Opcode }, 9165 { Bad_Opcode }, 9166 { Bad_Opcode }, 9167 { Bad_Opcode }, 9168 { Bad_Opcode }, 9169 { Bad_Opcode }, 9170 { Bad_Opcode }, 9171 /* d0 */ 9172 { Bad_Opcode }, 9173 { Bad_Opcode }, 9174 { Bad_Opcode }, 9175 { Bad_Opcode }, 9176 { Bad_Opcode }, 9177 { Bad_Opcode }, 9178 { Bad_Opcode }, 9179 { Bad_Opcode }, 9180 /* d8 */ 9181 { Bad_Opcode }, 9182 { Bad_Opcode }, 9183 { Bad_Opcode }, 9184 { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, 9185 { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, 9186 { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, 9187 { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, 9188 { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, 9189 /* e0 */ 9190 { Bad_Opcode }, 9191 { Bad_Opcode }, 9192 { Bad_Opcode }, 9193 { Bad_Opcode }, 9194 { Bad_Opcode }, 9195 { Bad_Opcode }, 9196 { Bad_Opcode }, 9197 { Bad_Opcode }, 9198 /* e8 */ 9199 { Bad_Opcode }, 9200 { Bad_Opcode }, 9201 { Bad_Opcode }, 9202 { Bad_Opcode }, 9203 { Bad_Opcode }, 9204 { Bad_Opcode }, 9205 { Bad_Opcode }, 9206 { Bad_Opcode }, 9207 /* f0 */ 9208 { Bad_Opcode }, 9209 { Bad_Opcode }, 9210 { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, 9211 { REG_TABLE (REG_VEX_0F38F3) }, 9212 { Bad_Opcode }, 9213 { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, 9214 { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, 9215 { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, 9216 /* f8 */ 9217 { Bad_Opcode }, 9218 { Bad_Opcode }, 9219 { Bad_Opcode }, 9220 { Bad_Opcode }, 9221 { Bad_Opcode }, 9222 { Bad_Opcode }, 9223 { Bad_Opcode }, 9224 { Bad_Opcode }, 9225 }, 9226 /* VEX_0F3A */ 9227 { 9228 /* 00 */ 9229 { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, 9230 { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, 9231 { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, 9232 { Bad_Opcode }, 9233 { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, 9234 { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, 9235 { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, 9236 { Bad_Opcode }, 9237 /* 08 */ 9238 { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, 9239 { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, 9240 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, 9241 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, 9242 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, 9243 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, 9244 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, 9245 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, 9246 /* 10 */ 9247 { Bad_Opcode }, 9248 { Bad_Opcode }, 9249 { Bad_Opcode }, 9250 { Bad_Opcode }, 9251 { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, 9252 { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, 9253 { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, 9254 { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, 9255 /* 18 */ 9256 { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, 9257 { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, 9258 { Bad_Opcode }, 9259 { Bad_Opcode }, 9260 { Bad_Opcode }, 9261 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, 9262 { Bad_Opcode }, 9263 { Bad_Opcode }, 9264 /* 20 */ 9265 { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, 9266 { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, 9267 { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, 9268 { Bad_Opcode }, 9269 { Bad_Opcode }, 9270 { Bad_Opcode }, 9271 { Bad_Opcode }, 9272 { Bad_Opcode }, 9273 /* 28 */ 9274 { Bad_Opcode }, 9275 { Bad_Opcode }, 9276 { Bad_Opcode }, 9277 { Bad_Opcode }, 9278 { Bad_Opcode }, 9279 { Bad_Opcode }, 9280 { Bad_Opcode }, 9281 { Bad_Opcode }, 9282 /* 30 */ 9283 { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, 9284 { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, 9285 { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, 9286 { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, 9287 { Bad_Opcode }, 9288 { Bad_Opcode }, 9289 { Bad_Opcode }, 9290 { Bad_Opcode }, 9291 /* 38 */ 9292 { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, 9293 { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, 9294 { Bad_Opcode }, 9295 { Bad_Opcode }, 9296 { Bad_Opcode }, 9297 { Bad_Opcode }, 9298 { Bad_Opcode }, 9299 { Bad_Opcode }, 9300 /* 40 */ 9301 { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, 9302 { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, 9303 { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, 9304 { Bad_Opcode }, 9305 { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, 9306 { Bad_Opcode }, 9307 { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, 9308 { Bad_Opcode }, 9309 /* 48 */ 9310 { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, 9311 { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, 9312 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, 9313 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, 9314 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, 9315 { Bad_Opcode }, 9316 { Bad_Opcode }, 9317 { Bad_Opcode }, 9318 /* 50 */ 9319 { Bad_Opcode }, 9320 { Bad_Opcode }, 9321 { Bad_Opcode }, 9322 { Bad_Opcode }, 9323 { Bad_Opcode }, 9324 { Bad_Opcode }, 9325 { Bad_Opcode }, 9326 { Bad_Opcode }, 9327 /* 58 */ 9328 { Bad_Opcode }, 9329 { Bad_Opcode }, 9330 { Bad_Opcode }, 9331 { Bad_Opcode }, 9332 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, 9333 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, 9334 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, 9335 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, 9336 /* 60 */ 9337 { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, 9338 { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, 9339 { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, 9340 { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, 9341 { Bad_Opcode }, 9342 { Bad_Opcode }, 9343 { Bad_Opcode }, 9344 { Bad_Opcode }, 9345 /* 68 */ 9346 { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, 9347 { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, 9348 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, 9349 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, 9350 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, 9351 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, 9352 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, 9353 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, 9354 /* 70 */ 9355 { Bad_Opcode }, 9356 { Bad_Opcode }, 9357 { Bad_Opcode }, 9358 { Bad_Opcode }, 9359 { Bad_Opcode }, 9360 { Bad_Opcode }, 9361 { Bad_Opcode }, 9362 { Bad_Opcode }, 9363 /* 78 */ 9364 { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, 9365 { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, 9366 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, 9367 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, 9368 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, 9369 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, 9370 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, 9371 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, 9372 /* 80 */ 9373 { Bad_Opcode }, 9374 { Bad_Opcode }, 9375 { Bad_Opcode }, 9376 { Bad_Opcode }, 9377 { Bad_Opcode }, 9378 { Bad_Opcode }, 9379 { Bad_Opcode }, 9380 { Bad_Opcode }, 9381 /* 88 */ 9382 { Bad_Opcode }, 9383 { Bad_Opcode }, 9384 { Bad_Opcode }, 9385 { Bad_Opcode }, 9386 { Bad_Opcode }, 9387 { Bad_Opcode }, 9388 { Bad_Opcode }, 9389 { Bad_Opcode }, 9390 /* 90 */ 9391 { Bad_Opcode }, 9392 { Bad_Opcode }, 9393 { Bad_Opcode }, 9394 { Bad_Opcode }, 9395 { Bad_Opcode }, 9396 { Bad_Opcode }, 9397 { Bad_Opcode }, 9398 { Bad_Opcode }, 9399 /* 98 */ 9400 { Bad_Opcode }, 9401 { Bad_Opcode }, 9402 { Bad_Opcode }, 9403 { Bad_Opcode }, 9404 { Bad_Opcode }, 9405 { Bad_Opcode }, 9406 { Bad_Opcode }, 9407 { Bad_Opcode }, 9408 /* a0 */ 9409 { Bad_Opcode }, 9410 { Bad_Opcode }, 9411 { Bad_Opcode }, 9412 { Bad_Opcode }, 9413 { Bad_Opcode }, 9414 { Bad_Opcode }, 9415 { Bad_Opcode }, 9416 { Bad_Opcode }, 9417 /* a8 */ 9418 { Bad_Opcode }, 9419 { Bad_Opcode }, 9420 { Bad_Opcode }, 9421 { Bad_Opcode }, 9422 { Bad_Opcode }, 9423 { Bad_Opcode }, 9424 { Bad_Opcode }, 9425 { Bad_Opcode }, 9426 /* b0 */ 9427 { Bad_Opcode }, 9428 { Bad_Opcode }, 9429 { Bad_Opcode }, 9430 { Bad_Opcode }, 9431 { Bad_Opcode }, 9432 { Bad_Opcode }, 9433 { Bad_Opcode }, 9434 { Bad_Opcode }, 9435 /* b8 */ 9436 { Bad_Opcode }, 9437 { Bad_Opcode }, 9438 { Bad_Opcode }, 9439 { Bad_Opcode }, 9440 { Bad_Opcode }, 9441 { Bad_Opcode }, 9442 { Bad_Opcode }, 9443 { Bad_Opcode }, 9444 /* c0 */ 9445 { Bad_Opcode }, 9446 { Bad_Opcode }, 9447 { Bad_Opcode }, 9448 { Bad_Opcode }, 9449 { Bad_Opcode }, 9450 { Bad_Opcode }, 9451 { Bad_Opcode }, 9452 { Bad_Opcode }, 9453 /* c8 */ 9454 { Bad_Opcode }, 9455 { Bad_Opcode }, 9456 { Bad_Opcode }, 9457 { Bad_Opcode }, 9458 { Bad_Opcode }, 9459 { Bad_Opcode }, 9460 { Bad_Opcode }, 9461 { Bad_Opcode }, 9462 /* d0 */ 9463 { Bad_Opcode }, 9464 { Bad_Opcode }, 9465 { Bad_Opcode }, 9466 { Bad_Opcode }, 9467 { Bad_Opcode }, 9468 { Bad_Opcode }, 9469 { Bad_Opcode }, 9470 { Bad_Opcode }, 9471 /* d8 */ 9472 { Bad_Opcode }, 9473 { Bad_Opcode }, 9474 { Bad_Opcode }, 9475 { Bad_Opcode }, 9476 { Bad_Opcode }, 9477 { Bad_Opcode }, 9478 { Bad_Opcode }, 9479 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, 9480 /* e0 */ 9481 { Bad_Opcode }, 9482 { Bad_Opcode }, 9483 { Bad_Opcode }, 9484 { Bad_Opcode }, 9485 { Bad_Opcode }, 9486 { Bad_Opcode }, 9487 { Bad_Opcode }, 9488 { Bad_Opcode }, 9489 /* e8 */ 9490 { Bad_Opcode }, 9491 { Bad_Opcode }, 9492 { Bad_Opcode }, 9493 { Bad_Opcode }, 9494 { Bad_Opcode }, 9495 { Bad_Opcode }, 9496 { Bad_Opcode }, 9497 { Bad_Opcode }, 9498 /* f0 */ 9499 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, 9500 { Bad_Opcode }, 9501 { Bad_Opcode }, 9502 { Bad_Opcode }, 9503 { Bad_Opcode }, 9504 { Bad_Opcode }, 9505 { Bad_Opcode }, 9506 { Bad_Opcode }, 9507 /* f8 */ 9508 { Bad_Opcode }, 9509 { Bad_Opcode }, 9510 { Bad_Opcode }, 9511 { Bad_Opcode }, 9512 { Bad_Opcode }, 9513 { Bad_Opcode }, 9514 { Bad_Opcode }, 9515 { Bad_Opcode }, 9516 }, 9517 }; 9518 9519 #define NEED_OPCODE_TABLE 9520 #include "i386-dis-evex.h" 9521 #undef NEED_OPCODE_TABLE 9522 static const struct dis386 vex_len_table[][2] = { 9523 /* VEX_LEN_0F10_P_1 */ 9524 { 9525 { VEX_W_TABLE (VEX_W_0F10_P_1) }, 9526 { VEX_W_TABLE (VEX_W_0F10_P_1) }, 9527 }, 9528 9529 /* VEX_LEN_0F10_P_3 */ 9530 { 9531 { VEX_W_TABLE (VEX_W_0F10_P_3) }, 9532 { VEX_W_TABLE (VEX_W_0F10_P_3) }, 9533 }, 9534 9535 /* VEX_LEN_0F11_P_1 */ 9536 { 9537 { VEX_W_TABLE (VEX_W_0F11_P_1) }, 9538 { VEX_W_TABLE (VEX_W_0F11_P_1) }, 9539 }, 9540 9541 /* VEX_LEN_0F11_P_3 */ 9542 { 9543 { VEX_W_TABLE (VEX_W_0F11_P_3) }, 9544 { VEX_W_TABLE (VEX_W_0F11_P_3) }, 9545 }, 9546 9547 /* VEX_LEN_0F12_P_0_M_0 */ 9548 { 9549 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, 9550 }, 9551 9552 /* VEX_LEN_0F12_P_0_M_1 */ 9553 { 9554 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, 9555 }, 9556 9557 /* VEX_LEN_0F12_P_2 */ 9558 { 9559 { VEX_W_TABLE (VEX_W_0F12_P_2) }, 9560 }, 9561 9562 /* VEX_LEN_0F13_M_0 */ 9563 { 9564 { VEX_W_TABLE (VEX_W_0F13_M_0) }, 9565 }, 9566 9567 /* VEX_LEN_0F16_P_0_M_0 */ 9568 { 9569 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, 9570 }, 9571 9572 /* VEX_LEN_0F16_P_0_M_1 */ 9573 { 9574 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, 9575 }, 9576 9577 /* VEX_LEN_0F16_P_2 */ 9578 { 9579 { VEX_W_TABLE (VEX_W_0F16_P_2) }, 9580 }, 9581 9582 /* VEX_LEN_0F17_M_0 */ 9583 { 9584 { VEX_W_TABLE (VEX_W_0F17_M_0) }, 9585 }, 9586 9587 /* VEX_LEN_0F2A_P_1 */ 9588 { 9589 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, 9590 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, 9591 }, 9592 9593 /* VEX_LEN_0F2A_P_3 */ 9594 { 9595 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, 9596 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, 9597 }, 9598 9599 /* VEX_LEN_0F2C_P_1 */ 9600 { 9601 { "vcvttss2siY", { Gv, EXdScalar }, 0 }, 9602 { "vcvttss2siY", { Gv, EXdScalar }, 0 }, 9603 }, 9604 9605 /* VEX_LEN_0F2C_P_3 */ 9606 { 9607 { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, 9608 { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, 9609 }, 9610 9611 /* VEX_LEN_0F2D_P_1 */ 9612 { 9613 { "vcvtss2siY", { Gv, EXdScalar }, 0 }, 9614 { "vcvtss2siY", { Gv, EXdScalar }, 0 }, 9615 }, 9616 9617 /* VEX_LEN_0F2D_P_3 */ 9618 { 9619 { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, 9620 { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, 9621 }, 9622 9623 /* VEX_LEN_0F2E_P_0 */ 9624 { 9625 { VEX_W_TABLE (VEX_W_0F2E_P_0) }, 9626 { VEX_W_TABLE (VEX_W_0F2E_P_0) }, 9627 }, 9628 9629 /* VEX_LEN_0F2E_P_2 */ 9630 { 9631 { VEX_W_TABLE (VEX_W_0F2E_P_2) }, 9632 { VEX_W_TABLE (VEX_W_0F2E_P_2) }, 9633 }, 9634 9635 /* VEX_LEN_0F2F_P_0 */ 9636 { 9637 { VEX_W_TABLE (VEX_W_0F2F_P_0) }, 9638 { VEX_W_TABLE (VEX_W_0F2F_P_0) }, 9639 }, 9640 9641 /* VEX_LEN_0F2F_P_2 */ 9642 { 9643 { VEX_W_TABLE (VEX_W_0F2F_P_2) }, 9644 { VEX_W_TABLE (VEX_W_0F2F_P_2) }, 9645 }, 9646 9647 /* VEX_LEN_0F41_P_0 */ 9648 { 9649 { Bad_Opcode }, 9650 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, 9651 }, 9652 /* VEX_LEN_0F41_P_2 */ 9653 { 9654 { Bad_Opcode }, 9655 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, 9656 }, 9657 /* VEX_LEN_0F42_P_0 */ 9658 { 9659 { Bad_Opcode }, 9660 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, 9661 }, 9662 /* VEX_LEN_0F42_P_2 */ 9663 { 9664 { Bad_Opcode }, 9665 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, 9666 }, 9667 /* VEX_LEN_0F44_P_0 */ 9668 { 9669 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, 9670 }, 9671 /* VEX_LEN_0F44_P_2 */ 9672 { 9673 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, 9674 }, 9675 /* VEX_LEN_0F45_P_0 */ 9676 { 9677 { Bad_Opcode }, 9678 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, 9679 }, 9680 /* VEX_LEN_0F45_P_2 */ 9681 { 9682 { Bad_Opcode }, 9683 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, 9684 }, 9685 /* VEX_LEN_0F46_P_0 */ 9686 { 9687 { Bad_Opcode }, 9688 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, 9689 }, 9690 /* VEX_LEN_0F46_P_2 */ 9691 { 9692 { Bad_Opcode }, 9693 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, 9694 }, 9695 /* VEX_LEN_0F47_P_0 */ 9696 { 9697 { Bad_Opcode }, 9698 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, 9699 }, 9700 /* VEX_LEN_0F47_P_2 */ 9701 { 9702 { Bad_Opcode }, 9703 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, 9704 }, 9705 /* VEX_LEN_0F4A_P_0 */ 9706 { 9707 { Bad_Opcode }, 9708 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, 9709 }, 9710 /* VEX_LEN_0F4A_P_2 */ 9711 { 9712 { Bad_Opcode }, 9713 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, 9714 }, 9715 /* VEX_LEN_0F4B_P_0 */ 9716 { 9717 { Bad_Opcode }, 9718 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, 9719 }, 9720 /* VEX_LEN_0F4B_P_2 */ 9721 { 9722 { Bad_Opcode }, 9723 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, 9724 }, 9725 9726 /* VEX_LEN_0F51_P_1 */ 9727 { 9728 { VEX_W_TABLE (VEX_W_0F51_P_1) }, 9729 { VEX_W_TABLE (VEX_W_0F51_P_1) }, 9730 }, 9731 9732 /* VEX_LEN_0F51_P_3 */ 9733 { 9734 { VEX_W_TABLE (VEX_W_0F51_P_3) }, 9735 { VEX_W_TABLE (VEX_W_0F51_P_3) }, 9736 }, 9737 9738 /* VEX_LEN_0F52_P_1 */ 9739 { 9740 { VEX_W_TABLE (VEX_W_0F52_P_1) }, 9741 { VEX_W_TABLE (VEX_W_0F52_P_1) }, 9742 }, 9743 9744 /* VEX_LEN_0F53_P_1 */ 9745 { 9746 { VEX_W_TABLE (VEX_W_0F53_P_1) }, 9747 { VEX_W_TABLE (VEX_W_0F53_P_1) }, 9748 }, 9749 9750 /* VEX_LEN_0F58_P_1 */ 9751 { 9752 { VEX_W_TABLE (VEX_W_0F58_P_1) }, 9753 { VEX_W_TABLE (VEX_W_0F58_P_1) }, 9754 }, 9755 9756 /* VEX_LEN_0F58_P_3 */ 9757 { 9758 { VEX_W_TABLE (VEX_W_0F58_P_3) }, 9759 { VEX_W_TABLE (VEX_W_0F58_P_3) }, 9760 }, 9761 9762 /* VEX_LEN_0F59_P_1 */ 9763 { 9764 { VEX_W_TABLE (VEX_W_0F59_P_1) }, 9765 { VEX_W_TABLE (VEX_W_0F59_P_1) }, 9766 }, 9767 9768 /* VEX_LEN_0F59_P_3 */ 9769 { 9770 { VEX_W_TABLE (VEX_W_0F59_P_3) }, 9771 { VEX_W_TABLE (VEX_W_0F59_P_3) }, 9772 }, 9773 9774 /* VEX_LEN_0F5A_P_1 */ 9775 { 9776 { VEX_W_TABLE (VEX_W_0F5A_P_1) }, 9777 { VEX_W_TABLE (VEX_W_0F5A_P_1) }, 9778 }, 9779 9780 /* VEX_LEN_0F5A_P_3 */ 9781 { 9782 { VEX_W_TABLE (VEX_W_0F5A_P_3) }, 9783 { VEX_W_TABLE (VEX_W_0F5A_P_3) }, 9784 }, 9785 9786 /* VEX_LEN_0F5C_P_1 */ 9787 { 9788 { VEX_W_TABLE (VEX_W_0F5C_P_1) }, 9789 { VEX_W_TABLE (VEX_W_0F5C_P_1) }, 9790 }, 9791 9792 /* VEX_LEN_0F5C_P_3 */ 9793 { 9794 { VEX_W_TABLE (VEX_W_0F5C_P_3) }, 9795 { VEX_W_TABLE (VEX_W_0F5C_P_3) }, 9796 }, 9797 9798 /* VEX_LEN_0F5D_P_1 */ 9799 { 9800 { VEX_W_TABLE (VEX_W_0F5D_P_1) }, 9801 { VEX_W_TABLE (VEX_W_0F5D_P_1) }, 9802 }, 9803 9804 /* VEX_LEN_0F5D_P_3 */ 9805 { 9806 { VEX_W_TABLE (VEX_W_0F5D_P_3) }, 9807 { VEX_W_TABLE (VEX_W_0F5D_P_3) }, 9808 }, 9809 9810 /* VEX_LEN_0F5E_P_1 */ 9811 { 9812 { VEX_W_TABLE (VEX_W_0F5E_P_1) }, 9813 { VEX_W_TABLE (VEX_W_0F5E_P_1) }, 9814 }, 9815 9816 /* VEX_LEN_0F5E_P_3 */ 9817 { 9818 { VEX_W_TABLE (VEX_W_0F5E_P_3) }, 9819 { VEX_W_TABLE (VEX_W_0F5E_P_3) }, 9820 }, 9821 9822 /* VEX_LEN_0F5F_P_1 */ 9823 { 9824 { VEX_W_TABLE (VEX_W_0F5F_P_1) }, 9825 { VEX_W_TABLE (VEX_W_0F5F_P_1) }, 9826 }, 9827 9828 /* VEX_LEN_0F5F_P_3 */ 9829 { 9830 { VEX_W_TABLE (VEX_W_0F5F_P_3) }, 9831 { VEX_W_TABLE (VEX_W_0F5F_P_3) }, 9832 }, 9833 9834 /* VEX_LEN_0F6E_P_2 */ 9835 { 9836 { "vmovK", { XMScalar, Edq }, 0 }, 9837 { "vmovK", { XMScalar, Edq }, 0 }, 9838 }, 9839 9840 /* VEX_LEN_0F7E_P_1 */ 9841 { 9842 { VEX_W_TABLE (VEX_W_0F7E_P_1) }, 9843 { VEX_W_TABLE (VEX_W_0F7E_P_1) }, 9844 }, 9845 9846 /* VEX_LEN_0F7E_P_2 */ 9847 { 9848 { "vmovK", { Edq, XMScalar }, 0 }, 9849 { "vmovK", { Edq, XMScalar }, 0 }, 9850 }, 9851 9852 /* VEX_LEN_0F90_P_0 */ 9853 { 9854 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, 9855 }, 9856 9857 /* VEX_LEN_0F90_P_2 */ 9858 { 9859 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, 9860 }, 9861 9862 /* VEX_LEN_0F91_P_0 */ 9863 { 9864 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, 9865 }, 9866 9867 /* VEX_LEN_0F91_P_2 */ 9868 { 9869 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, 9870 }, 9871 9872 /* VEX_LEN_0F92_P_0 */ 9873 { 9874 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, 9875 }, 9876 9877 /* VEX_LEN_0F92_P_2 */ 9878 { 9879 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, 9880 }, 9881 9882 /* VEX_LEN_0F92_P_3 */ 9883 { 9884 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, 9885 }, 9886 9887 /* VEX_LEN_0F93_P_0 */ 9888 { 9889 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, 9890 }, 9891 9892 /* VEX_LEN_0F93_P_2 */ 9893 { 9894 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, 9895 }, 9896 9897 /* VEX_LEN_0F93_P_3 */ 9898 { 9899 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, 9900 }, 9901 9902 /* VEX_LEN_0F98_P_0 */ 9903 { 9904 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, 9905 }, 9906 9907 /* VEX_LEN_0F98_P_2 */ 9908 { 9909 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, 9910 }, 9911 9912 /* VEX_LEN_0F99_P_0 */ 9913 { 9914 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, 9915 }, 9916 9917 /* VEX_LEN_0F99_P_2 */ 9918 { 9919 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, 9920 }, 9921 9922 /* VEX_LEN_0FAE_R_2_M_0 */ 9923 { 9924 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, 9925 }, 9926 9927 /* VEX_LEN_0FAE_R_3_M_0 */ 9928 { 9929 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, 9930 }, 9931 9932 /* VEX_LEN_0FC2_P_1 */ 9933 { 9934 { VEX_W_TABLE (VEX_W_0FC2_P_1) }, 9935 { VEX_W_TABLE (VEX_W_0FC2_P_1) }, 9936 }, 9937 9938 /* VEX_LEN_0FC2_P_3 */ 9939 { 9940 { VEX_W_TABLE (VEX_W_0FC2_P_3) }, 9941 { VEX_W_TABLE (VEX_W_0FC2_P_3) }, 9942 }, 9943 9944 /* VEX_LEN_0FC4_P_2 */ 9945 { 9946 { VEX_W_TABLE (VEX_W_0FC4_P_2) }, 9947 }, 9948 9949 /* VEX_LEN_0FC5_P_2 */ 9950 { 9951 { VEX_W_TABLE (VEX_W_0FC5_P_2) }, 9952 }, 9953 9954 /* VEX_LEN_0FD6_P_2 */ 9955 { 9956 { VEX_W_TABLE (VEX_W_0FD6_P_2) }, 9957 { VEX_W_TABLE (VEX_W_0FD6_P_2) }, 9958 }, 9959 9960 /* VEX_LEN_0FF7_P_2 */ 9961 { 9962 { VEX_W_TABLE (VEX_W_0FF7_P_2) }, 9963 }, 9964 9965 /* VEX_LEN_0F3816_P_2 */ 9966 { 9967 { Bad_Opcode }, 9968 { VEX_W_TABLE (VEX_W_0F3816_P_2) }, 9969 }, 9970 9971 /* VEX_LEN_0F3819_P_2 */ 9972 { 9973 { Bad_Opcode }, 9974 { VEX_W_TABLE (VEX_W_0F3819_P_2) }, 9975 }, 9976 9977 /* VEX_LEN_0F381A_P_2_M_0 */ 9978 { 9979 { Bad_Opcode }, 9980 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, 9981 }, 9982 9983 /* VEX_LEN_0F3836_P_2 */ 9984 { 9985 { Bad_Opcode }, 9986 { VEX_W_TABLE (VEX_W_0F3836_P_2) }, 9987 }, 9988 9989 /* VEX_LEN_0F3841_P_2 */ 9990 { 9991 { VEX_W_TABLE (VEX_W_0F3841_P_2) }, 9992 }, 9993 9994 /* VEX_LEN_0F385A_P_2_M_0 */ 9995 { 9996 { Bad_Opcode }, 9997 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, 9998 }, 9999 10000 /* VEX_LEN_0F38DB_P_2 */ 10001 { 10002 { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, 10003 }, 10004 10005 /* VEX_LEN_0F38DC_P_2 */ 10006 { 10007 { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, 10008 }, 10009 10010 /* VEX_LEN_0F38DD_P_2 */ 10011 { 10012 { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, 10013 }, 10014 10015 /* VEX_LEN_0F38DE_P_2 */ 10016 { 10017 { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, 10018 }, 10019 10020 /* VEX_LEN_0F38DF_P_2 */ 10021 { 10022 { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, 10023 }, 10024 10025 /* VEX_LEN_0F38F2_P_0 */ 10026 { 10027 { "andnS", { Gdq, VexGdq, Edq }, 0 }, 10028 }, 10029 10030 /* VEX_LEN_0F38F3_R_1_P_0 */ 10031 { 10032 { "blsrS", { VexGdq, Edq }, 0 }, 10033 }, 10034 10035 /* VEX_LEN_0F38F3_R_2_P_0 */ 10036 { 10037 { "blsmskS", { VexGdq, Edq }, 0 }, 10038 }, 10039 10040 /* VEX_LEN_0F38F3_R_3_P_0 */ 10041 { 10042 { "blsiS", { VexGdq, Edq }, 0 }, 10043 }, 10044 10045 /* VEX_LEN_0F38F5_P_0 */ 10046 { 10047 { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, 10048 }, 10049 10050 /* VEX_LEN_0F38F5_P_1 */ 10051 { 10052 { "pextS", { Gdq, VexGdq, Edq }, 0 }, 10053 }, 10054 10055 /* VEX_LEN_0F38F5_P_3 */ 10056 { 10057 { "pdepS", { Gdq, VexGdq, Edq }, 0 }, 10058 }, 10059 10060 /* VEX_LEN_0F38F6_P_3 */ 10061 { 10062 { "mulxS", { Gdq, VexGdq, Edq }, 0 }, 10063 }, 10064 10065 /* VEX_LEN_0F38F7_P_0 */ 10066 { 10067 { "bextrS", { Gdq, Edq, VexGdq }, 0 }, 10068 }, 10069 10070 /* VEX_LEN_0F38F7_P_1 */ 10071 { 10072 { "sarxS", { Gdq, Edq, VexGdq }, 0 }, 10073 }, 10074 10075 /* VEX_LEN_0F38F7_P_2 */ 10076 { 10077 { "shlxS", { Gdq, Edq, VexGdq }, 0 }, 10078 }, 10079 10080 /* VEX_LEN_0F38F7_P_3 */ 10081 { 10082 { "shrxS", { Gdq, Edq, VexGdq }, 0 }, 10083 }, 10084 10085 /* VEX_LEN_0F3A00_P_2 */ 10086 { 10087 { Bad_Opcode }, 10088 { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, 10089 }, 10090 10091 /* VEX_LEN_0F3A01_P_2 */ 10092 { 10093 { Bad_Opcode }, 10094 { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, 10095 }, 10096 10097 /* VEX_LEN_0F3A06_P_2 */ 10098 { 10099 { Bad_Opcode }, 10100 { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, 10101 }, 10102 10103 /* VEX_LEN_0F3A0A_P_2 */ 10104 { 10105 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, 10106 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, 10107 }, 10108 10109 /* VEX_LEN_0F3A0B_P_2 */ 10110 { 10111 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, 10112 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, 10113 }, 10114 10115 /* VEX_LEN_0F3A14_P_2 */ 10116 { 10117 { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, 10118 }, 10119 10120 /* VEX_LEN_0F3A15_P_2 */ 10121 { 10122 { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, 10123 }, 10124 10125 /* VEX_LEN_0F3A16_P_2 */ 10126 { 10127 { "vpextrK", { Edq, XM, Ib }, 0 }, 10128 }, 10129 10130 /* VEX_LEN_0F3A17_P_2 */ 10131 { 10132 { "vextractps", { Edqd, XM, Ib }, 0 }, 10133 }, 10134 10135 /* VEX_LEN_0F3A18_P_2 */ 10136 { 10137 { Bad_Opcode }, 10138 { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, 10139 }, 10140 10141 /* VEX_LEN_0F3A19_P_2 */ 10142 { 10143 { Bad_Opcode }, 10144 { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, 10145 }, 10146 10147 /* VEX_LEN_0F3A20_P_2 */ 10148 { 10149 { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, 10150 }, 10151 10152 /* VEX_LEN_0F3A21_P_2 */ 10153 { 10154 { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, 10155 }, 10156 10157 /* VEX_LEN_0F3A22_P_2 */ 10158 { 10159 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, 10160 }, 10161 10162 /* VEX_LEN_0F3A30_P_2 */ 10163 { 10164 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, 10165 }, 10166 10167 /* VEX_LEN_0F3A31_P_2 */ 10168 { 10169 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, 10170 }, 10171 10172 /* VEX_LEN_0F3A32_P_2 */ 10173 { 10174 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, 10175 }, 10176 10177 /* VEX_LEN_0F3A33_P_2 */ 10178 { 10179 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, 10180 }, 10181 10182 /* VEX_LEN_0F3A38_P_2 */ 10183 { 10184 { Bad_Opcode }, 10185 { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, 10186 }, 10187 10188 /* VEX_LEN_0F3A39_P_2 */ 10189 { 10190 { Bad_Opcode }, 10191 { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, 10192 }, 10193 10194 /* VEX_LEN_0F3A41_P_2 */ 10195 { 10196 { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, 10197 }, 10198 10199 /* VEX_LEN_0F3A44_P_2 */ 10200 { 10201 { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, 10202 }, 10203 10204 /* VEX_LEN_0F3A46_P_2 */ 10205 { 10206 { Bad_Opcode }, 10207 { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, 10208 }, 10209 10210 /* VEX_LEN_0F3A60_P_2 */ 10211 { 10212 { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, 10213 }, 10214 10215 /* VEX_LEN_0F3A61_P_2 */ 10216 { 10217 { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, 10218 }, 10219 10220 /* VEX_LEN_0F3A62_P_2 */ 10221 { 10222 { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, 10223 }, 10224 10225 /* VEX_LEN_0F3A63_P_2 */ 10226 { 10227 { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, 10228 }, 10229 10230 /* VEX_LEN_0F3A6A_P_2 */ 10231 { 10232 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, 10233 }, 10234 10235 /* VEX_LEN_0F3A6B_P_2 */ 10236 { 10237 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, 10238 }, 10239 10240 /* VEX_LEN_0F3A6E_P_2 */ 10241 { 10242 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, 10243 }, 10244 10245 /* VEX_LEN_0F3A6F_P_2 */ 10246 { 10247 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, 10248 }, 10249 10250 /* VEX_LEN_0F3A7A_P_2 */ 10251 { 10252 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, 10253 }, 10254 10255 /* VEX_LEN_0F3A7B_P_2 */ 10256 { 10257 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, 10258 }, 10259 10260 /* VEX_LEN_0F3A7E_P_2 */ 10261 { 10262 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, 10263 }, 10264 10265 /* VEX_LEN_0F3A7F_P_2 */ 10266 { 10267 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, 10268 }, 10269 10270 /* VEX_LEN_0F3ADF_P_2 */ 10271 { 10272 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, 10273 }, 10274 10275 /* VEX_LEN_0F3AF0_P_3 */ 10276 { 10277 { "rorxS", { Gdq, Edq, Ib }, 0 }, 10278 }, 10279 10280 /* VEX_LEN_0FXOP_08_CC */ 10281 { 10282 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, 10283 }, 10284 10285 /* VEX_LEN_0FXOP_08_CD */ 10286 { 10287 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, 10288 }, 10289 10290 /* VEX_LEN_0FXOP_08_CE */ 10291 { 10292 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, 10293 }, 10294 10295 /* VEX_LEN_0FXOP_08_CF */ 10296 { 10297 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, 10298 }, 10299 10300 /* VEX_LEN_0FXOP_08_EC */ 10301 { 10302 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, 10303 }, 10304 10305 /* VEX_LEN_0FXOP_08_ED */ 10306 { 10307 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, 10308 }, 10309 10310 /* VEX_LEN_0FXOP_08_EE */ 10311 { 10312 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, 10313 }, 10314 10315 /* VEX_LEN_0FXOP_08_EF */ 10316 { 10317 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, 10318 }, 10319 10320 /* VEX_LEN_0FXOP_09_80 */ 10321 { 10322 { "vfrczps", { XM, EXxmm }, 0 }, 10323 { "vfrczps", { XM, EXymmq }, 0 }, 10324 }, 10325 10326 /* VEX_LEN_0FXOP_09_81 */ 10327 { 10328 { "vfrczpd", { XM, EXxmm }, 0 }, 10329 { "vfrczpd", { XM, EXymmq }, 0 }, 10330 }, 10331 }; 10332 10333 static const struct dis386 vex_w_table[][2] = { 10334 { 10335 /* VEX_W_0F10_P_0 */ 10336 { "vmovups", { XM, EXx }, 0 }, 10337 }, 10338 { 10339 /* VEX_W_0F10_P_1 */ 10340 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, 10341 }, 10342 { 10343 /* VEX_W_0F10_P_2 */ 10344 { "vmovupd", { XM, EXx }, 0 }, 10345 }, 10346 { 10347 /* VEX_W_0F10_P_3 */ 10348 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, 10349 }, 10350 { 10351 /* VEX_W_0F11_P_0 */ 10352 { "vmovups", { EXxS, XM }, 0 }, 10353 }, 10354 { 10355 /* VEX_W_0F11_P_1 */ 10356 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, 10357 }, 10358 { 10359 /* VEX_W_0F11_P_2 */ 10360 { "vmovupd", { EXxS, XM }, 0 }, 10361 }, 10362 { 10363 /* VEX_W_0F11_P_3 */ 10364 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, 10365 }, 10366 { 10367 /* VEX_W_0F12_P_0_M_0 */ 10368 { "vmovlps", { XM, Vex128, EXq }, 0 }, 10369 }, 10370 { 10371 /* VEX_W_0F12_P_0_M_1 */ 10372 { "vmovhlps", { XM, Vex128, EXq }, 0 }, 10373 }, 10374 { 10375 /* VEX_W_0F12_P_1 */ 10376 { "vmovsldup", { XM, EXx }, 0 }, 10377 }, 10378 { 10379 /* VEX_W_0F12_P_2 */ 10380 { "vmovlpd", { XM, Vex128, EXq }, 0 }, 10381 }, 10382 { 10383 /* VEX_W_0F12_P_3 */ 10384 { "vmovddup", { XM, EXymmq }, 0 }, 10385 }, 10386 { 10387 /* VEX_W_0F13_M_0 */ 10388 { "vmovlpX", { EXq, XM }, 0 }, 10389 }, 10390 { 10391 /* VEX_W_0F14 */ 10392 { "vunpcklpX", { XM, Vex, EXx }, 0 }, 10393 }, 10394 { 10395 /* VEX_W_0F15 */ 10396 { "vunpckhpX", { XM, Vex, EXx }, 0 }, 10397 }, 10398 { 10399 /* VEX_W_0F16_P_0_M_0 */ 10400 { "vmovhps", { XM, Vex128, EXq }, 0 }, 10401 }, 10402 { 10403 /* VEX_W_0F16_P_0_M_1 */ 10404 { "vmovlhps", { XM, Vex128, EXq }, 0 }, 10405 }, 10406 { 10407 /* VEX_W_0F16_P_1 */ 10408 { "vmovshdup", { XM, EXx }, 0 }, 10409 }, 10410 { 10411 /* VEX_W_0F16_P_2 */ 10412 { "vmovhpd", { XM, Vex128, EXq }, 0 }, 10413 }, 10414 { 10415 /* VEX_W_0F17_M_0 */ 10416 { "vmovhpX", { EXq, XM }, 0 }, 10417 }, 10418 { 10419 /* VEX_W_0F28 */ 10420 { "vmovapX", { XM, EXx }, 0 }, 10421 }, 10422 { 10423 /* VEX_W_0F29 */ 10424 { "vmovapX", { EXxS, XM }, 0 }, 10425 }, 10426 { 10427 /* VEX_W_0F2B_M_0 */ 10428 { "vmovntpX", { Mx, XM }, 0 }, 10429 }, 10430 { 10431 /* VEX_W_0F2E_P_0 */ 10432 { "vucomiss", { XMScalar, EXdScalar }, 0 }, 10433 }, 10434 { 10435 /* VEX_W_0F2E_P_2 */ 10436 { "vucomisd", { XMScalar, EXqScalar }, 0 }, 10437 }, 10438 { 10439 /* VEX_W_0F2F_P_0 */ 10440 { "vcomiss", { XMScalar, EXdScalar }, 0 }, 10441 }, 10442 { 10443 /* VEX_W_0F2F_P_2 */ 10444 { "vcomisd", { XMScalar, EXqScalar }, 0 }, 10445 }, 10446 { 10447 /* VEX_W_0F41_P_0_LEN_1 */ 10448 { "kandw", { MaskG, MaskVex, MaskR }, 0 }, 10449 { "kandq", { MaskG, MaskVex, MaskR }, 0 }, 10450 }, 10451 { 10452 /* VEX_W_0F41_P_2_LEN_1 */ 10453 { "kandb", { MaskG, MaskVex, MaskR }, 0 }, 10454 { "kandd", { MaskG, MaskVex, MaskR }, 0 }, 10455 }, 10456 { 10457 /* VEX_W_0F42_P_0_LEN_1 */ 10458 { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, 10459 { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, 10460 }, 10461 { 10462 /* VEX_W_0F42_P_2_LEN_1 */ 10463 { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, 10464 { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, 10465 }, 10466 { 10467 /* VEX_W_0F44_P_0_LEN_0 */ 10468 { "knotw", { MaskG, MaskR }, 0 }, 10469 { "knotq", { MaskG, MaskR }, 0 }, 10470 }, 10471 { 10472 /* VEX_W_0F44_P_2_LEN_0 */ 10473 { "knotb", { MaskG, MaskR }, 0 }, 10474 { "knotd", { MaskG, MaskR }, 0 }, 10475 }, 10476 { 10477 /* VEX_W_0F45_P_0_LEN_1 */ 10478 { "korw", { MaskG, MaskVex, MaskR }, 0 }, 10479 { "korq", { MaskG, MaskVex, MaskR }, 0 }, 10480 }, 10481 { 10482 /* VEX_W_0F45_P_2_LEN_1 */ 10483 { "korb", { MaskG, MaskVex, MaskR }, 0 }, 10484 { "kord", { MaskG, MaskVex, MaskR }, 0 }, 10485 }, 10486 { 10487 /* VEX_W_0F46_P_0_LEN_1 */ 10488 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, 10489 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, 10490 }, 10491 { 10492 /* VEX_W_0F46_P_2_LEN_1 */ 10493 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, 10494 { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, 10495 }, 10496 { 10497 /* VEX_W_0F47_P_0_LEN_1 */ 10498 { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, 10499 { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, 10500 }, 10501 { 10502 /* VEX_W_0F47_P_2_LEN_1 */ 10503 { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, 10504 { "kxord", { MaskG, MaskVex, MaskR }, 0 }, 10505 }, 10506 { 10507 /* VEX_W_0F4A_P_0_LEN_1 */ 10508 { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, 10509 { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, 10510 }, 10511 { 10512 /* VEX_W_0F4A_P_2_LEN_1 */ 10513 { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, 10514 { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, 10515 }, 10516 { 10517 /* VEX_W_0F4B_P_0_LEN_1 */ 10518 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, 10519 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, 10520 }, 10521 { 10522 /* VEX_W_0F4B_P_2_LEN_1 */ 10523 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, 10524 }, 10525 { 10526 /* VEX_W_0F50_M_0 */ 10527 { "vmovmskpX", { Gdq, XS }, 0 }, 10528 }, 10529 { 10530 /* VEX_W_0F51_P_0 */ 10531 { "vsqrtps", { XM, EXx }, 0 }, 10532 }, 10533 { 10534 /* VEX_W_0F51_P_1 */ 10535 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10536 }, 10537 { 10538 /* VEX_W_0F51_P_2 */ 10539 { "vsqrtpd", { XM, EXx }, 0 }, 10540 }, 10541 { 10542 /* VEX_W_0F51_P_3 */ 10543 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10544 }, 10545 { 10546 /* VEX_W_0F52_P_0 */ 10547 { "vrsqrtps", { XM, EXx }, 0 }, 10548 }, 10549 { 10550 /* VEX_W_0F52_P_1 */ 10551 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10552 }, 10553 { 10554 /* VEX_W_0F53_P_0 */ 10555 { "vrcpps", { XM, EXx }, 0 }, 10556 }, 10557 { 10558 /* VEX_W_0F53_P_1 */ 10559 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10560 }, 10561 { 10562 /* VEX_W_0F58_P_0 */ 10563 { "vaddps", { XM, Vex, EXx }, 0 }, 10564 }, 10565 { 10566 /* VEX_W_0F58_P_1 */ 10567 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10568 }, 10569 { 10570 /* VEX_W_0F58_P_2 */ 10571 { "vaddpd", { XM, Vex, EXx }, 0 }, 10572 }, 10573 { 10574 /* VEX_W_0F58_P_3 */ 10575 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10576 }, 10577 { 10578 /* VEX_W_0F59_P_0 */ 10579 { "vmulps", { XM, Vex, EXx }, 0 }, 10580 }, 10581 { 10582 /* VEX_W_0F59_P_1 */ 10583 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10584 }, 10585 { 10586 /* VEX_W_0F59_P_2 */ 10587 { "vmulpd", { XM, Vex, EXx }, 0 }, 10588 }, 10589 { 10590 /* VEX_W_0F59_P_3 */ 10591 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10592 }, 10593 { 10594 /* VEX_W_0F5A_P_0 */ 10595 { "vcvtps2pd", { XM, EXxmmq }, 0 }, 10596 }, 10597 { 10598 /* VEX_W_0F5A_P_1 */ 10599 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, 10600 }, 10601 { 10602 /* VEX_W_0F5A_P_3 */ 10603 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, 10604 }, 10605 { 10606 /* VEX_W_0F5B_P_0 */ 10607 { "vcvtdq2ps", { XM, EXx }, 0 }, 10608 }, 10609 { 10610 /* VEX_W_0F5B_P_1 */ 10611 { "vcvttps2dq", { XM, EXx }, 0 }, 10612 }, 10613 { 10614 /* VEX_W_0F5B_P_2 */ 10615 { "vcvtps2dq", { XM, EXx }, 0 }, 10616 }, 10617 { 10618 /* VEX_W_0F5C_P_0 */ 10619 { "vsubps", { XM, Vex, EXx }, 0 }, 10620 }, 10621 { 10622 /* VEX_W_0F5C_P_1 */ 10623 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10624 }, 10625 { 10626 /* VEX_W_0F5C_P_2 */ 10627 { "vsubpd", { XM, Vex, EXx }, 0 }, 10628 }, 10629 { 10630 /* VEX_W_0F5C_P_3 */ 10631 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10632 }, 10633 { 10634 /* VEX_W_0F5D_P_0 */ 10635 { "vminps", { XM, Vex, EXx }, 0 }, 10636 }, 10637 { 10638 /* VEX_W_0F5D_P_1 */ 10639 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10640 }, 10641 { 10642 /* VEX_W_0F5D_P_2 */ 10643 { "vminpd", { XM, Vex, EXx }, 0 }, 10644 }, 10645 { 10646 /* VEX_W_0F5D_P_3 */ 10647 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10648 }, 10649 { 10650 /* VEX_W_0F5E_P_0 */ 10651 { "vdivps", { XM, Vex, EXx }, 0 }, 10652 }, 10653 { 10654 /* VEX_W_0F5E_P_1 */ 10655 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10656 }, 10657 { 10658 /* VEX_W_0F5E_P_2 */ 10659 { "vdivpd", { XM, Vex, EXx }, 0 }, 10660 }, 10661 { 10662 /* VEX_W_0F5E_P_3 */ 10663 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10664 }, 10665 { 10666 /* VEX_W_0F5F_P_0 */ 10667 { "vmaxps", { XM, Vex, EXx }, 0 }, 10668 }, 10669 { 10670 /* VEX_W_0F5F_P_1 */ 10671 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, 10672 }, 10673 { 10674 /* VEX_W_0F5F_P_2 */ 10675 { "vmaxpd", { XM, Vex, EXx }, 0 }, 10676 }, 10677 { 10678 /* VEX_W_0F5F_P_3 */ 10679 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, 10680 }, 10681 { 10682 /* VEX_W_0F60_P_2 */ 10683 { "vpunpcklbw", { XM, Vex, EXx }, 0 }, 10684 }, 10685 { 10686 /* VEX_W_0F61_P_2 */ 10687 { "vpunpcklwd", { XM, Vex, EXx }, 0 }, 10688 }, 10689 { 10690 /* VEX_W_0F62_P_2 */ 10691 { "vpunpckldq", { XM, Vex, EXx }, 0 }, 10692 }, 10693 { 10694 /* VEX_W_0F63_P_2 */ 10695 { "vpacksswb", { XM, Vex, EXx }, 0 }, 10696 }, 10697 { 10698 /* VEX_W_0F64_P_2 */ 10699 { "vpcmpgtb", { XM, Vex, EXx }, 0 }, 10700 }, 10701 { 10702 /* VEX_W_0F65_P_2 */ 10703 { "vpcmpgtw", { XM, Vex, EXx }, 0 }, 10704 }, 10705 { 10706 /* VEX_W_0F66_P_2 */ 10707 { "vpcmpgtd", { XM, Vex, EXx }, 0 }, 10708 }, 10709 { 10710 /* VEX_W_0F67_P_2 */ 10711 { "vpackuswb", { XM, Vex, EXx }, 0 }, 10712 }, 10713 { 10714 /* VEX_W_0F68_P_2 */ 10715 { "vpunpckhbw", { XM, Vex, EXx }, 0 }, 10716 }, 10717 { 10718 /* VEX_W_0F69_P_2 */ 10719 { "vpunpckhwd", { XM, Vex, EXx }, 0 }, 10720 }, 10721 { 10722 /* VEX_W_0F6A_P_2 */ 10723 { "vpunpckhdq", { XM, Vex, EXx }, 0 }, 10724 }, 10725 { 10726 /* VEX_W_0F6B_P_2 */ 10727 { "vpackssdw", { XM, Vex, EXx }, 0 }, 10728 }, 10729 { 10730 /* VEX_W_0F6C_P_2 */ 10731 { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, 10732 }, 10733 { 10734 /* VEX_W_0F6D_P_2 */ 10735 { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, 10736 }, 10737 { 10738 /* VEX_W_0F6F_P_1 */ 10739 { "vmovdqu", { XM, EXx }, 0 }, 10740 }, 10741 { 10742 /* VEX_W_0F6F_P_2 */ 10743 { "vmovdqa", { XM, EXx }, 0 }, 10744 }, 10745 { 10746 /* VEX_W_0F70_P_1 */ 10747 { "vpshufhw", { XM, EXx, Ib }, 0 }, 10748 }, 10749 { 10750 /* VEX_W_0F70_P_2 */ 10751 { "vpshufd", { XM, EXx, Ib }, 0 }, 10752 }, 10753 { 10754 /* VEX_W_0F70_P_3 */ 10755 { "vpshuflw", { XM, EXx, Ib }, 0 }, 10756 }, 10757 { 10758 /* VEX_W_0F71_R_2_P_2 */ 10759 { "vpsrlw", { Vex, XS, Ib }, 0 }, 10760 }, 10761 { 10762 /* VEX_W_0F71_R_4_P_2 */ 10763 { "vpsraw", { Vex, XS, Ib }, 0 }, 10764 }, 10765 { 10766 /* VEX_W_0F71_R_6_P_2 */ 10767 { "vpsllw", { Vex, XS, Ib }, 0 }, 10768 }, 10769 { 10770 /* VEX_W_0F72_R_2_P_2 */ 10771 { "vpsrld", { Vex, XS, Ib }, 0 }, 10772 }, 10773 { 10774 /* VEX_W_0F72_R_4_P_2 */ 10775 { "vpsrad", { Vex, XS, Ib }, 0 }, 10776 }, 10777 { 10778 /* VEX_W_0F72_R_6_P_2 */ 10779 { "vpslld", { Vex, XS, Ib }, 0 }, 10780 }, 10781 { 10782 /* VEX_W_0F73_R_2_P_2 */ 10783 { "vpsrlq", { Vex, XS, Ib }, 0 }, 10784 }, 10785 { 10786 /* VEX_W_0F73_R_3_P_2 */ 10787 { "vpsrldq", { Vex, XS, Ib }, 0 }, 10788 }, 10789 { 10790 /* VEX_W_0F73_R_6_P_2 */ 10791 { "vpsllq", { Vex, XS, Ib }, 0 }, 10792 }, 10793 { 10794 /* VEX_W_0F73_R_7_P_2 */ 10795 { "vpslldq", { Vex, XS, Ib }, 0 }, 10796 }, 10797 { 10798 /* VEX_W_0F74_P_2 */ 10799 { "vpcmpeqb", { XM, Vex, EXx }, 0 }, 10800 }, 10801 { 10802 /* VEX_W_0F75_P_2 */ 10803 { "vpcmpeqw", { XM, Vex, EXx }, 0 }, 10804 }, 10805 { 10806 /* VEX_W_0F76_P_2 */ 10807 { "vpcmpeqd", { XM, Vex, EXx }, 0 }, 10808 }, 10809 { 10810 /* VEX_W_0F77_P_0 */ 10811 { "", { VZERO }, 0 }, 10812 }, 10813 { 10814 /* VEX_W_0F7C_P_2 */ 10815 { "vhaddpd", { XM, Vex, EXx }, 0 }, 10816 }, 10817 { 10818 /* VEX_W_0F7C_P_3 */ 10819 { "vhaddps", { XM, Vex, EXx }, 0 }, 10820 }, 10821 { 10822 /* VEX_W_0F7D_P_2 */ 10823 { "vhsubpd", { XM, Vex, EXx }, 0 }, 10824 }, 10825 { 10826 /* VEX_W_0F7D_P_3 */ 10827 { "vhsubps", { XM, Vex, EXx }, 0 }, 10828 }, 10829 { 10830 /* VEX_W_0F7E_P_1 */ 10831 { "vmovq", { XMScalar, EXqScalar }, 0 }, 10832 }, 10833 { 10834 /* VEX_W_0F7F_P_1 */ 10835 { "vmovdqu", { EXxS, XM }, 0 }, 10836 }, 10837 { 10838 /* VEX_W_0F7F_P_2 */ 10839 { "vmovdqa", { EXxS, XM }, 0 }, 10840 }, 10841 { 10842 /* VEX_W_0F90_P_0_LEN_0 */ 10843 { "kmovw", { MaskG, MaskE }, 0 }, 10844 { "kmovq", { MaskG, MaskE }, 0 }, 10845 }, 10846 { 10847 /* VEX_W_0F90_P_2_LEN_0 */ 10848 { "kmovb", { MaskG, MaskBDE }, 0 }, 10849 { "kmovd", { MaskG, MaskBDE }, 0 }, 10850 }, 10851 { 10852 /* VEX_W_0F91_P_0_LEN_0 */ 10853 { "kmovw", { Ew, MaskG }, 0 }, 10854 { "kmovq", { Eq, MaskG }, 0 }, 10855 }, 10856 { 10857 /* VEX_W_0F91_P_2_LEN_0 */ 10858 { "kmovb", { Eb, MaskG }, 0 }, 10859 { "kmovd", { Ed, MaskG }, 0 }, 10860 }, 10861 { 10862 /* VEX_W_0F92_P_0_LEN_0 */ 10863 { "kmovw", { MaskG, Rdq }, 0 }, 10864 }, 10865 { 10866 /* VEX_W_0F92_P_2_LEN_0 */ 10867 { "kmovb", { MaskG, Rdq }, 0 }, 10868 }, 10869 { 10870 /* VEX_W_0F92_P_3_LEN_0 */ 10871 { "kmovd", { MaskG, Rdq }, 0 }, 10872 { "kmovq", { MaskG, Rdq }, 0 }, 10873 }, 10874 { 10875 /* VEX_W_0F93_P_0_LEN_0 */ 10876 { "kmovw", { Gdq, MaskR }, 0 }, 10877 }, 10878 { 10879 /* VEX_W_0F93_P_2_LEN_0 */ 10880 { "kmovb", { Gdq, MaskR }, 0 }, 10881 }, 10882 { 10883 /* VEX_W_0F93_P_3_LEN_0 */ 10884 { "kmovd", { Gdq, MaskR }, 0 }, 10885 { "kmovq", { Gdq, MaskR }, 0 }, 10886 }, 10887 { 10888 /* VEX_W_0F98_P_0_LEN_0 */ 10889 { "kortestw", { MaskG, MaskR }, 0 }, 10890 { "kortestq", { MaskG, MaskR }, 0 }, 10891 }, 10892 { 10893 /* VEX_W_0F98_P_2_LEN_0 */ 10894 { "kortestb", { MaskG, MaskR }, 0 }, 10895 { "kortestd", { MaskG, MaskR }, 0 }, 10896 }, 10897 { 10898 /* VEX_W_0F99_P_0_LEN_0 */ 10899 { "ktestw", { MaskG, MaskR }, 0 }, 10900 { "ktestq", { MaskG, MaskR }, 0 }, 10901 }, 10902 { 10903 /* VEX_W_0F99_P_2_LEN_0 */ 10904 { "ktestb", { MaskG, MaskR }, 0 }, 10905 { "ktestd", { MaskG, MaskR }, 0 }, 10906 }, 10907 { 10908 /* VEX_W_0FAE_R_2_M_0 */ 10909 { "vldmxcsr", { Md }, 0 }, 10910 }, 10911 { 10912 /* VEX_W_0FAE_R_3_M_0 */ 10913 { "vstmxcsr", { Md }, 0 }, 10914 }, 10915 { 10916 /* VEX_W_0FC2_P_0 */ 10917 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, 10918 }, 10919 { 10920 /* VEX_W_0FC2_P_1 */ 10921 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, 10922 }, 10923 { 10924 /* VEX_W_0FC2_P_2 */ 10925 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, 10926 }, 10927 { 10928 /* VEX_W_0FC2_P_3 */ 10929 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, 10930 }, 10931 { 10932 /* VEX_W_0FC4_P_2 */ 10933 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, 10934 }, 10935 { 10936 /* VEX_W_0FC5_P_2 */ 10937 { "vpextrw", { Gdq, XS, Ib }, 0 }, 10938 }, 10939 { 10940 /* VEX_W_0FD0_P_2 */ 10941 { "vaddsubpd", { XM, Vex, EXx }, 0 }, 10942 }, 10943 { 10944 /* VEX_W_0FD0_P_3 */ 10945 { "vaddsubps", { XM, Vex, EXx }, 0 }, 10946 }, 10947 { 10948 /* VEX_W_0FD1_P_2 */ 10949 { "vpsrlw", { XM, Vex, EXxmm }, 0 }, 10950 }, 10951 { 10952 /* VEX_W_0FD2_P_2 */ 10953 { "vpsrld", { XM, Vex, EXxmm }, 0 }, 10954 }, 10955 { 10956 /* VEX_W_0FD3_P_2 */ 10957 { "vpsrlq", { XM, Vex, EXxmm }, 0 }, 10958 }, 10959 { 10960 /* VEX_W_0FD4_P_2 */ 10961 { "vpaddq", { XM, Vex, EXx }, 0 }, 10962 }, 10963 { 10964 /* VEX_W_0FD5_P_2 */ 10965 { "vpmullw", { XM, Vex, EXx }, 0 }, 10966 }, 10967 { 10968 /* VEX_W_0FD6_P_2 */ 10969 { "vmovq", { EXqScalarS, XMScalar }, 0 }, 10970 }, 10971 { 10972 /* VEX_W_0FD7_P_2_M_1 */ 10973 { "vpmovmskb", { Gdq, XS }, 0 }, 10974 }, 10975 { 10976 /* VEX_W_0FD8_P_2 */ 10977 { "vpsubusb", { XM, Vex, EXx }, 0 }, 10978 }, 10979 { 10980 /* VEX_W_0FD9_P_2 */ 10981 { "vpsubusw", { XM, Vex, EXx }, 0 }, 10982 }, 10983 { 10984 /* VEX_W_0FDA_P_2 */ 10985 { "vpminub", { XM, Vex, EXx }, 0 }, 10986 }, 10987 { 10988 /* VEX_W_0FDB_P_2 */ 10989 { "vpand", { XM, Vex, EXx }, 0 }, 10990 }, 10991 { 10992 /* VEX_W_0FDC_P_2 */ 10993 { "vpaddusb", { XM, Vex, EXx }, 0 }, 10994 }, 10995 { 10996 /* VEX_W_0FDD_P_2 */ 10997 { "vpaddusw", { XM, Vex, EXx }, 0 }, 10998 }, 10999 { 11000 /* VEX_W_0FDE_P_2 */ 11001 { "vpmaxub", { XM, Vex, EXx }, 0 }, 11002 }, 11003 { 11004 /* VEX_W_0FDF_P_2 */ 11005 { "vpandn", { XM, Vex, EXx }, 0 }, 11006 }, 11007 { 11008 /* VEX_W_0FE0_P_2 */ 11009 { "vpavgb", { XM, Vex, EXx }, 0 }, 11010 }, 11011 { 11012 /* VEX_W_0FE1_P_2 */ 11013 { "vpsraw", { XM, Vex, EXxmm }, 0 }, 11014 }, 11015 { 11016 /* VEX_W_0FE2_P_2 */ 11017 { "vpsrad", { XM, Vex, EXxmm }, 0 }, 11018 }, 11019 { 11020 /* VEX_W_0FE3_P_2 */ 11021 { "vpavgw", { XM, Vex, EXx }, 0 }, 11022 }, 11023 { 11024 /* VEX_W_0FE4_P_2 */ 11025 { "vpmulhuw", { XM, Vex, EXx }, 0 }, 11026 }, 11027 { 11028 /* VEX_W_0FE5_P_2 */ 11029 { "vpmulhw", { XM, Vex, EXx }, 0 }, 11030 }, 11031 { 11032 /* VEX_W_0FE6_P_1 */ 11033 { "vcvtdq2pd", { XM, EXxmmq }, 0 }, 11034 }, 11035 { 11036 /* VEX_W_0FE6_P_2 */ 11037 { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, 11038 }, 11039 { 11040 /* VEX_W_0FE6_P_3 */ 11041 { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, 11042 }, 11043 { 11044 /* VEX_W_0FE7_P_2_M_0 */ 11045 { "vmovntdq", { Mx, XM }, 0 }, 11046 }, 11047 { 11048 /* VEX_W_0FE8_P_2 */ 11049 { "vpsubsb", { XM, Vex, EXx }, 0 }, 11050 }, 11051 { 11052 /* VEX_W_0FE9_P_2 */ 11053 { "vpsubsw", { XM, Vex, EXx }, 0 }, 11054 }, 11055 { 11056 /* VEX_W_0FEA_P_2 */ 11057 { "vpminsw", { XM, Vex, EXx }, 0 }, 11058 }, 11059 { 11060 /* VEX_W_0FEB_P_2 */ 11061 { "vpor", { XM, Vex, EXx }, 0 }, 11062 }, 11063 { 11064 /* VEX_W_0FEC_P_2 */ 11065 { "vpaddsb", { XM, Vex, EXx }, 0 }, 11066 }, 11067 { 11068 /* VEX_W_0FED_P_2 */ 11069 { "vpaddsw", { XM, Vex, EXx }, 0 }, 11070 }, 11071 { 11072 /* VEX_W_0FEE_P_2 */ 11073 { "vpmaxsw", { XM, Vex, EXx }, 0 }, 11074 }, 11075 { 11076 /* VEX_W_0FEF_P_2 */ 11077 { "vpxor", { XM, Vex, EXx }, 0 }, 11078 }, 11079 { 11080 /* VEX_W_0FF0_P_3_M_0 */ 11081 { "vlddqu", { XM, M }, 0 }, 11082 }, 11083 { 11084 /* VEX_W_0FF1_P_2 */ 11085 { "vpsllw", { XM, Vex, EXxmm }, 0 }, 11086 }, 11087 { 11088 /* VEX_W_0FF2_P_2 */ 11089 { "vpslld", { XM, Vex, EXxmm }, 0 }, 11090 }, 11091 { 11092 /* VEX_W_0FF3_P_2 */ 11093 { "vpsllq", { XM, Vex, EXxmm }, 0 }, 11094 }, 11095 { 11096 /* VEX_W_0FF4_P_2 */ 11097 { "vpmuludq", { XM, Vex, EXx }, 0 }, 11098 }, 11099 { 11100 /* VEX_W_0FF5_P_2 */ 11101 { "vpmaddwd", { XM, Vex, EXx }, 0 }, 11102 }, 11103 { 11104 /* VEX_W_0FF6_P_2 */ 11105 { "vpsadbw", { XM, Vex, EXx }, 0 }, 11106 }, 11107 { 11108 /* VEX_W_0FF7_P_2 */ 11109 { "vmaskmovdqu", { XM, XS }, 0 }, 11110 }, 11111 { 11112 /* VEX_W_0FF8_P_2 */ 11113 { "vpsubb", { XM, Vex, EXx }, 0 }, 11114 }, 11115 { 11116 /* VEX_W_0FF9_P_2 */ 11117 { "vpsubw", { XM, Vex, EXx }, 0 }, 11118 }, 11119 { 11120 /* VEX_W_0FFA_P_2 */ 11121 { "vpsubd", { XM, Vex, EXx }, 0 }, 11122 }, 11123 { 11124 /* VEX_W_0FFB_P_2 */ 11125 { "vpsubq", { XM, Vex, EXx }, 0 }, 11126 }, 11127 { 11128 /* VEX_W_0FFC_P_2 */ 11129 { "vpaddb", { XM, Vex, EXx }, 0 }, 11130 }, 11131 { 11132 /* VEX_W_0FFD_P_2 */ 11133 { "vpaddw", { XM, Vex, EXx }, 0 }, 11134 }, 11135 { 11136 /* VEX_W_0FFE_P_2 */ 11137 { "vpaddd", { XM, Vex, EXx }, 0 }, 11138 }, 11139 { 11140 /* VEX_W_0F3800_P_2 */ 11141 { "vpshufb", { XM, Vex, EXx }, 0 }, 11142 }, 11143 { 11144 /* VEX_W_0F3801_P_2 */ 11145 { "vphaddw", { XM, Vex, EXx }, 0 }, 11146 }, 11147 { 11148 /* VEX_W_0F3802_P_2 */ 11149 { "vphaddd", { XM, Vex, EXx }, 0 }, 11150 }, 11151 { 11152 /* VEX_W_0F3803_P_2 */ 11153 { "vphaddsw", { XM, Vex, EXx }, 0 }, 11154 }, 11155 { 11156 /* VEX_W_0F3804_P_2 */ 11157 { "vpmaddubsw", { XM, Vex, EXx }, 0 }, 11158 }, 11159 { 11160 /* VEX_W_0F3805_P_2 */ 11161 { "vphsubw", { XM, Vex, EXx }, 0 }, 11162 }, 11163 { 11164 /* VEX_W_0F3806_P_2 */ 11165 { "vphsubd", { XM, Vex, EXx }, 0 }, 11166 }, 11167 { 11168 /* VEX_W_0F3807_P_2 */ 11169 { "vphsubsw", { XM, Vex, EXx }, 0 }, 11170 }, 11171 { 11172 /* VEX_W_0F3808_P_2 */ 11173 { "vpsignb", { XM, Vex, EXx }, 0 }, 11174 }, 11175 { 11176 /* VEX_W_0F3809_P_2 */ 11177 { "vpsignw", { XM, Vex, EXx }, 0 }, 11178 }, 11179 { 11180 /* VEX_W_0F380A_P_2 */ 11181 { "vpsignd", { XM, Vex, EXx }, 0 }, 11182 }, 11183 { 11184 /* VEX_W_0F380B_P_2 */ 11185 { "vpmulhrsw", { XM, Vex, EXx }, 0 }, 11186 }, 11187 { 11188 /* VEX_W_0F380C_P_2 */ 11189 { "vpermilps", { XM, Vex, EXx }, 0 }, 11190 }, 11191 { 11192 /* VEX_W_0F380D_P_2 */ 11193 { "vpermilpd", { XM, Vex, EXx }, 0 }, 11194 }, 11195 { 11196 /* VEX_W_0F380E_P_2 */ 11197 { "vtestps", { XM, EXx }, 0 }, 11198 }, 11199 { 11200 /* VEX_W_0F380F_P_2 */ 11201 { "vtestpd", { XM, EXx }, 0 }, 11202 }, 11203 { 11204 /* VEX_W_0F3816_P_2 */ 11205 { "vpermps", { XM, Vex, EXx }, 0 }, 11206 }, 11207 { 11208 /* VEX_W_0F3817_P_2 */ 11209 { "vptest", { XM, EXx }, 0 }, 11210 }, 11211 { 11212 /* VEX_W_0F3818_P_2 */ 11213 { "vbroadcastss", { XM, EXxmm_md }, 0 }, 11214 }, 11215 { 11216 /* VEX_W_0F3819_P_2 */ 11217 { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, 11218 }, 11219 { 11220 /* VEX_W_0F381A_P_2_M_0 */ 11221 { "vbroadcastf128", { XM, Mxmm }, 0 }, 11222 }, 11223 { 11224 /* VEX_W_0F381C_P_2 */ 11225 { "vpabsb", { XM, EXx }, 0 }, 11226 }, 11227 { 11228 /* VEX_W_0F381D_P_2 */ 11229 { "vpabsw", { XM, EXx }, 0 }, 11230 }, 11231 { 11232 /* VEX_W_0F381E_P_2 */ 11233 { "vpabsd", { XM, EXx }, 0 }, 11234 }, 11235 { 11236 /* VEX_W_0F3820_P_2 */ 11237 { "vpmovsxbw", { XM, EXxmmq }, 0 }, 11238 }, 11239 { 11240 /* VEX_W_0F3821_P_2 */ 11241 { "vpmovsxbd", { XM, EXxmmqd }, 0 }, 11242 }, 11243 { 11244 /* VEX_W_0F3822_P_2 */ 11245 { "vpmovsxbq", { XM, EXxmmdw }, 0 }, 11246 }, 11247 { 11248 /* VEX_W_0F3823_P_2 */ 11249 { "vpmovsxwd", { XM, EXxmmq }, 0 }, 11250 }, 11251 { 11252 /* VEX_W_0F3824_P_2 */ 11253 { "vpmovsxwq", { XM, EXxmmqd }, 0 }, 11254 }, 11255 { 11256 /* VEX_W_0F3825_P_2 */ 11257 { "vpmovsxdq", { XM, EXxmmq }, 0 }, 11258 }, 11259 { 11260 /* VEX_W_0F3828_P_2 */ 11261 { "vpmuldq", { XM, Vex, EXx }, 0 }, 11262 }, 11263 { 11264 /* VEX_W_0F3829_P_2 */ 11265 { "vpcmpeqq", { XM, Vex, EXx }, 0 }, 11266 }, 11267 { 11268 /* VEX_W_0F382A_P_2_M_0 */ 11269 { "vmovntdqa", { XM, Mx }, 0 }, 11270 }, 11271 { 11272 /* VEX_W_0F382B_P_2 */ 11273 { "vpackusdw", { XM, Vex, EXx }, 0 }, 11274 }, 11275 { 11276 /* VEX_W_0F382C_P_2_M_0 */ 11277 { "vmaskmovps", { XM, Vex, Mx }, 0 }, 11278 }, 11279 { 11280 /* VEX_W_0F382D_P_2_M_0 */ 11281 { "vmaskmovpd", { XM, Vex, Mx }, 0 }, 11282 }, 11283 { 11284 /* VEX_W_0F382E_P_2_M_0 */ 11285 { "vmaskmovps", { Mx, Vex, XM }, 0 }, 11286 }, 11287 { 11288 /* VEX_W_0F382F_P_2_M_0 */ 11289 { "vmaskmovpd", { Mx, Vex, XM }, 0 }, 11290 }, 11291 { 11292 /* VEX_W_0F3830_P_2 */ 11293 { "vpmovzxbw", { XM, EXxmmq }, 0 }, 11294 }, 11295 { 11296 /* VEX_W_0F3831_P_2 */ 11297 { "vpmovzxbd", { XM, EXxmmqd }, 0 }, 11298 }, 11299 { 11300 /* VEX_W_0F3832_P_2 */ 11301 { "vpmovzxbq", { XM, EXxmmdw }, 0 }, 11302 }, 11303 { 11304 /* VEX_W_0F3833_P_2 */ 11305 { "vpmovzxwd", { XM, EXxmmq }, 0 }, 11306 }, 11307 { 11308 /* VEX_W_0F3834_P_2 */ 11309 { "vpmovzxwq", { XM, EXxmmqd }, 0 }, 11310 }, 11311 { 11312 /* VEX_W_0F3835_P_2 */ 11313 { "vpmovzxdq", { XM, EXxmmq }, 0 }, 11314 }, 11315 { 11316 /* VEX_W_0F3836_P_2 */ 11317 { "vpermd", { XM, Vex, EXx }, 0 }, 11318 }, 11319 { 11320 /* VEX_W_0F3837_P_2 */ 11321 { "vpcmpgtq", { XM, Vex, EXx }, 0 }, 11322 }, 11323 { 11324 /* VEX_W_0F3838_P_2 */ 11325 { "vpminsb", { XM, Vex, EXx }, 0 }, 11326 }, 11327 { 11328 /* VEX_W_0F3839_P_2 */ 11329 { "vpminsd", { XM, Vex, EXx }, 0 }, 11330 }, 11331 { 11332 /* VEX_W_0F383A_P_2 */ 11333 { "vpminuw", { XM, Vex, EXx }, 0 }, 11334 }, 11335 { 11336 /* VEX_W_0F383B_P_2 */ 11337 { "vpminud", { XM, Vex, EXx }, 0 }, 11338 }, 11339 { 11340 /* VEX_W_0F383C_P_2 */ 11341 { "vpmaxsb", { XM, Vex, EXx }, 0 }, 11342 }, 11343 { 11344 /* VEX_W_0F383D_P_2 */ 11345 { "vpmaxsd", { XM, Vex, EXx }, 0 }, 11346 }, 11347 { 11348 /* VEX_W_0F383E_P_2 */ 11349 { "vpmaxuw", { XM, Vex, EXx }, 0 }, 11350 }, 11351 { 11352 /* VEX_W_0F383F_P_2 */ 11353 { "vpmaxud", { XM, Vex, EXx }, 0 }, 11354 }, 11355 { 11356 /* VEX_W_0F3840_P_2 */ 11357 { "vpmulld", { XM, Vex, EXx }, 0 }, 11358 }, 11359 { 11360 /* VEX_W_0F3841_P_2 */ 11361 { "vphminposuw", { XM, EXx }, 0 }, 11362 }, 11363 { 11364 /* VEX_W_0F3846_P_2 */ 11365 { "vpsravd", { XM, Vex, EXx }, 0 }, 11366 }, 11367 { 11368 /* VEX_W_0F3858_P_2 */ 11369 { "vpbroadcastd", { XM, EXxmm_md }, 0 }, 11370 }, 11371 { 11372 /* VEX_W_0F3859_P_2 */ 11373 { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, 11374 }, 11375 { 11376 /* VEX_W_0F385A_P_2_M_0 */ 11377 { "vbroadcasti128", { XM, Mxmm }, 0 }, 11378 }, 11379 { 11380 /* VEX_W_0F3878_P_2 */ 11381 { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, 11382 }, 11383 { 11384 /* VEX_W_0F3879_P_2 */ 11385 { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, 11386 }, 11387 { 11388 /* VEX_W_0F38DB_P_2 */ 11389 { "vaesimc", { XM, EXx }, 0 }, 11390 }, 11391 { 11392 /* VEX_W_0F38DC_P_2 */ 11393 { "vaesenc", { XM, Vex128, EXx }, 0 }, 11394 }, 11395 { 11396 /* VEX_W_0F38DD_P_2 */ 11397 { "vaesenclast", { XM, Vex128, EXx }, 0 }, 11398 }, 11399 { 11400 /* VEX_W_0F38DE_P_2 */ 11401 { "vaesdec", { XM, Vex128, EXx }, 0 }, 11402 }, 11403 { 11404 /* VEX_W_0F38DF_P_2 */ 11405 { "vaesdeclast", { XM, Vex128, EXx }, 0 }, 11406 }, 11407 { 11408 /* VEX_W_0F3A00_P_2 */ 11409 { Bad_Opcode }, 11410 { "vpermq", { XM, EXx, Ib }, 0 }, 11411 }, 11412 { 11413 /* VEX_W_0F3A01_P_2 */ 11414 { Bad_Opcode }, 11415 { "vpermpd", { XM, EXx, Ib }, 0 }, 11416 }, 11417 { 11418 /* VEX_W_0F3A02_P_2 */ 11419 { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, 11420 }, 11421 { 11422 /* VEX_W_0F3A04_P_2 */ 11423 { "vpermilps", { XM, EXx, Ib }, 0 }, 11424 }, 11425 { 11426 /* VEX_W_0F3A05_P_2 */ 11427 { "vpermilpd", { XM, EXx, Ib }, 0 }, 11428 }, 11429 { 11430 /* VEX_W_0F3A06_P_2 */ 11431 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, 11432 }, 11433 { 11434 /* VEX_W_0F3A08_P_2 */ 11435 { "vroundps", { XM, EXx, Ib }, 0 }, 11436 }, 11437 { 11438 /* VEX_W_0F3A09_P_2 */ 11439 { "vroundpd", { XM, EXx, Ib }, 0 }, 11440 }, 11441 { 11442 /* VEX_W_0F3A0A_P_2 */ 11443 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, 11444 }, 11445 { 11446 /* VEX_W_0F3A0B_P_2 */ 11447 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, 11448 }, 11449 { 11450 /* VEX_W_0F3A0C_P_2 */ 11451 { "vblendps", { XM, Vex, EXx, Ib }, 0 }, 11452 }, 11453 { 11454 /* VEX_W_0F3A0D_P_2 */ 11455 { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, 11456 }, 11457 { 11458 /* VEX_W_0F3A0E_P_2 */ 11459 { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, 11460 }, 11461 { 11462 /* VEX_W_0F3A0F_P_2 */ 11463 { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, 11464 }, 11465 { 11466 /* VEX_W_0F3A14_P_2 */ 11467 { "vpextrb", { Edqb, XM, Ib }, 0 }, 11468 }, 11469 { 11470 /* VEX_W_0F3A15_P_2 */ 11471 { "vpextrw", { Edqw, XM, Ib }, 0 }, 11472 }, 11473 { 11474 /* VEX_W_0F3A18_P_2 */ 11475 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, 11476 }, 11477 { 11478 /* VEX_W_0F3A19_P_2 */ 11479 { "vextractf128", { EXxmm, XM, Ib }, 0 }, 11480 }, 11481 { 11482 /* VEX_W_0F3A20_P_2 */ 11483 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, 11484 }, 11485 { 11486 /* VEX_W_0F3A21_P_2 */ 11487 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, 11488 }, 11489 { 11490 /* VEX_W_0F3A30_P_2_LEN_0 */ 11491 { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, 11492 { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, 11493 }, 11494 { 11495 /* VEX_W_0F3A31_P_2_LEN_0 */ 11496 { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, 11497 { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, 11498 }, 11499 { 11500 /* VEX_W_0F3A32_P_2_LEN_0 */ 11501 { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, 11502 { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, 11503 }, 11504 { 11505 /* VEX_W_0F3A33_P_2_LEN_0 */ 11506 { "kshiftld", { MaskG, MaskR, Ib }, 0 }, 11507 { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, 11508 }, 11509 { 11510 /* VEX_W_0F3A38_P_2 */ 11511 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, 11512 }, 11513 { 11514 /* VEX_W_0F3A39_P_2 */ 11515 { "vextracti128", { EXxmm, XM, Ib }, 0 }, 11516 }, 11517 { 11518 /* VEX_W_0F3A40_P_2 */ 11519 { "vdpps", { XM, Vex, EXx, Ib }, 0 }, 11520 }, 11521 { 11522 /* VEX_W_0F3A41_P_2 */ 11523 { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, 11524 }, 11525 { 11526 /* VEX_W_0F3A42_P_2 */ 11527 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, 11528 }, 11529 { 11530 /* VEX_W_0F3A44_P_2 */ 11531 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, 11532 }, 11533 { 11534 /* VEX_W_0F3A46_P_2 */ 11535 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, 11536 }, 11537 { 11538 /* VEX_W_0F3A48_P_2 */ 11539 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, 11540 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, 11541 }, 11542 { 11543 /* VEX_W_0F3A49_P_2 */ 11544 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, 11545 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, 11546 }, 11547 { 11548 /* VEX_W_0F3A4A_P_2 */ 11549 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, 11550 }, 11551 { 11552 /* VEX_W_0F3A4B_P_2 */ 11553 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, 11554 }, 11555 { 11556 /* VEX_W_0F3A4C_P_2 */ 11557 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, 11558 }, 11559 { 11560 /* VEX_W_0F3A60_P_2 */ 11561 { "vpcmpestrm", { XM, EXx, Ib }, 0 }, 11562 }, 11563 { 11564 /* VEX_W_0F3A61_P_2 */ 11565 { "vpcmpestri", { XM, EXx, Ib }, 0 }, 11566 }, 11567 { 11568 /* VEX_W_0F3A62_P_2 */ 11569 { "vpcmpistrm", { XM, EXx, Ib }, 0 }, 11570 }, 11571 { 11572 /* VEX_W_0F3A63_P_2 */ 11573 { "vpcmpistri", { XM, EXx, Ib }, 0 }, 11574 }, 11575 { 11576 /* VEX_W_0F3ADF_P_2 */ 11577 { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, 11578 }, 11579 #define NEED_VEX_W_TABLE 11580 #include "i386-dis-evex.h" 11581 #undef NEED_VEX_W_TABLE 11582 }; 11583 11584 static const struct dis386 mod_table[][2] = { 11585 { 11586 /* MOD_8D */ 11587 { "leaS", { Gv, M }, 0 }, 11588 }, 11589 { 11590 /* MOD_C6_REG_7 */ 11591 { Bad_Opcode }, 11592 { RM_TABLE (RM_C6_REG_7) }, 11593 }, 11594 { 11595 /* MOD_C7_REG_7 */ 11596 { Bad_Opcode }, 11597 { RM_TABLE (RM_C7_REG_7) }, 11598 }, 11599 { 11600 /* MOD_FF_REG_3 */ 11601 { "Jcall^", { indirEp }, 0 }, 11602 }, 11603 { 11604 /* MOD_FF_REG_5 */ 11605 { "Jjmp^", { indirEp }, 0 }, 11606 }, 11607 { 11608 /* MOD_0F01_REG_0 */ 11609 { X86_64_TABLE (X86_64_0F01_REG_0) }, 11610 { RM_TABLE (RM_0F01_REG_0) }, 11611 }, 11612 { 11613 /* MOD_0F01_REG_1 */ 11614 { X86_64_TABLE (X86_64_0F01_REG_1) }, 11615 { RM_TABLE (RM_0F01_REG_1) }, 11616 }, 11617 { 11618 /* MOD_0F01_REG_2 */ 11619 { X86_64_TABLE (X86_64_0F01_REG_2) }, 11620 { RM_TABLE (RM_0F01_REG_2) }, 11621 }, 11622 { 11623 /* MOD_0F01_REG_3 */ 11624 { X86_64_TABLE (X86_64_0F01_REG_3) }, 11625 { RM_TABLE (RM_0F01_REG_3) }, 11626 }, 11627 { 11628 /* MOD_0F01_REG_7 */ 11629 { "invlpg", { Mb }, 0 }, 11630 { RM_TABLE (RM_0F01_REG_7) }, 11631 }, 11632 { 11633 /* MOD_0F12_PREFIX_0 */ 11634 { "movlps", { XM, EXq }, PREFIX_OPCODE }, 11635 { "movhlps", { XM, EXq }, PREFIX_OPCODE }, 11636 }, 11637 { 11638 /* MOD_0F13 */ 11639 { "movlpX", { EXq, XM }, PREFIX_OPCODE }, 11640 }, 11641 { 11642 /* MOD_0F16_PREFIX_0 */ 11643 { "movhps", { XM, EXq }, 0 }, 11644 { "movlhps", { XM, EXq }, 0 }, 11645 }, 11646 { 11647 /* MOD_0F17 */ 11648 { "movhpX", { EXq, XM }, PREFIX_OPCODE }, 11649 }, 11650 { 11651 /* MOD_0F18_REG_0 */ 11652 { "prefetchnta", { Mb }, 0 }, 11653 }, 11654 { 11655 /* MOD_0F18_REG_1 */ 11656 { "prefetcht0", { Mb }, 0 }, 11657 }, 11658 { 11659 /* MOD_0F18_REG_2 */ 11660 { "prefetcht1", { Mb }, 0 }, 11661 }, 11662 { 11663 /* MOD_0F18_REG_3 */ 11664 { "prefetcht2", { Mb }, 0 }, 11665 }, 11666 { 11667 /* MOD_0F18_REG_4 */ 11668 { "nop/reserved", { Mb }, 0 }, 11669 }, 11670 { 11671 /* MOD_0F18_REG_5 */ 11672 { "nop/reserved", { Mb }, 0 }, 11673 }, 11674 { 11675 /* MOD_0F18_REG_6 */ 11676 { "nop/reserved", { Mb }, 0 }, 11677 }, 11678 { 11679 /* MOD_0F18_REG_7 */ 11680 { "nop/reserved", { Mb }, 0 }, 11681 }, 11682 { 11683 /* MOD_0F1A_PREFIX_0 */ 11684 { "bndldx", { Gbnd, Ev_bnd }, 0 }, 11685 { "nopQ", { Ev }, 0 }, 11686 }, 11687 { 11688 /* MOD_0F1B_PREFIX_0 */ 11689 { "bndstx", { Ev_bnd, Gbnd }, 0 }, 11690 { "nopQ", { Ev }, 0 }, 11691 }, 11692 { 11693 /* MOD_0F1B_PREFIX_1 */ 11694 { "bndmk", { Gbnd, Ev_bnd }, 0 }, 11695 { "nopQ", { Ev }, 0 }, 11696 }, 11697 { 11698 /* MOD_0F24 */ 11699 { Bad_Opcode }, 11700 { "movL", { Rd, Td }, 0 }, 11701 }, 11702 { 11703 /* MOD_0F26 */ 11704 { Bad_Opcode }, 11705 { "movL", { Td, Rd }, 0 }, 11706 }, 11707 { 11708 /* MOD_0F2B_PREFIX_0 */ 11709 {"movntps", { Mx, XM }, PREFIX_OPCODE }, 11710 }, 11711 { 11712 /* MOD_0F2B_PREFIX_1 */ 11713 {"movntss", { Md, XM }, PREFIX_OPCODE }, 11714 }, 11715 { 11716 /* MOD_0F2B_PREFIX_2 */ 11717 {"movntpd", { Mx, XM }, PREFIX_OPCODE }, 11718 }, 11719 { 11720 /* MOD_0F2B_PREFIX_3 */ 11721 {"movntsd", { Mq, XM }, PREFIX_OPCODE }, 11722 }, 11723 { 11724 /* MOD_0F51 */ 11725 { Bad_Opcode }, 11726 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, 11727 }, 11728 { 11729 /* MOD_0F71_REG_2 */ 11730 { Bad_Opcode }, 11731 { "psrlw", { MS, Ib }, 0 }, 11732 }, 11733 { 11734 /* MOD_0F71_REG_4 */ 11735 { Bad_Opcode }, 11736 { "psraw", { MS, Ib }, 0 }, 11737 }, 11738 { 11739 /* MOD_0F71_REG_6 */ 11740 { Bad_Opcode }, 11741 { "psllw", { MS, Ib }, 0 }, 11742 }, 11743 { 11744 /* MOD_0F72_REG_2 */ 11745 { Bad_Opcode }, 11746 { "psrld", { MS, Ib }, 0 }, 11747 }, 11748 { 11749 /* MOD_0F72_REG_4 */ 11750 { Bad_Opcode }, 11751 { "psrad", { MS, Ib }, 0 }, 11752 }, 11753 { 11754 /* MOD_0F72_REG_6 */ 11755 { Bad_Opcode }, 11756 { "pslld", { MS, Ib }, 0 }, 11757 }, 11758 { 11759 /* MOD_0F73_REG_2 */ 11760 { Bad_Opcode }, 11761 { "psrlq", { MS, Ib }, 0 }, 11762 }, 11763 { 11764 /* MOD_0F73_REG_3 */ 11765 { Bad_Opcode }, 11766 { PREFIX_TABLE (PREFIX_0F73_REG_3) }, 11767 }, 11768 { 11769 /* MOD_0F73_REG_6 */ 11770 { Bad_Opcode }, 11771 { "psllq", { MS, Ib }, 0 }, 11772 }, 11773 { 11774 /* MOD_0F73_REG_7 */ 11775 { Bad_Opcode }, 11776 { PREFIX_TABLE (PREFIX_0F73_REG_7) }, 11777 }, 11778 { 11779 /* MOD_0FAE_REG_0 */ 11780 { "fxsave", { FXSAVE }, 0 }, 11781 { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, 11782 }, 11783 { 11784 /* MOD_0FAE_REG_1 */ 11785 { "fxrstor", { FXSAVE }, 0 }, 11786 { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, 11787 }, 11788 { 11789 /* MOD_0FAE_REG_2 */ 11790 { "ldmxcsr", { Md }, 0 }, 11791 { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, 11792 }, 11793 { 11794 /* MOD_0FAE_REG_3 */ 11795 { "stmxcsr", { Md }, 0 }, 11796 { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, 11797 }, 11798 { 11799 /* MOD_0FAE_REG_4 */ 11800 { "xsave", { FXSAVE }, 0 }, 11801 }, 11802 { 11803 /* MOD_0FAE_REG_5 */ 11804 { "xrstor", { FXSAVE }, 0 }, 11805 { RM_TABLE (RM_0FAE_REG_5) }, 11806 }, 11807 { 11808 /* MOD_0FAE_REG_6 */ 11809 { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, 11810 { RM_TABLE (RM_0FAE_REG_6) }, 11811 }, 11812 { 11813 /* MOD_0FAE_REG_7 */ 11814 { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, 11815 { RM_TABLE (RM_0FAE_REG_7) }, 11816 }, 11817 { 11818 /* MOD_0FB2 */ 11819 { "lssS", { Gv, Mp }, 0 }, 11820 }, 11821 { 11822 /* MOD_0FB4 */ 11823 { "lfsS", { Gv, Mp }, 0 }, 11824 }, 11825 { 11826 /* MOD_0FB5 */ 11827 { "lgsS", { Gv, Mp }, 0 }, 11828 }, 11829 { 11830 /* MOD_0FC7_REG_3 */ 11831 { "xrstors", { FXSAVE }, 0 }, 11832 }, 11833 { 11834 /* MOD_0FC7_REG_4 */ 11835 { "xsavec", { FXSAVE }, 0 }, 11836 }, 11837 { 11838 /* MOD_0FC7_REG_5 */ 11839 { "xsaves", { FXSAVE }, 0 }, 11840 }, 11841 { 11842 /* MOD_0FC7_REG_6 */ 11843 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, 11844 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } 11845 }, 11846 { 11847 /* MOD_0FC7_REG_7 */ 11848 { "vmptrst", { Mq }, 0 }, 11849 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } 11850 }, 11851 { 11852 /* MOD_0FD7 */ 11853 { Bad_Opcode }, 11854 { "pmovmskb", { Gdq, MS }, 0 }, 11855 }, 11856 { 11857 /* MOD_0FE7_PREFIX_2 */ 11858 { "movntdq", { Mx, XM }, 0 }, 11859 }, 11860 { 11861 /* MOD_0FF0_PREFIX_3 */ 11862 { "lddqu", { XM, M }, 0 }, 11863 }, 11864 { 11865 /* MOD_0F382A_PREFIX_2 */ 11866 { "movntdqa", { XM, Mx }, 0 }, 11867 }, 11868 { 11869 /* MOD_62_32BIT */ 11870 { "bound{S|}", { Gv, Ma }, 0 }, 11871 { EVEX_TABLE (EVEX_0F) }, 11872 }, 11873 { 11874 /* MOD_C4_32BIT */ 11875 { "lesS", { Gv, Mp }, 0 }, 11876 { VEX_C4_TABLE (VEX_0F) }, 11877 }, 11878 { 11879 /* MOD_C5_32BIT */ 11880 { "ldsS", { Gv, Mp }, 0 }, 11881 { VEX_C5_TABLE (VEX_0F) }, 11882 }, 11883 { 11884 /* MOD_VEX_0F12_PREFIX_0 */ 11885 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, 11886 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, 11887 }, 11888 { 11889 /* MOD_VEX_0F13 */ 11890 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, 11891 }, 11892 { 11893 /* MOD_VEX_0F16_PREFIX_0 */ 11894 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, 11895 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, 11896 }, 11897 { 11898 /* MOD_VEX_0F17 */ 11899 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, 11900 }, 11901 { 11902 /* MOD_VEX_0F2B */ 11903 { VEX_W_TABLE (VEX_W_0F2B_M_0) }, 11904 }, 11905 { 11906 /* MOD_VEX_0F50 */ 11907 { Bad_Opcode }, 11908 { VEX_W_TABLE (VEX_W_0F50_M_0) }, 11909 }, 11910 { 11911 /* MOD_VEX_0F71_REG_2 */ 11912 { Bad_Opcode }, 11913 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, 11914 }, 11915 { 11916 /* MOD_VEX_0F71_REG_4 */ 11917 { Bad_Opcode }, 11918 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, 11919 }, 11920 { 11921 /* MOD_VEX_0F71_REG_6 */ 11922 { Bad_Opcode }, 11923 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, 11924 }, 11925 { 11926 /* MOD_VEX_0F72_REG_2 */ 11927 { Bad_Opcode }, 11928 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, 11929 }, 11930 { 11931 /* MOD_VEX_0F72_REG_4 */ 11932 { Bad_Opcode }, 11933 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, 11934 }, 11935 { 11936 /* MOD_VEX_0F72_REG_6 */ 11937 { Bad_Opcode }, 11938 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, 11939 }, 11940 { 11941 /* MOD_VEX_0F73_REG_2 */ 11942 { Bad_Opcode }, 11943 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, 11944 }, 11945 { 11946 /* MOD_VEX_0F73_REG_3 */ 11947 { Bad_Opcode }, 11948 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, 11949 }, 11950 { 11951 /* MOD_VEX_0F73_REG_6 */ 11952 { Bad_Opcode }, 11953 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, 11954 }, 11955 { 11956 /* MOD_VEX_0F73_REG_7 */ 11957 { Bad_Opcode }, 11958 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, 11959 }, 11960 { 11961 /* MOD_VEX_0FAE_REG_2 */ 11962 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, 11963 }, 11964 { 11965 /* MOD_VEX_0FAE_REG_3 */ 11966 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, 11967 }, 11968 { 11969 /* MOD_VEX_0FD7_PREFIX_2 */ 11970 { Bad_Opcode }, 11971 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, 11972 }, 11973 { 11974 /* MOD_VEX_0FE7_PREFIX_2 */ 11975 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, 11976 }, 11977 { 11978 /* MOD_VEX_0FF0_PREFIX_3 */ 11979 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, 11980 }, 11981 { 11982 /* MOD_VEX_0F381A_PREFIX_2 */ 11983 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, 11984 }, 11985 { 11986 /* MOD_VEX_0F382A_PREFIX_2 */ 11987 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, 11988 }, 11989 { 11990 /* MOD_VEX_0F382C_PREFIX_2 */ 11991 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, 11992 }, 11993 { 11994 /* MOD_VEX_0F382D_PREFIX_2 */ 11995 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, 11996 }, 11997 { 11998 /* MOD_VEX_0F382E_PREFIX_2 */ 11999 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, 12000 }, 12001 { 12002 /* MOD_VEX_0F382F_PREFIX_2 */ 12003 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, 12004 }, 12005 { 12006 /* MOD_VEX_0F385A_PREFIX_2 */ 12007 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, 12008 }, 12009 { 12010 /* MOD_VEX_0F388C_PREFIX_2 */ 12011 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, 12012 }, 12013 { 12014 /* MOD_VEX_0F388E_PREFIX_2 */ 12015 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, 12016 }, 12017 #define NEED_MOD_TABLE 12018 #include "i386-dis-evex.h" 12019 #undef NEED_MOD_TABLE 12020 }; 12021 12022 static const struct dis386 rm_table[][8] = { 12023 { 12024 /* RM_C6_REG_7 */ 12025 { "xabort", { Skip_MODRM, Ib }, 0 }, 12026 }, 12027 { 12028 /* RM_C7_REG_7 */ 12029 { "xbeginT", { Skip_MODRM, Jv }, 0 }, 12030 }, 12031 { 12032 /* RM_0F01_REG_0 */ 12033 { Bad_Opcode }, 12034 { "vmcall", { Skip_MODRM }, 0 }, 12035 { "vmlaunch", { Skip_MODRM }, 0 }, 12036 { "vmresume", { Skip_MODRM }, 0 }, 12037 { "vmxoff", { Skip_MODRM }, 0 }, 12038 }, 12039 { 12040 /* RM_0F01_REG_1 */ 12041 { "monitor", { { OP_Monitor, 0 } }, 0 }, 12042 { "mwait", { { OP_Mwait, 0 } }, 0 }, 12043 { "clac", { Skip_MODRM }, 0 }, 12044 { "stac", { Skip_MODRM }, 0 }, 12045 { Bad_Opcode }, 12046 { Bad_Opcode }, 12047 { Bad_Opcode }, 12048 { "encls", { Skip_MODRM }, 0 }, 12049 }, 12050 { 12051 /* RM_0F01_REG_2 */ 12052 { "xgetbv", { Skip_MODRM }, 0 }, 12053 { "xsetbv", { Skip_MODRM }, 0 }, 12054 { Bad_Opcode }, 12055 { Bad_Opcode }, 12056 { "vmfunc", { Skip_MODRM }, 0 }, 12057 { "xend", { Skip_MODRM }, 0 }, 12058 { "xtest", { Skip_MODRM }, 0 }, 12059 { "enclu", { Skip_MODRM }, 0 }, 12060 }, 12061 { 12062 /* RM_0F01_REG_3 */ 12063 { "vmrun", { Skip_MODRM }, 0 }, 12064 { "vmmcall", { Skip_MODRM }, 0 }, 12065 { "vmload", { Skip_MODRM }, 0 }, 12066 { "vmsave", { Skip_MODRM }, 0 }, 12067 { "stgi", { Skip_MODRM }, 0 }, 12068 { "clgi", { Skip_MODRM }, 0 }, 12069 { "skinit", { Skip_MODRM }, 0 }, 12070 { "invlpga", { Skip_MODRM }, 0 }, 12071 }, 12072 { 12073 /* RM_0F01_REG_7 */ 12074 { "swapgs", { Skip_MODRM }, 0 }, 12075 { "rdtscp", { Skip_MODRM }, 0 }, 12076 { "monitorx", { { OP_Monitor, 0 } }, 0 }, 12077 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, 12078 { "clzero", { Skip_MODRM }, 0 }, 12079 }, 12080 { 12081 /* RM_0FAE_REG_5 */ 12082 { "lfence", { Skip_MODRM }, 0 }, 12083 }, 12084 { 12085 /* RM_0FAE_REG_6 */ 12086 { "mfence", { Skip_MODRM }, 0 }, 12087 }, 12088 { 12089 /* RM_0FAE_REG_7 */ 12090 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, 12091 }, 12092 }; 12093 12094 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") 12095 12096 /* We use the high bit to indicate different name for the same 12097 prefix. */ 12098 #define REP_PREFIX (0xf3 | 0x100) 12099 #define XACQUIRE_PREFIX (0xf2 | 0x200) 12100 #define XRELEASE_PREFIX (0xf3 | 0x400) 12101 #define BND_PREFIX (0xf2 | 0x400) 12102 12103 static int 12104 ckprefix (void) 12105 { 12106 int newrex, i, length; 12107 rex = 0; 12108 rex_ignored = 0; 12109 prefixes = 0; 12110 used_prefixes = 0; 12111 rex_used = 0; 12112 last_lock_prefix = -1; 12113 last_repz_prefix = -1; 12114 last_repnz_prefix = -1; 12115 last_data_prefix = -1; 12116 last_addr_prefix = -1; 12117 last_rex_prefix = -1; 12118 last_seg_prefix = -1; 12119 fwait_prefix = -1; 12120 active_seg_prefix = 0; 12121 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) 12122 all_prefixes[i] = 0; 12123 i = 0; 12124 length = 0; 12125 /* The maximum instruction length is 15bytes. */ 12126 while (length < MAX_CODE_LENGTH - 1) 12127 { 12128 FETCH_DATA (the_info, codep + 1); 12129 newrex = 0; 12130 switch (*codep) 12131 { 12132 /* REX prefixes family. */ 12133 case 0x40: 12134 case 0x41: 12135 case 0x42: 12136 case 0x43: 12137 case 0x44: 12138 case 0x45: 12139 case 0x46: 12140 case 0x47: 12141 case 0x48: 12142 case 0x49: 12143 case 0x4a: 12144 case 0x4b: 12145 case 0x4c: 12146 case 0x4d: 12147 case 0x4e: 12148 case 0x4f: 12149 if (address_mode == mode_64bit) 12150 newrex = *codep; 12151 else 12152 return 1; 12153 last_rex_prefix = i; 12154 break; 12155 case 0xf3: 12156 prefixes |= PREFIX_REPZ; 12157 last_repz_prefix = i; 12158 break; 12159 case 0xf2: 12160 prefixes |= PREFIX_REPNZ; 12161 last_repnz_prefix = i; 12162 break; 12163 case 0xf0: 12164 prefixes |= PREFIX_LOCK; 12165 last_lock_prefix = i; 12166 break; 12167 case 0x2e: 12168 prefixes |= PREFIX_CS; 12169 last_seg_prefix = i; 12170 active_seg_prefix = PREFIX_CS; 12171 break; 12172 case 0x36: 12173 prefixes |= PREFIX_SS; 12174 last_seg_prefix = i; 12175 active_seg_prefix = PREFIX_SS; 12176 break; 12177 case 0x3e: 12178 prefixes |= PREFIX_DS; 12179 last_seg_prefix = i; 12180 active_seg_prefix = PREFIX_DS; 12181 break; 12182 case 0x26: 12183 prefixes |= PREFIX_ES; 12184 last_seg_prefix = i; 12185 active_seg_prefix = PREFIX_ES; 12186 break; 12187 case 0x64: 12188 prefixes |= PREFIX_FS; 12189 last_seg_prefix = i; 12190 active_seg_prefix = PREFIX_FS; 12191 break; 12192 case 0x65: 12193 prefixes |= PREFIX_GS; 12194 last_seg_prefix = i; 12195 active_seg_prefix = PREFIX_GS; 12196 break; 12197 case 0x66: 12198 prefixes |= PREFIX_DATA; 12199 last_data_prefix = i; 12200 break; 12201 case 0x67: 12202 prefixes |= PREFIX_ADDR; 12203 last_addr_prefix = i; 12204 break; 12205 case FWAIT_OPCODE: 12206 /* fwait is really an instruction. If there are prefixes 12207 before the fwait, they belong to the fwait, *not* to the 12208 following instruction. */ 12209 fwait_prefix = i; 12210 if (prefixes || rex) 12211 { 12212 prefixes |= PREFIX_FWAIT; 12213 codep++; 12214 /* This ensures that the previous REX prefixes are noticed 12215 as unused prefixes, as in the return case below. */ 12216 rex_used = rex; 12217 return 1; 12218 } 12219 prefixes = PREFIX_FWAIT; 12220 break; 12221 default: 12222 return 1; 12223 } 12224 /* Rex is ignored when followed by another prefix. */ 12225 if (rex) 12226 { 12227 rex_used = rex; 12228 return 1; 12229 } 12230 if (*codep != FWAIT_OPCODE) 12231 all_prefixes[i++] = *codep; 12232 rex = newrex; 12233 codep++; 12234 length++; 12235 } 12236 return 0; 12237 } 12238 12239 /* Return the name of the prefix byte PREF, or NULL if PREF is not a 12240 prefix byte. */ 12241 12242 static const char * 12243 prefix_name (int pref, int sizeflag) 12244 { 12245 static const char *rexes [16] = 12246 { 12247 "rex", /* 0x40 */ 12248 "rex.B", /* 0x41 */ 12249 "rex.X", /* 0x42 */ 12250 "rex.XB", /* 0x43 */ 12251 "rex.R", /* 0x44 */ 12252 "rex.RB", /* 0x45 */ 12253 "rex.RX", /* 0x46 */ 12254 "rex.RXB", /* 0x47 */ 12255 "rex.W", /* 0x48 */ 12256 "rex.WB", /* 0x49 */ 12257 "rex.WX", /* 0x4a */ 12258 "rex.WXB", /* 0x4b */ 12259 "rex.WR", /* 0x4c */ 12260 "rex.WRB", /* 0x4d */ 12261 "rex.WRX", /* 0x4e */ 12262 "rex.WRXB", /* 0x4f */ 12263 }; 12264 12265 switch (pref) 12266 { 12267 /* REX prefixes family. */ 12268 case 0x40: 12269 case 0x41: 12270 case 0x42: 12271 case 0x43: 12272 case 0x44: 12273 case 0x45: 12274 case 0x46: 12275 case 0x47: 12276 case 0x48: 12277 case 0x49: 12278 case 0x4a: 12279 case 0x4b: 12280 case 0x4c: 12281 case 0x4d: 12282 case 0x4e: 12283 case 0x4f: 12284 return rexes [pref - 0x40]; 12285 case 0xf3: 12286 return "repz"; 12287 case 0xf2: 12288 return "repnz"; 12289 case 0xf0: 12290 return "lock"; 12291 case 0x2e: 12292 return "cs"; 12293 case 0x36: 12294 return "ss"; 12295 case 0x3e: 12296 return "ds"; 12297 case 0x26: 12298 return "es"; 12299 case 0x64: 12300 return "fs"; 12301 case 0x65: 12302 return "gs"; 12303 case 0x66: 12304 return (sizeflag & DFLAG) ? "data16" : "data32"; 12305 case 0x67: 12306 if (address_mode == mode_64bit) 12307 return (sizeflag & AFLAG) ? "addr32" : "addr64"; 12308 else 12309 return (sizeflag & AFLAG) ? "addr16" : "addr32"; 12310 case FWAIT_OPCODE: 12311 return "fwait"; 12312 case REP_PREFIX: 12313 return "rep"; 12314 case XACQUIRE_PREFIX: 12315 return "xacquire"; 12316 case XRELEASE_PREFIX: 12317 return "xrelease"; 12318 case BND_PREFIX: 12319 return "bnd"; 12320 default: 12321 return NULL; 12322 } 12323 } 12324 12325 static char op_out[MAX_OPERANDS][100]; 12326 static int op_ad, op_index[MAX_OPERANDS]; 12327 static int two_source_ops; 12328 static bfd_vma op_address[MAX_OPERANDS]; 12329 static bfd_vma op_riprel[MAX_OPERANDS]; 12330 static bfd_vma start_pc; 12331 12332 /* 12333 * On the 386's of 1988, the maximum length of an instruction is 15 bytes. 12334 * (see topic "Redundant prefixes" in the "Differences from 8086" 12335 * section of the "Virtual 8086 Mode" chapter.) 12336 * 'pc' should be the address of this instruction, it will 12337 * be used to print the target address if this is a relative jump or call 12338 * The function returns the length of this instruction in bytes. 12339 */ 12340 12341 static char intel_syntax; 12342 static char intel_mnemonic = !SYSV386_COMPAT; 12343 static char open_char; 12344 static char close_char; 12345 static char separator_char; 12346 static char scale_char; 12347 12348 enum x86_64_isa 12349 { 12350 amd64 = 0, 12351 intel64 12352 }; 12353 12354 static enum x86_64_isa isa64; 12355 12356 /* Here for backwards compatibility. When gdb stops using 12357 print_insn_i386_att and print_insn_i386_intel these functions can 12358 disappear, and print_insn_i386 be merged into print_insn. */ 12359 int 12360 print_insn_i386_att (bfd_vma pc, disassemble_info *info) 12361 { 12362 intel_syntax = 0; 12363 12364 return print_insn (pc, info); 12365 } 12366 12367 int 12368 print_insn_i386_intel (bfd_vma pc, disassemble_info *info) 12369 { 12370 intel_syntax = 1; 12371 12372 return print_insn (pc, info); 12373 } 12374 12375 int 12376 print_insn_i386 (bfd_vma pc, disassemble_info *info) 12377 { 12378 intel_syntax = -1; 12379 12380 return print_insn (pc, info); 12381 } 12382 12383 void 12384 print_i386_disassembler_options (FILE *stream) 12385 { 12386 fprintf (stream, _("\n\ 12387 The following i386/x86-64 specific disassembler options are supported for use\n\ 12388 with the -M switch (multiple options should be separated by commas):\n")); 12389 12390 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); 12391 fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); 12392 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); 12393 fprintf (stream, _(" att Display instruction in AT&T syntax\n")); 12394 fprintf (stream, _(" intel Display instruction in Intel syntax\n")); 12395 fprintf (stream, _(" att-mnemonic\n" 12396 " Display instruction in AT&T mnemonic\n")); 12397 fprintf (stream, _(" intel-mnemonic\n" 12398 " Display instruction in Intel mnemonic\n")); 12399 fprintf (stream, _(" addr64 Assume 64bit address size\n")); 12400 fprintf (stream, _(" addr32 Assume 32bit address size\n")); 12401 fprintf (stream, _(" addr16 Assume 16bit address size\n")); 12402 fprintf (stream, _(" data32 Assume 32bit data size\n")); 12403 fprintf (stream, _(" data16 Assume 16bit data size\n")); 12404 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); 12405 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); 12406 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); 12407 } 12408 12409 /* Bad opcode. */ 12410 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; 12411 12412 /* Get a pointer to struct dis386 with a valid name. */ 12413 12414 static const struct dis386 * 12415 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) 12416 { 12417 int vindex, vex_table_index; 12418 12419 if (dp->name != NULL) 12420 return dp; 12421 12422 switch (dp->op[0].bytemode) 12423 { 12424 case USE_REG_TABLE: 12425 dp = ®_table[dp->op[1].bytemode][modrm.reg]; 12426 break; 12427 12428 case USE_MOD_TABLE: 12429 vindex = modrm.mod == 0x3 ? 1 : 0; 12430 dp = &mod_table[dp->op[1].bytemode][vindex]; 12431 break; 12432 12433 case USE_RM_TABLE: 12434 dp = &rm_table[dp->op[1].bytemode][modrm.rm]; 12435 break; 12436 12437 case USE_PREFIX_TABLE: 12438 if (need_vex) 12439 { 12440 /* The prefix in VEX is implicit. */ 12441 switch (vex.prefix) 12442 { 12443 case 0: 12444 vindex = 0; 12445 break; 12446 case REPE_PREFIX_OPCODE: 12447 vindex = 1; 12448 break; 12449 case DATA_PREFIX_OPCODE: 12450 vindex = 2; 12451 break; 12452 case REPNE_PREFIX_OPCODE: 12453 vindex = 3; 12454 break; 12455 default: 12456 abort (); 12457 break; 12458 } 12459 } 12460 else 12461 { 12462 int last_prefix = -1; 12463 int prefix = 0; 12464 vindex = 0; 12465 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. 12466 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the 12467 last one wins. */ 12468 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) 12469 { 12470 if (last_repz_prefix > last_repnz_prefix) 12471 { 12472 vindex = 1; 12473 prefix = PREFIX_REPZ; 12474 last_prefix = last_repz_prefix; 12475 } 12476 else 12477 { 12478 vindex = 3; 12479 prefix = PREFIX_REPNZ; 12480 last_prefix = last_repnz_prefix; 12481 } 12482 12483 /* Check if prefix should be ignored. */ 12484 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement 12485 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) 12486 & prefix) != 0) 12487 vindex = 0; 12488 } 12489 12490 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) 12491 { 12492 vindex = 2; 12493 prefix = PREFIX_DATA; 12494 last_prefix = last_data_prefix; 12495 } 12496 12497 if (vindex != 0) 12498 { 12499 used_prefixes |= prefix; 12500 all_prefixes[last_prefix] = 0; 12501 } 12502 } 12503 dp = &prefix_table[dp->op[1].bytemode][vindex]; 12504 break; 12505 12506 case USE_X86_64_TABLE: 12507 vindex = address_mode == mode_64bit ? 1 : 0; 12508 dp = &x86_64_table[dp->op[1].bytemode][vindex]; 12509 break; 12510 12511 case USE_3BYTE_TABLE: 12512 FETCH_DATA (info, codep + 2); 12513 vindex = *codep++; 12514 dp = &three_byte_table[dp->op[1].bytemode][vindex]; 12515 end_codep = codep; 12516 modrm.mod = (*codep >> 6) & 3; 12517 modrm.reg = (*codep >> 3) & 7; 12518 modrm.rm = *codep & 7; 12519 break; 12520 12521 case USE_VEX_LEN_TABLE: 12522 if (!need_vex) 12523 abort (); 12524 12525 switch (vex.length) 12526 { 12527 case 128: 12528 vindex = 0; 12529 break; 12530 case 256: 12531 vindex = 1; 12532 break; 12533 default: 12534 abort (); 12535 break; 12536 } 12537 12538 dp = &vex_len_table[dp->op[1].bytemode][vindex]; 12539 break; 12540 12541 case USE_XOP_8F_TABLE: 12542 FETCH_DATA (info, codep + 3); 12543 /* All bits in the REX prefix are ignored. */ 12544 rex_ignored = rex; 12545 rex = ~(*codep >> 5) & 0x7; 12546 12547 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ 12548 switch ((*codep & 0x1f)) 12549 { 12550 default: 12551 dp = &bad_opcode; 12552 return dp; 12553 case 0x8: 12554 vex_table_index = XOP_08; 12555 break; 12556 case 0x9: 12557 vex_table_index = XOP_09; 12558 break; 12559 case 0xa: 12560 vex_table_index = XOP_0A; 12561 break; 12562 } 12563 codep++; 12564 vex.w = *codep & 0x80; 12565 if (vex.w && address_mode == mode_64bit) 12566 rex |= REX_W; 12567 12568 vex.register_specifier = (~(*codep >> 3)) & 0xf; 12569 if (address_mode != mode_64bit 12570 && vex.register_specifier > 0x7) 12571 { 12572 dp = &bad_opcode; 12573 return dp; 12574 } 12575 12576 vex.length = (*codep & 0x4) ? 256 : 128; 12577 switch ((*codep & 0x3)) 12578 { 12579 case 0: 12580 vex.prefix = 0; 12581 break; 12582 case 1: 12583 vex.prefix = DATA_PREFIX_OPCODE; 12584 break; 12585 case 2: 12586 vex.prefix = REPE_PREFIX_OPCODE; 12587 break; 12588 case 3: 12589 vex.prefix = REPNE_PREFIX_OPCODE; 12590 break; 12591 } 12592 need_vex = 1; 12593 need_vex_reg = 1; 12594 codep++; 12595 vindex = *codep++; 12596 dp = &xop_table[vex_table_index][vindex]; 12597 12598 end_codep = codep; 12599 FETCH_DATA (info, codep + 1); 12600 modrm.mod = (*codep >> 6) & 3; 12601 modrm.reg = (*codep >> 3) & 7; 12602 modrm.rm = *codep & 7; 12603 break; 12604 12605 case USE_VEX_C4_TABLE: 12606 /* VEX prefix. */ 12607 FETCH_DATA (info, codep + 3); 12608 /* All bits in the REX prefix are ignored. */ 12609 rex_ignored = rex; 12610 rex = ~(*codep >> 5) & 0x7; 12611 switch ((*codep & 0x1f)) 12612 { 12613 default: 12614 dp = &bad_opcode; 12615 return dp; 12616 case 0x1: 12617 vex_table_index = VEX_0F; 12618 break; 12619 case 0x2: 12620 vex_table_index = VEX_0F38; 12621 break; 12622 case 0x3: 12623 vex_table_index = VEX_0F3A; 12624 break; 12625 } 12626 codep++; 12627 vex.w = *codep & 0x80; 12628 if (vex.w && address_mode == mode_64bit) 12629 rex |= REX_W; 12630 12631 vex.register_specifier = (~(*codep >> 3)) & 0xf; 12632 if (address_mode != mode_64bit 12633 && vex.register_specifier > 0x7) 12634 { 12635 dp = &bad_opcode; 12636 return dp; 12637 } 12638 12639 vex.length = (*codep & 0x4) ? 256 : 128; 12640 switch ((*codep & 0x3)) 12641 { 12642 case 0: 12643 vex.prefix = 0; 12644 break; 12645 case 1: 12646 vex.prefix = DATA_PREFIX_OPCODE; 12647 break; 12648 case 2: 12649 vex.prefix = REPE_PREFIX_OPCODE; 12650 break; 12651 case 3: 12652 vex.prefix = REPNE_PREFIX_OPCODE; 12653 break; 12654 } 12655 need_vex = 1; 12656 need_vex_reg = 1; 12657 codep++; 12658 vindex = *codep++; 12659 dp = &vex_table[vex_table_index][vindex]; 12660 end_codep = codep; 12661 /* There is no MODRM byte for VEX [82|77]. */ 12662 if (vindex != 0x77 && vindex != 0x82) 12663 { 12664 FETCH_DATA (info, codep + 1); 12665 modrm.mod = (*codep >> 6) & 3; 12666 modrm.reg = (*codep >> 3) & 7; 12667 modrm.rm = *codep & 7; 12668 } 12669 break; 12670 12671 case USE_VEX_C5_TABLE: 12672 /* VEX prefix. */ 12673 FETCH_DATA (info, codep + 2); 12674 /* All bits in the REX prefix are ignored. */ 12675 rex_ignored = rex; 12676 rex = (*codep & 0x80) ? 0 : REX_R; 12677 12678 vex.register_specifier = (~(*codep >> 3)) & 0xf; 12679 if (address_mode != mode_64bit 12680 && vex.register_specifier > 0x7) 12681 { 12682 dp = &bad_opcode; 12683 return dp; 12684 } 12685 12686 vex.w = 0; 12687 12688 vex.length = (*codep & 0x4) ? 256 : 128; 12689 switch ((*codep & 0x3)) 12690 { 12691 case 0: 12692 vex.prefix = 0; 12693 break; 12694 case 1: 12695 vex.prefix = DATA_PREFIX_OPCODE; 12696 break; 12697 case 2: 12698 vex.prefix = REPE_PREFIX_OPCODE; 12699 break; 12700 case 3: 12701 vex.prefix = REPNE_PREFIX_OPCODE; 12702 break; 12703 } 12704 need_vex = 1; 12705 need_vex_reg = 1; 12706 codep++; 12707 vindex = *codep++; 12708 dp = &vex_table[dp->op[1].bytemode][vindex]; 12709 end_codep = codep; 12710 /* There is no MODRM byte for VEX [82|77]. */ 12711 if (vindex != 0x77 && vindex != 0x82) 12712 { 12713 FETCH_DATA (info, codep + 1); 12714 modrm.mod = (*codep >> 6) & 3; 12715 modrm.reg = (*codep >> 3) & 7; 12716 modrm.rm = *codep & 7; 12717 } 12718 break; 12719 12720 case USE_VEX_W_TABLE: 12721 if (!need_vex) 12722 abort (); 12723 12724 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; 12725 break; 12726 12727 case USE_EVEX_TABLE: 12728 two_source_ops = 0; 12729 /* EVEX prefix. */ 12730 vex.evex = 1; 12731 FETCH_DATA (info, codep + 4); 12732 /* All bits in the REX prefix are ignored. */ 12733 rex_ignored = rex; 12734 /* The first byte after 0x62. */ 12735 rex = ~(*codep >> 5) & 0x7; 12736 vex.r = *codep & 0x10; 12737 switch ((*codep & 0xf)) 12738 { 12739 default: 12740 return &bad_opcode; 12741 case 0x1: 12742 vex_table_index = EVEX_0F; 12743 break; 12744 case 0x2: 12745 vex_table_index = EVEX_0F38; 12746 break; 12747 case 0x3: 12748 vex_table_index = EVEX_0F3A; 12749 break; 12750 } 12751 12752 /* The second byte after 0x62. */ 12753 codep++; 12754 vex.w = *codep & 0x80; 12755 if (vex.w && address_mode == mode_64bit) 12756 rex |= REX_W; 12757 12758 vex.register_specifier = (~(*codep >> 3)) & 0xf; 12759 if (address_mode != mode_64bit) 12760 { 12761 /* In 16/32-bit mode silently ignore following bits. */ 12762 rex &= ~REX_B; 12763 vex.r = 1; 12764 vex.v = 1; 12765 vex.register_specifier &= 0x7; 12766 } 12767 12768 /* The U bit. */ 12769 if (!(*codep & 0x4)) 12770 return &bad_opcode; 12771 12772 switch ((*codep & 0x3)) 12773 { 12774 case 0: 12775 vex.prefix = 0; 12776 break; 12777 case 1: 12778 vex.prefix = DATA_PREFIX_OPCODE; 12779 break; 12780 case 2: 12781 vex.prefix = REPE_PREFIX_OPCODE; 12782 break; 12783 case 3: 12784 vex.prefix = REPNE_PREFIX_OPCODE; 12785 break; 12786 } 12787 12788 /* The third byte after 0x62. */ 12789 codep++; 12790 12791 /* Remember the static rounding bits. */ 12792 vex.ll = (*codep >> 5) & 3; 12793 vex.b = (*codep & 0x10) != 0; 12794 12795 vex.v = *codep & 0x8; 12796 vex.mask_register_specifier = *codep & 0x7; 12797 vex.zeroing = *codep & 0x80; 12798 12799 need_vex = 1; 12800 need_vex_reg = 1; 12801 codep++; 12802 vindex = *codep++; 12803 dp = &evex_table[vex_table_index][vindex]; 12804 end_codep = codep; 12805 FETCH_DATA (info, codep + 1); 12806 modrm.mod = (*codep >> 6) & 3; 12807 modrm.reg = (*codep >> 3) & 7; 12808 modrm.rm = *codep & 7; 12809 12810 /* Set vector length. */ 12811 if (modrm.mod == 3 && vex.b) 12812 vex.length = 512; 12813 else 12814 { 12815 switch (vex.ll) 12816 { 12817 case 0x0: 12818 vex.length = 128; 12819 break; 12820 case 0x1: 12821 vex.length = 256; 12822 break; 12823 case 0x2: 12824 vex.length = 512; 12825 break; 12826 default: 12827 return &bad_opcode; 12828 } 12829 } 12830 break; 12831 12832 case 0: 12833 dp = &bad_opcode; 12834 break; 12835 12836 default: 12837 abort (); 12838 } 12839 12840 if (dp->name != NULL) 12841 return dp; 12842 else 12843 return get_valid_dis386 (dp, info); 12844 } 12845 12846 static void 12847 get_sib (disassemble_info *info, int sizeflag) 12848 { 12849 /* If modrm.mod == 3, operand must be register. */ 12850 if (need_modrm 12851 && ((sizeflag & AFLAG) || address_mode == mode_64bit) 12852 && modrm.mod != 3 12853 && modrm.rm == 4) 12854 { 12855 FETCH_DATA (info, codep + 2); 12856 sib.index = (codep [1] >> 3) & 7; 12857 sib.scale = (codep [1] >> 6) & 3; 12858 sib.base = codep [1] & 7; 12859 } 12860 } 12861 12862 static int 12863 print_insn (bfd_vma pc, disassemble_info *info) 12864 { 12865 const struct dis386 *dp; 12866 int i; 12867 char *op_txt[MAX_OPERANDS]; 12868 int needcomma; 12869 int sizeflag, orig_sizeflag; 12870 const char *p; 12871 struct dis_private priv; 12872 int prefix_length; 12873 12874 priv.orig_sizeflag = AFLAG | DFLAG; 12875 if ((info->mach & bfd_mach_i386_i386) != 0) 12876 address_mode = mode_32bit; 12877 else if (info->mach == bfd_mach_i386_i8086) 12878 { 12879 address_mode = mode_16bit; 12880 priv.orig_sizeflag = 0; 12881 } 12882 else 12883 address_mode = mode_64bit; 12884 12885 if (intel_syntax == (char) -1) 12886 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; 12887 12888 for (p = info->disassembler_options; p != NULL; ) 12889 { 12890 if (CONST_STRNEQ (p, "amd64")) 12891 isa64 = amd64; 12892 else if (CONST_STRNEQ (p, "intel64")) 12893 isa64 = intel64; 12894 else if (CONST_STRNEQ (p, "x86-64")) 12895 { 12896 address_mode = mode_64bit; 12897 priv.orig_sizeflag = AFLAG | DFLAG; 12898 } 12899 else if (CONST_STRNEQ (p, "i386")) 12900 { 12901 address_mode = mode_32bit; 12902 priv.orig_sizeflag = AFLAG | DFLAG; 12903 } 12904 else if (CONST_STRNEQ (p, "i8086")) 12905 { 12906 address_mode = mode_16bit; 12907 priv.orig_sizeflag = 0; 12908 } 12909 else if (CONST_STRNEQ (p, "intel")) 12910 { 12911 intel_syntax = 1; 12912 if (CONST_STRNEQ (p + 5, "-mnemonic")) 12913 intel_mnemonic = 1; 12914 } 12915 else if (CONST_STRNEQ (p, "att")) 12916 { 12917 intel_syntax = 0; 12918 if (CONST_STRNEQ (p + 3, "-mnemonic")) 12919 intel_mnemonic = 0; 12920 } 12921 else if (CONST_STRNEQ (p, "addr")) 12922 { 12923 if (address_mode == mode_64bit) 12924 { 12925 if (p[4] == '3' && p[5] == '2') 12926 priv.orig_sizeflag &= ~AFLAG; 12927 else if (p[4] == '6' && p[5] == '4') 12928 priv.orig_sizeflag |= AFLAG; 12929 } 12930 else 12931 { 12932 if (p[4] == '1' && p[5] == '6') 12933 priv.orig_sizeflag &= ~AFLAG; 12934 else if (p[4] == '3' && p[5] == '2') 12935 priv.orig_sizeflag |= AFLAG; 12936 } 12937 } 12938 else if (CONST_STRNEQ (p, "data")) 12939 { 12940 if (p[4] == '1' && p[5] == '6') 12941 priv.orig_sizeflag &= ~DFLAG; 12942 else if (p[4] == '3' && p[5] == '2') 12943 priv.orig_sizeflag |= DFLAG; 12944 } 12945 else if (CONST_STRNEQ (p, "suffix")) 12946 priv.orig_sizeflag |= SUFFIX_ALWAYS; 12947 12948 p = strchr (p, ','); 12949 if (p != NULL) 12950 p++; 12951 } 12952 12953 if (intel_syntax) 12954 { 12955 names64 = intel_names64; 12956 names32 = intel_names32; 12957 names16 = intel_names16; 12958 names8 = intel_names8; 12959 names8rex = intel_names8rex; 12960 names_seg = intel_names_seg; 12961 names_mm = intel_names_mm; 12962 names_bnd = intel_names_bnd; 12963 names_xmm = intel_names_xmm; 12964 names_ymm = intel_names_ymm; 12965 names_zmm = intel_names_zmm; 12966 index64 = intel_index64; 12967 index32 = intel_index32; 12968 names_mask = intel_names_mask; 12969 index16 = intel_index16; 12970 open_char = '['; 12971 close_char = ']'; 12972 separator_char = '+'; 12973 scale_char = '*'; 12974 } 12975 else 12976 { 12977 names64 = att_names64; 12978 names32 = att_names32; 12979 names16 = att_names16; 12980 names8 = att_names8; 12981 names8rex = att_names8rex; 12982 names_seg = att_names_seg; 12983 names_mm = att_names_mm; 12984 names_bnd = att_names_bnd; 12985 names_xmm = att_names_xmm; 12986 names_ymm = att_names_ymm; 12987 names_zmm = att_names_zmm; 12988 index64 = att_index64; 12989 index32 = att_index32; 12990 names_mask = att_names_mask; 12991 index16 = att_index16; 12992 open_char = '('; 12993 close_char = ')'; 12994 separator_char = ','; 12995 scale_char = ','; 12996 } 12997 12998 /* The output looks better if we put 7 bytes on a line, since that 12999 puts most long word instructions on a single line. Use 8 bytes 13000 for Intel L1OM. */ 13001 if ((info->mach & bfd_mach_l1om) != 0) 13002 info->bytes_per_line = 8; 13003 else 13004 info->bytes_per_line = 7; 13005 13006 info->private_data = &priv; 13007 priv.max_fetched = priv.the_buffer; 13008 priv.insn_start = pc; 13009 13010 obuf[0] = 0; 13011 for (i = 0; i < MAX_OPERANDS; ++i) 13012 { 13013 op_out[i][0] = 0; 13014 op_index[i] = -1; 13015 } 13016 13017 the_info = info; 13018 start_pc = pc; 13019 start_codep = priv.the_buffer; 13020 codep = priv.the_buffer; 13021 13022 if (OPCODES_SIGSETJMP (priv.bailout) != 0) 13023 { 13024 const char *name; 13025 13026 /* Getting here means we tried for data but didn't get it. That 13027 means we have an incomplete instruction of some sort. Just 13028 print the first byte as a prefix or a .byte pseudo-op. */ 13029 if (codep > priv.the_buffer) 13030 { 13031 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); 13032 if (name != NULL) 13033 (*info->fprintf_func) (info->stream, "%s", name); 13034 else 13035 { 13036 /* Just print the first byte as a .byte instruction. */ 13037 (*info->fprintf_func) (info->stream, ".byte 0x%x", 13038 (unsigned int) priv.the_buffer[0]); 13039 } 13040 13041 return 1; 13042 } 13043 13044 return -1; 13045 } 13046 13047 obufp = obuf; 13048 sizeflag = priv.orig_sizeflag; 13049 13050 if (!ckprefix () || rex_used) 13051 { 13052 /* Too many prefixes or unused REX prefixes. */ 13053 for (i = 0; 13054 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; 13055 i++) 13056 (*info->fprintf_func) (info->stream, "%s%s", 13057 i == 0 ? "" : " ", 13058 prefix_name (all_prefixes[i], sizeflag)); 13059 return i; 13060 } 13061 13062 insn_codep = codep; 13063 13064 FETCH_DATA (info, codep + 1); 13065 two_source_ops = (*codep == 0x62) || (*codep == 0xc8); 13066 13067 if (((prefixes & PREFIX_FWAIT) 13068 && ((*codep < 0xd8) || (*codep > 0xdf)))) 13069 { 13070 /* Handle prefixes before fwait. */ 13071 for (i = 0; i < fwait_prefix && all_prefixes[i]; 13072 i++) 13073 (*info->fprintf_func) (info->stream, "%s ", 13074 prefix_name (all_prefixes[i], sizeflag)); 13075 (*info->fprintf_func) (info->stream, "fwait"); 13076 return i + 1; 13077 } 13078 13079 if (*codep == 0x0f) 13080 { 13081 unsigned char threebyte; 13082 FETCH_DATA (info, codep + 2); 13083 threebyte = *++codep; 13084 dp = &dis386_twobyte[threebyte]; 13085 need_modrm = twobyte_has_modrm[*codep]; 13086 codep++; 13087 } 13088 else 13089 { 13090 dp = &dis386[*codep]; 13091 need_modrm = onebyte_has_modrm[*codep]; 13092 codep++; 13093 } 13094 13095 /* Save sizeflag for printing the extra prefixes later before updating 13096 it for mnemonic and operand processing. The prefix names depend 13097 only on the address mode. */ 13098 orig_sizeflag = sizeflag; 13099 if (prefixes & PREFIX_ADDR) 13100 sizeflag ^= AFLAG; 13101 if ((prefixes & PREFIX_DATA)) 13102 sizeflag ^= DFLAG; 13103 13104 end_codep = codep; 13105 if (need_modrm) 13106 { 13107 FETCH_DATA (info, codep + 1); 13108 modrm.mod = (*codep >> 6) & 3; 13109 modrm.reg = (*codep >> 3) & 7; 13110 modrm.rm = *codep & 7; 13111 } 13112 13113 need_vex = 0; 13114 need_vex_reg = 0; 13115 vex_w_done = 0; 13116 vex.evex = 0; 13117 13118 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) 13119 { 13120 get_sib (info, sizeflag); 13121 dofloat (sizeflag); 13122 } 13123 else 13124 { 13125 dp = get_valid_dis386 (dp, info); 13126 if (dp != NULL && putop (dp->name, sizeflag) == 0) 13127 { 13128 get_sib (info, sizeflag); 13129 for (i = 0; i < MAX_OPERANDS; ++i) 13130 { 13131 obufp = op_out[i]; 13132 op_ad = MAX_OPERANDS - 1 - i; 13133 if (dp->op[i].rtn) 13134 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); 13135 /* For EVEX instruction after the last operand masking 13136 should be printed. */ 13137 if (i == 0 && vex.evex) 13138 { 13139 /* Don't print {%k0}. */ 13140 if (vex.mask_register_specifier) 13141 { 13142 oappend ("{"); 13143 oappend (names_mask[vex.mask_register_specifier]); 13144 oappend ("}"); 13145 } 13146 if (vex.zeroing) 13147 oappend ("{z}"); 13148 } 13149 } 13150 } 13151 } 13152 13153 /* Check if the REX prefix is used. */ 13154 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) 13155 all_prefixes[last_rex_prefix] = 0; 13156 13157 /* Check if the SEG prefix is used. */ 13158 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES 13159 | PREFIX_FS | PREFIX_GS)) != 0 13160 && (used_prefixes & active_seg_prefix) != 0) 13161 all_prefixes[last_seg_prefix] = 0; 13162 13163 /* Check if the ADDR prefix is used. */ 13164 if ((prefixes & PREFIX_ADDR) != 0 13165 && (used_prefixes & PREFIX_ADDR) != 0) 13166 all_prefixes[last_addr_prefix] = 0; 13167 13168 /* Check if the DATA prefix is used. */ 13169 if ((prefixes & PREFIX_DATA) != 0 13170 && (used_prefixes & PREFIX_DATA) != 0) 13171 all_prefixes[last_data_prefix] = 0; 13172 13173 /* Print the extra prefixes. */ 13174 prefix_length = 0; 13175 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) 13176 if (all_prefixes[i]) 13177 { 13178 const char *name; 13179 name = prefix_name (all_prefixes[i], orig_sizeflag); 13180 if (name == NULL) 13181 abort (); 13182 prefix_length += strlen (name) + 1; 13183 (*info->fprintf_func) (info->stream, "%s ", name); 13184 } 13185 13186 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is 13187 unused, opcode is invalid. Since the PREFIX_DATA prefix may be 13188 used by putop and MMX/SSE operand and may be overriden by the 13189 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix 13190 separately. */ 13191 if (dp->prefix_requirement == PREFIX_OPCODE 13192 && dp != &bad_opcode 13193 && (((prefixes 13194 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 13195 && (used_prefixes 13196 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) 13197 || ((((prefixes 13198 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) 13199 == PREFIX_DATA) 13200 && (used_prefixes & PREFIX_DATA) == 0)))) 13201 { 13202 (*info->fprintf_func) (info->stream, "(bad)"); 13203 return end_codep - priv.the_buffer; 13204 } 13205 13206 /* Check maximum code length. */ 13207 if ((codep - start_codep) > MAX_CODE_LENGTH) 13208 { 13209 (*info->fprintf_func) (info->stream, "(bad)"); 13210 return MAX_CODE_LENGTH; 13211 } 13212 13213 obufp = mnemonicendp; 13214 for (i = strlen (obuf) + prefix_length; i < 6; i++) 13215 oappend (" "); 13216 oappend (" "); 13217 (*info->fprintf_func) (info->stream, "%s", obuf); 13218 13219 /* The enter and bound instructions are printed with operands in the same 13220 order as the intel book; everything else is printed in reverse order. */ 13221 if (intel_syntax || two_source_ops) 13222 { 13223 bfd_vma riprel; 13224 13225 for (i = 0; i < MAX_OPERANDS; ++i) 13226 op_txt[i] = op_out[i]; 13227 13228 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding 13229 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) 13230 { 13231 op_txt[2] = op_out[3]; 13232 op_txt[3] = op_out[2]; 13233 } 13234 13235 for (i = 0; i < (MAX_OPERANDS >> 1); ++i) 13236 { 13237 op_ad = op_index[i]; 13238 op_index[i] = op_index[MAX_OPERANDS - 1 - i]; 13239 op_index[MAX_OPERANDS - 1 - i] = op_ad; 13240 riprel = op_riprel[i]; 13241 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; 13242 op_riprel[MAX_OPERANDS - 1 - i] = riprel; 13243 } 13244 } 13245 else 13246 { 13247 for (i = 0; i < MAX_OPERANDS; ++i) 13248 op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; 13249 } 13250 13251 needcomma = 0; 13252 for (i = 0; i < MAX_OPERANDS; ++i) 13253 if (*op_txt[i]) 13254 { 13255 if (needcomma) 13256 (*info->fprintf_func) (info->stream, ","); 13257 if (op_index[i] != -1 && !op_riprel[i]) 13258 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); 13259 else 13260 (*info->fprintf_func) (info->stream, "%s", op_txt[i]); 13261 needcomma = 1; 13262 } 13263 13264 for (i = 0; i < MAX_OPERANDS; i++) 13265 if (op_index[i] != -1 && op_riprel[i]) 13266 { 13267 (*info->fprintf_func) (info->stream, " # "); 13268 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep 13269 + op_address[op_index[i]]), info); 13270 break; 13271 } 13272 return codep - priv.the_buffer; 13273 } 13274 13275 static const char *float_mem[] = { 13276 /* d8 */ 13277 "fadd{s|}", 13278 "fmul{s|}", 13279 "fcom{s|}", 13280 "fcomp{s|}", 13281 "fsub{s|}", 13282 "fsubr{s|}", 13283 "fdiv{s|}", 13284 "fdivr{s|}", 13285 /* d9 */ 13286 "fld{s|}", 13287 "(bad)", 13288 "fst{s|}", 13289 "fstp{s|}", 13290 "fldenvIC", 13291 "fldcw", 13292 "fNstenvIC", 13293 "fNstcw", 13294 /* da */ 13295 "fiadd{l|}", 13296 "fimul{l|}", 13297 "ficom{l|}", 13298 "ficomp{l|}", 13299 "fisub{l|}", 13300 "fisubr{l|}", 13301 "fidiv{l|}", 13302 "fidivr{l|}", 13303 /* db */ 13304 "fild{l|}", 13305 "fisttp{l|}", 13306 "fist{l|}", 13307 "fistp{l|}", 13308 "(bad)", 13309 "fld{t||t|}", 13310 "(bad)", 13311 "fstp{t||t|}", 13312 /* dc */ 13313 "fadd{l|}", 13314 "fmul{l|}", 13315 "fcom{l|}", 13316 "fcomp{l|}", 13317 "fsub{l|}", 13318 "fsubr{l|}", 13319 "fdiv{l|}", 13320 "fdivr{l|}", 13321 /* dd */ 13322 "fld{l|}", 13323 "fisttp{ll|}", 13324 "fst{l||}", 13325 "fstp{l|}", 13326 "frstorIC", 13327 "(bad)", 13328 "fNsaveIC", 13329 "fNstsw", 13330 /* de */ 13331 "fiadd", 13332 "fimul", 13333 "ficom", 13334 "ficomp", 13335 "fisub", 13336 "fisubr", 13337 "fidiv", 13338 "fidivr", 13339 /* df */ 13340 "fild", 13341 "fisttp", 13342 "fist", 13343 "fistp", 13344 "fbld", 13345 "fild{ll|}", 13346 "fbstp", 13347 "fistp{ll|}", 13348 }; 13349 13350 static const unsigned char float_mem_mode[] = { 13351 /* d8 */ 13352 d_mode, 13353 d_mode, 13354 d_mode, 13355 d_mode, 13356 d_mode, 13357 d_mode, 13358 d_mode, 13359 d_mode, 13360 /* d9 */ 13361 d_mode, 13362 0, 13363 d_mode, 13364 d_mode, 13365 0, 13366 w_mode, 13367 0, 13368 w_mode, 13369 /* da */ 13370 d_mode, 13371 d_mode, 13372 d_mode, 13373 d_mode, 13374 d_mode, 13375 d_mode, 13376 d_mode, 13377 d_mode, 13378 /* db */ 13379 d_mode, 13380 d_mode, 13381 d_mode, 13382 d_mode, 13383 0, 13384 t_mode, 13385 0, 13386 t_mode, 13387 /* dc */ 13388 q_mode, 13389 q_mode, 13390 q_mode, 13391 q_mode, 13392 q_mode, 13393 q_mode, 13394 q_mode, 13395 q_mode, 13396 /* dd */ 13397 q_mode, 13398 q_mode, 13399 q_mode, 13400 q_mode, 13401 0, 13402 0, 13403 0, 13404 w_mode, 13405 /* de */ 13406 w_mode, 13407 w_mode, 13408 w_mode, 13409 w_mode, 13410 w_mode, 13411 w_mode, 13412 w_mode, 13413 w_mode, 13414 /* df */ 13415 w_mode, 13416 w_mode, 13417 w_mode, 13418 w_mode, 13419 t_mode, 13420 q_mode, 13421 t_mode, 13422 q_mode 13423 }; 13424 13425 #define ST { OP_ST, 0 } 13426 #define STi { OP_STi, 0 } 13427 13428 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 13429 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 13430 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 13431 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 13432 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 13433 #define FGRPda_5 NULL, { { NULL, 5 } }, 0 13434 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 13435 #define FGRPde_3 NULL, { { NULL, 7 } }, 0 13436 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 13437 13438 static const struct dis386 float_reg[][8] = { 13439 /* d8 */ 13440 { 13441 { "fadd", { ST, STi }, 0 }, 13442 { "fmul", { ST, STi }, 0 }, 13443 { "fcom", { STi }, 0 }, 13444 { "fcomp", { STi }, 0 }, 13445 { "fsub", { ST, STi }, 0 }, 13446 { "fsubr", { ST, STi }, 0 }, 13447 { "fdiv", { ST, STi }, 0 }, 13448 { "fdivr", { ST, STi }, 0 }, 13449 }, 13450 /* d9 */ 13451 { 13452 { "fld", { STi }, 0 }, 13453 { "fxch", { STi }, 0 }, 13454 { FGRPd9_2 }, 13455 { Bad_Opcode }, 13456 { FGRPd9_4 }, 13457 { FGRPd9_5 }, 13458 { FGRPd9_6 }, 13459 { FGRPd9_7 }, 13460 }, 13461 /* da */ 13462 { 13463 { "fcmovb", { ST, STi }, 0 }, 13464 { "fcmove", { ST, STi }, 0 }, 13465 { "fcmovbe",{ ST, STi }, 0 }, 13466 { "fcmovu", { ST, STi }, 0 }, 13467 { Bad_Opcode }, 13468 { FGRPda_5 }, 13469 { Bad_Opcode }, 13470 { Bad_Opcode }, 13471 }, 13472 /* db */ 13473 { 13474 { "fcmovnb",{ ST, STi }, 0 }, 13475 { "fcmovne",{ ST, STi }, 0 }, 13476 { "fcmovnbe",{ ST, STi }, 0 }, 13477 { "fcmovnu",{ ST, STi }, 0 }, 13478 { FGRPdb_4 }, 13479 { "fucomi", { ST, STi }, 0 }, 13480 { "fcomi", { ST, STi }, 0 }, 13481 { Bad_Opcode }, 13482 }, 13483 /* dc */ 13484 { 13485 { "fadd", { STi, ST }, 0 }, 13486 { "fmul", { STi, ST }, 0 }, 13487 { Bad_Opcode }, 13488 { Bad_Opcode }, 13489 { "fsub!M", { STi, ST }, 0 }, 13490 { "fsubM", { STi, ST }, 0 }, 13491 { "fdiv!M", { STi, ST }, 0 }, 13492 { "fdivM", { STi, ST }, 0 }, 13493 }, 13494 /* dd */ 13495 { 13496 { "ffree", { STi }, 0 }, 13497 { Bad_Opcode }, 13498 { "fst", { STi }, 0 }, 13499 { "fstp", { STi }, 0 }, 13500 { "fucom", { STi }, 0 }, 13501 { "fucomp", { STi }, 0 }, 13502 { Bad_Opcode }, 13503 { Bad_Opcode }, 13504 }, 13505 /* de */ 13506 { 13507 { "faddp", { STi, ST }, 0 }, 13508 { "fmulp", { STi, ST }, 0 }, 13509 { Bad_Opcode }, 13510 { FGRPde_3 }, 13511 { "fsub!Mp", { STi, ST }, 0 }, 13512 { "fsubMp", { STi, ST }, 0 }, 13513 { "fdiv!Mp", { STi, ST }, 0 }, 13514 { "fdivMp", { STi, ST }, 0 }, 13515 }, 13516 /* df */ 13517 { 13518 { "ffreep", { STi }, 0 }, 13519 { Bad_Opcode }, 13520 { Bad_Opcode }, 13521 { Bad_Opcode }, 13522 { FGRPdf_4 }, 13523 { "fucomip", { ST, STi }, 0 }, 13524 { "fcomip", { ST, STi }, 0 }, 13525 { Bad_Opcode }, 13526 }, 13527 }; 13528 13529 static char *fgrps[][8] = { 13530 /* d9_2 0 */ 13531 { 13532 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 13533 }, 13534 13535 /* d9_4 1 */ 13536 { 13537 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", 13538 }, 13539 13540 /* d9_5 2 */ 13541 { 13542 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", 13543 }, 13544 13545 /* d9_6 3 */ 13546 { 13547 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", 13548 }, 13549 13550 /* d9_7 4 */ 13551 { 13552 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", 13553 }, 13554 13555 /* da_5 5 */ 13556 { 13557 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 13558 }, 13559 13560 /* db_4 6 */ 13561 { 13562 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", 13563 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", 13564 }, 13565 13566 /* de_3 7 */ 13567 { 13568 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 13569 }, 13570 13571 /* df_4 8 */ 13572 { 13573 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 13574 }, 13575 }; 13576 13577 static void 13578 swap_operand (void) 13579 { 13580 mnemonicendp[0] = '.'; 13581 mnemonicendp[1] = 's'; 13582 mnemonicendp += 2; 13583 } 13584 13585 static void 13586 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, 13587 int sizeflag ATTRIBUTE_UNUSED) 13588 { 13589 /* Skip mod/rm byte. */ 13590 MODRM_CHECK; 13591 codep++; 13592 } 13593 13594 static void 13595 dofloat (int sizeflag) 13596 { 13597 const struct dis386 *dp; 13598 unsigned char floatop; 13599 13600 floatop = codep[-1]; 13601 13602 if (modrm.mod != 3) 13603 { 13604 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; 13605 13606 putop (float_mem[fp_indx], sizeflag); 13607 obufp = op_out[0]; 13608 op_ad = 2; 13609 OP_E (float_mem_mode[fp_indx], sizeflag); 13610 return; 13611 } 13612 /* Skip mod/rm byte. */ 13613 MODRM_CHECK; 13614 codep++; 13615 13616 dp = &float_reg[floatop - 0xd8][modrm.reg]; 13617 if (dp->name == NULL) 13618 { 13619 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); 13620 13621 /* Instruction fnstsw is only one with strange arg. */ 13622 if (floatop == 0xdf && codep[-1] == 0xe0) 13623 strcpy (op_out[0], names16[0]); 13624 } 13625 else 13626 { 13627 putop (dp->name, sizeflag); 13628 13629 obufp = op_out[0]; 13630 op_ad = 2; 13631 if (dp->op[0].rtn) 13632 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); 13633 13634 obufp = op_out[1]; 13635 op_ad = 1; 13636 if (dp->op[1].rtn) 13637 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); 13638 } 13639 } 13640 13641 /* Like oappend (below), but S is a string starting with '%'. 13642 In Intel syntax, the '%' is elided. */ 13643 static void 13644 oappend_maybe_intel (const char *s) 13645 { 13646 oappend (s + intel_syntax); 13647 } 13648 13649 static void 13650 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 13651 { 13652 oappend_maybe_intel ("%st"); 13653 } 13654 13655 static void 13656 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 13657 { 13658 sprintf (scratchbuf, "%%st(%d)", modrm.rm); 13659 oappend_maybe_intel (scratchbuf); 13660 } 13661 13662 /* Capital letters in template are macros. */ 13663 static int 13664 putop (const char *in_template, int sizeflag) 13665 { 13666 const char *p; 13667 int alt = 0; 13668 int cond = 1; 13669 unsigned int l = 0, len = 1; 13670 char last[4]; 13671 13672 #define SAVE_LAST(c) \ 13673 if (l < len && l < sizeof (last)) \ 13674 last[l++] = c; \ 13675 else \ 13676 abort (); 13677 13678 for (p = in_template; *p; p++) 13679 { 13680 switch (*p) 13681 { 13682 default: 13683 *obufp++ = *p; 13684 break; 13685 case '%': 13686 len++; 13687 break; 13688 case '!': 13689 cond = 0; 13690 break; 13691 case '{': 13692 alt = 0; 13693 if (intel_syntax) 13694 { 13695 while (*++p != '|') 13696 if (*p == '}' || *p == '\0') 13697 abort (); 13698 } 13699 /* Fall through. */ 13700 case 'I': 13701 alt = 1; 13702 continue; 13703 case '|': 13704 while (*++p != '}') 13705 { 13706 if (*p == '\0') 13707 abort (); 13708 } 13709 break; 13710 case '}': 13711 break; 13712 case 'A': 13713 if (intel_syntax) 13714 break; 13715 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 13716 *obufp++ = 'b'; 13717 break; 13718 case 'B': 13719 if (l == 0 && len == 1) 13720 { 13721 case_B: 13722 if (intel_syntax) 13723 break; 13724 if (sizeflag & SUFFIX_ALWAYS) 13725 *obufp++ = 'b'; 13726 } 13727 else 13728 { 13729 if (l != 1 13730 || len != 2 13731 || last[0] != 'L') 13732 { 13733 SAVE_LAST (*p); 13734 break; 13735 } 13736 13737 if (address_mode == mode_64bit 13738 && !(prefixes & PREFIX_ADDR)) 13739 { 13740 *obufp++ = 'a'; 13741 *obufp++ = 'b'; 13742 *obufp++ = 's'; 13743 } 13744 13745 goto case_B; 13746 } 13747 break; 13748 case 'C': 13749 if (intel_syntax && !alt) 13750 break; 13751 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 13752 { 13753 if (sizeflag & DFLAG) 13754 *obufp++ = intel_syntax ? 'd' : 'l'; 13755 else 13756 *obufp++ = intel_syntax ? 'w' : 's'; 13757 used_prefixes |= (prefixes & PREFIX_DATA); 13758 } 13759 break; 13760 case 'D': 13761 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 13762 break; 13763 USED_REX (REX_W); 13764 if (modrm.mod == 3) 13765 { 13766 if (rex & REX_W) 13767 *obufp++ = 'q'; 13768 else 13769 { 13770 if (sizeflag & DFLAG) 13771 *obufp++ = intel_syntax ? 'd' : 'l'; 13772 else 13773 *obufp++ = 'w'; 13774 used_prefixes |= (prefixes & PREFIX_DATA); 13775 } 13776 } 13777 else 13778 *obufp++ = 'w'; 13779 break; 13780 case 'E': /* For jcxz/jecxz */ 13781 if (address_mode == mode_64bit) 13782 { 13783 if (sizeflag & AFLAG) 13784 *obufp++ = 'r'; 13785 else 13786 *obufp++ = 'e'; 13787 } 13788 else 13789 if (sizeflag & AFLAG) 13790 *obufp++ = 'e'; 13791 used_prefixes |= (prefixes & PREFIX_ADDR); 13792 break; 13793 case 'F': 13794 if (intel_syntax) 13795 break; 13796 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) 13797 { 13798 if (sizeflag & AFLAG) 13799 *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; 13800 else 13801 *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; 13802 used_prefixes |= (prefixes & PREFIX_ADDR); 13803 } 13804 break; 13805 case 'G': 13806 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) 13807 break; 13808 if ((rex & REX_W) || (sizeflag & DFLAG)) 13809 *obufp++ = 'l'; 13810 else 13811 *obufp++ = 'w'; 13812 if (!(rex & REX_W)) 13813 used_prefixes |= (prefixes & PREFIX_DATA); 13814 break; 13815 case 'H': 13816 if (intel_syntax) 13817 break; 13818 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS 13819 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) 13820 { 13821 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); 13822 *obufp++ = ','; 13823 *obufp++ = 'p'; 13824 if (prefixes & PREFIX_DS) 13825 *obufp++ = 't'; 13826 else 13827 *obufp++ = 'n'; 13828 } 13829 break; 13830 case 'J': 13831 if (intel_syntax) 13832 break; 13833 *obufp++ = 'l'; 13834 break; 13835 case 'K': 13836 USED_REX (REX_W); 13837 if (rex & REX_W) 13838 *obufp++ = 'q'; 13839 else 13840 *obufp++ = 'd'; 13841 break; 13842 case 'Z': 13843 if (l != 0 || len != 1) 13844 { 13845 if (l != 1 || len != 2 || last[0] != 'X') 13846 { 13847 SAVE_LAST (*p); 13848 break; 13849 } 13850 if (!need_vex || !vex.evex) 13851 abort (); 13852 if (intel_syntax 13853 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) 13854 break; 13855 switch (vex.length) 13856 { 13857 case 128: 13858 *obufp++ = 'x'; 13859 break; 13860 case 256: 13861 *obufp++ = 'y'; 13862 break; 13863 case 512: 13864 *obufp++ = 'z'; 13865 break; 13866 default: 13867 abort (); 13868 } 13869 break; 13870 } 13871 if (intel_syntax) 13872 break; 13873 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) 13874 { 13875 *obufp++ = 'q'; 13876 break; 13877 } 13878 /* Fall through. */ 13879 goto case_L; 13880 case 'L': 13881 if (l != 0 || len != 1) 13882 { 13883 SAVE_LAST (*p); 13884 break; 13885 } 13886 case_L: 13887 if (intel_syntax) 13888 break; 13889 if (sizeflag & SUFFIX_ALWAYS) 13890 *obufp++ = 'l'; 13891 break; 13892 case 'M': 13893 if (intel_mnemonic != cond) 13894 *obufp++ = 'r'; 13895 break; 13896 case 'N': 13897 if ((prefixes & PREFIX_FWAIT) == 0) 13898 *obufp++ = 'n'; 13899 else 13900 used_prefixes |= PREFIX_FWAIT; 13901 break; 13902 case 'O': 13903 USED_REX (REX_W); 13904 if (rex & REX_W) 13905 *obufp++ = 'o'; 13906 else if (intel_syntax && (sizeflag & DFLAG)) 13907 *obufp++ = 'q'; 13908 else 13909 *obufp++ = 'd'; 13910 if (!(rex & REX_W)) 13911 used_prefixes |= (prefixes & PREFIX_DATA); 13912 break; 13913 case 'T': 13914 if (!intel_syntax 13915 && address_mode == mode_64bit 13916 && ((sizeflag & DFLAG) || (rex & REX_W))) 13917 { 13918 *obufp++ = 'q'; 13919 break; 13920 } 13921 /* Fall through. */ 13922 goto case_P; 13923 case 'P': 13924 if (l == 0 && len == 1) 13925 { 13926 case_P: 13927 if (intel_syntax) 13928 { 13929 if ((rex & REX_W) == 0 13930 && (prefixes & PREFIX_DATA)) 13931 { 13932 if ((sizeflag & DFLAG) == 0) 13933 *obufp++ = 'w'; 13934 used_prefixes |= (prefixes & PREFIX_DATA); 13935 } 13936 break; 13937 } 13938 if ((prefixes & PREFIX_DATA) 13939 || (rex & REX_W) 13940 || (sizeflag & SUFFIX_ALWAYS)) 13941 { 13942 USED_REX (REX_W); 13943 if (rex & REX_W) 13944 *obufp++ = 'q'; 13945 else 13946 { 13947 if (sizeflag & DFLAG) 13948 *obufp++ = 'l'; 13949 else 13950 *obufp++ = 'w'; 13951 used_prefixes |= (prefixes & PREFIX_DATA); 13952 } 13953 } 13954 } 13955 else 13956 { 13957 if (l != 1 || len != 2 || last[0] != 'L') 13958 { 13959 SAVE_LAST (*p); 13960 break; 13961 } 13962 13963 if ((prefixes & PREFIX_DATA) 13964 || (rex & REX_W) 13965 || (sizeflag & SUFFIX_ALWAYS)) 13966 { 13967 USED_REX (REX_W); 13968 if (rex & REX_W) 13969 *obufp++ = 'q'; 13970 else 13971 { 13972 if (sizeflag & DFLAG) 13973 *obufp++ = intel_syntax ? 'd' : 'l'; 13974 else 13975 *obufp++ = 'w'; 13976 used_prefixes |= (prefixes & PREFIX_DATA); 13977 } 13978 } 13979 } 13980 break; 13981 case 'U': 13982 if (intel_syntax) 13983 break; 13984 if (address_mode == mode_64bit 13985 && ((sizeflag & DFLAG) || (rex & REX_W))) 13986 { 13987 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 13988 *obufp++ = 'q'; 13989 break; 13990 } 13991 /* Fall through. */ 13992 goto case_Q; 13993 case 'Q': 13994 if (l == 0 && len == 1) 13995 { 13996 case_Q: 13997 if (intel_syntax && !alt) 13998 break; 13999 USED_REX (REX_W); 14000 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 14001 { 14002 if (rex & REX_W) 14003 *obufp++ = 'q'; 14004 else 14005 { 14006 if (sizeflag & DFLAG) 14007 *obufp++ = intel_syntax ? 'd' : 'l'; 14008 else 14009 *obufp++ = 'w'; 14010 used_prefixes |= (prefixes & PREFIX_DATA); 14011 } 14012 } 14013 } 14014 else 14015 { 14016 if (l != 1 || len != 2 || last[0] != 'L') 14017 { 14018 SAVE_LAST (*p); 14019 break; 14020 } 14021 if (intel_syntax 14022 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) 14023 break; 14024 if ((rex & REX_W)) 14025 { 14026 USED_REX (REX_W); 14027 *obufp++ = 'q'; 14028 } 14029 else 14030 *obufp++ = 'l'; 14031 } 14032 break; 14033 case 'R': 14034 USED_REX (REX_W); 14035 if (rex & REX_W) 14036 *obufp++ = 'q'; 14037 else if (sizeflag & DFLAG) 14038 { 14039 if (intel_syntax) 14040 *obufp++ = 'd'; 14041 else 14042 *obufp++ = 'l'; 14043 } 14044 else 14045 *obufp++ = 'w'; 14046 if (intel_syntax && !p[1] 14047 && ((rex & REX_W) || (sizeflag & DFLAG))) 14048 *obufp++ = 'e'; 14049 if (!(rex & REX_W)) 14050 used_prefixes |= (prefixes & PREFIX_DATA); 14051 break; 14052 case 'V': 14053 if (l == 0 && len == 1) 14054 { 14055 if (intel_syntax) 14056 break; 14057 if (address_mode == mode_64bit 14058 && ((sizeflag & DFLAG) || (rex & REX_W))) 14059 { 14060 if (sizeflag & SUFFIX_ALWAYS) 14061 *obufp++ = 'q'; 14062 break; 14063 } 14064 } 14065 else 14066 { 14067 if (l != 1 14068 || len != 2 14069 || last[0] != 'L') 14070 { 14071 SAVE_LAST (*p); 14072 break; 14073 } 14074 14075 if (rex & REX_W) 14076 { 14077 *obufp++ = 'a'; 14078 *obufp++ = 'b'; 14079 *obufp++ = 's'; 14080 } 14081 } 14082 /* Fall through. */ 14083 goto case_S; 14084 case 'S': 14085 if (l == 0 && len == 1) 14086 { 14087 case_S: 14088 if (intel_syntax) 14089 break; 14090 if (sizeflag & SUFFIX_ALWAYS) 14091 { 14092 if (rex & REX_W) 14093 *obufp++ = 'q'; 14094 else 14095 { 14096 if (sizeflag & DFLAG) 14097 *obufp++ = 'l'; 14098 else 14099 *obufp++ = 'w'; 14100 used_prefixes |= (prefixes & PREFIX_DATA); 14101 } 14102 } 14103 } 14104 else 14105 { 14106 if (l != 1 14107 || len != 2 14108 || last[0] != 'L') 14109 { 14110 SAVE_LAST (*p); 14111 break; 14112 } 14113 14114 if (address_mode == mode_64bit 14115 && !(prefixes & PREFIX_ADDR)) 14116 { 14117 *obufp++ = 'a'; 14118 *obufp++ = 'b'; 14119 *obufp++ = 's'; 14120 } 14121 14122 goto case_S; 14123 } 14124 break; 14125 case 'X': 14126 if (l != 0 || len != 1) 14127 { 14128 SAVE_LAST (*p); 14129 break; 14130 } 14131 if (need_vex && vex.prefix) 14132 { 14133 if (vex.prefix == DATA_PREFIX_OPCODE) 14134 *obufp++ = 'd'; 14135 else 14136 *obufp++ = 's'; 14137 } 14138 else 14139 { 14140 if (prefixes & PREFIX_DATA) 14141 *obufp++ = 'd'; 14142 else 14143 *obufp++ = 's'; 14144 used_prefixes |= (prefixes & PREFIX_DATA); 14145 } 14146 break; 14147 case 'Y': 14148 if (l == 0 && len == 1) 14149 { 14150 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 14151 break; 14152 if (rex & REX_W) 14153 { 14154 USED_REX (REX_W); 14155 *obufp++ = 'q'; 14156 } 14157 break; 14158 } 14159 else 14160 { 14161 if (l != 1 || len != 2 || last[0] != 'X') 14162 { 14163 SAVE_LAST (*p); 14164 break; 14165 } 14166 if (!need_vex) 14167 abort (); 14168 if (intel_syntax 14169 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) 14170 break; 14171 switch (vex.length) 14172 { 14173 case 128: 14174 *obufp++ = 'x'; 14175 break; 14176 case 256: 14177 *obufp++ = 'y'; 14178 break; 14179 case 512: 14180 if (!vex.evex) 14181 default: 14182 abort (); 14183 } 14184 } 14185 break; 14186 case 'W': 14187 if (l == 0 && len == 1) 14188 { 14189 /* operand size flag for cwtl, cbtw */ 14190 USED_REX (REX_W); 14191 if (rex & REX_W) 14192 { 14193 if (intel_syntax) 14194 *obufp++ = 'd'; 14195 else 14196 *obufp++ = 'l'; 14197 } 14198 else if (sizeflag & DFLAG) 14199 *obufp++ = 'w'; 14200 else 14201 *obufp++ = 'b'; 14202 if (!(rex & REX_W)) 14203 used_prefixes |= (prefixes & PREFIX_DATA); 14204 } 14205 else 14206 { 14207 if (l != 1 14208 || len != 2 14209 || (last[0] != 'X' 14210 && last[0] != 'L')) 14211 { 14212 SAVE_LAST (*p); 14213 break; 14214 } 14215 if (!need_vex) 14216 abort (); 14217 if (last[0] == 'X') 14218 *obufp++ = vex.w ? 'd': 's'; 14219 else 14220 *obufp++ = vex.w ? 'q': 'd'; 14221 } 14222 break; 14223 case '^': 14224 if (intel_syntax) 14225 break; 14226 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 14227 { 14228 if (sizeflag & DFLAG) 14229 *obufp++ = 'l'; 14230 else 14231 *obufp++ = 'w'; 14232 used_prefixes |= (prefixes & PREFIX_DATA); 14233 } 14234 break; 14235 case '@': 14236 if (intel_syntax) 14237 break; 14238 if (address_mode == mode_64bit 14239 && (isa64 == intel64 14240 || ((sizeflag & DFLAG) || (rex & REX_W)))) 14241 *obufp++ = 'q'; 14242 else if ((prefixes & PREFIX_DATA)) 14243 { 14244 if (!(sizeflag & DFLAG)) 14245 *obufp++ = 'w'; 14246 used_prefixes |= (prefixes & PREFIX_DATA); 14247 } 14248 break; 14249 } 14250 alt = 0; 14251 } 14252 *obufp = 0; 14253 mnemonicendp = obufp; 14254 return 0; 14255 } 14256 14257 static void 14258 oappend (const char *s) 14259 { 14260 obufp = stpcpy (obufp, s); 14261 } 14262 14263 static void 14264 append_seg (void) 14265 { 14266 /* Only print the active segment register. */ 14267 if (!active_seg_prefix) 14268 return; 14269 14270 used_prefixes |= active_seg_prefix; 14271 switch (active_seg_prefix) 14272 { 14273 case PREFIX_CS: 14274 oappend_maybe_intel ("%cs:"); 14275 break; 14276 case PREFIX_DS: 14277 oappend_maybe_intel ("%ds:"); 14278 break; 14279 case PREFIX_SS: 14280 oappend_maybe_intel ("%ss:"); 14281 break; 14282 case PREFIX_ES: 14283 oappend_maybe_intel ("%es:"); 14284 break; 14285 case PREFIX_FS: 14286 oappend_maybe_intel ("%fs:"); 14287 break; 14288 case PREFIX_GS: 14289 oappend_maybe_intel ("%gs:"); 14290 break; 14291 default: 14292 break; 14293 } 14294 } 14295 14296 static void 14297 OP_indirE (int bytemode, int sizeflag) 14298 { 14299 if (!intel_syntax) 14300 oappend ("*"); 14301 OP_E (bytemode, sizeflag); 14302 } 14303 14304 static void 14305 print_operand_value (char *buf, int hex, bfd_vma disp) 14306 { 14307 if (address_mode == mode_64bit) 14308 { 14309 if (hex) 14310 { 14311 char tmp[30]; 14312 int i; 14313 buf[0] = '0'; 14314 buf[1] = 'x'; 14315 sprintf_vma (tmp, disp); 14316 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); 14317 strcpy (buf + 2, tmp + i); 14318 } 14319 else 14320 { 14321 bfd_signed_vma v = disp; 14322 char tmp[30]; 14323 int i; 14324 if (v < 0) 14325 { 14326 *(buf++) = '-'; 14327 v = -disp; 14328 /* Check for possible overflow on 0x8000000000000000. */ 14329 if (v < 0) 14330 { 14331 strcpy (buf, "9223372036854775808"); 14332 return; 14333 } 14334 } 14335 if (!v) 14336 { 14337 strcpy (buf, "0"); 14338 return; 14339 } 14340 14341 i = 0; 14342 tmp[29] = 0; 14343 while (v) 14344 { 14345 tmp[28 - i] = (v % 10) + '0'; 14346 v /= 10; 14347 i++; 14348 } 14349 strcpy (buf, tmp + 29 - i); 14350 } 14351 } 14352 else 14353 { 14354 if (hex) 14355 sprintf (buf, "0x%x", (unsigned int) disp); 14356 else 14357 sprintf (buf, "%d", (int) disp); 14358 } 14359 } 14360 14361 /* Put DISP in BUF as signed hex number. */ 14362 14363 static void 14364 print_displacement (char *buf, bfd_vma disp) 14365 { 14366 bfd_signed_vma val = disp; 14367 char tmp[30]; 14368 int i, j = 0; 14369 14370 if (val < 0) 14371 { 14372 buf[j++] = '-'; 14373 val = -disp; 14374 14375 /* Check for possible overflow. */ 14376 if (val < 0) 14377 { 14378 switch (address_mode) 14379 { 14380 case mode_64bit: 14381 strcpy (buf + j, "0x8000000000000000"); 14382 break; 14383 case mode_32bit: 14384 strcpy (buf + j, "0x80000000"); 14385 break; 14386 case mode_16bit: 14387 strcpy (buf + j, "0x8000"); 14388 break; 14389 } 14390 return; 14391 } 14392 } 14393 14394 buf[j++] = '0'; 14395 buf[j++] = 'x'; 14396 14397 sprintf_vma (tmp, (bfd_vma) val); 14398 for (i = 0; tmp[i] == '0'; i++) 14399 continue; 14400 if (tmp[i] == '\0') 14401 i--; 14402 strcpy (buf + j, tmp + i); 14403 } 14404 14405 static void 14406 intel_operand_size (int bytemode, int sizeflag) 14407 { 14408 if (vex.evex 14409 && vex.b 14410 && (bytemode == x_mode 14411 || bytemode == evex_half_bcst_xmmq_mode)) 14412 { 14413 if (vex.w) 14414 oappend ("QWORD PTR "); 14415 else 14416 oappend ("DWORD PTR "); 14417 return; 14418 } 14419 switch (bytemode) 14420 { 14421 case b_mode: 14422 case b_swap_mode: 14423 case dqb_mode: 14424 case db_mode: 14425 oappend ("BYTE PTR "); 14426 break; 14427 case w_mode: 14428 case dw_mode: 14429 case dqw_mode: 14430 case dqw_swap_mode: 14431 oappend ("WORD PTR "); 14432 break; 14433 case stack_v_mode: 14434 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) 14435 { 14436 oappend ("QWORD PTR "); 14437 break; 14438 } 14439 /* FALLTHRU */ 14440 case v_mode: 14441 case v_swap_mode: 14442 case dq_mode: 14443 USED_REX (REX_W); 14444 if (rex & REX_W) 14445 oappend ("QWORD PTR "); 14446 else 14447 { 14448 if ((sizeflag & DFLAG) || bytemode == dq_mode) 14449 oappend ("DWORD PTR "); 14450 else 14451 oappend ("WORD PTR "); 14452 used_prefixes |= (prefixes & PREFIX_DATA); 14453 } 14454 break; 14455 case z_mode: 14456 if ((rex & REX_W) || (sizeflag & DFLAG)) 14457 *obufp++ = 'D'; 14458 oappend ("WORD PTR "); 14459 if (!(rex & REX_W)) 14460 used_prefixes |= (prefixes & PREFIX_DATA); 14461 break; 14462 case a_mode: 14463 if (sizeflag & DFLAG) 14464 oappend ("QWORD PTR "); 14465 else 14466 oappend ("DWORD PTR "); 14467 used_prefixes |= (prefixes & PREFIX_DATA); 14468 break; 14469 case d_mode: 14470 case d_scalar_mode: 14471 case d_scalar_swap_mode: 14472 case d_swap_mode: 14473 case dqd_mode: 14474 oappend ("DWORD PTR "); 14475 break; 14476 case q_mode: 14477 case q_scalar_mode: 14478 case q_scalar_swap_mode: 14479 case q_swap_mode: 14480 oappend ("QWORD PTR "); 14481 break; 14482 case m_mode: 14483 if (address_mode == mode_64bit) 14484 oappend ("QWORD PTR "); 14485 else 14486 oappend ("DWORD PTR "); 14487 break; 14488 case f_mode: 14489 if (sizeflag & DFLAG) 14490 oappend ("FWORD PTR "); 14491 else 14492 oappend ("DWORD PTR "); 14493 used_prefixes |= (prefixes & PREFIX_DATA); 14494 break; 14495 case t_mode: 14496 oappend ("TBYTE PTR "); 14497 break; 14498 case x_mode: 14499 case x_swap_mode: 14500 case evex_x_gscat_mode: 14501 case evex_x_nobcst_mode: 14502 if (need_vex) 14503 { 14504 switch (vex.length) 14505 { 14506 case 128: 14507 oappend ("XMMWORD PTR "); 14508 break; 14509 case 256: 14510 oappend ("YMMWORD PTR "); 14511 break; 14512 case 512: 14513 oappend ("ZMMWORD PTR "); 14514 break; 14515 default: 14516 abort (); 14517 } 14518 } 14519 else 14520 oappend ("XMMWORD PTR "); 14521 break; 14522 case xmm_mode: 14523 oappend ("XMMWORD PTR "); 14524 break; 14525 case ymm_mode: 14526 oappend ("YMMWORD PTR "); 14527 break; 14528 case xmmq_mode: 14529 case evex_half_bcst_xmmq_mode: 14530 if (!need_vex) 14531 abort (); 14532 14533 switch (vex.length) 14534 { 14535 case 128: 14536 oappend ("QWORD PTR "); 14537 break; 14538 case 256: 14539 oappend ("XMMWORD PTR "); 14540 break; 14541 case 512: 14542 oappend ("YMMWORD PTR "); 14543 break; 14544 default: 14545 abort (); 14546 } 14547 break; 14548 case xmm_mb_mode: 14549 if (!need_vex) 14550 abort (); 14551 14552 switch (vex.length) 14553 { 14554 case 128: 14555 case 256: 14556 case 512: 14557 oappend ("BYTE PTR "); 14558 break; 14559 default: 14560 abort (); 14561 } 14562 break; 14563 case xmm_mw_mode: 14564 if (!need_vex) 14565 abort (); 14566 14567 switch (vex.length) 14568 { 14569 case 128: 14570 case 256: 14571 case 512: 14572 oappend ("WORD PTR "); 14573 break; 14574 default: 14575 abort (); 14576 } 14577 break; 14578 case xmm_md_mode: 14579 if (!need_vex) 14580 abort (); 14581 14582 switch (vex.length) 14583 { 14584 case 128: 14585 case 256: 14586 case 512: 14587 oappend ("DWORD PTR "); 14588 break; 14589 default: 14590 abort (); 14591 } 14592 break; 14593 case xmm_mq_mode: 14594 if (!need_vex) 14595 abort (); 14596 14597 switch (vex.length) 14598 { 14599 case 128: 14600 case 256: 14601 case 512: 14602 oappend ("QWORD PTR "); 14603 break; 14604 default: 14605 abort (); 14606 } 14607 break; 14608 case xmmdw_mode: 14609 if (!need_vex) 14610 abort (); 14611 14612 switch (vex.length) 14613 { 14614 case 128: 14615 oappend ("WORD PTR "); 14616 break; 14617 case 256: 14618 oappend ("DWORD PTR "); 14619 break; 14620 case 512: 14621 oappend ("QWORD PTR "); 14622 break; 14623 default: 14624 abort (); 14625 } 14626 break; 14627 case xmmqd_mode: 14628 if (!need_vex) 14629 abort (); 14630 14631 switch (vex.length) 14632 { 14633 case 128: 14634 oappend ("DWORD PTR "); 14635 break; 14636 case 256: 14637 oappend ("QWORD PTR "); 14638 break; 14639 case 512: 14640 oappend ("XMMWORD PTR "); 14641 break; 14642 default: 14643 abort (); 14644 } 14645 break; 14646 case ymmq_mode: 14647 if (!need_vex) 14648 abort (); 14649 14650 switch (vex.length) 14651 { 14652 case 128: 14653 oappend ("QWORD PTR "); 14654 break; 14655 case 256: 14656 oappend ("YMMWORD PTR "); 14657 break; 14658 case 512: 14659 oappend ("ZMMWORD PTR "); 14660 break; 14661 default: 14662 abort (); 14663 } 14664 break; 14665 case ymmxmm_mode: 14666 if (!need_vex) 14667 abort (); 14668 14669 switch (vex.length) 14670 { 14671 case 128: 14672 case 256: 14673 oappend ("XMMWORD PTR "); 14674 break; 14675 default: 14676 abort (); 14677 } 14678 break; 14679 case o_mode: 14680 oappend ("OWORD PTR "); 14681 break; 14682 case xmm_mdq_mode: 14683 case vex_w_dq_mode: 14684 case vex_scalar_w_dq_mode: 14685 if (!need_vex) 14686 abort (); 14687 14688 if (vex.w) 14689 oappend ("QWORD PTR "); 14690 else 14691 oappend ("DWORD PTR "); 14692 break; 14693 case vex_vsib_d_w_dq_mode: 14694 case vex_vsib_q_w_dq_mode: 14695 if (!need_vex) 14696 abort (); 14697 14698 if (!vex.evex) 14699 { 14700 if (vex.w) 14701 oappend ("QWORD PTR "); 14702 else 14703 oappend ("DWORD PTR "); 14704 } 14705 else 14706 { 14707 switch (vex.length) 14708 { 14709 case 128: 14710 oappend ("XMMWORD PTR "); 14711 break; 14712 case 256: 14713 oappend ("YMMWORD PTR "); 14714 break; 14715 case 512: 14716 oappend ("ZMMWORD PTR "); 14717 break; 14718 default: 14719 abort (); 14720 } 14721 } 14722 break; 14723 case vex_vsib_q_w_d_mode: 14724 case vex_vsib_d_w_d_mode: 14725 if (!need_vex || !vex.evex) 14726 abort (); 14727 14728 switch (vex.length) 14729 { 14730 case 128: 14731 oappend ("QWORD PTR "); 14732 break; 14733 case 256: 14734 oappend ("XMMWORD PTR "); 14735 break; 14736 case 512: 14737 oappend ("YMMWORD PTR "); 14738 break; 14739 default: 14740 abort (); 14741 } 14742 14743 break; 14744 case mask_bd_mode: 14745 if (!need_vex || vex.length != 128) 14746 abort (); 14747 if (vex.w) 14748 oappend ("DWORD PTR "); 14749 else 14750 oappend ("BYTE PTR "); 14751 break; 14752 case mask_mode: 14753 if (!need_vex) 14754 abort (); 14755 if (vex.w) 14756 oappend ("QWORD PTR "); 14757 else 14758 oappend ("WORD PTR "); 14759 break; 14760 case v_bnd_mode: 14761 default: 14762 break; 14763 } 14764 } 14765 14766 static void 14767 OP_E_register (int bytemode, int sizeflag) 14768 { 14769 int reg = modrm.rm; 14770 const char **names; 14771 14772 USED_REX (REX_B); 14773 if ((rex & REX_B)) 14774 reg += 8; 14775 14776 if ((sizeflag & SUFFIX_ALWAYS) 14777 && (bytemode == b_swap_mode 14778 || bytemode == v_swap_mode 14779 || bytemode == dqw_swap_mode)) 14780 swap_operand (); 14781 14782 switch (bytemode) 14783 { 14784 case b_mode: 14785 case b_swap_mode: 14786 USED_REX (0); 14787 if (rex) 14788 names = names8rex; 14789 else 14790 names = names8; 14791 break; 14792 case w_mode: 14793 names = names16; 14794 break; 14795 case d_mode: 14796 case dw_mode: 14797 case db_mode: 14798 names = names32; 14799 break; 14800 case q_mode: 14801 names = names64; 14802 break; 14803 case m_mode: 14804 case v_bnd_mode: 14805 names = address_mode == mode_64bit ? names64 : names32; 14806 break; 14807 case bnd_mode: 14808 names = names_bnd; 14809 break; 14810 case stack_v_mode: 14811 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) 14812 { 14813 names = names64; 14814 break; 14815 } 14816 bytemode = v_mode; 14817 /* FALLTHRU */ 14818 case v_mode: 14819 case v_swap_mode: 14820 case dq_mode: 14821 case dqb_mode: 14822 case dqd_mode: 14823 case dqw_mode: 14824 case dqw_swap_mode: 14825 USED_REX (REX_W); 14826 if (rex & REX_W) 14827 names = names64; 14828 else 14829 { 14830 if ((sizeflag & DFLAG) 14831 || (bytemode != v_mode 14832 && bytemode != v_swap_mode)) 14833 names = names32; 14834 else 14835 names = names16; 14836 used_prefixes |= (prefixes & PREFIX_DATA); 14837 } 14838 break; 14839 case mask_bd_mode: 14840 case mask_mode: 14841 names = names_mask; 14842 break; 14843 case 0: 14844 return; 14845 default: 14846 oappend (INTERNAL_DISASSEMBLER_ERROR); 14847 return; 14848 } 14849 oappend (names[reg]); 14850 } 14851 14852 static void 14853 OP_E_memory (int bytemode, int sizeflag) 14854 { 14855 bfd_vma disp = 0; 14856 int add = (rex & REX_B) ? 8 : 0; 14857 int riprel = 0; 14858 int shift; 14859 14860 if (vex.evex) 14861 { 14862 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ 14863 if (vex.b 14864 && bytemode != x_mode 14865 && bytemode != xmmq_mode 14866 && bytemode != evex_half_bcst_xmmq_mode) 14867 { 14868 BadOp (); 14869 return; 14870 } 14871 switch (bytemode) 14872 { 14873 case dqw_mode: 14874 case dw_mode: 14875 case dqw_swap_mode: 14876 shift = 1; 14877 break; 14878 case dqb_mode: 14879 case db_mode: 14880 shift = 0; 14881 break; 14882 case vex_vsib_d_w_dq_mode: 14883 case vex_vsib_d_w_d_mode: 14884 case vex_vsib_q_w_dq_mode: 14885 case vex_vsib_q_w_d_mode: 14886 case evex_x_gscat_mode: 14887 case xmm_mdq_mode: 14888 shift = vex.w ? 3 : 2; 14889 break; 14890 case x_mode: 14891 case evex_half_bcst_xmmq_mode: 14892 case xmmq_mode: 14893 if (vex.b) 14894 { 14895 shift = vex.w ? 3 : 2; 14896 break; 14897 } 14898 /* Fall through if vex.b == 0. */ 14899 case xmmqd_mode: 14900 case xmmdw_mode: 14901 case ymmq_mode: 14902 case evex_x_nobcst_mode: 14903 case x_swap_mode: 14904 switch (vex.length) 14905 { 14906 case 128: 14907 shift = 4; 14908 break; 14909 case 256: 14910 shift = 5; 14911 break; 14912 case 512: 14913 shift = 6; 14914 break; 14915 default: 14916 abort (); 14917 } 14918 break; 14919 case ymm_mode: 14920 shift = 5; 14921 break; 14922 case xmm_mode: 14923 shift = 4; 14924 break; 14925 case xmm_mq_mode: 14926 case q_mode: 14927 case q_scalar_mode: 14928 case q_swap_mode: 14929 case q_scalar_swap_mode: 14930 shift = 3; 14931 break; 14932 case dqd_mode: 14933 case xmm_md_mode: 14934 case d_mode: 14935 case d_scalar_mode: 14936 case d_swap_mode: 14937 case d_scalar_swap_mode: 14938 shift = 2; 14939 break; 14940 case xmm_mw_mode: 14941 shift = 1; 14942 break; 14943 case xmm_mb_mode: 14944 shift = 0; 14945 break; 14946 default: 14947 abort (); 14948 } 14949 /* Make necessary corrections to shift for modes that need it. 14950 For these modes we currently have shift 4, 5 or 6 depending on 14951 vex.length (it corresponds to xmmword, ymmword or zmmword 14952 operand). We might want to make it 3, 4 or 5 (e.g. for 14953 xmmq_mode). In case of broadcast enabled the corrections 14954 aren't needed, as element size is always 32 or 64 bits. */ 14955 if (!vex.b 14956 && (bytemode == xmmq_mode 14957 || bytemode == evex_half_bcst_xmmq_mode)) 14958 shift -= 1; 14959 else if (bytemode == xmmqd_mode) 14960 shift -= 2; 14961 else if (bytemode == xmmdw_mode) 14962 shift -= 3; 14963 else if (bytemode == ymmq_mode && vex.length == 128) 14964 shift -= 1; 14965 } 14966 else 14967 shift = 0; 14968 14969 USED_REX (REX_B); 14970 if (intel_syntax) 14971 intel_operand_size (bytemode, sizeflag); 14972 append_seg (); 14973 14974 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 14975 { 14976 /* 32/64 bit address mode */ 14977 int havedisp; 14978 int havesib; 14979 int havebase; 14980 int haveindex; 14981 int needindex; 14982 int base, rbase; 14983 int vindex = 0; 14984 int scale = 0; 14985 int addr32flag = !((sizeflag & AFLAG) 14986 || bytemode == v_bnd_mode 14987 || bytemode == bnd_mode); 14988 const char **indexes64 = names64; 14989 const char **indexes32 = names32; 14990 14991 havesib = 0; 14992 havebase = 1; 14993 haveindex = 0; 14994 base = modrm.rm; 14995 14996 if (base == 4) 14997 { 14998 havesib = 1; 14999 vindex = sib.index; 15000 USED_REX (REX_X); 15001 if (rex & REX_X) 15002 vindex += 8; 15003 switch (bytemode) 15004 { 15005 case vex_vsib_d_w_dq_mode: 15006 case vex_vsib_d_w_d_mode: 15007 case vex_vsib_q_w_dq_mode: 15008 case vex_vsib_q_w_d_mode: 15009 if (!need_vex) 15010 abort (); 15011 if (vex.evex) 15012 { 15013 if (!vex.v) 15014 vindex += 16; 15015 } 15016 15017 haveindex = 1; 15018 switch (vex.length) 15019 { 15020 case 128: 15021 indexes64 = indexes32 = names_xmm; 15022 break; 15023 case 256: 15024 if (!vex.w 15025 || bytemode == vex_vsib_q_w_dq_mode 15026 || bytemode == vex_vsib_q_w_d_mode) 15027 indexes64 = indexes32 = names_ymm; 15028 else 15029 indexes64 = indexes32 = names_xmm; 15030 break; 15031 case 512: 15032 if (!vex.w 15033 || bytemode == vex_vsib_q_w_dq_mode 15034 || bytemode == vex_vsib_q_w_d_mode) 15035 indexes64 = indexes32 = names_zmm; 15036 else 15037 indexes64 = indexes32 = names_ymm; 15038 break; 15039 default: 15040 abort (); 15041 } 15042 break; 15043 default: 15044 haveindex = vindex != 4; 15045 break; 15046 } 15047 scale = sib.scale; 15048 base = sib.base; 15049 codep++; 15050 } 15051 rbase = base + add; 15052 15053 switch (modrm.mod) 15054 { 15055 case 0: 15056 if (base == 5) 15057 { 15058 havebase = 0; 15059 if (address_mode == mode_64bit && !havesib) 15060 riprel = 1; 15061 disp = get32s (); 15062 } 15063 break; 15064 case 1: 15065 FETCH_DATA (the_info, codep + 1); 15066 disp = *codep++; 15067 if ((disp & 0x80) != 0) 15068 disp -= 0x100; 15069 if (vex.evex && shift > 0) 15070 disp <<= shift; 15071 break; 15072 case 2: 15073 disp = get32s (); 15074 break; 15075 } 15076 15077 /* In 32bit mode, we need index register to tell [offset] from 15078 [eiz*1 + offset]. */ 15079 needindex = (havesib 15080 && !havebase 15081 && !haveindex 15082 && address_mode == mode_32bit); 15083 havedisp = (havebase 15084 || needindex 15085 || (havesib && (haveindex || scale != 0))); 15086 15087 if (!intel_syntax) 15088 if (modrm.mod != 0 || base == 5) 15089 { 15090 if (havedisp || riprel) 15091 print_displacement (scratchbuf, disp); 15092 else 15093 print_operand_value (scratchbuf, 1, disp); 15094 oappend (scratchbuf); 15095 if (riprel) 15096 { 15097 set_op (disp, 1); 15098 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); 15099 } 15100 } 15101 15102 if ((havebase || haveindex || riprel) 15103 && (bytemode != v_bnd_mode) 15104 && (bytemode != bnd_mode)) 15105 used_prefixes |= PREFIX_ADDR; 15106 15107 if (havedisp || (intel_syntax && riprel)) 15108 { 15109 *obufp++ = open_char; 15110 if (intel_syntax && riprel) 15111 { 15112 set_op (disp, 1); 15113 oappend (sizeflag & AFLAG ? "rip" : "eip"); 15114 } 15115 *obufp = '\0'; 15116 if (havebase) 15117 oappend (address_mode == mode_64bit && !addr32flag 15118 ? names64[rbase] : names32[rbase]); 15119 if (havesib) 15120 { 15121 /* ESP/RSP won't allow index. If base isn't ESP/RSP, 15122 print index to tell base + index from base. */ 15123 if (scale != 0 15124 || needindex 15125 || haveindex 15126 || (havebase && base != ESP_REG_NUM)) 15127 { 15128 if (!intel_syntax || havebase) 15129 { 15130 *obufp++ = separator_char; 15131 *obufp = '\0'; 15132 } 15133 if (haveindex) 15134 oappend (address_mode == mode_64bit && !addr32flag 15135 ? indexes64[vindex] : indexes32[vindex]); 15136 else 15137 oappend (address_mode == mode_64bit && !addr32flag 15138 ? index64 : index32); 15139 15140 *obufp++ = scale_char; 15141 *obufp = '\0'; 15142 sprintf (scratchbuf, "%d", 1 << scale); 15143 oappend (scratchbuf); 15144 } 15145 } 15146 if (intel_syntax 15147 && (disp || modrm.mod != 0 || base == 5)) 15148 { 15149 if (!havedisp || (bfd_signed_vma) disp >= 0) 15150 { 15151 *obufp++ = '+'; 15152 *obufp = '\0'; 15153 } 15154 else if (modrm.mod != 1 && disp != -disp) 15155 { 15156 *obufp++ = '-'; 15157 *obufp = '\0'; 15158 disp = - (bfd_signed_vma) disp; 15159 } 15160 15161 if (havedisp) 15162 print_displacement (scratchbuf, disp); 15163 else 15164 print_operand_value (scratchbuf, 1, disp); 15165 oappend (scratchbuf); 15166 } 15167 15168 *obufp++ = close_char; 15169 *obufp = '\0'; 15170 } 15171 else if (intel_syntax) 15172 { 15173 if (modrm.mod != 0 || base == 5) 15174 { 15175 if (!active_seg_prefix) 15176 { 15177 oappend (names_seg[ds_reg - es_reg]); 15178 oappend (":"); 15179 } 15180 print_operand_value (scratchbuf, 1, disp); 15181 oappend (scratchbuf); 15182 } 15183 } 15184 } 15185 else 15186 { 15187 /* 16 bit address mode */ 15188 used_prefixes |= prefixes & PREFIX_ADDR; 15189 switch (modrm.mod) 15190 { 15191 case 0: 15192 if (modrm.rm == 6) 15193 { 15194 disp = get16 (); 15195 if ((disp & 0x8000) != 0) 15196 disp -= 0x10000; 15197 } 15198 break; 15199 case 1: 15200 FETCH_DATA (the_info, codep + 1); 15201 disp = *codep++; 15202 if ((disp & 0x80) != 0) 15203 disp -= 0x100; 15204 break; 15205 case 2: 15206 disp = get16 (); 15207 if ((disp & 0x8000) != 0) 15208 disp -= 0x10000; 15209 break; 15210 } 15211 15212 if (!intel_syntax) 15213 if (modrm.mod != 0 || modrm.rm == 6) 15214 { 15215 print_displacement (scratchbuf, disp); 15216 oappend (scratchbuf); 15217 } 15218 15219 if (modrm.mod != 0 || modrm.rm != 6) 15220 { 15221 *obufp++ = open_char; 15222 *obufp = '\0'; 15223 oappend (index16[modrm.rm]); 15224 if (intel_syntax 15225 && (disp || modrm.mod != 0 || modrm.rm == 6)) 15226 { 15227 if ((bfd_signed_vma) disp >= 0) 15228 { 15229 *obufp++ = '+'; 15230 *obufp = '\0'; 15231 } 15232 else if (modrm.mod != 1) 15233 { 15234 *obufp++ = '-'; 15235 *obufp = '\0'; 15236 disp = - (bfd_signed_vma) disp; 15237 } 15238 15239 print_displacement (scratchbuf, disp); 15240 oappend (scratchbuf); 15241 } 15242 15243 *obufp++ = close_char; 15244 *obufp = '\0'; 15245 } 15246 else if (intel_syntax) 15247 { 15248 if (!active_seg_prefix) 15249 { 15250 oappend (names_seg[ds_reg - es_reg]); 15251 oappend (":"); 15252 } 15253 print_operand_value (scratchbuf, 1, disp & 0xffff); 15254 oappend (scratchbuf); 15255 } 15256 } 15257 if (vex.evex && vex.b 15258 && (bytemode == x_mode 15259 || bytemode == xmmq_mode 15260 || bytemode == evex_half_bcst_xmmq_mode)) 15261 { 15262 if (vex.w 15263 || bytemode == xmmq_mode 15264 || bytemode == evex_half_bcst_xmmq_mode) 15265 { 15266 switch (vex.length) 15267 { 15268 case 128: 15269 oappend ("{1to2}"); 15270 break; 15271 case 256: 15272 oappend ("{1to4}"); 15273 break; 15274 case 512: 15275 oappend ("{1to8}"); 15276 break; 15277 default: 15278 abort (); 15279 } 15280 } 15281 else 15282 { 15283 switch (vex.length) 15284 { 15285 case 128: 15286 oappend ("{1to4}"); 15287 break; 15288 case 256: 15289 oappend ("{1to8}"); 15290 break; 15291 case 512: 15292 oappend ("{1to16}"); 15293 break; 15294 default: 15295 abort (); 15296 } 15297 } 15298 } 15299 } 15300 15301 static void 15302 OP_E (int bytemode, int sizeflag) 15303 { 15304 /* Skip mod/rm byte. */ 15305 MODRM_CHECK; 15306 codep++; 15307 15308 if (modrm.mod == 3) 15309 OP_E_register (bytemode, sizeflag); 15310 else 15311 OP_E_memory (bytemode, sizeflag); 15312 } 15313 15314 static void 15315 OP_G (int bytemode, int sizeflag) 15316 { 15317 int add = 0; 15318 USED_REX (REX_R); 15319 if (rex & REX_R) 15320 add += 8; 15321 switch (bytemode) 15322 { 15323 case b_mode: 15324 USED_REX (0); 15325 if (rex) 15326 oappend (names8rex[modrm.reg + add]); 15327 else 15328 oappend (names8[modrm.reg + add]); 15329 break; 15330 case w_mode: 15331 oappend (names16[modrm.reg + add]); 15332 break; 15333 case d_mode: 15334 case db_mode: 15335 case dw_mode: 15336 oappend (names32[modrm.reg + add]); 15337 break; 15338 case q_mode: 15339 oappend (names64[modrm.reg + add]); 15340 break; 15341 case bnd_mode: 15342 oappend (names_bnd[modrm.reg]); 15343 break; 15344 case v_mode: 15345 case dq_mode: 15346 case dqb_mode: 15347 case dqd_mode: 15348 case dqw_mode: 15349 case dqw_swap_mode: 15350 USED_REX (REX_W); 15351 if (rex & REX_W) 15352 oappend (names64[modrm.reg + add]); 15353 else 15354 { 15355 if ((sizeflag & DFLAG) || bytemode != v_mode) 15356 oappend (names32[modrm.reg + add]); 15357 else 15358 oappend (names16[modrm.reg + add]); 15359 used_prefixes |= (prefixes & PREFIX_DATA); 15360 } 15361 break; 15362 case m_mode: 15363 if (address_mode == mode_64bit) 15364 oappend (names64[modrm.reg + add]); 15365 else 15366 oappend (names32[modrm.reg + add]); 15367 break; 15368 case mask_bd_mode: 15369 case mask_mode: 15370 oappend (names_mask[modrm.reg + add]); 15371 break; 15372 default: 15373 oappend (INTERNAL_DISASSEMBLER_ERROR); 15374 break; 15375 } 15376 } 15377 15378 static bfd_vma 15379 get64 (void) 15380 { 15381 bfd_vma x; 15382 #ifdef BFD64 15383 unsigned int a; 15384 unsigned int b; 15385 15386 FETCH_DATA (the_info, codep + 8); 15387 a = *codep++ & 0xff; 15388 a |= (*codep++ & 0xff) << 8; 15389 a |= (*codep++ & 0xff) << 16; 15390 a |= (*codep++ & 0xff) << 24; 15391 b = *codep++ & 0xff; 15392 b |= (*codep++ & 0xff) << 8; 15393 b |= (*codep++ & 0xff) << 16; 15394 b |= (*codep++ & 0xff) << 24; 15395 x = a + ((bfd_vma) b << 32); 15396 #else 15397 abort (); 15398 x = 0; 15399 #endif 15400 return x; 15401 } 15402 15403 static bfd_signed_vma 15404 get32 (void) 15405 { 15406 bfd_signed_vma x = 0; 15407 15408 FETCH_DATA (the_info, codep + 4); 15409 x = *codep++ & (bfd_signed_vma) 0xff; 15410 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 15411 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 15412 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 15413 return x; 15414 } 15415 15416 static bfd_signed_vma 15417 get32s (void) 15418 { 15419 bfd_signed_vma x = 0; 15420 15421 FETCH_DATA (the_info, codep + 4); 15422 x = *codep++ & (bfd_signed_vma) 0xff; 15423 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 15424 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 15425 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 15426 15427 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); 15428 15429 return x; 15430 } 15431 15432 static int 15433 get16 (void) 15434 { 15435 int x = 0; 15436 15437 FETCH_DATA (the_info, codep + 2); 15438 x = *codep++ & 0xff; 15439 x |= (*codep++ & 0xff) << 8; 15440 return x; 15441 } 15442 15443 static void 15444 set_op (bfd_vma op, int riprel) 15445 { 15446 op_index[op_ad] = op_ad; 15447 if (address_mode == mode_64bit) 15448 { 15449 op_address[op_ad] = op; 15450 op_riprel[op_ad] = riprel; 15451 } 15452 else 15453 { 15454 /* Mask to get a 32-bit address. */ 15455 op_address[op_ad] = op & 0xffffffff; 15456 op_riprel[op_ad] = riprel & 0xffffffff; 15457 } 15458 } 15459 15460 static void 15461 OP_REG (int code, int sizeflag) 15462 { 15463 const char *s; 15464 int add; 15465 15466 switch (code) 15467 { 15468 case es_reg: case ss_reg: case cs_reg: 15469 case ds_reg: case fs_reg: case gs_reg: 15470 oappend (names_seg[code - es_reg]); 15471 return; 15472 } 15473 15474 USED_REX (REX_B); 15475 if (rex & REX_B) 15476 add = 8; 15477 else 15478 add = 0; 15479 15480 switch (code) 15481 { 15482 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 15483 case sp_reg: case bp_reg: case si_reg: case di_reg: 15484 s = names16[code - ax_reg + add]; 15485 break; 15486 case al_reg: case ah_reg: case cl_reg: case ch_reg: 15487 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 15488 USED_REX (0); 15489 if (rex) 15490 s = names8rex[code - al_reg + add]; 15491 else 15492 s = names8[code - al_reg]; 15493 break; 15494 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: 15495 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: 15496 if (address_mode == mode_64bit 15497 && ((sizeflag & DFLAG) || (rex & REX_W))) 15498 { 15499 s = names64[code - rAX_reg + add]; 15500 break; 15501 } 15502 code += eAX_reg - rAX_reg; 15503 /* Fall through. */ 15504 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 15505 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 15506 USED_REX (REX_W); 15507 if (rex & REX_W) 15508 s = names64[code - eAX_reg + add]; 15509 else 15510 { 15511 if (sizeflag & DFLAG) 15512 s = names32[code - eAX_reg + add]; 15513 else 15514 s = names16[code - eAX_reg + add]; 15515 used_prefixes |= (prefixes & PREFIX_DATA); 15516 } 15517 break; 15518 default: 15519 s = INTERNAL_DISASSEMBLER_ERROR; 15520 break; 15521 } 15522 oappend (s); 15523 } 15524 15525 static void 15526 OP_IMREG (int code, int sizeflag) 15527 { 15528 const char *s; 15529 15530 switch (code) 15531 { 15532 case indir_dx_reg: 15533 if (intel_syntax) 15534 s = "dx"; 15535 else 15536 s = "(%dx)"; 15537 break; 15538 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 15539 case sp_reg: case bp_reg: case si_reg: case di_reg: 15540 s = names16[code - ax_reg]; 15541 break; 15542 case es_reg: case ss_reg: case cs_reg: 15543 case ds_reg: case fs_reg: case gs_reg: 15544 s = names_seg[code - es_reg]; 15545 break; 15546 case al_reg: case ah_reg: case cl_reg: case ch_reg: 15547 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 15548 USED_REX (0); 15549 if (rex) 15550 s = names8rex[code - al_reg]; 15551 else 15552 s = names8[code - al_reg]; 15553 break; 15554 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 15555 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 15556 USED_REX (REX_W); 15557 if (rex & REX_W) 15558 s = names64[code - eAX_reg]; 15559 else 15560 { 15561 if (sizeflag & DFLAG) 15562 s = names32[code - eAX_reg]; 15563 else 15564 s = names16[code - eAX_reg]; 15565 used_prefixes |= (prefixes & PREFIX_DATA); 15566 } 15567 break; 15568 case z_mode_ax_reg: 15569 if ((rex & REX_W) || (sizeflag & DFLAG)) 15570 s = *names32; 15571 else 15572 s = *names16; 15573 if (!(rex & REX_W)) 15574 used_prefixes |= (prefixes & PREFIX_DATA); 15575 break; 15576 default: 15577 s = INTERNAL_DISASSEMBLER_ERROR; 15578 break; 15579 } 15580 oappend (s); 15581 } 15582 15583 static void 15584 OP_I (int bytemode, int sizeflag) 15585 { 15586 bfd_signed_vma op; 15587 bfd_signed_vma mask = -1; 15588 15589 switch (bytemode) 15590 { 15591 case b_mode: 15592 FETCH_DATA (the_info, codep + 1); 15593 op = *codep++; 15594 mask = 0xff; 15595 break; 15596 case q_mode: 15597 if (address_mode == mode_64bit) 15598 { 15599 op = get32s (); 15600 break; 15601 } 15602 /* Fall through. */ 15603 case v_mode: 15604 USED_REX (REX_W); 15605 if (rex & REX_W) 15606 op = get32s (); 15607 else 15608 { 15609 if (sizeflag & DFLAG) 15610 { 15611 op = get32 (); 15612 mask = 0xffffffff; 15613 } 15614 else 15615 { 15616 op = get16 (); 15617 mask = 0xfffff; 15618 } 15619 used_prefixes |= (prefixes & PREFIX_DATA); 15620 } 15621 break; 15622 case w_mode: 15623 mask = 0xfffff; 15624 op = get16 (); 15625 break; 15626 case const_1_mode: 15627 if (intel_syntax) 15628 oappend ("1"); 15629 return; 15630 default: 15631 oappend (INTERNAL_DISASSEMBLER_ERROR); 15632 return; 15633 } 15634 15635 op &= mask; 15636 scratchbuf[0] = '$'; 15637 print_operand_value (scratchbuf + 1, 1, op); 15638 oappend_maybe_intel (scratchbuf); 15639 scratchbuf[0] = '\0'; 15640 } 15641 15642 static void 15643 OP_I64 (int bytemode, int sizeflag) 15644 { 15645 bfd_signed_vma op; 15646 bfd_signed_vma mask = -1; 15647 15648 if (address_mode != mode_64bit) 15649 { 15650 OP_I (bytemode, sizeflag); 15651 return; 15652 } 15653 15654 switch (bytemode) 15655 { 15656 case b_mode: 15657 FETCH_DATA (the_info, codep + 1); 15658 op = *codep++; 15659 mask = 0xff; 15660 break; 15661 case v_mode: 15662 USED_REX (REX_W); 15663 if (rex & REX_W) 15664 op = get64 (); 15665 else 15666 { 15667 if (sizeflag & DFLAG) 15668 { 15669 op = get32 (); 15670 mask = 0xffffffff; 15671 } 15672 else 15673 { 15674 op = get16 (); 15675 mask = 0xfffff; 15676 } 15677 used_prefixes |= (prefixes & PREFIX_DATA); 15678 } 15679 break; 15680 case w_mode: 15681 mask = 0xfffff; 15682 op = get16 (); 15683 break; 15684 default: 15685 oappend (INTERNAL_DISASSEMBLER_ERROR); 15686 return; 15687 } 15688 15689 op &= mask; 15690 scratchbuf[0] = '$'; 15691 print_operand_value (scratchbuf + 1, 1, op); 15692 oappend_maybe_intel (scratchbuf); 15693 scratchbuf[0] = '\0'; 15694 } 15695 15696 static void 15697 OP_sI (int bytemode, int sizeflag) 15698 { 15699 bfd_signed_vma op; 15700 15701 switch (bytemode) 15702 { 15703 case b_mode: 15704 case b_T_mode: 15705 FETCH_DATA (the_info, codep + 1); 15706 op = *codep++; 15707 if ((op & 0x80) != 0) 15708 op -= 0x100; 15709 if (bytemode == b_T_mode) 15710 { 15711 if (address_mode != mode_64bit 15712 || !((sizeflag & DFLAG) || (rex & REX_W))) 15713 { 15714 /* The operand-size prefix is overridden by a REX prefix. */ 15715 if ((sizeflag & DFLAG) || (rex & REX_W)) 15716 op &= 0xffffffff; 15717 else 15718 op &= 0xffff; 15719 } 15720 } 15721 else 15722 { 15723 if (!(rex & REX_W)) 15724 { 15725 if (sizeflag & DFLAG) 15726 op &= 0xffffffff; 15727 else 15728 op &= 0xffff; 15729 } 15730 } 15731 break; 15732 case v_mode: 15733 /* The operand-size prefix is overridden by a REX prefix. */ 15734 if ((sizeflag & DFLAG) || (rex & REX_W)) 15735 op = get32s (); 15736 else 15737 op = get16 (); 15738 break; 15739 default: 15740 oappend (INTERNAL_DISASSEMBLER_ERROR); 15741 return; 15742 } 15743 15744 scratchbuf[0] = '$'; 15745 print_operand_value (scratchbuf + 1, 1, op); 15746 oappend_maybe_intel (scratchbuf); 15747 } 15748 15749 static void 15750 OP_J (int bytemode, int sizeflag) 15751 { 15752 bfd_vma disp; 15753 bfd_vma mask = -1; 15754 bfd_vma segment = 0; 15755 15756 switch (bytemode) 15757 { 15758 case b_mode: 15759 FETCH_DATA (the_info, codep + 1); 15760 disp = *codep++; 15761 if ((disp & 0x80) != 0) 15762 disp -= 0x100; 15763 break; 15764 case v_mode: 15765 if (isa64 == amd64) 15766 USED_REX (REX_W); 15767 if ((sizeflag & DFLAG) 15768 || (address_mode == mode_64bit 15769 && (isa64 != amd64 || (rex & REX_W)))) 15770 disp = get32s (); 15771 else 15772 { 15773 disp = get16 (); 15774 if ((disp & 0x8000) != 0) 15775 disp -= 0x10000; 15776 /* In 16bit mode, address is wrapped around at 64k within 15777 the same segment. Otherwise, a data16 prefix on a jump 15778 instruction means that the pc is masked to 16 bits after 15779 the displacement is added! */ 15780 mask = 0xffff; 15781 if ((prefixes & PREFIX_DATA) == 0) 15782 segment = ((start_pc + codep - start_codep) 15783 & ~((bfd_vma) 0xffff)); 15784 } 15785 if (address_mode != mode_64bit 15786 || (isa64 == amd64 && !(rex & REX_W))) 15787 used_prefixes |= (prefixes & PREFIX_DATA); 15788 break; 15789 default: 15790 oappend (INTERNAL_DISASSEMBLER_ERROR); 15791 return; 15792 } 15793 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; 15794 set_op (disp, 0); 15795 print_operand_value (scratchbuf, 1, disp); 15796 oappend (scratchbuf); 15797 } 15798 15799 static void 15800 OP_SEG (int bytemode, int sizeflag) 15801 { 15802 if (bytemode == w_mode) 15803 oappend (names_seg[modrm.reg]); 15804 else 15805 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); 15806 } 15807 15808 static void 15809 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) 15810 { 15811 int seg, offset; 15812 15813 if (sizeflag & DFLAG) 15814 { 15815 offset = get32 (); 15816 seg = get16 (); 15817 } 15818 else 15819 { 15820 offset = get16 (); 15821 seg = get16 (); 15822 } 15823 used_prefixes |= (prefixes & PREFIX_DATA); 15824 if (intel_syntax) 15825 sprintf (scratchbuf, "0x%x:0x%x", seg, offset); 15826 else 15827 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); 15828 oappend (scratchbuf); 15829 } 15830 15831 static void 15832 OP_OFF (int bytemode, int sizeflag) 15833 { 15834 bfd_vma off; 15835 15836 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 15837 intel_operand_size (bytemode, sizeflag); 15838 append_seg (); 15839 15840 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 15841 off = get32 (); 15842 else 15843 off = get16 (); 15844 15845 if (intel_syntax) 15846 { 15847 if (!active_seg_prefix) 15848 { 15849 oappend (names_seg[ds_reg - es_reg]); 15850 oappend (":"); 15851 } 15852 } 15853 print_operand_value (scratchbuf, 1, off); 15854 oappend (scratchbuf); 15855 } 15856 15857 static void 15858 OP_OFF64 (int bytemode, int sizeflag) 15859 { 15860 bfd_vma off; 15861 15862 if (address_mode != mode_64bit 15863 || (prefixes & PREFIX_ADDR)) 15864 { 15865 OP_OFF (bytemode, sizeflag); 15866 return; 15867 } 15868 15869 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 15870 intel_operand_size (bytemode, sizeflag); 15871 append_seg (); 15872 15873 off = get64 (); 15874 15875 if (intel_syntax) 15876 { 15877 if (!active_seg_prefix) 15878 { 15879 oappend (names_seg[ds_reg - es_reg]); 15880 oappend (":"); 15881 } 15882 } 15883 print_operand_value (scratchbuf, 1, off); 15884 oappend (scratchbuf); 15885 } 15886 15887 static void 15888 ptr_reg (int code, int sizeflag) 15889 { 15890 const char *s; 15891 15892 *obufp++ = open_char; 15893 used_prefixes |= (prefixes & PREFIX_ADDR); 15894 if (address_mode == mode_64bit) 15895 { 15896 if (!(sizeflag & AFLAG)) 15897 s = names32[code - eAX_reg]; 15898 else 15899 s = names64[code - eAX_reg]; 15900 } 15901 else if (sizeflag & AFLAG) 15902 s = names32[code - eAX_reg]; 15903 else 15904 s = names16[code - eAX_reg]; 15905 oappend (s); 15906 *obufp++ = close_char; 15907 *obufp = 0; 15908 } 15909 15910 static void 15911 OP_ESreg (int code, int sizeflag) 15912 { 15913 if (intel_syntax) 15914 { 15915 switch (codep[-1]) 15916 { 15917 case 0x6d: /* insw/insl */ 15918 intel_operand_size (z_mode, sizeflag); 15919 break; 15920 case 0xa5: /* movsw/movsl/movsq */ 15921 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 15922 case 0xab: /* stosw/stosl */ 15923 case 0xaf: /* scasw/scasl */ 15924 intel_operand_size (v_mode, sizeflag); 15925 break; 15926 default: 15927 intel_operand_size (b_mode, sizeflag); 15928 } 15929 } 15930 oappend_maybe_intel ("%es:"); 15931 ptr_reg (code, sizeflag); 15932 } 15933 15934 static void 15935 OP_DSreg (int code, int sizeflag) 15936 { 15937 if (intel_syntax) 15938 { 15939 switch (codep[-1]) 15940 { 15941 case 0x6f: /* outsw/outsl */ 15942 intel_operand_size (z_mode, sizeflag); 15943 break; 15944 case 0xa5: /* movsw/movsl/movsq */ 15945 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 15946 case 0xad: /* lodsw/lodsl/lodsq */ 15947 intel_operand_size (v_mode, sizeflag); 15948 break; 15949 default: 15950 intel_operand_size (b_mode, sizeflag); 15951 } 15952 } 15953 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the 15954 default segment register DS is printed. */ 15955 if (!active_seg_prefix) 15956 active_seg_prefix = PREFIX_DS; 15957 append_seg (); 15958 ptr_reg (code, sizeflag); 15959 } 15960 15961 static void 15962 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15963 { 15964 int add; 15965 if (rex & REX_R) 15966 { 15967 USED_REX (REX_R); 15968 add = 8; 15969 } 15970 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) 15971 { 15972 all_prefixes[last_lock_prefix] = 0; 15973 used_prefixes |= PREFIX_LOCK; 15974 add = 8; 15975 } 15976 else 15977 add = 0; 15978 sprintf (scratchbuf, "%%cr%d", modrm.reg + add); 15979 oappend_maybe_intel (scratchbuf); 15980 } 15981 15982 static void 15983 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15984 { 15985 int add; 15986 USED_REX (REX_R); 15987 if (rex & REX_R) 15988 add = 8; 15989 else 15990 add = 0; 15991 if (intel_syntax) 15992 sprintf (scratchbuf, "db%d", modrm.reg + add); 15993 else 15994 sprintf (scratchbuf, "%%db%d", modrm.reg + add); 15995 oappend (scratchbuf); 15996 } 15997 15998 static void 15999 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16000 { 16001 sprintf (scratchbuf, "%%tr%d", modrm.reg); 16002 oappend_maybe_intel (scratchbuf); 16003 } 16004 16005 static void 16006 OP_R (int bytemode, int sizeflag) 16007 { 16008 /* Skip mod/rm byte. */ 16009 MODRM_CHECK; 16010 codep++; 16011 OP_E_register (bytemode, sizeflag); 16012 } 16013 16014 static void 16015 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16016 { 16017 int reg = modrm.reg; 16018 const char **names; 16019 16020 used_prefixes |= (prefixes & PREFIX_DATA); 16021 if (prefixes & PREFIX_DATA) 16022 { 16023 names = names_xmm; 16024 USED_REX (REX_R); 16025 if (rex & REX_R) 16026 reg += 8; 16027 } 16028 else 16029 names = names_mm; 16030 oappend (names[reg]); 16031 } 16032 16033 static void 16034 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 16035 { 16036 int reg = modrm.reg; 16037 const char **names; 16038 16039 USED_REX (REX_R); 16040 if (rex & REX_R) 16041 reg += 8; 16042 if (vex.evex) 16043 { 16044 if (!vex.r) 16045 reg += 16; 16046 } 16047 16048 if (need_vex 16049 && bytemode != xmm_mode 16050 && bytemode != xmmq_mode 16051 && bytemode != evex_half_bcst_xmmq_mode 16052 && bytemode != ymm_mode 16053 && bytemode != scalar_mode) 16054 { 16055 switch (vex.length) 16056 { 16057 case 128: 16058 names = names_xmm; 16059 break; 16060 case 256: 16061 if (vex.w 16062 || (bytemode != vex_vsib_q_w_dq_mode 16063 && bytemode != vex_vsib_q_w_d_mode)) 16064 names = names_ymm; 16065 else 16066 names = names_xmm; 16067 break; 16068 case 512: 16069 names = names_zmm; 16070 break; 16071 default: 16072 abort (); 16073 } 16074 } 16075 else if (bytemode == xmmq_mode 16076 || bytemode == evex_half_bcst_xmmq_mode) 16077 { 16078 switch (vex.length) 16079 { 16080 case 128: 16081 case 256: 16082 names = names_xmm; 16083 break; 16084 case 512: 16085 names = names_ymm; 16086 break; 16087 default: 16088 abort (); 16089 } 16090 } 16091 else if (bytemode == ymm_mode) 16092 names = names_ymm; 16093 else 16094 names = names_xmm; 16095 oappend (names[reg]); 16096 } 16097 16098 static void 16099 OP_EM (int bytemode, int sizeflag) 16100 { 16101 int reg; 16102 const char **names; 16103 16104 if (modrm.mod != 3) 16105 { 16106 if (intel_syntax 16107 && (bytemode == v_mode || bytemode == v_swap_mode)) 16108 { 16109 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 16110 used_prefixes |= (prefixes & PREFIX_DATA); 16111 } 16112 OP_E (bytemode, sizeflag); 16113 return; 16114 } 16115 16116 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) 16117 swap_operand (); 16118 16119 /* Skip mod/rm byte. */ 16120 MODRM_CHECK; 16121 codep++; 16122 used_prefixes |= (prefixes & PREFIX_DATA); 16123 reg = modrm.rm; 16124 if (prefixes & PREFIX_DATA) 16125 { 16126 names = names_xmm; 16127 USED_REX (REX_B); 16128 if (rex & REX_B) 16129 reg += 8; 16130 } 16131 else 16132 names = names_mm; 16133 oappend (names[reg]); 16134 } 16135 16136 /* cvt* are the only instructions in sse2 which have 16137 both SSE and MMX operands and also have 0x66 prefix 16138 in their opcode. 0x66 was originally used to differentiate 16139 between SSE and MMX instruction(operands). So we have to handle the 16140 cvt* separately using OP_EMC and OP_MXC */ 16141 static void 16142 OP_EMC (int bytemode, int sizeflag) 16143 { 16144 if (modrm.mod != 3) 16145 { 16146 if (intel_syntax && bytemode == v_mode) 16147 { 16148 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 16149 used_prefixes |= (prefixes & PREFIX_DATA); 16150 } 16151 OP_E (bytemode, sizeflag); 16152 return; 16153 } 16154 16155 /* Skip mod/rm byte. */ 16156 MODRM_CHECK; 16157 codep++; 16158 used_prefixes |= (prefixes & PREFIX_DATA); 16159 oappend (names_mm[modrm.rm]); 16160 } 16161 16162 static void 16163 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16164 { 16165 used_prefixes |= (prefixes & PREFIX_DATA); 16166 oappend (names_mm[modrm.reg]); 16167 } 16168 16169 static void 16170 OP_EX (int bytemode, int sizeflag) 16171 { 16172 int reg; 16173 const char **names; 16174 16175 /* Skip mod/rm byte. */ 16176 MODRM_CHECK; 16177 codep++; 16178 16179 if (modrm.mod != 3) 16180 { 16181 OP_E_memory (bytemode, sizeflag); 16182 return; 16183 } 16184 16185 reg = modrm.rm; 16186 USED_REX (REX_B); 16187 if (rex & REX_B) 16188 reg += 8; 16189 if (vex.evex) 16190 { 16191 USED_REX (REX_X); 16192 if ((rex & REX_X)) 16193 reg += 16; 16194 } 16195 16196 if ((sizeflag & SUFFIX_ALWAYS) 16197 && (bytemode == x_swap_mode 16198 || bytemode == d_swap_mode 16199 || bytemode == dqw_swap_mode 16200 || bytemode == d_scalar_swap_mode 16201 || bytemode == q_swap_mode 16202 || bytemode == q_scalar_swap_mode)) 16203 swap_operand (); 16204 16205 if (need_vex 16206 && bytemode != xmm_mode 16207 && bytemode != xmmdw_mode 16208 && bytemode != xmmqd_mode 16209 && bytemode != xmm_mb_mode 16210 && bytemode != xmm_mw_mode 16211 && bytemode != xmm_md_mode 16212 && bytemode != xmm_mq_mode 16213 && bytemode != xmm_mdq_mode 16214 && bytemode != xmmq_mode 16215 && bytemode != evex_half_bcst_xmmq_mode 16216 && bytemode != ymm_mode 16217 && bytemode != d_scalar_mode 16218 && bytemode != d_scalar_swap_mode 16219 && bytemode != q_scalar_mode 16220 && bytemode != q_scalar_swap_mode 16221 && bytemode != vex_scalar_w_dq_mode) 16222 { 16223 switch (vex.length) 16224 { 16225 case 128: 16226 names = names_xmm; 16227 break; 16228 case 256: 16229 names = names_ymm; 16230 break; 16231 case 512: 16232 names = names_zmm; 16233 break; 16234 default: 16235 abort (); 16236 } 16237 } 16238 else if (bytemode == xmmq_mode 16239 || bytemode == evex_half_bcst_xmmq_mode) 16240 { 16241 switch (vex.length) 16242 { 16243 case 128: 16244 case 256: 16245 names = names_xmm; 16246 break; 16247 case 512: 16248 names = names_ymm; 16249 break; 16250 default: 16251 abort (); 16252 } 16253 } 16254 else if (bytemode == ymm_mode) 16255 names = names_ymm; 16256 else 16257 names = names_xmm; 16258 oappend (names[reg]); 16259 } 16260 16261 static void 16262 OP_MS (int bytemode, int sizeflag) 16263 { 16264 if (modrm.mod == 3) 16265 OP_EM (bytemode, sizeflag); 16266 else 16267 BadOp (); 16268 } 16269 16270 static void 16271 OP_XS (int bytemode, int sizeflag) 16272 { 16273 if (modrm.mod == 3) 16274 OP_EX (bytemode, sizeflag); 16275 else 16276 BadOp (); 16277 } 16278 16279 static void 16280 OP_M (int bytemode, int sizeflag) 16281 { 16282 if (modrm.mod == 3) 16283 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ 16284 BadOp (); 16285 else 16286 OP_E (bytemode, sizeflag); 16287 } 16288 16289 static void 16290 OP_0f07 (int bytemode, int sizeflag) 16291 { 16292 if (modrm.mod != 3 || modrm.rm != 0) 16293 BadOp (); 16294 else 16295 OP_E (bytemode, sizeflag); 16296 } 16297 16298 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 16299 32bit mode and "xchg %rax,%rax" in 64bit mode. */ 16300 16301 static void 16302 NOP_Fixup1 (int bytemode, int sizeflag) 16303 { 16304 if ((prefixes & PREFIX_DATA) != 0 16305 || (rex != 0 16306 && rex != 0x48 16307 && address_mode == mode_64bit)) 16308 OP_REG (bytemode, sizeflag); 16309 else 16310 strcpy (obuf, "nop"); 16311 } 16312 16313 static void 16314 NOP_Fixup2 (int bytemode, int sizeflag) 16315 { 16316 if ((prefixes & PREFIX_DATA) != 0 16317 || (rex != 0 16318 && rex != 0x48 16319 && address_mode == mode_64bit)) 16320 OP_IMREG (bytemode, sizeflag); 16321 } 16322 16323 static const char *const Suffix3DNow[] = { 16324 /* 00 */ NULL, NULL, NULL, NULL, 16325 /* 04 */ NULL, NULL, NULL, NULL, 16326 /* 08 */ NULL, NULL, NULL, NULL, 16327 /* 0C */ "pi2fw", "pi2fd", NULL, NULL, 16328 /* 10 */ NULL, NULL, NULL, NULL, 16329 /* 14 */ NULL, NULL, NULL, NULL, 16330 /* 18 */ NULL, NULL, NULL, NULL, 16331 /* 1C */ "pf2iw", "pf2id", NULL, NULL, 16332 /* 20 */ NULL, NULL, NULL, NULL, 16333 /* 24 */ NULL, NULL, NULL, NULL, 16334 /* 28 */ NULL, NULL, NULL, NULL, 16335 /* 2C */ NULL, NULL, NULL, NULL, 16336 /* 30 */ NULL, NULL, NULL, NULL, 16337 /* 34 */ NULL, NULL, NULL, NULL, 16338 /* 38 */ NULL, NULL, NULL, NULL, 16339 /* 3C */ NULL, NULL, NULL, NULL, 16340 /* 40 */ NULL, NULL, NULL, NULL, 16341 /* 44 */ NULL, NULL, NULL, NULL, 16342 /* 48 */ NULL, NULL, NULL, NULL, 16343 /* 4C */ NULL, NULL, NULL, NULL, 16344 /* 50 */ NULL, NULL, NULL, NULL, 16345 /* 54 */ NULL, NULL, NULL, NULL, 16346 /* 58 */ NULL, NULL, NULL, NULL, 16347 /* 5C */ NULL, NULL, NULL, NULL, 16348 /* 60 */ NULL, NULL, NULL, NULL, 16349 /* 64 */ NULL, NULL, NULL, NULL, 16350 /* 68 */ NULL, NULL, NULL, NULL, 16351 /* 6C */ NULL, NULL, NULL, NULL, 16352 /* 70 */ NULL, NULL, NULL, NULL, 16353 /* 74 */ NULL, NULL, NULL, NULL, 16354 /* 78 */ NULL, NULL, NULL, NULL, 16355 /* 7C */ NULL, NULL, NULL, NULL, 16356 /* 80 */ NULL, NULL, NULL, NULL, 16357 /* 84 */ NULL, NULL, NULL, NULL, 16358 /* 88 */ NULL, NULL, "pfnacc", NULL, 16359 /* 8C */ NULL, NULL, "pfpnacc", NULL, 16360 /* 90 */ "pfcmpge", NULL, NULL, NULL, 16361 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", 16362 /* 98 */ NULL, NULL, "pfsub", NULL, 16363 /* 9C */ NULL, NULL, "pfadd", NULL, 16364 /* A0 */ "pfcmpgt", NULL, NULL, NULL, 16365 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", 16366 /* A8 */ NULL, NULL, "pfsubr", NULL, 16367 /* AC */ NULL, NULL, "pfacc", NULL, 16368 /* B0 */ "pfcmpeq", NULL, NULL, NULL, 16369 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", 16370 /* B8 */ NULL, NULL, NULL, "pswapd", 16371 /* BC */ NULL, NULL, NULL, "pavgusb", 16372 /* C0 */ NULL, NULL, NULL, NULL, 16373 /* C4 */ NULL, NULL, NULL, NULL, 16374 /* C8 */ NULL, NULL, NULL, NULL, 16375 /* CC */ NULL, NULL, NULL, NULL, 16376 /* D0 */ NULL, NULL, NULL, NULL, 16377 /* D4 */ NULL, NULL, NULL, NULL, 16378 /* D8 */ NULL, NULL, NULL, NULL, 16379 /* DC */ NULL, NULL, NULL, NULL, 16380 /* E0 */ NULL, NULL, NULL, NULL, 16381 /* E4 */ NULL, NULL, NULL, NULL, 16382 /* E8 */ NULL, NULL, NULL, NULL, 16383 /* EC */ NULL, NULL, NULL, NULL, 16384 /* F0 */ NULL, NULL, NULL, NULL, 16385 /* F4 */ NULL, NULL, NULL, NULL, 16386 /* F8 */ NULL, NULL, NULL, NULL, 16387 /* FC */ NULL, NULL, NULL, NULL, 16388 }; 16389 16390 static void 16391 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16392 { 16393 const char *mnemonic; 16394 16395 FETCH_DATA (the_info, codep + 1); 16396 /* AMD 3DNow! instructions are specified by an opcode suffix in the 16397 place where an 8-bit immediate would normally go. ie. the last 16398 byte of the instruction. */ 16399 obufp = mnemonicendp; 16400 mnemonic = Suffix3DNow[*codep++ & 0xff]; 16401 if (mnemonic) 16402 oappend (mnemonic); 16403 else 16404 { 16405 /* Since a variable sized modrm/sib chunk is between the start 16406 of the opcode (0x0f0f) and the opcode suffix, we need to do 16407 all the modrm processing first, and don't know until now that 16408 we have a bad opcode. This necessitates some cleaning up. */ 16409 op_out[0][0] = '\0'; 16410 op_out[1][0] = '\0'; 16411 BadOp (); 16412 } 16413 mnemonicendp = obufp; 16414 } 16415 16416 static struct op simd_cmp_op[] = 16417 { 16418 { STRING_COMMA_LEN ("eq") }, 16419 { STRING_COMMA_LEN ("lt") }, 16420 { STRING_COMMA_LEN ("le") }, 16421 { STRING_COMMA_LEN ("unord") }, 16422 { STRING_COMMA_LEN ("neq") }, 16423 { STRING_COMMA_LEN ("nlt") }, 16424 { STRING_COMMA_LEN ("nle") }, 16425 { STRING_COMMA_LEN ("ord") } 16426 }; 16427 16428 static void 16429 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16430 { 16431 unsigned int cmp_type; 16432 16433 FETCH_DATA (the_info, codep + 1); 16434 cmp_type = *codep++ & 0xff; 16435 if (cmp_type < ARRAY_SIZE (simd_cmp_op)) 16436 { 16437 char suffix [3]; 16438 char *p = mnemonicendp - 2; 16439 suffix[0] = p[0]; 16440 suffix[1] = p[1]; 16441 suffix[2] = '\0'; 16442 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 16443 mnemonicendp += simd_cmp_op[cmp_type].len; 16444 } 16445 else 16446 { 16447 /* We have a reserved extension byte. Output it directly. */ 16448 scratchbuf[0] = '$'; 16449 print_operand_value (scratchbuf + 1, 1, cmp_type); 16450 oappend_maybe_intel (scratchbuf); 16451 scratchbuf[0] = '\0'; 16452 } 16453 } 16454 16455 static void 16456 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, 16457 int sizeflag ATTRIBUTE_UNUSED) 16458 { 16459 /* mwaitx %eax,%ecx,%ebx */ 16460 if (!intel_syntax) 16461 { 16462 const char **names = (address_mode == mode_64bit 16463 ? names64 : names32); 16464 strcpy (op_out[0], names[0]); 16465 strcpy (op_out[1], names[1]); 16466 strcpy (op_out[2], names[3]); 16467 two_source_ops = 1; 16468 } 16469 /* Skip mod/rm byte. */ 16470 MODRM_CHECK; 16471 codep++; 16472 } 16473 16474 static void 16475 OP_Mwait (int bytemode ATTRIBUTE_UNUSED, 16476 int sizeflag ATTRIBUTE_UNUSED) 16477 { 16478 /* mwait %eax,%ecx */ 16479 if (!intel_syntax) 16480 { 16481 const char **names = (address_mode == mode_64bit 16482 ? names64 : names32); 16483 strcpy (op_out[0], names[0]); 16484 strcpy (op_out[1], names[1]); 16485 two_source_ops = 1; 16486 } 16487 /* Skip mod/rm byte. */ 16488 MODRM_CHECK; 16489 codep++; 16490 } 16491 16492 static void 16493 OP_Monitor (int bytemode ATTRIBUTE_UNUSED, 16494 int sizeflag ATTRIBUTE_UNUSED) 16495 { 16496 /* monitor %eax,%ecx,%edx" */ 16497 if (!intel_syntax) 16498 { 16499 const char **op1_names; 16500 const char **names = (address_mode == mode_64bit 16501 ? names64 : names32); 16502 16503 if (!(prefixes & PREFIX_ADDR)) 16504 op1_names = (address_mode == mode_16bit 16505 ? names16 : names); 16506 else 16507 { 16508 /* Remove "addr16/addr32". */ 16509 all_prefixes[last_addr_prefix] = 0; 16510 op1_names = (address_mode != mode_32bit 16511 ? names32 : names16); 16512 used_prefixes |= PREFIX_ADDR; 16513 } 16514 strcpy (op_out[0], op1_names[0]); 16515 strcpy (op_out[1], names[1]); 16516 strcpy (op_out[2], names[2]); 16517 two_source_ops = 1; 16518 } 16519 /* Skip mod/rm byte. */ 16520 MODRM_CHECK; 16521 codep++; 16522 } 16523 16524 static void 16525 BadOp (void) 16526 { 16527 /* Throw away prefixes and 1st. opcode byte. */ 16528 codep = insn_codep + 1; 16529 oappend ("(bad)"); 16530 } 16531 16532 static void 16533 REP_Fixup (int bytemode, int sizeflag) 16534 { 16535 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, 16536 lods and stos. */ 16537 if (prefixes & PREFIX_REPZ) 16538 all_prefixes[last_repz_prefix] = REP_PREFIX; 16539 16540 switch (bytemode) 16541 { 16542 case al_reg: 16543 case eAX_reg: 16544 case indir_dx_reg: 16545 OP_IMREG (bytemode, sizeflag); 16546 break; 16547 case eDI_reg: 16548 OP_ESreg (bytemode, sizeflag); 16549 break; 16550 case eSI_reg: 16551 OP_DSreg (bytemode, sizeflag); 16552 break; 16553 default: 16554 abort (); 16555 break; 16556 } 16557 } 16558 16559 /* For BND-prefixed instructions 0xF2 prefix should be displayed as 16560 "bnd". */ 16561 16562 static void 16563 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 16564 { 16565 if (prefixes & PREFIX_REPNZ) 16566 all_prefixes[last_repnz_prefix] = BND_PREFIX; 16567 } 16568 16569 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as 16570 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. 16571 */ 16572 16573 static void 16574 HLE_Fixup1 (int bytemode, int sizeflag) 16575 { 16576 if (modrm.mod != 3 16577 && (prefixes & PREFIX_LOCK) != 0) 16578 { 16579 if (prefixes & PREFIX_REPZ) 16580 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; 16581 if (prefixes & PREFIX_REPNZ) 16582 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; 16583 } 16584 16585 OP_E (bytemode, sizeflag); 16586 } 16587 16588 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as 16589 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. 16590 */ 16591 16592 static void 16593 HLE_Fixup2 (int bytemode, int sizeflag) 16594 { 16595 if (modrm.mod != 3) 16596 { 16597 if (prefixes & PREFIX_REPZ) 16598 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; 16599 if (prefixes & PREFIX_REPNZ) 16600 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; 16601 } 16602 16603 OP_E (bytemode, sizeflag); 16604 } 16605 16606 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as 16607 "xrelease" for memory operand. No check for LOCK prefix. */ 16608 16609 static void 16610 HLE_Fixup3 (int bytemode, int sizeflag) 16611 { 16612 if (modrm.mod != 3 16613 && last_repz_prefix > last_repnz_prefix 16614 && (prefixes & PREFIX_REPZ) != 0) 16615 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; 16616 16617 OP_E (bytemode, sizeflag); 16618 } 16619 16620 static void 16621 CMPXCHG8B_Fixup (int bytemode, int sizeflag) 16622 { 16623 USED_REX (REX_W); 16624 if (rex & REX_W) 16625 { 16626 /* Change cmpxchg8b to cmpxchg16b. */ 16627 char *p = mnemonicendp - 2; 16628 mnemonicendp = stpcpy (p, "16b"); 16629 bytemode = o_mode; 16630 } 16631 else if ((prefixes & PREFIX_LOCK) != 0) 16632 { 16633 if (prefixes & PREFIX_REPZ) 16634 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; 16635 if (prefixes & PREFIX_REPNZ) 16636 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; 16637 } 16638 16639 OP_M (bytemode, sizeflag); 16640 } 16641 16642 static void 16643 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) 16644 { 16645 const char **names; 16646 16647 if (need_vex) 16648 { 16649 switch (vex.length) 16650 { 16651 case 128: 16652 names = names_xmm; 16653 break; 16654 case 256: 16655 names = names_ymm; 16656 break; 16657 default: 16658 abort (); 16659 } 16660 } 16661 else 16662 names = names_xmm; 16663 oappend (names[reg]); 16664 } 16665 16666 static void 16667 CRC32_Fixup (int bytemode, int sizeflag) 16668 { 16669 /* Add proper suffix to "crc32". */ 16670 char *p = mnemonicendp; 16671 16672 switch (bytemode) 16673 { 16674 case b_mode: 16675 if (intel_syntax) 16676 goto skip; 16677 16678 *p++ = 'b'; 16679 break; 16680 case v_mode: 16681 if (intel_syntax) 16682 goto skip; 16683 16684 USED_REX (REX_W); 16685 if (rex & REX_W) 16686 *p++ = 'q'; 16687 else 16688 { 16689 if (sizeflag & DFLAG) 16690 *p++ = 'l'; 16691 else 16692 *p++ = 'w'; 16693 used_prefixes |= (prefixes & PREFIX_DATA); 16694 } 16695 break; 16696 default: 16697 oappend (INTERNAL_DISASSEMBLER_ERROR); 16698 break; 16699 } 16700 mnemonicendp = p; 16701 *p = '\0'; 16702 16703 skip: 16704 if (modrm.mod == 3) 16705 { 16706 int add; 16707 16708 /* Skip mod/rm byte. */ 16709 MODRM_CHECK; 16710 codep++; 16711 16712 USED_REX (REX_B); 16713 add = (rex & REX_B) ? 8 : 0; 16714 if (bytemode == b_mode) 16715 { 16716 USED_REX (0); 16717 if (rex) 16718 oappend (names8rex[modrm.rm + add]); 16719 else 16720 oappend (names8[modrm.rm + add]); 16721 } 16722 else 16723 { 16724 USED_REX (REX_W); 16725 if (rex & REX_W) 16726 oappend (names64[modrm.rm + add]); 16727 else if ((prefixes & PREFIX_DATA)) 16728 oappend (names16[modrm.rm + add]); 16729 else 16730 oappend (names32[modrm.rm + add]); 16731 } 16732 } 16733 else 16734 OP_E (bytemode, sizeflag); 16735 } 16736 16737 static void 16738 FXSAVE_Fixup (int bytemode, int sizeflag) 16739 { 16740 /* Add proper suffix to "fxsave" and "fxrstor". */ 16741 USED_REX (REX_W); 16742 if (rex & REX_W) 16743 { 16744 char *p = mnemonicendp; 16745 *p++ = '6'; 16746 *p++ = '4'; 16747 *p = '\0'; 16748 mnemonicendp = p; 16749 } 16750 OP_M (bytemode, sizeflag); 16751 } 16752 16753 /* Display the destination register operand for instructions with 16754 VEX. */ 16755 16756 static void 16757 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 16758 { 16759 int reg; 16760 const char **names; 16761 16762 if (!need_vex) 16763 abort (); 16764 16765 if (!need_vex_reg) 16766 return; 16767 16768 reg = vex.register_specifier; 16769 if (vex.evex) 16770 { 16771 if (!vex.v) 16772 reg += 16; 16773 } 16774 16775 if (bytemode == vex_scalar_mode) 16776 { 16777 oappend (names_xmm[reg]); 16778 return; 16779 } 16780 16781 switch (vex.length) 16782 { 16783 case 128: 16784 switch (bytemode) 16785 { 16786 case vex_mode: 16787 case vex128_mode: 16788 case vex_vsib_q_w_dq_mode: 16789 case vex_vsib_q_w_d_mode: 16790 names = names_xmm; 16791 break; 16792 case dq_mode: 16793 if (vex.w) 16794 names = names64; 16795 else 16796 names = names32; 16797 break; 16798 case mask_bd_mode: 16799 case mask_mode: 16800 names = names_mask; 16801 break; 16802 default: 16803 abort (); 16804 return; 16805 } 16806 break; 16807 case 256: 16808 switch (bytemode) 16809 { 16810 case vex_mode: 16811 case vex256_mode: 16812 names = names_ymm; 16813 break; 16814 case vex_vsib_q_w_dq_mode: 16815 case vex_vsib_q_w_d_mode: 16816 names = vex.w ? names_ymm : names_xmm; 16817 break; 16818 case mask_bd_mode: 16819 case mask_mode: 16820 names = names_mask; 16821 break; 16822 default: 16823 abort (); 16824 return; 16825 } 16826 break; 16827 case 512: 16828 names = names_zmm; 16829 break; 16830 default: 16831 abort (); 16832 break; 16833 } 16834 oappend (names[reg]); 16835 } 16836 16837 /* Get the VEX immediate byte without moving codep. */ 16838 16839 static unsigned char 16840 get_vex_imm8 (int sizeflag, int opnum) 16841 { 16842 int bytes_before_imm = 0; 16843 16844 if (modrm.mod != 3) 16845 { 16846 /* There are SIB/displacement bytes. */ 16847 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 16848 { 16849 /* 32/64 bit address mode */ 16850 int base = modrm.rm; 16851 16852 /* Check SIB byte. */ 16853 if (base == 4) 16854 { 16855 FETCH_DATA (the_info, codep + 1); 16856 base = *codep & 7; 16857 /* When decoding the third source, don't increase 16858 bytes_before_imm as this has already been incremented 16859 by one in OP_E_memory while decoding the second 16860 source operand. */ 16861 if (opnum == 0) 16862 bytes_before_imm++; 16863 } 16864 16865 /* Don't increase bytes_before_imm when decoding the third source, 16866 it has already been incremented by OP_E_memory while decoding 16867 the second source operand. */ 16868 if (opnum == 0) 16869 { 16870 switch (modrm.mod) 16871 { 16872 case 0: 16873 /* When modrm.rm == 5 or modrm.rm == 4 and base in 16874 SIB == 5, there is a 4 byte displacement. */ 16875 if (base != 5) 16876 /* No displacement. */ 16877 break; 16878 case 2: 16879 /* 4 byte displacement. */ 16880 bytes_before_imm += 4; 16881 break; 16882 case 1: 16883 /* 1 byte displacement. */ 16884 bytes_before_imm++; 16885 break; 16886 } 16887 } 16888 } 16889 else 16890 { 16891 /* 16 bit address mode */ 16892 /* Don't increase bytes_before_imm when decoding the third source, 16893 it has already been incremented by OP_E_memory while decoding 16894 the second source operand. */ 16895 if (opnum == 0) 16896 { 16897 switch (modrm.mod) 16898 { 16899 case 0: 16900 /* When modrm.rm == 6, there is a 2 byte displacement. */ 16901 if (modrm.rm != 6) 16902 /* No displacement. */ 16903 break; 16904 case 2: 16905 /* 2 byte displacement. */ 16906 bytes_before_imm += 2; 16907 break; 16908 case 1: 16909 /* 1 byte displacement: when decoding the third source, 16910 don't increase bytes_before_imm as this has already 16911 been incremented by one in OP_E_memory while decoding 16912 the second source operand. */ 16913 if (opnum == 0) 16914 bytes_before_imm++; 16915 16916 break; 16917 } 16918 } 16919 } 16920 } 16921 16922 FETCH_DATA (the_info, codep + bytes_before_imm + 1); 16923 return codep [bytes_before_imm]; 16924 } 16925 16926 static void 16927 OP_EX_VexReg (int bytemode, int sizeflag, int reg) 16928 { 16929 const char **names; 16930 16931 if (reg == -1 && modrm.mod != 3) 16932 { 16933 OP_E_memory (bytemode, sizeflag); 16934 return; 16935 } 16936 else 16937 { 16938 if (reg == -1) 16939 { 16940 reg = modrm.rm; 16941 USED_REX (REX_B); 16942 if (rex & REX_B) 16943 reg += 8; 16944 } 16945 else if (reg > 7 && address_mode != mode_64bit) 16946 BadOp (); 16947 } 16948 16949 switch (vex.length) 16950 { 16951 case 128: 16952 names = names_xmm; 16953 break; 16954 case 256: 16955 names = names_ymm; 16956 break; 16957 default: 16958 abort (); 16959 } 16960 oappend (names[reg]); 16961 } 16962 16963 static void 16964 OP_EX_VexImmW (int bytemode, int sizeflag) 16965 { 16966 int reg = -1; 16967 static unsigned char vex_imm8; 16968 16969 if (vex_w_done == 0) 16970 { 16971 vex_w_done = 1; 16972 16973 /* Skip mod/rm byte. */ 16974 MODRM_CHECK; 16975 codep++; 16976 16977 vex_imm8 = get_vex_imm8 (sizeflag, 0); 16978 16979 if (vex.w) 16980 reg = vex_imm8 >> 4; 16981 16982 OP_EX_VexReg (bytemode, sizeflag, reg); 16983 } 16984 else if (vex_w_done == 1) 16985 { 16986 vex_w_done = 2; 16987 16988 if (!vex.w) 16989 reg = vex_imm8 >> 4; 16990 16991 OP_EX_VexReg (bytemode, sizeflag, reg); 16992 } 16993 else 16994 { 16995 /* Output the imm8 directly. */ 16996 scratchbuf[0] = '$'; 16997 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); 16998 oappend_maybe_intel (scratchbuf); 16999 scratchbuf[0] = '\0'; 17000 codep++; 17001 } 17002 } 17003 17004 static void 17005 OP_Vex_2src (int bytemode, int sizeflag) 17006 { 17007 if (modrm.mod == 3) 17008 { 17009 int reg = modrm.rm; 17010 USED_REX (REX_B); 17011 if (rex & REX_B) 17012 reg += 8; 17013 oappend (names_xmm[reg]); 17014 } 17015 else 17016 { 17017 if (intel_syntax 17018 && (bytemode == v_mode || bytemode == v_swap_mode)) 17019 { 17020 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 17021 used_prefixes |= (prefixes & PREFIX_DATA); 17022 } 17023 OP_E (bytemode, sizeflag); 17024 } 17025 } 17026 17027 static void 17028 OP_Vex_2src_1 (int bytemode, int sizeflag) 17029 { 17030 if (modrm.mod == 3) 17031 { 17032 /* Skip mod/rm byte. */ 17033 MODRM_CHECK; 17034 codep++; 17035 } 17036 17037 if (vex.w) 17038 oappend (names_xmm[vex.register_specifier]); 17039 else 17040 OP_Vex_2src (bytemode, sizeflag); 17041 } 17042 17043 static void 17044 OP_Vex_2src_2 (int bytemode, int sizeflag) 17045 { 17046 if (vex.w) 17047 OP_Vex_2src (bytemode, sizeflag); 17048 else 17049 oappend (names_xmm[vex.register_specifier]); 17050 } 17051 17052 static void 17053 OP_EX_VexW (int bytemode, int sizeflag) 17054 { 17055 int reg = -1; 17056 17057 if (!vex_w_done) 17058 { 17059 vex_w_done = 1; 17060 17061 /* Skip mod/rm byte. */ 17062 MODRM_CHECK; 17063 codep++; 17064 17065 if (vex.w) 17066 reg = get_vex_imm8 (sizeflag, 0) >> 4; 17067 } 17068 else 17069 { 17070 if (!vex.w) 17071 reg = get_vex_imm8 (sizeflag, 1) >> 4; 17072 } 17073 17074 OP_EX_VexReg (bytemode, sizeflag, reg); 17075 } 17076 17077 static void 17078 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, 17079 int sizeflag ATTRIBUTE_UNUSED) 17080 { 17081 /* Skip the immediate byte and check for invalid bits. */ 17082 FETCH_DATA (the_info, codep + 1); 17083 if (*codep++ & 0xf) 17084 BadOp (); 17085 } 17086 17087 static void 17088 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 17089 { 17090 int reg; 17091 const char **names; 17092 17093 FETCH_DATA (the_info, codep + 1); 17094 reg = *codep++; 17095 17096 if (bytemode != x_mode) 17097 abort (); 17098 17099 if (reg & 0xf) 17100 BadOp (); 17101 17102 reg >>= 4; 17103 if (reg > 7 && address_mode != mode_64bit) 17104 BadOp (); 17105 17106 switch (vex.length) 17107 { 17108 case 128: 17109 names = names_xmm; 17110 break; 17111 case 256: 17112 names = names_ymm; 17113 break; 17114 default: 17115 abort (); 17116 } 17117 oappend (names[reg]); 17118 } 17119 17120 static void 17121 OP_XMM_VexW (int bytemode, int sizeflag) 17122 { 17123 /* Turn off the REX.W bit since it is used for swapping operands 17124 now. */ 17125 rex &= ~REX_W; 17126 OP_XMM (bytemode, sizeflag); 17127 } 17128 17129 static void 17130 OP_EX_Vex (int bytemode, int sizeflag) 17131 { 17132 if (modrm.mod != 3) 17133 { 17134 if (vex.register_specifier != 0) 17135 BadOp (); 17136 need_vex_reg = 0; 17137 } 17138 OP_EX (bytemode, sizeflag); 17139 } 17140 17141 static void 17142 OP_XMM_Vex (int bytemode, int sizeflag) 17143 { 17144 if (modrm.mod != 3) 17145 { 17146 if (vex.register_specifier != 0) 17147 BadOp (); 17148 need_vex_reg = 0; 17149 } 17150 OP_XMM (bytemode, sizeflag); 17151 } 17152 17153 static void 17154 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 17155 { 17156 switch (vex.length) 17157 { 17158 case 128: 17159 mnemonicendp = stpcpy (obuf, "vzeroupper"); 17160 break; 17161 case 256: 17162 mnemonicendp = stpcpy (obuf, "vzeroall"); 17163 break; 17164 default: 17165 abort (); 17166 } 17167 } 17168 17169 static struct op vex_cmp_op[] = 17170 { 17171 { STRING_COMMA_LEN ("eq") }, 17172 { STRING_COMMA_LEN ("lt") }, 17173 { STRING_COMMA_LEN ("le") }, 17174 { STRING_COMMA_LEN ("unord") }, 17175 { STRING_COMMA_LEN ("neq") }, 17176 { STRING_COMMA_LEN ("nlt") }, 17177 { STRING_COMMA_LEN ("nle") }, 17178 { STRING_COMMA_LEN ("ord") }, 17179 { STRING_COMMA_LEN ("eq_uq") }, 17180 { STRING_COMMA_LEN ("nge") }, 17181 { STRING_COMMA_LEN ("ngt") }, 17182 { STRING_COMMA_LEN ("false") }, 17183 { STRING_COMMA_LEN ("neq_oq") }, 17184 { STRING_COMMA_LEN ("ge") }, 17185 { STRING_COMMA_LEN ("gt") }, 17186 { STRING_COMMA_LEN ("true") }, 17187 { STRING_COMMA_LEN ("eq_os") }, 17188 { STRING_COMMA_LEN ("lt_oq") }, 17189 { STRING_COMMA_LEN ("le_oq") }, 17190 { STRING_COMMA_LEN ("unord_s") }, 17191 { STRING_COMMA_LEN ("neq_us") }, 17192 { STRING_COMMA_LEN ("nlt_uq") }, 17193 { STRING_COMMA_LEN ("nle_uq") }, 17194 { STRING_COMMA_LEN ("ord_s") }, 17195 { STRING_COMMA_LEN ("eq_us") }, 17196 { STRING_COMMA_LEN ("nge_uq") }, 17197 { STRING_COMMA_LEN ("ngt_uq") }, 17198 { STRING_COMMA_LEN ("false_os") }, 17199 { STRING_COMMA_LEN ("neq_os") }, 17200 { STRING_COMMA_LEN ("ge_oq") }, 17201 { STRING_COMMA_LEN ("gt_oq") }, 17202 { STRING_COMMA_LEN ("true_us") }, 17203 }; 17204 17205 static void 17206 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 17207 { 17208 unsigned int cmp_type; 17209 17210 FETCH_DATA (the_info, codep + 1); 17211 cmp_type = *codep++ & 0xff; 17212 if (cmp_type < ARRAY_SIZE (vex_cmp_op)) 17213 { 17214 char suffix [3]; 17215 char *p = mnemonicendp - 2; 17216 suffix[0] = p[0]; 17217 suffix[1] = p[1]; 17218 suffix[2] = '\0'; 17219 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); 17220 mnemonicendp += vex_cmp_op[cmp_type].len; 17221 } 17222 else 17223 { 17224 /* We have a reserved extension byte. Output it directly. */ 17225 scratchbuf[0] = '$'; 17226 print_operand_value (scratchbuf + 1, 1, cmp_type); 17227 oappend_maybe_intel (scratchbuf); 17228 scratchbuf[0] = '\0'; 17229 } 17230 } 17231 17232 static void 17233 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, 17234 int sizeflag ATTRIBUTE_UNUSED) 17235 { 17236 unsigned int cmp_type; 17237 17238 if (!vex.evex) 17239 abort (); 17240 17241 FETCH_DATA (the_info, codep + 1); 17242 cmp_type = *codep++ & 0xff; 17243 /* There are aliases for immediates 0, 1, 2, 4, 5, 6. 17244 If it's the case, print suffix, otherwise - print the immediate. */ 17245 if (cmp_type < ARRAY_SIZE (simd_cmp_op) 17246 && cmp_type != 3 17247 && cmp_type != 7) 17248 { 17249 char suffix [3]; 17250 char *p = mnemonicendp - 2; 17251 17252 /* vpcmp* can have both one- and two-lettered suffix. */ 17253 if (p[0] == 'p') 17254 { 17255 p++; 17256 suffix[0] = p[0]; 17257 suffix[1] = '\0'; 17258 } 17259 else 17260 { 17261 suffix[0] = p[0]; 17262 suffix[1] = p[1]; 17263 suffix[2] = '\0'; 17264 } 17265 17266 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 17267 mnemonicendp += simd_cmp_op[cmp_type].len; 17268 } 17269 else 17270 { 17271 /* We have a reserved extension byte. Output it directly. */ 17272 scratchbuf[0] = '$'; 17273 print_operand_value (scratchbuf + 1, 1, cmp_type); 17274 oappend_maybe_intel (scratchbuf); 17275 scratchbuf[0] = '\0'; 17276 } 17277 } 17278 17279 static const struct op pclmul_op[] = 17280 { 17281 { STRING_COMMA_LEN ("lql") }, 17282 { STRING_COMMA_LEN ("hql") }, 17283 { STRING_COMMA_LEN ("lqh") }, 17284 { STRING_COMMA_LEN ("hqh") } 17285 }; 17286 17287 static void 17288 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, 17289 int sizeflag ATTRIBUTE_UNUSED) 17290 { 17291 unsigned int pclmul_type; 17292 17293 FETCH_DATA (the_info, codep + 1); 17294 pclmul_type = *codep++ & 0xff; 17295 switch (pclmul_type) 17296 { 17297 case 0x10: 17298 pclmul_type = 2; 17299 break; 17300 case 0x11: 17301 pclmul_type = 3; 17302 break; 17303 default: 17304 break; 17305 } 17306 if (pclmul_type < ARRAY_SIZE (pclmul_op)) 17307 { 17308 char suffix [4]; 17309 char *p = mnemonicendp - 3; 17310 suffix[0] = p[0]; 17311 suffix[1] = p[1]; 17312 suffix[2] = p[2]; 17313 suffix[3] = '\0'; 17314 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); 17315 mnemonicendp += pclmul_op[pclmul_type].len; 17316 } 17317 else 17318 { 17319 /* We have a reserved extension byte. Output it directly. */ 17320 scratchbuf[0] = '$'; 17321 print_operand_value (scratchbuf + 1, 1, pclmul_type); 17322 oappend_maybe_intel (scratchbuf); 17323 scratchbuf[0] = '\0'; 17324 } 17325 } 17326 17327 static void 17328 MOVBE_Fixup (int bytemode, int sizeflag) 17329 { 17330 /* Add proper suffix to "movbe". */ 17331 char *p = mnemonicendp; 17332 17333 switch (bytemode) 17334 { 17335 case v_mode: 17336 if (intel_syntax) 17337 goto skip; 17338 17339 USED_REX (REX_W); 17340 if (sizeflag & SUFFIX_ALWAYS) 17341 { 17342 if (rex & REX_W) 17343 *p++ = 'q'; 17344 else 17345 { 17346 if (sizeflag & DFLAG) 17347 *p++ = 'l'; 17348 else 17349 *p++ = 'w'; 17350 used_prefixes |= (prefixes & PREFIX_DATA); 17351 } 17352 } 17353 break; 17354 default: 17355 oappend (INTERNAL_DISASSEMBLER_ERROR); 17356 break; 17357 } 17358 mnemonicendp = p; 17359 *p = '\0'; 17360 17361 skip: 17362 OP_M (bytemode, sizeflag); 17363 } 17364 17365 static void 17366 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 17367 { 17368 int reg; 17369 const char **names; 17370 17371 /* Skip mod/rm byte. */ 17372 MODRM_CHECK; 17373 codep++; 17374 17375 if (vex.w) 17376 names = names64; 17377 else 17378 names = names32; 17379 17380 reg = modrm.rm; 17381 USED_REX (REX_B); 17382 if (rex & REX_B) 17383 reg += 8; 17384 17385 oappend (names[reg]); 17386 } 17387 17388 static void 17389 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 17390 { 17391 const char **names; 17392 17393 if (vex.w) 17394 names = names64; 17395 else 17396 names = names32; 17397 17398 oappend (names[vex.register_specifier]); 17399 } 17400 17401 static void 17402 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 17403 { 17404 if (!vex.evex 17405 || (bytemode != mask_mode && bytemode != mask_bd_mode)) 17406 abort (); 17407 17408 USED_REX (REX_R); 17409 if ((rex & REX_R) != 0 || !vex.r) 17410 { 17411 BadOp (); 17412 return; 17413 } 17414 17415 oappend (names_mask [modrm.reg]); 17416 } 17417 17418 static void 17419 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 17420 { 17421 if (!vex.evex 17422 || (bytemode != evex_rounding_mode 17423 && bytemode != evex_sae_mode)) 17424 abort (); 17425 if (modrm.mod == 3 && vex.b) 17426 switch (bytemode) 17427 { 17428 case evex_rounding_mode: 17429 oappend (names_rounding[vex.ll]); 17430 break; 17431 case evex_sae_mode: 17432 oappend ("{sae}"); 17433 break; 17434 default: 17435 break; 17436 } 17437 } 17438
Indexes created Mon Mar 23 00:23:30 UTC 2026