mips-dis.c revision 1.1.1.1
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include "dis-asm.h" 26 #include "libiberty.h" 27 #include "opcode/mips.h" 28 #include "opintl.h" 29 30 /* FIXME: These are needed to figure out if the code is mips16 or 31 not. The low bit of the address is often a good indicator. No 32 symbol table is available when this code runs out in an embedded 33 system as when it is used for disassembler support in a monitor. */ 34 35 #if !defined(EMBEDDED_ENV) 36 #define SYMTAB_AVAILABLE 1 37 #include "elf-bfd.h" 38 #include "elf/mips.h" 39 #endif 40 41 /* Mips instructions are at maximum this many bytes long. */ 42 #define INSNLEN 4 43 44 45 /* FIXME: These should be shared with gdb somehow. */ 47 48 struct mips_cp0sel_name 49 { 50 unsigned int cp0reg; 51 unsigned int sel; 52 const char * const name; 53 }; 54 55 /* The mips16 registers. */ 56 static const unsigned int mips16_to_32_reg_map[] = 57 { 58 16, 17, 2, 3, 4, 5, 6, 7 59 }; 60 61 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 62 63 64 static const char * const mips_gpr_names_numeric[32] = 65 { 66 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 67 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 68 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 69 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 70 }; 71 72 static const char * const mips_gpr_names_oldabi[32] = 73 { 74 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 75 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 76 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 77 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 78 }; 79 80 static const char * const mips_gpr_names_newabi[32] = 81 { 82 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 83 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 84 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 85 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 86 }; 87 88 static const char * const mips_fpr_names_numeric[32] = 89 { 90 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 91 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 92 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 93 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 94 }; 95 96 static const char * const mips_fpr_names_32[32] = 97 { 98 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 99 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 100 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 101 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 102 }; 103 104 static const char * const mips_fpr_names_n32[32] = 105 { 106 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 107 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 108 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 109 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 110 }; 111 112 static const char * const mips_fpr_names_64[32] = 113 { 114 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 115 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 116 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 117 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 118 }; 119 120 static const char * const mips_cp0_names_numeric[32] = 121 { 122 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 123 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 124 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 125 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 126 }; 127 128 static const char * const mips_cp0_names_r3000[32] = 129 { 130 "c0_index", "c0_random", "c0_entrylo", "$3", 131 "c0_context", "$5", "$6", "$7", 132 "c0_badvaddr", "$9", "c0_entryhi", "$11", 133 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 134 "$16", "$17", "$18", "$19", 135 "$20", "$21", "$22", "$23", 136 "$24", "$25", "$26", "$27", 137 "$28", "$29", "$30", "$31", 138 }; 139 140 static const char * const mips_cp0_names_r4000[32] = 141 { 142 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 143 "c0_context", "c0_pagemask", "c0_wired", "$7", 144 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 145 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 146 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 147 "c0_xcontext", "$21", "$22", "$23", 148 "$24", "$25", "c0_ecc", "c0_cacheerr", 149 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 150 }; 151 152 static const char * const mips_cp0_names_mips3264[32] = 153 { 154 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 155 "c0_context", "c0_pagemask", "c0_wired", "$7", 156 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 157 "c0_status", "c0_cause", "c0_epc", "c0_prid", 158 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 159 "c0_xcontext", "$21", "$22", "c0_debug", 160 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 161 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 162 }; 163 164 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 165 { 166 { 16, 1, "c0_config1" }, 167 { 16, 2, "c0_config2" }, 168 { 16, 3, "c0_config3" }, 169 { 18, 1, "c0_watchlo,1" }, 170 { 18, 2, "c0_watchlo,2" }, 171 { 18, 3, "c0_watchlo,3" }, 172 { 18, 4, "c0_watchlo,4" }, 173 { 18, 5, "c0_watchlo,5" }, 174 { 18, 6, "c0_watchlo,6" }, 175 { 18, 7, "c0_watchlo,7" }, 176 { 19, 1, "c0_watchhi,1" }, 177 { 19, 2, "c0_watchhi,2" }, 178 { 19, 3, "c0_watchhi,3" }, 179 { 19, 4, "c0_watchhi,4" }, 180 { 19, 5, "c0_watchhi,5" }, 181 { 19, 6, "c0_watchhi,6" }, 182 { 19, 7, "c0_watchhi,7" }, 183 { 25, 1, "c0_perfcnt,1" }, 184 { 25, 2, "c0_perfcnt,2" }, 185 { 25, 3, "c0_perfcnt,3" }, 186 { 25, 4, "c0_perfcnt,4" }, 187 { 25, 5, "c0_perfcnt,5" }, 188 { 25, 6, "c0_perfcnt,6" }, 189 { 25, 7, "c0_perfcnt,7" }, 190 { 27, 1, "c0_cacheerr,1" }, 191 { 27, 2, "c0_cacheerr,2" }, 192 { 27, 3, "c0_cacheerr,3" }, 193 { 28, 1, "c0_datalo" }, 194 { 29, 1, "c0_datahi" } 195 }; 196 197 static const char * const mips_cp0_names_mips3264r2[32] = 198 { 199 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 200 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 201 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 202 "c0_status", "c0_cause", "c0_epc", "c0_prid", 203 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 204 "c0_xcontext", "$21", "$22", "c0_debug", 205 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 206 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 207 }; 208 209 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 210 { 211 { 4, 1, "c0_contextconfig" }, 212 { 0, 1, "c0_mvpcontrol" }, 213 { 0, 2, "c0_mvpconf0" }, 214 { 0, 3, "c0_mvpconf1" }, 215 { 1, 1, "c0_vpecontrol" }, 216 { 1, 2, "c0_vpeconf0" }, 217 { 1, 3, "c0_vpeconf1" }, 218 { 1, 4, "c0_yqmask" }, 219 { 1, 5, "c0_vpeschedule" }, 220 { 1, 6, "c0_vpeschefback" }, 221 { 2, 1, "c0_tcstatus" }, 222 { 2, 2, "c0_tcbind" }, 223 { 2, 3, "c0_tcrestart" }, 224 { 2, 4, "c0_tchalt" }, 225 { 2, 5, "c0_tccontext" }, 226 { 2, 6, "c0_tcschedule" }, 227 { 2, 7, "c0_tcschefback" }, 228 { 5, 1, "c0_pagegrain" }, 229 { 6, 1, "c0_srsconf0" }, 230 { 6, 2, "c0_srsconf1" }, 231 { 6, 3, "c0_srsconf2" }, 232 { 6, 4, "c0_srsconf3" }, 233 { 6, 5, "c0_srsconf4" }, 234 { 12, 1, "c0_intctl" }, 235 { 12, 2, "c0_srsctl" }, 236 { 12, 3, "c0_srsmap" }, 237 { 15, 1, "c0_ebase" }, 238 { 16, 1, "c0_config1" }, 239 { 16, 2, "c0_config2" }, 240 { 16, 3, "c0_config3" }, 241 { 18, 1, "c0_watchlo,1" }, 242 { 18, 2, "c0_watchlo,2" }, 243 { 18, 3, "c0_watchlo,3" }, 244 { 18, 4, "c0_watchlo,4" }, 245 { 18, 5, "c0_watchlo,5" }, 246 { 18, 6, "c0_watchlo,6" }, 247 { 18, 7, "c0_watchlo,7" }, 248 { 19, 1, "c0_watchhi,1" }, 249 { 19, 2, "c0_watchhi,2" }, 250 { 19, 3, "c0_watchhi,3" }, 251 { 19, 4, "c0_watchhi,4" }, 252 { 19, 5, "c0_watchhi,5" }, 253 { 19, 6, "c0_watchhi,6" }, 254 { 19, 7, "c0_watchhi,7" }, 255 { 23, 1, "c0_tracecontrol" }, 256 { 23, 2, "c0_tracecontrol2" }, 257 { 23, 3, "c0_usertracedata" }, 258 { 23, 4, "c0_tracebpc" }, 259 { 25, 1, "c0_perfcnt,1" }, 260 { 25, 2, "c0_perfcnt,2" }, 261 { 25, 3, "c0_perfcnt,3" }, 262 { 25, 4, "c0_perfcnt,4" }, 263 { 25, 5, "c0_perfcnt,5" }, 264 { 25, 6, "c0_perfcnt,6" }, 265 { 25, 7, "c0_perfcnt,7" }, 266 { 27, 1, "c0_cacheerr,1" }, 267 { 27, 2, "c0_cacheerr,2" }, 268 { 27, 3, "c0_cacheerr,3" }, 269 { 28, 1, "c0_datalo" }, 270 { 28, 2, "c0_taglo1" }, 271 { 28, 3, "c0_datalo1" }, 272 { 28, 4, "c0_taglo2" }, 273 { 28, 5, "c0_datalo2" }, 274 { 28, 6, "c0_taglo3" }, 275 { 28, 7, "c0_datalo3" }, 276 { 29, 1, "c0_datahi" }, 277 { 29, 2, "c0_taghi1" }, 278 { 29, 3, "c0_datahi1" }, 279 { 29, 4, "c0_taghi2" }, 280 { 29, 5, "c0_datahi2" }, 281 { 29, 6, "c0_taghi3" }, 282 { 29, 7, "c0_datahi3" }, 283 }; 284 285 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 286 static const char * const mips_cp0_names_sb1[32] = 287 { 288 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 289 "c0_context", "c0_pagemask", "c0_wired", "$7", 290 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 291 "c0_status", "c0_cause", "c0_epc", "c0_prid", 292 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 293 "c0_xcontext", "$21", "$22", "c0_debug", 294 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 295 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 296 }; 297 298 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 299 { 300 { 16, 1, "c0_config1" }, 301 { 18, 1, "c0_watchlo,1" }, 302 { 19, 1, "c0_watchhi,1" }, 303 { 22, 0, "c0_perftrace" }, 304 { 23, 3, "c0_edebug" }, 305 { 25, 1, "c0_perfcnt,1" }, 306 { 25, 2, "c0_perfcnt,2" }, 307 { 25, 3, "c0_perfcnt,3" }, 308 { 25, 4, "c0_perfcnt,4" }, 309 { 25, 5, "c0_perfcnt,5" }, 310 { 25, 6, "c0_perfcnt,6" }, 311 { 25, 7, "c0_perfcnt,7" }, 312 { 26, 1, "c0_buserr_pa" }, 313 { 27, 1, "c0_cacheerr_d" }, 314 { 27, 3, "c0_cacheerr_d_pa" }, 315 { 28, 1, "c0_datalo_i" }, 316 { 28, 2, "c0_taglo_d" }, 317 { 28, 3, "c0_datalo_d" }, 318 { 29, 1, "c0_datahi_i" }, 319 { 29, 2, "c0_taghi_d" }, 320 { 29, 3, "c0_datahi_d" }, 321 }; 322 323 /* Xlr cop0 register names. */ 324 static const char * const mips_cp0_names_xlr[32] = { 325 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 326 "c0_context", "c0_pagemask", "c0_wired", "$7", 327 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 328 "c0_status", "c0_cause", "c0_epc", "c0_prid", 329 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 330 "c0_xcontext", "$21", "$22", "c0_debug", 331 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 332 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 333 }; 334 335 /* XLR's CP0 Select Registers. */ 336 337 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 338 { 9, 6, "c0_extintreq" }, 339 { 9, 7, "c0_extintmask" }, 340 { 15, 1, "c0_ebase" }, 341 { 16, 1, "c0_config1" }, 342 { 16, 2, "c0_config2" }, 343 { 16, 3, "c0_config3" }, 344 { 16, 7, "c0_procid2" }, 345 { 18, 1, "c0_watchlo,1" }, 346 { 18, 2, "c0_watchlo,2" }, 347 { 18, 3, "c0_watchlo,3" }, 348 { 18, 4, "c0_watchlo,4" }, 349 { 18, 5, "c0_watchlo,5" }, 350 { 18, 6, "c0_watchlo,6" }, 351 { 18, 7, "c0_watchlo,7" }, 352 { 19, 1, "c0_watchhi,1" }, 353 { 19, 2, "c0_watchhi,2" }, 354 { 19, 3, "c0_watchhi,3" }, 355 { 19, 4, "c0_watchhi,4" }, 356 { 19, 5, "c0_watchhi,5" }, 357 { 19, 6, "c0_watchhi,6" }, 358 { 19, 7, "c0_watchhi,7" }, 359 { 25, 1, "c0_perfcnt,1" }, 360 { 25, 2, "c0_perfcnt,2" }, 361 { 25, 3, "c0_perfcnt,3" }, 362 { 25, 4, "c0_perfcnt,4" }, 363 { 25, 5, "c0_perfcnt,5" }, 364 { 25, 6, "c0_perfcnt,6" }, 365 { 25, 7, "c0_perfcnt,7" }, 366 { 27, 1, "c0_cacheerr,1" }, 367 { 27, 2, "c0_cacheerr,2" }, 368 { 27, 3, "c0_cacheerr,3" }, 369 { 28, 1, "c0_datalo" }, 370 { 29, 1, "c0_datahi" } 371 }; 372 373 static const char * const mips_hwr_names_numeric[32] = 374 { 375 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 376 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 377 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 378 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 379 }; 380 381 static const char * const mips_hwr_names_mips3264r2[32] = 382 { 383 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 384 "$4", "$5", "$6", "$7", 385 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 386 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 387 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 388 }; 389 390 struct mips_abi_choice 391 { 392 const char * name; 393 const char * const *gpr_names; 394 const char * const *fpr_names; 395 }; 396 397 struct mips_abi_choice mips_abi_choices[] = 398 { 399 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 400 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 401 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 402 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 403 }; 404 405 struct mips_arch_choice 406 { 407 const char *name; 408 int bfd_mach_valid; 409 unsigned long bfd_mach; 410 int processor; 411 int isa; 412 const char * const *cp0_names; 413 const struct mips_cp0sel_name *cp0sel_names; 414 unsigned int cp0sel_names_len; 415 const char * const *hwr_names; 416 }; 417 418 const struct mips_arch_choice mips_arch_choices[] = 419 { 420 { "numeric", 0, 0, 0, 0, 421 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 422 423 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 424 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, 425 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 426 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 427 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 428 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 429 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 430 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 431 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 432 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 433 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 434 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 435 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 436 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 437 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 438 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 439 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 440 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 441 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 442 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 443 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 444 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 445 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 446 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 447 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 448 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 449 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 450 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 451 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 452 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 453 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 454 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 455 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 456 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 457 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 458 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 459 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 460 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 461 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 462 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 463 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 464 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 465 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 466 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 467 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 468 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 469 470 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 471 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 472 _MIPS32 Architecture For Programmers Volume I: Introduction to the 473 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 474 page 1. */ 475 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 476 ISA_MIPS32 | INSN_SMARTMIPS, 477 mips_cp0_names_mips3264, 478 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 479 mips_hwr_names_numeric }, 480 481 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 482 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 483 | INSN_MIPS3D | INSN_MT), 484 mips_cp0_names_mips3264r2, 485 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 486 mips_hwr_names_mips3264r2 }, 487 488 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 489 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 490 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX, 491 mips_cp0_names_mips3264, 492 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 493 mips_hwr_names_numeric }, 494 495 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 496 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 497 | INSN_DSP64 | INSN_MT | INSN_MDMX), 498 mips_cp0_names_mips3264r2, 499 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 500 mips_hwr_names_mips3264r2 }, 501 502 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 503 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 504 mips_cp0_names_sb1, 505 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 506 mips_hwr_names_numeric }, 507 508 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 509 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, 510 NULL, 0, mips_hwr_names_numeric }, 511 512 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 513 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 514 NULL, 0, mips_hwr_names_numeric }, 515 516 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 517 ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric, 518 NULL, 0, mips_hwr_names_numeric }, 519 520 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 521 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, 522 mips_hwr_names_numeric }, 523 524 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 525 ISA_MIPS64 | INSN_XLR, 526 mips_cp0_names_xlr, 527 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 528 mips_hwr_names_numeric }, 529 530 /* This entry, mips16, is here only for ISA/processor selection; do 531 not print its name. */ 532 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 533 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 534 }; 535 536 /* ISA and processor type to disassemble for, and register names to use. 537 set_default_mips_dis_options and parse_mips_dis_options fill in these 538 values. */ 539 static int mips_processor; 540 static int mips_isa; 541 static const char * const *mips_gpr_names; 542 static const char * const *mips_fpr_names; 543 static const char * const *mips_cp0_names; 544 static const struct mips_cp0sel_name *mips_cp0sel_names; 545 static int mips_cp0sel_names_len; 546 static const char * const *mips_hwr_names; 547 548 /* Other options */ 549 static int no_aliases; /* If set disassemble as most general inst. */ 550 551 static const struct mips_abi_choice * 553 choose_abi_by_name (const char *name, unsigned int namelen) 554 { 555 const struct mips_abi_choice *c; 556 unsigned int i; 557 558 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 559 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 560 && strlen (mips_abi_choices[i].name) == namelen) 561 c = &mips_abi_choices[i]; 562 563 return c; 564 } 565 566 static const struct mips_arch_choice * 567 choose_arch_by_name (const char *name, unsigned int namelen) 568 { 569 const struct mips_arch_choice *c = NULL; 570 unsigned int i; 571 572 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 573 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 574 && strlen (mips_arch_choices[i].name) == namelen) 575 c = &mips_arch_choices[i]; 576 577 return c; 578 } 579 580 static const struct mips_arch_choice * 581 choose_arch_by_number (unsigned long mach) 582 { 583 static unsigned long hint_bfd_mach; 584 static const struct mips_arch_choice *hint_arch_choice; 585 const struct mips_arch_choice *c; 586 unsigned int i; 587 588 /* We optimize this because even if the user specifies no 589 flags, this will be done for every instruction! */ 590 if (hint_bfd_mach == mach 591 && hint_arch_choice != NULL 592 && hint_arch_choice->bfd_mach == hint_bfd_mach) 593 return hint_arch_choice; 594 595 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 596 { 597 if (mips_arch_choices[i].bfd_mach_valid 598 && mips_arch_choices[i].bfd_mach == mach) 599 { 600 c = &mips_arch_choices[i]; 601 hint_bfd_mach = mach; 602 hint_arch_choice = c; 603 } 604 } 605 return c; 606 } 607 608 /* Check if the object uses NewABI conventions. */ 609 610 static int 611 is_newabi (Elf_Internal_Ehdr *header) 612 { 613 /* There are no old-style ABIs which use 64-bit ELF. */ 614 if (header->e_ident[EI_CLASS] == ELFCLASS64) 615 return 1; 616 617 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 618 if ((header->e_flags & EF_MIPS_ABI2) != 0) 619 return 1; 620 621 return 0; 622 } 623 624 static void 625 set_default_mips_dis_options (struct disassemble_info *info) 626 { 627 const struct mips_arch_choice *chosen_arch; 628 629 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 630 and numeric FPR, CP0 register, and HWR names. */ 631 mips_isa = ISA_MIPS3; 632 mips_processor = CPU_R3000; 633 mips_gpr_names = mips_gpr_names_oldabi; 634 mips_fpr_names = mips_fpr_names_numeric; 635 mips_cp0_names = mips_cp0_names_numeric; 636 mips_cp0sel_names = NULL; 637 mips_cp0sel_names_len = 0; 638 mips_hwr_names = mips_hwr_names_numeric; 639 no_aliases = 0; 640 641 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 642 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 643 { 644 Elf_Internal_Ehdr *header; 645 646 header = elf_elfheader (info->section->owner); 647 if (is_newabi (header)) 648 mips_gpr_names = mips_gpr_names_newabi; 649 } 650 651 /* Set ISA, architecture, and cp0 register names as best we can. */ 652 #if ! SYMTAB_AVAILABLE 653 /* This is running out on a target machine, not in a host tool. 654 FIXME: Where does mips_target_info come from? */ 655 target_processor = mips_target_info.processor; 656 mips_isa = mips_target_info.isa; 657 #else 658 chosen_arch = choose_arch_by_number (info->mach); 659 if (chosen_arch != NULL) 660 { 661 mips_processor = chosen_arch->processor; 662 mips_isa = chosen_arch->isa; 663 mips_cp0_names = chosen_arch->cp0_names; 664 mips_cp0sel_names = chosen_arch->cp0sel_names; 665 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 666 mips_hwr_names = chosen_arch->hwr_names; 667 } 668 #endif 669 } 670 671 static void 672 parse_mips_dis_option (const char *option, unsigned int len) 673 { 674 unsigned int i, optionlen, vallen; 675 const char *val; 676 const struct mips_abi_choice *chosen_abi; 677 const struct mips_arch_choice *chosen_arch; 678 679 /* Try to match options that are simple flags */ 680 if (CONST_STRNEQ (option, "no-aliases")) 681 { 682 no_aliases = 1; 683 return; 684 } 685 686 /* Look for the = that delimits the end of the option name. */ 687 for (i = 0; i < len; i++) 688 if (option[i] == '=') 689 break; 690 691 if (i == 0) /* Invalid option: no name before '='. */ 692 return; 693 if (i == len) /* Invalid option: no '='. */ 694 return; 695 if (i == (len - 1)) /* Invalid option: no value after '='. */ 696 return; 697 698 optionlen = i; 699 val = option + (optionlen + 1); 700 vallen = len - (optionlen + 1); 701 702 if (strncmp ("gpr-names", option, optionlen) == 0 703 && strlen ("gpr-names") == optionlen) 704 { 705 chosen_abi = choose_abi_by_name (val, vallen); 706 if (chosen_abi != NULL) 707 mips_gpr_names = chosen_abi->gpr_names; 708 return; 709 } 710 711 if (strncmp ("fpr-names", option, optionlen) == 0 712 && strlen ("fpr-names") == optionlen) 713 { 714 chosen_abi = choose_abi_by_name (val, vallen); 715 if (chosen_abi != NULL) 716 mips_fpr_names = chosen_abi->fpr_names; 717 return; 718 } 719 720 if (strncmp ("cp0-names", option, optionlen) == 0 721 && strlen ("cp0-names") == optionlen) 722 { 723 chosen_arch = choose_arch_by_name (val, vallen); 724 if (chosen_arch != NULL) 725 { 726 mips_cp0_names = chosen_arch->cp0_names; 727 mips_cp0sel_names = chosen_arch->cp0sel_names; 728 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 729 } 730 return; 731 } 732 733 if (strncmp ("hwr-names", option, optionlen) == 0 734 && strlen ("hwr-names") == optionlen) 735 { 736 chosen_arch = choose_arch_by_name (val, vallen); 737 if (chosen_arch != NULL) 738 mips_hwr_names = chosen_arch->hwr_names; 739 return; 740 } 741 742 if (strncmp ("reg-names", option, optionlen) == 0 743 && strlen ("reg-names") == optionlen) 744 { 745 /* We check both ABI and ARCH here unconditionally, so 746 that "numeric" will do the desirable thing: select 747 numeric register names for all registers. Other than 748 that, a given name probably won't match both. */ 749 chosen_abi = choose_abi_by_name (val, vallen); 750 if (chosen_abi != NULL) 751 { 752 mips_gpr_names = chosen_abi->gpr_names; 753 mips_fpr_names = chosen_abi->fpr_names; 754 } 755 chosen_arch = choose_arch_by_name (val, vallen); 756 if (chosen_arch != NULL) 757 { 758 mips_cp0_names = chosen_arch->cp0_names; 759 mips_cp0sel_names = chosen_arch->cp0sel_names; 760 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 761 mips_hwr_names = chosen_arch->hwr_names; 762 } 763 return; 764 } 765 766 /* Invalid option. */ 767 } 768 769 static void 770 parse_mips_dis_options (const char *options) 771 { 772 const char *option_end; 773 774 if (options == NULL) 775 return; 776 777 while (*options != '\0') 778 { 779 /* Skip empty options. */ 780 if (*options == ',') 781 { 782 options++; 783 continue; 784 } 785 786 /* We know that *options is neither NUL or a comma. */ 787 option_end = options + 1; 788 while (*option_end != ',' && *option_end != '\0') 789 option_end++; 790 791 parse_mips_dis_option (options, option_end - options); 792 793 /* Go on to the next one. If option_end points to a comma, it 794 will be skipped above. */ 795 options = option_end; 796 } 797 } 798 799 static const struct mips_cp0sel_name * 800 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 801 unsigned int len, 802 unsigned int cp0reg, 803 unsigned int sel) 804 { 805 unsigned int i; 806 807 for (i = 0; i < len; i++) 808 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 809 return &names[i]; 810 return NULL; 811 } 812 813 /* Print insn arguments for 32/64-bit code. */ 815 816 static void 817 print_insn_args (const char *d, 818 register unsigned long int l, 819 bfd_vma pc, 820 struct disassemble_info *info, 821 const struct mips_opcode *opp) 822 { 823 int op, delta; 824 unsigned int lsb, msb, msbd; 825 826 lsb = 0; 827 828 for (; *d != '\0'; d++) 829 { 830 switch (*d) 831 { 832 case ',': 833 case '(': 834 case ')': 835 case '[': 836 case ']': 837 (*info->fprintf_func) (info->stream, "%c", *d); 838 break; 839 840 case '+': 841 /* Extension character; switch for second char. */ 842 d++; 843 switch (*d) 844 { 845 case '\0': 846 /* xgettext:c-format */ 847 (*info->fprintf_func) (info->stream, 848 _("# internal error, incomplete extension sequence (+)")); 849 return; 850 851 case 'A': 852 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 853 (*info->fprintf_func) (info->stream, "0x%x", lsb); 854 break; 855 856 case 'B': 857 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 858 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 859 break; 860 861 case '1': 862 (*info->fprintf_func) (info->stream, "0x%lx", 863 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 864 break; 865 866 case '2': 867 (*info->fprintf_func) (info->stream, "0x%lx", 868 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 869 break; 870 871 case '3': 872 (*info->fprintf_func) (info->stream, "0x%lx", 873 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 874 break; 875 876 case '4': 877 (*info->fprintf_func) (info->stream, "0x%lx", 878 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 879 break; 880 881 case 'C': 882 case 'H': 883 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 884 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 885 break; 886 887 case 'D': 888 { 889 const struct mips_cp0sel_name *n; 890 unsigned int cp0reg, sel; 891 892 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 893 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 894 895 /* CP0 register including 'sel' code for mtcN (et al.), to be 896 printed textually if known. If not known, print both 897 CP0 register name and sel numerically since CP0 register 898 with sel 0 may have a name unrelated to register being 899 printed. */ 900 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 901 mips_cp0sel_names_len, cp0reg, sel); 902 if (n != NULL) 903 (*info->fprintf_func) (info->stream, "%s", n->name); 904 else 905 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 906 break; 907 } 908 909 case 'E': 910 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 911 (*info->fprintf_func) (info->stream, "0x%x", lsb); 912 break; 913 914 case 'F': 915 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 916 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 917 break; 918 919 case 'G': 920 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 921 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 922 break; 923 924 case 't': /* Coprocessor 0 reg name */ 925 (*info->fprintf_func) (info->stream, "%s", 926 mips_cp0_names[(l >> OP_SH_RT) & 927 OP_MASK_RT]); 928 break; 929 930 case 'T': /* Coprocessor 0 reg name */ 931 { 932 const struct mips_cp0sel_name *n; 933 unsigned int cp0reg, sel; 934 935 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 936 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 937 938 /* CP0 register including 'sel' code for mftc0, to be 939 printed textually if known. If not known, print both 940 CP0 register name and sel numerically since CP0 register 941 with sel 0 may have a name unrelated to register being 942 printed. */ 943 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 944 mips_cp0sel_names_len, cp0reg, sel); 945 if (n != NULL) 946 (*info->fprintf_func) (info->stream, "%s", n->name); 947 else 948 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 949 break; 950 } 951 952 case 'x': /* bbit bit index */ 953 (*info->fprintf_func) (info->stream, "0x%lx", 954 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND); 955 break; 956 957 case 'p': /* cins, cins32, exts and exts32 position */ 958 (*info->fprintf_func) (info->stream, "0x%lx", 959 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS); 960 break; 961 962 case 's': /* cins and exts length-minus-one */ 963 (*info->fprintf_func) (info->stream, "0x%lx", 964 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); 965 break; 966 967 case 'S': /* cins32 and exts32 length-minus-one field */ 968 (*info->fprintf_func) (info->stream, "0x%lx", 969 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); 970 break; 971 972 case 'Q': /* seqi/snei immediate field */ 973 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI; 974 /* Sign-extend it. */ 975 op = (op ^ 512) - 512; 976 (*info->fprintf_func) (info->stream, "%d", op); 977 break; 978 979 case 'a': /* 8-bit signed offset in bit 6 */ 980 delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A; 981 if (delta & 0x80) 982 delta |= ~OP_MASK_OFFSET_A; 983 (*info->fprintf_func) (info->stream, "%d", delta); 984 break; 985 986 case 'b': /* 8-bit signed offset in bit 3 */ 987 delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B; 988 if (delta & 0x80) 989 delta |= ~OP_MASK_OFFSET_B; 990 (*info->fprintf_func) (info->stream, "%d", delta); 991 break; 992 993 case 'c': /* 9-bit signed offset in bit 6 */ 994 delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C; 995 if (delta & 0x100) 996 delta |= ~OP_MASK_OFFSET_C; 997 /* Left shift 4 bits to print the real offset. */ 998 (*info->fprintf_func) (info->stream, "%d", delta << 4); 999 break; 1000 1001 case 'z': 1002 (*info->fprintf_func) (info->stream, "%s", 1003 mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]); 1004 break; 1005 1006 case 'Z': 1007 (*info->fprintf_func) (info->stream, "%s", 1008 mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]); 1009 break; 1010 1011 default: 1012 /* xgettext:c-format */ 1013 (*info->fprintf_func) (info->stream, 1014 _("# internal error, undefined extension sequence (+%c)"), 1015 *d); 1016 return; 1017 } 1018 break; 1019 1020 case '2': 1021 (*info->fprintf_func) (info->stream, "0x%lx", 1022 (l >> OP_SH_BP) & OP_MASK_BP); 1023 break; 1024 1025 case '3': 1026 (*info->fprintf_func) (info->stream, "0x%lx", 1027 (l >> OP_SH_SA3) & OP_MASK_SA3); 1028 break; 1029 1030 case '4': 1031 (*info->fprintf_func) (info->stream, "0x%lx", 1032 (l >> OP_SH_SA4) & OP_MASK_SA4); 1033 break; 1034 1035 case '5': 1036 (*info->fprintf_func) (info->stream, "0x%lx", 1037 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 1038 break; 1039 1040 case '6': 1041 (*info->fprintf_func) (info->stream, "0x%lx", 1042 (l >> OP_SH_RS) & OP_MASK_RS); 1043 break; 1044 1045 case '7': 1046 (*info->fprintf_func) (info->stream, "$ac%ld", 1047 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 1048 break; 1049 1050 case '8': 1051 (*info->fprintf_func) (info->stream, "0x%lx", 1052 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 1053 break; 1054 1055 case '9': 1056 (*info->fprintf_func) (info->stream, "$ac%ld", 1057 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 1058 break; 1059 1060 case '0': /* dsp 6-bit signed immediate in bit 20 */ 1061 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 1062 if (delta & 0x20) /* test sign bit */ 1063 delta |= ~OP_MASK_DSPSFT; 1064 (*info->fprintf_func) (info->stream, "%d", delta); 1065 break; 1066 1067 case ':': /* dsp 7-bit signed immediate in bit 19 */ 1068 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 1069 if (delta & 0x40) /* test sign bit */ 1070 delta |= ~OP_MASK_DSPSFT_7; 1071 (*info->fprintf_func) (info->stream, "%d", delta); 1072 break; 1073 1074 case '\'': 1075 (*info->fprintf_func) (info->stream, "0x%lx", 1076 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 1077 break; 1078 1079 case '@': /* dsp 10-bit signed immediate in bit 16 */ 1080 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 1081 if (delta & 0x200) /* test sign bit */ 1082 delta |= ~OP_MASK_IMM10; 1083 (*info->fprintf_func) (info->stream, "%d", delta); 1084 break; 1085 1086 case '!': 1087 (*info->fprintf_func) (info->stream, "%ld", 1088 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 1089 break; 1090 1091 case '$': 1092 (*info->fprintf_func) (info->stream, "%ld", 1093 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 1094 break; 1095 1096 case '*': 1097 (*info->fprintf_func) (info->stream, "$ac%ld", 1098 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 1099 break; 1100 1101 case '&': 1102 (*info->fprintf_func) (info->stream, "$ac%ld", 1103 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 1104 break; 1105 1106 case 'g': 1107 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 1108 (*info->fprintf_func) (info->stream, "$%ld", 1109 (l >> OP_SH_RD) & OP_MASK_RD); 1110 break; 1111 1112 case 's': 1113 case 'b': 1114 case 'r': 1115 case 'v': 1116 (*info->fprintf_func) (info->stream, "%s", 1117 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 1118 break; 1119 1120 case 't': 1121 case 'w': 1122 (*info->fprintf_func) (info->stream, "%s", 1123 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1124 break; 1125 1126 case 'i': 1127 case 'u': 1128 (*info->fprintf_func) (info->stream, "0x%lx", 1129 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 1130 break; 1131 1132 case 'j': /* Same as i, but sign-extended. */ 1133 case 'o': 1134 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 1135 if (delta & 0x8000) 1136 delta |= ~0xffff; 1137 (*info->fprintf_func) (info->stream, "%d", 1138 delta); 1139 break; 1140 1141 case 'h': 1142 (*info->fprintf_func) (info->stream, "0x%x", 1143 (unsigned int) ((l >> OP_SH_PREFX) 1144 & OP_MASK_PREFX)); 1145 break; 1146 1147 case 'k': 1148 (*info->fprintf_func) (info->stream, "0x%x", 1149 (unsigned int) ((l >> OP_SH_CACHE) 1150 & OP_MASK_CACHE)); 1151 break; 1152 1153 case 'a': 1154 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 1155 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 1156 /* For gdb disassembler, force odd address on jalx. */ 1157 if (info->flavour == bfd_target_unknown_flavour 1158 && strcmp (opp->name, "jalx") == 0) 1159 info->target |= 1; 1160 (*info->print_address_func) (info->target, info); 1161 break; 1162 1163 case 'p': 1164 /* Sign extend the displacement. */ 1165 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 1166 if (delta & 0x8000) 1167 delta |= ~0xffff; 1168 info->target = (delta << 2) + pc + INSNLEN; 1169 (*info->print_address_func) (info->target, info); 1170 break; 1171 1172 case 'd': 1173 (*info->fprintf_func) (info->stream, "%s", 1174 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1175 break; 1176 1177 case 'U': 1178 { 1179 /* First check for both rd and rt being equal. */ 1180 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 1181 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 1182 (*info->fprintf_func) (info->stream, "%s", 1183 mips_gpr_names[reg]); 1184 else 1185 { 1186 /* If one is zero use the other. */ 1187 if (reg == 0) 1188 (*info->fprintf_func) (info->stream, "%s", 1189 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1190 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 1191 (*info->fprintf_func) (info->stream, "%s", 1192 mips_gpr_names[reg]); 1193 else /* Bogus, result depends on processor. */ 1194 (*info->fprintf_func) (info->stream, "%s or %s", 1195 mips_gpr_names[reg], 1196 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1197 } 1198 } 1199 break; 1200 1201 case 'z': 1202 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1203 break; 1204 1205 case '<': 1206 case '1': 1207 (*info->fprintf_func) (info->stream, "0x%lx", 1208 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 1209 break; 1210 1211 case 'c': 1212 (*info->fprintf_func) (info->stream, "0x%lx", 1213 (l >> OP_SH_CODE) & OP_MASK_CODE); 1214 break; 1215 1216 case 'q': 1217 (*info->fprintf_func) (info->stream, "0x%lx", 1218 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 1219 break; 1220 1221 case 'C': 1222 (*info->fprintf_func) (info->stream, "0x%lx", 1223 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 1224 break; 1225 1226 case 'B': 1227 (*info->fprintf_func) (info->stream, "0x%lx", 1228 1229 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 1230 break; 1231 1232 case 'J': 1233 (*info->fprintf_func) (info->stream, "0x%lx", 1234 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 1235 break; 1236 1237 case 'S': 1238 case 'V': 1239 (*info->fprintf_func) (info->stream, "%s", 1240 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 1241 break; 1242 1243 case 'T': 1244 case 'W': 1245 (*info->fprintf_func) (info->stream, "%s", 1246 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 1247 break; 1248 1249 case 'D': 1250 (*info->fprintf_func) (info->stream, "%s", 1251 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 1252 break; 1253 1254 case 'R': 1255 (*info->fprintf_func) (info->stream, "%s", 1256 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 1257 break; 1258 1259 case 'E': 1260 /* Coprocessor register for lwcN instructions, et al. 1261 1262 Note that there is no load/store cp0 instructions, and 1263 that FPU (cp1) instructions disassemble this field using 1264 'T' format. Therefore, until we gain understanding of 1265 cp2 register names, we can simply print the register 1266 numbers. */ 1267 (*info->fprintf_func) (info->stream, "$%ld", 1268 (l >> OP_SH_RT) & OP_MASK_RT); 1269 break; 1270 1271 case 'G': 1272 /* Coprocessor register for mtcN instructions, et al. Note 1273 that FPU (cp1) instructions disassemble this field using 1274 'S' format. Therefore, we only need to worry about cp0, 1275 cp2, and cp3. */ 1276 op = (l >> OP_SH_OP) & OP_MASK_OP; 1277 if (op == OP_OP_COP0) 1278 (*info->fprintf_func) (info->stream, "%s", 1279 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1280 else 1281 (*info->fprintf_func) (info->stream, "$%ld", 1282 (l >> OP_SH_RD) & OP_MASK_RD); 1283 break; 1284 1285 case 'K': 1286 (*info->fprintf_func) (info->stream, "%s", 1287 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1288 break; 1289 1290 case 'N': 1291 (*info->fprintf_func) (info->stream, 1292 ((opp->pinfo & (FP_D | FP_S)) != 0 1293 ? "$fcc%ld" : "$cc%ld"), 1294 (l >> OP_SH_BCC) & OP_MASK_BCC); 1295 break; 1296 1297 case 'M': 1298 (*info->fprintf_func) (info->stream, "$fcc%ld", 1299 (l >> OP_SH_CCC) & OP_MASK_CCC); 1300 break; 1301 1302 case 'P': 1303 (*info->fprintf_func) (info->stream, "%ld", 1304 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 1305 break; 1306 1307 case 'e': 1308 (*info->fprintf_func) (info->stream, "%ld", 1309 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 1310 break; 1311 1312 case '%': 1313 (*info->fprintf_func) (info->stream, "%ld", 1314 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 1315 break; 1316 1317 case 'H': 1318 (*info->fprintf_func) (info->stream, "%ld", 1319 (l >> OP_SH_SEL) & OP_MASK_SEL); 1320 break; 1321 1322 case 'O': 1323 (*info->fprintf_func) (info->stream, "%ld", 1324 (l >> OP_SH_ALN) & OP_MASK_ALN); 1325 break; 1326 1327 case 'Q': 1328 { 1329 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 1330 1331 if ((vsel & 0x10) == 0) 1332 { 1333 int fmt; 1334 1335 vsel &= 0x0f; 1336 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1337 if ((vsel & 1) == 0) 1338 break; 1339 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 1340 (l >> OP_SH_FT) & OP_MASK_FT, 1341 vsel >> 1); 1342 } 1343 else if ((vsel & 0x08) == 0) 1344 { 1345 (*info->fprintf_func) (info->stream, "$v%ld", 1346 (l >> OP_SH_FT) & OP_MASK_FT); 1347 } 1348 else 1349 { 1350 (*info->fprintf_func) (info->stream, "0x%lx", 1351 (l >> OP_SH_FT) & OP_MASK_FT); 1352 } 1353 } 1354 break; 1355 1356 case 'X': 1357 (*info->fprintf_func) (info->stream, "$v%ld", 1358 (l >> OP_SH_FD) & OP_MASK_FD); 1359 break; 1360 1361 case 'Y': 1362 (*info->fprintf_func) (info->stream, "$v%ld", 1363 (l >> OP_SH_FS) & OP_MASK_FS); 1364 break; 1365 1366 case 'Z': 1367 (*info->fprintf_func) (info->stream, "$v%ld", 1368 (l >> OP_SH_FT) & OP_MASK_FT); 1369 break; 1370 1371 default: 1372 /* xgettext:c-format */ 1373 (*info->fprintf_func) (info->stream, 1374 _("# internal error, undefined modifier (%c)"), 1375 *d); 1376 return; 1377 } 1378 } 1379 } 1380 1381 /* Print the mips instruction at address MEMADDR in debugged memory, 1383 on using INFO. Returns length of the instruction, in bytes, which is 1384 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1385 this is little-endian code. */ 1386 1387 static int 1388 print_insn_mips (bfd_vma memaddr, 1389 unsigned long int word, 1390 struct disassemble_info *info) 1391 { 1392 const struct mips_opcode *op; 1393 static bfd_boolean init = 0; 1394 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1395 1396 /* Build a hash table to shorten the search time. */ 1397 if (! init) 1398 { 1399 unsigned int i; 1400 1401 for (i = 0; i <= OP_MASK_OP; i++) 1402 { 1403 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1404 { 1405 if (op->pinfo == INSN_MACRO 1406 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1407 continue; 1408 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 1409 { 1410 mips_hash[i] = op; 1411 break; 1412 } 1413 } 1414 } 1415 1416 init = 1; 1417 } 1418 1419 info->bytes_per_chunk = INSNLEN; 1420 info->display_endian = info->endian; 1421 info->insn_info_valid = 1; 1422 info->branch_delay_insns = 0; 1423 info->data_size = 0; 1424 info->insn_type = dis_nonbranch; 1425 info->target = 0; 1426 info->target2 = 0; 1427 1428 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 1429 if (op != NULL) 1430 { 1431 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1432 { 1433 if (op->pinfo != INSN_MACRO 1434 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1435 && (word & op->mask) == op->match) 1436 { 1437 const char *d; 1438 1439 /* We always allow to disassemble the jalx instruction. */ 1440 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 1441 && strcmp (op->name, "jalx")) 1442 continue; 1443 1444 /* Figure out instruction type and branch delay information. */ 1445 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1446 { 1447 if ((op->pinfo & (INSN_WRITE_GPR_31 1448 | INSN_WRITE_GPR_D)) != 0) 1449 info->insn_type = dis_jsr; 1450 else 1451 info->insn_type = dis_branch; 1452 info->branch_delay_insns = 1; 1453 } 1454 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1455 | INSN_COND_BRANCH_LIKELY)) != 0) 1456 { 1457 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1458 info->insn_type = dis_condjsr; 1459 else 1460 info->insn_type = dis_condbranch; 1461 info->branch_delay_insns = 1; 1462 } 1463 else if ((op->pinfo & (INSN_STORE_MEMORY 1464 | INSN_LOAD_MEMORY_DELAY)) != 0) 1465 info->insn_type = dis_dref; 1466 1467 (*info->fprintf_func) (info->stream, "%s", op->name); 1468 1469 d = op->args; 1470 if (d != NULL && *d != '\0') 1471 { 1472 (*info->fprintf_func) (info->stream, "\t"); 1473 print_insn_args (d, word, memaddr, info, op); 1474 } 1475 1476 return INSNLEN; 1477 } 1478 } 1479 } 1480 1481 /* Handle undefined instructions. */ 1482 info->insn_type = dis_noninsn; 1483 (*info->fprintf_func) (info->stream, "0x%lx", word); 1484 return INSNLEN; 1485 } 1486 1487 /* Disassemble an operand for a mips16 instruction. */ 1489 1490 static void 1491 print_mips16_insn_arg (char type, 1492 const struct mips_opcode *op, 1493 int l, 1494 bfd_boolean use_extend, 1495 int extend, 1496 bfd_vma memaddr, 1497 struct disassemble_info *info) 1498 { 1499 switch (type) 1500 { 1501 case ',': 1502 case '(': 1503 case ')': 1504 (*info->fprintf_func) (info->stream, "%c", type); 1505 break; 1506 1507 case 'y': 1508 case 'w': 1509 (*info->fprintf_func) (info->stream, "%s", 1510 mips16_reg_names(((l >> MIPS16OP_SH_RY) 1511 & MIPS16OP_MASK_RY))); 1512 break; 1513 1514 case 'x': 1515 case 'v': 1516 (*info->fprintf_func) (info->stream, "%s", 1517 mips16_reg_names(((l >> MIPS16OP_SH_RX) 1518 & MIPS16OP_MASK_RX))); 1519 break; 1520 1521 case 'z': 1522 (*info->fprintf_func) (info->stream, "%s", 1523 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 1524 & MIPS16OP_MASK_RZ))); 1525 break; 1526 1527 case 'Z': 1528 (*info->fprintf_func) (info->stream, "%s", 1529 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 1530 & MIPS16OP_MASK_MOVE32Z))); 1531 break; 1532 1533 case '0': 1534 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1535 break; 1536 1537 case 'S': 1538 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 1539 break; 1540 1541 case 'P': 1542 (*info->fprintf_func) (info->stream, "$pc"); 1543 break; 1544 1545 case 'R': 1546 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 1547 break; 1548 1549 case 'X': 1550 (*info->fprintf_func) (info->stream, "%s", 1551 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 1552 & MIPS16OP_MASK_REGR32)]); 1553 break; 1554 1555 case 'Y': 1556 (*info->fprintf_func) (info->stream, "%s", 1557 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 1558 break; 1559 1560 case '<': 1561 case '>': 1562 case '[': 1563 case ']': 1564 case '4': 1565 case '5': 1566 case 'H': 1567 case 'W': 1568 case 'D': 1569 case 'j': 1570 case '6': 1571 case '8': 1572 case 'V': 1573 case 'C': 1574 case 'U': 1575 case 'k': 1576 case 'K': 1577 case 'p': 1578 case 'q': 1579 case 'A': 1580 case 'B': 1581 case 'E': 1582 { 1583 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 1584 1585 shift = 0; 1586 signedp = 0; 1587 extbits = 16; 1588 pcrel = 0; 1589 extu = 0; 1590 branch = 0; 1591 switch (type) 1592 { 1593 case '<': 1594 nbits = 3; 1595 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1596 extbits = 5; 1597 extu = 1; 1598 break; 1599 case '>': 1600 nbits = 3; 1601 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1602 extbits = 5; 1603 extu = 1; 1604 break; 1605 case '[': 1606 nbits = 3; 1607 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1608 extbits = 6; 1609 extu = 1; 1610 break; 1611 case ']': 1612 nbits = 3; 1613 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1614 extbits = 6; 1615 extu = 1; 1616 break; 1617 case '4': 1618 nbits = 4; 1619 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 1620 signedp = 1; 1621 extbits = 15; 1622 break; 1623 case '5': 1624 nbits = 5; 1625 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1626 info->insn_type = dis_dref; 1627 info->data_size = 1; 1628 break; 1629 case 'H': 1630 nbits = 5; 1631 shift = 1; 1632 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1633 info->insn_type = dis_dref; 1634 info->data_size = 2; 1635 break; 1636 case 'W': 1637 nbits = 5; 1638 shift = 2; 1639 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1640 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 1641 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 1642 { 1643 info->insn_type = dis_dref; 1644 info->data_size = 4; 1645 } 1646 break; 1647 case 'D': 1648 nbits = 5; 1649 shift = 3; 1650 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1651 info->insn_type = dis_dref; 1652 info->data_size = 8; 1653 break; 1654 case 'j': 1655 nbits = 5; 1656 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1657 signedp = 1; 1658 break; 1659 case '6': 1660 nbits = 6; 1661 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1662 break; 1663 case '8': 1664 nbits = 8; 1665 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1666 break; 1667 case 'V': 1668 nbits = 8; 1669 shift = 2; 1670 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1671 /* FIXME: This might be lw, or it might be addiu to $sp or 1672 $pc. We assume it's load. */ 1673 info->insn_type = dis_dref; 1674 info->data_size = 4; 1675 break; 1676 case 'C': 1677 nbits = 8; 1678 shift = 3; 1679 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1680 info->insn_type = dis_dref; 1681 info->data_size = 8; 1682 break; 1683 case 'U': 1684 nbits = 8; 1685 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1686 extu = 1; 1687 break; 1688 case 'k': 1689 nbits = 8; 1690 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1691 signedp = 1; 1692 break; 1693 case 'K': 1694 nbits = 8; 1695 shift = 3; 1696 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1697 signedp = 1; 1698 break; 1699 case 'p': 1700 nbits = 8; 1701 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1702 signedp = 1; 1703 pcrel = 1; 1704 branch = 1; 1705 break; 1706 case 'q': 1707 nbits = 11; 1708 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 1709 signedp = 1; 1710 pcrel = 1; 1711 branch = 1; 1712 break; 1713 case 'A': 1714 nbits = 8; 1715 shift = 2; 1716 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1717 pcrel = 1; 1718 /* FIXME: This can be lw or la. We assume it is lw. */ 1719 info->insn_type = dis_dref; 1720 info->data_size = 4; 1721 break; 1722 case 'B': 1723 nbits = 5; 1724 shift = 3; 1725 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1726 pcrel = 1; 1727 info->insn_type = dis_dref; 1728 info->data_size = 8; 1729 break; 1730 case 'E': 1731 nbits = 5; 1732 shift = 2; 1733 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1734 pcrel = 1; 1735 break; 1736 default: 1737 abort (); 1738 } 1739 1740 if (! use_extend) 1741 { 1742 if (signedp && immed >= (1 << (nbits - 1))) 1743 immed -= 1 << nbits; 1744 immed <<= shift; 1745 if ((type == '<' || type == '>' || type == '[' || type == ']') 1746 && immed == 0) 1747 immed = 8; 1748 } 1749 else 1750 { 1751 if (extbits == 16) 1752 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1753 else if (extbits == 15) 1754 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1755 else 1756 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 1757 immed &= (1 << extbits) - 1; 1758 if (! extu && immed >= (1 << (extbits - 1))) 1759 immed -= 1 << extbits; 1760 } 1761 1762 if (! pcrel) 1763 (*info->fprintf_func) (info->stream, "%d", immed); 1764 else 1765 { 1766 bfd_vma baseaddr; 1767 1768 if (branch) 1769 { 1770 immed *= 2; 1771 baseaddr = memaddr + 2; 1772 } 1773 else if (use_extend) 1774 baseaddr = memaddr - 2; 1775 else 1776 { 1777 int status; 1778 bfd_byte buffer[2]; 1779 1780 baseaddr = memaddr; 1781 1782 /* If this instruction is in the delay slot of a jr 1783 instruction, the base address is the address of the 1784 jr instruction. If it is in the delay slot of jalr 1785 instruction, the base address is the address of the 1786 jalr instruction. This test is unreliable: we have 1787 no way of knowing whether the previous word is 1788 instruction or data. */ 1789 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 1790 info); 1791 if (status == 0 1792 && (((info->endian == BFD_ENDIAN_BIG 1793 ? bfd_getb16 (buffer) 1794 : bfd_getl16 (buffer)) 1795 & 0xf800) == 0x1800)) 1796 baseaddr = memaddr - 4; 1797 else 1798 { 1799 status = (*info->read_memory_func) (memaddr - 2, buffer, 1800 2, info); 1801 if (status == 0 1802 && (((info->endian == BFD_ENDIAN_BIG 1803 ? bfd_getb16 (buffer) 1804 : bfd_getl16 (buffer)) 1805 & 0xf81f) == 0xe800)) 1806 baseaddr = memaddr - 2; 1807 } 1808 } 1809 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 1810 if (pcrel && branch 1811 && info->flavour == bfd_target_unknown_flavour) 1812 /* For gdb disassembler, maintain odd address. */ 1813 info->target |= 1; 1814 (*info->print_address_func) (info->target, info); 1815 } 1816 } 1817 break; 1818 1819 case 'a': 1820 { 1821 int jalx = l & 0x400; 1822 1823 if (! use_extend) 1824 extend = 0; 1825 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 1826 if (!jalx && info->flavour == bfd_target_unknown_flavour) 1827 /* For gdb disassembler, maintain odd address. */ 1828 l |= 1; 1829 } 1830 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 1831 (*info->print_address_func) (info->target, info); 1832 break; 1833 1834 case 'l': 1835 case 'L': 1836 { 1837 int need_comma, amask, smask; 1838 1839 need_comma = 0; 1840 1841 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1842 1843 amask = (l >> 3) & 7; 1844 1845 if (amask > 0 && amask < 5) 1846 { 1847 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1848 if (amask > 1) 1849 (*info->fprintf_func) (info->stream, "-%s", 1850 mips_gpr_names[amask + 3]); 1851 need_comma = 1; 1852 } 1853 1854 smask = (l >> 1) & 3; 1855 if (smask == 3) 1856 { 1857 (*info->fprintf_func) (info->stream, "%s??", 1858 need_comma ? "," : ""); 1859 need_comma = 1; 1860 } 1861 else if (smask > 0) 1862 { 1863 (*info->fprintf_func) (info->stream, "%s%s", 1864 need_comma ? "," : "", 1865 mips_gpr_names[16]); 1866 if (smask > 1) 1867 (*info->fprintf_func) (info->stream, "-%s", 1868 mips_gpr_names[smask + 15]); 1869 need_comma = 1; 1870 } 1871 1872 if (l & 1) 1873 { 1874 (*info->fprintf_func) (info->stream, "%s%s", 1875 need_comma ? "," : "", 1876 mips_gpr_names[31]); 1877 need_comma = 1; 1878 } 1879 1880 if (amask == 5 || amask == 6) 1881 { 1882 (*info->fprintf_func) (info->stream, "%s$f0", 1883 need_comma ? "," : ""); 1884 if (amask == 6) 1885 (*info->fprintf_func) (info->stream, "-$f1"); 1886 } 1887 } 1888 break; 1889 1890 case 'm': 1891 case 'M': 1892 /* MIPS16e save/restore. */ 1893 { 1894 int need_comma = 0; 1895 int amask, args, statics; 1896 int nsreg, smask; 1897 int framesz; 1898 int i, j; 1899 1900 l = l & 0x7f; 1901 if (use_extend) 1902 l |= extend << 16; 1903 1904 amask = (l >> 16) & 0xf; 1905 if (amask == MIPS16_ALL_ARGS) 1906 { 1907 args = 4; 1908 statics = 0; 1909 } 1910 else if (amask == MIPS16_ALL_STATICS) 1911 { 1912 args = 0; 1913 statics = 4; 1914 } 1915 else 1916 { 1917 args = amask >> 2; 1918 statics = amask & 3; 1919 } 1920 1921 if (args > 0) { 1922 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1923 if (args > 1) 1924 (*info->fprintf_func) (info->stream, "-%s", 1925 mips_gpr_names[4 + args - 1]); 1926 need_comma = 1; 1927 } 1928 1929 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 1930 if (framesz == 0 && !use_extend) 1931 framesz = 128; 1932 1933 (*info->fprintf_func) (info->stream, "%s%d", 1934 need_comma ? "," : "", 1935 framesz); 1936 1937 if (l & 0x40) /* $ra */ 1938 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 1939 1940 nsreg = (l >> 24) & 0x7; 1941 smask = 0; 1942 if (l & 0x20) /* $s0 */ 1943 smask |= 1 << 0; 1944 if (l & 0x10) /* $s1 */ 1945 smask |= 1 << 1; 1946 if (nsreg > 0) /* $s2-$s8 */ 1947 smask |= ((1 << nsreg) - 1) << 2; 1948 1949 /* Find first set static reg bit. */ 1950 for (i = 0; i < 9; i++) 1951 { 1952 if (smask & (1 << i)) 1953 { 1954 (*info->fprintf_func) (info->stream, ",%s", 1955 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1956 /* Skip over string of set bits. */ 1957 for (j = i; smask & (2 << j); j++) 1958 continue; 1959 if (j > i) 1960 (*info->fprintf_func) (info->stream, "-%s", 1961 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1962 i = j + 1; 1963 } 1964 } 1965 1966 /* Statics $ax - $a3. */ 1967 if (statics == 1) 1968 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 1969 else if (statics > 0) 1970 (*info->fprintf_func) (info->stream, ",%s-%s", 1971 mips_gpr_names[7 - statics + 1], 1972 mips_gpr_names[7]); 1973 } 1974 break; 1975 1976 default: 1977 /* xgettext:c-format */ 1978 (*info->fprintf_func) 1979 (info->stream, 1980 _("# internal disassembler error, unrecognised modifier (%c)"), 1981 type); 1982 abort (); 1983 } 1984 } 1985 1986 /* Disassemble mips16 instructions. */ 1987 1988 static int 1989 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 1990 { 1991 int status; 1992 bfd_byte buffer[2]; 1993 int length; 1994 int insn; 1995 bfd_boolean use_extend; 1996 int extend = 0; 1997 const struct mips_opcode *op, *opend; 1998 1999 info->bytes_per_chunk = 2; 2000 info->display_endian = info->endian; 2001 info->insn_info_valid = 1; 2002 info->branch_delay_insns = 0; 2003 info->data_size = 0; 2004 info->insn_type = dis_nonbranch; 2005 info->target = 0; 2006 info->target2 = 0; 2007 2008 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2009 if (status != 0) 2010 { 2011 (*info->memory_error_func) (status, memaddr, info); 2012 return -1; 2013 } 2014 2015 length = 2; 2016 2017 if (info->endian == BFD_ENDIAN_BIG) 2018 insn = bfd_getb16 (buffer); 2019 else 2020 insn = bfd_getl16 (buffer); 2021 2022 /* Handle the extend opcode specially. */ 2023 use_extend = FALSE; 2024 if ((insn & 0xf800) == 0xf000) 2025 { 2026 use_extend = TRUE; 2027 extend = insn & 0x7ff; 2028 2029 memaddr += 2; 2030 2031 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2032 if (status != 0) 2033 { 2034 (*info->fprintf_func) (info->stream, "extend 0x%x", 2035 (unsigned int) extend); 2036 (*info->memory_error_func) (status, memaddr, info); 2037 return -1; 2038 } 2039 2040 if (info->endian == BFD_ENDIAN_BIG) 2041 insn = bfd_getb16 (buffer); 2042 else 2043 insn = bfd_getl16 (buffer); 2044 2045 /* Check for an extend opcode followed by an extend opcode. */ 2046 if ((insn & 0xf800) == 0xf000) 2047 { 2048 (*info->fprintf_func) (info->stream, "extend 0x%x", 2049 (unsigned int) extend); 2050 info->insn_type = dis_noninsn; 2051 return length; 2052 } 2053 2054 length += 2; 2055 } 2056 2057 /* FIXME: Should probably use a hash table on the major opcode here. */ 2058 2059 opend = mips16_opcodes + bfd_mips16_num_opcodes; 2060 for (op = mips16_opcodes; op < opend; op++) 2061 { 2062 if (op->pinfo != INSN_MACRO 2063 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2064 && (insn & op->mask) == op->match) 2065 { 2066 const char *s; 2067 2068 if (strchr (op->args, 'a') != NULL) 2069 { 2070 if (use_extend) 2071 { 2072 (*info->fprintf_func) (info->stream, "extend 0x%x", 2073 (unsigned int) extend); 2074 info->insn_type = dis_noninsn; 2075 return length - 2; 2076 } 2077 2078 use_extend = FALSE; 2079 2080 memaddr += 2; 2081 2082 status = (*info->read_memory_func) (memaddr, buffer, 2, 2083 info); 2084 if (status == 0) 2085 { 2086 use_extend = TRUE; 2087 if (info->endian == BFD_ENDIAN_BIG) 2088 extend = bfd_getb16 (buffer); 2089 else 2090 extend = bfd_getl16 (buffer); 2091 length += 2; 2092 } 2093 } 2094 2095 (*info->fprintf_func) (info->stream, "%s", op->name); 2096 if (op->args[0] != '\0') 2097 (*info->fprintf_func) (info->stream, "\t"); 2098 2099 for (s = op->args; *s != '\0'; s++) 2100 { 2101 if (*s == ',' 2102 && s[1] == 'w' 2103 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 2104 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 2105 { 2106 /* Skip the register and the comma. */ 2107 ++s; 2108 continue; 2109 } 2110 if (*s == ',' 2111 && s[1] == 'v' 2112 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 2113 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 2114 { 2115 /* Skip the register and the comma. */ 2116 ++s; 2117 continue; 2118 } 2119 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 2120 info); 2121 } 2122 2123 /* Figure out branch instruction type and delay slot information. */ 2124 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2125 info->branch_delay_insns = 1; 2126 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY 2127 | MIPS16_INSN_UNCOND_BRANCH)) != 0) 2128 { 2129 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2130 info->insn_type = dis_jsr; 2131 else 2132 info->insn_type = dis_branch; 2133 } 2134 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0) 2135 info->insn_type = dis_condbranch; 2136 2137 return length; 2138 } 2139 } 2140 2141 if (use_extend) 2142 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 2143 (*info->fprintf_func) (info->stream, "0x%x", insn); 2144 info->insn_type = dis_noninsn; 2145 2146 return length; 2147 } 2148 2149 /* In an environment where we do not know the symbol type of the 2150 instruction we are forced to assume that the low order bit of the 2151 instructions' address may mark it as a mips16 instruction. If we 2152 are single stepping, or the pc is within the disassembled function, 2153 this works. Otherwise, we need a clue. Sometimes. */ 2154 2155 static int 2156 _print_insn_mips (bfd_vma memaddr, 2157 struct disassemble_info *info, 2158 enum bfd_endian endianness) 2159 { 2160 bfd_byte buffer[INSNLEN]; 2161 int status; 2162 2163 set_default_mips_dis_options (info); 2164 parse_mips_dis_options (info->disassembler_options); 2165 2166 #if 1 2167 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 2168 /* Only a few tools will work this way. */ 2169 if (memaddr & 0x01) 2170 return print_insn_mips16 (memaddr, info); 2171 #endif 2172 2173 #if SYMTAB_AVAILABLE 2174 if (info->mach == bfd_mach_mips16 2175 || (info->symbols != NULL 2176 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 2177 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols) 2178 ->internal_elf_sym.st_other))) 2179 return print_insn_mips16 (memaddr, info); 2180 #endif 2181 2182 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2183 if (status == 0) 2184 { 2185 unsigned long insn; 2186 2187 if (endianness == BFD_ENDIAN_BIG) 2188 insn = (unsigned long) bfd_getb32 (buffer); 2189 else 2190 insn = (unsigned long) bfd_getl32 (buffer); 2191 2192 return print_insn_mips (memaddr, insn, info); 2193 } 2194 else 2195 { 2196 (*info->memory_error_func) (status, memaddr, info); 2197 return -1; 2198 } 2199 } 2200 2201 int 2202 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2203 { 2204 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2205 } 2206 2207 int 2208 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2209 { 2210 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2211 } 2212 2213 void 2215 print_mips_disassembler_options (FILE *stream) 2216 { 2217 unsigned int i; 2218 2219 fprintf (stream, _("\n\ 2220 The following MIPS specific disassembler options are supported for use\n\ 2221 with the -M switch (multiple options should be separated by commas):\n")); 2222 2223 fprintf (stream, _("\n\ 2224 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2225 Default: based on binary being disassembled.\n")); 2226 2227 fprintf (stream, _("\n\ 2228 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2229 Default: numeric.\n")); 2230 2231 fprintf (stream, _("\n\ 2232 cp0-names=ARCH Print CP0 register names according to\n\ 2233 specified architecture.\n\ 2234 Default: based on binary being disassembled.\n")); 2235 2236 fprintf (stream, _("\n\ 2237 hwr-names=ARCH Print HWR names according to specified \n\ 2238 architecture.\n\ 2239 Default: based on binary being disassembled.\n")); 2240 2241 fprintf (stream, _("\n\ 2242 reg-names=ABI Print GPR and FPR names according to\n\ 2243 specified ABI.\n")); 2244 2245 fprintf (stream, _("\n\ 2246 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2247 specified architecture.\n")); 2248 2249 fprintf (stream, _("\n\ 2250 For the options above, the following values are supported for \"ABI\":\n\ 2251 ")); 2252 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2253 fprintf (stream, " %s", mips_abi_choices[i].name); 2254 fprintf (stream, _("\n")); 2255 2256 fprintf (stream, _("\n\ 2257 For the options above, The following values are supported for \"ARCH\":\n\ 2258 ")); 2259 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2260 if (*mips_arch_choices[i].name != '\0') 2261 fprintf (stream, " %s", mips_arch_choices[i].name); 2262 fprintf (stream, _("\n")); 2263 2264 fprintf (stream, _("\n")); 2265 } 2266
Indexes created Mon Mar 30 00:23:01 UTC 2026