mips-dis.c revision 1.1.1.2.2.1
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include "dis-asm.h" 26 #include "libiberty.h" 27 #include "opcode/mips.h" 28 #include "opintl.h" 29 30 /* FIXME: These are needed to figure out if the code is mips16 or 31 not. The low bit of the address is often a good indicator. No 32 symbol table is available when this code runs out in an embedded 33 system as when it is used for disassembler support in a monitor. */ 34 35 #if !defined(EMBEDDED_ENV) 36 #define SYMTAB_AVAILABLE 1 37 #include "elf-bfd.h" 38 #include "elf/mips.h" 39 #endif 40 41 /* Mips instructions are at maximum this many bytes long. */ 42 #define INSNLEN 4 43 44 45 /* FIXME: These should be shared with gdb somehow. */ 47 48 struct mips_cp0sel_name 49 { 50 unsigned int cp0reg; 51 unsigned int sel; 52 const char * const name; 53 }; 54 55 static const char * const mips_gpr_names_numeric[32] = 56 { 57 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 58 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 59 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 60 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 61 }; 62 63 static const char * const mips_gpr_names_oldabi[32] = 64 { 65 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 66 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 67 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 68 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 69 }; 70 71 static const char * const mips_gpr_names_newabi[32] = 72 { 73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 74 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 77 }; 78 79 static const char * const mips_fpr_names_numeric[32] = 80 { 81 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 82 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 83 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 84 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 85 }; 86 87 static const char * const mips_fpr_names_32[32] = 88 { 89 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 90 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 91 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 92 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 93 }; 94 95 static const char * const mips_fpr_names_n32[32] = 96 { 97 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 98 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 99 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 100 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 101 }; 102 103 static const char * const mips_fpr_names_64[32] = 104 { 105 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 107 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 108 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 109 }; 110 111 static const char * const mips_cp0_names_numeric[32] = 112 { 113 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 114 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 115 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 116 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 117 }; 118 119 static const char * const mips_cp1_names_numeric[32] = 120 { 121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 125 }; 126 127 static const char * const mips_cp0_names_r3000[32] = 128 { 129 "c0_index", "c0_random", "c0_entrylo", "$3", 130 "c0_context", "$5", "$6", "$7", 131 "c0_badvaddr", "$9", "c0_entryhi", "$11", 132 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 133 "$16", "$17", "$18", "$19", 134 "$20", "$21", "$22", "$23", 135 "$24", "$25", "$26", "$27", 136 "$28", "$29", "$30", "$31", 137 }; 138 139 static const char * const mips_cp0_names_r4000[32] = 140 { 141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 142 "c0_context", "c0_pagemask", "c0_wired", "$7", 143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 144 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 146 "c0_xcontext", "$21", "$22", "$23", 147 "$24", "$25", "c0_ecc", "c0_cacheerr", 148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 149 }; 150 151 static const char * const mips_cp0_names_r5900[32] = 152 { 153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 154 "c0_context", "c0_pagemask", "c0_wired", "$7", 155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 156 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 157 "c0_config", "$17", "$18", "$19", 158 "$20", "$21", "$22", "c0_badpaddr", 159 "c0_depc", "c0_perfcnt", "$26", "$27", 160 "c0_taglo", "c0_taghi", "c0_errorepc", "$31" 161 }; 162 163 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] = 164 { 165 { 24, 2, "c0_iab" }, 166 { 24, 3, "c0_iabm" }, 167 { 24, 4, "c0_dab" }, 168 { 24, 5, "c0_dabm" }, 169 { 24, 6, "c0_dvb" }, 170 { 24, 7, "c0_dvbm" }, 171 { 25, 1, "c0_perfcnt,1" }, 172 { 25, 2, "c0_perfcnt,2" } 173 }; 174 175 static const char * const mips_cp0_names_mips3264[32] = 176 { 177 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 178 "c0_context", "c0_pagemask", "c0_wired", "$7", 179 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 180 "c0_status", "c0_cause", "c0_epc", "c0_prid", 181 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 182 "c0_xcontext", "$21", "$22", "c0_debug", 183 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 184 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 185 }; 186 187 static const char * const mips_cp1_names_mips3264[32] = 188 { 189 "c1_fir", "c1_ufr", "$2", "$3", 190 "c1_unfr", "$5", "$6", "$7", 191 "$8", "$9", "$10", "$11", 192 "$12", "$13", "$14", "$15", 193 "$16", "$17", "$18", "$19", 194 "$20", "$21", "$22", "$23", 195 "$24", "c1_fccr", "c1_fexr", "$27", 196 "c1_fenr", "$29", "$30", "c1_fcsr" 197 }; 198 199 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 200 { 201 { 16, 1, "c0_config1" }, 202 { 16, 2, "c0_config2" }, 203 { 16, 3, "c0_config3" }, 204 { 18, 1, "c0_watchlo,1" }, 205 { 18, 2, "c0_watchlo,2" }, 206 { 18, 3, "c0_watchlo,3" }, 207 { 18, 4, "c0_watchlo,4" }, 208 { 18, 5, "c0_watchlo,5" }, 209 { 18, 6, "c0_watchlo,6" }, 210 { 18, 7, "c0_watchlo,7" }, 211 { 19, 1, "c0_watchhi,1" }, 212 { 19, 2, "c0_watchhi,2" }, 213 { 19, 3, "c0_watchhi,3" }, 214 { 19, 4, "c0_watchhi,4" }, 215 { 19, 5, "c0_watchhi,5" }, 216 { 19, 6, "c0_watchhi,6" }, 217 { 19, 7, "c0_watchhi,7" }, 218 { 25, 1, "c0_perfcnt,1" }, 219 { 25, 2, "c0_perfcnt,2" }, 220 { 25, 3, "c0_perfcnt,3" }, 221 { 25, 4, "c0_perfcnt,4" }, 222 { 25, 5, "c0_perfcnt,5" }, 223 { 25, 6, "c0_perfcnt,6" }, 224 { 25, 7, "c0_perfcnt,7" }, 225 { 27, 1, "c0_cacheerr,1" }, 226 { 27, 2, "c0_cacheerr,2" }, 227 { 27, 3, "c0_cacheerr,3" }, 228 { 28, 1, "c0_datalo" }, 229 { 29, 1, "c0_datahi" } 230 }; 231 232 static const char * const mips_cp0_names_mips3264r2[32] = 233 { 234 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 235 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 236 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 237 "c0_status", "c0_cause", "c0_epc", "c0_prid", 238 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 239 "c0_xcontext", "$21", "$22", "c0_debug", 240 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 241 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 242 }; 243 244 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 245 { 246 { 4, 1, "c0_contextconfig" }, 247 { 0, 1, "c0_mvpcontrol" }, 248 { 0, 2, "c0_mvpconf0" }, 249 { 0, 3, "c0_mvpconf1" }, 250 { 1, 1, "c0_vpecontrol" }, 251 { 1, 2, "c0_vpeconf0" }, 252 { 1, 3, "c0_vpeconf1" }, 253 { 1, 4, "c0_yqmask" }, 254 { 1, 5, "c0_vpeschedule" }, 255 { 1, 6, "c0_vpeschefback" }, 256 { 2, 1, "c0_tcstatus" }, 257 { 2, 2, "c0_tcbind" }, 258 { 2, 3, "c0_tcrestart" }, 259 { 2, 4, "c0_tchalt" }, 260 { 2, 5, "c0_tccontext" }, 261 { 2, 6, "c0_tcschedule" }, 262 { 2, 7, "c0_tcschefback" }, 263 { 5, 1, "c0_pagegrain" }, 264 { 6, 1, "c0_srsconf0" }, 265 { 6, 2, "c0_srsconf1" }, 266 { 6, 3, "c0_srsconf2" }, 267 { 6, 4, "c0_srsconf3" }, 268 { 6, 5, "c0_srsconf4" }, 269 { 12, 1, "c0_intctl" }, 270 { 12, 2, "c0_srsctl" }, 271 { 12, 3, "c0_srsmap" }, 272 { 15, 1, "c0_ebase" }, 273 { 16, 1, "c0_config1" }, 274 { 16, 2, "c0_config2" }, 275 { 16, 3, "c0_config3" }, 276 { 18, 1, "c0_watchlo,1" }, 277 { 18, 2, "c0_watchlo,2" }, 278 { 18, 3, "c0_watchlo,3" }, 279 { 18, 4, "c0_watchlo,4" }, 280 { 18, 5, "c0_watchlo,5" }, 281 { 18, 6, "c0_watchlo,6" }, 282 { 18, 7, "c0_watchlo,7" }, 283 { 19, 1, "c0_watchhi,1" }, 284 { 19, 2, "c0_watchhi,2" }, 285 { 19, 3, "c0_watchhi,3" }, 286 { 19, 4, "c0_watchhi,4" }, 287 { 19, 5, "c0_watchhi,5" }, 288 { 19, 6, "c0_watchhi,6" }, 289 { 19, 7, "c0_watchhi,7" }, 290 { 23, 1, "c0_tracecontrol" }, 291 { 23, 2, "c0_tracecontrol2" }, 292 { 23, 3, "c0_usertracedata" }, 293 { 23, 4, "c0_tracebpc" }, 294 { 25, 1, "c0_perfcnt,1" }, 295 { 25, 2, "c0_perfcnt,2" }, 296 { 25, 3, "c0_perfcnt,3" }, 297 { 25, 4, "c0_perfcnt,4" }, 298 { 25, 5, "c0_perfcnt,5" }, 299 { 25, 6, "c0_perfcnt,6" }, 300 { 25, 7, "c0_perfcnt,7" }, 301 { 27, 1, "c0_cacheerr,1" }, 302 { 27, 2, "c0_cacheerr,2" }, 303 { 27, 3, "c0_cacheerr,3" }, 304 { 28, 1, "c0_datalo" }, 305 { 28, 2, "c0_taglo1" }, 306 { 28, 3, "c0_datalo1" }, 307 { 28, 4, "c0_taglo2" }, 308 { 28, 5, "c0_datalo2" }, 309 { 28, 6, "c0_taglo3" }, 310 { 28, 7, "c0_datalo3" }, 311 { 29, 1, "c0_datahi" }, 312 { 29, 2, "c0_taghi1" }, 313 { 29, 3, "c0_datahi1" }, 314 { 29, 4, "c0_taghi2" }, 315 { 29, 5, "c0_datahi2" }, 316 { 29, 6, "c0_taghi3" }, 317 { 29, 7, "c0_datahi3" }, 318 }; 319 320 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 321 static const char * const mips_cp0_names_sb1[32] = 322 { 323 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 324 "c0_context", "c0_pagemask", "c0_wired", "$7", 325 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 326 "c0_status", "c0_cause", "c0_epc", "c0_prid", 327 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 328 "c0_xcontext", "$21", "$22", "c0_debug", 329 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 330 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 331 }; 332 333 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 334 { 335 { 16, 1, "c0_config1" }, 336 { 18, 1, "c0_watchlo,1" }, 337 { 19, 1, "c0_watchhi,1" }, 338 { 22, 0, "c0_perftrace" }, 339 { 23, 3, "c0_edebug" }, 340 { 25, 1, "c0_perfcnt,1" }, 341 { 25, 2, "c0_perfcnt,2" }, 342 { 25, 3, "c0_perfcnt,3" }, 343 { 25, 4, "c0_perfcnt,4" }, 344 { 25, 5, "c0_perfcnt,5" }, 345 { 25, 6, "c0_perfcnt,6" }, 346 { 25, 7, "c0_perfcnt,7" }, 347 { 26, 1, "c0_buserr_pa" }, 348 { 27, 1, "c0_cacheerr_d" }, 349 { 27, 3, "c0_cacheerr_d_pa" }, 350 { 28, 1, "c0_datalo_i" }, 351 { 28, 2, "c0_taglo_d" }, 352 { 28, 3, "c0_datalo_d" }, 353 { 29, 1, "c0_datahi_i" }, 354 { 29, 2, "c0_taghi_d" }, 355 { 29, 3, "c0_datahi_d" }, 356 }; 357 358 /* Xlr cop0 register names. */ 359 static const char * const mips_cp0_names_xlr[32] = { 360 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 361 "c0_context", "c0_pagemask", "c0_wired", "$7", 362 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 363 "c0_status", "c0_cause", "c0_epc", "c0_prid", 364 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 365 "c0_xcontext", "$21", "$22", "c0_debug", 366 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 367 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 368 }; 369 370 /* XLR's CP0 Select Registers. */ 371 372 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 373 { 9, 6, "c0_extintreq" }, 374 { 9, 7, "c0_extintmask" }, 375 { 15, 1, "c0_ebase" }, 376 { 16, 1, "c0_config1" }, 377 { 16, 2, "c0_config2" }, 378 { 16, 3, "c0_config3" }, 379 { 16, 7, "c0_procid2" }, 380 { 18, 1, "c0_watchlo,1" }, 381 { 18, 2, "c0_watchlo,2" }, 382 { 18, 3, "c0_watchlo,3" }, 383 { 18, 4, "c0_watchlo,4" }, 384 { 18, 5, "c0_watchlo,5" }, 385 { 18, 6, "c0_watchlo,6" }, 386 { 18, 7, "c0_watchlo,7" }, 387 { 19, 1, "c0_watchhi,1" }, 388 { 19, 2, "c0_watchhi,2" }, 389 { 19, 3, "c0_watchhi,3" }, 390 { 19, 4, "c0_watchhi,4" }, 391 { 19, 5, "c0_watchhi,5" }, 392 { 19, 6, "c0_watchhi,6" }, 393 { 19, 7, "c0_watchhi,7" }, 394 { 25, 1, "c0_perfcnt,1" }, 395 { 25, 2, "c0_perfcnt,2" }, 396 { 25, 3, "c0_perfcnt,3" }, 397 { 25, 4, "c0_perfcnt,4" }, 398 { 25, 5, "c0_perfcnt,5" }, 399 { 25, 6, "c0_perfcnt,6" }, 400 { 25, 7, "c0_perfcnt,7" }, 401 { 27, 1, "c0_cacheerr,1" }, 402 { 27, 2, "c0_cacheerr,2" }, 403 { 27, 3, "c0_cacheerr,3" }, 404 { 28, 1, "c0_datalo" }, 405 { 29, 1, "c0_datahi" } 406 }; 407 408 static const char * const mips_hwr_names_numeric[32] = 409 { 410 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 411 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 412 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 413 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 414 }; 415 416 static const char * const mips_hwr_names_mips3264r2[32] = 417 { 418 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 419 "$4", "$5", "$6", "$7", 420 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 421 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 422 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 423 }; 424 425 static const char * const msa_control_names[32] = 426 { 427 "msa_ir", "msa_csr", "msa_access", "msa_save", 428 "msa_modify", "msa_request", "msa_map", "msa_unmap", 429 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 430 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 431 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 432 }; 433 434 struct mips_abi_choice 435 { 436 const char * name; 437 const char * const *gpr_names; 438 const char * const *fpr_names; 439 }; 440 441 struct mips_abi_choice mips_abi_choices[] = 442 { 443 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 444 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 445 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 446 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 447 }; 448 449 struct mips_arch_choice 450 { 451 const char *name; 452 int bfd_mach_valid; 453 unsigned long bfd_mach; 454 int processor; 455 int isa; 456 int ase; 457 const char * const *cp0_names; 458 const struct mips_cp0sel_name *cp0sel_names; 459 unsigned int cp0sel_names_len; 460 const char * const *cp1_names; 461 const char * const *hwr_names; 462 }; 463 464 const struct mips_arch_choice mips_arch_choices[] = 465 { 466 { "numeric", 0, 0, 0, 0, 0, 467 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 468 mips_hwr_names_numeric }, 469 470 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, 471 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, 472 mips_hwr_names_numeric }, 473 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, 474 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 475 mips_hwr_names_numeric }, 476 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, 477 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 478 mips_hwr_names_numeric }, 479 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, 480 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 481 mips_hwr_names_numeric }, 482 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, 483 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 484 mips_hwr_names_numeric }, 485 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, 486 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 487 mips_hwr_names_numeric }, 488 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, 489 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 490 mips_hwr_names_numeric }, 491 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, 492 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 493 mips_hwr_names_numeric }, 494 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, 495 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 496 mips_hwr_names_numeric }, 497 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, 498 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 499 mips_hwr_names_numeric }, 500 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, 501 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 502 mips_hwr_names_numeric }, 503 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, 504 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 505 mips_hwr_names_numeric }, 506 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, 507 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 508 mips_hwr_names_numeric }, 509 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, 510 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 511 mips_hwr_names_numeric }, 512 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, 513 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, 514 mips_hwr_names_numeric }, 515 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, 516 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 517 mips_hwr_names_numeric }, 518 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 519 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 520 mips_hwr_names_numeric }, 521 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 522 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 523 mips_hwr_names_numeric }, 524 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, 525 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 526 mips_hwr_names_numeric }, 527 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, 528 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 529 mips_hwr_names_numeric }, 530 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, 531 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 532 mips_hwr_names_numeric }, 533 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, 534 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 535 mips_hwr_names_numeric }, 536 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, 537 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 538 mips_hwr_names_numeric }, 539 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, 540 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 541 mips_hwr_names_numeric }, 542 543 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 544 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 545 _MIPS32 Architecture For Programmers Volume I: Introduction to the 546 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 547 page 1. */ 548 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 549 ISA_MIPS32, ASE_SMARTMIPS, 550 mips_cp0_names_mips3264, 551 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 552 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 553 554 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 555 ISA_MIPS32R2, 556 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 557 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA), 558 mips_cp0_names_mips3264r2, 559 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 560 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 561 562 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 563 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 564 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX, 565 mips_cp0_names_mips3264, 566 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 567 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 568 569 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 570 ISA_MIPS64R2, 571 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 572 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64), 573 mips_cp0_names_mips3264r2, 574 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 575 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 576 577 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 578 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, 579 mips_cp0_names_sb1, 580 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 581 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 582 583 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 584 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, 585 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 586 587 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 588 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, 589 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 590 591 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 592 ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, 593 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 594 595 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 596 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, 597 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 598 599 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, 600 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, 601 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 602 603 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, 604 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, 605 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 606 607 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 608 ISA_MIPS64 | INSN_XLR, 0, 609 mips_cp0_names_xlr, 610 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 611 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 612 613 /* XLP is mostly like XLR, with the prominent exception it is being 614 MIPS64R2. */ 615 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, 616 ISA_MIPS64R2 | INSN_XLR, 0, 617 mips_cp0_names_xlr, 618 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 619 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 620 621 /* This entry, mips16, is here only for ISA/processor selection; do 622 not print its name. */ 623 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, 624 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 625 mips_hwr_names_numeric }, 626 }; 627 628 /* ISA and processor type to disassemble for, and register names to use. 629 set_default_mips_dis_options and parse_mips_dis_options fill in these 630 values. */ 631 static int mips_processor; 632 static int mips_isa; 633 static int mips_ase; 634 static int micromips_ase; 635 static const char * const *mips_gpr_names; 636 static const char * const *mips_fpr_names; 637 static const char * const *mips_cp0_names; 638 static const struct mips_cp0sel_name *mips_cp0sel_names; 639 static int mips_cp0sel_names_len; 640 static const char * const *mips_cp1_names; 641 static const char * const *mips_hwr_names; 642 643 /* Other options */ 644 static int no_aliases; /* If set disassemble as most general inst. */ 645 646 static const struct mips_abi_choice * 648 choose_abi_by_name (const char *name, unsigned int namelen) 649 { 650 const struct mips_abi_choice *c; 651 unsigned int i; 652 653 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 654 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 655 && strlen (mips_abi_choices[i].name) == namelen) 656 c = &mips_abi_choices[i]; 657 658 return c; 659 } 660 661 static const struct mips_arch_choice * 662 choose_arch_by_name (const char *name, unsigned int namelen) 663 { 664 const struct mips_arch_choice *c = NULL; 665 unsigned int i; 666 667 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 668 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 669 && strlen (mips_arch_choices[i].name) == namelen) 670 c = &mips_arch_choices[i]; 671 672 return c; 673 } 674 675 static const struct mips_arch_choice * 676 choose_arch_by_number (unsigned long mach) 677 { 678 static unsigned long hint_bfd_mach; 679 static const struct mips_arch_choice *hint_arch_choice; 680 const struct mips_arch_choice *c; 681 unsigned int i; 682 683 /* We optimize this because even if the user specifies no 684 flags, this will be done for every instruction! */ 685 if (hint_bfd_mach == mach 686 && hint_arch_choice != NULL 687 && hint_arch_choice->bfd_mach == hint_bfd_mach) 688 return hint_arch_choice; 689 690 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 691 { 692 if (mips_arch_choices[i].bfd_mach_valid 693 && mips_arch_choices[i].bfd_mach == mach) 694 { 695 c = &mips_arch_choices[i]; 696 hint_bfd_mach = mach; 697 hint_arch_choice = c; 698 } 699 } 700 return c; 701 } 702 703 /* Check if the object uses NewABI conventions. */ 704 705 static int 706 is_newabi (Elf_Internal_Ehdr *header) 707 { 708 /* There are no old-style ABIs which use 64-bit ELF. */ 709 if (header->e_ident[EI_CLASS] == ELFCLASS64) 710 return 1; 711 712 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 713 if ((header->e_flags & EF_MIPS_ABI2) != 0) 714 return 1; 715 716 return 0; 717 } 718 719 /* Check if the object has microMIPS ASE code. */ 720 721 static int 722 is_micromips (Elf_Internal_Ehdr *header) 723 { 724 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) 725 return 1; 726 727 return 0; 728 } 729 730 static void 731 set_default_mips_dis_options (struct disassemble_info *info) 732 { 733 const struct mips_arch_choice *chosen_arch; 734 735 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code 736 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR, 737 CP0 register, and HWR names. */ 738 mips_isa = ISA_MIPS3; 739 mips_processor = CPU_R3000; 740 micromips_ase = 0; 741 mips_ase = 0; 742 mips_gpr_names = mips_gpr_names_oldabi; 743 mips_fpr_names = mips_fpr_names_numeric; 744 mips_cp0_names = mips_cp0_names_numeric; 745 mips_cp0sel_names = NULL; 746 mips_cp0sel_names_len = 0; 747 mips_cp1_names = mips_cp1_names_numeric; 748 mips_hwr_names = mips_hwr_names_numeric; 749 no_aliases = 0; 750 751 /* Update settings according to the ELF file header flags. */ 752 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 753 { 754 Elf_Internal_Ehdr *header; 755 756 header = elf_elfheader (info->section->owner); 757 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 758 if (is_newabi (header)) 759 mips_gpr_names = mips_gpr_names_newabi; 760 /* If a microMIPS binary, then don't use MIPS16 bindings. */ 761 micromips_ase = is_micromips (header); 762 } 763 764 /* Set ISA, architecture, and cp0 register names as best we can. */ 765 #if ! SYMTAB_AVAILABLE 766 /* This is running out on a target machine, not in a host tool. 767 FIXME: Where does mips_target_info come from? */ 768 target_processor = mips_target_info.processor; 769 mips_isa = mips_target_info.isa; 770 mips_ase = mips_target_info.ase; 771 #else 772 chosen_arch = choose_arch_by_number (info->mach); 773 if (chosen_arch != NULL) 774 { 775 mips_processor = chosen_arch->processor; 776 mips_isa = chosen_arch->isa; 777 mips_ase = chosen_arch->ase; 778 mips_cp0_names = chosen_arch->cp0_names; 779 mips_cp0sel_names = chosen_arch->cp0sel_names; 780 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 781 mips_cp1_names = chosen_arch->cp1_names; 782 mips_hwr_names = chosen_arch->hwr_names; 783 } 784 #endif 785 } 786 787 static void 788 parse_mips_dis_option (const char *option, unsigned int len) 789 { 790 unsigned int i, optionlen, vallen; 791 const char *val; 792 const struct mips_abi_choice *chosen_abi; 793 const struct mips_arch_choice *chosen_arch; 794 795 /* Try to match options that are simple flags */ 796 if (CONST_STRNEQ (option, "no-aliases")) 797 { 798 no_aliases = 1; 799 return; 800 } 801 802 if (CONST_STRNEQ (option, "msa")) 803 { 804 mips_ase |= ASE_MSA; 805 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2) 806 mips_ase |= ASE_MSA64; 807 return; 808 } 809 810 if (CONST_STRNEQ (option, "virt")) 811 { 812 mips_ase |= ASE_VIRT; 813 if (mips_isa & ISA_MIPS64R2) 814 mips_ase |= ASE_VIRT64; 815 return; 816 } 817 818 /* Look for the = that delimits the end of the option name. */ 819 for (i = 0; i < len; i++) 820 if (option[i] == '=') 821 break; 822 823 if (i == 0) /* Invalid option: no name before '='. */ 824 return; 825 if (i == len) /* Invalid option: no '='. */ 826 return; 827 if (i == (len - 1)) /* Invalid option: no value after '='. */ 828 return; 829 830 optionlen = i; 831 val = option + (optionlen + 1); 832 vallen = len - (optionlen + 1); 833 834 if (strncmp ("gpr-names", option, optionlen) == 0 835 && strlen ("gpr-names") == optionlen) 836 { 837 chosen_abi = choose_abi_by_name (val, vallen); 838 if (chosen_abi != NULL) 839 mips_gpr_names = chosen_abi->gpr_names; 840 return; 841 } 842 843 if (strncmp ("fpr-names", option, optionlen) == 0 844 && strlen ("fpr-names") == optionlen) 845 { 846 chosen_abi = choose_abi_by_name (val, vallen); 847 if (chosen_abi != NULL) 848 mips_fpr_names = chosen_abi->fpr_names; 849 return; 850 } 851 852 if (strncmp ("cp0-names", option, optionlen) == 0 853 && strlen ("cp0-names") == optionlen) 854 { 855 chosen_arch = choose_arch_by_name (val, vallen); 856 if (chosen_arch != NULL) 857 { 858 mips_cp0_names = chosen_arch->cp0_names; 859 mips_cp0sel_names = chosen_arch->cp0sel_names; 860 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 861 } 862 return; 863 } 864 865 if (strncmp ("cp1-names", option, optionlen) == 0 866 && strlen ("cp1-names") == optionlen) 867 { 868 chosen_arch = choose_arch_by_name (val, vallen); 869 if (chosen_arch != NULL) 870 mips_cp1_names = chosen_arch->cp1_names; 871 return; 872 } 873 874 if (strncmp ("hwr-names", option, optionlen) == 0 875 && strlen ("hwr-names") == optionlen) 876 { 877 chosen_arch = choose_arch_by_name (val, vallen); 878 if (chosen_arch != NULL) 879 mips_hwr_names = chosen_arch->hwr_names; 880 return; 881 } 882 883 if (strncmp ("reg-names", option, optionlen) == 0 884 && strlen ("reg-names") == optionlen) 885 { 886 /* We check both ABI and ARCH here unconditionally, so 887 that "numeric" will do the desirable thing: select 888 numeric register names for all registers. Other than 889 that, a given name probably won't match both. */ 890 chosen_abi = choose_abi_by_name (val, vallen); 891 if (chosen_abi != NULL) 892 { 893 mips_gpr_names = chosen_abi->gpr_names; 894 mips_fpr_names = chosen_abi->fpr_names; 895 } 896 chosen_arch = choose_arch_by_name (val, vallen); 897 if (chosen_arch != NULL) 898 { 899 mips_cp0_names = chosen_arch->cp0_names; 900 mips_cp0sel_names = chosen_arch->cp0sel_names; 901 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 902 mips_cp1_names = chosen_arch->cp1_names; 903 mips_hwr_names = chosen_arch->hwr_names; 904 } 905 return; 906 } 907 908 /* Invalid option. */ 909 } 910 911 static void 912 parse_mips_dis_options (const char *options) 913 { 914 const char *option_end; 915 916 if (options == NULL) 917 return; 918 919 while (*options != '\0') 920 { 921 /* Skip empty options. */ 922 if (*options == ',') 923 { 924 options++; 925 continue; 926 } 927 928 /* We know that *options is neither NUL or a comma. */ 929 option_end = options + 1; 930 while (*option_end != ',' && *option_end != '\0') 931 option_end++; 932 933 parse_mips_dis_option (options, option_end - options); 934 935 /* Go on to the next one. If option_end points to a comma, it 936 will be skipped above. */ 937 options = option_end; 938 } 939 } 940 941 static const struct mips_cp0sel_name * 942 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 943 unsigned int len, 944 unsigned int cp0reg, 945 unsigned int sel) 946 { 947 unsigned int i; 948 949 for (i = 0; i < len; i++) 950 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 951 return &names[i]; 952 return NULL; 953 } 954 955 /* Print register REGNO, of type TYPE, for instruction OPCODE. */ 956 957 static void 958 print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, 959 enum mips_reg_operand_type type, int regno) 960 { 961 switch (type) 962 { 963 case OP_REG_GP: 964 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]); 965 break; 966 967 case OP_REG_FP: 968 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]); 969 break; 970 971 case OP_REG_CCC: 972 if (opcode->pinfo & (FP_D | FP_S)) 973 info->fprintf_func (info->stream, "$fcc%d", regno); 974 else 975 info->fprintf_func (info->stream, "$cc%d", regno); 976 break; 977 978 case OP_REG_VEC: 979 if (opcode->membership & INSN_5400) 980 info->fprintf_func (info->stream, "$f%d", regno); 981 else 982 info->fprintf_func (info->stream, "$v%d", regno); 983 break; 984 985 case OP_REG_ACC: 986 info->fprintf_func (info->stream, "$ac%d", regno); 987 break; 988 989 case OP_REG_COPRO: 990 if (opcode->name[strlen (opcode->name) - 1] == '0') 991 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); 992 else if (opcode->name[strlen (opcode->name) - 1] == '1') 993 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); 994 else 995 info->fprintf_func (info->stream, "$%d", regno); 996 break; 997 998 case OP_REG_HW: 999 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]); 1000 break; 1001 1002 case OP_REG_VF: 1003 info->fprintf_func (info->stream, "$vf%d", regno); 1004 break; 1005 1006 case OP_REG_VI: 1007 info->fprintf_func (info->stream, "$vi%d", regno); 1008 break; 1009 1010 case OP_REG_R5900_I: 1011 info->fprintf_func (info->stream, "$I"); 1012 break; 1013 1014 case OP_REG_R5900_Q: 1015 info->fprintf_func (info->stream, "$Q"); 1016 break; 1017 1018 case OP_REG_R5900_R: 1019 info->fprintf_func (info->stream, "$R"); 1020 break; 1021 1022 case OP_REG_R5900_ACC: 1023 info->fprintf_func (info->stream, "$ACC"); 1024 break; 1025 1026 case OP_REG_MSA: 1027 info->fprintf_func (info->stream, "$w%d", regno); 1028 break; 1029 1030 case OP_REG_MSA_CTRL: 1031 info->fprintf_func (info->stream, "%s", msa_control_names[regno]); 1032 break; 1033 1034 } 1035 } 1036 1037 /* Used to track the state carried over from previous operands in 1039 an instruction. */ 1040 struct mips_print_arg_state { 1041 /* The value of the last OP_INT seen. We only use this for OP_MSB, 1042 where the value is known to be unsigned and small. */ 1043 unsigned int last_int; 1044 1045 /* The type and number of the last OP_REG seen. We only use this for 1046 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ 1047 enum mips_reg_operand_type last_reg_type; 1048 unsigned int last_regno; 1049 }; 1050 1051 /* Initialize STATE for the start of an instruction. */ 1052 1053 static inline void 1054 init_print_arg_state (struct mips_print_arg_state *state) 1055 { 1056 memset (state, 0, sizeof (*state)); 1057 } 1058 1059 /* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND, 1060 whose value is given by UVAL. */ 1061 1062 static void 1063 print_vu0_channel (struct disassemble_info *info, 1064 const struct mips_operand *operand, unsigned int uval) 1065 { 1066 if (operand->size == 4) 1067 info->fprintf_func (info->stream, "%s%s%s%s", 1068 uval & 8 ? "x" : "", 1069 uval & 4 ? "y" : "", 1070 uval & 2 ? "z" : "", 1071 uval & 1 ? "w" : ""); 1072 else if (operand->size == 2) 1073 info->fprintf_func (info->stream, "%c", "xyzw"[uval]); 1074 else 1075 abort (); 1076 } 1077 1078 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. 1079 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is 1080 the base address for OP_PCREL operands. */ 1081 1082 static void 1083 print_insn_arg (struct disassemble_info *info, 1084 struct mips_print_arg_state *state, 1085 const struct mips_opcode *opcode, 1086 const struct mips_operand *operand, 1087 bfd_vma base_pc, 1088 unsigned int uval) 1089 { 1090 const fprintf_ftype infprintf = info->fprintf_func; 1091 void *is = info->stream; 1092 1093 switch (operand->type) 1094 { 1095 case OP_INT: 1096 { 1097 const struct mips_int_operand *int_op; 1098 1099 int_op = (const struct mips_int_operand *) operand; 1100 uval = mips_decode_int_operand (int_op, uval); 1101 state->last_int = uval; 1102 if (int_op->print_hex) 1103 infprintf (is, "0x%x", uval); 1104 else 1105 infprintf (is, "%d", uval); 1106 } 1107 break; 1108 1109 case OP_MAPPED_INT: 1110 { 1111 const struct mips_mapped_int_operand *mint_op; 1112 1113 mint_op = (const struct mips_mapped_int_operand *) operand; 1114 uval = mint_op->int_map[uval]; 1115 state->last_int = uval; 1116 if (mint_op->print_hex) 1117 infprintf (is, "0x%x", uval); 1118 else 1119 infprintf (is, "%d", uval); 1120 } 1121 break; 1122 1123 case OP_MSB: 1124 { 1125 const struct mips_msb_operand *msb_op; 1126 1127 msb_op = (const struct mips_msb_operand *) operand; 1128 uval += msb_op->bias; 1129 if (msb_op->add_lsb) 1130 uval -= state->last_int; 1131 infprintf (is, "0x%x", uval); 1132 } 1133 break; 1134 1135 case OP_REG: 1136 case OP_OPTIONAL_REG: 1137 { 1138 const struct mips_reg_operand *reg_op; 1139 1140 reg_op = (const struct mips_reg_operand *) operand; 1141 uval = mips_decode_reg_operand (reg_op, uval); 1142 print_reg (info, opcode, reg_op->reg_type, uval); 1143 1144 state->last_reg_type = reg_op->reg_type; 1145 state->last_regno = uval; 1146 } 1147 break; 1148 1149 case OP_REG_PAIR: 1150 { 1151 const struct mips_reg_pair_operand *pair_op; 1152 1153 pair_op = (const struct mips_reg_pair_operand *) operand; 1154 print_reg (info, opcode, pair_op->reg_type, 1155 pair_op->reg1_map[uval]); 1156 infprintf (is, ","); 1157 print_reg (info, opcode, pair_op->reg_type, 1158 pair_op->reg2_map[uval]); 1159 } 1160 break; 1161 1162 case OP_PCREL: 1163 { 1164 const struct mips_pcrel_operand *pcrel_op; 1165 1166 pcrel_op = (const struct mips_pcrel_operand *) operand; 1167 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); 1168 1169 /* Preserve the ISA bit for the GDB disassembler, 1170 otherwise clear it. */ 1171 if (info->flavour != bfd_target_unknown_flavour) 1172 info->target &= -2; 1173 1174 (*info->print_address_func) (info->target, info); 1175 } 1176 break; 1177 1178 case OP_PERF_REG: 1179 infprintf (is, "%d", uval); 1180 break; 1181 1182 case OP_ADDIUSP_INT: 1183 { 1184 int sval; 1185 1186 sval = mips_signed_operand (operand, uval) * 4; 1187 if (sval >= -8 && sval < 8) 1188 sval ^= 0x400; 1189 infprintf (is, "%d", sval); 1190 break; 1191 } 1192 1193 case OP_CLO_CLZ_DEST: 1194 { 1195 unsigned int reg1, reg2; 1196 1197 reg1 = uval & 31; 1198 reg2 = uval >> 5; 1199 /* If one is zero use the other. */ 1200 if (reg1 == reg2 || reg2 == 0) 1201 infprintf (is, "%s", mips_gpr_names[reg1]); 1202 else if (reg1 == 0) 1203 infprintf (is, "%s", mips_gpr_names[reg2]); 1204 else 1205 /* Bogus, result depends on processor. */ 1206 infprintf (is, "%s or %s", mips_gpr_names[reg1], 1207 mips_gpr_names[reg2]); 1208 } 1209 break; 1210 1211 case OP_LWM_SWM_LIST: 1212 if (operand->size == 2) 1213 { 1214 if (uval == 0) 1215 infprintf (is, "%s,%s", 1216 mips_gpr_names[16], 1217 mips_gpr_names[31]); 1218 else 1219 infprintf (is, "%s-%s,%s", 1220 mips_gpr_names[16], 1221 mips_gpr_names[16 + uval], 1222 mips_gpr_names[31]); 1223 } 1224 else 1225 { 1226 int s_reg_encode; 1227 1228 s_reg_encode = uval & 0xf; 1229 if (s_reg_encode != 0) 1230 { 1231 if (s_reg_encode == 1) 1232 infprintf (is, "%s", mips_gpr_names[16]); 1233 else if (s_reg_encode < 9) 1234 infprintf (is, "%s-%s", 1235 mips_gpr_names[16], 1236 mips_gpr_names[15 + s_reg_encode]); 1237 else if (s_reg_encode == 9) 1238 infprintf (is, "%s-%s,%s", 1239 mips_gpr_names[16], 1240 mips_gpr_names[23], 1241 mips_gpr_names[30]); 1242 else 1243 infprintf (is, "UNKNOWN"); 1244 } 1245 1246 if (uval & 0x10) /* For ra. */ 1247 { 1248 if (s_reg_encode == 0) 1249 infprintf (is, "%s", mips_gpr_names[31]); 1250 else 1251 infprintf (is, ",%s", mips_gpr_names[31]); 1252 } 1253 } 1254 break; 1255 1256 case OP_ENTRY_EXIT_LIST: 1257 { 1258 const char *sep; 1259 unsigned int amask, smask; 1260 1261 sep = ""; 1262 amask = (uval >> 3) & 7; 1263 if (amask > 0 && amask < 5) 1264 { 1265 infprintf (is, "%s", mips_gpr_names[4]); 1266 if (amask > 1) 1267 infprintf (is, "-%s", mips_gpr_names[amask + 3]); 1268 sep = ","; 1269 } 1270 1271 smask = (uval >> 1) & 3; 1272 if (smask == 3) 1273 { 1274 infprintf (is, "%s??", sep); 1275 sep = ","; 1276 } 1277 else if (smask > 0) 1278 { 1279 infprintf (is, "%s%s", sep, mips_gpr_names[16]); 1280 if (smask > 1) 1281 infprintf (is, "-%s", mips_gpr_names[smask + 15]); 1282 sep = ","; 1283 } 1284 1285 if (uval & 1) 1286 { 1287 infprintf (is, "%s%s", sep, mips_gpr_names[31]); 1288 sep = ","; 1289 } 1290 1291 if (amask == 5 || amask == 6) 1292 { 1293 infprintf (is, "%s%s", sep, mips_fpr_names[0]); 1294 if (amask == 6) 1295 infprintf (is, "-%s", mips_fpr_names[1]); 1296 } 1297 } 1298 break; 1299 1300 case OP_SAVE_RESTORE_LIST: 1301 /* Should be handled by the caller due to extend behavior. */ 1302 abort (); 1303 1304 case OP_MDMX_IMM_REG: 1305 { 1306 unsigned int vsel; 1307 1308 vsel = uval >> 5; 1309 uval &= 31; 1310 if ((vsel & 0x10) == 0) 1311 { 1312 int fmt; 1313 1314 vsel &= 0x0f; 1315 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1316 if ((vsel & 1) == 0) 1317 break; 1318 print_reg (info, opcode, OP_REG_VEC, uval); 1319 infprintf (is, "[%d]", vsel >> 1); 1320 } 1321 else if ((vsel & 0x08) == 0) 1322 print_reg (info, opcode, OP_REG_VEC, uval); 1323 else 1324 infprintf (is, "0x%x", uval); 1325 } 1326 break; 1327 1328 case OP_REPEAT_PREV_REG: 1329 print_reg (info, opcode, state->last_reg_type, state->last_regno); 1330 break; 1331 1332 case OP_REPEAT_DEST_REG: 1333 /* Should always match OP_REPEAT_PREV_REG first. */ 1334 abort (); 1335 1336 case OP_PC: 1337 infprintf (is, "$pc"); 1338 break; 1339 1340 case OP_VU0_SUFFIX: 1341 case OP_VU0_MATCH_SUFFIX: 1342 print_vu0_channel (info, operand, uval); 1343 break; 1344 1345 case OP_IMM_INDEX: 1346 infprintf (is, "[%d]", uval); 1347 break; 1348 1349 case OP_REG_INDEX: 1350 infprintf (is, "["); 1351 print_reg (info, opcode, OP_REG_GP, uval); 1352 infprintf (is, "]"); 1353 break; 1354 } 1355 } 1356 1357 /* Print the arguments for INSN, which is described by OPCODE. 1358 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC 1359 as the base of OP_PCREL operands. */ 1360 1361 static void 1362 print_insn_args (struct disassemble_info *info, 1363 const struct mips_opcode *opcode, 1364 const struct mips_operand *(*decode_operand) (const char *), 1365 unsigned int insn, bfd_vma base_pc) 1366 { 1367 const fprintf_ftype infprintf = info->fprintf_func; 1368 void *is = info->stream; 1369 struct mips_print_arg_state state; 1370 const struct mips_operand *operand; 1371 const char *s; 1372 1373 init_print_arg_state (&state); 1374 for (s = opcode->args; *s; ++s) 1375 { 1376 switch (*s) 1377 { 1378 case ',': 1379 case '(': 1380 case ')': 1381 infprintf (is, "%c", *s); 1382 break; 1383 1384 case '#': 1385 ++s; 1386 infprintf (is, "%c%c", *s, *s); 1387 break; 1388 1389 default: 1390 operand = decode_operand (s); 1391 if (!operand) 1392 { 1393 /* xgettext:c-format */ 1394 infprintf (is, 1395 _("# internal error, undefined operand in `%s %s'"), 1396 opcode->name, opcode->args); 1397 return; 1398 } 1399 if (operand->type == OP_REG 1400 && s[1] == ',' 1401 && s[2] == 'H' 1402 && opcode->name[strlen (opcode->name) - 1] == '0') 1403 { 1404 /* Coprocessor register 0 with sel field (MT ASE). */ 1405 const struct mips_cp0sel_name *n; 1406 unsigned int reg, sel; 1407 1408 reg = mips_extract_operand (operand, insn); 1409 s += 2; 1410 operand = decode_operand (s); 1411 sel = mips_extract_operand (operand, insn); 1412 1413 /* CP0 register including 'sel' code for mftc0, to be 1414 printed textually if known. If not known, print both 1415 CP0 register name and sel numerically since CP0 register 1416 with sel 0 may have a name unrelated to register being 1417 printed. */ 1418 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 1419 mips_cp0sel_names_len, 1420 reg, sel); 1421 if (n != NULL) 1422 infprintf (is, "%s", n->name); 1423 else 1424 infprintf (is, "$%d,%d", reg, sel); 1425 } 1426 else 1427 print_insn_arg (info, &state, opcode, operand, base_pc, 1428 mips_extract_operand (operand, insn)); 1429 if (*s == 'm' || *s == '+') 1430 ++s; 1431 break; 1432 } 1433 } 1434 } 1435 1436 /* Print the mips instruction at address MEMADDR in debugged memory, 1438 on using INFO. Returns length of the instruction, in bytes, which is 1439 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1440 this is little-endian code. */ 1441 1442 static int 1443 print_insn_mips (bfd_vma memaddr, 1444 int word, 1445 struct disassemble_info *info) 1446 { 1447 #define GET_OP(insn, field) \ 1448 (((insn) >> OP_SH_##field) & OP_MASK_##field) 1449 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1450 const fprintf_ftype infprintf = info->fprintf_func; 1451 const struct mips_opcode *op; 1452 static bfd_boolean init = 0; 1453 void *is = info->stream; 1454 1455 /* Build a hash table to shorten the search time. */ 1456 if (! init) 1457 { 1458 unsigned int i; 1459 1460 for (i = 0; i <= OP_MASK_OP; i++) 1461 { 1462 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1463 { 1464 if (op->pinfo == INSN_MACRO 1465 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1466 continue; 1467 if (i == GET_OP (op->match, OP)) 1468 { 1469 mips_hash[i] = op; 1470 break; 1471 } 1472 } 1473 } 1474 1475 init = 1; 1476 } 1477 1478 info->bytes_per_chunk = INSNLEN; 1479 info->display_endian = info->endian; 1480 info->insn_info_valid = 1; 1481 info->branch_delay_insns = 0; 1482 info->data_size = 0; 1483 info->insn_type = dis_nonbranch; 1484 info->target = 0; 1485 info->target2 = 0; 1486 1487 op = mips_hash[GET_OP (word, OP)]; 1488 if (op != NULL) 1489 { 1490 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1491 { 1492 if (op->pinfo != INSN_MACRO 1493 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1494 && (word & op->mask) == op->match) 1495 { 1496 /* We always allow to disassemble the jalx instruction. */ 1497 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) 1498 && strcmp (op->name, "jalx")) 1499 continue; 1500 1501 /* Figure out instruction type and branch delay information. */ 1502 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1503 { 1504 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 1505 info->insn_type = dis_jsr; 1506 else 1507 info->insn_type = dis_branch; 1508 info->branch_delay_insns = 1; 1509 } 1510 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1511 | INSN_COND_BRANCH_LIKELY)) != 0) 1512 { 1513 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1514 info->insn_type = dis_condjsr; 1515 else 1516 info->insn_type = dis_condbranch; 1517 info->branch_delay_insns = 1; 1518 } 1519 else if ((op->pinfo & (INSN_STORE_MEMORY 1520 | INSN_LOAD_MEMORY)) != 0) 1521 info->insn_type = dis_dref; 1522 1523 infprintf (is, "%s", op->name); 1524 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 1525 { 1526 unsigned int uval; 1527 1528 infprintf (is, "."); 1529 uval = mips_extract_operand (&mips_vu0_channel_mask, word); 1530 print_vu0_channel (info, &mips_vu0_channel_mask, uval); 1531 } 1532 1533 if (op->args[0]) 1534 { 1535 infprintf (is, "\t"); 1536 print_insn_args (info, op, decode_mips_operand, word, 1537 memaddr + 4); 1538 } 1539 1540 return INSNLEN; 1541 } 1542 } 1543 } 1544 #undef GET_OP 1545 1546 /* Handle undefined instructions. */ 1547 info->insn_type = dis_noninsn; 1548 infprintf (is, "0x%x", word); 1549 return INSNLEN; 1550 } 1551 1552 /* Disassemble an operand for a mips16 instruction. */ 1554 1555 static void 1556 print_mips16_insn_arg (struct disassemble_info *info, 1557 struct mips_print_arg_state *state, 1558 const struct mips_opcode *opcode, 1559 char type, bfd_vma memaddr, 1560 unsigned insn, bfd_boolean use_extend, 1561 unsigned extend, bfd_boolean is_offset) 1562 { 1563 const fprintf_ftype infprintf = info->fprintf_func; 1564 void *is = info->stream; 1565 const struct mips_operand *operand, *ext_operand; 1566 unsigned int uval; 1567 bfd_vma baseaddr; 1568 1569 if (!use_extend) 1570 extend = 0; 1571 1572 switch (type) 1573 { 1574 case ',': 1575 case '(': 1576 case ')': 1577 infprintf (is, "%c", type); 1578 break; 1579 1580 default: 1581 operand = decode_mips16_operand (type, FALSE); 1582 if (!operand) 1583 { 1584 /* xgettext:c-format */ 1585 infprintf (is, _("# internal error, undefined operand in `%s %s'"), 1586 opcode->name, opcode->args); 1587 return; 1588 } 1589 1590 if (operand->type == OP_SAVE_RESTORE_LIST) 1591 { 1592 /* Handle this case here because of the complex interation 1593 with the EXTEND opcode. */ 1594 unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j; 1595 const char *sep; 1596 1597 amask = extend & 0xf; 1598 if (amask == MIPS16_ALL_ARGS) 1599 { 1600 nargs = 4; 1601 nstatics = 0; 1602 } 1603 else if (amask == MIPS16_ALL_STATICS) 1604 { 1605 nargs = 0; 1606 nstatics = 4; 1607 } 1608 else 1609 { 1610 nargs = amask >> 2; 1611 nstatics = amask & 3; 1612 } 1613 1614 sep = ""; 1615 if (nargs > 0) 1616 { 1617 infprintf (is, "%s", mips_gpr_names[4]); 1618 if (nargs > 1) 1619 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); 1620 sep = ","; 1621 } 1622 1623 frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; 1624 if (frame_size == 0 && !use_extend) 1625 frame_size = 128; 1626 infprintf (is, "%s%d", sep, frame_size); 1627 1628 if (insn & 0x40) /* $ra */ 1629 infprintf (is, ",%s", mips_gpr_names[31]); 1630 1631 nsreg = (extend >> 8) & 0x7; 1632 smask = 0; 1633 if (insn & 0x20) /* $s0 */ 1634 smask |= 1 << 0; 1635 if (insn & 0x10) /* $s1 */ 1636 smask |= 1 << 1; 1637 if (nsreg > 0) /* $s2-$s8 */ 1638 smask |= ((1 << nsreg) - 1) << 2; 1639 1640 for (i = 0; i < 9; i++) 1641 if (smask & (1 << i)) 1642 { 1643 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1644 /* Skip over string of set bits. */ 1645 for (j = i; smask & (2 << j); j++) 1646 continue; 1647 if (j > i) 1648 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1649 i = j + 1; 1650 } 1651 /* Statics $ax - $a3. */ 1652 if (nstatics == 1) 1653 infprintf (is, ",%s", mips_gpr_names[7]); 1654 else if (nstatics > 0) 1655 infprintf (is, ",%s-%s", 1656 mips_gpr_names[7 - nstatics + 1], 1657 mips_gpr_names[7]); 1658 break; 1659 } 1660 1661 if (is_offset && operand->type == OP_INT) 1662 { 1663 const struct mips_int_operand *int_op; 1664 1665 int_op = (const struct mips_int_operand *) operand; 1666 info->insn_type = dis_dref; 1667 info->data_size = 1 << int_op->shift; 1668 } 1669 1670 if (operand->size == 26) 1671 /* In this case INSN is the first two bytes of the instruction 1672 and EXTEND is the second two bytes. */ 1673 uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend; 1674 else 1675 { 1676 /* Calculate the full field value. */ 1677 uval = mips_extract_operand (operand, insn); 1678 if (use_extend) 1679 { 1680 ext_operand = decode_mips16_operand (type, TRUE); 1681 if (ext_operand != operand) 1682 { 1683 operand = ext_operand; 1684 if (operand->size == 16) 1685 uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1686 else if (operand->size == 15) 1687 uval |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1688 else 1689 uval = ((extend >> 6) & 0x1f) | (extend & 0x20); 1690 } 1691 } 1692 } 1693 1694 baseaddr = memaddr + 2; 1695 if (operand->type == OP_PCREL) 1696 { 1697 const struct mips_pcrel_operand *pcrel_op; 1698 1699 pcrel_op = (const struct mips_pcrel_operand *) operand; 1700 if (!pcrel_op->include_isa_bit && use_extend) 1701 baseaddr = memaddr - 2; 1702 else if (!pcrel_op->include_isa_bit) 1703 { 1704 bfd_byte buffer[2]; 1705 1706 /* If this instruction is in the delay slot of a JR 1707 instruction, the base address is the address of the 1708 JR instruction. If it is in the delay slot of a JALR 1709 instruction, the base address is the address of the 1710 JALR instruction. This test is unreliable: we have 1711 no way of knowing whether the previous word is 1712 instruction or data. */ 1713 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 1714 && (((info->endian == BFD_ENDIAN_BIG 1715 ? bfd_getb16 (buffer) 1716 : bfd_getl16 (buffer)) 1717 & 0xf800) == 0x1800)) 1718 baseaddr = memaddr - 4; 1719 else if (info->read_memory_func (memaddr - 2, buffer, 2, 1720 info) == 0 1721 && (((info->endian == BFD_ENDIAN_BIG 1722 ? bfd_getb16 (buffer) 1723 : bfd_getl16 (buffer)) 1724 & 0xf81f) == 0xe800)) 1725 baseaddr = memaddr - 2; 1726 else 1727 baseaddr = memaddr; 1728 } 1729 } 1730 1731 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); 1732 break; 1733 } 1734 } 1735 1736 1737 /* Check if the given address is the last word of a MIPS16 PLT entry. 1738 This word is data and depending on the value it may interfere with 1739 disassembly of further PLT entries. We make use of the fact PLT 1740 symbols are marked BSF_SYNTHETIC. */ 1741 static bfd_boolean 1742 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) 1743 { 1744 if (info->symbols 1745 && info->symbols[0] 1746 && (info->symbols[0]->flags & BSF_SYNTHETIC) 1747 && addr == bfd_asymbol_value (info->symbols[0]) + 12) 1748 return TRUE; 1749 1750 return FALSE; 1751 } 1752 1753 /* Disassemble mips16 instructions. */ 1754 1755 static int 1756 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 1757 { 1758 const fprintf_ftype infprintf = info->fprintf_func; 1759 int status; 1760 bfd_byte buffer[4]; 1761 int length; 1762 int insn; 1763 bfd_boolean use_extend; 1764 int extend = 0; 1765 const struct mips_opcode *op, *opend; 1766 struct mips_print_arg_state state; 1767 void *is = info->stream; 1768 1769 info->bytes_per_chunk = 2; 1770 info->display_endian = info->endian; 1771 info->insn_info_valid = 1; 1772 info->branch_delay_insns = 0; 1773 info->data_size = 0; 1774 info->target = 0; 1775 info->target2 = 0; 1776 1777 #define GET_OP(insn, field) \ 1778 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field) 1779 /* Decode PLT entry's GOT slot address word. */ 1780 if (is_mips16_plt_tail (info, memaddr)) 1781 { 1782 info->insn_type = dis_noninsn; 1783 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 1784 if (status == 0) 1785 { 1786 unsigned int gotslot; 1787 1788 if (info->endian == BFD_ENDIAN_BIG) 1789 gotslot = bfd_getb32 (buffer); 1790 else 1791 gotslot = bfd_getl32 (buffer); 1792 infprintf (is, ".word\t0x%x", gotslot); 1793 1794 return 4; 1795 } 1796 } 1797 else 1798 { 1799 info->insn_type = dis_nonbranch; 1800 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1801 } 1802 if (status != 0) 1803 { 1804 (*info->memory_error_func) (status, memaddr, info); 1805 return -1; 1806 } 1807 1808 length = 2; 1809 1810 if (info->endian == BFD_ENDIAN_BIG) 1811 insn = bfd_getb16 (buffer); 1812 else 1813 insn = bfd_getl16 (buffer); 1814 1815 /* Handle the extend opcode specially. */ 1816 use_extend = FALSE; 1817 if ((insn & 0xf800) == 0xf000) 1818 { 1819 use_extend = TRUE; 1820 extend = insn & 0x7ff; 1821 1822 memaddr += 2; 1823 1824 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1825 if (status != 0) 1826 { 1827 infprintf (is, "extend 0x%x", (unsigned int) extend); 1828 (*info->memory_error_func) (status, memaddr, info); 1829 return -1; 1830 } 1831 1832 if (info->endian == BFD_ENDIAN_BIG) 1833 insn = bfd_getb16 (buffer); 1834 else 1835 insn = bfd_getl16 (buffer); 1836 1837 /* Check for an extend opcode followed by an extend opcode. */ 1838 if ((insn & 0xf800) == 0xf000) 1839 { 1840 infprintf (is, "extend 0x%x", (unsigned int) extend); 1841 info->insn_type = dis_noninsn; 1842 return length; 1843 } 1844 1845 length += 2; 1846 } 1847 1848 /* FIXME: Should probably use a hash table on the major opcode here. */ 1849 1850 opend = mips16_opcodes + bfd_mips16_num_opcodes; 1851 for (op = mips16_opcodes; op < opend; op++) 1852 { 1853 if (op->pinfo != INSN_MACRO 1854 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1855 && (insn & op->mask) == op->match) 1856 { 1857 const char *s; 1858 1859 if (op->args[0] == 'a' || op->args[0] == 'i') 1860 { 1861 if (use_extend) 1862 { 1863 infprintf (is, "extend 0x%x", (unsigned int) extend); 1864 info->insn_type = dis_noninsn; 1865 return length - 2; 1866 } 1867 1868 use_extend = FALSE; 1869 1870 memaddr += 2; 1871 1872 status = (*info->read_memory_func) (memaddr, buffer, 2, 1873 info); 1874 if (status == 0) 1875 { 1876 use_extend = TRUE; 1877 if (info->endian == BFD_ENDIAN_BIG) 1878 extend = bfd_getb16 (buffer); 1879 else 1880 extend = bfd_getl16 (buffer); 1881 length += 2; 1882 } 1883 } 1884 1885 infprintf (is, "%s", op->name); 1886 if (op->args[0] != '\0') 1887 infprintf (is, "\t"); 1888 1889 init_print_arg_state (&state); 1890 for (s = op->args; *s != '\0'; s++) 1891 { 1892 if (*s == ',' 1893 && s[1] == 'w' 1894 && GET_OP (insn, RX) == GET_OP (insn, RY)) 1895 { 1896 /* Skip the register and the comma. */ 1897 ++s; 1898 continue; 1899 } 1900 if (*s == ',' 1901 && s[1] == 'v' 1902 && GET_OP (insn, RZ) == GET_OP (insn, RX)) 1903 { 1904 /* Skip the register and the comma. */ 1905 ++s; 1906 continue; 1907 } 1908 print_mips16_insn_arg (info, &state, op, *s, memaddr, insn, 1909 use_extend, extend, s[1] == '('); 1910 } 1911 1912 /* Figure out branch instruction type and delay slot information. */ 1913 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1914 info->branch_delay_insns = 1; 1915 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 1916 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0) 1917 { 1918 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1919 info->insn_type = dis_jsr; 1920 else 1921 info->insn_type = dis_branch; 1922 } 1923 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) 1924 info->insn_type = dis_condbranch; 1925 1926 return length; 1927 } 1928 } 1929 #undef GET_OP 1930 1931 if (use_extend) 1932 infprintf (is, "0x%x", extend | 0xf000); 1933 infprintf (is, "0x%x", insn); 1934 info->insn_type = dis_noninsn; 1935 1936 return length; 1937 } 1938 1939 /* Disassemble microMIPS instructions. */ 1940 1941 static int 1942 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) 1943 { 1944 const fprintf_ftype infprintf = info->fprintf_func; 1945 const struct mips_opcode *op, *opend; 1946 void *is = info->stream; 1947 bfd_byte buffer[2]; 1948 unsigned int higher; 1949 unsigned int length; 1950 int status; 1951 unsigned int insn; 1952 1953 info->bytes_per_chunk = 2; 1954 info->display_endian = info->endian; 1955 info->insn_info_valid = 1; 1956 info->branch_delay_insns = 0; 1957 info->data_size = 0; 1958 info->insn_type = dis_nonbranch; 1959 info->target = 0; 1960 info->target2 = 0; 1961 1962 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1963 if (status != 0) 1964 { 1965 (*info->memory_error_func) (status, memaddr, info); 1966 return -1; 1967 } 1968 1969 length = 2; 1970 1971 if (info->endian == BFD_ENDIAN_BIG) 1972 insn = bfd_getb16 (buffer); 1973 else 1974 insn = bfd_getl16 (buffer); 1975 1976 if ((insn & 0xfc00) == 0x7c00) 1977 { 1978 /* This is a 48-bit microMIPS instruction. */ 1979 higher = insn; 1980 1981 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 1982 if (status != 0) 1983 { 1984 infprintf (is, "micromips 0x%x", higher); 1985 (*info->memory_error_func) (status, memaddr + 2, info); 1986 return -1; 1987 } 1988 if (info->endian == BFD_ENDIAN_BIG) 1989 insn = bfd_getb16 (buffer); 1990 else 1991 insn = bfd_getl16 (buffer); 1992 higher = (higher << 16) | insn; 1993 1994 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); 1995 if (status != 0) 1996 { 1997 infprintf (is, "micromips 0x%x", higher); 1998 (*info->memory_error_func) (status, memaddr + 4, info); 1999 return -1; 2000 } 2001 if (info->endian == BFD_ENDIAN_BIG) 2002 insn = bfd_getb16 (buffer); 2003 else 2004 insn = bfd_getl16 (buffer); 2005 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); 2006 2007 info->insn_type = dis_noninsn; 2008 return 6; 2009 } 2010 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) 2011 { 2012 /* This is a 32-bit microMIPS instruction. */ 2013 higher = insn; 2014 2015 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2016 if (status != 0) 2017 { 2018 infprintf (is, "micromips 0x%x", higher); 2019 (*info->memory_error_func) (status, memaddr + 2, info); 2020 return -1; 2021 } 2022 2023 if (info->endian == BFD_ENDIAN_BIG) 2024 insn = bfd_getb16 (buffer); 2025 else 2026 insn = bfd_getl16 (buffer); 2027 2028 insn = insn | (higher << 16); 2029 2030 length += 2; 2031 } 2032 2033 /* FIXME: Should probably use a hash table on the major opcode here. */ 2034 2035 opend = micromips_opcodes + bfd_micromips_num_opcodes; 2036 for (op = micromips_opcodes; op < opend; op++) 2037 { 2038 if (op->pinfo != INSN_MACRO 2039 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2040 && (insn & op->mask) == op->match 2041 && ((length == 2 && (op->mask & 0xffff0000) == 0) 2042 || (length == 4 && (op->mask & 0xffff0000) != 0))) 2043 { 2044 infprintf (is, "%s", op->name); 2045 2046 if (op->args[0]) 2047 { 2048 infprintf (is, "\t"); 2049 print_insn_args (info, op, decode_micromips_operand, insn, 2050 memaddr + length + 1); 2051 } 2052 2053 /* Figure out instruction type and branch delay information. */ 2054 if ((op->pinfo 2055 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0) 2056 info->branch_delay_insns = 1; 2057 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY) 2058 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0) 2059 { 2060 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 2061 info->insn_type = dis_jsr; 2062 else 2063 info->insn_type = dis_branch; 2064 } 2065 else if (((op->pinfo & INSN_COND_BRANCH_DELAY) 2066 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0) 2067 { 2068 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2069 info->insn_type = dis_condjsr; 2070 else 2071 info->insn_type = dis_condbranch; 2072 } 2073 else if ((op->pinfo 2074 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) 2075 info->insn_type = dis_dref; 2076 2077 return length; 2078 } 2079 } 2080 2081 infprintf (is, "0x%x", insn); 2082 info->insn_type = dis_noninsn; 2083 2084 return length; 2085 } 2086 2087 /* Return 1 if a symbol associated with the location being disassembled 2088 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over 2089 all the symbols at the address being considered assuming if at least 2090 one of them indicates code compression, then such code has been 2091 genuinely produced here (other symbols could have been derived from 2092 function symbols defined elsewhere or could define data). Otherwise, 2093 return 0. */ 2094 2095 static bfd_boolean 2096 is_compressed_mode_p (struct disassemble_info *info) 2097 { 2098 int i; 2099 int l; 2100 2101 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) 2102 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 2103 && ((!micromips_ase 2104 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) 2105 || (micromips_ase 2106 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) 2107 return 1; 2108 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour 2109 && info->symtab[i]->section == info->section) 2110 { 2111 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; 2112 if ((!micromips_ase 2113 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) 2114 || (micromips_ase 2115 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) 2116 return 1; 2117 } 2118 2119 return 0; 2120 } 2121 2122 /* In an environment where we do not know the symbol type of the 2123 instruction we are forced to assume that the low order bit of the 2124 instructions' address may mark it as a mips16 instruction. If we 2125 are single stepping, or the pc is within the disassembled function, 2126 this works. Otherwise, we need a clue. Sometimes. */ 2127 2128 static int 2129 _print_insn_mips (bfd_vma memaddr, 2130 struct disassemble_info *info, 2131 enum bfd_endian endianness) 2132 { 2133 int (*print_insn_compr) (bfd_vma, struct disassemble_info *); 2134 bfd_byte buffer[INSNLEN]; 2135 int status; 2136 2137 set_default_mips_dis_options (info); 2138 parse_mips_dis_options (info->disassembler_options); 2139 2140 if (info->mach == bfd_mach_mips16) 2141 return print_insn_mips16 (memaddr, info); 2142 if (info->mach == bfd_mach_mips_micromips) 2143 return print_insn_micromips (memaddr, info); 2144 2145 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips; 2146 2147 #if 1 2148 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ 2149 /* Only a few tools will work this way. */ 2150 if (memaddr & 0x01) 2151 return print_insn_compr (memaddr, info); 2152 #endif 2153 2154 #if SYMTAB_AVAILABLE 2155 if (is_compressed_mode_p (info)) 2156 return print_insn_compr (memaddr, info); 2157 #endif 2158 2159 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2160 if (status == 0) 2161 { 2162 int insn; 2163 2164 if (endianness == BFD_ENDIAN_BIG) 2165 insn = bfd_getb32 (buffer); 2166 else 2167 insn = bfd_getl32 (buffer); 2168 2169 return print_insn_mips (memaddr, insn, info); 2170 } 2171 else 2172 { 2173 (*info->memory_error_func) (status, memaddr, info); 2174 return -1; 2175 } 2176 } 2177 2178 int 2179 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2180 { 2181 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2182 } 2183 2184 int 2185 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2186 { 2187 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2188 } 2189 2190 void 2192 print_mips_disassembler_options (FILE *stream) 2193 { 2194 unsigned int i; 2195 2196 fprintf (stream, _("\n\ 2197 The following MIPS specific disassembler options are supported for use\n\ 2198 with the -M switch (multiple options should be separated by commas):\n")); 2199 2200 fprintf (stream, _("\n\ 2201 msa Recognize MSA instructions.\n")); 2202 2203 fprintf (stream, _("\n\ 2204 virt Recognize the virtualization ASE instructions.\n")); 2205 2206 fprintf (stream, _("\n\ 2207 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2208 Default: based on binary being disassembled.\n")); 2209 2210 fprintf (stream, _("\n\ 2211 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2212 Default: numeric.\n")); 2213 2214 fprintf (stream, _("\n\ 2215 cp0-names=ARCH Print CP0 register names according to\n\ 2216 specified architecture.\n\ 2217 Default: based on binary being disassembled.\n")); 2218 2219 fprintf (stream, _("\n\ 2220 hwr-names=ARCH Print HWR names according to specified \n\ 2221 architecture.\n\ 2222 Default: based on binary being disassembled.\n")); 2223 2224 fprintf (stream, _("\n\ 2225 reg-names=ABI Print GPR and FPR names according to\n\ 2226 specified ABI.\n")); 2227 2228 fprintf (stream, _("\n\ 2229 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2230 specified architecture.\n")); 2231 2232 fprintf (stream, _("\n\ 2233 For the options above, the following values are supported for \"ABI\":\n\ 2234 ")); 2235 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2236 fprintf (stream, " %s", mips_abi_choices[i].name); 2237 fprintf (stream, _("\n")); 2238 2239 fprintf (stream, _("\n\ 2240 For the options above, The following values are supported for \"ARCH\":\n\ 2241 ")); 2242 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2243 if (*mips_arch_choices[i].name != '\0') 2244 fprintf (stream, " %s", mips_arch_choices[i].name); 2245 fprintf (stream, _("\n")); 2246 2247 fprintf (stream, _("\n")); 2248 } 2249
Indexes created Mon Mar 30 00:23:01 UTC 2026