riscv-dis.c revision 1.1.1.5
1 /* RISC-V disassembler 2 Copyright (C) 2011-2024 Free Software Foundation, Inc. 3 4 Contributed by Andrew Waterman (andrew (at) sifive.com). 5 Based on MIPS target. 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING3. If not, 21 see <http://www.gnu.org/licenses/>. */ 22 23 #include "sysdep.h" 24 #include "disassemble.h" 25 #include "libiberty.h" 26 #include "opcode/riscv.h" 27 #include "opintl.h" 28 #include "elf-bfd.h" 29 #include "elf/riscv.h" 30 #include "elfxx-riscv.h" 31 32 #include <stdint.h> 33 #include <ctype.h> 34 35 /* Current XLEN for the disassembler. */ 36 static unsigned xlen = 0; 37 38 /* Default ISA specification version (constant as of now). */ 39 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; 40 41 /* Default privileged specification 42 (as specified by the ELF attributes or the `priv-spec' option). */ 43 static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; 44 45 static riscv_subset_list_t riscv_subsets; 46 static riscv_parse_subset_t riscv_rps_dis = 47 { 48 &riscv_subsets, /* subset_list. */ 49 opcodes_error_handler,/* error_handler. */ 50 &xlen, /* xlen. */ 51 &default_isa_spec, /* isa_spec. */ 52 false, /* check_unknown_prefixed_ext. */ 53 }; 54 55 struct riscv_private_data 56 { 57 bfd_vma gp; 58 bfd_vma print_addr; 59 bfd_vma hi_addr[OP_MASK_RD + 1]; 60 bool to_print_addr; 61 bool has_gp; 62 }; 63 64 /* Used for mapping symbols. */ 65 static int last_map_symbol = -1; 66 static bfd_vma last_stop_offset = 0; 67 static bfd_vma last_map_symbol_boundary = 0; 68 static enum riscv_seg_mstate last_map_state = MAP_NONE; 69 static asection *last_map_section = NULL; 70 71 /* Register names as used by the disassembler. */ 72 static const char (*riscv_gpr_names)[NRC]; 73 static const char (*riscv_fpr_names)[NRC]; 74 75 /* If set, disassemble as most general instruction. */ 76 static bool no_aliases = false; 77 78 79 /* Set default RISC-V disassembler options. */ 80 81 static void 82 set_default_riscv_dis_options (void) 83 { 84 riscv_gpr_names = riscv_gpr_names_abi; 85 riscv_fpr_names = riscv_fpr_names_abi; 86 no_aliases = false; 87 } 88 89 /* Parse RISC-V disassembler option (without arguments). */ 90 91 static bool 92 parse_riscv_dis_option_without_args (const char *option) 93 { 94 if (strcmp (option, "no-aliases") == 0) 95 no_aliases = true; 96 else if (strcmp (option, "numeric") == 0) 97 { 98 riscv_gpr_names = riscv_gpr_names_numeric; 99 riscv_fpr_names = riscv_fpr_names_numeric; 100 } 101 else 102 return false; 103 return true; 104 } 105 106 /* Parse RISC-V disassembler option (possibly with arguments). */ 107 108 static void 109 parse_riscv_dis_option (const char *option) 110 { 111 char *equal, *value; 112 113 if (parse_riscv_dis_option_without_args (option)) 114 return; 115 116 equal = strchr (option, '='); 117 if (equal == NULL) 118 { 119 /* The option without '=' should be defined above. */ 120 opcodes_error_handler (_("unrecognized disassembler option: %s"), option); 121 return; 122 } 123 if (equal == option 124 || *(equal + 1) == '\0') 125 { 126 /* Invalid options with '=', no option name before '=', 127 and no value after '='. */ 128 opcodes_error_handler (_("unrecognized disassembler option with '=': %s"), 129 option); 130 return; 131 } 132 133 *equal = '\0'; 134 value = equal + 1; 135 if (strcmp (option, "priv-spec") == 0) 136 { 137 enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE; 138 const char *name = NULL; 139 140 RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec); 141 if (priv_spec == PRIV_SPEC_CLASS_NONE) 142 opcodes_error_handler (_("unknown privileged spec set by %s=%s"), 143 option, value); 144 else if (default_priv_spec == PRIV_SPEC_CLASS_NONE) 145 default_priv_spec = priv_spec; 146 else if (default_priv_spec != priv_spec) 147 { 148 RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec); 149 opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, " 150 "the elf privilege attribute is %s"), 151 option, value, name); 152 } 153 } 154 else 155 { 156 /* xgettext:c-format */ 157 opcodes_error_handler (_("unrecognized disassembler option: %s"), option); 158 } 159 } 160 161 /* Parse RISC-V disassembler options. */ 162 163 static void 164 parse_riscv_dis_options (const char *opts_in) 165 { 166 char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; 167 168 set_default_riscv_dis_options (); 169 170 for ( ; opt_end != NULL; opt = opt_end + 1) 171 { 172 if ((opt_end = strchr (opt, ',')) != NULL) 173 *opt_end = 0; 174 parse_riscv_dis_option (opt); 175 } 176 177 free (opts); 178 } 179 180 /* Print one argument from an array. */ 181 182 static void 183 arg_print (struct disassemble_info *info, unsigned long val, 184 const char* const* array, size_t size) 185 { 186 const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; 187 (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s", s); 188 } 189 190 /* If we need to print an address, set its value and state. */ 191 192 static void 193 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, 194 int wide) 195 { 196 if (pd->hi_addr[base_reg] != (bfd_vma)-1) 197 { 198 pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset; 199 pd->hi_addr[base_reg] = -1; 200 } 201 else if (base_reg == X_GP && pd->has_gp) 202 pd->print_addr = pd->gp + offset; 203 else if (base_reg == X_TP || base_reg == 0) 204 pd->print_addr = offset; 205 else 206 return; /* Don't print the address. */ 207 pd->to_print_addr = true; 208 209 /* Sign-extend a 32-bit value to a 64-bit value. */ 210 if (wide) 211 pd->print_addr = (bfd_vma)(int32_t) pd->print_addr; 212 213 /* Fit into a 32-bit value on RV32. */ 214 if (xlen == 32) 215 pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr; 216 } 217 218 /* Get Zcmp reg_list field. */ 219 220 static void 221 print_reg_list (disassemble_info *info, insn_t l) 222 { 223 bool numeric = riscv_gpr_names == riscv_gpr_names_numeric; 224 unsigned reg_list = (int)EXTRACT_OPERAND (REG_LIST, l); 225 unsigned r_start = numeric ? X_S2 : X_S0; 226 info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]); 227 228 if (reg_list == 5) 229 info->fprintf_func (info->stream, ",%s", 230 riscv_gpr_names[X_S0]); 231 else if (reg_list == 6 || (numeric && reg_list > 6)) 232 info->fprintf_func (info->stream, ",%s-%s", 233 riscv_gpr_names[X_S0], 234 riscv_gpr_names[X_S1]); 235 if (reg_list == 15) 236 info->fprintf_func (info->stream, ",%s-%s", 237 riscv_gpr_names[r_start], 238 riscv_gpr_names[X_S11]); 239 else if (reg_list == 7 && numeric) 240 info->fprintf_func (info->stream, ",%s", 241 riscv_gpr_names[X_S2]); 242 else if (reg_list > 6) 243 info->fprintf_func (info->stream, ",%s-%s", 244 riscv_gpr_names[r_start], 245 riscv_gpr_names[reg_list + 11]); 246 } 247 248 /* Get Zcmp sp adjustment immediate. */ 249 250 static int 251 riscv_get_spimm (insn_t l) 252 { 253 int spimm = riscv_get_sp_base(l, *riscv_rps_dis.xlen); 254 spimm += EXTRACT_ZCMP_SPIMM (l); 255 if (((l ^ MATCH_CM_PUSH) & MASK_CM_PUSH) == 0) 256 spimm *= -1; 257 return spimm; 258 } 259 260 /* Print insn arguments for 32/64-bit code. */ 261 262 static void 263 print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info) 264 { 265 struct riscv_private_data *pd = info->private_data; 266 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; 267 int rd = (l >> OP_SH_RD) & OP_MASK_RD; 268 fprintf_styled_ftype print = info->fprintf_styled_func; 269 const char *opargStart; 270 271 if (*oparg != '\0') 272 print (info->stream, dis_style_text, "\t"); 273 274 for (; *oparg != '\0'; oparg++) 275 { 276 opargStart = oparg; 277 switch (*oparg) 278 { 279 case 'C': /* RVC */ 280 switch (*++oparg) 281 { 282 case 's': /* RS1 x8-x15. */ 283 case 'w': /* RS1 x8-x15. */ 284 print (info->stream, dis_style_register, "%s", 285 riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); 286 break; 287 case 't': /* RS2 x8-x15. */ 288 case 'x': /* RS2 x8-x15. */ 289 print (info->stream, dis_style_register, "%s", 290 riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); 291 break; 292 case 'U': /* RS1, constrained to equal RD. */ 293 print (info->stream, dis_style_register, 294 "%s", riscv_gpr_names[rd]); 295 break; 296 case 'c': /* RS1, constrained to equal sp. */ 297 print (info->stream, dis_style_register, "%s", 298 riscv_gpr_names[X_SP]); 299 break; 300 case 'V': /* RS2 */ 301 print (info->stream, dis_style_register, "%s", 302 riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); 303 break; 304 case 'o': 305 case 'j': 306 if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) 307 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); 308 if (info->mach == bfd_mach_riscv64 309 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) 310 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); 311 print (info->stream, dis_style_immediate, "%d", 312 (int)EXTRACT_CITYPE_IMM (l)); 313 break; 314 case 'k': 315 print (info->stream, dis_style_address_offset, "%d", 316 (int)EXTRACT_CLTYPE_LW_IMM (l)); 317 break; 318 case 'l': 319 print (info->stream, dis_style_address_offset, "%d", 320 (int)EXTRACT_CLTYPE_LD_IMM (l)); 321 break; 322 case 'm': 323 print (info->stream, dis_style_address_offset, "%d", 324 (int)EXTRACT_CITYPE_LWSP_IMM (l)); 325 break; 326 case 'n': 327 print (info->stream, dis_style_address_offset, "%d", 328 (int)EXTRACT_CITYPE_LDSP_IMM (l)); 329 break; 330 case 'K': 331 print (info->stream, dis_style_immediate, "%d", 332 (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l)); 333 break; 334 case 'L': 335 print (info->stream, dis_style_immediate, "%d", 336 (int)EXTRACT_CITYPE_ADDI16SP_IMM (l)); 337 break; 338 case 'M': 339 print (info->stream, dis_style_address_offset, "%d", 340 (int)EXTRACT_CSSTYPE_SWSP_IMM (l)); 341 break; 342 case 'N': 343 print (info->stream, dis_style_address_offset, "%d", 344 (int)EXTRACT_CSSTYPE_SDSP_IMM (l)); 345 break; 346 case 'p': 347 info->target = EXTRACT_CBTYPE_IMM (l) + pc; 348 (*info->print_address_func) (info->target, info); 349 break; 350 case 'a': 351 info->target = EXTRACT_CJTYPE_IMM (l) + pc; 352 (*info->print_address_func) (info->target, info); 353 break; 354 case 'u': 355 print (info->stream, dis_style_immediate, "0x%x", 356 (unsigned)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1))); 357 break; 358 case '>': 359 print (info->stream, dis_style_immediate, "0x%x", 360 (unsigned)EXTRACT_CITYPE_IMM (l) & 0x3f); 361 break; 362 case '<': 363 print (info->stream, dis_style_immediate, "0x%x", 364 (unsigned)EXTRACT_CITYPE_IMM (l) & 0x1f); 365 break; 366 case 'T': /* Floating-point RS2. */ 367 print (info->stream, dis_style_register, "%s", 368 riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); 369 break; 370 case 'D': /* Floating-point RS2 x8-x15. */ 371 print (info->stream, dis_style_register, "%s", 372 riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); 373 break; 374 } 375 break; 376 377 case 'V': /* RVV */ 378 switch (*++oparg) 379 { 380 case 'd': 381 case 'f': 382 print (info->stream, dis_style_register, "%s", 383 riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]); 384 break; 385 case 'e': 386 if (!EXTRACT_OPERAND (VWD, l)) 387 print (info->stream, dis_style_register, "%s", 388 riscv_gpr_names[0]); 389 else 390 print (info->stream, dis_style_register, "%s", 391 riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]); 392 break; 393 case 's': 394 print (info->stream, dis_style_register, "%s", 395 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS1, l)]); 396 break; 397 case 't': 398 case 'u': /* VS1 == VS2 already verified at this point. */ 399 case 'v': /* VD == VS1 == VS2 already verified at this point. */ 400 print (info->stream, dis_style_register, "%s", 401 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]); 402 break; 403 case '0': 404 print (info->stream, dis_style_register, "%s", 405 riscv_vecr_names_numeric[0]); 406 break; 407 case 'b': 408 case 'c': 409 { 410 int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l) 411 : EXTRACT_RVV_VC_IMM (l); 412 unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm); 413 unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm); 414 unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm); 415 unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm); 416 unsigned int imm_vtype_res = (imm >> 8); 417 418 if (imm_vsew < ARRAY_SIZE (riscv_vsew) 419 && imm_vlmul < ARRAY_SIZE (riscv_vlmul) 420 && imm_vta < ARRAY_SIZE (riscv_vta) 421 && imm_vma < ARRAY_SIZE (riscv_vma) 422 && !imm_vtype_res 423 && riscv_vsew[imm_vsew] != NULL 424 && riscv_vlmul[imm_vlmul] != NULL) 425 print (info->stream, dis_style_text, "%s,%s,%s,%s", 426 riscv_vsew[imm_vsew], 427 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta], 428 riscv_vma[imm_vma]); 429 else 430 print (info->stream, dis_style_immediate, "%d", imm); 431 } 432 break; 433 case 'i': 434 print (info->stream, dis_style_immediate, "%d", 435 (int)EXTRACT_RVV_VI_IMM (l)); 436 break; 437 case 'j': 438 print (info->stream, dis_style_immediate, "%d", 439 (int)EXTRACT_RVV_VI_UIMM (l)); 440 break; 441 case 'k': 442 print (info->stream, dis_style_immediate, "%d", 443 (int)EXTRACT_RVV_OFFSET (l)); 444 break; 445 case 'l': 446 print (info->stream, dis_style_immediate, "%d", 447 (int)EXTRACT_RVV_VI_UIMM6 (l)); 448 break; 449 case 'm': 450 if (!EXTRACT_OPERAND (VMASK, l)) 451 { 452 print (info->stream, dis_style_text, ","); 453 print (info->stream, dis_style_register, "%s", 454 riscv_vecm_names_numeric[0]); 455 } 456 break; 457 } 458 break; 459 460 case ',': 461 case '(': 462 case ')': 463 case '[': 464 case ']': 465 case '{': 466 case '}': 467 print (info->stream, dis_style_text, "%c", *oparg); 468 break; 469 470 case '0': 471 /* Only print constant 0 if it is the last argument. */ 472 if (!oparg[1]) 473 print (info->stream, dis_style_immediate, "0"); 474 break; 475 476 case 's': 477 if ((l & MASK_JALR) == MATCH_JALR) 478 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); 479 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]); 480 break; 481 482 case 't': 483 print (info->stream, dis_style_register, "%s", 484 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); 485 break; 486 487 case 'u': 488 print (info->stream, dis_style_immediate, "0x%x", 489 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); 490 break; 491 492 case 'm': 493 arg_print (info, EXTRACT_OPERAND (RM, l), 494 riscv_rm, ARRAY_SIZE (riscv_rm)); 495 break; 496 497 case 'P': 498 arg_print (info, EXTRACT_OPERAND (PRED, l), 499 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); 500 break; 501 502 case 'Q': 503 arg_print (info, EXTRACT_OPERAND (SUCC, l), 504 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); 505 break; 506 507 case 'o': 508 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); 509 /* Fall through. */ 510 case 'j': 511 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) 512 || (l & MASK_JALR) == MATCH_JALR) 513 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); 514 if (info->mach == bfd_mach_riscv64 515 && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) 516 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); 517 print (info->stream, dis_style_immediate, "%d", 518 (int)EXTRACT_ITYPE_IMM (l)); 519 break; 520 521 case 'q': 522 maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0); 523 print (info->stream, dis_style_address_offset, "%d", 524 (int)EXTRACT_STYPE_IMM (l)); 525 break; 526 527 case 'a': 528 info->target = EXTRACT_JTYPE_IMM (l) + pc; 529 (*info->print_address_func) (info->target, info); 530 break; 531 532 case 'p': 533 info->target = EXTRACT_BTYPE_IMM (l) + pc; 534 (*info->print_address_func) (info->target, info); 535 break; 536 537 case 'd': 538 if ((l & MASK_AUIPC) == MATCH_AUIPC) 539 pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); 540 else if ((l & MASK_LUI) == MATCH_LUI) 541 pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); 542 else if ((l & MASK_C_LUI) == MATCH_C_LUI) 543 pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l); 544 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rd]); 545 break; 546 547 case 'y': 548 print (info->stream, dis_style_immediate, "0x%x", 549 EXTRACT_OPERAND (BS, l)); 550 break; 551 552 case 'z': 553 print (info->stream, dis_style_register, "%s", riscv_gpr_names[0]); 554 break; 555 556 case '>': 557 print (info->stream, dis_style_immediate, "0x%x", 558 EXTRACT_OPERAND (SHAMT, l)); 559 break; 560 561 case '<': 562 print (info->stream, dis_style_immediate, "0x%x", 563 EXTRACT_OPERAND (SHAMTW, l)); 564 break; 565 566 case 'S': 567 case 'U': 568 print (info->stream, dis_style_register, "%s", riscv_fpr_names[rs1]); 569 break; 570 571 case 'T': 572 print (info->stream, dis_style_register, "%s", 573 riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); 574 break; 575 576 case 'D': 577 print (info->stream, dis_style_register, "%s", riscv_fpr_names[rd]); 578 break; 579 580 case 'R': 581 print (info->stream, dis_style_register, "%s", 582 riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); 583 break; 584 585 case 'E': 586 { 587 static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */ 588 static bool init_csr = false; 589 unsigned int csr = EXTRACT_OPERAND (CSR, l); 590 591 if (!init_csr) 592 { 593 unsigned int i; 594 for (i = 0; i < 4096; i++) 595 riscv_csr_hash[i] = NULL; 596 597 /* Set to the newest privileged version. */ 598 if (default_priv_spec == PRIV_SPEC_CLASS_NONE) 599 default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; 600 601 #define DECLARE_CSR(name, num, class, define_version, abort_version) \ 602 if (riscv_csr_hash[num] == NULL \ 603 && ((define_version == PRIV_SPEC_CLASS_NONE \ 604 && abort_version == PRIV_SPEC_CLASS_NONE) \ 605 || (default_priv_spec >= define_version \ 606 && default_priv_spec < abort_version))) \ 607 riscv_csr_hash[num] = #name; 608 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ 609 DECLARE_CSR (name, num, class, define_version, abort_version) 610 #include "opcode/riscv-opc.h" 611 #undef DECLARE_CSR 612 } 613 614 if (riscv_csr_hash[csr] != NULL) 615 if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector") 616 && (csr == CSR_VSTART 617 || csr == CSR_VXSAT 618 || csr == CSR_VXRM 619 || csr == CSR_VL 620 || csr == CSR_VTYPE 621 || csr == CSR_VLENB)) 622 print (info->stream, dis_style_register, "%s", 623 concat ("th.", riscv_csr_hash[csr], NULL)); 624 else 625 print (info->stream, dis_style_register, "%s", 626 riscv_csr_hash[csr]); 627 else 628 print (info->stream, dis_style_immediate, "0x%x", csr); 629 break; 630 } 631 632 case 'Y': 633 print (info->stream, dis_style_immediate, "0x%x", 634 EXTRACT_OPERAND (RNUM, l)); 635 break; 636 637 case 'Z': 638 print (info->stream, dis_style_immediate, "%d", rs1); 639 break; 640 641 case 'W': /* Various operands for standard z extensions. */ 642 switch (*++oparg) 643 { 644 case 'i': 645 switch (*++oparg) 646 { 647 case 'f': 648 print (info->stream, dis_style_address_offset, "%d", 649 (int) EXTRACT_STYPE_IMM (l)); 650 break; 651 default: 652 goto undefined_modifier; 653 } 654 break; 655 case 'f': 656 switch (*++oparg) 657 { 658 case 'v': 659 if (riscv_fli_symval[rs1]) 660 print (info->stream, dis_style_text, "%s", 661 riscv_fli_symval[rs1]); 662 else 663 print (info->stream, dis_style_immediate, "%a", 664 riscv_fli_numval[rs1]); 665 break; 666 default: 667 goto undefined_modifier; 668 } 669 break; 670 case 'c': /* Zcb extension 16 bits length instruction fields. */ 671 switch (*++oparg) 672 { 673 case 'b': 674 print (info->stream, dis_style_immediate, "%d", 675 (int)EXTRACT_ZCB_BYTE_UIMM (l)); 676 break; 677 case 'h': 678 print (info->stream, dis_style_immediate, "%d", 679 (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); 680 break; 681 case 'r': 682 print_reg_list (info, l); 683 break; 684 case 'p': 685 print (info->stream, dis_style_immediate, "%d", 686 riscv_get_spimm (l)); 687 break; 688 default: 689 goto undefined_modifier; 690 } 691 break; 692 default: 693 goto undefined_modifier; 694 } 695 break; 696 697 case 'X': /* Vendor-specific operands. */ 698 switch (*++oparg) 699 { 700 case 't': /* Vendor-specific (T-head) operands. */ 701 { 702 size_t n; 703 size_t s; 704 bool sign; 705 switch (*++oparg) 706 { 707 case 'V': 708 ++oparg; 709 if (*oparg != 'c') 710 goto undefined_modifier; 711 712 int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l) 713 : EXTRACT_RVV_VC_IMM (l); 714 unsigned int imm_vediv = EXTRACT_OPERAND (XTHEADVEDIV, imm); 715 unsigned int imm_vlmul = EXTRACT_OPERAND (XTHEADVLMUL, imm); 716 unsigned int imm_vsew = EXTRACT_OPERAND (XTHEADVSEW, imm); 717 unsigned int imm_vtype_res 718 = EXTRACT_OPERAND (XTHEADVTYPE_RES, imm); 719 if (imm_vsew < ARRAY_SIZE (riscv_vsew) 720 && imm_vlmul < ARRAY_SIZE (riscv_th_vlen) 721 && imm_vediv < ARRAY_SIZE (riscv_th_vediv) 722 && ! imm_vtype_res) 723 print (info->stream, dis_style_text, "%s,%s,%s", 724 riscv_vsew[imm_vsew], riscv_th_vlen[imm_vlmul], 725 riscv_th_vediv[imm_vediv]); 726 else 727 print (info->stream, dis_style_immediate, "%d", imm); 728 break; 729 case 'l': /* Integer immediate, literal. */ 730 oparg++; 731 while (*oparg && *oparg != ',') 732 { 733 print (info->stream, dis_style_immediate, "%c", *oparg); 734 oparg++; 735 } 736 oparg--; 737 break; 738 case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */ 739 sign = true; 740 goto print_imm; 741 case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */ 742 sign = false; 743 goto print_imm; 744 print_imm: 745 n = strtol (oparg + 1, (char **)&oparg, 10); 746 if (*oparg != '@') 747 goto undefined_modifier; 748 s = strtol (oparg + 1, (char **)&oparg, 10); 749 oparg--; 750 751 if (!sign) 752 print (info->stream, dis_style_immediate, "%lu", 753 (unsigned long)EXTRACT_U_IMM (n, s, l)); 754 else 755 print (info->stream, dis_style_immediate, "%li", 756 (signed long)EXTRACT_S_IMM (n, s, l)); 757 break; 758 default: 759 goto undefined_modifier; 760 } 761 } 762 break; 763 case 'c': /* Vendor-specific (CORE-V) operands. */ 764 switch (*++oparg) 765 { 766 case '2': 767 print (info->stream, dis_style_immediate, "%d", 768 ((int) EXTRACT_CV_IS2_UIMM5 (l))); 769 break; 770 case '3': 771 print (info->stream, dis_style_immediate, "%d", 772 ((int) EXTRACT_CV_IS3_UIMM5 (l))); 773 break; 774 default: 775 goto undefined_modifier; 776 } 777 break; 778 case 's': /* Vendor-specific (SiFive) operands. */ 779 switch (*++oparg) 780 { 781 /* SiFive vector coprocessor interface. */ 782 case 'd': 783 print (info->stream, dis_style_register, "0x%x", 784 (unsigned) EXTRACT_OPERAND (RD, l)); 785 break; 786 case 't': 787 print (info->stream, dis_style_register, "0x%x", 788 (unsigned) EXTRACT_OPERAND (RS2, l)); 789 break; 790 case 'O': 791 switch (*++oparg) 792 { 793 case '2': 794 print (info->stream, dis_style_register, "0x%x", 795 (unsigned) EXTRACT_OPERAND (XSO2, l)); 796 break; 797 case '1': 798 print (info->stream, dis_style_register, "0x%x", 799 (unsigned) EXTRACT_OPERAND (XSO1, l)); 800 break; 801 } 802 break; 803 } 804 break; 805 default: 806 goto undefined_modifier; 807 } 808 break; 809 810 default: 811 undefined_modifier: 812 /* xgettext:c-format */ 813 print (info->stream, dis_style_text, 814 _("# internal error, undefined modifier (%c)"), 815 *opargStart); 816 return; 817 } 818 } 819 } 820 821 /* Print the RISC-V instruction at address MEMADDR in debugged memory, 822 on using INFO. Returns length of the instruction, in bytes. 823 BIGENDIAN must be 1 if this is big-endian code, 0 if 824 this is little-endian code. */ 825 826 static int 827 riscv_disassemble_insn (bfd_vma memaddr, 828 insn_t word, 829 const bfd_byte *packet, 830 disassemble_info *info) 831 { 832 const struct riscv_opcode *op; 833 static bool init = false; 834 static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; 835 struct riscv_private_data *pd = info->private_data; 836 int insnlen, i; 837 bool printed; 838 839 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) 840 841 /* Build a hash table to shorten the search time. */ 842 if (! init) 843 { 844 for (op = riscv_opcodes; op->name; op++) 845 if (!riscv_hash[OP_HASH_IDX (op->match)]) 846 riscv_hash[OP_HASH_IDX (op->match)] = op; 847 848 init = true; 849 } 850 851 insnlen = riscv_insn_length (word); 852 853 /* RISC-V instructions are always little-endian. */ 854 info->endian_code = BFD_ENDIAN_LITTLE; 855 856 info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; 857 info->bytes_per_line = 8; 858 /* We don't support constant pools, so this must be code. */ 859 info->display_endian = info->endian_code; 860 info->insn_info_valid = 1; 861 info->branch_delay_insns = 0; 862 info->data_size = 0; 863 info->insn_type = dis_nonbranch; 864 info->target = 0; 865 info->target2 = 0; 866 867 op = riscv_hash[OP_HASH_IDX (word)]; 868 if (op != NULL) 869 { 870 /* If XLEN is not known, get its value from the ELF class. */ 871 if (info->mach == bfd_mach_riscv64) 872 xlen = 64; 873 else if (info->mach == bfd_mach_riscv32) 874 xlen = 32; 875 else if (info->section != NULL) 876 { 877 Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); 878 xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; 879 } 880 881 /* If arch has the Zfinx extension, replace FPR with GPR. */ 882 if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) 883 riscv_fpr_names = riscv_gpr_names; 884 else 885 riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi ? 886 riscv_fpr_names_abi : riscv_fpr_names_numeric; 887 888 for (; op->name; op++) 889 { 890 /* Ignore macro insns. */ 891 if (op->pinfo == INSN_MACRO) 892 continue; 893 /* Does the opcode match? */ 894 if (! (op->match_func) (op, word)) 895 continue; 896 /* Is this a pseudo-instruction and may we print it as such? */ 897 if (no_aliases && (op->pinfo & INSN_ALIAS)) 898 continue; 899 /* Is this instruction restricted to a certain value of XLEN? */ 900 if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) 901 continue; 902 /* Is this instruction supported by the current architecture? */ 903 if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) 904 continue; 905 906 /* It's a match. */ 907 (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, 908 "%s", op->name); 909 print_insn_args (op->args, word, memaddr, info); 910 911 /* Try to disassemble multi-instruction addressing sequences. */ 912 if (pd->to_print_addr) 913 { 914 info->target = pd->print_addr; 915 (*info->fprintf_styled_func) 916 (info->stream, dis_style_comment_start, " # "); 917 (*info->print_address_func) (info->target, info); 918 pd->to_print_addr = false; 919 } 920 921 /* Finish filling out insn_info fields. */ 922 switch (op->pinfo & INSN_TYPE) 923 { 924 case INSN_BRANCH: 925 info->insn_type = dis_branch; 926 break; 927 case INSN_CONDBRANCH: 928 info->insn_type = dis_condbranch; 929 break; 930 case INSN_JSR: 931 info->insn_type = dis_jsr; 932 break; 933 case INSN_DREF: 934 info->insn_type = dis_dref; 935 break; 936 default: 937 break; 938 } 939 940 if (op->pinfo & INSN_DATA_SIZE) 941 { 942 int size = ((op->pinfo & INSN_DATA_SIZE) 943 >> INSN_DATA_SIZE_SHIFT); 944 info->data_size = 1 << (size - 1); 945 } 946 947 return insnlen; 948 } 949 } 950 951 /* We did not find a match, so just print the instruction bits in 952 the shape of an assembler .insn directive. */ 953 info->insn_type = dis_noninsn; 954 (*info->fprintf_styled_func) 955 (info->stream, dis_style_assembler_directive, ".insn"); 956 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t"); 957 (*info->fprintf_styled_func) (info->stream, dis_style_immediate, 958 "%d", insnlen); 959 (*info->fprintf_styled_func) (info->stream, dis_style_text, ", "); 960 (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x"); 961 for (i = insnlen, printed = false; i >= 2; ) 962 { 963 i -= 2; 964 word = bfd_get_bits (packet + i, 16, false); 965 if (!word && !printed) 966 continue; 967 968 (*info->fprintf_styled_func) (info->stream, dis_style_immediate, 969 "%04x", (unsigned int) word); 970 printed = true; 971 } 972 973 return insnlen; 974 } 975 976 /* If we find the suitable mapping symbol update the STATE. 977 Otherwise, do nothing. */ 978 979 static void 980 riscv_update_map_state (int n, 981 enum riscv_seg_mstate *state, 982 struct disassemble_info *info) 983 { 984 const char *name; 985 986 /* If the symbol is in a different section, ignore it. */ 987 if (info->section != NULL 988 && info->section != info->symtab[n]->section) 989 return; 990 991 name = bfd_asymbol_name(info->symtab[n]); 992 if (strcmp (name, "$x") == 0) 993 *state = MAP_INSN; 994 else if (strcmp (name, "$d") == 0) 995 *state = MAP_DATA; 996 else if (strncmp (name, "$xrv", 4) == 0) 997 { 998 *state = MAP_INSN; 999 riscv_release_subset_list (&riscv_subsets); 1000 1001 /* ISA mapping string may be numbered, suffixed with '.n'. Do not 1002 consider this as part of the ISA string. */ 1003 char *suffix = strchr (name, '.'); 1004 if (suffix) 1005 { 1006 int suffix_index = (int)(suffix - name); 1007 char *name_substr = xmalloc (suffix_index + 1); 1008 strncpy (name_substr, name, suffix_index); 1009 name_substr[suffix_index] = '\0'; 1010 riscv_parse_subset (&riscv_rps_dis, name_substr + 2); 1011 free (name_substr); 1012 } 1013 else 1014 riscv_parse_subset (&riscv_rps_dis, name + 2); 1015 } 1016 } 1017 1018 /* Return true if we find the suitable mapping symbol. 1019 Otherwise, return false. */ 1020 1021 static bool 1022 riscv_is_valid_mapping_symbol (int n, 1023 struct disassemble_info *info) 1024 { 1025 const char *name; 1026 1027 /* If the symbol is in a different section, ignore it. */ 1028 if (info->section != NULL 1029 && info->section != info->symtab[n]->section) 1030 return false; 1031 1032 name = bfd_asymbol_name(info->symtab[n]); 1033 return riscv_elf_is_mapping_symbols (name); 1034 } 1035 1036 /* Check the sorted symbol table (sorted by the symbol value), find the 1037 suitable mapping symbols. */ 1038 1039 static enum riscv_seg_mstate 1040 riscv_search_mapping_symbol (bfd_vma memaddr, 1041 struct disassemble_info *info) 1042 { 1043 enum riscv_seg_mstate mstate; 1044 bool from_last_map_symbol; 1045 bool found = false; 1046 int symbol = -1; 1047 int n; 1048 1049 /* Return the last map state if the address is still within the range of the 1050 last mapping symbol. */ 1051 if (last_map_section == info->section 1052 && (memaddr < last_map_symbol_boundary)) 1053 return last_map_state; 1054 1055 last_map_section = info->section; 1056 1057 /* Decide whether to print the data or instruction by default, in case 1058 we can not find the corresponding mapping symbols. */ 1059 mstate = MAP_DATA; 1060 if ((info->section 1061 && info->section->flags & SEC_CODE) 1062 || !info->section) 1063 mstate = MAP_INSN; 1064 1065 if (info->symtab_size == 0 1066 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 1067 return mstate; 1068 1069 /* Reset the last_map_symbol if we start to dump a new section. */ 1070 if (memaddr <= 0) 1071 last_map_symbol = -1; 1072 1073 /* If the last stop offset is different from the current one, then 1074 don't use the last_map_symbol to search. We usually reset the 1075 info->stop_offset when handling a new section. */ 1076 from_last_map_symbol = (last_map_symbol >= 0 1077 && info->stop_offset == last_stop_offset); 1078 1079 /* Start scanning from wherever we finished last time, or the start 1080 of the function. */ 1081 n = from_last_map_symbol ? last_map_symbol : info->symtab_pos + 1; 1082 1083 /* Find the suitable mapping symbol to dump. */ 1084 for (; n < info->symtab_size; n++) 1085 { 1086 bfd_vma addr = bfd_asymbol_value (info->symtab[n]); 1087 /* We have searched all possible symbols in the range. */ 1088 if (addr > memaddr) 1089 break; 1090 if (riscv_is_valid_mapping_symbol (n, info)) 1091 { 1092 symbol = n; 1093 found = true; 1094 /* Do not stop searching, in case there are some mapping 1095 symbols have the same value, but have different names. 1096 Use the last one. */ 1097 } 1098 } 1099 1100 /* We can not find the suitable mapping symbol above. Therefore, we 1101 look forwards and try to find it again, but don't go past the start 1102 of the section. Otherwise a data section without mapping symbols 1103 can pick up a text mapping symbol of a preceeding section. */ 1104 if (!found) 1105 { 1106 n = from_last_map_symbol ? last_map_symbol : info->symtab_pos; 1107 1108 for (; n >= 0; n--) 1109 { 1110 bfd_vma addr = bfd_asymbol_value (info->symtab[n]); 1111 /* We have searched all possible symbols in the range. */ 1112 if (addr < (info->section ? info->section->vma : 0)) 1113 break; 1114 /* Stop searching once we find the closed mapping symbol. */ 1115 if (riscv_is_valid_mapping_symbol (n, info)) 1116 { 1117 symbol = n; 1118 found = true; 1119 break; 1120 } 1121 } 1122 } 1123 1124 if (found) 1125 { 1126 riscv_update_map_state (symbol, &mstate, info); 1127 1128 /* Find the next mapping symbol to determine the boundary of this mapping 1129 symbol. */ 1130 1131 bool found_next = false; 1132 /* Try to found next mapping symbol. */ 1133 for (n = symbol + 1; n < info->symtab_size; n++) 1134 { 1135 if (info->symtab[symbol]->section != info->symtab[n]->section) 1136 continue; 1137 1138 bfd_vma addr = bfd_asymbol_value (info->symtab[n]); 1139 const char *sym_name = bfd_asymbol_name(info->symtab[n]); 1140 if (sym_name[0] == '$' && (sym_name[1] == 'x' || sym_name[1] == 'd')) 1141 { 1142 /* The next mapping symbol has been found, and it represents the 1143 boundary of this mapping symbol. */ 1144 found_next = true; 1145 last_map_symbol_boundary = addr; 1146 break; 1147 } 1148 } 1149 1150 /* No further mapping symbol has been found, indicating that the boundary 1151 of the current mapping symbol is the end of this section. */ 1152 if (!found_next) 1153 last_map_symbol_boundary = info->section->vma + info->section->size; 1154 } 1155 1156 /* Save the information for next use. */ 1157 last_map_symbol = symbol; 1158 last_stop_offset = info->stop_offset; 1159 1160 return mstate; 1161 } 1162 1163 /* Decide which data size we should print. */ 1164 1165 static bfd_vma 1166 riscv_data_length (bfd_vma memaddr, 1167 disassemble_info *info) 1168 { 1169 bfd_vma length; 1170 bool found = false; 1171 1172 length = 4; 1173 if (info->symtab_size != 0 1174 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour 1175 && last_map_symbol >= 0) 1176 { 1177 int n; 1178 enum riscv_seg_mstate m = MAP_NONE; 1179 for (n = last_map_symbol + 1; n < info->symtab_size; n++) 1180 { 1181 bfd_vma addr = bfd_asymbol_value (info->symtab[n]); 1182 if (addr > memaddr 1183 && riscv_is_valid_mapping_symbol (n, info)) 1184 { 1185 if (addr - memaddr < length) 1186 length = addr - memaddr; 1187 found = true; 1188 riscv_update_map_state (n, &m, info); 1189 break; 1190 } 1191 } 1192 } 1193 if (!found) 1194 { 1195 /* Do not set the length which exceeds the section size. */ 1196 bfd_vma offset = info->section->vma + info->section->size; 1197 offset -= memaddr; 1198 length = (offset < length) ? offset : length; 1199 } 1200 length = length == 3 ? 2 : length; 1201 return length; 1202 } 1203 1204 /* Dump the data contents. */ 1205 1206 static int 1207 riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED, 1208 insn_t data, 1209 const bfd_byte *packet ATTRIBUTE_UNUSED, 1210 disassemble_info *info) 1211 { 1212 info->display_endian = info->endian; 1213 1214 switch (info->bytes_per_chunk) 1215 { 1216 case 1: 1217 info->bytes_per_line = 6; 1218 (*info->fprintf_styled_func) 1219 (info->stream, dis_style_assembler_directive, ".byte"); 1220 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t"); 1221 (*info->fprintf_styled_func) (info->stream, dis_style_immediate, 1222 "0x%02x", (unsigned)data); 1223 break; 1224 case 2: 1225 info->bytes_per_line = 8; 1226 (*info->fprintf_styled_func) 1227 (info->stream, dis_style_assembler_directive, ".short"); 1228 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t"); 1229 (*info->fprintf_styled_func) 1230 (info->stream, dis_style_immediate, "0x%04x", (unsigned) data); 1231 break; 1232 case 4: 1233 info->bytes_per_line = 8; 1234 (*info->fprintf_styled_func) 1235 (info->stream, dis_style_assembler_directive, ".word"); 1236 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t"); 1237 (*info->fprintf_styled_func) 1238 (info->stream, dis_style_immediate, "0x%08lx", 1239 (unsigned long) data); 1240 break; 1241 case 8: 1242 info->bytes_per_line = 8; 1243 (*info->fprintf_styled_func) 1244 (info->stream, dis_style_assembler_directive, ".dword"); 1245 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t"); 1246 (*info->fprintf_styled_func) 1247 (info->stream, dis_style_immediate, "0x%016llx", 1248 (unsigned long long) data); 1249 break; 1250 default: 1251 abort (); 1252 } 1253 return info->bytes_per_chunk; 1254 } 1255 1256 static bool 1257 riscv_init_disasm_info (struct disassemble_info *info) 1258 { 1259 int i; 1260 1261 struct riscv_private_data *pd = 1262 xcalloc (1, sizeof (struct riscv_private_data)); 1263 pd->gp = 0; 1264 pd->print_addr = 0; 1265 for (i = 0; i < (int) ARRAY_SIZE (pd->hi_addr); i++) 1266 pd->hi_addr[i] = -1; 1267 pd->to_print_addr = false; 1268 pd->has_gp = false; 1269 1270 for (i = 0; i < info->symtab_size; i++) 1271 { 1272 asymbol *sym = info->symtab[i]; 1273 if (strcmp (bfd_asymbol_name (sym), RISCV_GP_SYMBOL) == 0) 1274 { 1275 pd->gp = bfd_asymbol_value (sym); 1276 pd->has_gp = true; 1277 } 1278 } 1279 1280 info->private_data = pd; 1281 return true; 1282 } 1283 1284 int 1285 print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) 1286 { 1287 bfd_byte packet[RISCV_MAX_INSN_LEN]; 1288 insn_t insn = 0; 1289 bfd_vma dump_size; 1290 int status; 1291 enum riscv_seg_mstate mstate; 1292 int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *, 1293 struct disassemble_info *); 1294 1295 if (info->disassembler_options != NULL) 1296 { 1297 parse_riscv_dis_options (info->disassembler_options); 1298 /* Avoid repeatedly parsing the options. */ 1299 info->disassembler_options = NULL; 1300 } 1301 else if (riscv_gpr_names == NULL) 1302 set_default_riscv_dis_options (); 1303 1304 if (info->private_data == NULL && !riscv_init_disasm_info (info)) 1305 return -1; 1306 1307 mstate = riscv_search_mapping_symbol (memaddr, info); 1308 /* Save the last mapping state. */ 1309 last_map_state = mstate; 1310 1311 /* Set the size to dump. */ 1312 if (mstate == MAP_DATA 1313 && (info->flags & DISASSEMBLE_DATA) == 0) 1314 { 1315 dump_size = riscv_data_length (memaddr, info); 1316 info->bytes_per_chunk = dump_size; 1317 riscv_disassembler = riscv_disassemble_data; 1318 } 1319 else 1320 { 1321 /* Get the first 2-bytes to check the lenghth of instruction. */ 1322 status = (*info->read_memory_func) (memaddr, packet, 2, info); 1323 if (status != 0) 1324 { 1325 (*info->memory_error_func) (status, memaddr, info); 1326 return -1; 1327 } 1328 insn = (insn_t) bfd_getl16 (packet); 1329 dump_size = riscv_insn_length (insn); 1330 riscv_disassembler = riscv_disassemble_insn; 1331 } 1332 1333 /* Fetch the instruction to dump. */ 1334 status = (*info->read_memory_func) (memaddr, packet, dump_size, info); 1335 if (status != 0) 1336 { 1337 (*info->memory_error_func) (status, memaddr, info); 1338 return -1; 1339 } 1340 insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false); 1341 1342 return (*riscv_disassembler) (memaddr, insn, packet, info); 1343 } 1344 1345 disassembler_ftype 1346 riscv_get_disassembler (bfd *abfd) 1347 { 1348 const char *default_arch = "rv64gc"; 1349 1350 if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour) 1351 { 1352 const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section; 1353 if (bfd_get_section_by_name (abfd, sec_name) != NULL) 1354 { 1355 obj_attribute *attr = elf_known_obj_attributes_proc (abfd); 1356 unsigned int Tag_a = Tag_RISCV_priv_spec; 1357 unsigned int Tag_b = Tag_RISCV_priv_spec_minor; 1358 unsigned int Tag_c = Tag_RISCV_priv_spec_revision; 1359 riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i, 1360 attr[Tag_b].i, 1361 attr[Tag_c].i, 1362 &default_priv_spec); 1363 default_arch = attr[Tag_RISCV_arch].s; 1364 } 1365 } 1366 1367 riscv_release_subset_list (&riscv_subsets); 1368 riscv_parse_subset (&riscv_rps_dis, default_arch); 1369 return print_insn_riscv; 1370 } 1371 1372 /* Prevent use of the fake labels that are generated as part of the DWARF 1373 and for relaxable relocations in the assembler. */ 1374 1375 bool 1376 riscv_symbol_is_valid (asymbol * sym, 1377 struct disassemble_info * info ATTRIBUTE_UNUSED) 1378 { 1379 const char * name; 1380 1381 if (sym == NULL) 1382 return false; 1383 1384 name = bfd_asymbol_name (sym); 1385 1386 return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0 1387 && !riscv_elf_is_mapping_symbols (name)); 1388 } 1389 1390 1392 /* Indices into option argument vector for options accepting an argument. 1393 Use RISCV_OPTION_ARG_NONE for options accepting no argument. */ 1394 1395 typedef enum 1396 { 1397 RISCV_OPTION_ARG_NONE = -1, 1398 RISCV_OPTION_ARG_PRIV_SPEC, 1399 1400 RISCV_OPTION_ARG_COUNT 1401 } riscv_option_arg_t; 1402 1403 /* Valid RISCV disassembler options. */ 1404 1405 static struct 1406 { 1407 const char *name; 1408 const char *description; 1409 riscv_option_arg_t arg; 1410 } riscv_options[] = 1411 { 1412 { "numeric", 1413 N_("Print numeric register names, rather than ABI names."), 1414 RISCV_OPTION_ARG_NONE }, 1415 { "no-aliases", 1416 N_("Disassemble only into canonical instructions."), 1417 RISCV_OPTION_ARG_NONE }, 1418 { "priv-spec=", 1419 N_("Print the CSR according to the chosen privilege spec."), 1420 RISCV_OPTION_ARG_PRIV_SPEC } 1421 }; 1422 1423 /* Build the structure representing valid RISCV disassembler options. 1424 This is done dynamically for maintenance ease purpose; a static 1425 initializer would be unreadable. */ 1426 1427 const disasm_options_and_args_t * 1428 disassembler_options_riscv (void) 1429 { 1430 static disasm_options_and_args_t *opts_and_args; 1431 1432 if (opts_and_args == NULL) 1433 { 1434 size_t num_options = ARRAY_SIZE (riscv_options); 1435 size_t num_args = RISCV_OPTION_ARG_COUNT; 1436 disasm_option_arg_t *args; 1437 disasm_options_t *opts; 1438 size_t i, priv_spec_count; 1439 1440 args = XNEWVEC (disasm_option_arg_t, num_args + 1); 1441 1442 args[RISCV_OPTION_ARG_PRIV_SPEC].name = "SPEC"; 1443 priv_spec_count = PRIV_SPEC_CLASS_DRAFT - PRIV_SPEC_CLASS_NONE - 1; 1444 args[RISCV_OPTION_ARG_PRIV_SPEC].values 1445 = XNEWVEC (const char *, priv_spec_count + 1); 1446 for (i = 0; i < priv_spec_count; i++) 1447 args[RISCV_OPTION_ARG_PRIV_SPEC].values[i] 1448 = riscv_priv_specs[i].name; 1449 /* The array we return must be NULL terminated. */ 1450 args[RISCV_OPTION_ARG_PRIV_SPEC].values[i] = NULL; 1451 1452 /* The array we return must be NULL terminated. */ 1453 args[num_args].name = NULL; 1454 args[num_args].values = NULL; 1455 1456 opts_and_args = XNEW (disasm_options_and_args_t); 1457 opts_and_args->args = args; 1458 1459 opts = &opts_and_args->options; 1460 opts->name = XNEWVEC (const char *, num_options + 1); 1461 opts->description = XNEWVEC (const char *, num_options + 1); 1462 opts->arg = XNEWVEC (const disasm_option_arg_t *, num_options + 1); 1463 for (i = 0; i < num_options; i++) 1464 { 1465 opts->name[i] = riscv_options[i].name; 1466 opts->description[i] = _(riscv_options[i].description); 1467 if (riscv_options[i].arg != RISCV_OPTION_ARG_NONE) 1468 opts->arg[i] = &args[riscv_options[i].arg]; 1469 else 1470 opts->arg[i] = NULL; 1471 } 1472 /* The array we return must be NULL terminated. */ 1473 opts->name[i] = NULL; 1474 opts->description[i] = NULL; 1475 opts->arg[i] = NULL; 1476 } 1477 1478 return opts_and_args; 1479 } 1480 1481 void 1482 print_riscv_disassembler_options (FILE *stream) 1483 { 1484 const disasm_options_and_args_t *opts_and_args; 1485 const disasm_option_arg_t *args; 1486 const disasm_options_t *opts; 1487 size_t max_len = 0; 1488 size_t i; 1489 size_t j; 1490 1491 opts_and_args = disassembler_options_riscv (); 1492 opts = &opts_and_args->options; 1493 args = opts_and_args->args; 1494 1495 fprintf (stream, _("\n\ 1496 The following RISC-V specific disassembler options are supported for use\n\ 1497 with the -M switch (multiple options should be separated by commas):\n")); 1498 fprintf (stream, "\n"); 1499 1500 /* Compute the length of the longest option name. */ 1501 for (i = 0; opts->name[i] != NULL; i++) 1502 { 1503 size_t len = strlen (opts->name[i]); 1504 1505 if (opts->arg[i] != NULL) 1506 len += strlen (opts->arg[i]->name); 1507 if (max_len < len) 1508 max_len = len; 1509 } 1510 1511 for (i = 0, max_len++; opts->name[i] != NULL; i++) 1512 { 1513 fprintf (stream, " %s", opts->name[i]); 1514 if (opts->arg[i] != NULL) 1515 fprintf (stream, "%s", opts->arg[i]->name); 1516 if (opts->description[i] != NULL) 1517 { 1518 size_t len = strlen (opts->name[i]); 1519 1520 if (opts->arg != NULL && opts->arg[i] != NULL) 1521 len += strlen (opts->arg[i]->name); 1522 fprintf (stream, "%*c %s", (int) (max_len - len), ' ', 1523 opts->description[i]); 1524 } 1525 fprintf (stream, "\n"); 1526 } 1527 1528 for (i = 0; args[i].name != NULL; i++) 1529 { 1530 if (args[i].values == NULL) 1531 continue; 1532 fprintf (stream, _("\n\ 1533 For the options above, the following values are supported for \"%s\":\n "), 1534 args[i].name); 1535 for (j = 0; args[i].values[j] != NULL; j++) 1536 fprintf (stream, " %s", args[i].values[j]); 1537 fprintf (stream, _("\n")); 1538 } 1539 1540 fprintf (stream, _("\n")); 1541 } 1542 1543 void disassemble_free_riscv (struct disassemble_info *info ATTRIBUTE_UNUSED) 1544 { 1545 riscv_release_subset_list (&riscv_subsets); 1546 } 1547
Indexes created Mon Mar 30 00:23:01 UTC 2026