s12z-opc.c revision 1.1.1.2
1 /* s12z-decode.c -- Freescale S12Z disassembly 2 Copyright (C) 2018-2020 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include <stdio.h> 23 #include <stdint.h> 24 #include <stdbool.h> 25 #include <assert.h> 26 27 #include "opcode/s12z.h" 28 29 #include "bfd.h" 30 31 #include "s12z-opc.h" 32 33 34 typedef int (*insn_bytes_f) (struct mem_read_abstraction_base *); 35 36 typedef int (*operands_f) (struct mem_read_abstraction_base *, 37 int *n_operands, struct operand **operand); 38 39 typedef enum optr (*discriminator_f) (struct mem_read_abstraction_base *, 40 enum optr hint); 41 42 enum OPR_MODE 43 { 44 OPR_IMMe4, 45 OPR_REG, 46 OPR_OFXYS, 47 OPR_XY_PRE_INC, 48 OPR_XY_POST_INC, 49 OPR_XY_PRE_DEC, 50 OPR_XY_POST_DEC, 51 OPR_S_PRE_DEC, 52 OPR_S_POST_INC, 53 OPR_REG_DIRECT, 54 OPR_REG_INDIRECT, 55 OPR_IDX_DIRECT, 56 OPR_IDX_INDIRECT, 57 OPR_EXT1, 58 OPR_IDX2_REG, 59 OPR_IDX3_DIRECT, 60 OPR_IDX3_INDIRECT, 61 62 OPR_EXT18, 63 OPR_IDX3_DIRECT_REG, 64 OPR_EXT3_DIRECT, 65 OPR_EXT3_INDIRECT 66 }; 67 68 struct opr_pb 69 { 70 uint8_t mask; 71 uint8_t value; 72 int n_operands; 73 enum OPR_MODE mode; 74 }; 75 76 static const struct opr_pb opr_pb[] = { 77 {0xF0, 0x70, 1, OPR_IMMe4}, 78 {0xF8, 0xB8, 1, OPR_REG}, 79 {0xC0, 0x40, 1, OPR_OFXYS}, 80 {0xEF, 0xE3, 1, OPR_XY_PRE_INC}, 81 {0xEF, 0xE7, 1, OPR_XY_POST_INC}, 82 {0xEF, 0xC3, 1, OPR_XY_PRE_DEC}, 83 {0xEF, 0xC7, 1, OPR_XY_POST_DEC}, 84 {0xFF, 0xFB, 1, OPR_S_PRE_DEC}, 85 {0xFF, 0xFF, 1, OPR_S_POST_INC}, 86 {0xC8, 0x88, 1, OPR_REG_DIRECT}, 87 {0xE8, 0xC8, 1, OPR_REG_INDIRECT}, 88 89 {0xCE, 0xC0, 2, OPR_IDX_DIRECT}, 90 {0xCE, 0xC4, 2, OPR_IDX_INDIRECT}, 91 {0xC0, 0x00, 2, OPR_EXT1}, 92 93 {0xC8, 0x80, 3, OPR_IDX2_REG}, 94 {0xFA, 0xF8, 3, OPR_EXT18}, 95 96 {0xCF, 0xC2, 4, OPR_IDX3_DIRECT}, 97 {0xCF, 0xC6, 4, OPR_IDX3_INDIRECT}, 98 99 {0xF8, 0xE8, 4, OPR_IDX3_DIRECT_REG}, 100 {0xFF, 0xFA, 4, OPR_EXT3_DIRECT}, 101 {0xFF, 0xFE, 4, OPR_EXT3_INDIRECT}, 102 }; 103 104 /* Return the number of bytes in a OPR operand, including the XB postbyte. 105 It does not include any preceeding opcodes. */ 106 static int 107 x_opr_n_bytes (struct mem_read_abstraction_base *mra, int offset) 108 { 109 bfd_byte xb; 110 int status = mra->read (mra, offset, 1, &xb); 111 if (status < 0) 112 return status; 113 114 size_t i; 115 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i) 116 { 117 const struct opr_pb *pb = opr_pb + i; 118 if ((xb & pb->mask) == pb->value) 119 { 120 return pb->n_operands; 121 } 122 } 123 124 return 1; 125 } 126 127 static int 128 opr_n_bytes_p1 (struct mem_read_abstraction_base *mra) 129 { 130 int n = x_opr_n_bytes (mra, 0); 131 if (n < 0) 132 return n; 133 return 1 + n; 134 } 135 136 static int 137 opr_n_bytes2 (struct mem_read_abstraction_base *mra) 138 { 139 int s = x_opr_n_bytes (mra, 0); 140 if (s < 0) 141 return s; 142 int n = x_opr_n_bytes (mra, s); 143 if (n < 0) 144 return n; 145 return s + n + 1; 146 } 147 148 enum BB_MODE 149 { 150 BB_REG_REG_REG, 151 BB_REG_REG_IMM, 152 BB_REG_OPR_REG, 153 BB_OPR_REG_REG, 154 BB_REG_OPR_IMM, 155 BB_OPR_REG_IMM 156 }; 157 158 struct opr_bb 159 { 160 uint8_t mask; 161 uint8_t value; 162 int n_operands; 163 bool opr; 164 enum BB_MODE mode; 165 }; 166 167 static const struct opr_bb bb_modes[] = 168 { 169 {0x60, 0x00, 2, false, BB_REG_REG_REG}, 170 {0x60, 0x20, 3, false, BB_REG_REG_IMM}, 171 {0x70, 0x40, 2, true, BB_REG_OPR_REG}, 172 {0x70, 0x50, 2, true, BB_OPR_REG_REG}, 173 {0x70, 0x60, 3, true, BB_REG_OPR_IMM}, 174 {0x70, 0x70, 3, true, BB_OPR_REG_IMM} 175 }; 176 177 static int 178 bfextins_n_bytes (struct mem_read_abstraction_base *mra) 179 { 180 bfd_byte bb; 181 int status = mra->read (mra, 0, 1, &bb); 182 if (status < 0) 183 return status; 184 185 size_t i; 186 const struct opr_bb *bbs = 0; 187 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i) 188 { 189 bbs = bb_modes + i; 190 if ((bb & bbs->mask) == bbs->value) 191 { 192 break; 193 } 194 } 195 196 int n = bbs->n_operands; 197 if (bbs->opr) 198 { 199 int x = x_opr_n_bytes (mra, n - 1); 200 if (x < 0) 201 return x; 202 n += x; 203 } 204 205 return n; 206 } 207 208 static int 209 single (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED) 210 { 211 return 1; 212 } 213 214 static int 215 two (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED) 216 { 217 return 2; 218 } 219 220 static int 221 three (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED) 222 { 223 return 3; 224 } 225 226 static int 227 four (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED) 228 { 229 return 4; 230 } 231 232 static int 233 five (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED) 234 { 235 return 5; 236 } 237 238 static int 239 pcrel_15bit (struct mem_read_abstraction_base *mra) 240 { 241 bfd_byte byte; 242 int status = mra->read (mra, 0, 1, &byte); 243 if (status < 0) 244 return status; 245 return (byte & 0x80) ? 3 : 2; 246 } 247 248 249 250 static int 252 xysp_reg_from_postbyte (uint8_t postbyte) 253 { 254 int reg = -1; 255 switch ((postbyte & 0x30) >> 4) 256 { 257 case 0: 258 reg = REG_X; 259 break; 260 case 1: 261 reg = REG_Y; 262 break; 263 case 2: 264 reg = REG_S; 265 break; 266 default: 267 reg = REG_P; 268 } 269 return reg; 270 } 271 272 static struct operand * 273 create_immediate_operand (int value) 274 { 275 struct immediate_operand *op = malloc (sizeof (*op)); 276 277 if (op != NULL) 278 { 279 op->parent.cl = OPND_CL_IMMEDIATE; 280 op->parent.osize = -1; 281 op->value = value; 282 } 283 return (struct operand *) op; 284 } 285 286 static struct operand * 287 create_bitfield_operand (int width, int offset) 288 { 289 struct bitfield_operand *op = malloc (sizeof (*op)); 290 291 if (op != NULL) 292 { 293 op->parent.cl = OPND_CL_BIT_FIELD; 294 op->parent.osize = -1; 295 op->width = width; 296 op->offset = offset; 297 } 298 return (struct operand *) op; 299 } 300 301 static struct operand * 302 create_register_operand_with_size (int reg, short osize) 303 { 304 struct register_operand *op = malloc (sizeof (*op)); 305 306 if (op != NULL) 307 { 308 op->parent.cl = OPND_CL_REGISTER; 309 op->parent.osize = osize; 310 op->reg = reg; 311 } 312 return (struct operand *) op; 313 } 314 315 static struct operand * 316 create_register_operand (int reg) 317 { 318 return create_register_operand_with_size (reg, -1); 319 } 320 321 static struct operand * 322 create_register_all_operand (void) 323 { 324 struct register_operand *op = malloc (sizeof (*op)); 325 326 if (op != NULL) 327 { 328 op->parent.cl = OPND_CL_REGISTER_ALL; 329 op->parent.osize = -1; 330 } 331 return (struct operand *) op; 332 } 333 334 static struct operand * 335 create_register_all16_operand (void) 336 { 337 struct register_operand *op = malloc (sizeof (*op)); 338 339 if (op != NULL) 340 { 341 op->parent.cl = OPND_CL_REGISTER_ALL16; 342 op->parent.osize = -1; 343 } 344 return (struct operand *) op; 345 } 346 347 348 static struct operand * 349 create_simple_memory_operand (bfd_vma addr, bfd_vma base, bool relative) 350 { 351 struct simple_memory_operand *op; 352 353 assert (relative || base == 0); 354 op = malloc (sizeof (*op)); 355 if (op != NULL) 356 { 357 op->parent.cl = OPND_CL_SIMPLE_MEMORY; 358 op->parent.osize = -1; 359 op->addr = addr; 360 op->base = base; 361 op->relative = relative; 362 } 363 return (struct operand *) op; 364 } 365 366 static struct operand * 367 create_memory_operand (bool indirect, int base, int n_regs, int reg0, int reg1) 368 { 369 struct memory_operand *op = malloc (sizeof (*op)); 370 371 if (op != NULL) 372 { 373 op->parent.cl = OPND_CL_MEMORY; 374 op->parent.osize = -1; 375 op->indirect = indirect; 376 op->base_offset = base; 377 op->mutation = OPND_RM_NONE; 378 op->n_regs = n_regs; 379 op->regs[0] = reg0; 380 op->regs[1] = reg1; 381 } 382 return (struct operand *) op; 383 } 384 385 static struct operand * 386 create_memory_auto_operand (enum op_reg_mutation mutation, int reg) 387 { 388 struct memory_operand *op = malloc (sizeof (*op)); 389 390 if (op != NULL) 391 { 392 op->parent.cl = OPND_CL_MEMORY; 393 op->parent.osize = -1; 394 op->indirect = false; 395 op->base_offset = 0; 396 op->mutation = mutation; 397 op->n_regs = 1; 398 op->regs[0] = reg; 399 op->regs[1] = -1; 400 } 401 return (struct operand *) op; 402 } 403 404 405 407 static int 408 z_ext24_decode (struct mem_read_abstraction_base *mra, int *n_operands, 409 struct operand **operand) 410 { 411 struct operand *op; 412 uint8_t buffer[3]; 413 int status = mra->read (mra, 0, 3, buffer); 414 if (status < 0) 415 return status; 416 417 int i; 418 uint32_t addr = 0; 419 for (i = 0; i < 3; ++i) 420 { 421 addr <<= 8; 422 addr |= buffer[i]; 423 } 424 425 op = create_simple_memory_operand (addr, 0, false); 426 if (op == NULL) 427 return -1; 428 operand[(*n_operands)++] = op; 429 return 0; 430 } 431 432 433 static int 434 z_decode_signed_value (struct mem_read_abstraction_base *mra, int offset, 435 short size, uint32_t *result) 436 { 437 assert (size >0); 438 assert (size <= 4); 439 bfd_byte buffer[4]; 440 int status = mra->read (mra, offset, size, buffer); 441 if (status < 0) 442 return status; 443 444 int i; 445 uint32_t value = 0; 446 for (i = 0; i < size; ++i) 447 value = (value << 8) | buffer[i]; 448 449 if (buffer[0] & 0x80) 450 { 451 /* Deal with negative values */ 452 value -= 1u << (size * 4) << (size * 4); 453 } 454 *result = value; 455 return 0; 456 } 457 458 static int 459 decode_signed_value (struct mem_read_abstraction_base *mra, short size, 460 uint32_t *result) 461 { 462 return z_decode_signed_value (mra, 0, size, result); 463 } 464 465 static int 466 x_imm1 (struct mem_read_abstraction_base *mra, 467 int offset, 468 int *n_operands, struct operand **operand) 469 { 470 struct operand *op; 471 bfd_byte byte; 472 int status = mra->read (mra, offset, 1, &byte); 473 if (status < 0) 474 return status; 475 476 op = create_immediate_operand (byte); 477 if (op == NULL) 478 return -1; 479 operand[(*n_operands)++] = op; 480 return 0; 481 } 482 483 /* An eight bit immediate operand. */ 484 static int 485 imm1_decode (struct mem_read_abstraction_base *mra, 486 int *n_operands, struct operand **operand) 487 { 488 return x_imm1 (mra, 0, n_operands, operand); 489 } 490 491 static int 492 trap_decode (struct mem_read_abstraction_base *mra, 493 int *n_operands, struct operand **operand) 494 { 495 return x_imm1 (mra, -1, n_operands, operand); 496 } 497 498 499 static struct operand * 500 x_opr_decode_with_size (struct mem_read_abstraction_base *mra, int offset, 501 short osize) 502 { 503 bfd_byte postbyte; 504 int status = mra->read (mra, offset, 1, &postbyte); 505 if (status < 0) 506 return NULL; 507 offset++; 508 509 enum OPR_MODE mode = -1; 510 size_t i; 511 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i) 512 { 513 const struct opr_pb *pb = opr_pb + i; 514 if ((postbyte & pb->mask) == pb->value) 515 { 516 mode = pb->mode; 517 break; 518 } 519 } 520 521 struct operand *operand = NULL; 522 switch (mode) 523 { 524 case OPR_IMMe4: 525 { 526 int n; 527 uint8_t x = (postbyte & 0x0F); 528 if (x == 0) 529 n = -1; 530 else 531 n = x; 532 533 operand = create_immediate_operand (n); 534 break; 535 } 536 case OPR_REG: 537 { 538 uint8_t x = (postbyte & 0x07); 539 operand = create_register_operand (x); 540 break; 541 } 542 case OPR_OFXYS: 543 { 544 operand = create_memory_operand (false, postbyte & 0x0F, 1, 545 xysp_reg_from_postbyte (postbyte), -1); 546 break; 547 } 548 case OPR_REG_DIRECT: 549 { 550 operand = create_memory_operand (false, 0, 2, postbyte & 0x07, 551 xysp_reg_from_postbyte (postbyte)); 552 break; 553 } 554 case OPR_REG_INDIRECT: 555 { 556 operand = create_memory_operand (true, 0, 2, postbyte & 0x07, 557 (postbyte & 0x10) ? REG_Y : REG_X); 558 break; 559 } 560 561 case OPR_IDX_INDIRECT: 562 { 563 uint8_t x1; 564 status = mra->read (mra, offset, 1, &x1); 565 if (status < 0) 566 return NULL; 567 int idx = x1; 568 569 if (postbyte & 0x01) 570 { 571 /* Deal with negative values */ 572 idx -= 0x1UL << 8; 573 } 574 575 operand = create_memory_operand (true, idx, 1, 576 xysp_reg_from_postbyte (postbyte), -1); 577 break; 578 } 579 580 case OPR_IDX3_DIRECT: 581 { 582 uint8_t x[3]; 583 status = mra->read (mra, offset, 3, x); 584 if (status < 0) 585 return NULL; 586 int idx = x[0] << 16 | x[1] << 8 | x[2]; 587 588 if (x[0] & 0x80) 589 { 590 /* Deal with negative values */ 591 idx -= 0x1UL << 24; 592 } 593 594 operand = create_memory_operand (false, idx, 1, 595 xysp_reg_from_postbyte (postbyte), -1); 596 break; 597 } 598 599 case OPR_IDX3_DIRECT_REG: 600 { 601 uint8_t x[3]; 602 status = mra->read (mra, offset, 3, x); 603 if (status < 0) 604 return NULL; 605 int idx = x[0] << 16 | x[1] << 8 | x[2]; 606 607 if (x[0] & 0x80) 608 { 609 /* Deal with negative values */ 610 idx -= 0x1UL << 24; 611 } 612 613 operand = create_memory_operand (false, idx, 1, postbyte & 0x07, -1); 614 break; 615 } 616 617 case OPR_IDX3_INDIRECT: 618 { 619 uint8_t x[3]; 620 status = mra->read (mra, offset, 3, x); 621 if (status < 0) 622 return NULL; 623 int idx = x[0] << 16 | x[1] << 8 | x[2]; 624 625 if (x[0] & 0x80) 626 { 627 /* Deal with negative values */ 628 idx -= 0x1UL << 24; 629 } 630 631 operand = create_memory_operand (true, idx, 1, 632 xysp_reg_from_postbyte (postbyte), -1); 633 break; 634 } 635 636 case OPR_IDX_DIRECT: 637 { 638 uint8_t x1; 639 status = mra->read (mra, offset, 1, &x1); 640 if (status < 0) 641 return NULL; 642 int idx = x1; 643 644 if (postbyte & 0x01) 645 { 646 /* Deal with negative values */ 647 idx -= 0x1UL << 8; 648 } 649 650 operand = create_memory_operand (false, idx, 1, 651 xysp_reg_from_postbyte (postbyte), -1); 652 break; 653 } 654 655 case OPR_IDX2_REG: 656 { 657 uint8_t x[2]; 658 status = mra->read (mra, offset, 2, x); 659 if (status < 0) 660 return NULL; 661 uint32_t idx = x[1] | x[0] << 8 ; 662 idx |= (postbyte & 0x30) << 12; 663 664 operand = create_memory_operand (false, idx, 1, postbyte & 0x07, -1); 665 break; 666 } 667 668 case OPR_XY_PRE_INC: 669 { 670 operand = create_memory_auto_operand (OPND_RM_PRE_INC, 671 (postbyte & 0x10) ? REG_Y: REG_X); 672 break; 673 } 674 case OPR_XY_POST_INC: 675 { 676 operand = create_memory_auto_operand (OPND_RM_POST_INC, 677 (postbyte & 0x10) ? REG_Y: REG_X); 678 break; 679 } 680 case OPR_XY_PRE_DEC: 681 { 682 operand = create_memory_auto_operand (OPND_RM_PRE_DEC, 683 (postbyte & 0x10) ? REG_Y: REG_X); 684 break; 685 } 686 case OPR_XY_POST_DEC: 687 { 688 operand = create_memory_auto_operand (OPND_RM_POST_DEC, 689 (postbyte & 0x10) ? REG_Y: REG_X); 690 break; 691 } 692 case OPR_S_PRE_DEC: 693 { 694 operand = create_memory_auto_operand (OPND_RM_PRE_DEC, REG_S); 695 break; 696 } 697 case OPR_S_POST_INC: 698 { 699 operand = create_memory_auto_operand (OPND_RM_POST_INC, REG_S); 700 break; 701 } 702 703 case OPR_EXT18: 704 { 705 const size_t size = 2; 706 bfd_byte buffer[4]; 707 status = mra->read (mra, offset, size, buffer); 708 if (status < 0) 709 return NULL; 710 711 uint32_t ext18 = 0; 712 for (i = 0; i < size; ++i) 713 { 714 ext18 <<= 8; 715 ext18 |= buffer[i]; 716 } 717 718 ext18 |= (postbyte & 0x01) << 16; 719 ext18 |= (postbyte & 0x04) << 15; 720 721 operand = create_simple_memory_operand (ext18, 0, false); 722 break; 723 } 724 725 case OPR_EXT1: 726 { 727 uint8_t x1 = 0; 728 status = mra->read (mra, offset, 1, &x1); 729 if (status < 0) 730 return NULL; 731 int16_t addr; 732 addr = x1; 733 addr |= (postbyte & 0x3f) << 8; 734 735 operand = create_simple_memory_operand (addr, 0, false); 736 break; 737 } 738 739 case OPR_EXT3_DIRECT: 740 { 741 const size_t size = 3; 742 bfd_byte buffer[4]; 743 status = mra->read (mra, offset, size, buffer); 744 if (status < 0) 745 return NULL; 746 747 uint32_t ext24 = 0; 748 for (i = 0; i < size; ++i) 749 { 750 ext24 |= buffer[i] << (8 * (size - i - 1)); 751 } 752 753 operand = create_simple_memory_operand (ext24, 0, false); 754 break; 755 } 756 757 case OPR_EXT3_INDIRECT: 758 { 759 const size_t size = 3; 760 bfd_byte buffer[4]; 761 status = mra->read (mra, offset, size, buffer); 762 if (status < 0) 763 return NULL; 764 765 uint32_t ext24 = 0; 766 for (i = 0; i < size; ++i) 767 { 768 ext24 |= buffer[i] << (8 * (size - i - 1)); 769 } 770 771 operand = create_memory_operand (true, ext24, 0, -1, -1); 772 break; 773 } 774 775 default: 776 printf ("Unknown OPR mode #0x%x (%d)", postbyte, mode); 777 abort (); 778 } 779 780 if (operand != NULL) 781 operand->osize = osize; 782 783 return operand; 784 } 785 786 static struct operand * 787 x_opr_decode (struct mem_read_abstraction_base *mra, int offset) 788 { 789 return x_opr_decode_with_size (mra, offset, -1); 790 } 791 792 static int 793 z_opr_decode (struct mem_read_abstraction_base *mra, 794 int *n_operands, struct operand **operand) 795 { 796 struct operand *op = x_opr_decode (mra, 0); 797 if (op == NULL) 798 return -1; 799 operand[(*n_operands)++] = op; 800 return 0; 801 } 802 803 static int 804 z_opr_decode2 (struct mem_read_abstraction_base *mra, 805 int *n_operands, struct operand **operand) 806 { 807 int n = x_opr_n_bytes (mra, 0); 808 if (n < 0) 809 return n; 810 struct operand *op = x_opr_decode (mra, 0); 811 if (op == NULL) 812 return -1; 813 operand[(*n_operands)++] = op; 814 op = x_opr_decode (mra, n); 815 if (op == NULL) 816 return -1; 817 operand[(*n_operands)++] = op; 818 return 0; 819 } 820 821 static int 822 imm1234 (struct mem_read_abstraction_base *mra, int base, 823 int *n_operands, struct operand **operand) 824 { 825 struct operand *op; 826 bfd_byte opcode; 827 int status = mra->read (mra, -1, 1, &opcode); 828 if (status < 0) 829 return status; 830 831 opcode -= base; 832 833 int size = registers[opcode & 0xF].bytes; 834 835 uint32_t imm; 836 if (decode_signed_value (mra, size, &imm) < 0) 837 return -1; 838 839 op = create_immediate_operand (imm); 840 if (op == NULL) 841 return -1; 842 operand[(*n_operands)++] = op; 843 return 0; 844 } 845 846 847 /* Special case of LD and CMP with register S and IMM operand */ 848 static int 849 reg_s_imm (struct mem_read_abstraction_base *mra, int *n_operands, 850 struct operand **operand) 851 { 852 struct operand *op; 853 854 op = create_register_operand (REG_S); 855 if (op == NULL) 856 return -1; 857 operand[(*n_operands)++] = op; 858 859 uint32_t imm; 860 if (decode_signed_value (mra, 3, &imm) < 0) 861 return -1; 862 op = create_immediate_operand (imm); 863 if (op == NULL) 864 return -1; 865 operand[(*n_operands)++] = op; 866 return 0; 867 } 868 869 /* Special case of LD, CMP and ST with register S and OPR operand */ 870 static int 871 reg_s_opr (struct mem_read_abstraction_base *mra, int *n_operands, 872 struct operand **operand) 873 { 874 struct operand *op; 875 876 op = create_register_operand (REG_S); 877 if (op == NULL) 878 return -1; 879 operand[(*n_operands)++] = op; 880 op = x_opr_decode (mra, 0); 881 if (op == NULL) 882 return -1; 883 operand[(*n_operands)++] = op; 884 return 0; 885 } 886 887 static int 888 z_imm1234_8base (struct mem_read_abstraction_base *mra, int *n_operands, 889 struct operand **operand) 890 { 891 return imm1234 (mra, 8, n_operands, operand); 892 } 893 894 static int 895 z_imm1234_0base (struct mem_read_abstraction_base *mra, int *n_operands, 896 struct operand **operand) 897 { 898 return imm1234 (mra, 0, n_operands, operand); 899 } 900 901 902 static int 903 z_tfr (struct mem_read_abstraction_base *mra, int *n_operands, 904 struct operand **operand) 905 { 906 struct operand *op; 907 bfd_byte byte; 908 int status = mra->read (mra, 0, 1, &byte); 909 if (status < 0) 910 return status; 911 912 op = create_register_operand (byte >> 4); 913 if (op == NULL) 914 return -1; 915 operand[(*n_operands)++] = op; 916 op = create_register_operand (byte & 0x0F); 917 if (op == NULL) 918 return -1; 919 operand[(*n_operands)++] = op; 920 return 0; 921 } 922 923 static int 924 z_reg (struct mem_read_abstraction_base *mra, int *n_operands, 925 struct operand **operand) 926 { 927 struct operand *op; 928 bfd_byte byte; 929 int status = mra->read (mra, -1, 1, &byte); 930 if (status < 0) 931 return status; 932 933 op = create_register_operand (byte & 0x07); 934 if (op == NULL) 935 return -1; 936 operand[(*n_operands)++] = op; 937 return 0; 938 } 939 940 941 static int 942 reg_xy (struct mem_read_abstraction_base *mra, 943 int *n_operands, struct operand **operand) 944 { 945 struct operand *op; 946 bfd_byte byte; 947 int status = mra->read (mra, -1, 1, &byte); 948 if (status < 0) 949 return status; 950 951 op = create_register_operand ((byte & 0x01) ? REG_Y : REG_X); 952 if (op == NULL) 953 return -1; 954 operand[(*n_operands)++] = op; 955 return 0; 956 } 957 958 static int 959 lea_reg_xys_opr (struct mem_read_abstraction_base *mra, 960 int *n_operands, struct operand **operand) 961 { 962 struct operand *op; 963 bfd_byte byte; 964 int status = mra->read (mra, -1, 1, &byte); 965 if (status < 0) 966 return status; 967 968 int reg_xys = -1; 969 switch (byte & 0x03) 970 { 971 case 0x00: 972 reg_xys = REG_X; 973 break; 974 case 0x01: 975 reg_xys = REG_Y; 976 break; 977 case 0x02: 978 reg_xys = REG_S; 979 break; 980 } 981 982 op = create_register_operand (reg_xys); 983 if (op == NULL) 984 return -1; 985 operand[(*n_operands)++] = op; 986 op = x_opr_decode (mra, 0); 987 if (op == NULL) 988 return -1; 989 operand[(*n_operands)++] = op; 990 return 0; 991 } 992 993 static int 994 lea_reg_xys (struct mem_read_abstraction_base *mra, 995 int *n_operands, struct operand **operand) 996 { 997 struct operand *op; 998 bfd_byte byte; 999 int status = mra->read (mra, -1, 1, &byte); 1000 if (status < 0) 1001 return status; 1002 1003 int reg_n = -1; 1004 switch (byte & 0x03) 1005 { 1006 case 0x00: 1007 reg_n = REG_X; 1008 break; 1009 case 0x01: 1010 reg_n = REG_Y; 1011 break; 1012 case 0x02: 1013 reg_n = REG_S; 1014 break; 1015 } 1016 1017 status = mra->read (mra, 0, 1, &byte); 1018 if (status < 0) 1019 return status; 1020 1021 op = create_register_operand (reg_n); 1022 if (op == NULL) 1023 return -1; 1024 operand[(*n_operands)++] = op; 1025 op = create_memory_operand (false, (int8_t) byte, 1, reg_n, -1); 1026 if (op == NULL) 1027 return -1; 1028 operand[(*n_operands)++] = op; 1029 return 0; 1030 } 1031 1032 1033 /* PC Relative offsets of size 15 or 7 bits */ 1034 static int 1035 rel_15_7 (struct mem_read_abstraction_base *mra, int offset, 1036 int *n_operands, struct operand **operands) 1037 { 1038 struct operand *op; 1039 bfd_byte upper; 1040 int status = mra->read (mra, offset - 1, 1, &upper); 1041 if (status < 0) 1042 return status; 1043 1044 bool rel_size = (upper & 0x80); 1045 1046 int16_t addr = upper; 1047 if (rel_size) 1048 { 1049 /* 15 bits. Get the next byte */ 1050 bfd_byte lower; 1051 status = mra->read (mra, offset, 1, &lower); 1052 if (status < 0) 1053 return status; 1054 1055 addr <<= 8; 1056 addr |= lower; 1057 addr &= 0x7FFF; 1058 1059 bool negative = (addr & 0x4000); 1060 addr &= 0x3FFF; 1061 if (negative) 1062 addr = addr - 0x4000; 1063 } 1064 else 1065 { 1066 /* 7 bits. */ 1067 bool negative = (addr & 0x40); 1068 addr &= 0x3F; 1069 if (negative) 1070 addr = addr - 0x40; 1071 } 1072 1073 op = create_simple_memory_operand (addr, mra->posn (mra) - 1, true); 1074 if (op == NULL) 1075 return -1; 1076 operands[(*n_operands)++] = op; 1077 return 0; 1078 } 1079 1080 1081 /* PC Relative offsets of size 15 or 7 bits */ 1082 static int 1083 decode_rel_15_7 (struct mem_read_abstraction_base *mra, 1084 int *n_operands, struct operand **operand) 1085 { 1086 return rel_15_7 (mra, 1, n_operands, operand); 1087 } 1088 1089 static int shift_n_bytes (struct mem_read_abstraction_base *); 1090 static int mov_imm_opr_n_bytes (struct mem_read_abstraction_base *); 1091 static int loop_prim_n_bytes (struct mem_read_abstraction_base *); 1092 static int bm_rel_n_bytes (struct mem_read_abstraction_base *); 1093 static int mul_n_bytes (struct mem_read_abstraction_base *); 1094 static int bm_n_bytes (struct mem_read_abstraction_base *); 1095 1096 static int psh_pul_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1097 static int shift_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1098 static int mul_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1099 static int bm_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1100 static int bm_rel_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1101 static int mov_imm_opr (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operand); 1102 static int loop_primitive_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands); 1103 static int bit_field_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands); 1104 static int exg_sex_decode (struct mem_read_abstraction_base *mra, int *n_operands, struct operand **operands); 1105 1106 1107 static enum optr shift_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1108 static enum optr psh_pul_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1109 static enum optr mul_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1110 static enum optr loop_primitive_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1111 static enum optr bit_field_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1112 static enum optr exg_sex_discrim (struct mem_read_abstraction_base *mra, enum optr hint); 1113 1114 1115 static int 1116 cmp_xy (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED, 1117 int *n_operands, struct operand **operand) 1118 { 1119 struct operand *op; 1120 1121 op = create_register_operand (REG_X); 1122 if (op == NULL) 1123 return -1; 1124 operand[(*n_operands)++] = op; 1125 op = create_register_operand (REG_Y); 1126 if (op == NULL) 1127 return -1; 1128 operand[(*n_operands)++] = op; 1129 return 0; 1130 } 1131 1132 static int 1133 sub_d6_x_y (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED, 1134 int *n_operands, struct operand **operand) 1135 { 1136 struct operand *op; 1137 1138 op = create_register_operand (REG_D6); 1139 if (op == NULL) 1140 return -1; 1141 operand[(*n_operands)++] = op; 1142 op = create_register_operand (REG_X); 1143 if (op == NULL) 1144 return -1; 1145 operand[(*n_operands)++] = op; 1146 op = create_register_operand (REG_Y); 1147 if (op == NULL) 1148 return -1; 1149 operand[(*n_operands)++] = op; 1150 return 0; 1151 } 1152 1153 static int 1154 sub_d6_y_x (struct mem_read_abstraction_base *mra ATTRIBUTE_UNUSED, 1155 int *n_operands, struct operand **operand) 1156 { 1157 struct operand *op; 1158 1159 op = create_register_operand (REG_D6); 1160 if (op == NULL) 1161 return -1; 1162 operand[(*n_operands)++] = op; 1163 op = create_register_operand (REG_Y); 1164 if (op == NULL) 1165 return -1; 1166 operand[(*n_operands)++] = op; 1167 op = create_register_operand (REG_X); 1168 if (op == NULL) 1169 return -1; 1170 operand[(*n_operands)++] = op; 1171 return 0; 1172 } 1173 1174 static int 1175 ld_18bit_decode (struct mem_read_abstraction_base *mra, int *n_operands, 1176 struct operand **operand); 1177 1178 static enum optr 1179 mul_discrim (struct mem_read_abstraction_base *mra, enum optr hint) 1180 { 1181 uint8_t mb; 1182 int status = mra->read (mra, 0, 1, &mb); 1183 if (status < 0) 1184 return OP_INVALID; 1185 1186 bool signed_op = (mb & 0x80); 1187 1188 switch (hint) 1189 { 1190 case OPBASE_mul: 1191 return signed_op ? OP_muls : OP_mulu; 1192 break; 1193 case OPBASE_div: 1194 return signed_op ? OP_divs : OP_divu; 1195 break; 1196 case OPBASE_mod: 1197 return signed_op ? OP_mods : OP_modu; 1198 break; 1199 case OPBASE_mac: 1200 return signed_op ? OP_macs : OP_macu; 1201 break; 1202 case OPBASE_qmul: 1203 return signed_op ? OP_qmuls : OP_qmulu; 1204 break; 1205 default: 1206 abort (); 1207 } 1208 1209 return OP_INVALID; 1210 } 1211 1212 struct opcode 1213 { 1214 /* The operation that this opcode performs. */ 1215 enum optr operator; 1216 1217 /* The size of this operation. May be -1 if it is implied 1218 in the operands or if size is not applicable. */ 1219 short osize; 1220 1221 /* Some operations need this function to work out which operation 1222 is intended. */ 1223 discriminator_f discriminator; 1224 1225 /* A function returning the number of bytes in this instruction. */ 1226 insn_bytes_f insn_bytes; 1227 1228 operands_f operands; 1229 operands_f operands2; 1230 }; 1231 1232 static const struct opcode page2[] = 1233 { 1234 [0x00] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_s_opr, 0}, 1235 [0x01] = {OP_st, -1, 0, opr_n_bytes_p1, reg_s_opr, 0}, 1236 [0x02] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_s_opr, 0}, 1237 [0x03] = {OP_ld, -1, 0, four, reg_s_imm, 0}, 1238 [0x04] = {OP_cmp, -1, 0, four, reg_s_imm, 0}, 1239 [0x05] = {OP_stop, -1, 0, single, 0, 0}, 1240 [0x06] = {OP_wai, -1, 0, single, 0, 0}, 1241 [0x07] = {OP_sys, -1, 0, single, 0, 0}, 1242 [0x08] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, /* BFEXT / BFINS */ 1243 [0x09] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1244 [0x0a] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1245 [0x0b] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1246 [0x0c] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1247 [0x0d] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1248 [0x0e] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1249 [0x0f] = {0xFFFF, -1, bit_field_discrim, bfextins_n_bytes, bit_field_decode, 0}, 1250 [0x10] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1251 [0x11] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1252 [0x12] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1253 [0x13] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1254 [0x14] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1255 [0x15] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1256 [0x16] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1257 [0x17] = {OP_minu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1258 [0x18] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1259 [0x19] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1260 [0x1a] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1261 [0x1b] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1262 [0x1c] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1263 [0x1d] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1264 [0x1e] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1265 [0x1f] = {OP_maxu, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1266 [0x20] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1267 [0x21] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1268 [0x22] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1269 [0x23] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1270 [0x24] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1271 [0x25] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1272 [0x26] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1273 [0x27] = {OP_mins, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1274 [0x28] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1275 [0x29] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1276 [0x2a] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1277 [0x2b] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1278 [0x2c] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1279 [0x2d] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1280 [0x2e] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1281 [0x2f] = {OP_maxs, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1282 [0x30] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1283 [0x31] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1284 [0x32] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1285 [0x33] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1286 [0x34] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1287 [0x35] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1288 [0x36] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1289 [0x37] = {OPBASE_div, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1290 [0x38] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1291 [0x39] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1292 [0x3a] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1293 [0x3b] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1294 [0x3c] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1295 [0x3d] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1296 [0x3e] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1297 [0x3f] = {OPBASE_mod, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1298 [0x40] = {OP_abs, -1, 0, single, z_reg, 0}, 1299 [0x41] = {OP_abs, -1, 0, single, z_reg, 0}, 1300 [0x42] = {OP_abs, -1, 0, single, z_reg, 0}, 1301 [0x43] = {OP_abs, -1, 0, single, z_reg, 0}, 1302 [0x44] = {OP_abs, -1, 0, single, z_reg, 0}, 1303 [0x45] = {OP_abs, -1, 0, single, z_reg, 0}, 1304 [0x46] = {OP_abs, -1, 0, single, z_reg, 0}, 1305 [0x47] = {OP_abs, -1, 0, single, z_reg, 0}, 1306 [0x48] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1307 [0x49] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1308 [0x4a] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1309 [0x4b] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1310 [0x4c] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1311 [0x4d] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1312 [0x4e] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1313 [0x4f] = {OPBASE_mac, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1314 [0x50] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base}, 1315 [0x51] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base}, 1316 [0x52] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base}, 1317 [0x53] = {OP_adc, -1, 0, three, z_reg, z_imm1234_0base}, 1318 [0x54] = {OP_adc, -1, 0, two, z_reg, z_imm1234_0base}, 1319 [0x55] = {OP_adc, -1, 0, two, z_reg, z_imm1234_0base}, 1320 [0x56] = {OP_adc, -1, 0, five, z_reg, z_imm1234_0base}, 1321 [0x57] = {OP_adc, -1, 0, five, z_reg, z_imm1234_0base}, 1322 [0x58] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base}, 1323 [0x59] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base}, 1324 [0x5a] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base}, 1325 [0x5b] = {OP_bit, -1, 0, three, z_reg, z_imm1234_8base}, 1326 [0x5c] = {OP_bit, -1, 0, two, z_reg, z_imm1234_8base}, 1327 [0x5d] = {OP_bit, -1, 0, two, z_reg, z_imm1234_8base}, 1328 [0x5e] = {OP_bit, -1, 0, five, z_reg, z_imm1234_8base}, 1329 [0x5f] = {OP_bit, -1, 0, five, z_reg, z_imm1234_8base}, 1330 [0x60] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1331 [0x61] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1332 [0x62] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1333 [0x63] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1334 [0x64] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1335 [0x65] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1336 [0x66] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1337 [0x67] = {OP_adc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1338 [0x68] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1339 [0x69] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1340 [0x6a] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1341 [0x6b] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1342 [0x6c] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1343 [0x6d] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1344 [0x6e] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1345 [0x6f] = {OP_bit, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1346 [0x70] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base}, 1347 [0x71] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base}, 1348 [0x72] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base}, 1349 [0x73] = {OP_sbc, -1, 0, three, z_reg, z_imm1234_0base}, 1350 [0x74] = {OP_sbc, -1, 0, two, z_reg, z_imm1234_0base}, 1351 [0x75] = {OP_sbc, -1, 0, two, z_reg, z_imm1234_0base}, 1352 [0x76] = {OP_sbc, -1, 0, five, z_reg, z_imm1234_0base}, 1353 [0x77] = {OP_sbc, -1, 0, five, z_reg, z_imm1234_0base}, 1354 [0x78] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base}, 1355 [0x79] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base}, 1356 [0x7a] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base}, 1357 [0x7b] = {OP_eor, -1, 0, three, z_reg, z_imm1234_8base}, 1358 [0x7c] = {OP_eor, -1, 0, two, z_reg, z_imm1234_8base}, 1359 [0x7d] = {OP_eor, -1, 0, two, z_reg, z_imm1234_8base}, 1360 [0x7e] = {OP_eor, -1, 0, five, z_reg, z_imm1234_8base}, 1361 [0x7f] = {OP_eor, -1, 0, five, z_reg, z_imm1234_8base}, 1362 [0x80] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1363 [0x81] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1364 [0x82] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1365 [0x83] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1366 [0x84] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1367 [0x85] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1368 [0x86] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1369 [0x87] = {OP_sbc, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1370 [0x88] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1371 [0x89] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1372 [0x8a] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1373 [0x8b] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1374 [0x8c] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1375 [0x8d] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1376 [0x8e] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1377 [0x8f] = {OP_eor, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1378 [0x90] = {OP_rti, -1, 0, single, 0, 0}, 1379 [0x91] = {OP_clb, -1, 0, two, z_tfr, 0}, 1380 [0x92] = {OP_trap, -1, 0, single, trap_decode, 0}, 1381 [0x93] = {OP_trap, -1, 0, single, trap_decode, 0}, 1382 [0x94] = {OP_trap, -1, 0, single, trap_decode, 0}, 1383 [0x95] = {OP_trap, -1, 0, single, trap_decode, 0}, 1384 [0x96] = {OP_trap, -1, 0, single, trap_decode, 0}, 1385 [0x97] = {OP_trap, -1, 0, single, trap_decode, 0}, 1386 [0x98] = {OP_trap, -1, 0, single, trap_decode, 0}, 1387 [0x99] = {OP_trap, -1, 0, single, trap_decode, 0}, 1388 [0x9a] = {OP_trap, -1, 0, single, trap_decode, 0}, 1389 [0x9b] = {OP_trap, -1, 0, single, trap_decode, 0}, 1390 [0x9c] = {OP_trap, -1, 0, single, trap_decode, 0}, 1391 [0x9d] = {OP_trap, -1, 0, single, trap_decode, 0}, 1392 [0x9e] = {OP_trap, -1, 0, single, trap_decode, 0}, 1393 [0x9f] = {OP_trap, -1, 0, single, trap_decode, 0}, 1394 [0xa0] = {OP_sat, -1, 0, single, z_reg, 0}, 1395 [0xa1] = {OP_sat, -1, 0, single, z_reg, 0}, 1396 [0xa2] = {OP_sat, -1, 0, single, z_reg, 0}, 1397 [0xa3] = {OP_sat, -1, 0, single, z_reg, 0}, 1398 [0xa4] = {OP_sat, -1, 0, single, z_reg, 0}, 1399 [0xa5] = {OP_sat, -1, 0, single, z_reg, 0}, 1400 [0xa6] = {OP_sat, -1, 0, single, z_reg, 0}, 1401 [0xa7] = {OP_sat, -1, 0, single, z_reg, 0}, 1402 [0xa8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1403 [0xa9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1404 [0xaa] = {OP_trap, -1, 0, single, trap_decode, 0}, 1405 [0xab] = {OP_trap, -1, 0, single, trap_decode, 0}, 1406 [0xac] = {OP_trap, -1, 0, single, trap_decode, 0}, 1407 [0xad] = {OP_trap, -1, 0, single, trap_decode, 0}, 1408 [0xae] = {OP_trap, -1, 0, single, trap_decode, 0}, 1409 [0xaf] = {OP_trap, -1, 0, single, trap_decode, 0}, 1410 [0xb0] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1411 [0xb1] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1412 [0xb2] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1413 [0xb3] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1414 [0xb4] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1415 [0xb5] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1416 [0xb6] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1417 [0xb7] = {OPBASE_qmul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1418 [0xb8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1419 [0xb9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1420 [0xba] = {OP_trap, -1, 0, single, trap_decode, 0}, 1421 [0xbb] = {OP_trap, -1, 0, single, trap_decode, 0}, 1422 [0xbc] = {OP_trap, -1, 0, single, trap_decode, 0}, 1423 [0xbd] = {OP_trap, -1, 0, single, trap_decode, 0}, 1424 [0xbe] = {OP_trap, -1, 0, single, trap_decode, 0}, 1425 [0xbf] = {OP_trap, -1, 0, single, trap_decode, 0}, 1426 [0xc0] = {OP_trap, -1, 0, single, trap_decode, 0}, 1427 [0xc1] = {OP_trap, -1, 0, single, trap_decode, 0}, 1428 [0xc2] = {OP_trap, -1, 0, single, trap_decode, 0}, 1429 [0xc3] = {OP_trap, -1, 0, single, trap_decode, 0}, 1430 [0xc4] = {OP_trap, -1, 0, single, trap_decode, 0}, 1431 [0xc5] = {OP_trap, -1, 0, single, trap_decode, 0}, 1432 [0xc6] = {OP_trap, -1, 0, single, trap_decode, 0}, 1433 [0xc7] = {OP_trap, -1, 0, single, trap_decode, 0}, 1434 [0xc8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1435 [0xc9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1436 [0xca] = {OP_trap, -1, 0, single, trap_decode, 0}, 1437 [0xcb] = {OP_trap, -1, 0, single, trap_decode, 0}, 1438 [0xcc] = {OP_trap, -1, 0, single, trap_decode, 0}, 1439 [0xcd] = {OP_trap, -1, 0, single, trap_decode, 0}, 1440 [0xce] = {OP_trap, -1, 0, single, trap_decode, 0}, 1441 [0xcf] = {OP_trap, -1, 0, single, trap_decode, 0}, 1442 [0xd0] = {OP_trap, -1, 0, single, trap_decode, 0}, 1443 [0xd1] = {OP_trap, -1, 0, single, trap_decode, 0}, 1444 [0xd2] = {OP_trap, -1, 0, single, trap_decode, 0}, 1445 [0xd3] = {OP_trap, -1, 0, single, trap_decode, 0}, 1446 [0xd4] = {OP_trap, -1, 0, single, trap_decode, 0}, 1447 [0xd5] = {OP_trap, -1, 0, single, trap_decode, 0}, 1448 [0xd6] = {OP_trap, -1, 0, single, trap_decode, 0}, 1449 [0xd7] = {OP_trap, -1, 0, single, trap_decode, 0}, 1450 [0xd8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1451 [0xd9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1452 [0xda] = {OP_trap, -1, 0, single, trap_decode, 0}, 1453 [0xdb] = {OP_trap, -1, 0, single, trap_decode, 0}, 1454 [0xdc] = {OP_trap, -1, 0, single, trap_decode, 0}, 1455 [0xdd] = {OP_trap, -1, 0, single, trap_decode, 0}, 1456 [0xde] = {OP_trap, -1, 0, single, trap_decode, 0}, 1457 [0xdf] = {OP_trap, -1, 0, single, trap_decode, 0}, 1458 [0xe0] = {OP_trap, -1, 0, single, trap_decode, 0}, 1459 [0xe1] = {OP_trap, -1, 0, single, trap_decode, 0}, 1460 [0xe2] = {OP_trap, -1, 0, single, trap_decode, 0}, 1461 [0xe3] = {OP_trap, -1, 0, single, trap_decode, 0}, 1462 [0xe4] = {OP_trap, -1, 0, single, trap_decode, 0}, 1463 [0xe5] = {OP_trap, -1, 0, single, trap_decode, 0}, 1464 [0xe6] = {OP_trap, -1, 0, single, trap_decode, 0}, 1465 [0xe7] = {OP_trap, -1, 0, single, trap_decode, 0}, 1466 [0xe8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1467 [0xe9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1468 [0xea] = {OP_trap, -1, 0, single, trap_decode, 0}, 1469 [0xeb] = {OP_trap, -1, 0, single, trap_decode, 0}, 1470 [0xec] = {OP_trap, -1, 0, single, trap_decode, 0}, 1471 [0xed] = {OP_trap, -1, 0, single, trap_decode, 0}, 1472 [0xee] = {OP_trap, -1, 0, single, trap_decode, 0}, 1473 [0xef] = {OP_trap, -1, 0, single, trap_decode, 0}, 1474 [0xf0] = {OP_trap, -1, 0, single, trap_decode, 0}, 1475 [0xf1] = {OP_trap, -1, 0, single, trap_decode, 0}, 1476 [0xf2] = {OP_trap, -1, 0, single, trap_decode, 0}, 1477 [0xf3] = {OP_trap, -1, 0, single, trap_decode, 0}, 1478 [0xf4] = {OP_trap, -1, 0, single, trap_decode, 0}, 1479 [0xf5] = {OP_trap, -1, 0, single, trap_decode, 0}, 1480 [0xf6] = {OP_trap, -1, 0, single, trap_decode, 0}, 1481 [0xf7] = {OP_trap, -1, 0, single, trap_decode, 0}, 1482 [0xf8] = {OP_trap, -1, 0, single, trap_decode, 0}, 1483 [0xf9] = {OP_trap, -1, 0, single, trap_decode, 0}, 1484 [0xfa] = {OP_trap, -1, 0, single, trap_decode, 0}, 1485 [0xfb] = {OP_trap, -1, 0, single, trap_decode, 0}, 1486 [0xfc] = {OP_trap, -1, 0, single, trap_decode, 0}, 1487 [0xfd] = {OP_trap, -1, 0, single, trap_decode, 0}, 1488 [0xfe] = {OP_trap, -1, 0, single, trap_decode, 0}, 1489 [0xff] = {OP_trap, -1, 0, single, trap_decode, 0}, 1490 }; 1491 1492 static const struct opcode page1[] = 1493 { 1494 [0x00] = {OP_bgnd, -1, 0, single, 0, 0}, 1495 [0x01] = {OP_nop, -1, 0, single, 0, 0}, 1496 [0x02] = {OP_brclr, -1, 0, bm_rel_n_bytes, bm_rel_decode, 0}, 1497 [0x03] = {OP_brset, -1, 0, bm_rel_n_bytes, bm_rel_decode, 0}, 1498 [0x04] = {0xFFFF, -1, psh_pul_discrim, two, psh_pul_decode, 0}, /* psh/pul */ 1499 [0x05] = {OP_rts, -1, 0, single, 0, 0}, 1500 [0x06] = {OP_lea, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1501 [0x07] = {OP_lea, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1502 [0x08] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0}, 1503 [0x09] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0}, 1504 [0x0a] = {OP_lea, -1, 0, opr_n_bytes_p1, lea_reg_xys_opr, 0}, 1505 [0x0b] = {0xFFFF, -1, loop_primitive_discrim, loop_prim_n_bytes, loop_primitive_decode, 0}, /* Loop primitives TBcc / DBcc */ 1506 [0x0c] = {OP_mov, 0, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0}, 1507 [0x0d] = {OP_mov, 1, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0}, 1508 [0x0e] = {OP_mov, 2, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0}, 1509 [0x0f] = {OP_mov, 3, 0, mov_imm_opr_n_bytes, mov_imm_opr, 0}, 1510 [0x10] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, /* lsr/lsl/asl/asr/rol/ror */ 1511 [0x11] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1512 [0x12] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1513 [0x13] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1514 [0x14] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1515 [0x15] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1516 [0x16] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1517 [0x17] = {0xFFFF, -1, shift_discrim, shift_n_bytes, shift_decode, 0}, 1518 [0x18] = {OP_lea, -1, 0, two, lea_reg_xys, NULL}, 1519 [0x19] = {OP_lea, -1, 0, two, lea_reg_xys, NULL}, 1520 [0x1a] = {OP_lea, -1, 0, two, lea_reg_xys, NULL}, 1521 /* 0x1b PG2 */ 1522 [0x1c] = {OP_mov, 0, 0, opr_n_bytes2, z_opr_decode2, 0}, 1523 [0x1d] = {OP_mov, 1, 0, opr_n_bytes2, z_opr_decode2, 0}, 1524 [0x1e] = {OP_mov, 2, 0, opr_n_bytes2, z_opr_decode2, 0}, 1525 [0x1f] = {OP_mov, 3, 0, opr_n_bytes2, z_opr_decode2, 0}, 1526 [0x20] = {OP_bra, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1527 [0x21] = {OP_bsr, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1528 [0x22] = {OP_bhi, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1529 [0x23] = {OP_bls, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1530 [0x24] = {OP_bcc, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1531 [0x25] = {OP_bcs, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1532 [0x26] = {OP_bne, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1533 [0x27] = {OP_beq, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1534 [0x28] = {OP_bvc, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1535 [0x29] = {OP_bvs, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1536 [0x2a] = {OP_bpl, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1537 [0x2b] = {OP_bmi, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1538 [0x2c] = {OP_bge, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1539 [0x2d] = {OP_blt, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1540 [0x2e] = {OP_bgt, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1541 [0x2f] = {OP_ble, -1, 0, pcrel_15bit, decode_rel_15_7, 0}, 1542 [0x30] = {OP_inc, -1, 0, single, z_reg, 0}, 1543 [0x31] = {OP_inc, -1, 0, single, z_reg, 0}, 1544 [0x32] = {OP_inc, -1, 0, single, z_reg, 0}, 1545 [0x33] = {OP_inc, -1, 0, single, z_reg, 0}, 1546 [0x34] = {OP_inc, -1, 0, single, z_reg, 0}, 1547 [0x35] = {OP_inc, -1, 0, single, z_reg, 0}, 1548 [0x36] = {OP_inc, -1, 0, single, z_reg, 0}, 1549 [0x37] = {OP_inc, -1, 0, single, z_reg, 0}, 1550 [0x38] = {OP_clr, -1, 0, single, z_reg, 0}, 1551 [0x39] = {OP_clr, -1, 0, single, z_reg, 0}, 1552 [0x3a] = {OP_clr, -1, 0, single, z_reg, 0}, 1553 [0x3b] = {OP_clr, -1, 0, single, z_reg, 0}, 1554 [0x3c] = {OP_clr, -1, 0, single, z_reg, 0}, 1555 [0x3d] = {OP_clr, -1, 0, single, z_reg, 0}, 1556 [0x3e] = {OP_clr, -1, 0, single, z_reg, 0}, 1557 [0x3f] = {OP_clr, -1, 0, single, z_reg, 0}, 1558 [0x40] = {OP_dec, -1, 0, single, z_reg, 0}, 1559 [0x41] = {OP_dec, -1, 0, single, z_reg, 0}, 1560 [0x42] = {OP_dec, -1, 0, single, z_reg, 0}, 1561 [0x43] = {OP_dec, -1, 0, single, z_reg, 0}, 1562 [0x44] = {OP_dec, -1, 0, single, z_reg, 0}, 1563 [0x45] = {OP_dec, -1, 0, single, z_reg, 0}, 1564 [0x46] = {OP_dec, -1, 0, single, z_reg, 0}, 1565 [0x47] = {OP_dec, -1, 0, single, z_reg, 0}, 1566 [0x48] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1567 [0x49] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1568 [0x4a] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1569 [0x4b] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1570 [0x4c] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1571 [0x4d] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1572 [0x4e] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1573 [0x4f] = {OPBASE_mul, -1, mul_discrim, mul_n_bytes, mul_decode, 0}, 1574 [0x50] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base}, 1575 [0x51] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base}, 1576 [0x52] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base}, 1577 [0x53] = {OP_add, -1, 0, three, z_reg, z_imm1234_0base}, 1578 [0x54] = {OP_add, -1, 0, two, z_reg, z_imm1234_0base}, 1579 [0x55] = {OP_add, -1, 0, two, z_reg, z_imm1234_0base}, 1580 [0x56] = {OP_add, -1, 0, five, z_reg, z_imm1234_0base}, 1581 [0x57] = {OP_add, -1, 0, five, z_reg, z_imm1234_0base}, 1582 [0x58] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base}, 1583 [0x59] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base}, 1584 [0x5a] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base}, 1585 [0x5b] = {OP_and, -1, 0, three, z_reg, z_imm1234_8base}, 1586 [0x5c] = {OP_and, -1, 0, two, z_reg, z_imm1234_8base}, 1587 [0x5d] = {OP_and, -1, 0, two, z_reg, z_imm1234_8base}, 1588 [0x5e] = {OP_and, -1, 0, five, z_reg, z_imm1234_8base}, 1589 [0x5f] = {OP_and, -1, 0, five, z_reg, z_imm1234_8base}, 1590 [0x60] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1591 [0x61] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1592 [0x62] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1593 [0x63] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1594 [0x64] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1595 [0x65] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1596 [0x66] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1597 [0x67] = {OP_add, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1598 [0x68] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1599 [0x69] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1600 [0x6a] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1601 [0x6b] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1602 [0x6c] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1603 [0x6d] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1604 [0x6e] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1605 [0x6f] = {OP_and, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1606 [0x70] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base}, 1607 [0x71] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base}, 1608 [0x72] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base}, 1609 [0x73] = {OP_sub, -1, 0, three, z_reg, z_imm1234_0base}, 1610 [0x74] = {OP_sub, -1, 0, two, z_reg, z_imm1234_0base}, 1611 [0x75] = {OP_sub, -1, 0, two, z_reg, z_imm1234_0base}, 1612 [0x76] = {OP_sub, -1, 0, five, z_reg, z_imm1234_0base}, 1613 [0x77] = {OP_sub, -1, 0, five, z_reg, z_imm1234_0base}, 1614 [0x78] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base}, 1615 [0x79] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base}, 1616 [0x7a] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base}, 1617 [0x7b] = {OP_or, -1, 0, three, z_reg, z_imm1234_8base}, 1618 [0x7c] = {OP_or, -1, 0, two, z_reg, z_imm1234_8base}, 1619 [0x7d] = {OP_or, -1, 0, two, z_reg, z_imm1234_8base}, 1620 [0x7e] = {OP_or, -1, 0, five, z_reg, z_imm1234_8base}, 1621 [0x7f] = {OP_or, -1, 0, five, z_reg, z_imm1234_8base}, 1622 [0x80] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1623 [0x81] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1624 [0x82] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1625 [0x83] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1626 [0x84] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1627 [0x85] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1628 [0x86] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1629 [0x87] = {OP_sub, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1630 [0x88] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1631 [0x89] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1632 [0x8a] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1633 [0x8b] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1634 [0x8c] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1635 [0x8d] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1636 [0x8e] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1637 [0x8f] = {OP_or, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1638 [0x90] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base}, 1639 [0x91] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base}, 1640 [0x92] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base}, 1641 [0x93] = {OP_ld, -1, 0, three, z_reg, z_imm1234_0base}, 1642 [0x94] = {OP_ld, -1, 0, two, z_reg, z_imm1234_0base}, 1643 [0x95] = {OP_ld, -1, 0, two, z_reg, z_imm1234_0base}, 1644 [0x96] = {OP_ld, -1, 0, five, z_reg, z_imm1234_0base}, 1645 [0x97] = {OP_ld, -1, 0, five, z_reg, z_imm1234_0base}, 1646 [0x98] = {OP_ld, -1, 0, four, reg_xy, z_imm1234_0base}, 1647 [0x99] = {OP_ld, -1, 0, four, reg_xy, z_imm1234_0base}, 1648 [0x9a] = {OP_clr, -1, 0, single, reg_xy, 0}, 1649 [0x9b] = {OP_clr, -1, 0, single, reg_xy, 0}, 1650 [0x9c] = {OP_inc, 0, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1651 [0x9d] = {OP_inc, 1, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1652 [0x9e] = {OP_tfr, -1, 0, two, z_tfr, NULL}, 1653 [0x9f] = {OP_inc, 3, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1654 [0xa0] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1655 [0xa1] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1656 [0xa2] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1657 [0xa3] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1658 [0xa4] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1659 [0xa5] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1660 [0xa6] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1661 [0xa7] = {OP_ld, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1662 [0xa8] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1663 [0xa9] = {OP_ld, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1664 [0xaa] = {OP_jmp, -1, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1665 [0xab] = {OP_jsr, -1, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1666 [0xac] = {OP_dec, 0, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1667 [0xad] = {OP_dec, 1, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1668 [0xae] = {0xFFFF, -1, exg_sex_discrim, two, exg_sex_decode, 0}, /* EXG / SEX */ 1669 [0xaf] = {OP_dec, 3, 0, opr_n_bytes_p1, 0, z_opr_decode}, 1670 [0xb0] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1671 [0xb1] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1672 [0xb2] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1673 [0xb3] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1674 [0xb4] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1675 [0xb5] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1676 [0xb6] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1677 [0xb7] = {OP_ld, -1, 0, four, z_reg, z_ext24_decode}, 1678 [0xb8] = {OP_ld, -1, 0, four, reg_xy, z_ext24_decode}, 1679 [0xb9] = {OP_ld, -1, 0, four, reg_xy, z_ext24_decode}, 1680 [0xba] = {OP_jmp, -1, 0, four, z_ext24_decode, 0}, 1681 [0xbb] = {OP_jsr, -1, 0, four, z_ext24_decode, 0}, 1682 [0xbc] = {OP_clr, 0, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1683 [0xbd] = {OP_clr, 1, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1684 [0xbe] = {OP_clr, 2, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1685 [0xbf] = {OP_clr, 3, 0, opr_n_bytes_p1, z_opr_decode, 0}, 1686 [0xc0] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1687 [0xc1] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1688 [0xc2] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1689 [0xc3] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1690 [0xc4] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1691 [0xc5] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1692 [0xc6] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1693 [0xc7] = {OP_st, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1694 [0xc8] = {OP_st, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1695 [0xc9] = {OP_st, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1696 [0xca] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1697 [0xcb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1698 [0xcc] = {OP_com, 0, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1699 [0xcd] = {OP_com, 1, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1700 [0xce] = {OP_andcc, -1, 0, two, imm1_decode, 0}, 1701 [0xcf] = {OP_com, 3, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1702 [0xd0] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1703 [0xd1] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1704 [0xd2] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1705 [0xd3] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1706 [0xd4] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1707 [0xd5] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1708 [0xd6] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1709 [0xd7] = {OP_st, -1, 0, four, z_reg, z_ext24_decode}, 1710 [0xd8] = {OP_st, -1, 0, four, reg_xy, z_ext24_decode}, 1711 [0xd9] = {OP_st, -1, 0, four, reg_xy, z_ext24_decode}, 1712 [0xda] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1713 [0xdb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1714 [0xdc] = {OP_neg, 0, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1715 [0xdd] = {OP_neg, 1, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1716 [0xde] = {OP_orcc, -1, 0, two, imm1_decode, 0}, 1717 [0xdf] = {OP_neg, 3, 0, opr_n_bytes_p1, NULL, z_opr_decode}, 1718 [0xe0] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base}, 1719 [0xe1] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base}, 1720 [0xe2] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base}, 1721 [0xe3] = {OP_cmp, -1, 0, three, z_reg, z_imm1234_0base}, 1722 [0xe4] = {OP_cmp, -1, 0, two, z_reg, z_imm1234_0base}, 1723 [0xe5] = {OP_cmp, -1, 0, two, z_reg, z_imm1234_0base}, 1724 [0xe6] = {OP_cmp, -1, 0, five, z_reg, z_imm1234_0base}, 1725 [0xe7] = {OP_cmp, -1, 0, five, z_reg, z_imm1234_0base}, 1726 [0xe8] = {OP_cmp, -1, 0, four, reg_xy, z_imm1234_0base}, 1727 [0xe9] = {OP_cmp, -1, 0, four, reg_xy, z_imm1234_0base}, 1728 [0xea] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1729 [0xeb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1730 [0xec] = {OP_bclr, -1, 0, bm_n_bytes, bm_decode, 0}, 1731 [0xed] = {OP_bset, -1, 0, bm_n_bytes, bm_decode, 0}, 1732 [0xee] = {OP_btgl, -1, 0, bm_n_bytes, bm_decode, 0}, 1733 [0xef] = {OP_INVALID, -1, 0, NULL, NULL, NULL}, /* SPARE */ 1734 [0xf0] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1735 [0xf1] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1736 [0xf2] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1737 [0xf3] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1738 [0xf4] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1739 [0xf5] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1740 [0xf6] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1741 [0xf7] = {OP_cmp, -1, 0, opr_n_bytes_p1, z_reg, z_opr_decode}, 1742 [0xf8] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1743 [0xf9] = {OP_cmp, -1, 0, opr_n_bytes_p1, reg_xy, z_opr_decode}, 1744 [0xfa] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1745 [0xfb] = {OP_ld, -1, 0, three, reg_xy, ld_18bit_decode}, 1746 [0xfc] = {OP_cmp, -1, 0, single, cmp_xy, 0}, 1747 [0xfd] = {OP_sub, -1, 0, single, sub_d6_x_y, 0}, 1748 [0xfe] = {OP_sub, -1, 0, single, sub_d6_y_x, 0}, 1749 [0xff] = {OP_swi, -1, 0, single, 0, 0} 1750 }; 1751 1752 static const int oprregs1[] = 1753 { 1754 REG_D3, REG_D2, REG_D1, REG_D0, REG_CCL, REG_CCH 1755 }; 1756 1757 static const int oprregs2[] = 1758 { 1759 REG_Y, REG_X, REG_D7, REG_D6, REG_D5, REG_D4 1760 }; 1761 1762 1763 1764 1766 enum MUL_MODE 1767 { 1768 MUL_REG_REG, 1769 MUL_REG_OPR, 1770 MUL_REG_IMM, 1771 MUL_OPR_OPR 1772 }; 1773 1774 struct mb 1775 { 1776 uint8_t mask; 1777 uint8_t value; 1778 enum MUL_MODE mode; 1779 }; 1780 1781 static const struct mb mul_table[] = { 1782 {0x40, 0x00, MUL_REG_REG}, 1783 1784 {0x47, 0x40, MUL_REG_OPR}, 1785 {0x47, 0x41, MUL_REG_OPR}, 1786 {0x47, 0x43, MUL_REG_OPR}, 1787 1788 {0x47, 0x44, MUL_REG_IMM}, 1789 {0x47, 0x45, MUL_REG_IMM}, 1790 {0x47, 0x47, MUL_REG_IMM}, 1791 1792 {0x43, 0x42, MUL_OPR_OPR}, 1793 }; 1794 1795 1796 static int 1797 mul_decode (struct mem_read_abstraction_base *mra, 1798 int *n_operands, struct operand **operand) 1799 { 1800 uint8_t mb; 1801 struct operand *op; 1802 int status = mra->read (mra, 0, 1, &mb); 1803 if (status < 0) 1804 return status; 1805 1806 uint8_t byte; 1807 status = mra->read (mra, -1, 1, &byte); 1808 if (status < 0) 1809 return status; 1810 1811 enum MUL_MODE mode = -1; 1812 size_t i; 1813 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i) 1814 { 1815 const struct mb *mm = mul_table + i; 1816 if ((mb & mm->mask) == mm->value) 1817 { 1818 mode = mm->mode; 1819 break; 1820 } 1821 } 1822 op = create_register_operand (byte & 0x07); 1823 if (op == NULL) 1824 return -1; 1825 operand[(*n_operands)++] = op; 1826 1827 switch (mode) 1828 { 1829 case MUL_REG_IMM: 1830 { 1831 int size = (mb & 0x3); 1832 op = create_register_operand_with_size ((mb & 0x38) >> 3, size); 1833 if (op == NULL) 1834 return -1; 1835 operand[(*n_operands)++] = op; 1836 1837 uint32_t imm; 1838 if (z_decode_signed_value (mra, 1, size + 1, &imm) < 0) 1839 return -1; 1840 op = create_immediate_operand (imm); 1841 if (op == NULL) 1842 return -1; 1843 operand[(*n_operands)++] = op; 1844 } 1845 break; 1846 case MUL_REG_REG: 1847 op = create_register_operand ((mb & 0x38) >> 3); 1848 if (op == NULL) 1849 return -1; 1850 operand[(*n_operands)++] = op; 1851 op = create_register_operand (mb & 0x07); 1852 if (op == NULL) 1853 return -1; 1854 operand[(*n_operands)++] = op; 1855 break; 1856 case MUL_REG_OPR: 1857 op = create_register_operand ((mb & 0x38) >> 3); 1858 if (op == NULL) 1859 return -1; 1860 operand[(*n_operands)++] = op; 1861 op = x_opr_decode_with_size (mra, 1, mb & 0x3); 1862 if (op == NULL) 1863 return -1; 1864 operand[(*n_operands)++] = op; 1865 break; 1866 case MUL_OPR_OPR: 1867 { 1868 int first = x_opr_n_bytes (mra, 1); 1869 if (first < 0) 1870 return first; 1871 op = x_opr_decode_with_size (mra, 1, (mb & 0x30) >> 4); 1872 if (op == NULL) 1873 return -1; 1874 operand[(*n_operands)++] = op; 1875 op = x_opr_decode_with_size (mra, first + 1, (mb & 0x0c) >> 2); 1876 if (op == NULL) 1877 return -1; 1878 operand[(*n_operands)++] = op; 1879 break; 1880 } 1881 } 1882 return 0; 1883 } 1884 1885 1886 static int 1887 mul_n_bytes (struct mem_read_abstraction_base *mra) 1888 { 1889 int nx = 2; 1890 int first, second; 1891 uint8_t mb; 1892 int status = mra->read (mra, 0, 1, &mb); 1893 if (status < 0) 1894 return status; 1895 1896 enum MUL_MODE mode = -1; 1897 size_t i; 1898 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i) 1899 { 1900 const struct mb *mm = mul_table + i; 1901 if ((mb & mm->mask) == mm->value) 1902 { 1903 mode = mm->mode; 1904 break; 1905 } 1906 } 1907 1908 int size = (mb & 0x3) + 1; 1909 1910 switch (mode) 1911 { 1912 case MUL_REG_IMM: 1913 nx += size; 1914 break; 1915 case MUL_REG_REG: 1916 break; 1917 case MUL_REG_OPR: 1918 first = x_opr_n_bytes (mra, 1); 1919 if (first < 0) 1920 return first; 1921 nx += first; 1922 break; 1923 case MUL_OPR_OPR: 1924 first = x_opr_n_bytes (mra, nx - 1); 1925 if (first < 0) 1926 return first; 1927 nx += first; 1928 second = x_opr_n_bytes (mra, nx - 1); 1929 if (second < 0) 1930 return second; 1931 nx += second; 1932 break; 1933 } 1934 1935 return nx; 1936 } 1937 1938 1939 /* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1, 1941 and contains obvious typos. 1942 However the Freescale tools and experiments with the chip itself 1943 seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG 1944 respectively. */ 1945 1946 enum BM_MODE 1947 { 1948 BM_REG_IMM, 1949 BM_RESERVED0, 1950 BM_OPR_B, 1951 BM_OPR_W, 1952 BM_OPR_L, 1953 BM_OPR_REG, 1954 BM_RESERVED1 1955 }; 1956 1957 struct bm 1958 { 1959 uint8_t mask; 1960 uint8_t value; 1961 enum BM_MODE mode; 1962 }; 1963 1964 static const struct bm bm_table[] = { 1965 { 0xC6, 0x04, BM_REG_IMM}, 1966 { 0x84, 0x00, BM_REG_IMM}, 1967 { 0x06, 0x06, BM_REG_IMM}, 1968 { 0xC6, 0x44, BM_RESERVED0}, 1969 1970 { 0x8F, 0x80, BM_OPR_B}, 1971 { 0x8E, 0x82, BM_OPR_W}, 1972 { 0x8C, 0x88, BM_OPR_L}, 1973 1974 { 0x83, 0x81, BM_OPR_REG}, 1975 { 0x87, 0x84, BM_RESERVED1}, 1976 }; 1977 1978 static int 1979 bm_decode (struct mem_read_abstraction_base *mra, 1980 int *n_operands, struct operand **operand) 1981 { 1982 struct operand *op; 1983 uint8_t bm; 1984 int status = mra->read (mra, 0, 1, &bm); 1985 if (status < 0) 1986 return status; 1987 1988 size_t i; 1989 enum BM_MODE mode = -1; 1990 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i) 1991 { 1992 const struct bm *bme = bm_table + i; 1993 if ((bm & bme->mask) == bme->value) 1994 { 1995 mode = bme->mode; 1996 break; 1997 } 1998 } 1999 2000 switch (mode) 2001 { 2002 case BM_REG_IMM: 2003 case BM_RESERVED0: 2004 op = create_register_operand (bm & 0x07); 2005 if (op == NULL) 2006 return -1; 2007 operand[(*n_operands)++] = op; 2008 break; 2009 case BM_OPR_B: 2010 op = x_opr_decode_with_size (mra, 1, 0); 2011 if (op == NULL) 2012 return -1; 2013 operand[(*n_operands)++] = op; 2014 break; 2015 case BM_OPR_W: 2016 op = x_opr_decode_with_size (mra, 1, 1); 2017 if (op == NULL) 2018 return -1; 2019 operand[(*n_operands)++] = op; 2020 break; 2021 case BM_OPR_L: 2022 op = x_opr_decode_with_size (mra, 1, 3); 2023 if (op == NULL) 2024 return -1; 2025 operand[(*n_operands)++] = op; 2026 break; 2027 case BM_OPR_REG: 2028 case BM_RESERVED1: 2029 { 2030 uint8_t xb; 2031 status = mra->read (mra, 1, 1, &xb); 2032 if (status < 0) 2033 return status; 2034 /* Don't emit a size suffix for register operands */ 2035 if ((xb & 0xF8) != 0xB8) 2036 op = x_opr_decode_with_size (mra, 1, (bm & 0x0c) >> 2); 2037 else 2038 op = x_opr_decode (mra, 1); 2039 if (op == NULL) 2040 return -1; 2041 operand[(*n_operands)++] = op; 2042 } 2043 break; 2044 } 2045 2046 uint8_t imm = 0; 2047 switch (mode) 2048 { 2049 case BM_REG_IMM: 2050 case BM_RESERVED0: 2051 imm = (bm & 0x38) >> 3; 2052 op = create_immediate_operand (imm); 2053 if (op == NULL) 2054 return -1; 2055 operand[(*n_operands)++] = op; 2056 break; 2057 case BM_OPR_L: 2058 imm |= (bm & 0x03) << 3; 2059 /* fallthrough */ 2060 case BM_OPR_W: 2061 imm |= (bm & 0x01) << 3; 2062 /* fallthrough */ 2063 case BM_OPR_B: 2064 imm |= (bm & 0x70) >> 4; 2065 op = create_immediate_operand (imm); 2066 if (op == NULL) 2067 return -1; 2068 operand[(*n_operands)++] = op; 2069 break; 2070 case BM_OPR_REG: 2071 case BM_RESERVED1: 2072 op = create_register_operand ((bm & 0x70) >> 4); 2073 if (op == NULL) 2074 return -1; 2075 operand[(*n_operands)++] = op; 2076 break; 2077 } 2078 return 0; 2079 } 2080 2081 2082 static int 2083 bm_rel_decode (struct mem_read_abstraction_base *mra, 2084 int *n_operands, struct operand **operand) 2085 { 2086 struct operand *op; 2087 uint8_t bm; 2088 int status = mra->read (mra, 0, 1, &bm); 2089 if (status < 0) 2090 return status; 2091 2092 size_t i; 2093 enum BM_MODE mode = -1; 2094 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i) 2095 { 2096 const struct bm *bme = bm_table + i; 2097 if ((bm & bme->mask) == bme->value) 2098 { 2099 mode = bme->mode; 2100 break; 2101 } 2102 } 2103 2104 int n = 1; 2105 switch (mode) 2106 { 2107 case BM_REG_IMM: 2108 case BM_RESERVED0: 2109 op = create_register_operand (bm & 0x07); 2110 if (op == NULL) 2111 return -1; 2112 operand[(*n_operands)++] = op; 2113 break; 2114 case BM_OPR_B: 2115 op = x_opr_decode_with_size (mra, 1, 0); 2116 if (op == NULL) 2117 return -1; 2118 operand[(*n_operands)++] = op; 2119 n = x_opr_n_bytes (mra, 1); 2120 if (n < 0) 2121 return n; 2122 n += 1; 2123 break; 2124 case BM_OPR_W: 2125 op = x_opr_decode_with_size (mra, 1, 1); 2126 if (op == NULL) 2127 return -1; 2128 operand[(*n_operands)++] = op; 2129 n = x_opr_n_bytes (mra, 1); 2130 if (n < 0) 2131 return n; 2132 n += 1; 2133 break; 2134 case BM_OPR_L: 2135 op = x_opr_decode_with_size (mra, 1, 3); 2136 if (op == NULL) 2137 return -1; 2138 operand[(*n_operands)++] = op; 2139 n = x_opr_n_bytes (mra, 1); 2140 if (n < 0) 2141 return n; 2142 n += 1; 2143 break; 2144 case BM_OPR_REG: 2145 case BM_RESERVED1: 2146 { 2147 uint8_t xb; 2148 status = mra->read (mra, +1, 1, &xb); 2149 if (status < 0) 2150 return status; 2151 /* Don't emit a size suffix for register operands */ 2152 if ((xb & 0xF8) != 0xB8) 2153 { 2154 short os = (bm & 0x0c) >> 2; 2155 op = x_opr_decode_with_size (mra, 1, os); 2156 } 2157 else 2158 op = x_opr_decode (mra, 1); 2159 if (op == NULL) 2160 return -1; 2161 operand[(*n_operands)++] = op; 2162 } 2163 break; 2164 } 2165 2166 int x, imm = 0; 2167 switch (mode) 2168 { 2169 case BM_OPR_L: 2170 imm |= (bm & 0x02) << 3; 2171 /* fall through */ 2172 case BM_OPR_W: 2173 imm |= (bm & 0x01) << 3; 2174 /* fall through */ 2175 case BM_OPR_B: 2176 imm |= (bm & 0x70) >> 4; 2177 op = create_immediate_operand (imm); 2178 if (op == NULL) 2179 return -1; 2180 operand[(*n_operands)++] = op; 2181 break; 2182 case BM_RESERVED0: 2183 imm = (bm & 0x38) >> 3; 2184 op = create_immediate_operand (imm); 2185 if (op == NULL) 2186 return -1; 2187 operand[(*n_operands)++] = op; 2188 break; 2189 case BM_REG_IMM: 2190 imm = (bm & 0xF8) >> 3; 2191 op = create_immediate_operand (imm); 2192 if (op == NULL) 2193 return -1; 2194 operand[(*n_operands)++] = op; 2195 break; 2196 case BM_OPR_REG: 2197 case BM_RESERVED1: 2198 op = create_register_operand ((bm & 0x70) >> 4); 2199 if (op == NULL) 2200 return -1; 2201 operand[(*n_operands)++] = op; 2202 x = x_opr_n_bytes (mra, 1); 2203 if (x < 0) 2204 return x; 2205 n += x; 2206 break; 2207 } 2208 2209 return rel_15_7 (mra, n + 1, n_operands, operand); 2210 } 2211 2212 static int 2213 bm_n_bytes (struct mem_read_abstraction_base *mra) 2214 { 2215 uint8_t bm; 2216 int status = mra->read (mra, 0, 1, &bm); 2217 if (status < 0) 2218 return status; 2219 2220 size_t i; 2221 enum BM_MODE mode = -1; 2222 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i) 2223 { 2224 const struct bm *bme = bm_table + i; 2225 if ((bm & bme->mask) == bme->value) 2226 { 2227 mode = bme->mode; 2228 break; 2229 } 2230 } 2231 2232 int n = 0; 2233 switch (mode) 2234 { 2235 case BM_REG_IMM: 2236 case BM_RESERVED0: 2237 break; 2238 2239 case BM_OPR_B: 2240 case BM_OPR_W: 2241 case BM_OPR_L: 2242 case BM_OPR_REG: 2243 case BM_RESERVED1: 2244 n = x_opr_n_bytes (mra, 1); 2245 if (n < 0) 2246 return n; 2247 break; 2248 } 2249 2250 return n + 2; 2251 } 2252 2253 static int 2254 bm_rel_n_bytes (struct mem_read_abstraction_base *mra) 2255 { 2256 int n = 1 + bm_n_bytes (mra); 2257 2258 bfd_byte rb; 2259 int status = mra->read (mra, n - 2, 1, &rb); 2260 if (status != 0) 2261 return status; 2262 2263 if (rb & 0x80) 2264 n++; 2265 2266 return n; 2267 } 2268 2269 2270 2271 2273 2274 /* shift direction */ 2275 enum SB_DIR 2276 { 2277 SB_LEFT, 2278 SB_RIGHT 2279 }; 2280 2281 enum SB_TYPE 2282 { 2283 SB_ARITHMETIC, 2284 SB_LOGICAL 2285 }; 2286 2287 2288 enum SB_MODE 2289 { 2290 SB_REG_REG_N_EFF, 2291 SB_REG_REG_N, 2292 SB_REG_OPR_EFF, 2293 SB_ROT, 2294 SB_REG_OPR_OPR, 2295 SB_OPR_N 2296 }; 2297 2298 struct sb 2299 { 2300 uint8_t mask; 2301 uint8_t value; 2302 enum SB_MODE mode; 2303 }; 2304 2305 static const struct sb sb_table[] = { 2306 {0x30, 0x00, SB_REG_REG_N_EFF}, 2307 {0x30, 0x10, SB_REG_REG_N}, 2308 {0x34, 0x20, SB_REG_OPR_EFF}, 2309 {0x34, 0x24, SB_ROT}, 2310 {0x34, 0x30, SB_REG_OPR_OPR}, 2311 {0x34, 0x34, SB_OPR_N}, 2312 }; 2313 2314 static int 2315 shift_n_bytes (struct mem_read_abstraction_base *mra) 2316 { 2317 bfd_byte sb; 2318 int opr1, opr2; 2319 int status = mra->read (mra, 0, 1, &sb); 2320 if (status != 0) 2321 return status; 2322 2323 size_t i; 2324 enum SB_MODE mode = -1; 2325 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i) 2326 { 2327 const struct sb *sbe = sb_table + i; 2328 if ((sb & sbe->mask) == sbe->value) 2329 mode = sbe->mode; 2330 } 2331 2332 switch (mode) 2333 { 2334 case SB_REG_REG_N_EFF: 2335 return 2; 2336 case SB_REG_OPR_EFF: 2337 case SB_ROT: 2338 opr1 = x_opr_n_bytes (mra, 1); 2339 if (opr1 < 0) 2340 return opr1; 2341 return 2 + opr1; 2342 case SB_REG_OPR_OPR: 2343 opr1 = x_opr_n_bytes (mra, 1); 2344 if (opr1 < 0) 2345 return opr1; 2346 opr2 = 0; 2347 if ((sb & 0x30) != 0x20) 2348 { 2349 opr2 = x_opr_n_bytes (mra, opr1 + 1); 2350 if (opr2 < 0) 2351 return opr2; 2352 } 2353 return 2 + opr1 + opr2; 2354 default: 2355 return 3; 2356 } 2357 2358 /* not reached */ 2359 return -1; 2360 } 2361 2362 2364 static int 2365 mov_imm_opr_n_bytes (struct mem_read_abstraction_base *mra) 2366 { 2367 bfd_byte byte; 2368 int status = mra->read (mra, -1, 1, &byte); 2369 if (status < 0) 2370 return status; 2371 2372 int size = byte - 0x0c + 1; 2373 int n = x_opr_n_bytes (mra, size); 2374 if (n < 0) 2375 return n; 2376 2377 return size + n + 1; 2378 } 2379 2380 static int 2381 mov_imm_opr (struct mem_read_abstraction_base *mra, 2382 int *n_operands, struct operand **operand) 2383 { 2384 struct operand *op; 2385 bfd_byte byte; 2386 int status = mra->read (mra, -1, 1, &byte); 2387 if (status < 0) 2388 return status; 2389 2390 int size = byte - 0x0c + 1; 2391 uint32_t imm; 2392 if (decode_signed_value (mra, size, &imm)) 2393 return -1; 2394 2395 op = create_immediate_operand (imm); 2396 if (op == NULL) 2397 return -1; 2398 operand[(*n_operands)++] = op; 2399 op = x_opr_decode (mra, size); 2400 if (op == NULL) 2401 return -1; 2402 operand[(*n_operands)++] = op; 2403 return 0; 2404 } 2405 2406 2407 2409 static int 2410 ld_18bit_decode (struct mem_read_abstraction_base *mra, 2411 int *n_operands, struct operand **operand) 2412 { 2413 struct operand *op; 2414 size_t size = 3; 2415 bfd_byte buffer[3]; 2416 int status = mra->read (mra, 0, 2, buffer + 1); 2417 if (status < 0) 2418 return status; 2419 2420 status = mra->read (mra, -1, 1, buffer); 2421 if (status < 0) 2422 return status; 2423 2424 buffer[0] = (buffer[0] & 0x30) >> 4; 2425 2426 size_t i; 2427 uint32_t imm = 0; 2428 for (i = 0; i < size; ++i) 2429 { 2430 imm |= buffer[i] << (8 * (size - i - 1)); 2431 } 2432 2433 op = create_immediate_operand (imm); 2434 if (op == NULL) 2435 return -1; 2436 operand[(*n_operands)++] = op; 2437 return 0; 2438 } 2439 2440 2441 2443 /* Loop Primitives */ 2444 2445 enum LP_MODE { 2446 LP_REG, 2447 LP_XY, 2448 LP_OPR 2449 }; 2450 2451 struct lp 2452 { 2453 uint8_t mask; 2454 uint8_t value; 2455 enum LP_MODE mode; 2456 }; 2457 2458 static const struct lp lp_mode[] = { 2459 {0x08, 0x00, LP_REG}, 2460 {0x0C, 0x08, LP_XY}, 2461 {0x0C, 0x0C, LP_OPR}, 2462 }; 2463 2464 2465 static int 2466 loop_prim_n_bytes (struct mem_read_abstraction_base *mra) 2467 { 2468 int mx = 0; 2469 uint8_t lb; 2470 int status = mra->read (mra, mx++, 1, &lb); 2471 if (status < 0) 2472 return status; 2473 2474 enum LP_MODE mode = -1; 2475 size_t i; 2476 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i) 2477 { 2478 const struct lp *pb = lp_mode + i; 2479 if ((lb & pb->mask) == pb->value) 2480 { 2481 mode = pb->mode; 2482 break; 2483 } 2484 } 2485 2486 if (mode == LP_OPR) 2487 { 2488 int n = x_opr_n_bytes (mra, mx); 2489 if (n < 0) 2490 return n; 2491 mx += n; 2492 } 2493 2494 uint8_t rb; 2495 status = mra->read (mra, mx++, 1, &rb); 2496 if (status < 0) 2497 return status; 2498 if (rb & 0x80) 2499 mx++; 2500 2501 return mx + 1; 2502 } 2503 2504 2505 2506 2508 static enum optr 2509 exg_sex_discrim (struct mem_read_abstraction_base *mra, 2510 enum optr hint ATTRIBUTE_UNUSED) 2511 { 2512 uint8_t eb; 2513 int status = mra->read (mra, 0, 1, &eb); 2514 enum optr operator = OP_INVALID; 2515 if (status < 0) 2516 return operator; 2517 2518 struct operand *op0 = create_register_operand ((eb & 0xf0) >> 4); 2519 if (op0 == NULL) 2520 return -1; 2521 struct operand *op1 = create_register_operand (eb & 0xf); 2522 if (op1 == NULL) 2523 return -1; 2524 2525 int reg0 = ((struct register_operand *) op0)->reg; 2526 int reg1 = ((struct register_operand *) op1)->reg; 2527 if (reg0 >= 0 && reg0 < S12Z_N_REGISTERS 2528 && reg1 >= 0 && reg1 < S12Z_N_REGISTERS) 2529 { 2530 const struct reg *r0 = registers + reg0; 2531 const struct reg *r1 = registers + reg1; 2532 2533 operator = r0->bytes < r1->bytes ? OP_sex : OP_exg; 2534 } 2535 2536 free (op0); 2537 free (op1); 2538 2539 return operator; 2540 } 2541 2542 2543 static int 2544 exg_sex_decode (struct mem_read_abstraction_base *mra, 2545 int *n_operands, struct operand **operands) 2546 { 2547 struct operand *op; 2548 uint8_t eb; 2549 int status = mra->read (mra, 0, 1, &eb); 2550 if (status < 0) 2551 return status; 2552 2553 /* Ship out the operands. */ 2554 op = create_register_operand ((eb & 0xf0) >> 4); 2555 if (op == NULL) 2556 return -1; 2557 operands[(*n_operands)++] = op; 2558 op = create_register_operand (eb & 0xf); 2559 if (op == NULL) 2560 return -1; 2561 operands[(*n_operands)++] = op; 2562 return 0; 2563 } 2564 2565 static enum optr 2566 loop_primitive_discrim (struct mem_read_abstraction_base *mra, 2567 enum optr hint ATTRIBUTE_UNUSED) 2568 { 2569 uint8_t lb; 2570 int status = mra->read (mra, 0, 1, &lb); 2571 if (status < 0) 2572 return OP_INVALID; 2573 2574 enum optr opbase = (lb & 0x80) ? OP_dbNE : OP_tbNE; 2575 return opbase + ((lb & 0x70) >> 4); 2576 } 2577 2578 static int 2579 loop_primitive_decode (struct mem_read_abstraction_base *mra, 2580 int *n_operands, struct operand **operands) 2581 { 2582 struct operand *op; 2583 int n, offs = 1; 2584 uint8_t lb; 2585 int status = mra->read (mra, 0, 1, &lb); 2586 if (status < 0) 2587 return status; 2588 2589 enum LP_MODE mode = -1; 2590 size_t i; 2591 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i) 2592 { 2593 const struct lp *pb = lp_mode + i; 2594 if ((lb & pb->mask) == pb->value) 2595 { 2596 mode = pb->mode; 2597 break; 2598 } 2599 } 2600 2601 switch (mode) 2602 { 2603 case LP_REG: 2604 op = create_register_operand (lb & 0x07); 2605 if (op == NULL) 2606 return -1; 2607 operands[(*n_operands)++] = op; 2608 break; 2609 case LP_XY: 2610 op = create_register_operand ((lb & 0x01) + REG_X); 2611 if (op == NULL) 2612 return -1; 2613 operands[(*n_operands)++] = op; 2614 break; 2615 case LP_OPR: 2616 n = x_opr_n_bytes (mra, 1); 2617 if (n < 0) 2618 return n; 2619 offs += n; 2620 op = x_opr_decode_with_size (mra, 1, lb & 0x03); 2621 if (op == NULL) 2622 return -1; 2623 operands[(*n_operands)++] = op; 2624 break; 2625 } 2626 2627 return rel_15_7 (mra, offs + 1, n_operands, operands); 2628 } 2629 2630 2631 static enum optr 2632 shift_discrim (struct mem_read_abstraction_base *mra, 2633 enum optr hint ATTRIBUTE_UNUSED) 2634 { 2635 size_t i; 2636 uint8_t sb; 2637 int status = mra->read (mra, 0, 1, &sb); 2638 if (status < 0) 2639 return OP_INVALID; 2640 2641 enum SB_DIR dir = (sb & 0x40) ? SB_LEFT : SB_RIGHT; 2642 enum SB_TYPE type = (sb & 0x80) ? SB_ARITHMETIC : SB_LOGICAL; 2643 enum SB_MODE mode = -1; 2644 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i) 2645 { 2646 const struct sb *sbe = sb_table + i; 2647 if ((sb & sbe->mask) == sbe->value) 2648 mode = sbe->mode; 2649 } 2650 2651 if (mode == SB_ROT) 2652 return (dir == SB_LEFT) ? OP_rol : OP_ror; 2653 2654 if (type == SB_LOGICAL) 2655 return (dir == SB_LEFT) ? OP_lsl : OP_lsr; 2656 2657 return (dir == SB_LEFT) ? OP_asl : OP_asr; 2658 } 2659 2660 2661 static int 2662 shift_decode (struct mem_read_abstraction_base *mra, int *n_operands, 2663 struct operand **operands) 2664 { 2665 struct operand *op; 2666 size_t i; 2667 uint8_t byte; 2668 int status = mra->read (mra, -1, 1, &byte); 2669 if (status < 0) 2670 return status; 2671 2672 uint8_t sb; 2673 status = mra->read (mra, 0, 1, &sb); 2674 if (status < 0) 2675 return status; 2676 2677 enum SB_MODE mode = -1; 2678 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i) 2679 { 2680 const struct sb *sbe = sb_table + i; 2681 if ((sb & sbe->mask) == sbe->value) 2682 mode = sbe->mode; 2683 } 2684 2685 short osize = -1; 2686 switch (mode) 2687 { 2688 case SB_REG_OPR_EFF: 2689 case SB_ROT: 2690 case SB_REG_OPR_OPR: 2691 osize = sb & 0x03; 2692 break; 2693 case SB_OPR_N: 2694 { 2695 uint8_t xb; 2696 status = mra->read (mra, 1, 1, &xb); 2697 if (status < 0) 2698 return status; 2699 /* The size suffix is not printed if the OPR operand refers 2700 directly to a register, because the size is implied by the 2701 size of that register. */ 2702 if ((xb & 0xF8) != 0xB8) 2703 osize = sb & 0x03; 2704 } 2705 break; 2706 default: 2707 break; 2708 }; 2709 2710 /* Destination register */ 2711 switch (mode) 2712 { 2713 case SB_REG_REG_N_EFF: 2714 case SB_REG_REG_N: 2715 op = create_register_operand (byte & 0x07); 2716 if (op == NULL) 2717 return -1; 2718 operands[(*n_operands)++] = op; 2719 break; 2720 case SB_REG_OPR_EFF: 2721 case SB_REG_OPR_OPR: 2722 op = create_register_operand (byte & 0x07); 2723 if (op == NULL) 2724 return -1; 2725 operands[(*n_operands)++] = op; 2726 break; 2727 2728 case SB_ROT: 2729 op = x_opr_decode_with_size (mra, 1, osize); 2730 if (op == NULL) 2731 return -1; 2732 operands[(*n_operands)++] = op; 2733 break; 2734 2735 default: 2736 break; 2737 } 2738 2739 /* Source register */ 2740 switch (mode) 2741 { 2742 case SB_REG_REG_N_EFF: 2743 case SB_REG_REG_N: 2744 op = create_register_operand_with_size (sb & 0x07, osize); 2745 if (op == NULL) 2746 return -1; 2747 operands[(*n_operands)++] = op; 2748 break; 2749 2750 case SB_REG_OPR_OPR: 2751 op = x_opr_decode_with_size (mra, 1, osize); 2752 if (op == NULL) 2753 return -1; 2754 operands[(*n_operands)++] = op; 2755 break; 2756 2757 default: 2758 break; 2759 } 2760 2761 /* 3rd arg */ 2762 switch (mode) 2763 { 2764 case SB_REG_OPR_EFF: 2765 case SB_OPR_N: 2766 op = x_opr_decode_with_size (mra, 1, osize); 2767 if (op == NULL) 2768 return -1; 2769 operands[(*n_operands)++] = op; 2770 break; 2771 2772 case SB_REG_REG_N: 2773 { 2774 uint8_t xb; 2775 status = mra->read (mra, 1, 1, &xb); 2776 if (status < 0) 2777 return status; 2778 2779 /* This case is slightly unusual. 2780 If XB matches the binary pattern 0111XXXX, then instead of 2781 interpreting this as a general OPR postbyte in the IMMe4 mode, 2782 the XB byte is interpreted in s special way. */ 2783 if ((xb & 0xF0) == 0x70) 2784 { 2785 if (byte & 0x10) 2786 { 2787 int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1); 2788 op = create_immediate_operand (shift); 2789 if (op == NULL) 2790 return -1; 2791 operands[(*n_operands)++] = op; 2792 } 2793 else 2794 { 2795 /* This should not happen. */ 2796 abort (); 2797 } 2798 } 2799 else 2800 { 2801 op = x_opr_decode (mra, 1); 2802 if (op == NULL) 2803 return -1; 2804 operands[(*n_operands)++] = op; 2805 } 2806 } 2807 break; 2808 case SB_REG_OPR_OPR: 2809 { 2810 uint8_t xb; 2811 int n = x_opr_n_bytes (mra, 1); 2812 if (n < 0) 2813 return n; 2814 status = mra->read (mra, 1 + n, 1, &xb); 2815 if (status < 0) 2816 return status; 2817 2818 if ((xb & 0xF0) == 0x70) 2819 { 2820 int imm = xb & 0x0F; 2821 imm <<= 1; 2822 imm |= (sb & 0x08) >> 3; 2823 op = create_immediate_operand (imm); 2824 if (op == NULL) 2825 return -1; 2826 operands[(*n_operands)++] = op; 2827 } 2828 else 2829 { 2830 op = x_opr_decode (mra, 1 + n); 2831 if (op == NULL) 2832 return -1; 2833 operands[(*n_operands)++] = op; 2834 } 2835 } 2836 break; 2837 default: 2838 break; 2839 } 2840 2841 switch (mode) 2842 { 2843 case SB_REG_REG_N_EFF: 2844 case SB_REG_OPR_EFF: 2845 case SB_OPR_N: 2846 { 2847 int imm = (sb & 0x08) ? 2 : 1; 2848 op = create_immediate_operand (imm); 2849 if (op == NULL) 2850 return -1; 2851 operands[(*n_operands)++] = op; 2852 } 2853 break; 2854 2855 default: 2856 break; 2857 } 2858 return 0; 2859 } 2860 2861 static enum optr 2862 psh_pul_discrim (struct mem_read_abstraction_base *mra, 2863 enum optr hint ATTRIBUTE_UNUSED) 2864 { 2865 uint8_t byte; 2866 int status = mra->read (mra, 0, 1, &byte); 2867 if (status != 0) 2868 return OP_INVALID; 2869 2870 return (byte & 0x80) ? OP_pull: OP_push; 2871 } 2872 2873 2874 static int 2875 psh_pul_decode (struct mem_read_abstraction_base *mra, 2876 int *n_operands, struct operand **operand) 2877 { 2878 struct operand *op; 2879 uint8_t byte; 2880 int status = mra->read (mra, 0, 1, &byte); 2881 if (status != 0) 2882 return status; 2883 int bit; 2884 if (byte & 0x40) 2885 { 2886 if ((byte & 0x3F) == 0) 2887 { 2888 op = create_register_all16_operand (); 2889 if (op == NULL) 2890 return -1; 2891 operand[(*n_operands)++] = op; 2892 } 2893 else 2894 for (bit = 5; bit >= 0; --bit) 2895 { 2896 if (byte & (0x1 << bit)) 2897 { 2898 op = create_register_operand (oprregs2[bit]); 2899 if (op == NULL) 2900 return -1; 2901 operand[(*n_operands)++] = op; 2902 } 2903 } 2904 } 2905 else 2906 { 2907 if ((byte & 0x3F) == 0) 2908 { 2909 op = create_register_all_operand (); 2910 if (op == NULL) 2911 return -1; 2912 operand[(*n_operands)++] = op; 2913 } 2914 else 2915 for (bit = 5; bit >= 0; --bit) 2916 { 2917 if (byte & (0x1 << bit)) 2918 { 2919 op = create_register_operand (oprregs1[bit]); 2920 if (op == NULL) 2921 return -1; 2922 operand[(*n_operands)++] = op; 2923 } 2924 } 2925 } 2926 return 0; 2927 } 2928 2929 static enum optr 2930 bit_field_discrim (struct mem_read_abstraction_base *mra, 2931 enum optr hint ATTRIBUTE_UNUSED) 2932 { 2933 int status; 2934 bfd_byte bb; 2935 status = mra->read (mra, 0, 1, &bb); 2936 if (status != 0) 2937 return OP_INVALID; 2938 2939 return (bb & 0x80) ? OP_bfins : OP_bfext; 2940 } 2941 2942 static int 2943 bit_field_decode (struct mem_read_abstraction_base *mra, 2944 int *n_operands, struct operand **operands) 2945 { 2946 struct operand *op; 2947 int status; 2948 2949 bfd_byte byte2; 2950 status = mra->read (mra, -1, 1, &byte2); 2951 if (status != 0) 2952 return status; 2953 2954 bfd_byte bb; 2955 status = mra->read (mra, 0, 1, &bb); 2956 if (status != 0) 2957 return status; 2958 2959 enum BB_MODE mode = -1; 2960 size_t i; 2961 const struct opr_bb *bbs = 0; 2962 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i) 2963 { 2964 bbs = bb_modes + i; 2965 if ((bb & bbs->mask) == bbs->value) 2966 { 2967 mode = bbs->mode; 2968 break; 2969 } 2970 } 2971 int reg1 = byte2 & 0x07; 2972 /* First operand */ 2973 switch (mode) 2974 { 2975 case BB_REG_REG_REG: 2976 case BB_REG_REG_IMM: 2977 case BB_REG_OPR_REG: 2978 case BB_REG_OPR_IMM: 2979 op = create_register_operand (reg1); 2980 if (op == NULL) 2981 return -1; 2982 operands[(*n_operands)++] = op; 2983 break; 2984 case BB_OPR_REG_REG: 2985 op = x_opr_decode_with_size (mra, 1, (bb >> 2) & 0x03); 2986 if (op == NULL) 2987 return -1; 2988 operands[(*n_operands)++] = op; 2989 break; 2990 case BB_OPR_REG_IMM: 2991 op = x_opr_decode_with_size (mra, 2, (bb >> 2) & 0x03); 2992 if (op == NULL) 2993 return -1; 2994 operands[(*n_operands)++] = op; 2995 break; 2996 } 2997 2998 /* Second operand */ 2999 switch (mode) 3000 { 3001 case BB_REG_REG_REG: 3002 case BB_REG_REG_IMM: 3003 { 3004 int reg_src = (bb >> 2) & 0x07; 3005 op = create_register_operand (reg_src); 3006 if (op == NULL) 3007 return -1; 3008 operands[(*n_operands)++] = op; 3009 } 3010 break; 3011 case BB_OPR_REG_REG: 3012 case BB_OPR_REG_IMM: 3013 { 3014 int reg_src = (byte2 & 0x07); 3015 op = create_register_operand (reg_src); 3016 if (op == NULL) 3017 return -1; 3018 operands[(*n_operands)++] = op; 3019 } 3020 break; 3021 case BB_REG_OPR_REG: 3022 op = x_opr_decode_with_size (mra, 1, (bb >> 2) & 0x03); 3023 if (op == NULL) 3024 return -1; 3025 operands[(*n_operands)++] = op; 3026 break; 3027 case BB_REG_OPR_IMM: 3028 op = x_opr_decode_with_size (mra, 2, (bb >> 2) & 0x03); 3029 if (op == NULL) 3030 return -1; 3031 operands[(*n_operands)++] = op; 3032 break; 3033 } 3034 3035 /* Third operand */ 3036 switch (mode) 3037 { 3038 case BB_REG_REG_REG: 3039 case BB_OPR_REG_REG: 3040 case BB_REG_OPR_REG: 3041 { 3042 int reg_parm = bb & 0x03; 3043 op = create_register_operand (reg_parm); 3044 if (op == NULL) 3045 return -1; 3046 operands[(*n_operands)++] = op; 3047 } 3048 break; 3049 case BB_REG_REG_IMM: 3050 case BB_OPR_REG_IMM: 3051 case BB_REG_OPR_IMM: 3052 { 3053 bfd_byte i1; 3054 status = mra->read (mra, 1, 1, &i1); 3055 if (status < 0) 3056 return status; 3057 int offset = i1 & 0x1f; 3058 int width = bb & 0x03; 3059 width <<= 3; 3060 width |= i1 >> 5; 3061 op = create_bitfield_operand (width, offset); 3062 if (op == NULL) 3063 return -1; 3064 operands[(*n_operands)++] = op; 3065 } 3066 break; 3067 } 3068 return 0; 3069 } 3070 3071 3072 /* Decode the next instruction at MRA, according to OPC. 3073 The operation to be performed is returned. 3074 The number of operands, will be placed in N_OPERANDS. 3075 The operands themselved into OPERANDS. */ 3076 static enum optr 3077 decode_operation (const struct opcode *opc, 3078 struct mem_read_abstraction_base *mra, 3079 int *n_operands, struct operand **operands) 3080 { 3081 enum optr op = opc->operator; 3082 if (opc->discriminator) 3083 { 3084 op = opc->discriminator (mra, opc->operator); 3085 if (op == OP_INVALID) 3086 return op; 3087 } 3088 3089 if (opc->operands) 3090 if (opc->operands (mra, n_operands, operands) < 0) 3091 return OP_INVALID; 3092 3093 if (opc->operands2) 3094 if (opc->operands2 (mra, n_operands, operands) < 0) 3095 return OP_INVALID; 3096 3097 return op; 3098 } 3099 3100 int 3101 decode_s12z (enum optr *myoperator, short *osize, 3102 int *n_operands, struct operand **operands, 3103 struct mem_read_abstraction_base *mra) 3104 { 3105 int n_bytes = 0; 3106 bfd_byte byte; 3107 3108 int status = mra->read (mra, 0, 1, &byte); 3109 if (status < 0) 3110 return status; 3111 3112 mra->advance (mra); 3113 3114 const struct opcode *opc = page1 + byte; 3115 if (byte == PAGE2_PREBYTE) 3116 { 3117 /* Opcodes in page2 have an additional byte */ 3118 n_bytes++; 3119 3120 bfd_byte byte2; 3121 status = mra->read (mra, 0, 1, &byte2); 3122 if (status < 0) 3123 return status; 3124 mra->advance (mra); 3125 opc = page2 + byte2; 3126 } 3127 *myoperator = decode_operation (opc, mra, n_operands, operands); 3128 *osize = opc->osize; 3129 3130 /* Return the number of bytes in the instruction. */ 3131 if (*myoperator != OP_INVALID && opc->insn_bytes) 3132 { 3133 int n = opc->insn_bytes (mra); 3134 if (n < 0) 3135 return n; 3136 n_bytes += n; 3137 } 3138 else 3139 n_bytes += 1; 3140 3141 return n_bytes; 3142 } 3143 3144
Indexes created Sat Apr 11 00:22:22 UTC 2026