profile-fr500.c revision 1.1.1.11
1 /* frv simulator fr500 dependent profiling code. 2 3 Copyright (C) 1998-2025 Free Software Foundation, Inc. 4 Contributed by Red Hat 5 6 This file is part of the GNU simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #define WANT_CPU 25 #define WANT_CPU_FRVBF 26 27 #include "sim-main.h" 28 #include "bfd.h" 29 30 #if WITH_PROFILE_MODEL_P 31 32 #include "profile.h" 33 #include "profile-fr500.h" 34 35 /* Initialize cycle counting for an insn. 36 FIRST_P is non-zero if this is the first insn in a set of parallel 37 insns. */ 38 void 39 fr500_model_insn_before (SIM_CPU *cpu, int first_p) 40 { 41 if (first_p) 42 { 43 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 44 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); 45 ps->cur_gr_complex = ps->prev_gr_complex; 46 d->cur_fpop = d->prev_fpop; 47 d->cur_media = d->prev_media; 48 d->cur_cc_complex = d->prev_cc_complex; 49 } 50 } 51 52 /* Record the cycles computed for an insn. 53 LAST_P is non-zero if this is the last insn in a set of parallel insns, 54 and we update the total cycle count. 55 CYCLES is the cycle count of the insn. */ 56 void 57 fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) 58 { 59 if (last_p) 60 { 61 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 62 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); 63 ps->prev_gr_complex = ps->cur_gr_complex; 64 d->prev_fpop = d->cur_fpop; 65 d->prev_media = d->cur_media; 66 d->prev_cc_complex = d->cur_cc_complex; 67 } 68 } 69 70 static void 71 set_use_is_fpop (SIM_CPU *cpu, INT fr) 72 { 73 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 74 fr500_reset_fr_flags (cpu, (fr)); 75 d->cur_fpop |= (((DI)1) << (fr)); 76 } 77 78 static void 79 set_use_not_fpop (SIM_CPU *cpu, INT fr) 80 { 81 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 82 d->cur_fpop &= ~(((DI)1) << (fr)); 83 } 84 85 static int 86 use_is_fpop (SIM_CPU *cpu, INT fr) 87 { 88 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 89 return d->prev_fpop & (((DI)1) << (fr)); 90 } 91 92 static void 93 set_use_is_media ( SIM_CPU *cpu, INT fr) 94 { 95 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 96 fr500_reset_fr_flags (cpu, (fr)); 97 d->cur_media |= (((DI)1) << (fr)); 98 } 99 100 static void 101 set_use_not_media (SIM_CPU *cpu, INT fr) 102 { 103 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 104 d->cur_media &= ~(((DI)1) << (fr)); 105 } 106 107 static int 108 use_is_media (SIM_CPU *cpu, INT fr) 109 { 110 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 111 return d->prev_media & (((DI)1) << (fr)); 112 } 113 114 static void 115 set_use_is_cc_complex (SIM_CPU *cpu, INT cc) 116 { 117 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 118 fr500_reset_cc_flags (cpu, cc); 119 d->cur_cc_complex |= (((DI)1) << (cc)); 120 } 121 122 static void 123 set_use_not_cc_complex (SIM_CPU *cpu, INT cc) 124 { 125 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 126 d->cur_cc_complex &= ~(((DI)1) << (cc)); 127 } 128 129 #if 0 130 static int 131 use_is_cc_complex (SIM_CPU *cpu, INT cc) 132 { 133 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu); 134 return d->prev_cc_complex & (((DI)1) << (cc)); 135 } 136 #endif 137 138 void 139 fr500_reset_fr_flags (SIM_CPU *cpu, INT fr) 140 { 141 set_use_not_fpop (cpu, fr); 142 set_use_not_media (cpu, fr); 143 } 144 145 void 146 fr500_reset_cc_flags (SIM_CPU *cpu, INT cc) 147 { 148 set_use_not_cc_complex (cpu, cc); 149 } 150 151 /* Latency of floating point registers may be less than recorded when followed 152 by another floating point insn. */ 153 static void 154 adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, 155 int cycles) 156 { 157 /* If the registers were previously used in a floating point op, 158 then their latency will be less than previously recorded. 159 See Table 13-13 in the LSI. */ 160 if (in_FRi >= 0) 161 { 162 if (use_is_fpop (cpu, in_FRi)) 163 decrease_FR_busy (cpu, in_FRi, cycles); 164 else 165 enforce_full_fr_latency (cpu, in_FRi); 166 } 167 168 if (in_FRj >= 0 && in_FRj != in_FRi) 169 { 170 if (use_is_fpop (cpu, in_FRj)) 171 decrease_FR_busy (cpu, in_FRj, cycles); 172 else 173 enforce_full_fr_latency (cpu, in_FRj); 174 } 175 176 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) 177 { 178 if (use_is_fpop (cpu, out_FRk)) 179 decrease_FR_busy (cpu, out_FRk, cycles); 180 else 181 enforce_full_fr_latency (cpu, out_FRk); 182 } 183 } 184 185 /* Latency of floating point registers may be less than recorded when followed 186 by another floating point insn. */ 187 static void 188 adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, 189 int cycles) 190 { 191 /* If the registers were previously used in a floating point op, 192 then their latency will be less than previously recorded. 193 See Table 13-13 in the LSI. */ 194 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); 195 if (in_FRi >= 0) ++in_FRi; 196 if (in_FRj >= 0) ++in_FRj; 197 if (out_FRk >= 0) ++out_FRk; 198 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); 199 } 200 201 /* Latency of floating point registers is less than recorded when followed 202 by another floating point insn. */ 203 static void 204 restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, 205 int cycles) 206 { 207 /* If the registers were previously used in a floating point op, 208 then their latency will be less than previously recorded. 209 See Table 13-13 in the LSI. */ 210 if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi)) 211 increase_FR_busy (cpu, in_FRi, cycles); 212 if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj)) 213 increase_FR_busy (cpu, in_FRj, cycles); 214 if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk)) 215 increase_FR_busy (cpu, out_FRk, cycles); 216 } 217 218 /* Latency of floating point registers is less than recorded when followed 219 by another floating point insn. */ 220 static void 221 restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk, 222 int cycles) 223 { 224 /* If the registers were previously used in a floating point op, 225 then their latency will be less than previously recorded. 226 See Table 13-13 in the LSI. */ 227 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); 228 if (in_FRi >= 0) ++in_FRi; 229 if (in_FRj >= 0) ++in_FRj; 230 if (out_FRk >= 0) ++out_FRk; 231 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles); 232 } 233 234 int 235 frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc, 236 int unit_num, int referenced) 237 { 238 return idesc->timing->units[unit_num].done; 239 } 240 241 int 242 frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc, 243 int unit_num, int referenced, 244 INT in_GRi, INT in_GRj, INT out_GRk, 245 INT out_ICCi_1) 246 { 247 int cycles; 248 249 if (model_insn == FRV_INSN_MODEL_PASS_1) 250 { 251 /* icc0-icc4 are the upper 4 fields of the CCR. */ 252 if (out_ICCi_1 >= 0) 253 out_ICCi_1 += 4; 254 255 /* The entire VLIW insn must wait if there is a dependency on a register 256 which is not ready yet. 257 The latency of the registers may be less than previously recorded, 258 depending on how they were used previously. 259 See Table 13-8 in the LSI. */ 260 if (in_GRi != out_GRk && in_GRi >= 0) 261 { 262 if (use_is_gr_complex (cpu, in_GRi)) 263 decrease_GR_busy (cpu, in_GRi, 1); 264 } 265 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) 266 { 267 if (use_is_gr_complex (cpu, in_GRj)) 268 decrease_GR_busy (cpu, in_GRj, 1); 269 } 270 vliw_wait_for_GR (cpu, in_GRi); 271 vliw_wait_for_GR (cpu, in_GRj); 272 vliw_wait_for_GR (cpu, out_GRk); 273 vliw_wait_for_CCR (cpu, out_ICCi_1); 274 handle_resource_wait (cpu); 275 load_wait_for_GR (cpu, in_GRi); 276 load_wait_for_GR (cpu, in_GRj); 277 load_wait_for_GR (cpu, out_GRk); 278 trace_vliw_wait_cycles (cpu); 279 return 0; 280 } 281 282 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */ 283 cycles = idesc->timing->units[unit_num].done; 284 return cycles; 285 } 286 287 int 288 frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc, 289 int unit_num, int referenced, 290 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) 291 { 292 int cycles; 293 /* icc0-icc4 are the upper 4 fields of the CCR. */ 294 if (out_ICCi_1 >= 0) 295 out_ICCi_1 += 4; 296 297 if (model_insn == FRV_INSN_MODEL_PASS_1) 298 { 299 /* The entire VLIW insn must wait if there is a dependency on a register 300 which is not ready yet. 301 The latency of the registers may be less than previously recorded, 302 depending on how they were used previously. 303 See Table 13-8 in the LSI. */ 304 if (in_GRi != out_GRk && in_GRi >= 0) 305 { 306 if (use_is_gr_complex (cpu, in_GRi)) 307 decrease_GR_busy (cpu, in_GRi, 1); 308 } 309 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) 310 { 311 if (use_is_gr_complex (cpu, in_GRj)) 312 decrease_GR_busy (cpu, in_GRj, 1); 313 } 314 vliw_wait_for_GR (cpu, in_GRi); 315 vliw_wait_for_GR (cpu, in_GRj); 316 vliw_wait_for_GRdouble (cpu, out_GRk); 317 vliw_wait_for_CCR (cpu, out_ICCi_1); 318 handle_resource_wait (cpu); 319 load_wait_for_GR (cpu, in_GRi); 320 load_wait_for_GR (cpu, in_GRj); 321 load_wait_for_GRdouble (cpu, out_GRk); 322 trace_vliw_wait_cycles (cpu); 323 return 0; 324 } 325 326 /* GRk has a latency of 2 cycles. */ 327 cycles = idesc->timing->units[unit_num].done; 328 update_GRdouble_latency (cpu, out_GRk, cycles + 2); 329 set_use_is_gr_complex (cpu, out_GRk); 330 set_use_is_gr_complex (cpu, out_GRk + 1); 331 332 /* ICCi_1 has a latency of 1 cycle. */ 333 update_CCR_latency (cpu, out_ICCi_1, cycles + 1); 334 335 return cycles; 336 } 337 338 int 339 frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc, 340 int unit_num, int referenced, 341 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) 342 { 343 int cycles; 344 FRV_VLIW *vliw; 345 int slot; 346 347 /* icc0-icc4 are the upper 4 fields of the CCR. */ 348 if (out_ICCi_1 >= 0) 349 out_ICCi_1 += 4; 350 351 vliw = CPU_VLIW (cpu); 352 slot = vliw->next_slot - 1; 353 slot = (*vliw->current_vliw)[slot] - UNIT_I0; 354 355 if (model_insn == FRV_INSN_MODEL_PASS_1) 356 { 357 /* The entire VLIW insn must wait if there is a dependency on a register 358 which is not ready yet. 359 The latency of the registers may be less than previously recorded, 360 depending on how they were used previously. 361 See Table 13-8 in the LSI. */ 362 if (in_GRi != out_GRk && in_GRi >= 0) 363 { 364 if (use_is_gr_complex (cpu, in_GRi)) 365 decrease_GR_busy (cpu, in_GRi, 1); 366 } 367 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) 368 { 369 if (use_is_gr_complex (cpu, in_GRj)) 370 decrease_GR_busy (cpu, in_GRj, 1); 371 } 372 vliw_wait_for_GR (cpu, in_GRi); 373 vliw_wait_for_GR (cpu, in_GRj); 374 vliw_wait_for_GR (cpu, out_GRk); 375 vliw_wait_for_CCR (cpu, out_ICCi_1); 376 vliw_wait_for_idiv_resource (cpu, slot); 377 handle_resource_wait (cpu); 378 load_wait_for_GR (cpu, in_GRi); 379 load_wait_for_GR (cpu, in_GRj); 380 load_wait_for_GR (cpu, out_GRk); 381 trace_vliw_wait_cycles (cpu); 382 return 0; 383 } 384 385 /* GRk has a latency of 19 cycles! */ 386 cycles = idesc->timing->units[unit_num].done; 387 update_GR_latency (cpu, out_GRk, cycles + 19); 388 set_use_is_gr_complex (cpu, out_GRk); 389 390 /* ICCi_1 has a latency of 19 cycles. */ 391 update_CCR_latency (cpu, out_ICCi_1, cycles + 19); 392 set_use_is_cc_complex (cpu, out_ICCi_1); 393 394 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 395 { 396 /* GNER has a latency of 18 cycles. */ 397 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18); 398 } 399 400 /* the idiv resource has a latency of 18 cycles! */ 401 update_idiv_resource_latency (cpu, slot, cycles + 18); 402 403 return cycles; 404 } 405 406 int 407 frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc, 408 int unit_num, int referenced, 409 INT in_GRi, INT in_GRj, 410 INT in_ICCi_2, INT in_FCCi_2) 411 { 412 int cycles; 413 FRV_PROFILE_STATE *ps; 414 415 if (model_insn == FRV_INSN_MODEL_PASS_1) 416 { 417 /* icc0-icc4 are the upper 4 fields of the CCR. */ 418 if (in_ICCi_2 >= 0) 419 in_ICCi_2 += 4; 420 421 /* The entire VLIW insn must wait if there is a dependency on a register 422 which is not ready yet. 423 The latency of the registers may be less than previously recorded, 424 depending on how they were used previously. 425 See Table 13-8 in the LSI. */ 426 if (in_GRi >= 0) 427 { 428 if (use_is_gr_complex (cpu, in_GRi)) 429 decrease_GR_busy (cpu, in_GRi, 1); 430 } 431 if (in_GRj != in_GRi && in_GRj >= 0) 432 { 433 if (use_is_gr_complex (cpu, in_GRj)) 434 decrease_GR_busy (cpu, in_GRj, 1); 435 } 436 vliw_wait_for_GR (cpu, in_GRi); 437 vliw_wait_for_GR (cpu, in_GRj); 438 vliw_wait_for_CCR (cpu, in_ICCi_2); 439 vliw_wait_for_CCR (cpu, in_FCCi_2); 440 handle_resource_wait (cpu); 441 load_wait_for_GR (cpu, in_GRi); 442 load_wait_for_GR (cpu, in_GRj); 443 trace_vliw_wait_cycles (cpu); 444 return 0; 445 } 446 447 /* When counting branches taken or not taken, don't consider branches after 448 the first taken branch in a vliw insn. */ 449 ps = CPU_PROFILE_STATE (cpu); 450 if (! ps->vliw_branch_taken) 451 { 452 /* (1 << 4): The pc is the 5th element in inputs, outputs. 453 ??? can be cleaned up */ 454 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); 455 int taken = (referenced & (1 << 4)) != 0; 456 if (taken) 457 { 458 ++PROFILE_MODEL_TAKEN_COUNT (p); 459 ps->vliw_branch_taken = 1; 460 } 461 else 462 ++PROFILE_MODEL_UNTAKEN_COUNT (p); 463 } 464 465 cycles = idesc->timing->units[unit_num].done; 466 return cycles; 467 } 468 469 int 470 frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc, 471 int unit_num, int referenced, 472 INT in_GRi, INT in_GRj, 473 INT in_ICCi_2, INT in_FCCi_2) 474 { 475 int cycles; 476 477 if (model_insn == FRV_INSN_MODEL_PASS_1) 478 { 479 /* icc0-icc4 are the upper 4 fields of the CCR. */ 480 if (in_ICCi_2 >= 0) 481 in_ICCi_2 += 4; 482 483 /* The entire VLIW insn must wait if there is a dependency on a register 484 which is not ready yet. 485 The latency of the registers may be less than previously recorded, 486 depending on how they were used previously. 487 See Table 13-8 in the LSI. */ 488 if (in_GRi >= 0) 489 { 490 if (use_is_gr_complex (cpu, in_GRi)) 491 decrease_GR_busy (cpu, in_GRi, 1); 492 } 493 if (in_GRj != in_GRi && in_GRj >= 0) 494 { 495 if (use_is_gr_complex (cpu, in_GRj)) 496 decrease_GR_busy (cpu, in_GRj, 1); 497 } 498 vliw_wait_for_GR (cpu, in_GRi); 499 vliw_wait_for_GR (cpu, in_GRj); 500 vliw_wait_for_CCR (cpu, in_ICCi_2); 501 vliw_wait_for_CCR (cpu, in_FCCi_2); 502 handle_resource_wait (cpu); 503 load_wait_for_GR (cpu, in_GRi); 504 load_wait_for_GR (cpu, in_GRj); 505 trace_vliw_wait_cycles (cpu); 506 return 0; 507 } 508 509 cycles = idesc->timing->units[unit_num].done; 510 return cycles; 511 } 512 513 int 514 frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc, 515 int unit_num, int referenced, 516 INT in_ICCi_3, INT in_FCCi_3) 517 { 518 int cycles; 519 520 if (model_insn == FRV_INSN_MODEL_PASS_1) 521 { 522 /* icc0-icc4 are the upper 4 fields of the CCR. */ 523 if (in_ICCi_3 >= 0) 524 in_ICCi_3 += 4; 525 526 /* The entire VLIW insn must wait if there is a dependency on a register 527 which is not ready yet. */ 528 vliw_wait_for_CCR (cpu, in_ICCi_3); 529 vliw_wait_for_CCR (cpu, in_FCCi_3); 530 handle_resource_wait (cpu); 531 trace_vliw_wait_cycles (cpu); 532 return 0; 533 } 534 535 cycles = idesc->timing->units[unit_num].done; 536 return cycles; 537 } 538 539 int 540 frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc, 541 int unit_num, int referenced, 542 INT in_GRk) 543 { 544 int cycles; 545 546 if (model_insn == FRV_INSN_MODEL_PASS_1) 547 { 548 /* Wait for both GNER registers or just the one specified. */ 549 if (in_GRk == -1) 550 { 551 vliw_wait_for_SPR (cpu, H_SPR_GNER0); 552 vliw_wait_for_SPR (cpu, H_SPR_GNER1); 553 } 554 else 555 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); 556 handle_resource_wait (cpu); 557 trace_vliw_wait_cycles (cpu); 558 return 0; 559 } 560 561 cycles = idesc->timing->units[unit_num].done; 562 return cycles; 563 } 564 565 int 566 frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, 567 int unit_num, int referenced, 568 INT in_FRk) 569 { 570 int cycles; 571 572 if (model_insn == FRV_INSN_MODEL_PASS_1) 573 { 574 /* Wait for both GNER registers or just the one specified. */ 575 if (in_FRk == -1) 576 { 577 vliw_wait_for_SPR (cpu, H_SPR_FNER0); 578 vliw_wait_for_SPR (cpu, H_SPR_FNER1); 579 } 580 else 581 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); 582 handle_resource_wait (cpu); 583 trace_vliw_wait_cycles (cpu); 584 return 0; 585 } 586 587 cycles = idesc->timing->units[unit_num].done; 588 return cycles; 589 } 590 591 int 592 frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc, 593 int unit_num, int referenced, 594 INT in_GRk, INT in_FRk) 595 { 596 int cycles; 597 598 if (model_insn == FRV_INSN_MODEL_PASS_1) 599 { 600 /* If GR is specified, then FR is not and vice-versa. If neither is 601 then it's a commitga or commitfa. Check the insn attribute to 602 figure out which. */ 603 if (in_GRk != -1) 604 vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); 605 else if (in_FRk != -1) 606 vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); 607 else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS)) 608 { 609 vliw_wait_for_SPR (cpu, H_SPR_FNER0); 610 vliw_wait_for_SPR (cpu, H_SPR_FNER1); 611 } 612 else 613 { 614 vliw_wait_for_SPR (cpu, H_SPR_GNER0); 615 vliw_wait_for_SPR (cpu, H_SPR_GNER1); 616 } 617 handle_resource_wait (cpu); 618 trace_vliw_wait_cycles (cpu); 619 return 0; 620 } 621 622 cycles = idesc->timing->units[unit_num].done; 623 return cycles; 624 } 625 626 int 627 frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, 628 int unit_num, int referenced, 629 INT out_GRkhi, INT out_GRklo) 630 { 631 int cycles; 632 633 if (model_insn == FRV_INSN_MODEL_PASS_1) 634 { 635 /* The entire VLIW insn must wait if there is a dependency on a GR 636 which is not ready yet. */ 637 vliw_wait_for_GR (cpu, out_GRkhi); 638 vliw_wait_for_GR (cpu, out_GRklo); 639 handle_resource_wait (cpu); 640 load_wait_for_GR (cpu, out_GRkhi); 641 load_wait_for_GR (cpu, out_GRklo); 642 trace_vliw_wait_cycles (cpu); 643 return 0; 644 } 645 646 /* GRk is available immediately to the next VLIW insn. */ 647 cycles = idesc->timing->units[unit_num].done; 648 649 set_use_not_gr_complex (cpu, out_GRkhi); 650 set_use_not_gr_complex (cpu, out_GRklo); 651 652 return cycles; 653 } 654 655 int 656 frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, 657 int unit_num, int referenced, 658 INT in_GRi, INT in_GRj, 659 INT out_GRk, INT out_GRdoublek) 660 { 661 int cycles; 662 663 if (model_insn == FRV_INSN_MODEL_PASS_1) 664 { 665 /* The entire VLIW insn must wait if there is a dependency on a register 666 which is not ready yet. 667 The latency of the registers may be less than previously recorded, 668 depending on how they were used previously. 669 See Table 13-8 in the LSI. */ 670 if (in_GRi != out_GRk && in_GRi != out_GRdoublek 671 && in_GRi != out_GRdoublek + 1 && in_GRi >= 0) 672 { 673 if (use_is_gr_complex (cpu, in_GRi)) 674 decrease_GR_busy (cpu, in_GRi, 1); 675 } 676 if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek 677 && in_GRj != out_GRdoublek + 1 && in_GRj >= 0) 678 679 { 680 if (use_is_gr_complex (cpu, in_GRj)) 681 decrease_GR_busy (cpu, in_GRj, 1); 682 } 683 vliw_wait_for_GR (cpu, in_GRi); 684 vliw_wait_for_GR (cpu, in_GRj); 685 vliw_wait_for_GR (cpu, out_GRk); 686 vliw_wait_for_GRdouble (cpu, out_GRdoublek); 687 handle_resource_wait (cpu); 688 load_wait_for_GR (cpu, in_GRi); 689 load_wait_for_GR (cpu, in_GRj); 690 load_wait_for_GR (cpu, out_GRk); 691 load_wait_for_GRdouble (cpu, out_GRdoublek); 692 trace_vliw_wait_cycles (cpu); 693 return 0; 694 } 695 696 cycles = idesc->timing->units[unit_num].done; 697 698 /* The latency of GRk for a load will depend on how long it takes to retrieve 699 the the data from the cache or memory. */ 700 update_GR_latency_for_load (cpu, out_GRk, cycles); 701 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); 702 703 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 704 { 705 /* GNER has a latency of 2 cycles. */ 706 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); 707 update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); 708 } 709 710 if (out_GRk >= 0) 711 set_use_is_gr_complex (cpu, out_GRk); 712 if (out_GRdoublek != -1) 713 { 714 set_use_is_gr_complex (cpu, out_GRdoublek); 715 set_use_is_gr_complex (cpu, out_GRdoublek + 1); 716 } 717 718 return cycles; 719 } 720 721 int 722 frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, 723 int unit_num, int referenced, 724 INT in_GRi, INT in_GRj, 725 INT in_GRk, INT in_GRdoublek) 726 { 727 int cycles; 728 729 if (model_insn == FRV_INSN_MODEL_PASS_1) 730 { 731 /* The entire VLIW insn must wait if there is a dependency on a register 732 which is not ready yet. 733 The latency of the registers may be less than previously recorded, 734 depending on how they were used previously. 735 See Table 13-8 in the LSI. */ 736 if (in_GRi >= 0) 737 { 738 if (use_is_gr_complex (cpu, in_GRi)) 739 decrease_GR_busy (cpu, in_GRi, 1); 740 } 741 if (in_GRj != in_GRi && in_GRj >= 0) 742 { 743 if (use_is_gr_complex (cpu, in_GRj)) 744 decrease_GR_busy (cpu, in_GRj, 1); 745 } 746 if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0) 747 { 748 if (use_is_gr_complex (cpu, in_GRk)) 749 decrease_GR_busy (cpu, in_GRk, 1); 750 } 751 if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj 752 && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj 753 && in_GRdoublek >= 0) 754 { 755 if (use_is_gr_complex (cpu, in_GRdoublek)) 756 decrease_GR_busy (cpu, in_GRdoublek, 1); 757 if (use_is_gr_complex (cpu, in_GRdoublek + 1)) 758 decrease_GR_busy (cpu, in_GRdoublek + 1, 1); 759 } 760 vliw_wait_for_GR (cpu, in_GRi); 761 vliw_wait_for_GR (cpu, in_GRj); 762 vliw_wait_for_GR (cpu, in_GRk); 763 vliw_wait_for_GRdouble (cpu, in_GRdoublek); 764 handle_resource_wait (cpu); 765 load_wait_for_GR (cpu, in_GRi); 766 load_wait_for_GR (cpu, in_GRj); 767 load_wait_for_GR (cpu, in_GRk); 768 load_wait_for_GRdouble (cpu, in_GRdoublek); 769 trace_vliw_wait_cycles (cpu); 770 return 0; 771 } 772 773 cycles = idesc->timing->units[unit_num].done; 774 775 return cycles; 776 } 777 778 int 779 frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc, 780 int unit_num, int referenced, 781 INT in_GRi, INT in_GRj, 782 INT in_GRk, INT in_GRdoublek) 783 { 784 int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, 785 in_GRi, in_GRj, in_GRk, 786 in_GRdoublek); 787 788 if (model_insn == FRV_INSN_MODEL_PASS_2) 789 { 790 if (CPU_RSTR_INVALIDATE(cpu)) 791 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); 792 } 793 794 return cycles; 795 } 796 797 int 798 frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, 799 int unit_num, int referenced, 800 INT in_GRi, INT in_GRj, 801 INT out_FRk, INT out_FRdoublek) 802 { 803 int cycles; 804 805 if (model_insn == FRV_INSN_MODEL_PASS_1) 806 { 807 /* The entire VLIW insn must wait if there is a dependency on a register 808 which is not ready yet. 809 The latency of the registers may be less than previously recorded, 810 depending on how they were used previously. 811 See Table 13-8 in the LSI. */ 812 if (in_GRi >= 0) 813 { 814 if (use_is_gr_complex (cpu, in_GRi)) 815 decrease_GR_busy (cpu, in_GRi, 1); 816 } 817 if (in_GRj != in_GRi && in_GRj >= 0) 818 { 819 if (use_is_gr_complex (cpu, in_GRj)) 820 decrease_GR_busy (cpu, in_GRj, 1); 821 } 822 if (out_FRk >= 0) 823 { 824 if (use_is_media (cpu, out_FRk)) 825 decrease_FR_busy (cpu, out_FRk, 1); 826 else 827 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); 828 } 829 if (out_FRdoublek >= 0) 830 { 831 if (use_is_media (cpu, out_FRdoublek)) 832 decrease_FR_busy (cpu, out_FRdoublek, 1); 833 else 834 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1); 835 if (use_is_media (cpu, out_FRdoublek + 1)) 836 decrease_FR_busy (cpu, out_FRdoublek + 1, 1); 837 else 838 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1); 839 } 840 vliw_wait_for_GR (cpu, in_GRi); 841 vliw_wait_for_GR (cpu, in_GRj); 842 vliw_wait_for_FR (cpu, out_FRk); 843 vliw_wait_for_FRdouble (cpu, out_FRdoublek); 844 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 845 { 846 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 847 vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); 848 } 849 handle_resource_wait (cpu); 850 load_wait_for_GR (cpu, in_GRi); 851 load_wait_for_GR (cpu, in_GRj); 852 load_wait_for_FR (cpu, out_FRk); 853 load_wait_for_FRdouble (cpu, out_FRdoublek); 854 trace_vliw_wait_cycles (cpu); 855 return 0; 856 } 857 858 cycles = idesc->timing->units[unit_num].done; 859 860 /* The latency of FRk for a load will depend on how long it takes to retrieve 861 the the data from the cache or memory. */ 862 update_FR_latency_for_load (cpu, out_FRk, cycles); 863 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); 864 865 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 866 { 867 /* FNER has a latency of 3 cycles. */ 868 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); 869 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); 870 } 871 872 fr500_reset_fr_flags (cpu, out_FRk); 873 874 return cycles; 875 } 876 877 int 878 frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, 879 int unit_num, int referenced, 880 INT in_GRi, INT in_GRj, 881 INT in_FRk, INT in_FRdoublek) 882 { 883 int cycles; 884 885 if (model_insn == FRV_INSN_MODEL_PASS_1) 886 { 887 /* The entire VLIW insn must wait if there is a dependency on a register 888 which is not ready yet. 889 The latency of the registers may be less than previously recorded, 890 depending on how they were used previously. 891 See Table 13-8 in the LSI. */ 892 if (in_GRi >= 0) 893 { 894 if (use_is_gr_complex (cpu, in_GRi)) 895 decrease_GR_busy (cpu, in_GRi, 1); 896 } 897 if (in_GRj != in_GRi && in_GRj >= 0) 898 { 899 if (use_is_gr_complex (cpu, in_GRj)) 900 decrease_GR_busy (cpu, in_GRj, 1); 901 } 902 if (in_FRk >= 0) 903 { 904 if (use_is_media (cpu, in_FRk)) 905 decrease_FR_busy (cpu, in_FRk, 1); 906 else 907 adjust_float_register_busy (cpu, -1, -1, in_FRk, 1); 908 } 909 if (in_FRdoublek >= 0) 910 { 911 if (use_is_media (cpu, in_FRdoublek)) 912 decrease_FR_busy (cpu, in_FRdoublek, 1); 913 else 914 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1); 915 if (use_is_media (cpu, in_FRdoublek + 1)) 916 decrease_FR_busy (cpu, in_FRdoublek + 1, 1); 917 else 918 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1); 919 } 920 vliw_wait_for_GR (cpu, in_GRi); 921 vliw_wait_for_GR (cpu, in_GRj); 922 vliw_wait_for_FR (cpu, in_FRk); 923 vliw_wait_for_FRdouble (cpu, in_FRdoublek); 924 handle_resource_wait (cpu); 925 load_wait_for_GR (cpu, in_GRi); 926 load_wait_for_GR (cpu, in_GRj); 927 load_wait_for_FR (cpu, in_FRk); 928 load_wait_for_FRdouble (cpu, in_FRdoublek); 929 trace_vliw_wait_cycles (cpu); 930 return 0; 931 } 932 933 cycles = idesc->timing->units[unit_num].done; 934 935 return cycles; 936 } 937 938 int 939 frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc, 940 int unit_num, int referenced, 941 INT in_GRi, INT in_GRj, 942 INT in_FRk, INT in_FRdoublek) 943 { 944 int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced, 945 in_GRi, in_GRj, in_FRk, 946 in_FRdoublek); 947 948 if (model_insn == FRV_INSN_MODEL_PASS_2) 949 { 950 if (CPU_RSTR_INVALIDATE(cpu)) 951 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); 952 } 953 954 return cycles; 955 } 956 957 int 958 frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc, 959 int unit_num, int referenced, 960 INT in_GRi, INT in_GRj, INT out_GRk) 961 { 962 int cycles; 963 964 if (model_insn == FRV_INSN_MODEL_PASS_1) 965 { 966 /* The entire VLIW insn must wait if there is a dependency on a register 967 which is not ready yet. 968 The latency of the registers may be less than previously recorded, 969 depending on how they were used previously. 970 See Table 13-8 in the LSI. */ 971 if (in_GRi != out_GRk && in_GRi >= 0) 972 { 973 if (use_is_gr_complex (cpu, in_GRi)) 974 decrease_GR_busy (cpu, in_GRi, 1); 975 } 976 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) 977 { 978 if (use_is_gr_complex (cpu, in_GRj)) 979 decrease_GR_busy (cpu, in_GRj, 1); 980 } 981 vliw_wait_for_GR (cpu, in_GRi); 982 vliw_wait_for_GR (cpu, in_GRj); 983 vliw_wait_for_GR (cpu, out_GRk); 984 handle_resource_wait (cpu); 985 load_wait_for_GR (cpu, in_GRi); 986 load_wait_for_GR (cpu, in_GRj); 987 load_wait_for_GR (cpu, out_GRk); 988 trace_vliw_wait_cycles (cpu); 989 return 0; 990 } 991 992 cycles = idesc->timing->units[unit_num].done; 993 994 /* The latency of GRk will depend on how long it takes to swap 995 the the data from the cache or memory. */ 996 update_GR_latency_for_swap (cpu, out_GRk, cycles); 997 set_use_is_gr_complex (cpu, out_GRk); 998 999 return cycles; 1000 } 1001 1002 int 1003 frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc, 1004 int unit_num, int referenced, 1005 INT in_FRj, INT out_FRk) 1006 { 1007 int cycles; 1008 1009 if (model_insn == FRV_INSN_MODEL_PASS_1) 1010 { 1011 /* The entire VLIW insn must wait if there is a dependency on a register 1012 which is not ready yet. */ 1013 if (in_FRj >= 0) 1014 { 1015 if (use_is_media (cpu, in_FRj)) 1016 decrease_FR_busy (cpu, in_FRj, 1); 1017 else 1018 adjust_float_register_busy (cpu, -1, in_FRj, -1, 1); 1019 } 1020 if (out_FRk >= 0 && out_FRk != in_FRj) 1021 { 1022 if (use_is_media (cpu, out_FRk)) 1023 decrease_FR_busy (cpu, out_FRk, 1); 1024 else 1025 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); 1026 } 1027 vliw_wait_for_FR (cpu, in_FRj); 1028 vliw_wait_for_FR (cpu, out_FRk); 1029 handle_resource_wait (cpu); 1030 load_wait_for_FR (cpu, in_FRj); 1031 load_wait_for_FR (cpu, out_FRk); 1032 trace_vliw_wait_cycles (cpu); 1033 return 0; 1034 } 1035 1036 /* The latency of FRj is 3 cycles. */ 1037 cycles = idesc->timing->units[unit_num].done; 1038 update_FR_latency (cpu, out_FRk, cycles + 3); 1039 1040 return cycles; 1041 } 1042 1043 int 1044 frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, 1045 int unit_num, int referenced, 1046 INT in_FRk, INT out_GRj) 1047 { 1048 int cycles; 1049 1050 if (model_insn == FRV_INSN_MODEL_PASS_1) 1051 { 1052 /* The entire VLIW insn must wait if there is a dependency on a register 1053 which is not ready yet. */ 1054 if (in_FRk >= 0) 1055 { 1056 if (use_is_media (cpu, in_FRk)) 1057 decrease_FR_busy (cpu, in_FRk, 1); 1058 else 1059 adjust_float_register_busy (cpu, -1, in_FRk, -1, 1); 1060 } 1061 vliw_wait_for_FR (cpu, in_FRk); 1062 vliw_wait_for_GR (cpu, out_GRj); 1063 handle_resource_wait (cpu); 1064 load_wait_for_FR (cpu, in_FRk); 1065 load_wait_for_GR (cpu, out_GRj); 1066 trace_vliw_wait_cycles (cpu); 1067 return 0; 1068 } 1069 1070 /* The latency of GRj is 2 cycles. */ 1071 cycles = idesc->timing->units[unit_num].done; 1072 update_GR_latency (cpu, out_GRj, cycles + 2); 1073 set_use_is_gr_complex (cpu, out_GRj); 1074 1075 return cycles; 1076 } 1077 1078 int 1079 frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, 1080 int unit_num, int referenced, 1081 INT in_spr, INT out_GRj) 1082 { 1083 int cycles; 1084 1085 if (model_insn == FRV_INSN_MODEL_PASS_1) 1086 { 1087 /* The entire VLIW insn must wait if there is a dependency on a register 1088 which is not ready yet. */ 1089 vliw_wait_for_SPR (cpu, in_spr); 1090 vliw_wait_for_GR (cpu, out_GRj); 1091 handle_resource_wait (cpu); 1092 load_wait_for_GR (cpu, out_GRj); 1093 trace_vliw_wait_cycles (cpu); 1094 return 0; 1095 } 1096 1097 cycles = idesc->timing->units[unit_num].done; 1098 1099 #if 0 /* no latency? */ 1100 /* The latency of GRj is 2 cycles. */ 1101 update_GR_latency (cpu, out_GRj, cycles + 2); 1102 #endif 1103 1104 return cycles; 1105 } 1106 1107 int 1108 frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, 1109 int unit_num, int referenced, 1110 INT in_GRj, INT out_FRk) 1111 { 1112 int cycles; 1113 1114 if (model_insn == FRV_INSN_MODEL_PASS_1) 1115 { 1116 /* The entire VLIW insn must wait if there is a dependency on a register 1117 which is not ready yet. 1118 The latency of the registers may be less than previously recorded, 1119 depending on how they were used previously. 1120 See Table 13-8 in the LSI. */ 1121 if (in_GRj >= 0) 1122 { 1123 if (use_is_gr_complex (cpu, in_GRj)) 1124 decrease_GR_busy (cpu, in_GRj, 1); 1125 } 1126 if (out_FRk >= 0) 1127 { 1128 if (use_is_media (cpu, out_FRk)) 1129 decrease_FR_busy (cpu, out_FRk, 1); 1130 else 1131 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); 1132 } 1133 vliw_wait_for_GR (cpu, in_GRj); 1134 vliw_wait_for_FR (cpu, out_FRk); 1135 handle_resource_wait (cpu); 1136 load_wait_for_GR (cpu, in_GRj); 1137 load_wait_for_FR (cpu, out_FRk); 1138 trace_vliw_wait_cycles (cpu); 1139 return 0; 1140 } 1141 1142 /* The latency of FRk is 2 cycles. */ 1143 cycles = idesc->timing->units[unit_num].done; 1144 update_FR_latency (cpu, out_FRk, cycles + 2); 1145 1146 /* Mark this use of the register as NOT a floating point op. */ 1147 fr500_reset_fr_flags (cpu, out_FRk); 1148 1149 return cycles; 1150 } 1151 1152 int 1153 frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, 1154 int unit_num, int referenced, 1155 INT in_GRj, INT out_spr) 1156 { 1157 int cycles; 1158 1159 if (model_insn == FRV_INSN_MODEL_PASS_1) 1160 { 1161 /* The entire VLIW insn must wait if there is a dependency on a register 1162 which is not ready yet. 1163 The latency of the registers may be less than previously recorded, 1164 depending on how they were used previously. 1165 See Table 13-8 in the LSI. */ 1166 if (in_GRj >= 0) 1167 { 1168 if (use_is_gr_complex (cpu, in_GRj)) 1169 decrease_GR_busy (cpu, in_GRj, 1); 1170 } 1171 vliw_wait_for_GR (cpu, in_GRj); 1172 vliw_wait_for_SPR (cpu, out_spr); 1173 handle_resource_wait (cpu); 1174 load_wait_for_GR (cpu, in_GRj); 1175 trace_vliw_wait_cycles (cpu); 1176 return 0; 1177 } 1178 1179 cycles = idesc->timing->units[unit_num].done; 1180 1181 #if 0 1182 /* The latency of spr is ? cycles. */ 1183 update_SPR_latency (cpu, out_spr, cycles + ?); 1184 #endif 1185 1186 return cycles; 1187 } 1188 1189 int 1190 frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc, 1191 int unit_num, int referenced, 1192 INT in_GRi, INT in_GRj) 1193 { 1194 int cycles; 1195 1196 if (model_insn == FRV_INSN_MODEL_PASS_1) 1197 { 1198 /* The entire VLIW insn must wait if there is a dependency on a register 1199 which is not ready yet. 1200 The latency of the registers may be less than previously recorded, 1201 depending on how they were used previously. 1202 See Table 13-8 in the LSI. */ 1203 if (in_GRi >= 0) 1204 { 1205 if (use_is_gr_complex (cpu, in_GRi)) 1206 decrease_GR_busy (cpu, in_GRi, 1); 1207 } 1208 if (in_GRj != in_GRi && in_GRj >= 0) 1209 { 1210 if (use_is_gr_complex (cpu, in_GRj)) 1211 decrease_GR_busy (cpu, in_GRj, 1); 1212 } 1213 vliw_wait_for_GR (cpu, in_GRi); 1214 vliw_wait_for_GR (cpu, in_GRj); 1215 handle_resource_wait (cpu); 1216 load_wait_for_GR (cpu, in_GRi); 1217 load_wait_for_GR (cpu, in_GRj); 1218 trace_vliw_wait_cycles (cpu); 1219 return 0; 1220 } 1221 1222 cycles = idesc->timing->units[unit_num].done; 1223 request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles); 1224 return cycles; 1225 } 1226 1227 int 1228 frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc, 1229 int unit_num, int referenced, 1230 INT in_GRi, INT in_GRj) 1231 { 1232 int cycles; 1233 1234 if (model_insn == FRV_INSN_MODEL_PASS_1) 1235 { 1236 /* The entire VLIW insn must wait if there is a dependency on a register 1237 which is not ready yet. 1238 The latency of the registers may be less than previously recorded, 1239 depending on how they were used previously. 1240 See Table 13-8 in the LSI. */ 1241 if (in_GRi >= 0) 1242 { 1243 if (use_is_gr_complex (cpu, in_GRi)) 1244 decrease_GR_busy (cpu, in_GRi, 1); 1245 } 1246 if (in_GRj != in_GRi && in_GRj >= 0) 1247 { 1248 if (use_is_gr_complex (cpu, in_GRj)) 1249 decrease_GR_busy (cpu, in_GRj, 1); 1250 } 1251 vliw_wait_for_GR (cpu, in_GRi); 1252 vliw_wait_for_GR (cpu, in_GRj); 1253 handle_resource_wait (cpu); 1254 load_wait_for_GR (cpu, in_GRi); 1255 load_wait_for_GR (cpu, in_GRj); 1256 trace_vliw_wait_cycles (cpu); 1257 return 0; 1258 } 1259 1260 cycles = idesc->timing->units[unit_num].done; 1261 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles); 1262 return cycles; 1263 } 1264 1265 int 1266 frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc, 1267 int unit_num, int referenced, 1268 INT in_GRi, INT in_GRj) 1269 { 1270 int cycles; 1271 1272 if (model_insn == FRV_INSN_MODEL_PASS_1) 1273 { 1274 /* The entire VLIW insn must wait if there is a dependency on a register 1275 which is not ready yet. 1276 The latency of the registers may be less than previously recorded, 1277 depending on how they were used previously. 1278 See Table 13-8 in the LSI. */ 1279 if (in_GRi >= 0) 1280 { 1281 if (use_is_gr_complex (cpu, in_GRi)) 1282 decrease_GR_busy (cpu, in_GRi, 1); 1283 } 1284 if (in_GRj != in_GRi && in_GRj >= 0) 1285 { 1286 if (use_is_gr_complex (cpu, in_GRj)) 1287 decrease_GR_busy (cpu, in_GRj, 1); 1288 } 1289 vliw_wait_for_GR (cpu, in_GRi); 1290 vliw_wait_for_GR (cpu, in_GRj); 1291 handle_resource_wait (cpu); 1292 load_wait_for_GR (cpu, in_GRi); 1293 load_wait_for_GR (cpu, in_GRj); 1294 trace_vliw_wait_cycles (cpu); 1295 return 0; 1296 } 1297 1298 cycles = idesc->timing->units[unit_num].done; 1299 request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles); 1300 return cycles; 1301 } 1302 1303 int 1304 frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc, 1305 int unit_num, int referenced, 1306 INT in_GRi, INT in_GRj) 1307 { 1308 int cycles; 1309 1310 if (model_insn == FRV_INSN_MODEL_PASS_1) 1311 { 1312 /* The entire VLIW insn must wait if there is a dependency on a register 1313 which is not ready yet. 1314 The latency of the registers may be less than previously recorded, 1315 depending on how they were used previously. 1316 See Table 13-8 in the LSI. */ 1317 if (in_GRi >= 0) 1318 { 1319 if (use_is_gr_complex (cpu, in_GRi)) 1320 decrease_GR_busy (cpu, in_GRi, 1); 1321 } 1322 if (in_GRj != in_GRi && in_GRj >= 0) 1323 { 1324 if (use_is_gr_complex (cpu, in_GRj)) 1325 decrease_GR_busy (cpu, in_GRj, 1); 1326 } 1327 vliw_wait_for_GR (cpu, in_GRi); 1328 vliw_wait_for_GR (cpu, in_GRj); 1329 handle_resource_wait (cpu); 1330 load_wait_for_GR (cpu, in_GRi); 1331 load_wait_for_GR (cpu, in_GRj); 1332 trace_vliw_wait_cycles (cpu); 1333 return 0; 1334 } 1335 1336 cycles = idesc->timing->units[unit_num].done; 1337 request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles); 1338 return cycles; 1339 } 1340 1341 int 1342 frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, 1343 int unit_num, int referenced, 1344 INT in_GRi, INT in_GRj) 1345 { 1346 int cycles; 1347 1348 if (model_insn == FRV_INSN_MODEL_PASS_1) 1349 { 1350 /* The entire VLIW insn must wait if there is a dependency on a register 1351 which is not ready yet. 1352 The latency of the registers may be less than previously recorded, 1353 depending on how they were used previously. 1354 See Table 13-8 in the LSI. */ 1355 if (in_GRi >= 0) 1356 { 1357 if (use_is_gr_complex (cpu, in_GRi)) 1358 decrease_GR_busy (cpu, in_GRi, 1); 1359 } 1360 if (in_GRj != in_GRi && in_GRj >= 0) 1361 { 1362 if (use_is_gr_complex (cpu, in_GRj)) 1363 decrease_GR_busy (cpu, in_GRj, 1); 1364 } 1365 vliw_wait_for_GR (cpu, in_GRi); 1366 vliw_wait_for_GR (cpu, in_GRj); 1367 handle_resource_wait (cpu); 1368 load_wait_for_GR (cpu, in_GRi); 1369 load_wait_for_GR (cpu, in_GRj); 1370 trace_vliw_wait_cycles (cpu); 1371 return 0; 1372 } 1373 1374 cycles = idesc->timing->units[unit_num].done; 1375 request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles); 1376 return cycles; 1377 } 1378 1379 int 1380 frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc, 1381 int unit_num, int referenced, 1382 INT in_GRi, INT in_GRj) 1383 { 1384 int cycles; 1385 1386 if (model_insn == FRV_INSN_MODEL_PASS_1) 1387 { 1388 /* The entire VLIW insn must wait if there is a dependency on a register 1389 which is not ready yet. 1390 The latency of the registers may be less than previously recorded, 1391 depending on how they were used previously. 1392 See Table 13-8 in the LSI. */ 1393 if (in_GRi >= 0) 1394 { 1395 if (use_is_gr_complex (cpu, in_GRi)) 1396 decrease_GR_busy (cpu, in_GRi, 1); 1397 } 1398 if (in_GRj != in_GRi && in_GRj >= 0) 1399 { 1400 if (use_is_gr_complex (cpu, in_GRj)) 1401 decrease_GR_busy (cpu, in_GRj, 1); 1402 } 1403 vliw_wait_for_GR (cpu, in_GRi); 1404 vliw_wait_for_GR (cpu, in_GRj); 1405 handle_resource_wait (cpu); 1406 load_wait_for_GR (cpu, in_GRi); 1407 load_wait_for_GR (cpu, in_GRj); 1408 trace_vliw_wait_cycles (cpu); 1409 return 0; 1410 } 1411 1412 cycles = idesc->timing->units[unit_num].done; 1413 request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles); 1414 return cycles; 1415 } 1416 1417 int 1418 frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc, 1419 int unit_num, int referenced, 1420 INT in_GRi, INT in_GRj) 1421 { 1422 int cycles; 1423 1424 if (model_insn == FRV_INSN_MODEL_PASS_1) 1425 { 1426 /* The entire VLIW insn must wait if there is a dependency on a register 1427 which is not ready yet. 1428 The latency of the registers may be less than previously recorded, 1429 depending on how they were used previously. 1430 See Table 13-8 in the LSI. */ 1431 if (in_GRi >= 0) 1432 { 1433 if (use_is_gr_complex (cpu, in_GRi)) 1434 decrease_GR_busy (cpu, in_GRi, 1); 1435 } 1436 if (in_GRj != in_GRi && in_GRj >= 0) 1437 { 1438 if (use_is_gr_complex (cpu, in_GRj)) 1439 decrease_GR_busy (cpu, in_GRj, 1); 1440 } 1441 vliw_wait_for_GR (cpu, in_GRi); 1442 vliw_wait_for_GR (cpu, in_GRj); 1443 handle_resource_wait (cpu); 1444 load_wait_for_GR (cpu, in_GRi); 1445 load_wait_for_GR (cpu, in_GRj); 1446 trace_vliw_wait_cycles (cpu); 1447 return 0; 1448 } 1449 1450 cycles = idesc->timing->units[unit_num].done; 1451 request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles); 1452 return cycles; 1453 } 1454 1455 int 1456 frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, 1457 int unit_num, int referenced, 1458 INT in_FRi, INT in_FRj, 1459 INT in_FRdoublei, INT in_FRdoublej, 1460 INT out_FRk, INT out_FRdoublek) 1461 { 1462 int cycles; 1463 FRV_PROFILE_STATE *ps; 1464 1465 if (model_insn == FRV_INSN_MODEL_PASS_1) 1466 return 0; 1467 1468 /* The preprocessing can execute right away. */ 1469 cycles = idesc->timing->units[unit_num].done; 1470 1471 /* The post processing must wait if there is a dependency on a FR 1472 which is not ready yet. */ 1473 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1474 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, 1475 1); 1476 ps = CPU_PROFILE_STATE (cpu); 1477 ps->post_wait = cycles; 1478 post_wait_for_FR (cpu, in_FRi); 1479 post_wait_for_FR (cpu, in_FRj); 1480 post_wait_for_FR (cpu, out_FRk); 1481 post_wait_for_FRdouble (cpu, in_FRdoublei); 1482 post_wait_for_FRdouble (cpu, in_FRdoublej); 1483 post_wait_for_FRdouble (cpu, out_FRdoublek); 1484 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1485 { 1486 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 1487 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); 1488 } 1489 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1490 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, 1491 1); 1492 1493 /* The latency of FRk will be at least the latency of the other inputs. */ 1494 update_FR_latency (cpu, out_FRk, ps->post_wait); 1495 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); 1496 1497 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1498 { 1499 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); 1500 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); 1501 } 1502 1503 /* Once initiated, post-processing will take 3 cycles. */ 1504 update_FR_ptime (cpu, out_FRk, 3); 1505 update_FRdouble_ptime (cpu, out_FRdoublek, 3); 1506 1507 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1508 { 1509 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); 1510 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); 1511 } 1512 1513 /* Mark this use of the register as a floating point op. */ 1514 if (out_FRk >= 0) 1515 set_use_is_fpop (cpu, out_FRk); 1516 if (out_FRdoublek >= 0) 1517 { 1518 set_use_is_fpop (cpu, out_FRdoublek); 1519 if (out_FRdoublek < 63) 1520 set_use_is_fpop (cpu, out_FRdoublek + 1); 1521 } 1522 1523 return cycles; 1524 } 1525 1526 int 1527 frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, 1528 int unit_num, int referenced, 1529 INT in_FRi, INT in_FRj, 1530 INT in_FRdoublei, INT in_FRdoublej, 1531 INT out_FRk, INT out_FRdoublek) 1532 { 1533 int cycles; 1534 INT dual_FRi; 1535 INT dual_FRj; 1536 INT dual_FRk; 1537 INT dual_FRdoublei; 1538 INT dual_FRdoublej; 1539 INT dual_FRdoublek; 1540 FRV_PROFILE_STATE *ps; 1541 1542 if (model_insn == FRV_INSN_MODEL_PASS_1) 1543 return 0; 1544 1545 /* The preprocessing can execute right away. */ 1546 cycles = idesc->timing->units[unit_num].done; 1547 1548 /* The post processing must wait if there is a dependency on a FR 1549 which is not ready yet. */ 1550 dual_FRi = DUAL_REG (in_FRi); 1551 dual_FRj = DUAL_REG (in_FRj); 1552 dual_FRk = DUAL_REG (out_FRk); 1553 dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei); 1554 dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej); 1555 dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek); 1556 1557 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1558 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); 1559 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, 1560 1); 1561 adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, 1562 dual_FRdoublek, 1); 1563 ps = CPU_PROFILE_STATE (cpu); 1564 ps->post_wait = cycles; 1565 post_wait_for_FR (cpu, in_FRi); 1566 post_wait_for_FR (cpu, in_FRj); 1567 post_wait_for_FR (cpu, out_FRk); 1568 post_wait_for_FR (cpu, dual_FRi); 1569 post_wait_for_FR (cpu, dual_FRj); 1570 post_wait_for_FR (cpu, dual_FRk); 1571 post_wait_for_FRdouble (cpu, in_FRdoublei); 1572 post_wait_for_FRdouble (cpu, in_FRdoublej); 1573 post_wait_for_FRdouble (cpu, out_FRdoublek); 1574 post_wait_for_FRdouble (cpu, dual_FRdoublei); 1575 post_wait_for_FRdouble (cpu, dual_FRdoublej); 1576 post_wait_for_FRdouble (cpu, dual_FRdoublek); 1577 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1578 { 1579 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 1580 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); 1581 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); 1582 post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); 1583 } 1584 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1585 restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); 1586 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, 1587 1); 1588 restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej, 1589 dual_FRdoublek, 1); 1590 1591 /* The latency of FRk will be at least the latency of the other inputs. */ 1592 update_FR_latency (cpu, out_FRk, ps->post_wait); 1593 update_FR_latency (cpu, dual_FRk, ps->post_wait); 1594 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); 1595 update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); 1596 1597 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1598 { 1599 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); 1600 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); 1601 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); 1602 update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); 1603 } 1604 1605 /* Once initiated, post-processing will take 3 cycles. */ 1606 update_FR_ptime (cpu, out_FRk, 3); 1607 update_FR_ptime (cpu, dual_FRk, 3); 1608 update_FRdouble_ptime (cpu, out_FRdoublek, 3); 1609 update_FRdouble_ptime (cpu, dual_FRdoublek, 3); 1610 1611 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1612 { 1613 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); 1614 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); 1615 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); 1616 update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); 1617 } 1618 1619 /* Mark this use of the register as a floating point op. */ 1620 if (out_FRk >= 0) 1621 set_use_is_fpop (cpu, out_FRk); 1622 if (dual_FRk >= 0) 1623 set_use_is_fpop (cpu, dual_FRk); 1624 if (out_FRdoublek >= 0) 1625 { 1626 set_use_is_fpop (cpu, out_FRdoublek); 1627 if (out_FRdoublek < 63) 1628 set_use_is_fpop (cpu, out_FRdoublek + 1); 1629 } 1630 if (dual_FRdoublek >= 0) 1631 { 1632 set_use_is_fpop (cpu, dual_FRdoublek); 1633 if (dual_FRdoublek < 63) 1634 set_use_is_fpop (cpu, dual_FRdoublek + 1); 1635 } 1636 1637 return cycles; 1638 } 1639 1640 int 1641 frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc, 1642 int unit_num, int referenced, 1643 INT in_FRi, INT in_FRj, INT out_FRk) 1644 { 1645 int cycles; 1646 FRV_VLIW *vliw; 1647 int slot; 1648 FRV_PROFILE_STATE *ps; 1649 1650 if (model_insn == FRV_INSN_MODEL_PASS_1) 1651 return 0; 1652 1653 cycles = idesc->timing->units[unit_num].done; 1654 1655 /* The post processing must wait if there is a dependency on a FR 1656 which is not ready yet. */ 1657 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1658 ps = CPU_PROFILE_STATE (cpu); 1659 ps->post_wait = cycles; 1660 post_wait_for_FR (cpu, in_FRi); 1661 post_wait_for_FR (cpu, in_FRj); 1662 post_wait_for_FR (cpu, out_FRk); 1663 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1664 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 1665 vliw = CPU_VLIW (cpu); 1666 slot = vliw->next_slot - 1; 1667 slot = (*vliw->current_vliw)[slot] - UNIT_FM0; 1668 post_wait_for_fdiv (cpu, slot); 1669 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); 1670 1671 /* The latency of FRk will be at least the latency of the other inputs. */ 1672 /* Once initiated, post-processing will take 10 cycles. */ 1673 update_FR_latency (cpu, out_FRk, ps->post_wait); 1674 update_FR_ptime (cpu, out_FRk, 10); 1675 1676 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1677 { 1678 /* FNER has a latency of 10 cycles. */ 1679 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); 1680 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10); 1681 } 1682 1683 /* The latency of the fdiv unit will be at least the latency of the other 1684 inputs. Once initiated, post-processing will take 9 cycles. */ 1685 update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); 1686 1687 /* Mark this use of the register as a floating point op. */ 1688 set_use_is_fpop (cpu, out_FRk); 1689 1690 return cycles; 1691 } 1692 1693 int 1694 frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, 1695 int unit_num, int referenced, 1696 INT in_FRj, INT in_FRdoublej, 1697 INT out_FRk, INT out_FRdoublek) 1698 { 1699 int cycles; 1700 FRV_VLIW *vliw; 1701 int slot; 1702 FRV_PROFILE_STATE *ps; 1703 1704 if (model_insn == FRV_INSN_MODEL_PASS_1) 1705 return 0; 1706 1707 cycles = idesc->timing->units[unit_num].done; 1708 1709 /* The post processing must wait if there is a dependency on a FR 1710 which is not ready yet. */ 1711 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1712 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); 1713 ps = CPU_PROFILE_STATE (cpu); 1714 ps->post_wait = cycles; 1715 post_wait_for_FR (cpu, in_FRj); 1716 post_wait_for_FR (cpu, out_FRk); 1717 post_wait_for_FRdouble (cpu, in_FRdoublej); 1718 post_wait_for_FRdouble (cpu, out_FRdoublek); 1719 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1720 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 1721 vliw = CPU_VLIW (cpu); 1722 slot = vliw->next_slot - 1; 1723 slot = (*vliw->current_vliw)[slot] - UNIT_FM0; 1724 post_wait_for_fsqrt (cpu, slot); 1725 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1726 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); 1727 1728 /* The latency of FRk will be at least the latency of the other inputs. */ 1729 update_FR_latency (cpu, out_FRk, ps->post_wait); 1730 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); 1731 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1732 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); 1733 1734 /* Once initiated, post-processing will take 15 cycles. */ 1735 update_FR_ptime (cpu, out_FRk, 15); 1736 update_FRdouble_ptime (cpu, out_FRdoublek, 15); 1737 1738 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1739 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15); 1740 1741 /* The latency of the sqrt unit will be the latency of the other 1742 inputs plus 14 cycles. */ 1743 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); 1744 1745 /* Mark this use of the register as a floating point op. */ 1746 if (out_FRk >= 0) 1747 set_use_is_fpop (cpu, out_FRk); 1748 if (out_FRdoublek >= 0) 1749 { 1750 set_use_is_fpop (cpu, out_FRdoublek); 1751 if (out_FRdoublek < 63) 1752 set_use_is_fpop (cpu, out_FRdoublek + 1); 1753 } 1754 1755 return cycles; 1756 } 1757 1758 int 1759 frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc, 1760 int unit_num, int referenced, 1761 INT in_FRj, INT out_FRk) 1762 { 1763 int cycles; 1764 FRV_VLIW *vliw; 1765 int slot; 1766 INT dual_FRj; 1767 INT dual_FRk; 1768 FRV_PROFILE_STATE *ps; 1769 1770 if (model_insn == FRV_INSN_MODEL_PASS_1) 1771 return 0; 1772 1773 cycles = idesc->timing->units[unit_num].done; 1774 1775 /* The post processing must wait if there is a dependency on a FR 1776 which is not ready yet. */ 1777 dual_FRj = DUAL_REG (in_FRj); 1778 dual_FRk = DUAL_REG (out_FRk); 1779 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1780 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); 1781 ps = CPU_PROFILE_STATE (cpu); 1782 ps->post_wait = cycles; 1783 post_wait_for_FR (cpu, in_FRj); 1784 post_wait_for_FR (cpu, out_FRk); 1785 post_wait_for_FR (cpu, dual_FRj); 1786 post_wait_for_FR (cpu, dual_FRk); 1787 1788 vliw = CPU_VLIW (cpu); 1789 slot = vliw->next_slot - 1; 1790 slot = (*vliw->current_vliw)[slot] - UNIT_FM0; 1791 post_wait_for_fsqrt (cpu, slot); 1792 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1793 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); 1794 1795 /* The latency of FRk will be at least the latency of the other inputs. */ 1796 update_FR_latency (cpu, out_FRk, ps->post_wait); 1797 update_FR_latency (cpu, dual_FRk, ps->post_wait); 1798 1799 /* Once initiated, post-processing will take 15 cycles. */ 1800 update_FR_ptime (cpu, out_FRk, 15); 1801 update_FR_ptime (cpu, dual_FRk, 15); 1802 1803 /* The latency of the sqrt unit will be at least the latency of the other 1804 inputs. */ 1805 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); 1806 1807 /* Mark this use of the register as a floating point op. */ 1808 if (out_FRk >= 0) 1809 set_use_is_fpop (cpu, out_FRk); 1810 if (dual_FRk >= 0) 1811 set_use_is_fpop (cpu, dual_FRk); 1812 1813 return cycles; 1814 } 1815 1816 int 1817 frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc, 1818 int unit_num, int referenced, 1819 INT in_FRi, INT in_FRj, 1820 INT in_FRdoublei, INT in_FRdoublej, 1821 INT out_FCCi_2) 1822 { 1823 int cycles; 1824 FRV_PROFILE_STATE *ps; 1825 1826 if (model_insn == FRV_INSN_MODEL_PASS_1) 1827 return 0; 1828 1829 /* The preprocessing can execute right away. */ 1830 cycles = idesc->timing->units[unit_num].done; 1831 1832 /* The post processing must wait if there is a dependency on a FR 1833 which is not ready yet. */ 1834 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); 1835 ps = CPU_PROFILE_STATE (cpu); 1836 ps->post_wait = cycles; 1837 post_wait_for_FR (cpu, in_FRi); 1838 post_wait_for_FR (cpu, in_FRj); 1839 post_wait_for_FRdouble (cpu, in_FRdoublei); 1840 post_wait_for_FRdouble (cpu, in_FRdoublej); 1841 post_wait_for_CCR (cpu, out_FCCi_2); 1842 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1); 1843 1844 /* The latency of FCCi_2 will be the latency of the other inputs plus 3 1845 cycles. */ 1846 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); 1847 1848 return cycles; 1849 } 1850 1851 int 1852 frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc, 1853 int unit_num, int referenced, 1854 INT in_FRi, INT in_FRj, 1855 INT out_FCCi_2) 1856 { 1857 int cycles; 1858 INT dual_FRi; 1859 INT dual_FRj; 1860 INT dual_FCCi_2; 1861 FRV_PROFILE_STATE *ps; 1862 1863 if (model_insn == FRV_INSN_MODEL_PASS_1) 1864 return 0; 1865 1866 /* The preprocessing can execute right away. */ 1867 cycles = idesc->timing->units[unit_num].done; 1868 1869 /* The post processing must wait if there is a dependency on a FR 1870 which is not ready yet. */ 1871 ps = CPU_PROFILE_STATE (cpu); 1872 ps->post_wait = cycles; 1873 dual_FRi = DUAL_REG (in_FRi); 1874 dual_FRj = DUAL_REG (in_FRj); 1875 dual_FCCi_2 = out_FCCi_2 + 1; 1876 adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); 1877 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); 1878 post_wait_for_FR (cpu, in_FRi); 1879 post_wait_for_FR (cpu, in_FRj); 1880 post_wait_for_FR (cpu, dual_FRi); 1881 post_wait_for_FR (cpu, dual_FRj); 1882 post_wait_for_CCR (cpu, out_FCCi_2); 1883 post_wait_for_CCR (cpu, dual_FCCi_2); 1884 restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1); 1885 restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1); 1886 1887 /* The latency of FCCi_2 will be the latency of the other inputs plus 3 1888 cycles. */ 1889 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3); 1890 update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3); 1891 1892 return cycles; 1893 } 1894 1895 int 1896 frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, 1897 int unit_num, int referenced, 1898 INT in_FRj, INT in_FRintj, INT in_FRdoublej, 1899 INT out_FRk, INT out_FRintk, 1900 INT out_FRdoublek) 1901 { 1902 int cycles; 1903 FRV_PROFILE_STATE *ps; 1904 1905 if (model_insn == FRV_INSN_MODEL_PASS_1) 1906 return 0; 1907 1908 /* The preprocessing can execute right away. */ 1909 cycles = idesc->timing->units[unit_num].done; 1910 1911 /* The post processing must wait if there is a dependency on a FR 1912 which is not ready yet. */ 1913 ps = CPU_PROFILE_STATE (cpu); 1914 ps->post_wait = cycles; 1915 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1916 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); 1917 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); 1918 post_wait_for_FR (cpu, in_FRj); 1919 post_wait_for_FR (cpu, in_FRintj); 1920 post_wait_for_FRdouble (cpu, in_FRdoublej); 1921 post_wait_for_FR (cpu, out_FRk); 1922 post_wait_for_FR (cpu, out_FRintk); 1923 post_wait_for_FRdouble (cpu, out_FRdoublek); 1924 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1925 { 1926 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); 1927 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); 1928 post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); 1929 } 1930 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 1931 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); 1932 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); 1933 1934 /* The latency of FRk will be at least the latency of the other inputs. */ 1935 update_FR_latency (cpu, out_FRk, ps->post_wait); 1936 update_FR_latency (cpu, out_FRintk, ps->post_wait); 1937 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); 1938 1939 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1940 { 1941 update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); 1942 update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); 1943 update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); 1944 } 1945 1946 /* Once initiated, post-processing will take 3 cycles. */ 1947 update_FR_ptime (cpu, out_FRk, 3); 1948 update_FR_ptime (cpu, out_FRintk, 3); 1949 update_FRdouble_ptime (cpu, out_FRdoublek, 3); 1950 1951 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) 1952 { 1953 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); 1954 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3); 1955 update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); 1956 } 1957 1958 /* Mark this use of the register as a floating point op. */ 1959 if (out_FRk >= 0) 1960 set_use_is_fpop (cpu, out_FRk); 1961 if (out_FRintk >= 0) 1962 set_use_is_fpop (cpu, out_FRintk); 1963 if (out_FRdoublek >= 0) 1964 { 1965 set_use_is_fpop (cpu, out_FRdoublek); 1966 set_use_is_fpop (cpu, out_FRdoublek + 1); 1967 } 1968 1969 return cycles; 1970 } 1971 1972 int 1973 frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc, 1974 int unit_num, int referenced, 1975 INT in_FRj, INT in_FRintj, 1976 INT out_FRk, INT out_FRintk) 1977 { 1978 int cycles; 1979 INT dual_FRj; 1980 INT dual_FRintj; 1981 INT dual_FRk; 1982 INT dual_FRintk; 1983 FRV_PROFILE_STATE *ps; 1984 1985 if (model_insn == FRV_INSN_MODEL_PASS_1) 1986 return 0; 1987 1988 /* The preprocessing can execute right away. */ 1989 cycles = idesc->timing->units[unit_num].done; 1990 1991 /* The post processing must wait if there is a dependency on a FR 1992 which is not ready yet. */ 1993 ps = CPU_PROFILE_STATE (cpu); 1994 ps->post_wait = cycles; 1995 dual_FRj = DUAL_REG (in_FRj); 1996 dual_FRintj = DUAL_REG (in_FRintj); 1997 dual_FRk = DUAL_REG (out_FRk); 1998 dual_FRintk = DUAL_REG (out_FRintk); 1999 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 2000 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); 2001 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); 2002 adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); 2003 post_wait_for_FR (cpu, in_FRj); 2004 post_wait_for_FR (cpu, in_FRintj); 2005 post_wait_for_FR (cpu, out_FRk); 2006 post_wait_for_FR (cpu, out_FRintk); 2007 post_wait_for_FR (cpu, dual_FRj); 2008 post_wait_for_FR (cpu, dual_FRintj); 2009 post_wait_for_FR (cpu, dual_FRk); 2010 post_wait_for_FR (cpu, dual_FRintk); 2011 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); 2012 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1); 2013 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); 2014 restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1); 2015 2016 /* The latency of FRk will be at least the latency of the other inputs. */ 2017 update_FR_latency (cpu, out_FRk, ps->post_wait); 2018 update_FR_latency (cpu, out_FRintk, ps->post_wait); 2019 update_FR_latency (cpu, dual_FRk, ps->post_wait); 2020 update_FR_latency (cpu, dual_FRintk, ps->post_wait); 2021 2022 /* Once initiated, post-processing will take 3 cycles. */ 2023 update_FR_ptime (cpu, out_FRk, 3); 2024 update_FR_ptime (cpu, out_FRintk, 3); 2025 update_FR_ptime (cpu, dual_FRk, 3); 2026 update_FR_ptime (cpu, dual_FRintk, 3); 2027 2028 /* Mark this use of the register as a floating point op. */ 2029 if (out_FRk >= 0) 2030 set_use_is_fpop (cpu, out_FRk); 2031 if (out_FRintk >= 0) 2032 set_use_is_fpop (cpu, out_FRintk); 2033 2034 return cycles; 2035 } 2036 2037 int 2038 frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc, 2039 int unit_num, int referenced, 2040 INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi, 2041 INT out_FRk, 2042 INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk) 2043 { 2044 int cycles; 2045 FRV_PROFILE_STATE *ps; 2046 int busy_adjustment[] = {0, 0, 0}; 2047 int *fr; 2048 2049 if (model_insn == FRV_INSN_MODEL_PASS_1) 2050 return 0; 2051 2052 /* The preprocessing can execute right away. */ 2053 cycles = idesc->timing->units[unit_num].done; 2054 2055 ps = CPU_PROFILE_STATE (cpu); 2056 2057 /* If the previous use of the registers was a media op, 2058 then their latency will be less than previously recorded. 2059 See Table 13-13 in the LSI. */ 2060 if (in_FRi >= 0) 2061 { 2062 if (use_is_media (cpu, in_FRi)) 2063 { 2064 busy_adjustment[0] = 2; 2065 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2066 } 2067 else 2068 enforce_full_fr_latency (cpu, in_FRi); 2069 } 2070 if (in_FRj >= 0 && in_FRj != in_FRi) 2071 { 2072 if (use_is_media (cpu, in_FRj)) 2073 { 2074 busy_adjustment[1] = 2; 2075 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); 2076 } 2077 else 2078 enforce_full_fr_latency (cpu, in_FRj); 2079 } 2080 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj) 2081 { 2082 if (use_is_media (cpu, out_FRk)) 2083 { 2084 busy_adjustment[2] = 2; 2085 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); 2086 } 2087 else 2088 enforce_full_fr_latency (cpu, out_FRk); 2089 } 2090 2091 /* The post processing must wait if there is a dependency on a FR 2092 which is not ready yet. */ 2093 ps->post_wait = cycles; 2094 post_wait_for_FR (cpu, in_FRi); 2095 post_wait_for_FR (cpu, in_FRj); 2096 post_wait_for_FR (cpu, out_FRk); 2097 post_wait_for_ACC (cpu, in_ACC40Si); 2098 post_wait_for_ACC (cpu, in_ACCGi); 2099 post_wait_for_ACC (cpu, out_ACC40Sk); 2100 post_wait_for_ACC (cpu, out_ACC40Uk); 2101 post_wait_for_ACC (cpu, out_ACCGk); 2102 2103 /* Restore the busy cycles of the registers we used. */ 2104 fr = ps->fr_busy; 2105 if (in_FRi >= 0) 2106 fr[in_FRi] += busy_adjustment[0]; 2107 if (in_FRj >= 0) 2108 fr[in_FRj] += busy_adjustment[1]; 2109 if (out_FRk >= 0) 2110 fr[out_FRk] += busy_adjustment[2]; 2111 2112 /* The latency of tht output register will be at least the latency of the 2113 other inputs. Once initiated, post-processing will take 3 cycles. */ 2114 if (out_FRk >= 0) 2115 { 2116 update_FR_latency (cpu, out_FRk, ps->post_wait); 2117 update_FR_ptime (cpu, out_FRk, 3); 2118 /* Mark this use of the register as a media op. */ 2119 set_use_is_media (cpu, out_FRk); 2120 } 2121 /* The latency of tht output accumulator will be at least the latency of the 2122 other inputs. Once initiated, post-processing will take 1 cycle. */ 2123 if (out_ACC40Sk >= 0) 2124 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 2125 if (out_ACC40Uk >= 0) 2126 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); 2127 if (out_ACCGk >= 0) 2128 update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1); 2129 2130 return cycles; 2131 } 2132 2133 int 2134 frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc, 2135 int unit_num, int referenced, 2136 INT in_FRi, INT in_FRj, 2137 INT out_FRk) 2138 { 2139 int cycles; 2140 INT dual_FRi; 2141 INT dual_FRj; 2142 INT dual_FRk; 2143 FRV_PROFILE_STATE *ps; 2144 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 2145 int *fr; 2146 2147 if (model_insn == FRV_INSN_MODEL_PASS_1) 2148 return 0; 2149 2150 /* The preprocessing can execute right away. */ 2151 cycles = idesc->timing->units[unit_num].done; 2152 2153 ps = CPU_PROFILE_STATE (cpu); 2154 dual_FRi = DUAL_REG (in_FRi); 2155 dual_FRj = DUAL_REG (in_FRj); 2156 dual_FRk = DUAL_REG (out_FRk); 2157 2158 /* If the previous use of the registers was a media op, 2159 then their latency will be less than previously recorded. 2160 See Table 13-13 in the LSI. */ 2161 if (use_is_media (cpu, in_FRi)) 2162 { 2163 busy_adjustment[0] = 2; 2164 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2165 } 2166 else 2167 enforce_full_fr_latency (cpu, in_FRi); 2168 if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi)) 2169 { 2170 busy_adjustment[1] = 2; 2171 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); 2172 } 2173 else 2174 enforce_full_fr_latency (cpu, dual_FRi); 2175 if (in_FRj != in_FRi) 2176 { 2177 if (use_is_media (cpu, in_FRj)) 2178 { 2179 busy_adjustment[2] = 2; 2180 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); 2181 } 2182 else 2183 enforce_full_fr_latency (cpu, in_FRj); 2184 if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj)) 2185 { 2186 busy_adjustment[3] = 2; 2187 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); 2188 } 2189 else 2190 enforce_full_fr_latency (cpu, dual_FRj + 1); 2191 } 2192 if (out_FRk != in_FRi && out_FRk != in_FRj) 2193 { 2194 if (use_is_media (cpu, out_FRk)) 2195 { 2196 busy_adjustment[4] = 2; 2197 decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]); 2198 } 2199 else 2200 enforce_full_fr_latency (cpu, out_FRk); 2201 if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk)) 2202 { 2203 busy_adjustment[5] = 2; 2204 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]); 2205 } 2206 else 2207 enforce_full_fr_latency (cpu, dual_FRk); 2208 } 2209 2210 /* The post processing must wait if there is a dependency on a FR 2211 which is not ready yet. */ 2212 ps->post_wait = cycles; 2213 post_wait_for_FR (cpu, in_FRi); 2214 post_wait_for_FR (cpu, dual_FRi); 2215 post_wait_for_FR (cpu, in_FRj); 2216 post_wait_for_FR (cpu, dual_FRj); 2217 post_wait_for_FR (cpu, out_FRk); 2218 post_wait_for_FR (cpu, dual_FRk); 2219 2220 /* Restore the busy cycles of the registers we used. */ 2221 fr = ps->fr_busy; 2222 fr[in_FRi] += busy_adjustment[0]; 2223 if (dual_FRi >= 0) 2224 fr[dual_FRi] += busy_adjustment[1]; 2225 fr[in_FRj] += busy_adjustment[2]; 2226 if (dual_FRj >= 0) 2227 fr[dual_FRj] += busy_adjustment[3]; 2228 fr[out_FRk] += busy_adjustment[4]; 2229 if (dual_FRk >= 0) 2230 fr[dual_FRk] += busy_adjustment[5]; 2231 2232 /* The latency of tht output register will be at least the latency of the 2233 other inputs. */ 2234 update_FR_latency (cpu, out_FRk, ps->post_wait); 2235 2236 /* Once initiated, post-processing will take 3 cycles. */ 2237 update_FR_ptime (cpu, out_FRk, 3); 2238 2239 /* Mark this use of the register as a media op. */ 2240 set_use_is_media (cpu, out_FRk); 2241 if (dual_FRk >= 0) 2242 { 2243 update_FR_latency (cpu, dual_FRk, ps->post_wait); 2244 update_FR_ptime (cpu, dual_FRk, 3); 2245 /* Mark this use of the register as a media op. */ 2246 set_use_is_media (cpu, dual_FRk); 2247 } 2248 2249 return cycles; 2250 } 2251 2252 int 2253 frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc, 2254 int unit_num, int referenced, 2255 INT in_FRi, INT in_FRj, 2256 INT out_ACC40Sk, INT out_ACC40Uk) 2257 { 2258 int cycles; 2259 INT dual_ACC40Sk; 2260 INT dual_ACC40Uk; 2261 FRV_PROFILE_STATE *ps; 2262 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 2263 int *fr; 2264 int *acc; 2265 2266 if (model_insn == FRV_INSN_MODEL_PASS_1) 2267 return 0; 2268 2269 /* The preprocessing can execute right away. */ 2270 cycles = idesc->timing->units[unit_num].done; 2271 2272 ps = CPU_PROFILE_STATE (cpu); 2273 dual_ACC40Sk = DUAL_REG (out_ACC40Sk); 2274 dual_ACC40Uk = DUAL_REG (out_ACC40Uk); 2275 2276 /* If the previous use of the registers was a media op, 2277 then their latency will be less than previously recorded. 2278 See Table 13-13 in the LSI. */ 2279 if (use_is_media (cpu, in_FRi)) 2280 { 2281 busy_adjustment[0] = 2; 2282 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2283 } 2284 else 2285 enforce_full_fr_latency (cpu, in_FRi); 2286 if (in_FRj != in_FRi) 2287 { 2288 if (use_is_media (cpu, in_FRj)) 2289 { 2290 busy_adjustment[1] = 2; 2291 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); 2292 } 2293 else 2294 enforce_full_fr_latency (cpu, in_FRj); 2295 } 2296 if (out_ACC40Sk >= 0) 2297 { 2298 busy_adjustment[2] = 1; 2299 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); 2300 } 2301 if (dual_ACC40Sk >= 0) 2302 { 2303 busy_adjustment[3] = 1; 2304 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); 2305 } 2306 if (out_ACC40Uk >= 0) 2307 { 2308 busy_adjustment[4] = 1; 2309 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); 2310 } 2311 if (dual_ACC40Uk >= 0) 2312 { 2313 busy_adjustment[5] = 1; 2314 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); 2315 } 2316 2317 /* The post processing must wait if there is a dependency on a FR 2318 which is not ready yet. */ 2319 ps->post_wait = cycles; 2320 post_wait_for_FR (cpu, in_FRi); 2321 post_wait_for_FR (cpu, in_FRj); 2322 post_wait_for_ACC (cpu, out_ACC40Sk); 2323 post_wait_for_ACC (cpu, dual_ACC40Sk); 2324 post_wait_for_ACC (cpu, out_ACC40Uk); 2325 post_wait_for_ACC (cpu, dual_ACC40Uk); 2326 2327 /* Restore the busy cycles of the registers we used. */ 2328 fr = ps->fr_busy; 2329 acc = ps->acc_busy; 2330 fr[in_FRi] += busy_adjustment[0]; 2331 fr[in_FRj] += busy_adjustment[1]; 2332 if (out_ACC40Sk >= 0) 2333 acc[out_ACC40Sk] += busy_adjustment[2]; 2334 if (dual_ACC40Sk >= 0) 2335 acc[dual_ACC40Sk] += busy_adjustment[3]; 2336 if (out_ACC40Uk >= 0) 2337 acc[out_ACC40Uk] += busy_adjustment[4]; 2338 if (dual_ACC40Uk >= 0) 2339 acc[dual_ACC40Uk] += busy_adjustment[5]; 2340 2341 /* The latency of tht output register will be at least the latency of the 2342 other inputs. Once initiated, post-processing will take 1 cycle. */ 2343 if (out_ACC40Sk >= 0) 2344 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 2345 if (dual_ACC40Sk >= 0) 2346 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); 2347 if (out_ACC40Uk >= 0) 2348 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); 2349 if (dual_ACC40Uk >= 0) 2350 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); 2351 2352 return cycles; 2353 } 2354 2355 int 2356 frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc, 2357 int unit_num, int referenced, 2358 INT in_FRi, INT in_FRj, 2359 INT out_ACC40Sk, INT out_ACC40Uk) 2360 { 2361 int cycles; 2362 INT FRi_1; 2363 INT FRj_1; 2364 INT ACC40Sk_1; 2365 INT ACC40Sk_2; 2366 INT ACC40Sk_3; 2367 INT ACC40Uk_1; 2368 INT ACC40Uk_2; 2369 INT ACC40Uk_3; 2370 FRV_PROFILE_STATE *ps; 2371 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; 2372 int *fr; 2373 int *acc; 2374 2375 if (model_insn == FRV_INSN_MODEL_PASS_1) 2376 return 0; 2377 2378 /* The preprocessing can execute right away. */ 2379 cycles = idesc->timing->units[unit_num].done; 2380 2381 FRi_1 = DUAL_REG (in_FRi); 2382 FRj_1 = DUAL_REG (in_FRj); 2383 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 2384 ACC40Sk_2 = DUAL_REG (ACC40Sk_1); 2385 ACC40Sk_3 = DUAL_REG (ACC40Sk_2); 2386 ACC40Uk_1 = DUAL_REG (out_ACC40Uk); 2387 ACC40Uk_2 = DUAL_REG (ACC40Uk_1); 2388 ACC40Uk_3 = DUAL_REG (ACC40Uk_2); 2389 2390 /* If the previous use of the registers was a media op, 2391 then their latency will be less than previously recorded. 2392 See Table 13-13 in the LSI. */ 2393 ps = CPU_PROFILE_STATE (cpu); 2394 if (use_is_media (cpu, in_FRi)) 2395 { 2396 busy_adjustment[0] = 2; 2397 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2398 } 2399 else 2400 enforce_full_fr_latency (cpu, in_FRi); 2401 if (FRi_1 >= 0) 2402 { 2403 if (use_is_media (cpu, FRi_1)) 2404 { 2405 busy_adjustment[1] = 2; 2406 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); 2407 } 2408 else 2409 enforce_full_fr_latency (cpu, FRi_1); 2410 } 2411 if (in_FRj != in_FRi) 2412 { 2413 if (use_is_media (cpu, in_FRj)) 2414 { 2415 busy_adjustment[2] = 2; 2416 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); 2417 } 2418 else 2419 enforce_full_fr_latency (cpu, in_FRj); 2420 if (FRj_1 >= 0) 2421 { 2422 if (use_is_media (cpu, FRj_1)) 2423 { 2424 busy_adjustment[3] = 2; 2425 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); 2426 } 2427 else 2428 enforce_full_fr_latency (cpu, FRj_1); 2429 } 2430 } 2431 if (out_ACC40Sk >= 0) 2432 { 2433 busy_adjustment[4] = 1; 2434 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); 2435 2436 if (ACC40Sk_1 >= 0) 2437 { 2438 busy_adjustment[5] = 1; 2439 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); 2440 } 2441 if (ACC40Sk_2 >= 0) 2442 { 2443 busy_adjustment[6] = 1; 2444 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); 2445 } 2446 if (ACC40Sk_3 >= 0) 2447 { 2448 busy_adjustment[7] = 1; 2449 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); 2450 } 2451 } 2452 else if (out_ACC40Uk >= 0) 2453 { 2454 busy_adjustment[4] = 1; 2455 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); 2456 2457 if (ACC40Uk_1 >= 0) 2458 { 2459 busy_adjustment[5] = 1; 2460 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); 2461 } 2462 if (ACC40Uk_2 >= 0) 2463 { 2464 busy_adjustment[6] = 1; 2465 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); 2466 } 2467 if (ACC40Uk_3 >= 0) 2468 { 2469 busy_adjustment[7] = 1; 2470 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); 2471 } 2472 } 2473 2474 /* The post processing must wait if there is a dependency on a FR 2475 which is not ready yet. */ 2476 ps->post_wait = cycles; 2477 post_wait_for_FR (cpu, in_FRi); 2478 post_wait_for_FR (cpu, FRi_1); 2479 post_wait_for_FR (cpu, in_FRj); 2480 post_wait_for_FR (cpu, FRj_1); 2481 post_wait_for_ACC (cpu, out_ACC40Sk); 2482 post_wait_for_ACC (cpu, ACC40Sk_1); 2483 post_wait_for_ACC (cpu, ACC40Sk_2); 2484 post_wait_for_ACC (cpu, ACC40Sk_3); 2485 post_wait_for_ACC (cpu, out_ACC40Uk); 2486 post_wait_for_ACC (cpu, ACC40Uk_1); 2487 post_wait_for_ACC (cpu, ACC40Uk_2); 2488 post_wait_for_ACC (cpu, ACC40Uk_3); 2489 2490 /* Restore the busy cycles of the registers we used. */ 2491 fr = ps->fr_busy; 2492 acc = ps->acc_busy; 2493 fr[in_FRi] += busy_adjustment[0]; 2494 if (FRi_1 >= 0) 2495 fr[FRi_1] += busy_adjustment[1]; 2496 fr[in_FRj] += busy_adjustment[2]; 2497 if (FRj_1 > 0) 2498 fr[FRj_1] += busy_adjustment[3]; 2499 if (out_ACC40Sk >= 0) 2500 { 2501 acc[out_ACC40Sk] += busy_adjustment[4]; 2502 if (ACC40Sk_1 >= 0) 2503 acc[ACC40Sk_1] += busy_adjustment[5]; 2504 if (ACC40Sk_2 >= 0) 2505 acc[ACC40Sk_2] += busy_adjustment[6]; 2506 if (ACC40Sk_3 >= 0) 2507 acc[ACC40Sk_3] += busy_adjustment[7]; 2508 } 2509 else if (out_ACC40Uk >= 0) 2510 { 2511 acc[out_ACC40Uk] += busy_adjustment[4]; 2512 if (ACC40Uk_1 >= 0) 2513 acc[ACC40Uk_1] += busy_adjustment[5]; 2514 if (ACC40Uk_2 >= 0) 2515 acc[ACC40Uk_2] += busy_adjustment[6]; 2516 if (ACC40Uk_3 >= 0) 2517 acc[ACC40Uk_3] += busy_adjustment[7]; 2518 } 2519 2520 /* The latency of tht output register will be at least the latency of the 2521 other inputs. Once initiated, post-processing will take 1 cycle. */ 2522 if (out_ACC40Sk >= 0) 2523 { 2524 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 2525 if (ACC40Sk_1 >= 0) 2526 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 2527 if (ACC40Sk_2 >= 0) 2528 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); 2529 if (ACC40Sk_3 >= 0) 2530 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); 2531 } 2532 else if (out_ACC40Uk >= 0) 2533 { 2534 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); 2535 if (ACC40Uk_1 >= 0) 2536 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); 2537 if (ACC40Uk_2 >= 0) 2538 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); 2539 if (ACC40Uk_3 >= 0) 2540 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); 2541 } 2542 2543 return cycles; 2544 } 2545 2546 int 2547 frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc, 2548 int unit_num, int referenced, 2549 INT in_FRi, INT in_FRj, 2550 INT out_ACC40Sk) 2551 { 2552 int cycles; 2553 INT FRi_1; 2554 INT FRj_1; 2555 INT ACC40Sk_1; 2556 FRV_PROFILE_STATE *ps; 2557 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 2558 int *fr; 2559 int *acc; 2560 2561 if (model_insn == FRV_INSN_MODEL_PASS_1) 2562 return 0; 2563 2564 /* The preprocessing can execute right away. */ 2565 cycles = idesc->timing->units[unit_num].done; 2566 2567 FRi_1 = DUAL_REG (in_FRi); 2568 FRj_1 = DUAL_REG (in_FRj); 2569 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 2570 2571 /* If the previous use of the registers was a media op, 2572 then their latency will be less than previously recorded. 2573 See Table 13-13 in the LSI. */ 2574 ps = CPU_PROFILE_STATE (cpu); 2575 if (use_is_media (cpu, in_FRi)) 2576 { 2577 busy_adjustment[0] = 2; 2578 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2579 } 2580 else 2581 enforce_full_fr_latency (cpu, in_FRi); 2582 if (FRi_1 >= 0) 2583 { 2584 if (use_is_media (cpu, FRi_1)) 2585 { 2586 busy_adjustment[1] = 2; 2587 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); 2588 } 2589 else 2590 enforce_full_fr_latency (cpu, FRi_1); 2591 } 2592 if (in_FRj != in_FRi) 2593 { 2594 if (use_is_media (cpu, in_FRj)) 2595 { 2596 busy_adjustment[2] = 2; 2597 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); 2598 } 2599 else 2600 enforce_full_fr_latency (cpu, in_FRj); 2601 if (FRj_1 >= 0) 2602 { 2603 if (use_is_media (cpu, FRj_1)) 2604 { 2605 busy_adjustment[3] = 2; 2606 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]); 2607 } 2608 else 2609 enforce_full_fr_latency (cpu, FRj_1); 2610 } 2611 } 2612 if (out_ACC40Sk >= 0) 2613 { 2614 busy_adjustment[4] = 1; 2615 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); 2616 2617 if (ACC40Sk_1 >= 0) 2618 { 2619 busy_adjustment[5] = 1; 2620 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); 2621 } 2622 } 2623 2624 /* The post processing must wait if there is a dependency on a FR 2625 which is not ready yet. */ 2626 ps->post_wait = cycles; 2627 post_wait_for_FR (cpu, in_FRi); 2628 post_wait_for_FR (cpu, FRi_1); 2629 post_wait_for_FR (cpu, in_FRj); 2630 post_wait_for_FR (cpu, FRj_1); 2631 post_wait_for_ACC (cpu, out_ACC40Sk); 2632 post_wait_for_ACC (cpu, ACC40Sk_1); 2633 2634 /* Restore the busy cycles of the registers we used. */ 2635 fr = ps->fr_busy; 2636 acc = ps->acc_busy; 2637 fr[in_FRi] += busy_adjustment[0]; 2638 if (FRi_1 >= 0) 2639 fr[FRi_1] += busy_adjustment[1]; 2640 fr[in_FRj] += busy_adjustment[2]; 2641 if (FRj_1 > 0) 2642 fr[FRj_1] += busy_adjustment[3]; 2643 if (out_ACC40Sk >= 0) 2644 { 2645 acc[out_ACC40Sk] += busy_adjustment[4]; 2646 if (ACC40Sk_1 >= 0) 2647 acc[ACC40Sk_1] += busy_adjustment[5]; 2648 } 2649 2650 /* The latency of tht output register will be at least the latency of the 2651 other inputs. Once initiated, post-processing will take 1 cycle. */ 2652 if (out_ACC40Sk >= 0) 2653 { 2654 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 2655 if (ACC40Sk_1 >= 0) 2656 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 2657 } 2658 2659 return cycles; 2660 } 2661 2662 int 2663 frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, 2664 int unit_num, int referenced, 2665 INT in_FRi, 2666 INT out_FRk) 2667 { 2668 int cycles; 2669 INT dual_FRk; 2670 FRV_PROFILE_STATE *ps; 2671 int busy_adjustment[] = {0, 0, 0}; 2672 int *fr; 2673 2674 if (model_insn == FRV_INSN_MODEL_PASS_1) 2675 return 0; 2676 2677 /* The preprocessing can execute right away. */ 2678 cycles = idesc->timing->units[unit_num].done; 2679 2680 /* If the previous use of the registers was a media op, 2681 then their latency will be less than previously recorded. 2682 See Table 13-13 in the LSI. */ 2683 dual_FRk = DUAL_REG (out_FRk); 2684 ps = CPU_PROFILE_STATE (cpu); 2685 if (use_is_media (cpu, in_FRi)) 2686 { 2687 busy_adjustment[0] = 2; 2688 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2689 } 2690 else 2691 enforce_full_fr_latency (cpu, in_FRi); 2692 if (out_FRk != in_FRi) 2693 { 2694 if (use_is_media (cpu, out_FRk)) 2695 { 2696 busy_adjustment[1] = 2; 2697 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); 2698 } 2699 else 2700 enforce_full_fr_latency (cpu, out_FRk); 2701 } 2702 if (dual_FRk >= 0 && dual_FRk != in_FRi) 2703 { 2704 if (use_is_media (cpu, dual_FRk)) 2705 { 2706 busy_adjustment[2] = 2; 2707 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]); 2708 } 2709 else 2710 enforce_full_fr_latency (cpu, dual_FRk); 2711 } 2712 2713 /* The post processing must wait if there is a dependency on a FR 2714 which is not ready yet. */ 2715 ps->post_wait = cycles; 2716 post_wait_for_FR (cpu, in_FRi); 2717 post_wait_for_FR (cpu, out_FRk); 2718 post_wait_for_FR (cpu, dual_FRk); 2719 2720 /* Restore the busy cycles of the registers we used. */ 2721 fr = ps->fr_busy; 2722 fr[in_FRi] += busy_adjustment[0]; 2723 fr[out_FRk] += busy_adjustment[1]; 2724 if (dual_FRk >= 0) 2725 fr[dual_FRk] += busy_adjustment[2]; 2726 2727 /* The latency of the output register will be at least the latency of the 2728 other inputs. Once initiated, post-processing will take 3 cycles. */ 2729 update_FR_latency (cpu, out_FRk, ps->post_wait); 2730 update_FR_ptime (cpu, out_FRk, 3); 2731 2732 /* Mark this use of the register as a media op. */ 2733 set_use_is_media (cpu, out_FRk); 2734 if (dual_FRk >= 0) 2735 { 2736 update_FR_latency (cpu, dual_FRk, ps->post_wait); 2737 update_FR_ptime (cpu, dual_FRk, 3); 2738 2739 /* Mark this use of the register as a media op. */ 2740 set_use_is_media (cpu, dual_FRk); 2741 } 2742 2743 return cycles; 2744 } 2745 2746 int 2747 frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc, 2748 int unit_num, int referenced, 2749 INT in_FRi, 2750 INT out_FRk) 2751 { 2752 int cycles; 2753 INT FRi_1; 2754 INT FRk_1; 2755 INT FRk_2; 2756 INT FRk_3; 2757 FRV_PROFILE_STATE *ps; 2758 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 2759 int *fr; 2760 2761 if (model_insn == FRV_INSN_MODEL_PASS_1) 2762 return 0; 2763 2764 /* The preprocessing can execute right away. */ 2765 cycles = idesc->timing->units[unit_num].done; 2766 2767 FRi_1 = DUAL_REG (in_FRi); 2768 FRk_1 = DUAL_REG (out_FRk); 2769 FRk_2 = DUAL_REG (FRk_1); 2770 FRk_3 = DUAL_REG (FRk_2); 2771 2772 /* If the previous use of the registers was a media op, 2773 then their latency will be less than previously recorded. 2774 See Table 13-13 in the LSI. */ 2775 ps = CPU_PROFILE_STATE (cpu); 2776 if (use_is_media (cpu, in_FRi)) 2777 { 2778 busy_adjustment[0] = 2; 2779 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 2780 } 2781 else 2782 enforce_full_fr_latency (cpu, in_FRi); 2783 if (FRi_1 >= 0 && use_is_media (cpu, FRi_1)) 2784 { 2785 busy_adjustment[1] = 2; 2786 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]); 2787 } 2788 else 2789 enforce_full_fr_latency (cpu, FRi_1); 2790 if (out_FRk != in_FRi) 2791 { 2792 if (use_is_media (cpu, out_FRk)) 2793 { 2794 busy_adjustment[2] = 2; 2795 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); 2796 } 2797 else 2798 enforce_full_fr_latency (cpu, out_FRk); 2799 if (FRk_1 >= 0 && FRk_1 != in_FRi) 2800 { 2801 if (use_is_media (cpu, FRk_1)) 2802 { 2803 busy_adjustment[3] = 2; 2804 decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]); 2805 } 2806 else 2807 enforce_full_fr_latency (cpu, FRk_1); 2808 } 2809 if (FRk_2 >= 0 && FRk_2 != in_FRi) 2810 { 2811 if (use_is_media (cpu, FRk_2)) 2812 { 2813 busy_adjustment[4] = 2; 2814 decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]); 2815 } 2816 else 2817 enforce_full_fr_latency (cpu, FRk_2); 2818 } 2819 if (FRk_3 >= 0 && FRk_3 != in_FRi) 2820 { 2821 if (use_is_media (cpu, FRk_3)) 2822 { 2823 busy_adjustment[5] = 2; 2824 decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]); 2825 } 2826 else 2827 enforce_full_fr_latency (cpu, FRk_3); 2828 } 2829 } 2830 2831 /* The post processing must wait if there is a dependency on a FR 2832 which is not ready yet. */ 2833 ps->post_wait = cycles; 2834 post_wait_for_FR (cpu, in_FRi); 2835 post_wait_for_FR (cpu, FRi_1); 2836 post_wait_for_FR (cpu, out_FRk); 2837 post_wait_for_FR (cpu, FRk_1); 2838 post_wait_for_FR (cpu, FRk_2); 2839 post_wait_for_FR (cpu, FRk_3); 2840 2841 /* Restore the busy cycles of the registers we used. */ 2842 fr = ps->fr_busy; 2843 fr[in_FRi] += busy_adjustment[0]; 2844 if (FRi_1 >= 0) 2845 fr[FRi_1] += busy_adjustment[1]; 2846 fr[out_FRk] += busy_adjustment[2]; 2847 if (FRk_1 >= 0) 2848 fr[FRk_1] += busy_adjustment[3]; 2849 if (FRk_2 >= 0) 2850 fr[FRk_2] += busy_adjustment[4]; 2851 if (FRk_3 >= 0) 2852 fr[FRk_3] += busy_adjustment[5]; 2853 2854 /* The latency of tht output register will be at least the latency of the 2855 other inputs. Once initiated, post-processing will take 3 cycles. */ 2856 update_FR_latency (cpu, out_FRk, ps->post_wait); 2857 update_FR_ptime (cpu, out_FRk, 3); 2858 2859 /* Mark this use of the register as a media op. */ 2860 set_use_is_media (cpu, out_FRk); 2861 if (FRk_1 >= 0) 2862 { 2863 update_FR_latency (cpu, FRk_1, ps->post_wait); 2864 update_FR_ptime (cpu, FRk_1, 3); 2865 2866 /* Mark this use of the register as a media op. */ 2867 set_use_is_media (cpu, FRk_1); 2868 } 2869 if (FRk_2 >= 0) 2870 { 2871 update_FR_latency (cpu, FRk_2, ps->post_wait); 2872 update_FR_ptime (cpu, FRk_2, 3); 2873 2874 /* Mark this use of the register as a media op. */ 2875 set_use_is_media (cpu, FRk_2); 2876 } 2877 if (FRk_3 >= 0) 2878 { 2879 update_FR_latency (cpu, FRk_3, ps->post_wait); 2880 update_FR_ptime (cpu, FRk_3, 3); 2881 2882 /* Mark this use of the register as a media op. */ 2883 set_use_is_media (cpu, FRk_3); 2884 } 2885 2886 return cycles; 2887 } 2888 2889 int 2890 frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc, 2891 int unit_num, int referenced, 2892 INT in_FRj, 2893 INT out_FRk) 2894 { 2895 return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num, 2896 referenced, in_FRj, out_FRk); 2897 } 2898 2899 int 2900 frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, 2901 int unit_num, int referenced, 2902 INT in_FRj, 2903 INT out_FRk) 2904 { 2905 int cycles; 2906 INT dual_FRj; 2907 FRV_PROFILE_STATE *ps; 2908 int busy_adjustment[] = {0, 0, 0}; 2909 int *fr; 2910 2911 if (model_insn == FRV_INSN_MODEL_PASS_1) 2912 return 0; 2913 2914 /* The preprocessing can execute right away. */ 2915 cycles = idesc->timing->units[unit_num].done; 2916 2917 /* If the previous use of the registers was a media op, 2918 then their latency will be less than previously recorded. 2919 See Table 13-13 in the LSI. */ 2920 dual_FRj = DUAL_REG (in_FRj); 2921 ps = CPU_PROFILE_STATE (cpu); 2922 if (use_is_media (cpu, in_FRj)) 2923 { 2924 busy_adjustment[0] = 2; 2925 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); 2926 } 2927 else 2928 enforce_full_fr_latency (cpu, in_FRj); 2929 if (dual_FRj >= 0) 2930 { 2931 if (use_is_media (cpu, dual_FRj)) 2932 { 2933 busy_adjustment[1] = 2; 2934 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); 2935 } 2936 else 2937 enforce_full_fr_latency (cpu, dual_FRj); 2938 } 2939 if (out_FRk != in_FRj) 2940 { 2941 if (use_is_media (cpu, out_FRk)) 2942 { 2943 busy_adjustment[2] = 2; 2944 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]); 2945 } 2946 else 2947 enforce_full_fr_latency (cpu, out_FRk); 2948 } 2949 2950 /* The post processing must wait if there is a dependency on a FR 2951 which is not ready yet. */ 2952 ps->post_wait = cycles; 2953 post_wait_for_FR (cpu, in_FRj); 2954 post_wait_for_FR (cpu, dual_FRj); 2955 post_wait_for_FR (cpu, out_FRk); 2956 2957 /* Restore the busy cycles of the registers we used. */ 2958 fr = ps->fr_busy; 2959 fr[in_FRj] += busy_adjustment[0]; 2960 if (dual_FRj >= 0) 2961 fr[dual_FRj] += busy_adjustment[1]; 2962 fr[out_FRk] += busy_adjustment[2]; 2963 2964 /* The latency of tht output register will be at least the latency of the 2965 other inputs. */ 2966 update_FR_latency (cpu, out_FRk, ps->post_wait); 2967 2968 /* Once initiated, post-processing will take 3 cycles. */ 2969 update_FR_ptime (cpu, out_FRk, 3); 2970 2971 /* Mark this use of the register as a media op. */ 2972 set_use_is_media (cpu, out_FRk); 2973 2974 return cycles; 2975 } 2976 2977 int 2978 frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc, 2979 int unit_num, int referenced, 2980 INT in_FRj, 2981 INT out_FRk) 2982 { 2983 int cycles; 2984 INT FRk_1; 2985 INT FRk_2; 2986 INT FRk_3; 2987 FRV_PROFILE_STATE *ps; 2988 int busy_adjustment[] = {0, 0, 0, 0, 0}; 2989 int *fr; 2990 2991 if (model_insn == FRV_INSN_MODEL_PASS_1) 2992 return 0; 2993 2994 /* The preprocessing can execute right away. */ 2995 cycles = idesc->timing->units[unit_num].done; 2996 2997 FRk_1 = DUAL_REG (out_FRk); 2998 FRk_2 = DUAL_REG (FRk_1); 2999 FRk_3 = DUAL_REG (FRk_2); 3000 3001 /* If the previous use of the registers was a media op, 3002 then their latency will be less than previously recorded. 3003 See Table 13-13 in the LSI. */ 3004 ps = CPU_PROFILE_STATE (cpu); 3005 if (use_is_media (cpu, in_FRj)) 3006 { 3007 busy_adjustment[0] = 2; 3008 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); 3009 } 3010 else 3011 enforce_full_fr_latency (cpu, in_FRj); 3012 if (out_FRk != in_FRj) 3013 { 3014 if (use_is_media (cpu, out_FRk)) 3015 { 3016 busy_adjustment[1] = 2; 3017 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]); 3018 } 3019 else 3020 enforce_full_fr_latency (cpu, out_FRk); 3021 if (FRk_1 >= 0 && FRk_1 != in_FRj) 3022 { 3023 if (use_is_media (cpu, FRk_1)) 3024 { 3025 busy_adjustment[2] = 2; 3026 decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]); 3027 } 3028 else 3029 enforce_full_fr_latency (cpu, FRk_1); 3030 } 3031 if (FRk_2 >= 0 && FRk_2 != in_FRj) 3032 { 3033 if (use_is_media (cpu, FRk_2)) 3034 { 3035 busy_adjustment[3] = 2; 3036 decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]); 3037 } 3038 else 3039 enforce_full_fr_latency (cpu, FRk_2); 3040 } 3041 if (FRk_3 >= 0 && FRk_3 != in_FRj) 3042 { 3043 if (use_is_media (cpu, FRk_3)) 3044 { 3045 busy_adjustment[4] = 2; 3046 decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]); 3047 } 3048 else 3049 enforce_full_fr_latency (cpu, FRk_3); 3050 } 3051 } 3052 3053 /* The post processing must wait if there is a dependency on a FR 3054 which is not ready yet. */ 3055 ps->post_wait = cycles; 3056 post_wait_for_FR (cpu, in_FRj); 3057 post_wait_for_FR (cpu, out_FRk); 3058 post_wait_for_FR (cpu, FRk_1); 3059 post_wait_for_FR (cpu, FRk_2); 3060 post_wait_for_FR (cpu, FRk_3); 3061 3062 /* Restore the busy cycles of the registers we used. */ 3063 fr = ps->fr_busy; 3064 fr[in_FRj] += busy_adjustment[0]; 3065 fr[out_FRk] += busy_adjustment[1]; 3066 if (FRk_1 >= 0) 3067 fr[FRk_1] += busy_adjustment[2]; 3068 if (FRk_2 >= 0) 3069 fr[FRk_2] += busy_adjustment[3]; 3070 if (FRk_3 >= 0) 3071 fr[FRk_3] += busy_adjustment[4]; 3072 3073 /* The latency of tht output register will be at least the latency of the 3074 other inputs. Once initiated, post-processing will take 3 cycles. */ 3075 update_FR_latency (cpu, out_FRk, ps->post_wait); 3076 update_FR_ptime (cpu, out_FRk, 3); 3077 3078 /* Mark this use of the register as a media op. */ 3079 set_use_is_media (cpu, out_FRk); 3080 if (FRk_1 >= 0) 3081 { 3082 update_FR_latency (cpu, FRk_1, ps->post_wait); 3083 update_FR_ptime (cpu, FRk_1, 3); 3084 3085 /* Mark this use of the register as a media op. */ 3086 set_use_is_media (cpu, FRk_1); 3087 } 3088 if (FRk_2 >= 0) 3089 { 3090 update_FR_latency (cpu, FRk_2, ps->post_wait); 3091 update_FR_ptime (cpu, FRk_2, 3); 3092 3093 /* Mark this use of the register as a media op. */ 3094 set_use_is_media (cpu, FRk_2); 3095 } 3096 if (FRk_3 >= 0) 3097 { 3098 update_FR_latency (cpu, FRk_3, ps->post_wait); 3099 update_FR_ptime (cpu, FRk_3, 3); 3100 3101 /* Mark this use of the register as a media op. */ 3102 set_use_is_media (cpu, FRk_3); 3103 } 3104 3105 return cycles; 3106 } 3107 3108 int 3109 frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc, 3110 int unit_num, int referenced) 3111 { 3112 int cycles; 3113 if (model_insn == FRV_INSN_MODEL_PASS_1) 3114 { 3115 int i; 3116 /* Wait for ALL resources. */ 3117 for (i = 0; i < 64; ++i) 3118 { 3119 enforce_full_fr_latency (cpu, i); 3120 vliw_wait_for_GR (cpu, i); 3121 vliw_wait_for_FR (cpu, i); 3122 vliw_wait_for_ACC (cpu, i); 3123 } 3124 for (i = 0; i < 8; ++i) 3125 vliw_wait_for_CCR (cpu, i); 3126 for (i = 0; i < 2; ++i) 3127 { 3128 vliw_wait_for_idiv_resource (cpu, i); 3129 vliw_wait_for_fdiv_resource (cpu, i); 3130 vliw_wait_for_fsqrt_resource (cpu, i); 3131 } 3132 handle_resource_wait (cpu); 3133 for (i = 0; i < 64; ++i) 3134 { 3135 load_wait_for_GR (cpu, i); 3136 load_wait_for_FR (cpu, i); 3137 } 3138 trace_vliw_wait_cycles (cpu); 3139 return 0; 3140 } 3141 3142 cycles = idesc->timing->units[unit_num].done; 3143 return cycles; 3144 } 3145 3146 int 3147 frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc, 3148 int unit_num, int referenced) 3149 { 3150 int cycles; 3151 if (model_insn == FRV_INSN_MODEL_PASS_1) 3152 { 3153 int i; 3154 /* Wait for ALL resources, except GR and ICC. */ 3155 for (i = 0; i < 64; ++i) 3156 { 3157 enforce_full_fr_latency (cpu, i); 3158 vliw_wait_for_FR (cpu, i); 3159 vliw_wait_for_ACC (cpu, i); 3160 } 3161 for (i = 0; i < 4; ++i) 3162 vliw_wait_for_CCR (cpu, i); 3163 for (i = 0; i < 2; ++i) 3164 { 3165 vliw_wait_for_idiv_resource (cpu, i); 3166 vliw_wait_for_fdiv_resource (cpu, i); 3167 vliw_wait_for_fsqrt_resource (cpu, i); 3168 } 3169 handle_resource_wait (cpu); 3170 for (i = 0; i < 64; ++i) 3171 { 3172 load_wait_for_FR (cpu, i); 3173 } 3174 trace_vliw_wait_cycles (cpu); 3175 return 0; 3176 } 3177 3178 cycles = idesc->timing->units[unit_num].done; 3179 return cycles; 3180 } 3181 3182 /* The frv machine is a fictional implementation of the fr500 which implements 3183 all frv architectural features. */ 3184 int 3185 frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc, 3186 int unit_num, int referenced) 3187 { 3188 return idesc->timing->units[unit_num].done; 3189 } 3190 3191 /* The simple machine is a fictional implementation of the fr500 which 3192 implements limited frv architectural features. */ 3193 int 3194 frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc, 3195 int unit_num, int referenced) 3196 { 3197 return idesc->timing->units[unit_num].done; 3198 } 3199 3200 /* The tomcat machine is models a prototype fr500 machine which had a few 3201 bugs and restrictions to work around. */ 3202 int 3203 frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc, 3204 int unit_num, int referenced) 3205 { 3206 return idesc->timing->units[unit_num].done; 3207 } 3208 3209 #endif /* WITH_PROFILE_MODEL_P */ 3210
Indexes created Tue May 05 00:25:04 UTC 2026