sim-main.h revision 1.1.1.11
1 /* MIPS Simulator definition. 2 Copyright (C) 1997-2024 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of the MIPS sim. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef SIM_MAIN_H 21 #define SIM_MAIN_H 22 23 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ 24 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) 25 26 #include "sim-basics.h" 27 #include "sim-base.h" 28 #include "bfd/elf-bfd.h" 29 #include "elf/mips.h" 30 31 /* Deprecated macros and types for manipulating 64bit values. Use 32 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ 33 34 typedef int64_t word64; 35 typedef uint64_t uword64; 36 37 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) 38 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) 39 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF) 40 #define SET64HI(t) (((uword64)(t))<<32) 41 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l)))) 42 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l)) 43 44 /* Check if a value will fit within a halfword: */ 45 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) 46 47 48 typedef enum { 49 cp0_dmfc0, 50 cp0_dmtc0, 51 cp0_mfc0, 52 cp0_mtc0, 53 cp0_tlbr, 54 cp0_tlbwi, 55 cp0_tlbwr, 56 cp0_tlbp, 57 cp0_cache, 58 cp0_eret, 59 cp0_deret, 60 cp0_rfe 61 } CP0_operation; 62 63 /* Floating-point operations: */ 64 65 #include "sim-fpu.h" 66 #include "cp1.h" 67 68 /* FPU registers must be one of the following types. All other values 69 are reserved (and undefined). */ 70 typedef enum { 71 fmt_single = 0, 72 fmt_double = 1, 73 fmt_word = 4, 74 fmt_long = 5, 75 fmt_ps = 6, 76 /* The following is a special case for FP conditions where only 77 the lower 32bits are considered. This is a HACK. */ 78 fmt_dc32 = 7, 79 /* The following are well outside the normal acceptable format 80 range, and are used in the register status vector. */ 81 fmt_unknown = 0x10000000, 82 fmt_uninterpreted = 0x20000000, 83 fmt_uninterpreted_32 = 0x40000000, 84 fmt_uninterpreted_64 = 0x80000000U, 85 } FP_formats; 86 87 /* For paired word (pw) operations, the opcode representation is fmt_word, 88 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ 89 #define fmt_pw fmt_long 90 91 /* This should be the COC1 value at the start of the preceding 92 instruction: */ 93 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) 94 95 #ifdef TARGET_ENABLE_FR 96 /* FIXME: this should be enabled for all targets, but needs testing first. */ 97 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \ 98 ? ((SR & status_FR) ? 64 : 32) \ 99 : (WITH_TARGET_FLOATING_POINT_BITSIZE)) 100 #else 101 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) 102 #endif 103 104 105 106 107 108 /* HI/LO register accesses */ 109 110 /* For some MIPS targets, the HI/LO registers have certain timing 111 restrictions in that, for instance, a read of a HI register must be 112 separated by at least three instructions from a preceeding read. 113 114 The struct below is used to record the last access by each of A MT, 115 MF or other OP instruction to a HI/LO register. See mips.igen for 116 more details. */ 117 118 typedef struct _hilo_access { 119 int64_t timestamp; 120 address_word cia; 121 } hilo_access; 122 123 typedef struct _hilo_history { 124 hilo_access mt; 125 hilo_access mf; 126 hilo_access op; 127 } hilo_history; 128 129 130 131 132 /* Integer ALU operations: */ 133 134 #include "sim-alu.h" 135 136 #define ALU32_END(ANS) \ 137 if (ALU32_HAD_OVERFLOW) \ 138 SignalExceptionIntegerOverflow (); \ 139 (ANS) = (int32_t) ALU32_OVERFLOW_RESULT 140 141 142 #define ALU64_END(ANS) \ 143 if (ALU64_HAD_OVERFLOW) \ 144 SignalExceptionIntegerOverflow (); \ 145 (ANS) = ALU64_OVERFLOW_RESULT; 146 147 148 149 150 151 /* The following is probably not used for MIPS IV onwards: */ 152 /* Slots for delayed register updates. For the moment we just have a 153 fixed number of slots (rather than a more generic, dynamic 154 system). This keeps the simulator fast. However, we only allow 155 for the register update to be delayed for a single instruction 156 cycle. */ 157 #define PSLOTS (8) /* Maximum number of instruction cycles */ 158 159 typedef struct _pending_write_queue { 160 int in; 161 int out; 162 int total; 163 int slot_delay[PSLOTS]; 164 int slot_size[PSLOTS]; 165 int slot_bit[PSLOTS]; 166 void *slot_dest[PSLOTS]; 167 uint64_t slot_value[PSLOTS]; 168 } pending_write_queue; 169 170 #ifndef PENDING_TRACE 171 #define PENDING_TRACE 0 172 #endif 173 #define PENDING_IN (MIPS_SIM_CPU (CPU)->pending.in) 174 #define PENDING_OUT (MIPS_SIM_CPU (CPU)->pending.out) 175 #define PENDING_TOTAL (MIPS_SIM_CPU (CPU)->pending.total) 176 #define PENDING_SLOT_SIZE (MIPS_SIM_CPU (CPU)->pending.slot_size) 177 #define PENDING_SLOT_BIT (MIPS_SIM_CPU (CPU)->pending.slot_bit) 178 #define PENDING_SLOT_DELAY (MIPS_SIM_CPU (CPU)->pending.slot_delay) 179 #define PENDING_SLOT_DEST (MIPS_SIM_CPU (CPU)->pending.slot_dest) 180 #define PENDING_SLOT_VALUE (MIPS_SIM_CPU (CPU)->pending.slot_value) 181 182 /* Invalidate the pending write queue, all pending writes are 183 discarded. */ 184 185 #define PENDING_INVALIDATE() \ 186 memset (&MIPS_SIM_CPU (CPU)->pending, 0, sizeof (MIPS_SIM_CPU (CPU)->pending)) 187 188 /* Schedule a write to DEST for N cycles time. For 64 bit 189 destinations, schedule two writes. For floating point registers, 190 the caller should schedule a write to both the dest register and 191 the FPR_STATE register. When BIT is non-negative, only BIT of DEST 192 is updated. */ 193 194 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \ 195 do { \ 196 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \ 197 sim_engine_abort (SD, CPU, cia, \ 198 "PENDING_SCHED - buffer overflow\n"); \ 199 if (PENDING_TRACE) \ 200 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \ 201 (unsigned long) cia, (unsigned long) &(DEST), \ 202 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\ 203 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \ 204 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \ 205 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \ 206 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \ 207 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \ 208 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \ 209 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \ 210 PENDING_TOTAL += 1; \ 211 } while (0) 212 213 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1) 214 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT) 215 216 #define PENDING_TICK() pending_tick (SD, CPU, cia) 217 218 #define PENDING_FLUSH() abort () /* think about this one */ 219 #define PENDING_FP() abort () /* think about this one */ 220 221 /* For backward compatibility */ 222 #define PENDING_FILL(R,VAL) \ 223 do { \ 224 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ 225 { \ 226 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ 227 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ 228 } \ 229 else \ 230 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ 231 } while (0) 232 233 234 enum float_operation 235 { 236 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD, 237 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS, 238 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23 239 }; 240 241 242 /* The internal representation of an MDMX accumulator. 243 Note that 24 and 48 bit accumulator elements are represented in 244 32 or 64 bits. Since the accumulators are 2's complement with 245 overflow suppressed, high-order bits can be ignored in most contexts. */ 246 247 typedef int32_t signed24; 248 typedef int64_t signed48; 249 250 typedef union { 251 signed24 ob[8]; 252 signed48 qh[4]; 253 } MDMX_accumulator; 254 255 256 /* Conventional system arguments. */ 257 #define SIM_STATE sim_cpu *cpu, address_word cia 258 #define SIM_ARGS CPU, cia 259 260 struct mips_sim_cpu { 261 262 /* The following are internal simulator state variables: */ 263 address_word dspc; /* delay-slot PC */ 264 #define DSPC (MIPS_SIM_CPU (CPU)->dspc) 265 266 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET)) 267 #define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); } 268 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_) 269 270 271 /* State of the simulator */ 272 unsigned int state; 273 unsigned int dsstate; 274 #define STATE (MIPS_SIM_CPU (CPU)->state) 275 #define DSSTATE (MIPS_SIM_CPU (CPU)->dsstate) 276 277 /* Flags in the "state" variable: */ 278 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ 279 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ 280 #define simTRACE (1 << 8) /* 1 = trace address activity */ 281 #define simPCOC0 (1 << 17) /* COC[1] from current */ 282 #define simPCOC1 (1 << 18) /* COC[1] from previous */ 283 #define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */ 284 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ 285 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ 286 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ 287 #define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */ 288 289 #ifndef ENGINE_ISSUE_PREFIX_HOOK 290 #define ENGINE_ISSUE_PREFIX_HOOK() \ 291 { \ 292 /* Perform any pending writes */ \ 293 PENDING_TICK(); \ 294 /* Set previous flag, depending on current: */ \ 295 if (STATE & simPCOC0) \ 296 STATE |= simPCOC1; \ 297 else \ 298 STATE &= ~simPCOC1; \ 299 /* and update the current value: */ \ 300 if (GETFCC(0)) \ 301 STATE |= simPCOC0; \ 302 else \ 303 STATE &= ~simPCOC0; \ 304 } 305 #endif /* ENGINE_ISSUE_PREFIX_HOOK */ 306 307 308 /* This is nasty, since we have to rely on matching the register 309 numbers used by GDB. Unfortunately, depending on the MIPS target 310 GDB uses different register numbers. We cannot just include the 311 relevant "gdb/tm.h" link, since GDB may not be configured before 312 the sim world, and also the GDB header file requires too much other 313 state. */ 314 315 #ifndef TM_MIPS_H 316 #define LAST_EMBED_REGNUM (96) 317 #define NUM_REGS (LAST_EMBED_REGNUM + 1) 318 319 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ 320 #define FCRCS_REGNUM 70 /* FP control/status */ 321 #define FCRIR_REGNUM 71 /* FP implementation/revision */ 322 #endif 323 324 325 /* To keep this default simulator simple, and fast, we use a direct 326 vector of registers. The internal simulator engine then uses 327 manifests to access the correct slot. */ 328 329 unsigned_word registers[LAST_EMBED_REGNUM + 1]; 330 331 int register_widths[NUM_REGS]; 332 #define REGISTERS (MIPS_SIM_CPU (CPU)->registers) 333 334 #define GPR (®ISTERS[0]) 335 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) 336 337 #define LO (REGISTERS[33]) 338 #define HI (REGISTERS[34]) 339 #define PCIDX 37 340 #define PC (REGISTERS[PCIDX]) 341 #define CAUSE (REGISTERS[36]) 342 #define SRIDX (32) 343 #define SR (REGISTERS[SRIDX]) /* CPU status register */ 344 #define FCR0IDX (71) 345 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */ 346 #define FCR31IDX (70) 347 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */ 348 #define FCSR (FCR31) 349 #define Debug (REGISTERS[86]) 350 #define DEPC (REGISTERS[87]) 351 #define EPC (REGISTERS[88]) 352 #define ACX (REGISTERS[89]) 353 354 #define AC0LOIDX (33) /* Must be the same register as LO */ 355 #define AC0HIIDX (34) /* Must be the same register as HI */ 356 #define AC1LOIDX (90) 357 #define AC1HIIDX (91) 358 #define AC2LOIDX (92) 359 #define AC2HIIDX (93) 360 #define AC3LOIDX (94) 361 #define AC3HIIDX (95) 362 363 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) 364 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) 365 366 #define DSPCRIDX (96) /* DSP control register */ 367 #define DSPCR (REGISTERS[DSPCRIDX]) 368 369 #define DSPCR_POS_SHIFT (0) 370 #define DSPCR_POS_MASK (0x3f) 371 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) 372 373 #define DSPCR_SCOUNT_SHIFT (7) 374 #define DSPCR_SCOUNT_MASK (0x3f) 375 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) 376 377 #define DSPCR_CARRY_SHIFT (13) 378 #define DSPCR_CARRY_MASK (1) 379 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) 380 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) 381 382 #define DSPCR_EFI_SHIFT (14) 383 #define DSPCR_EFI_MASK (1) 384 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) 385 #define DSPCR_EFI (1 << DSPCR_EFI_MASK) 386 387 #define DSPCR_OUFLAG_SHIFT (16) 388 #define DSPCR_OUFLAG_MASK (0xff) 389 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) 390 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) 391 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) 392 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) 393 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) 394 395 #define DSPCR_CCOND_SHIFT (24) 396 #define DSPCR_CCOND_MASK (0xf) 397 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) 398 399 /* All internal state modified by signal_exception() that may need to be 400 rolled back for passing moment-of-exception image back to gdb. */ 401 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1]; 402 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1]; 403 int exc_suspended; 404 405 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA) 406 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC) 407 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC) 408 409 unsigned_word c0_config_reg; 410 #define C0_CONFIG (MIPS_SIM_CPU (CPU)->c0_config_reg) 411 412 /* The following are pseudonyms for standard registers */ 413 #define ZERO (REGISTERS[0]) 414 #define V0 (REGISTERS[2]) 415 #define A0 (REGISTERS[4]) 416 #define A1 (REGISTERS[5]) 417 #define A2 (REGISTERS[6]) 418 #define A3 (REGISTERS[7]) 419 #define T8IDX 24 420 #define T8 (REGISTERS[T8IDX]) 421 #define SPIDX 29 422 #define SP (REGISTERS[SPIDX]) 423 #define RAIDX 31 424 #define RA (REGISTERS[RAIDX]) 425 426 /* While space is allocated in the main registers arrray for some of 427 the COP0 registers, that space isn't sufficient. Unknown COP0 428 registers overflow into the array below */ 429 430 #define NR_COP0_GPR 32 431 unsigned_word cop0_gpr[NR_COP0_GPR]; 432 #define COP0_GPR (MIPS_SIM_CPU (CPU)->cop0_gpr) 433 #define COP0_BADVADDR (COP0_GPR[8]) 434 435 /* While space is allocated for the floating point registers in the 436 main registers array, they are stored separatly. This is because 437 their size may not necessarily match the size of either the 438 general-purpose or system specific registers. */ 439 #define NR_FGR (32) 440 #define FGR_BASE FP0_REGNUM 441 fp_word fgr[NR_FGR]; 442 #define FGR (MIPS_SIM_CPU (CPU)->fgr) 443 444 /* Keep the current format state for each register: */ 445 FP_formats fpr_state[32]; 446 #define FPR_STATE (MIPS_SIM_CPU (CPU)->fpr_state) 447 448 pending_write_queue pending; 449 450 /* The MDMX accumulator (used only for MDMX ASE). */ 451 MDMX_accumulator acc; 452 #define ACC (MIPS_SIM_CPU (CPU)->acc) 453 454 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic 455 read-write instructions. It is set when a linked load occurs. It 456 is tested and cleared by the conditional store. It is cleared 457 (during other CPU operations) when a store to the location would 458 no longer be atomic. In particular, it is cleared by exception 459 return instructions. */ 460 int llbit; 461 #define LLBIT (MIPS_SIM_CPU (CPU)->llbit) 462 463 464 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that 465 corruptions caused by using the HI or LO register too close to a 466 following operation is spotted. See mips.igen for more details. */ 467 468 hilo_history hi_history; 469 #define HIHISTORY (&MIPS_SIM_CPU (CPU)->hi_history) 470 hilo_history lo_history; 471 #define LOHISTORY (&MIPS_SIM_CPU (CPU)->lo_history) 472 }; 473 #define MIPS_SIM_CPU(cpu) ((struct mips_sim_cpu *) CPU_ARCH_DATA (cpu)) 474 475 extern void mips_sim_close (SIM_DESC sd, int quitting); 476 #define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__) 477 478 /* FIXME: At present much of the simulator is still static */ 479 struct mips_sim_state { 480 /* microMIPS ISA mode. */ 481 int isa_mode; 482 }; 483 #define MIPS_SIM_STATE(sd) ((struct mips_sim_state *) STATE_ARCH_DATA (sd)) 484 485 486 /* Status information: */ 487 488 /* TODO : these should be the bitmasks for these bits within the 489 status register. At the moment the following are VR4300 490 bit-positions: */ 491 #define status_KSU_mask (0x18) /* mask for KSU bits */ 492 #define status_KSU_shift (3) /* shift for field */ 493 #define ksu_kernel (0x0) 494 #define ksu_supervisor (0x1) 495 #define ksu_user (0x2) 496 #define ksu_unknown (0x3) 497 498 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift) 499 500 #define status_IE (1 << 0) /* Interrupt enable */ 501 #define status_EIE (1 << 16) /* Enable Interrupt Enable */ 502 #define status_EXL (1 << 1) /* Exception level */ 503 #define status_RE (1 << 25) /* Reverse Endian in user mode */ 504 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ 505 #define status_SR (1 << 20) /* soft reset or NMI */ 506 #define status_BEV (1 << 22) /* Location of general exception vectors */ 507 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 508 #define status_ERL (1 << 2) /* Error level */ 509 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */ 510 #define status_RP (1 << 27) /* Reduced Power mode */ 511 512 /* Specializations for TX39 family */ 513 #define status_IEc (1 << 0) /* Interrupt enable (current) */ 514 #define status_KUc (1 << 1) /* Kernel/User mode */ 515 #define status_IEp (1 << 2) /* Interrupt enable (previous) */ 516 #define status_KUp (1 << 3) /* Kernel/User mode */ 517 #define status_IEo (1 << 4) /* Interrupt enable (old) */ 518 #define status_KUo (1 << 5) /* Kernel/User mode */ 519 #define status_IM_mask (0xff) /* Interrupt mask */ 520 #define status_IM_shift (8) 521 #define status_NMI (1 << 20) /* NMI */ 522 #define status_NMI (1 << 20) /* NMI */ 523 524 /* Status bits used by MIPS32/MIPS64. */ 525 #define status_UX (1 << 5) /* 64-bit user addrs */ 526 #define status_SX (1 << 6) /* 64-bit supervisor addrs */ 527 #define status_KX (1 << 7) /* 64-bit kernel addrs */ 528 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 529 #define status_PX (1 << 23) /* Enable 64 bit operations */ 530 #define status_MX (1 << 24) /* Enable MDMX resources */ 531 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */ 532 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */ 533 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */ 534 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */ 535 /* Bits reserved for implementations: */ 536 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ 537 538 /* From R6 onwards, some instructions (e.g. ADDIUPC) change behaviour based 539 * on the Status.UX bits to either sign extend, or act as full 64 bit. */ 540 #define status_optional_EXTEND32(x) ((SR & status_UX) ? x : EXTEND32(x)) 541 542 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ 543 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ 544 #define cause_CE_mask 0x30000000 /* Coprocessor exception */ 545 #define cause_CE_shift 28 546 #define cause_EXC2_mask 0x00070000 547 #define cause_EXC2_shift 16 548 #define cause_IP7 (1 << 15) /* Interrupt pending */ 549 #define cause_SIOP (1 << 12) /* SIO pending */ 550 #define cause_IP3 (1 << 11) /* Int 0 pending */ 551 #define cause_IP2 (1 << 10) /* Int 1 pending */ 552 553 #define cause_EXC_mask (0x1c) /* Exception code */ 554 #define cause_EXC_shift (2) 555 556 #define cause_SW0 (1 << 8) /* Software interrupt 0 */ 557 #define cause_SW1 (1 << 9) /* Software interrupt 1 */ 558 #define cause_IP_mask (0x3f) /* Interrupt pending field */ 559 #define cause_IP_shift (10) 560 561 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask) 562 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask) 563 564 565 /* NOTE: We keep the following status flags as bit values (1 for true, 566 0 for false). This allows them to be used in binary boolean 567 operations without worrying about what exactly the non-zero true 568 value is. */ 569 570 /* UserMode */ 571 #ifdef SUBTARGET_R3900 572 #define UserMode ((SR & status_KUc) ? 1 : 0) 573 #else 574 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) 575 #endif /* SUBTARGET_R3900 */ 576 577 /* BigEndianMem */ 578 /* Hardware configuration. Affects endianness of LoadMemory and 579 StoreMemory and the endianness of Kernel and Supervisor mode 580 execution. The value is 0 for little-endian; 1 for big-endian. */ 581 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 582 /*(state & simBE) ? 1 : 0)*/ 583 584 /* ReverseEndian */ 585 /* This mode is selected if in User mode with the RE bit being set in 586 SR (Status Register). It reverses the endianness of load and store 587 instructions. */ 588 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) 589 590 /* BigEndianCPU */ 591 /* The endianness for load and store instructions (0=little;1=big). In 592 User mode this endianness may be switched by setting the state_RE 593 bit in the SR register. Thus, BigEndianCPU may be computed as 594 (BigEndianMem EOR ReverseEndian). */ 595 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ 596 597 598 599 /* Exceptions: */ 600 601 /* NOTE: These numbers depend on the processor architecture being 602 simulated: */ 603 enum ExceptionCause { 604 Interrupt = 0, 605 TLBModification = 1, 606 TLBLoad = 2, 607 TLBStore = 3, 608 AddressLoad = 4, 609 AddressStore = 5, 610 InstructionFetch = 6, 611 DataReference = 7, 612 SystemCall = 8, 613 BreakPoint = 9, 614 ReservedInstruction = 10, 615 CoProcessorUnusable = 11, 616 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ 617 Trap = 13, 618 FPE = 15, 619 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ 620 MDMX = 22, 621 Watch = 23, 622 MCheck = 24, 623 CacheErr = 30, 624 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ 625 626 627 /* The following exception code is actually private to the simulator 628 world. It is *NOT* a processor feature, and is used to signal 629 run-time errors in the simulator. */ 630 SimulatorFault = 0xFFFFFFFF 631 }; 632 633 #define TLB_REFILL (0) 634 #define TLB_INVALID (1) 635 636 637 /* The following break instructions are reserved for use by the 638 simulator. The first is used to halt the simulation. The second 639 is used by gdb for break-points. NOTE: Care must be taken, since 640 this value may be used in later revisions of the MIPS ISA. */ 641 #define HALT_INSTRUCTION_MASK (0x03FFFFC0) 642 643 #define HALT_INSTRUCTION (0x03ff000d) 644 #define HALT_INSTRUCTION2 (0x0000ffcd) 645 646 647 #define BREAKPOINT_INSTRUCTION (0x0005000d) 648 #define BREAKPOINT_INSTRUCTION2 (0x0000014d) 649 650 651 652 void interrupt_event (SIM_DESC sd, void *data); 653 654 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); 655 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) 656 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level) 657 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) 658 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) 659 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) 660 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference) 661 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) 662 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) 663 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) 664 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable) 665 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset) 666 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL) 667 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL) 668 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) 669 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) 670 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) 671 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) 672 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) 673 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) 674 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) 675 676 /* Co-processor accesses */ 677 678 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ 679 #define COP_Usable(coproc_num) (coproc_num == 1) 680 681 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword); 682 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword); 683 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 684 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 685 686 #define COP_LW(coproc_num,coproc_reg,memword) \ 687 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) 688 #define COP_LD(coproc_num,coproc_reg,memword) \ 689 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) 690 #define COP_SW(coproc_num,coproc_reg) \ 691 cop_sw (SD, CPU, cia, coproc_num, coproc_reg) 692 #define COP_SD(coproc_num,coproc_reg) \ 693 cop_sd (SD, CPU, cia, coproc_num, coproc_reg) 694 695 696 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, 697 unsigned int instruction, int coprocnum, CP0_operation op, 698 int rt, int rd, int sel); 699 #define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \ 700 decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \ 701 (rt), (rd), (sel)) 702 703 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); 704 705 706 /* FPR access. */ 707 uint64_t value_fpr (SIM_STATE, int fpr, FP_formats); 708 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) 709 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value); 710 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) 711 uint64_t ps_lower (SIM_STATE, uint64_t op); 712 #define PSLower(op) ps_lower (SIM_ARGS, op) 713 uint64_t ps_upper (SIM_STATE, uint64_t op); 714 #define PSUpper(op) ps_upper (SIM_ARGS, op) 715 uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from); 716 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) 717 718 719 /* FCR access. */ 720 unsigned_word value_fcr (SIM_STATE, int fcr); 721 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) 722 void store_fcr (SIM_STATE, int fcr, unsigned_word value); 723 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) 724 void test_fcsr (SIM_STATE); 725 #define TestFCSR() test_fcsr (SIM_ARGS) 726 727 728 /* FPU operations. */ 729 /* Non-signalling */ 730 #define FP_R6CMP_AF 0x0 731 #define FP_R6CMP_EQ 0x2 732 #define FP_R6CMP_LE 0x6 733 #define FP_R6CMP_LT 0x4 734 #define FP_R6CMP_NE 0x13 735 #define FP_R6CMP_OR 0x11 736 #define FP_R6CMP_UEQ 0x3 737 #define FP_R6CMP_ULE 0x7 738 #define FP_R6CMP_ULT 0x5 739 #define FP_R6CMP_UN 0x1 740 #define FP_R6CMP_UNE 0x12 741 742 /* Signalling */ 743 #define FP_R6CMP_SAF 0x8 744 #define FP_R6CMP_SEQ 0xa 745 #define FP_R6CMP_SLE 0xe 746 #define FP_R6CMP_SLT 0xc 747 #define FP_R6CMP_SNE 0x1b 748 #define FP_R6CMP_SOR 0x19 749 #define FP_R6CMP_SUEQ 0xb 750 #define FP_R6CMP_SULE 0xf 751 #define FP_R6CMP_SULT 0xd 752 #define FP_R6CMP_SUN 0x9 753 #define FP_R6CMP_SUNE 0x1a 754 755 /* FPU Class */ 756 #define FP_R6CLASS_SNAN (1<<0) 757 #define FP_R6CLASS_QNAN (1<<1) 758 #define FP_R6CLASS_NEGINF (1<<2) 759 #define FP_R6CLASS_NEGNORM (1<<3) 760 #define FP_R6CLASS_NEGSUB (1<<4) 761 #define FP_R6CLASS_NEGZERO (1<<5) 762 #define FP_R6CLASS_POSINF (1<<6) 763 #define FP_R6CLASS_POSNORM (1<<7) 764 #define FP_R6CLASS_POSSUB (1<<8) 765 #define FP_R6CLASS_POSZERO (1<<9) 766 767 void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, 768 int abs, int cond, int cc); 769 #define Compare(op1,op2,fmt,cond,cc) \ 770 fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) 771 uint64_t fp_r6_cmp (SIM_STATE, uint64_t op1, uint64_t op2, 772 FP_formats fmt, int cond); 773 #define R6Compare(op1,op2,fmt,cond) fp_r6_cmp(SIM_ARGS, op1, op2, fmt, cond) 774 uint64_t fp_classify(SIM_STATE, uint64_t op, FP_formats fmt); 775 #define Classify(op, fmt) fp_classify(SIM_ARGS, op, fmt) 776 int fp_rint(SIM_STATE, uint64_t op, uint64_t *ans, FP_formats fmt); 777 #define RoundToIntegralExact(op, ans, fmt) fp_rint(SIM_ARGS, op, ans, fmt) 778 uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt); 779 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) 780 uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt); 781 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) 782 uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 783 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) 784 uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 785 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) 786 uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 787 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) 788 uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 789 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) 790 uint64_t fp_min (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 791 #define Min(op1,op2,fmt) fp_min(SIM_ARGS, op1, op2, fmt) 792 uint64_t fp_max (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 793 #define Max(op1,op2,fmt) fp_max(SIM_ARGS, op1, op2, fmt) 794 uint64_t fp_mina (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 795 #define MinA(op1,op2,fmt) fp_mina(SIM_ARGS, op1, op2, fmt) 796 uint64_t fp_maxa (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 797 #define MaxA(op1,op2,fmt) fp_maxa(SIM_ARGS, op1, op2, fmt) 798 uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt); 799 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) 800 uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt); 801 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) 802 uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt); 803 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) 804 uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2, 805 uint64_t op3, FP_formats fmt); 806 #define FusedMultiplyAdd(op1,op2,op3,fmt) fp_fmadd(SIM_ARGS, op1, op2, op3, fmt) 807 uint64_t fp_fmadd (SIM_STATE, uint64_t op1, uint64_t op2, 808 uint64_t op3, FP_formats fmt); 809 #define FusedMultiplySub(op1,op2,op3,fmt) fp_fmsub(SIM_ARGS, op1, op2, op3, fmt) 810 uint64_t fp_fmsub (SIM_STATE, uint64_t op1, uint64_t op2, 811 uint64_t op3, FP_formats fmt); 812 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) 813 uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2, 814 uint64_t op3, FP_formats fmt); 815 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) 816 uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2, 817 uint64_t op3, FP_formats fmt); 818 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) 819 uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2, 820 uint64_t op3, FP_formats fmt); 821 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) 822 uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to); 823 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) 824 uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from, 825 FP_formats to); 826 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) 827 828 829 /* MIPS-3D ASE operations. */ 830 #define CompareAbs(op1,op2,fmt,cond,cc) \ 831 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) 832 uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 833 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) 834 uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 835 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) 836 uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt); 837 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) 838 uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 839 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) 840 uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt); 841 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) 842 uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 843 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) 844 845 846 /* MDMX access. */ 847 848 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ 849 #define ob_fmtsel(sel) (((sel)<<1)|0x0) 850 #define qh_fmtsel(sel) (((sel)<<2)|0x1) 851 852 #define fmt_mdmx fmt_uninterpreted 853 854 #define MX_VECT_AND (0) 855 #define MX_VECT_NOR (1) 856 #define MX_VECT_OR (2) 857 #define MX_VECT_XOR (3) 858 #define MX_VECT_SLL (4) 859 #define MX_VECT_SRL (5) 860 #define MX_VECT_ADD (6) 861 #define MX_VECT_SUB (7) 862 #define MX_VECT_MIN (8) 863 #define MX_VECT_MAX (9) 864 #define MX_VECT_MUL (10) 865 #define MX_VECT_MSGN (11) 866 #define MX_VECT_SRA (12) 867 #define MX_VECT_ABSD (13) /* SB-1 only. */ 868 #define MX_VECT_AVG (14) /* SB-1 only. */ 869 870 uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 871 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) 872 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) 873 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) 874 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) 875 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) 876 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) 877 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) 878 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) 879 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) 880 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) 881 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) 882 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) 883 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) 884 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) 885 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) 886 887 #define MX_C_EQ 0x1 888 #define MX_C_LT 0x4 889 890 void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel); 891 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) 892 893 uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel); 894 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) 895 896 #define MX_VECT_ADDA (0) 897 #define MX_VECT_ADDL (1) 898 #define MX_VECT_MULA (2) 899 #define MX_VECT_MULL (3) 900 #define MX_VECT_MULS (4) 901 #define MX_VECT_MULSL (5) 902 #define MX_VECT_SUBA (6) 903 #define MX_VECT_SUBL (7) 904 #define MX_VECT_ABSDA (8) /* SB-1 only. */ 905 906 void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 907 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) 908 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) 909 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) 910 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) 911 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) 912 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) 913 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) 914 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) 915 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) 916 917 #define MX_FMT_OB (0) 918 #define MX_FMT_QH (1) 919 920 /* The following codes chosen to indicate the units of shift. */ 921 #define MX_RAC_L (0) 922 #define MX_RAC_M (1) 923 #define MX_RAC_H (2) 924 925 uint64_t mdmx_rac_op (SIM_STATE, int, int); 926 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) 927 928 void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t); 929 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) 930 void mdmx_wach (SIM_STATE, int, uint64_t); 931 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) 932 933 #define MX_RND_AS (0) 934 #define MX_RND_AU (1) 935 #define MX_RND_ES (2) 936 #define MX_RND_EU (3) 937 #define MX_RND_ZS (4) 938 #define MX_RND_ZU (5) 939 940 uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 941 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) 942 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) 943 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) 944 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) 945 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) 946 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) 947 948 uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t); 949 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) 950 951 952 953 /* Memory accesses */ 954 955 /* The following are generic to all versions of the MIPS architecture 956 to date: */ 957 958 #define isINSTRUCTION (1 == 0) /* FALSE */ 959 #define isDATA (1 == 1) /* TRUE */ 960 #define isLOAD (1 == 0) /* FALSE */ 961 #define isSTORE (1 == 1) /* TRUE */ 962 #define isREAL (1 == 0) /* FALSE */ 963 #define isRAW (1 == 1) /* TRUE */ 964 /* The parameter HOST (isTARGET / isHOST) is ignored */ 965 #define isTARGET (1 == 0) /* FALSE */ 966 /* #define isHOST (1 == 1) TRUE */ 967 968 /* The "AccessLength" specifications for Loads and Stores. NOTE: This 969 is the number of bytes minus 1. */ 970 #define AccessLength_BYTE (0) 971 #define AccessLength_HALFWORD (1) 972 #define AccessLength_TRIPLEBYTE (2) 973 #define AccessLength_WORD (3) 974 #define AccessLength_QUINTIBYTE (4) 975 #define AccessLength_SEXTIBYTE (5) 976 #define AccessLength_SEPTIBYTE (6) 977 #define AccessLength_DOUBLEWORD (7) 978 #define AccessLength_QUADWORD (15) 979 980 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \ 981 ? AccessLength_DOUBLEWORD /*7*/ \ 982 : AccessLength_WORD /*3*/) 983 984 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); 985 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ 986 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) 987 988 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); 989 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 990 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) 991 992 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); 993 #define CacheOp(op,pAddr,vAddr,instruction) \ 994 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) 995 996 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype); 997 #define SyncOperation(stype) \ 998 sync_operation (SD, CPU, cia, (stype)) 999 1000 void unpredictable_action (sim_cpu *cpu, address_word cia); 1001 #define NotWordValue(val) not_word_value (SD_, (val)) 1002 #define Unpredictable() unpredictable (SD_) 1003 #define UnpredictableResult() /* For now, do nothing. */ 1004 1005 INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 1006 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) 1007 INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 1008 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) 1009 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) 1010 #define IMEM32_MICROMIPS(CIA) \ 1011 (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \ 1012 (CIA + 2))) 1013 #define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA))) 1014 1015 #define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10) 1016 1017 #define MICROMIPS_DELAYSLOT_SIZE_ANY 0 1018 #define MICROMIPS_DELAYSLOT_SIZE_16 2 1019 #define MICROMIPS_DELAYSLOT_SIZE_32 4 1020 1021 extern int isa_mode; 1022 1023 #define ISA_MODE_MIPS32 0 1024 #define ISA_MODE_MICROMIPS 1 1025 1026 address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu, 1027 address_word cia, 1028 int instruction_size); 1029 1030 #if WITH_TRACE_ANY_P 1031 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, address_word address, int width, const char *comment, ...) ATTRIBUTE_PRINTF (7, 8); 1032 extern FILE *tracefh; 1033 #else 1034 #define dotrace(sd, cpu, tracefh, type, address, width, comment, ...) 1035 #endif 1036 1037 extern int DSPLO_REGNUM[4]; 1038 extern int DSPHI_REGNUM[4]; 1039 1040 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia); 1041 extern SIM_CORE_SIGNAL_FN mips_core_signal ATTRIBUTE_NORETURN; 1042 1043 char* pr_addr (address_word addr); 1044 char* pr_uword64 (uword64 addr); 1045 1046 1047 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) 1048 1049 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 1050 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 1051 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 1052 1053 /* Macros for determining whether a MIPS IV or MIPS V part is subject 1054 to the hi/lo restrictions described in mips.igen. */ 1055 1056 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ 1057 (STATE_ARCHITECTURE (SD)->mach != bfd_mach_mips5500) 1058 1059 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ 1060 (STATE_ARCHITECTURE (SD)->mach != bfd_mach_mips5500) 1061 1062 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ 1063 (STATE_ARCHITECTURE (SD)->mach != bfd_mach_mips5500) 1064 1065 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) 1066 #include "sim-main.c" 1067 #endif 1068 1069 #endif 1070
Indexes created Sat Apr 11 00:22:22 UTC 2026