sim-main.h revision 1.1.1.3
1 /* MIPS Simulator definition. 2 Copyright (C) 1997-2014 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef SIM_MAIN_H 21 #define SIM_MAIN_H 22 23 /* This simulator doesn't cache the Current Instruction Address */ 24 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */ 25 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */ 26 27 #define SIM_HAVE_BIENDIAN 28 29 30 /* hobble some common features for moment */ 31 #define WITH_WATCHPOINTS 1 32 #define WITH_MODULO_MEMORY 1 33 34 35 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ 36 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) 37 38 #include "sim-basics.h" 39 40 typedef address_word sim_cia; 41 42 #include "sim-base.h" 43 #include "bfd.h" 44 45 /* Deprecated macros and types for manipulating 64bit values. Use 46 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ 47 48 typedef signed64 word64; 49 typedef unsigned64 uword64; 50 51 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) 52 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) 53 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF) 54 #define SET64HI(t) (((uword64)(t))<<32) 55 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l)))) 56 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l)) 57 58 /* Check if a value will fit within a halfword: */ 59 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) 60 61 62 63 /* Floating-point operations: */ 64 65 #include "sim-fpu.h" 66 #include "cp1.h" 67 68 /* FPU registers must be one of the following types. All other values 69 are reserved (and undefined). */ 70 typedef enum { 71 fmt_single = 0, 72 fmt_double = 1, 73 fmt_word = 4, 74 fmt_long = 5, 75 fmt_ps = 6, 76 /* The following are well outside the normal acceptable format 77 range, and are used in the register status vector. */ 78 fmt_unknown = 0x10000000, 79 fmt_uninterpreted = 0x20000000, 80 fmt_uninterpreted_32 = 0x40000000, 81 fmt_uninterpreted_64 = 0x80000000U, 82 } FP_formats; 83 84 /* For paired word (pw) operations, the opcode representation is fmt_word, 85 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ 86 #define fmt_pw fmt_long 87 88 /* This should be the COC1 value at the start of the preceding 89 instruction: */ 90 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) 91 92 #ifdef TARGET_ENABLE_FR 93 /* FIXME: this should be enabled for all targets, but needs testing first. */ 94 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \ 95 ? ((SR & status_FR) ? 64 : 32) \ 96 : (WITH_TARGET_FLOATING_POINT_BITSIZE)) 97 #else 98 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) 99 #endif 100 101 102 103 104 105 /* HI/LO register accesses */ 106 107 /* For some MIPS targets, the HI/LO registers have certain timing 108 restrictions in that, for instance, a read of a HI register must be 109 separated by at least three instructions from a preceeding read. 110 111 The struct below is used to record the last access by each of A MT, 112 MF or other OP instruction to a HI/LO register. See mips.igen for 113 more details. */ 114 115 typedef struct _hilo_access { 116 signed64 timestamp; 117 address_word cia; 118 } hilo_access; 119 120 typedef struct _hilo_history { 121 hilo_access mt; 122 hilo_access mf; 123 hilo_access op; 124 } hilo_history; 125 126 127 128 129 /* Integer ALU operations: */ 130 131 #include "sim-alu.h" 132 133 #define ALU32_END(ANS) \ 134 if (ALU32_HAD_OVERFLOW) \ 135 SignalExceptionIntegerOverflow (); \ 136 (ANS) = (signed32) ALU32_OVERFLOW_RESULT 137 138 139 #define ALU64_END(ANS) \ 140 if (ALU64_HAD_OVERFLOW) \ 141 SignalExceptionIntegerOverflow (); \ 142 (ANS) = ALU64_OVERFLOW_RESULT; 143 144 145 146 147 148 /* The following is probably not used for MIPS IV onwards: */ 149 /* Slots for delayed register updates. For the moment we just have a 150 fixed number of slots (rather than a more generic, dynamic 151 system). This keeps the simulator fast. However, we only allow 152 for the register update to be delayed for a single instruction 153 cycle. */ 154 #define PSLOTS (8) /* Maximum number of instruction cycles */ 155 156 typedef struct _pending_write_queue { 157 int in; 158 int out; 159 int total; 160 int slot_delay[PSLOTS]; 161 int slot_size[PSLOTS]; 162 int slot_bit[PSLOTS]; 163 void *slot_dest[PSLOTS]; 164 unsigned64 slot_value[PSLOTS]; 165 } pending_write_queue; 166 167 #ifndef PENDING_TRACE 168 #define PENDING_TRACE 0 169 #endif 170 #define PENDING_IN ((CPU)->pending.in) 171 #define PENDING_OUT ((CPU)->pending.out) 172 #define PENDING_TOTAL ((CPU)->pending.total) 173 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size) 174 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit) 175 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay) 176 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest) 177 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value) 178 179 /* Invalidate the pending write queue, all pending writes are 180 discarded. */ 181 182 #define PENDING_INVALIDATE() \ 183 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) 184 185 /* Schedule a write to DEST for N cycles time. For 64 bit 186 destinations, schedule two writes. For floating point registers, 187 the caller should schedule a write to both the dest register and 188 the FPR_STATE register. When BIT is non-negative, only BIT of DEST 189 is updated. */ 190 191 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \ 192 do { \ 193 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \ 194 sim_engine_abort (SD, CPU, cia, \ 195 "PENDING_SCHED - buffer overflow\n"); \ 196 if (PENDING_TRACE) \ 197 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \ 198 (unsigned long) cia, (unsigned long) &(DEST), \ 199 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\ 200 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \ 201 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \ 202 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \ 203 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \ 204 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \ 205 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \ 206 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \ 207 PENDING_TOTAL += 1; \ 208 } while (0) 209 210 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1) 211 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT) 212 213 #define PENDING_TICK() pending_tick (SD, CPU, cia) 214 215 #define PENDING_FLUSH() abort () /* think about this one */ 216 #define PENDING_FP() abort () /* think about this one */ 217 218 /* For backward compatibility */ 219 #define PENDING_FILL(R,VAL) \ 220 do { \ 221 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ 222 { \ 223 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ 224 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ 225 } \ 226 else \ 227 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ 228 } while (0) 229 230 231 enum float_operation 232 { 233 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD, 234 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS, 235 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23 236 }; 237 238 239 /* The internal representation of an MDMX accumulator. 240 Note that 24 and 48 bit accumulator elements are represented in 241 32 or 64 bits. Since the accumulators are 2's complement with 242 overflow suppressed, high-order bits can be ignored in most contexts. */ 243 244 typedef signed32 signed24; 245 typedef signed64 signed48; 246 247 typedef union { 248 signed24 ob[8]; 249 signed48 qh[4]; 250 } MDMX_accumulator; 251 252 253 /* Conventional system arguments. */ 254 #define SIM_STATE sim_cpu *cpu, address_word cia 255 #define SIM_ARGS CPU, cia 256 257 struct _sim_cpu { 258 259 260 /* The following are internal simulator state variables: */ 261 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) 262 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) 263 address_word dspc; /* delay-slot PC */ 264 #define DSPC ((CPU)->dspc) 265 266 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET)) 267 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_) 268 269 270 /* State of the simulator */ 271 unsigned int state; 272 unsigned int dsstate; 273 #define STATE ((CPU)->state) 274 #define DSSTATE ((CPU)->dsstate) 275 276 /* Flags in the "state" variable: */ 277 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ 278 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ 279 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ 280 #define simPCOC0 (1 << 17) /* COC[1] from current */ 281 #define simPCOC1 (1 << 18) /* COC[1] from previous */ 282 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ 283 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ 284 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ 285 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ 286 287 #ifndef ENGINE_ISSUE_PREFIX_HOOK 288 #define ENGINE_ISSUE_PREFIX_HOOK() \ 289 { \ 290 /* Perform any pending writes */ \ 291 PENDING_TICK(); \ 292 /* Set previous flag, depending on current: */ \ 293 if (STATE & simPCOC0) \ 294 STATE |= simPCOC1; \ 295 else \ 296 STATE &= ~simPCOC1; \ 297 /* and update the current value: */ \ 298 if (GETFCC(0)) \ 299 STATE |= simPCOC0; \ 300 else \ 301 STATE &= ~simPCOC0; \ 302 } 303 #endif /* ENGINE_ISSUE_PREFIX_HOOK */ 304 305 306 /* This is nasty, since we have to rely on matching the register 307 numbers used by GDB. Unfortunately, depending on the MIPS target 308 GDB uses different register numbers. We cannot just include the 309 relevant "gdb/tm.h" link, since GDB may not be configured before 310 the sim world, and also the GDB header file requires too much other 311 state. */ 312 313 #ifndef TM_MIPS_H 314 #define LAST_EMBED_REGNUM (96) 315 #define NUM_REGS (LAST_EMBED_REGNUM + 1) 316 317 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ 318 #define FCRCS_REGNUM 70 /* FP control/status */ 319 #define FCRIR_REGNUM 71 /* FP implementation/revision */ 320 #endif 321 322 323 /* To keep this default simulator simple, and fast, we use a direct 324 vector of registers. The internal simulator engine then uses 325 manifests to access the correct slot. */ 326 327 unsigned_word registers[LAST_EMBED_REGNUM + 1]; 328 329 int register_widths[NUM_REGS]; 330 #define REGISTERS ((CPU)->registers) 331 332 #define GPR (®ISTERS[0]) 333 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) 334 335 #define LO (REGISTERS[33]) 336 #define HI (REGISTERS[34]) 337 #define PCIDX 37 338 #define PC (REGISTERS[PCIDX]) 339 #define CAUSE (REGISTERS[36]) 340 #define SRIDX (32) 341 #define SR (REGISTERS[SRIDX]) /* CPU status register */ 342 #define FCR0IDX (71) 343 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */ 344 #define FCR31IDX (70) 345 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */ 346 #define FCSR (FCR31) 347 #define Debug (REGISTERS[86]) 348 #define DEPC (REGISTERS[87]) 349 #define EPC (REGISTERS[88]) 350 #define ACX (REGISTERS[89]) 351 352 #define AC0LOIDX (33) /* Must be the same register as LO */ 353 #define AC0HIIDX (34) /* Must be the same register as HI */ 354 #define AC1LOIDX (90) 355 #define AC1HIIDX (91) 356 #define AC2LOIDX (92) 357 #define AC2HIIDX (93) 358 #define AC3LOIDX (94) 359 #define AC3HIIDX (95) 360 361 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) 362 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) 363 364 #define DSPCRIDX (96) /* DSP control register */ 365 #define DSPCR (REGISTERS[DSPCRIDX]) 366 367 #define DSPCR_POS_SHIFT (0) 368 #define DSPCR_POS_MASK (0x3f) 369 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) 370 371 #define DSPCR_SCOUNT_SHIFT (7) 372 #define DSPCR_SCOUNT_MASK (0x3f) 373 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) 374 375 #define DSPCR_CARRY_SHIFT (13) 376 #define DSPCR_CARRY_MASK (1) 377 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) 378 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) 379 380 #define DSPCR_EFI_SHIFT (14) 381 #define DSPCR_EFI_MASK (1) 382 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) 383 #define DSPCR_EFI (1 << DSPCR_EFI_MASK) 384 385 #define DSPCR_OUFLAG_SHIFT (16) 386 #define DSPCR_OUFLAG_MASK (0xff) 387 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) 388 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) 389 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) 390 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) 391 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) 392 393 #define DSPCR_CCOND_SHIFT (24) 394 #define DSPCR_CCOND_MASK (0xf) 395 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) 396 397 /* All internal state modified by signal_exception() that may need to be 398 rolled back for passing moment-of-exception image back to gdb. */ 399 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1]; 400 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1]; 401 int exc_suspended; 402 403 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA) 404 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC) 405 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC) 406 407 unsigned_word c0_config_reg; 408 #define C0_CONFIG ((CPU)->c0_config_reg) 409 410 /* The following are pseudonyms for standard registers */ 411 #define ZERO (REGISTERS[0]) 412 #define V0 (REGISTERS[2]) 413 #define A0 (REGISTERS[4]) 414 #define A1 (REGISTERS[5]) 415 #define A2 (REGISTERS[6]) 416 #define A3 (REGISTERS[7]) 417 #define T8IDX 24 418 #define T8 (REGISTERS[T8IDX]) 419 #define SPIDX 29 420 #define SP (REGISTERS[SPIDX]) 421 #define RAIDX 31 422 #define RA (REGISTERS[RAIDX]) 423 424 /* While space is allocated in the main registers arrray for some of 425 the COP0 registers, that space isn't sufficient. Unknown COP0 426 registers overflow into the array below */ 427 428 #define NR_COP0_GPR 32 429 unsigned_word cop0_gpr[NR_COP0_GPR]; 430 #define COP0_GPR ((CPU)->cop0_gpr) 431 #define COP0_BADVADDR (COP0_GPR[8]) 432 433 /* While space is allocated for the floating point registers in the 434 main registers array, they are stored separatly. This is because 435 their size may not necessarily match the size of either the 436 general-purpose or system specific registers. */ 437 #define NR_FGR (32) 438 #define FGR_BASE FP0_REGNUM 439 fp_word fgr[NR_FGR]; 440 #define FGR ((CPU)->fgr) 441 442 /* Keep the current format state for each register: */ 443 FP_formats fpr_state[32]; 444 #define FPR_STATE ((CPU)->fpr_state) 445 446 pending_write_queue pending; 447 448 /* The MDMX accumulator (used only for MDMX ASE). */ 449 MDMX_accumulator acc; 450 #define ACC ((CPU)->acc) 451 452 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic 453 read-write instructions. It is set when a linked load occurs. It 454 is tested and cleared by the conditional store. It is cleared 455 (during other CPU operations) when a store to the location would 456 no longer be atomic. In particular, it is cleared by exception 457 return instructions. */ 458 int llbit; 459 #define LLBIT ((CPU)->llbit) 460 461 462 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that 463 corruptions caused by using the HI or LO register too close to a 464 following operation is spotted. See mips.igen for more details. */ 465 466 hilo_history hi_history; 467 #define HIHISTORY (&(CPU)->hi_history) 468 hilo_history lo_history; 469 #define LOHISTORY (&(CPU)->lo_history) 470 471 472 sim_cpu_base base; 473 }; 474 475 476 /* MIPS specific simulator watch config */ 477 478 void watch_options_install (SIM_DESC sd); 479 480 struct swatch { 481 sim_event *pc; 482 sim_event *clock; 483 sim_event *cycles; 484 }; 485 486 487 /* FIXME: At present much of the simulator is still static */ 488 struct sim_state { 489 490 struct swatch watch; 491 492 sim_cpu cpu[MAX_NR_PROCESSORS]; 493 #if (WITH_SMP) 494 #define STATE_CPU(sd,n) (&(sd)->cpu[n]) 495 #else 496 #define STATE_CPU(sd,n) (&(sd)->cpu[0]) 497 #endif 498 499 500 sim_state_base base; 501 }; 502 503 504 505 /* Status information: */ 506 507 /* TODO : these should be the bitmasks for these bits within the 508 status register. At the moment the following are VR4300 509 bit-positions: */ 510 #define status_KSU_mask (0x18) /* mask for KSU bits */ 511 #define status_KSU_shift (3) /* shift for field */ 512 #define ksu_kernel (0x0) 513 #define ksu_supervisor (0x1) 514 #define ksu_user (0x2) 515 #define ksu_unknown (0x3) 516 517 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift) 518 519 #define status_IE (1 << 0) /* Interrupt enable */ 520 #define status_EIE (1 << 16) /* Enable Interrupt Enable */ 521 #define status_EXL (1 << 1) /* Exception level */ 522 #define status_RE (1 << 25) /* Reverse Endian in user mode */ 523 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ 524 #define status_SR (1 << 20) /* soft reset or NMI */ 525 #define status_BEV (1 << 22) /* Location of general exception vectors */ 526 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 527 #define status_ERL (1 << 2) /* Error level */ 528 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */ 529 #define status_RP (1 << 27) /* Reduced Power mode */ 530 531 /* Specializations for TX39 family */ 532 #define status_IEc (1 << 0) /* Interrupt enable (current) */ 533 #define status_KUc (1 << 1) /* Kernel/User mode */ 534 #define status_IEp (1 << 2) /* Interrupt enable (previous) */ 535 #define status_KUp (1 << 3) /* Kernel/User mode */ 536 #define status_IEo (1 << 4) /* Interrupt enable (old) */ 537 #define status_KUo (1 << 5) /* Kernel/User mode */ 538 #define status_IM_mask (0xff) /* Interrupt mask */ 539 #define status_IM_shift (8) 540 #define status_NMI (1 << 20) /* NMI */ 541 #define status_NMI (1 << 20) /* NMI */ 542 543 /* Status bits used by MIPS32/MIPS64. */ 544 #define status_UX (1 << 5) /* 64-bit user addrs */ 545 #define status_SX (1 << 6) /* 64-bit supervisor addrs */ 546 #define status_KX (1 << 7) /* 64-bit kernel addrs */ 547 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 548 #define status_PX (1 << 23) /* Enable 64 bit operations */ 549 #define status_MX (1 << 24) /* Enable MDMX resources */ 550 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */ 551 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */ 552 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */ 553 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */ 554 /* Bits reserved for implementations: */ 555 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ 556 557 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ 558 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ 559 #define cause_CE_mask 0x30000000 /* Coprocessor exception */ 560 #define cause_CE_shift 28 561 #define cause_EXC2_mask 0x00070000 562 #define cause_EXC2_shift 16 563 #define cause_IP7 (1 << 15) /* Interrupt pending */ 564 #define cause_SIOP (1 << 12) /* SIO pending */ 565 #define cause_IP3 (1 << 11) /* Int 0 pending */ 566 #define cause_IP2 (1 << 10) /* Int 1 pending */ 567 568 #define cause_EXC_mask (0x1c) /* Exception code */ 569 #define cause_EXC_shift (2) 570 571 #define cause_SW0 (1 << 8) /* Software interrupt 0 */ 572 #define cause_SW1 (1 << 9) /* Software interrupt 1 */ 573 #define cause_IP_mask (0x3f) /* Interrupt pending field */ 574 #define cause_IP_shift (10) 575 576 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask) 577 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask) 578 579 580 /* NOTE: We keep the following status flags as bit values (1 for true, 581 0 for false). This allows them to be used in binary boolean 582 operations without worrying about what exactly the non-zero true 583 value is. */ 584 585 /* UserMode */ 586 #ifdef SUBTARGET_R3900 587 #define UserMode ((SR & status_KUc) ? 1 : 0) 588 #else 589 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) 590 #endif /* SUBTARGET_R3900 */ 591 592 /* BigEndianMem */ 593 /* Hardware configuration. Affects endianness of LoadMemory and 594 StoreMemory and the endianness of Kernel and Supervisor mode 595 execution. The value is 0 for little-endian; 1 for big-endian. */ 596 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) 597 /*(state & simBE) ? 1 : 0)*/ 598 599 /* ReverseEndian */ 600 /* This mode is selected if in User mode with the RE bit being set in 601 SR (Status Register). It reverses the endianness of load and store 602 instructions. */ 603 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) 604 605 /* BigEndianCPU */ 606 /* The endianness for load and store instructions (0=little;1=big). In 607 User mode this endianness may be switched by setting the state_RE 608 bit in the SR register. Thus, BigEndianCPU may be computed as 609 (BigEndianMem EOR ReverseEndian). */ 610 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ 611 612 613 614 /* Exceptions: */ 615 616 /* NOTE: These numbers depend on the processor architecture being 617 simulated: */ 618 enum ExceptionCause { 619 Interrupt = 0, 620 TLBModification = 1, 621 TLBLoad = 2, 622 TLBStore = 3, 623 AddressLoad = 4, 624 AddressStore = 5, 625 InstructionFetch = 6, 626 DataReference = 7, 627 SystemCall = 8, 628 BreakPoint = 9, 629 ReservedInstruction = 10, 630 CoProcessorUnusable = 11, 631 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ 632 Trap = 13, 633 FPE = 15, 634 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ 635 MDMX = 22, 636 Watch = 23, 637 MCheck = 24, 638 CacheErr = 30, 639 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ 640 641 642 /* The following exception code is actually private to the simulator 643 world. It is *NOT* a processor feature, and is used to signal 644 run-time errors in the simulator. */ 645 SimulatorFault = 0xFFFFFFFF 646 }; 647 648 #define TLB_REFILL (0) 649 #define TLB_INVALID (1) 650 651 652 /* The following break instructions are reserved for use by the 653 simulator. The first is used to halt the simulation. The second 654 is used by gdb for break-points. NOTE: Care must be taken, since 655 this value may be used in later revisions of the MIPS ISA. */ 656 #define HALT_INSTRUCTION_MASK (0x03FFFFC0) 657 658 #define HALT_INSTRUCTION (0x03ff000d) 659 #define HALT_INSTRUCTION2 (0x0000ffcd) 660 661 662 #define BREAKPOINT_INSTRUCTION (0x0005000d) 663 #define BREAKPOINT_INSTRUCTION2 (0x0000014d) 664 665 666 667 void interrupt_event (SIM_DESC sd, void *data); 668 669 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); 670 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) 671 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level) 672 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) 673 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) 674 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) 675 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference) 676 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) 677 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) 678 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) 679 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable) 680 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset) 681 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL) 682 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL) 683 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) 684 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) 685 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) 686 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) 687 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) 688 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) 689 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) 690 691 /* Co-processor accesses */ 692 693 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ 694 #define COP_Usable(coproc_num) (coproc_num == 1) 695 696 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword); 697 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword); 698 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 699 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 700 701 #define COP_LW(coproc_num,coproc_reg,memword) \ 702 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) 703 #define COP_LD(coproc_num,coproc_reg,memword) \ 704 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) 705 #define COP_SW(coproc_num,coproc_reg) \ 706 cop_sw (SD, CPU, cia, coproc_num, coproc_reg) 707 #define COP_SD(coproc_num,coproc_reg) \ 708 cop_sd (SD, CPU, cia, coproc_num, coproc_reg) 709 710 711 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction); 712 #define DecodeCoproc(instruction) \ 713 decode_coproc (SD, CPU, cia, (instruction)) 714 715 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); 716 717 718 /* FPR access. */ 719 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); 720 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) 721 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); 722 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) 723 unsigned64 ps_lower (SIM_STATE, unsigned64 op); 724 #define PSLower(op) ps_lower (SIM_ARGS, op) 725 unsigned64 ps_upper (SIM_STATE, unsigned64 op); 726 #define PSUpper(op) ps_upper (SIM_ARGS, op) 727 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); 728 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) 729 730 731 /* FCR access. */ 732 unsigned_word value_fcr (SIM_STATE, int fcr); 733 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) 734 void store_fcr (SIM_STATE, int fcr, unsigned_word value); 735 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) 736 void test_fcsr (SIM_STATE); 737 #define TestFCSR() test_fcsr (SIM_ARGS) 738 739 740 /* FPU operations. */ 741 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); 742 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) 743 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); 744 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) 745 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); 746 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) 747 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 748 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) 749 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 750 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) 751 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 752 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) 753 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 754 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) 755 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); 756 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) 757 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 758 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) 759 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 760 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) 761 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, 762 unsigned64 op3, FP_formats fmt); 763 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) 764 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, 765 unsigned64 op3, FP_formats fmt); 766 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) 767 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, 768 unsigned64 op3, FP_formats fmt); 769 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) 770 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, 771 unsigned64 op3, FP_formats fmt); 772 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) 773 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); 774 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) 775 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, 776 FP_formats to); 777 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) 778 779 780 /* MIPS-3D ASE operations. */ 781 #define CompareAbs(op1,op2,fmt,cond,cc) \ 782 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) 783 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 784 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) 785 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 786 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) 787 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); 788 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) 789 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 790 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) 791 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); 792 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) 793 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 794 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) 795 796 797 /* MDMX access. */ 798 799 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ 800 #define ob_fmtsel(sel) (((sel)<<1)|0x0) 801 #define qh_fmtsel(sel) (((sel)<<2)|0x1) 802 803 #define fmt_mdmx fmt_uninterpreted 804 805 #define MX_VECT_AND (0) 806 #define MX_VECT_NOR (1) 807 #define MX_VECT_OR (2) 808 #define MX_VECT_XOR (3) 809 #define MX_VECT_SLL (4) 810 #define MX_VECT_SRL (5) 811 #define MX_VECT_ADD (6) 812 #define MX_VECT_SUB (7) 813 #define MX_VECT_MIN (8) 814 #define MX_VECT_MAX (9) 815 #define MX_VECT_MUL (10) 816 #define MX_VECT_MSGN (11) 817 #define MX_VECT_SRA (12) 818 #define MX_VECT_ABSD (13) /* SB-1 only. */ 819 #define MX_VECT_AVG (14) /* SB-1 only. */ 820 821 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 822 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) 823 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) 824 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) 825 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) 826 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) 827 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) 828 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) 829 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) 830 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) 831 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) 832 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) 833 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) 834 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) 835 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) 836 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) 837 838 #define MX_C_EQ 0x1 839 #define MX_C_LT 0x4 840 841 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); 842 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) 843 844 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); 845 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) 846 847 #define MX_VECT_ADDA (0) 848 #define MX_VECT_ADDL (1) 849 #define MX_VECT_MULA (2) 850 #define MX_VECT_MULL (3) 851 #define MX_VECT_MULS (4) 852 #define MX_VECT_MULSL (5) 853 #define MX_VECT_SUBA (6) 854 #define MX_VECT_SUBL (7) 855 #define MX_VECT_ABSDA (8) /* SB-1 only. */ 856 857 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 858 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) 859 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) 860 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) 861 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) 862 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) 863 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) 864 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) 865 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) 866 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) 867 868 #define MX_FMT_OB (0) 869 #define MX_FMT_QH (1) 870 871 /* The following codes chosen to indicate the units of shift. */ 872 #define MX_RAC_L (0) 873 #define MX_RAC_M (1) 874 #define MX_RAC_H (2) 875 876 unsigned64 mdmx_rac_op (SIM_STATE, int, int); 877 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) 878 879 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); 880 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) 881 void mdmx_wach (SIM_STATE, int, unsigned64); 882 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) 883 884 #define MX_RND_AS (0) 885 #define MX_RND_AU (1) 886 #define MX_RND_ES (2) 887 #define MX_RND_EU (3) 888 #define MX_RND_ZS (4) 889 #define MX_RND_ZU (5) 890 891 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 892 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) 893 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) 894 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) 895 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) 896 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) 897 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) 898 899 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); 900 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) 901 902 903 904 /* Memory accesses */ 905 906 /* The following are generic to all versions of the MIPS architecture 907 to date: */ 908 909 /* Memory Access Types (for CCA): */ 910 #define Uncached (0) 911 #define CachedNoncoherent (1) 912 #define CachedCoherent (2) 913 #define Cached (3) 914 915 #define isINSTRUCTION (1 == 0) /* FALSE */ 916 #define isDATA (1 == 1) /* TRUE */ 917 #define isLOAD (1 == 0) /* FALSE */ 918 #define isSTORE (1 == 1) /* TRUE */ 919 #define isREAL (1 == 0) /* FALSE */ 920 #define isRAW (1 == 1) /* TRUE */ 921 /* The parameter HOST (isTARGET / isHOST) is ignored */ 922 #define isTARGET (1 == 0) /* FALSE */ 923 /* #define isHOST (1 == 1) TRUE */ 924 925 /* The "AccessLength" specifications for Loads and Stores. NOTE: This 926 is the number of bytes minus 1. */ 927 #define AccessLength_BYTE (0) 928 #define AccessLength_HALFWORD (1) 929 #define AccessLength_TRIPLEBYTE (2) 930 #define AccessLength_WORD (3) 931 #define AccessLength_QUINTIBYTE (4) 932 #define AccessLength_SEXTIBYTE (5) 933 #define AccessLength_SEPTIBYTE (6) 934 #define AccessLength_DOUBLEWORD (7) 935 #define AccessLength_QUADWORD (15) 936 937 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \ 938 ? AccessLength_DOUBLEWORD /*7*/ \ 939 : AccessLength_WORD /*3*/) 940 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) 941 942 943 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw); 944 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ 945 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) 946 947 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); 948 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ 949 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) 950 951 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); 952 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 953 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) 954 955 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); 956 #define CacheOp(op,pAddr,vAddr,instruction) \ 957 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) 958 959 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype); 960 #define SyncOperation(stype) \ 961 sync_operation (SD, CPU, cia, (stype)) 962 963 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint); 964 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ 965 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) 966 967 void unpredictable_action (sim_cpu *cpu, address_word cia); 968 #define NotWordValue(val) not_word_value (SD_, (val)) 969 #define Unpredictable() unpredictable (SD_) 970 #define UnpredictableResult() /* For now, do nothing. */ 971 972 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 973 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) 974 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 975 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) 976 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) 977 978 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...); 979 extern FILE *tracefh; 980 981 extern int DSPLO_REGNUM[4]; 982 extern int DSPHI_REGNUM[4]; 983 984 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia); 985 extern SIM_CORE_SIGNAL_FN mips_core_signal; 986 987 char* pr_addr (SIM_ADDR addr); 988 char* pr_uword64 (uword64 addr); 989 990 991 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) 992 993 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 994 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 995 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 996 997 #ifdef MIPS_MACH_MULTI 998 extern int mips_mach_multi(SIM_DESC sd); 999 #define MIPS_MACH(SD) mips_mach_multi(SD) 1000 #else 1001 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT 1002 #endif 1003 1004 /* Macros for determining whether a MIPS IV or MIPS V part is subject 1005 to the hi/lo restrictions described in mips.igen. */ 1006 1007 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ 1008 (MIPS_MACH (SD) != bfd_mach_mips5500) 1009 1010 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ 1011 (MIPS_MACH (SD) != bfd_mach_mips5500) 1012 1013 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ 1014 (MIPS_MACH (SD) != bfd_mach_mips5500) 1015 1016 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) 1017 #include "sim-main.c" 1018 #endif 1019 1020 #endif 1021
Indexes created Tue Apr 14 00:22:26 UTC 2026