extw.s revision 1.1
1 # Hitachi H8 testcase 'exts.w, extu.w' 2 # mach(): h8300h h8300s h8sx 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .data 16 .align 2 17 pos: .word 0xff01 18 neg: .word 0x0080 19 20 .text 21 22 exts_w_reg16_p: 23 set_grs_a5a5 24 set_ccr_zero 25 ;; exts.w rn16 26 mov.b #1, r0l 27 exts.w r0 28 29 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 30 test_cc_clear 31 32 test_h_gr32 0xa5a50001 er0 ; result of sign extend 33 test_gr_a5a5 1 ; Make sure other general regs not disturbed 34 test_gr_a5a5 2 35 test_gr_a5a5 3 36 test_gr_a5a5 4 37 test_gr_a5a5 5 38 test_gr_a5a5 6 39 test_gr_a5a5 7 40 41 exts_w_reg16_n: 42 set_grs_a5a5 43 set_ccr_zero 44 ;; exts.w rn16 45 mov.b #0xff, r0l 46 exts.w r0 47 48 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 49 test_neg_set 50 test_zero_clear 51 test_ovf_clear 52 test_carry_clear 53 54 test_h_gr32 0xa5a5ffff er0 ; result of sign extend 55 test_gr_a5a5 1 ; Make sure other general regs not disturbed 56 test_gr_a5a5 2 57 test_gr_a5a5 3 58 test_gr_a5a5 4 59 test_gr_a5a5 5 60 test_gr_a5a5 6 61 test_gr_a5a5 7 62 63 extu_w_reg16_n: 64 set_grs_a5a5 65 set_ccr_zero 66 ;; extu.w rn16 67 mov.b #0xff, r0l 68 extu.w r0 69 70 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 71 test_cc_clear 72 73 test_h_gr32 0xa5a500ff er0 ; result of zero extend 74 test_gr_a5a5 1 ; Make sure other general regs not disturbed 75 test_gr_a5a5 2 76 test_gr_a5a5 3 77 test_gr_a5a5 4 78 test_gr_a5a5 5 79 test_gr_a5a5 6 80 test_gr_a5a5 7 81 82 .if (sim_cpu == h8sx) 83 exts_w_ind_p: 84 set_grs_a5a5 85 set_ccr_zero 86 ;; exts.w @ern 87 mov.l #pos, er1 88 exts.w @er1 89 90 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 91 test_cc_clear 92 93 test_h_gr32 pos er1 ; er1 still contains target address 94 test_gr_a5a5 0 ; Make sure other general regs not disturbed 95 test_gr_a5a5 2 96 test_gr_a5a5 3 97 test_gr_a5a5 4 98 test_gr_a5a5 5 99 test_gr_a5a5 6 100 test_gr_a5a5 7 101 cmp.w #0x0001, @pos 102 beq .Lswindp 103 fail 104 .Lswindp: 105 mov.w #0xff01, @pos ; Restore initial value 106 107 exts_w_ind_n: 108 set_grs_a5a5 109 set_ccr_zero 110 ;; exts.w @ern 111 mov.l #neg, er1 112 exts.w @er1 113 114 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 115 test_neg_set 116 test_zero_clear 117 test_ovf_clear 118 test_carry_clear 119 120 test_h_gr32 neg er1 ; er1 still contains target address 121 test_gr_a5a5 0 ; Make sure other general regs not disturbed 122 test_gr_a5a5 2 123 test_gr_a5a5 3 124 test_gr_a5a5 4 125 test_gr_a5a5 5 126 test_gr_a5a5 6 127 test_gr_a5a5 7 128 cmp.w #0xff80, @neg 129 beq .Lswindn 130 fail 131 .Lswindn: 132 ;; Note: leave the value as 0xff80, so that extu has work to do. 133 134 extu_w_ind_n: 135 set_grs_a5a5 136 set_ccr_zero 137 ;; extu.w @ern 138 mov.l #neg, er1 139 extu.w @er1 140 141 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 142 test_cc_clear 143 144 test_h_gr32 neg er1 ; er1 still contains target address 145 test_gr_a5a5 0 ; Make sure other general regs not disturbed 146 test_gr_a5a5 2 147 test_gr_a5a5 3 148 test_gr_a5a5 4 149 test_gr_a5a5 5 150 test_gr_a5a5 6 151 test_gr_a5a5 7 152 cmp.w #0x0080, @neg 153 beq .Luwindn 154 fail 155 .Luwindn: 156 ;; Note: leave the value as 0x0080, like it started out. 157 158 exts_w_postinc_p: 159 set_grs_a5a5 160 set_ccr_zero 161 ;; exts.w @ern+ 162 mov.l #pos, er1 163 exts.w @er1+ 164 165 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 166 test_cc_clear 167 168 test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 169 test_gr_a5a5 0 ; Make sure other general regs not disturbed 170 test_gr_a5a5 2 171 test_gr_a5a5 3 172 test_gr_a5a5 4 173 test_gr_a5a5 5 174 test_gr_a5a5 6 175 test_gr_a5a5 7 176 cmp.w #0x0001, @pos 177 beq .Lswpostincp 178 fail 179 .Lswpostincp: 180 mov.w #0xff01, @pos ; Restore initial value 181 182 exts_w_postinc_n: 183 set_grs_a5a5 184 set_ccr_zero 185 ;; exts.w @ern+ 186 mov.l #neg, er1 187 exts.w @er1+ 188 189 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 190 test_neg_set 191 test_zero_clear 192 test_ovf_clear 193 test_carry_clear 194 195 test_h_gr32 neg+2 er1 ; er1 still contains target address 196 test_gr_a5a5 0 ; Make sure other general regs not disturbed 197 test_gr_a5a5 2 198 test_gr_a5a5 3 199 test_gr_a5a5 4 200 test_gr_a5a5 5 201 test_gr_a5a5 6 202 test_gr_a5a5 7 203 cmp.w #0xff80, @neg 204 beq .Lswpostincn 205 fail 206 .Lswpostincn: 207 ;; Note: leave the value as 0xff80, so that extu has work to do. 208 209 extu_w_postinc_n: 210 set_grs_a5a5 211 set_ccr_zero 212 ;; extu.w @ern+ 213 mov.l #neg, er1 214 extu.w @er1+ 215 216 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 217 test_cc_clear 218 219 test_h_gr32 neg+2 er1 ; er1 still contains target address 220 test_gr_a5a5 0 ; Make sure other general regs not disturbed 221 test_gr_a5a5 2 222 test_gr_a5a5 3 223 test_gr_a5a5 4 224 test_gr_a5a5 5 225 test_gr_a5a5 6 226 test_gr_a5a5 7 227 cmp.w #0x0080, @neg 228 beq .Luwpostincn 229 fail 230 .Luwpostincn: 231 ;; Note: leave the value as 0x0080, like it started out. 232 233 exts_w_postdec_p: 234 set_grs_a5a5 235 set_ccr_zero 236 ;; exts.w @ern- 237 mov.l #pos, er1 238 exts.w @er1- 239 240 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 241 test_cc_clear 242 243 test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 244 test_gr_a5a5 0 ; Make sure other general regs not disturbed 245 test_gr_a5a5 2 246 test_gr_a5a5 3 247 test_gr_a5a5 4 248 test_gr_a5a5 5 249 test_gr_a5a5 6 250 test_gr_a5a5 7 251 cmp.w #0x0001, @pos 252 beq .Lswpostdecp 253 fail 254 .Lswpostdecp: 255 mov.w #0xff01, @pos ; Restore initial value 256 257 exts_w_postdec_n: 258 set_grs_a5a5 259 set_ccr_zero 260 ;; exts.w @ern- 261 mov.l #neg, er1 262 exts.w @er1- 263 264 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 265 test_neg_set 266 test_zero_clear 267 test_ovf_clear 268 test_carry_clear 269 270 test_h_gr32 neg-2 er1 ; er1 still contains target address 271 test_gr_a5a5 0 ; Make sure other general regs not disturbed 272 test_gr_a5a5 2 273 test_gr_a5a5 3 274 test_gr_a5a5 4 275 test_gr_a5a5 5 276 test_gr_a5a5 6 277 test_gr_a5a5 7 278 cmp.w #0xff80, @neg 279 beq .Lswpostdecn 280 fail 281 .Lswpostdecn: 282 ;; Note: leave the value as 0xff80, so that extu has work to do. 283 284 extu_w_postdec_n: 285 set_grs_a5a5 286 set_ccr_zero 287 ;; extu.w @ern- 288 mov.l #neg, er1 289 extu.w @er1- 290 291 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 292 test_cc_clear 293 294 test_h_gr32 neg-2 er1 ; er1 still contains target address 295 test_gr_a5a5 0 ; Make sure other general regs not disturbed 296 test_gr_a5a5 2 297 test_gr_a5a5 3 298 test_gr_a5a5 4 299 test_gr_a5a5 5 300 test_gr_a5a5 6 301 test_gr_a5a5 7 302 cmp.w #0x0080, @neg 303 beq .Luwpostdecn 304 fail 305 .Luwpostdecn: 306 ;; Note: leave the value as 0x0080, like it started out. 307 308 exts_w_preinc_p: 309 set_grs_a5a5 310 set_ccr_zero 311 ;; exts.w @+ern 312 mov.l #pos-2, er1 313 exts.w @+er1 314 315 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 316 test_cc_clear 317 318 test_h_gr32 pos er1 ; er1 still contains target address plus 2 319 test_gr_a5a5 0 ; Make sure other general regs not disturbed 320 test_gr_a5a5 2 321 test_gr_a5a5 3 322 test_gr_a5a5 4 323 test_gr_a5a5 5 324 test_gr_a5a5 6 325 test_gr_a5a5 7 326 cmp.w #0x0001, @pos 327 beq .Lswpreincp 328 fail 329 .Lswpreincp: 330 mov.w #0xff01, @pos ; Restore initial value 331 332 exts_w_preinc_n: 333 set_grs_a5a5 334 set_ccr_zero 335 ;; exts.w @+ern 336 mov.l #neg-2, er1 337 exts.w @+er1 338 339 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 340 test_neg_set 341 test_zero_clear 342 test_ovf_clear 343 test_carry_clear 344 345 test_h_gr32 neg er1 ; er1 still contains target address 346 test_gr_a5a5 0 ; Make sure other general regs not disturbed 347 test_gr_a5a5 2 348 test_gr_a5a5 3 349 test_gr_a5a5 4 350 test_gr_a5a5 5 351 test_gr_a5a5 6 352 test_gr_a5a5 7 353 cmp.w #0xff80, @neg 354 beq .Lswpreincn 355 fail 356 .Lswpreincn: 357 ;; Note: leave the value as 0xff80, so that extu has work to do. 358 359 extu_w_preinc_n: 360 set_grs_a5a5 361 set_ccr_zero 362 ;; extu.w @+ern 363 mov.l #neg-2, er1 364 extu.w @+er1 365 366 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 367 test_cc_clear 368 369 test_h_gr32 neg er1 ; er1 still contains target address 370 test_gr_a5a5 0 ; Make sure other general regs not disturbed 371 test_gr_a5a5 2 372 test_gr_a5a5 3 373 test_gr_a5a5 4 374 test_gr_a5a5 5 375 test_gr_a5a5 6 376 test_gr_a5a5 7 377 cmp.w #0x0080, @neg 378 beq .Luwpreincn 379 fail 380 .Luwpreincn: 381 ;; Note: leave the value as 0x0080, like it started out. 382 383 exts_w_predec_p: 384 set_grs_a5a5 385 set_ccr_zero 386 ;; exts.w @-ern 387 mov.l #pos+2, er1 388 exts.w @-er1 389 390 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 391 test_cc_clear 392 393 test_h_gr32 pos er1 ; er1 still contains target address plus 2 394 test_gr_a5a5 0 ; Make sure other general regs not disturbed 395 test_gr_a5a5 2 396 test_gr_a5a5 3 397 test_gr_a5a5 4 398 test_gr_a5a5 5 399 test_gr_a5a5 6 400 test_gr_a5a5 7 401 cmp.w #0x0001, @pos 402 beq .Lswpredecp 403 fail 404 .Lswpredecp: 405 mov.w #0xff01, @pos ; Restore initial value 406 407 exts_w_predec_n: 408 set_grs_a5a5 409 set_ccr_zero 410 ;; exts.w @-ern 411 mov.l #neg+2, er1 412 exts.w @-er1 413 414 ;; Test ccr H=0 N=1 Z=0 V=0 C=0 415 test_neg_set 416 test_zero_clear 417 test_ovf_clear 418 test_carry_clear 419 420 test_h_gr32 neg er1 ; er1 still contains target address 421 test_gr_a5a5 0 ; Make sure other general regs not disturbed 422 test_gr_a5a5 2 423 test_gr_a5a5 3 424 test_gr_a5a5 4 425 test_gr_a5a5 5 426 test_gr_a5a5 6 427 test_gr_a5a5 7 428 cmp.w #0xff80, @neg 429 beq .Lswpredecn 430 fail 431 .Lswpredecn: 432 ;; Note: leave the value as 0xff80, so that extu has work to do. 433 434 extu_w_predec_n: 435 set_grs_a5a5 436 set_ccr_zero 437 ;; extu.w @-ern 438 mov.l #neg+2, er1 439 extu.w @-er1 440 441 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 442 test_cc_clear 443 444 test_h_gr32 neg er1 ; er1 still contains target address 445 test_gr_a5a5 0 ; Make sure other general regs not disturbed 446 test_gr_a5a5 2 447 test_gr_a5a5 3 448 test_gr_a5a5 4 449 test_gr_a5a5 5 450 test_gr_a5a5 6 451 test_gr_a5a5 7 452 cmp.w #0x0080, @neg 453 beq .Luwpredecn 454 fail 455 .Luwpredecn: 456 ;; Note: leave the value as 0x0080, like it started out. 457 458 extu_w_disp2_n: 459 set_grs_a5a5 460 set_ccr_zero 461 ;; extu.w @(dd:2, ern) 462 mov.l #neg-2, er1 463 extu.w @(2:2, er1) 464 465 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 466 test_cc_clear 467 468 test_h_gr32 neg-2 er1 ; er1 still contains target address 469 test_gr_a5a5 0 ; Make sure other general regs not disturbed 470 test_gr_a5a5 2 471 test_gr_a5a5 3 472 test_gr_a5a5 4 473 test_gr_a5a5 5 474 test_gr_a5a5 6 475 test_gr_a5a5 7 476 cmp.w #0x0080, @neg 477 beq .Luwdisp2n 478 fail 479 .Luwdisp2n: 480 ;; Note: leave the value as 0x0080, like it started out. 481 482 extu_w_disp16_n: 483 set_grs_a5a5 484 set_ccr_zero 485 ;; extu.w @(dd:16, ern) 486 mov.l #neg-44, er1 487 extu.w @(44:16, er1) 488 489 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 490 test_cc_clear 491 492 test_h_gr32 neg-44 er1 ; er1 still contains target address 493 test_gr_a5a5 0 ; Make sure other general regs not disturbed 494 test_gr_a5a5 2 495 test_gr_a5a5 3 496 test_gr_a5a5 4 497 test_gr_a5a5 5 498 test_gr_a5a5 6 499 test_gr_a5a5 7 500 cmp.w #0x0080, @neg 501 beq .Luwdisp16n 502 fail 503 .Luwdisp16n: 504 ;; Note: leave the value as 0x0080, like it started out. 505 506 extu_w_disp32_n: 507 set_grs_a5a5 508 set_ccr_zero 509 ;; extu.w @(dd:32, ern) 510 mov.l #neg+444, er1 511 extu.w @(-444:32, er1) 512 513 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 514 test_cc_clear 515 516 test_h_gr32 neg+444 er1 ; er1 still contains target address 517 test_gr_a5a5 0 ; Make sure other general regs not disturbed 518 test_gr_a5a5 2 519 test_gr_a5a5 3 520 test_gr_a5a5 4 521 test_gr_a5a5 5 522 test_gr_a5a5 6 523 test_gr_a5a5 7 524 cmp.w #0x0080, @neg 525 beq .Luwdisp32n 526 fail 527 .Luwdisp32n: 528 ;; Note: leave the value as 0x0080, like it started out. 529 530 extu_w_abs16_n: 531 set_grs_a5a5 532 set_ccr_zero 533 ;; extu.w @aa:16 534 extu.w @neg:16 535 536 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 537 test_cc_clear 538 539 test_gr_a5a5 0 ; Make sure other general regs not disturbed 540 test_gr_a5a5 1 541 test_gr_a5a5 2 542 test_gr_a5a5 3 543 test_gr_a5a5 4 544 test_gr_a5a5 5 545 test_gr_a5a5 6 546 test_gr_a5a5 7 547 cmp.w #0x0080, @neg 548 beq .Luwabs16n 549 fail 550 .Luwabs16n: 551 ;; Note: leave the value as 0x0080, like it started out. 552 553 extu_w_abs32_n: 554 set_grs_a5a5 555 set_ccr_zero 556 ;; extu.w @aa:32 557 extu.w @neg:32 558 559 ;; Test ccr H=0 N=0 Z=0 V=0 C=0 560 test_cc_clear 561 562 test_gr_a5a5 0 ; Make sure other general regs not disturbed 563 test_gr_a5a5 1 564 test_gr_a5a5 2 565 test_gr_a5a5 3 566 test_gr_a5a5 4 567 test_gr_a5a5 5 568 test_gr_a5a5 6 569 test_gr_a5a5 7 570 cmp.w #0x0080, @neg 571 beq .Luwabs32n 572 fail 573 .Luwabs32n: 574 ;; Note: leave the value as 0x0080, like it started out. 575 576 .endif 577 578 pass 579 580 exit 0 581
Indexes created Sun Mar 01 05:31:48 UTC 2026