shll.s revision 1.1
1 1.1 christos # Hitachi H8 testcase 'shll' 2 1.1 christos # mach(): h8300s h8sx 3 1.1 christos # as(h8300): --defsym sim_cpu=0 4 1.1 christos # as(h8300h): --defsym sim_cpu=1 5 1.1 christos # as(h8300s): --defsym sim_cpu=2 6 1.1 christos # as(h8sx): --defsym sim_cpu=3 7 1.1 christos # ld(h8300h): -m h8300helf 8 1.1 christos # ld(h8300s): -m h8300self 9 1.1 christos # ld(h8sx): -m h8300sxelf 10 1.1 christos 11 1.1 christos .include "testutils.inc" 12 1.1 christos 13 1.1 christos start 14 1.1 christos 15 1.1 christos .data 16 1.1 christos byte_dest: .byte 0xa5 17 1.1 christos .align 2 18 1.1 christos word_dest: .word 0xa5a5 19 1.1 christos .align 4 20 1.1 christos long_dest: .long 0xa5a5a5a5 21 1.1 christos 22 1.1 christos .text 23 1.1 christos 24 1.1 christos shll_b_reg8_1: 25 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 26 1.1 christos set_ccr_zero 27 1.1 christos 28 1.1 christos shll.b r0l ; shift left logical by one 29 1.1 christos ;;; .word 0x1008 30 1.1 christos 31 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 32 1.1 christos test_zero_clear 33 1.1 christos test_ovf_clear 34 1.1 christos test_neg_clear 35 1.1 christos test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 36 1.1 christos .if (sim_cpu) 37 1.1 christos test_h_gr32 0xa5a5a54a er0 38 1.1 christos .endif 39 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 40 1.1 christos test_gr_a5a5 2 41 1.1 christos test_gr_a5a5 3 42 1.1 christos test_gr_a5a5 4 43 1.1 christos test_gr_a5a5 5 44 1.1 christos test_gr_a5a5 6 45 1.1 christos test_gr_a5a5 7 46 1.1 christos 47 1.1 christos shll_b_reg8_2: 48 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 49 1.1 christos set_ccr_zero 50 1.1 christos 51 1.1 christos shll.b #2, r0l ; shift left logical by two 52 1.1 christos ;;; .word 0x1048 53 1.1 christos 54 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 55 1.1 christos test_zero_clear 56 1.1 christos test_ovf_clear 57 1.1 christos test_neg_set 58 1.1 christos 59 1.1 christos test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 60 1.1 christos .if (sim_cpu) 61 1.1 christos test_h_gr32 0xa5a5a594 er0 62 1.1 christos .endif 63 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 64 1.1 christos test_gr_a5a5 2 65 1.1 christos test_gr_a5a5 3 66 1.1 christos test_gr_a5a5 4 67 1.1 christos test_gr_a5a5 5 68 1.1 christos test_gr_a5a5 6 69 1.1 christos test_gr_a5a5 7 70 1.1 christos 71 1.1 christos .if (sim_cpu == h8sx) 72 1.1 christos shll_b_reg8_4: 73 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 74 1.1 christos set_ccr_zero 75 1.1 christos 76 1.1 christos shll.b #4, r0l ; shift left logical by four 77 1.1 christos ;;; .word 0x10a8 78 1.1 christos 79 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 80 1.1 christos test_zero_clear 81 1.1 christos test_ovf_clear 82 1.1 christos test_neg_clear 83 1.1 christos test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 84 1.1 christos test_h_gr32 0xa5a5a550 er0 85 1.1 christos 86 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 87 1.1 christos test_gr_a5a5 2 88 1.1 christos test_gr_a5a5 3 89 1.1 christos test_gr_a5a5 4 90 1.1 christos test_gr_a5a5 5 91 1.1 christos test_gr_a5a5 6 92 1.1 christos test_gr_a5a5 7 93 1.1 christos 94 1.1 christos shll_b_reg8_reg8: 95 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 96 1.1 christos set_ccr_zero 97 1.1 christos 98 1.1 christos mov #5, r0h 99 1.1 christos shll.b r0h, r0l ; shift left logical by register value 100 1.1 christos 101 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 102 1.1 christos test_zero_clear 103 1.1 christos test_ovf_clear 104 1.1 christos test_neg_set 105 1.1 christos test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000 106 1.1 christos test_h_gr32 0xa5a505a0 er0 107 1.1 christos 108 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 109 1.1 christos test_gr_a5a5 2 110 1.1 christos test_gr_a5a5 3 111 1.1 christos test_gr_a5a5 4 112 1.1 christos test_gr_a5a5 5 113 1.1 christos test_gr_a5a5 6 114 1.1 christos test_gr_a5a5 7 115 1.1 christos .endif 116 1.1 christos 117 1.1 christos .if (sim_cpu) ; Not available in h8300 mode 118 1.1 christos shll_w_reg16_1: 119 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 120 1.1 christos set_ccr_zero 121 1.1 christos 122 1.1 christos shll.w r0 ; shift left logical by one 123 1.1 christos ;;; .word 0x1010 124 1.1 christos 125 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 126 1.1 christos test_zero_clear 127 1.1 christos test_ovf_clear 128 1.1 christos test_neg_clear 129 1.1 christos test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 130 1.1 christos test_h_gr32 0xa5a54b4a er0 131 1.1 christos 132 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 133 1.1 christos test_gr_a5a5 2 134 1.1 christos test_gr_a5a5 3 135 1.1 christos test_gr_a5a5 4 136 1.1 christos test_gr_a5a5 5 137 1.1 christos test_gr_a5a5 6 138 1.1 christos test_gr_a5a5 7 139 1.1 christos 140 1.1 christos shll_w_reg16_2: 141 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 142 1.1 christos set_ccr_zero 143 1.1 christos 144 1.1 christos shll.w #2, r0 ; shift left logical by two 145 1.1 christos ;;; .word 0x1050 146 1.1 christos 147 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 148 1.1 christos test_zero_clear 149 1.1 christos test_ovf_clear 150 1.1 christos test_neg_set 151 1.1 christos test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 152 1.1 christos test_h_gr32 0xa5a59694 er0 153 1.1 christos 154 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 155 1.1 christos test_gr_a5a5 2 156 1.1 christos test_gr_a5a5 3 157 1.1 christos test_gr_a5a5 4 158 1.1 christos test_gr_a5a5 5 159 1.1 christos test_gr_a5a5 6 160 1.1 christos test_gr_a5a5 7 161 1.1 christos 162 1.1 christos .if (sim_cpu == h8sx) 163 1.1 christos shll_w_reg16_4: 164 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 165 1.1 christos set_ccr_zero 166 1.1 christos 167 1.1 christos shll.w #4, r0 ; shift left logical by four 168 1.1 christos ;;; .word 0x1020 169 1.1 christos 170 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 171 1.1 christos test_zero_clear 172 1.1 christos test_ovf_clear 173 1.1 christos test_neg_clear 174 1.1 christos test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 175 1.1 christos test_h_gr32 0xa5a55a50 er0 176 1.1 christos 177 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 178 1.1 christos test_gr_a5a5 2 179 1.1 christos test_gr_a5a5 3 180 1.1 christos test_gr_a5a5 4 181 1.1 christos test_gr_a5a5 5 182 1.1 christos test_gr_a5a5 6 183 1.1 christos test_gr_a5a5 7 184 1.1 christos 185 1.1 christos shll_w_reg16_8: 186 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 187 1.1 christos set_ccr_zero 188 1.1 christos 189 1.1 christos shll.w #8, r0 ; shift left logical by eight 190 1.1 christos ;;; .word 0x1060 191 1.1 christos 192 1.1 christos test_carry_set ; H=0 N=1 Z=0 V=0 C=1 193 1.1 christos test_zero_clear 194 1.1 christos test_ovf_clear 195 1.1 christos test_neg_set 196 1.1 christos test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 197 1.1 christos test_h_gr32 0xa5a5a500 er0 198 1.1 christos 199 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 200 1.1 christos test_gr_a5a5 2 201 1.1 christos test_gr_a5a5 3 202 1.1 christos test_gr_a5a5 4 203 1.1 christos test_gr_a5a5 5 204 1.1 christos test_gr_a5a5 6 205 1.1 christos test_gr_a5a5 7 206 1.1 christos 207 1.1 christos shll_w_reg16_reg8: 208 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 209 1.1 christos set_ccr_zero 210 1.1 christos 211 1.1 christos mov #5, r0h 212 1.1 christos shll.w r0h, r0 ; shift left logical by register value 213 1.1 christos 214 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 215 1.1 christos test_zero_clear 216 1.1 christos test_ovf_clear 217 1.1 christos test_neg_set 218 1.1 christos test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000 219 1.1 christos test_h_gr32 0xa5a5b4a0 er0 220 1.1 christos 221 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 222 1.1 christos test_gr_a5a5 2 223 1.1 christos test_gr_a5a5 3 224 1.1 christos test_gr_a5a5 4 225 1.1 christos test_gr_a5a5 5 226 1.1 christos test_gr_a5a5 6 227 1.1 christos test_gr_a5a5 7 228 1.1 christos .endif 229 1.1 christos 230 1.1 christos shll_l_reg32_1: 231 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 232 1.1 christos set_ccr_zero 233 1.1 christos 234 1.1 christos shll.l er0 ; shift left logical by one 235 1.1 christos ;;; .word 1030 236 1.1 christos 237 1.1 christos test_carry_set ; H=0 N=0 Z=0 V=0 C=1 238 1.1 christos test_zero_clear 239 1.1 christos test_ovf_clear 240 1.1 christos test_neg_clear 241 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 242 1.1 christos ; -> 0100 1011 0100 1011 0100 1011 0100 1010 243 1.1 christos test_h_gr32 0x4b4b4b4a er0 244 1.1 christos 245 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 246 1.1 christos test_gr_a5a5 2 247 1.1 christos test_gr_a5a5 3 248 1.1 christos test_gr_a5a5 4 249 1.1 christos test_gr_a5a5 5 250 1.1 christos test_gr_a5a5 6 251 1.1 christos test_gr_a5a5 7 252 1.1 christos 253 1.1 christos shll_l_reg32_2: 254 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 255 1.1 christos set_ccr_zero 256 1.1 christos 257 1.1 christos shll.l #2, er0 ; shift left logical by two 258 1.1 christos ;;; .word 0x1070 259 1.1 christos 260 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 261 1.1 christos test_zero_clear 262 1.1 christos test_ovf_clear 263 1.1 christos test_neg_set 264 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 265 1.1 christos ; -> 1001 0110 1001 0110 1001 0110 1001 0100 266 1.1 christos test_h_gr32 0x96969694 er0 267 1.1 christos 268 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 269 1.1 christos test_gr_a5a5 2 270 1.1 christos test_gr_a5a5 3 271 1.1 christos test_gr_a5a5 4 272 1.1 christos test_gr_a5a5 5 273 1.1 christos test_gr_a5a5 6 274 1.1 christos test_gr_a5a5 7 275 1.1 christos 276 1.1 christos .if (sim_cpu == h8sx) 277 1.1 christos shll_l_reg32_4: 278 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 279 1.1 christos set_ccr_zero 280 1.1 christos 281 1.1 christos shll.l #4, er0 ; shift left logical by four 282 1.1 christos ;;; .word 0x1038 283 1.1 christos 284 1.1 christos test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 285 1.1 christos test_zero_clear 286 1.1 christos test_ovf_clear 287 1.1 christos test_neg_clear 288 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 289 1.1 christos ; -> 0101 1010 0101 1010 0101 1010 0101 0000 290 1.1 christos test_h_gr32 0x5a5a5a50 er0 291 1.1 christos 292 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 293 1.1 christos test_gr_a5a5 2 294 1.1 christos test_gr_a5a5 3 295 1.1 christos test_gr_a5a5 4 296 1.1 christos test_gr_a5a5 5 297 1.1 christos test_gr_a5a5 6 298 1.1 christos test_gr_a5a5 7 299 1.1 christos 300 1.1 christos shll_l_reg32_8: 301 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 302 1.1 christos set_ccr_zero 303 1.1 christos 304 1.1 christos shll.l #8, er0 ; shift left logical by eight 305 1.1 christos ;;; .word 0x1078 306 1.1 christos 307 1.1 christos test_carry_set ; H=0 N=1 Z=0 V=0 C=1 308 1.1 christos test_zero_clear 309 1.1 christos test_ovf_clear 310 1.1 christos test_neg_set 311 1.1 christos test_h_gr16 0xa500 r0 312 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 313 1.1 christos ; -> 1010 0101 1010 0101 1010 0101 0000 0000 314 1.1 christos test_h_gr32 0xa5a5a500 er0 315 1.1 christos 316 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 317 1.1 christos test_gr_a5a5 2 318 1.1 christos test_gr_a5a5 3 319 1.1 christos test_gr_a5a5 4 320 1.1 christos test_gr_a5a5 5 321 1.1 christos test_gr_a5a5 6 322 1.1 christos test_gr_a5a5 7 323 1.1 christos 324 1.1 christos shll_l_reg32_16: 325 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 326 1.1 christos set_ccr_zero 327 1.1 christos 328 1.1 christos shll.l #16, er0 ; shift left logical by sixteen 329 1.1 christos ;;; .word 0x10f8 330 1.1 christos 331 1.1 christos test_carry_set ; H=0 N=1 Z=0 V=0 C=1 332 1.1 christos test_zero_clear 333 1.1 christos test_ovf_clear 334 1.1 christos test_neg_set 335 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 336 1.1 christos ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 337 1.1 christos test_h_gr32 0xa5a50000 er0 338 1.1 christos 339 1.1 christos test_gr_a5a5 1 ; Make sure other general regs not disturbed 340 1.1 christos test_gr_a5a5 2 341 1.1 christos test_gr_a5a5 3 342 1.1 christos test_gr_a5a5 4 343 1.1 christos test_gr_a5a5 5 344 1.1 christos test_gr_a5a5 6 345 1.1 christos test_gr_a5a5 7 346 1.1 christos 347 1.1 christos shll_l_reg32_reg8: 348 1.1 christos set_grs_a5a5 ; Fill all general regs with a fixed pattern 349 1.1 christos set_ccr_zero 350 1.1 christos 351 1.1 christos mov #5, r1l 352 1.1 christos shll.l r1l, er0 ; shift left logical by register value 353 1.1 christos 354 1.1 christos test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 355 1.1 christos test_zero_clear 356 1.1 christos test_ovf_clear 357 1.1 christos test_neg_set 358 1.1 christos ; 1010 0101 1010 0101 1010 0101 1010 0101 359 1.1 christos ; -> 1011 0100 1011 0100 1011 0100 1010 0000 360 1.1 christos test_h_gr32 0xb4b4b4a0 er0 361 1.1 christos 362 1.1 christos test_h_gr32 0xa5a5a505 er1 363 1.1 christos test_gr_a5a5 2 ; Make sure other general regs not disturbed 364 1.1 christos test_gr_a5a5 3 365 1.1 christos test_gr_a5a5 4 366 1.1 christos test_gr_a5a5 5 367 1.1 christos test_gr_a5a5 6 368 1.1 christos test_gr_a5a5 7 369 1.1 christos .endif 370 1.1 christos .endif 371 1.1 christos 372 1.1 christos pass 373 1.1 christos 374 1.1 christos exit 0 375 1.1 christos 376
Indexes created Thu May 14 00:25:00 UTC 2026