README revision 1.1.1.1
1 1.1 mrg Copyright 1999, 2001, 2002, 2004 Free Software Foundation, Inc. 2 1.1 mrg 3 1.1 mrg This file is part of the GNU MP Library. 4 1.1 mrg 5 1.1 mrg The GNU MP Library is free software; you can redistribute it and/or modify 6 1.1 mrg it under the terms of the GNU Lesser General Public License as published by 7 1.1 mrg the Free Software Foundation; either version 3 of the License, or (at your 8 1.1 mrg option) any later version. 9 1.1 mrg 10 1.1 mrg The GNU MP Library is distributed in the hope that it will be useful, but 11 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 1.1 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public 13 1.1 mrg License for more details. 14 1.1 mrg 15 1.1 mrg You should have received a copy of the GNU Lesser General Public License 16 1.1 mrg along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. 17 1.1 mrg 18 1.1 mrg 19 1.1 mrg 20 1.1 mrg 21 1.1 mrg This directory contains mpn functions for 64-bit PA-RISC 2.0. 22 1.1 mrg 23 1.1 mrg PIPELINE SUMMARY 24 1.1 mrg 25 1.1 mrg The PA8x00 processors have an orthogonal 4-way out-of-order pipeline. Each 26 1.1 mrg cycle two ALU operations and two MEM operations can issue, but just one of the 27 1.1 mrg MEM operations may be a store. The two ALU operations can be almost any 28 1.1 mrg combination of non-memory operations. Unlike every other processor, integer 29 1.1 mrg and fp operations are completely equal here; they both count as just ALU 30 1.1 mrg operations. 31 1.1 mrg 32 1.1 mrg Unfortunately, some operations cause hickups in the pipeline. Combining 33 1.1 mrg carry-consuming operations like ADD,DC with operations that does not set carry 34 1.1 mrg like ADD,L cause long delays. Skip operations also seem to cause hickups. If 35 1.1 mrg several ADD,DC are issued consecutively, or if plain carry-generating ADD feed 36 1.1 mrg ADD,DC, stalling does not occur. We can effectively issue two ADD,DC 37 1.1 mrg operations/cycle. 38 1.1 mrg 39 1.1 mrg Latency scheduling is not as important as making sure to have a mix of ALU and 40 1.1 mrg MEM operations, but for full pipeline utilization, it is still a good idea to 41 1.1 mrg do some amount of latency scheduling. 42 1.1 mrg 43 1.1 mrg Like for all other processors, RAW memory scheduling is critically important. 44 1.1 mrg Since integer multiplication takes place in the floating-point unit, the GMP 45 1.1 mrg code needs to handle this problem frequently. 46 1.1 mrg 47 1.1 mrg STATUS 48 1.1 mrg 49 1.1 mrg * mpn_lshift and mpn_rshift run at 1.5 cycles/limb on PA8000 and at 1.0 50 1.1 mrg cycles/limb on PA8500. With latency scheduling, the numbers could 51 1.1 mrg probably be improved to 1.0 cycles/limb for all PA8x00 chips. 52 1.1 mrg 53 1.1 mrg * mpn_add_n and mpn_sub_n run at 2.0 cycles/limb on PA8000 and at about 54 1.1 mrg 1.6875 cycles/limb on PA8500. With latency scheduling, this could 55 1.1 mrg probably be improved to get close to 1.5 cycles/limb. A problem is the 56 1.1 mrg stalling of carry-inputting instructions after instructions that do not 57 1.1 mrg write to carry. 58 1.1 mrg 59 1.1 mrg * mpn_mul_1, mpn_addmul_1, and mpn_submul_1 run at between 5.625 and 6.375 60 1.1 mrg on PA8500 and later, and about a cycle/limb slower on older chips. The 61 1.1 mrg code uses ADD,DC for adjacent limbs, and relies heavily on reordering. 62 1.1 mrg 63 1.1 mrg 64 1.1 mrg REFERENCES 65 1.1 mrg 66 1.1 mrg Hewlett Packard, "64-Bit Runtime Architecture for PA-RISC 2.0", version 3.3, 67 1.1 mrg October 1997. 68
Indexes created Sun Jun 07 00:24:08 UTC 2026