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README revision 1.1 
      1 Copyright 1999, 2001, 2002, 2004 Free Software Foundation, Inc.
      2 
      3 This file is part of the GNU MP Library.
      4 
      5 The GNU MP Library is free software; you can redistribute it and/or modify
      6 it under the terms of the GNU Lesser General Public License as published by
      7 the Free Software Foundation; either version 3 of the License, or (at your
      8 option) any later version.
      9 
     10 The GNU MP Library is distributed in the hope that it will be useful, but
     11 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     12 or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
     13 License for more details.
     14 
     15 You should have received a copy of the GNU Lesser General Public License
     16 along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.
     17 
     18 
     19 
     20 
     21 This directory contains mpn functions for 64-bit PA-RISC 2.0.
     22 
     23 PIPELINE SUMMARY
     24 
     25 The PA8x00 processors have an orthogonal 4-way out-of-order pipeline.  Each
     26 cycle two ALU operations and two MEM operations can issue, but just one of the
     27 MEM operations may be a store.  The two ALU operations can be almost any
     28 combination of non-memory operations.  Unlike every other processor, integer
     29 and fp operations are completely equal here; they both count as just ALU
     30 operations.
     31 
     32 Unfortunately, some operations cause hickups in the pipeline.  Combining
     33 carry-consuming operations like ADD,DC with operations that does not set carry
     34 like ADD,L cause long delays.  Skip operations also seem to cause hickups.  If
     35 several ADD,DC are issued consecutively, or if plain carry-generating ADD feed
     36 ADD,DC, stalling does not occur.  We can effectively issue two ADD,DC
     37 operations/cycle.
     38 
     39 Latency scheduling is not as important as making sure to have a mix of ALU and
     40 MEM operations, but for full pipeline utilization, it is still a good idea to
     41 do some amount of latency scheduling.
     42 
     43 Like for all other processors, RAW memory scheduling is critically important.
     44 Since integer multiplication takes place in the floating-point unit, the GMP
     45 code needs to handle this problem frequently.
     46 
     47 STATUS
     48 
     49 * mpn_lshift and mpn_rshift run at 1.5 cycles/limb on PA8000 and at 1.0
     50   cycles/limb on PA8500.  With latency scheduling, the numbers could
     51   probably be improved to 1.0 cycles/limb for all PA8x00 chips.
     52 
     53 * mpn_add_n and mpn_sub_n run at 2.0 cycles/limb on PA8000 and at about
     54   1.6875 cycles/limb on PA8500.  With latency scheduling, this could
     55   probably be improved to get close to 1.5 cycles/limb.  A problem is the
     56   stalling of carry-inputting instructions after instructions that do not
     57   write to carry.
     58 
     59 * mpn_mul_1, mpn_addmul_1, and mpn_submul_1 run at between 5.625 and 6.375
     60   on PA8500 and later, and about a cycle/limb slower on older chips.  The
     61   code uses ADD,DC for adjacent limbs, and relies heavily on reordering.
     62 
     63 
     64 REFERENCES
     65 
     66 Hewlett Packard, "64-Bit Runtime Architecture for PA-RISC 2.0", version 3.3,
     67 October 1997.
     68