1 1.1 mrg Copyright 2000, 2001 Free Software Foundation, Inc. 2 1.1 mrg 3 1.1 mrg This file is part of the GNU MP Library. 4 1.1 mrg 5 1.1 mrg The GNU MP Library is free software; you can redistribute it and/or modify 6 1.1.1.3 mrg it under the terms of either: 7 1.1.1.3 mrg 8 1.1.1.3 mrg * the GNU Lesser General Public License as published by the Free 9 1.1.1.3 mrg Software Foundation; either version 3 of the License, or (at your 10 1.1.1.3 mrg option) any later version. 11 1.1.1.3 mrg 12 1.1.1.3 mrg or 13 1.1.1.3 mrg 14 1.1.1.3 mrg * the GNU General Public License as published by the Free Software 15 1.1.1.3 mrg Foundation; either version 2 of the License, or (at your option) any 16 1.1.1.3 mrg later version. 17 1.1.1.3 mrg 18 1.1.1.3 mrg or both in parallel, as here. 19 1.1 mrg 20 1.1 mrg The GNU MP Library is distributed in the hope that it will be useful, but 21 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 22 1.1.1.3 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 23 1.1.1.3 mrg for more details. 24 1.1 mrg 25 1.1.1.3 mrg You should have received copies of the GNU General Public License and the 26 1.1.1.3 mrg GNU Lesser General Public License along with the GNU MP Library. If not, 27 1.1.1.3 mrg see https://www.gnu.org/licenses/. 28 1.1 mrg 29 1.1 mrg 30 1.1 mrg 31 1.1 mrg 32 1.1 mrg 33 1.1 mrg INTEL P6 MPN SUBROUTINES 34 1.1 mrg 35 1.1 mrg 36 1.1 mrg 37 1.1 mrg This directory contains code optimized for Intel P6 class CPUs, meaning 38 1.1 mrg PentiumPro, Pentium II and Pentium III. The mmx and p3mmx subdirectories 39 1.1 mrg have routines using MMX instructions. 40 1.1 mrg 41 1.1 mrg 42 1.1 mrg 43 1.1 mrg STATUS 44 1.1 mrg 45 1.1 mrg Times for the loops, with all code and data in L1 cache, are as follows. 46 1.1 mrg Some of these might be able to be improved. 47 1.1 mrg 48 1.1 mrg cycles/limb 49 1.1 mrg 50 1.1 mrg mpn_add_n/sub_n 3.7 51 1.1 mrg 52 1.1 mrg mpn_copyi 0.75 53 1.1 mrg mpn_copyd 1.75 (or 0.75 if no overlap) 54 1.1 mrg 55 1.1 mrg mpn_divrem_1 39.0 56 1.1 mrg mpn_mod_1 21.5 57 1.1 mrg mpn_divexact_by3 8.5 58 1.1 mrg 59 1.1 mrg mpn_mul_1 5.5 60 1.1 mrg mpn_addmul/submul_1 6.35 61 1.1 mrg 62 1.1 mrg mpn_l/rshift 2.5 63 1.1 mrg 64 1.1 mrg mpn_mul_basecase 8.2 cycles/crossproduct (approx) 65 1.1 mrg mpn_sqr_basecase 4.0 cycles/crossproduct (approx) 66 1.1.1.2 mrg or 7.75 cycles/triangleproduct (approx) 67 1.1 mrg 68 1.1 mrg Pentium II and III have MMX and get the following improvements. 69 1.1 mrg 70 1.1 mrg mpn_divrem_1 25.0 integer part, 17.5 fractional part 71 1.1 mrg 72 1.1 mrg mpn_l/rshift 1.75 73 1.1 mrg 74 1.1 mrg 75 1.1 mrg 76 1.1 mrg 77 1.1 mrg NOTES 78 1.1 mrg 79 1.1 mrg Write-allocate L1 data cache means prefetching of destinations is unnecessary. 80 1.1 mrg 81 1.1 mrg Mispredicted branches have a penalty of between 9 and 15 cycles, and even up 82 1.1 mrg to 26 cycles depending how far speculative execution has gone. The 9 cycle 83 1.1 mrg minimum penalty comes from the issue pipeline being 9 stages. 84 1.1 mrg 85 1.1 mrg A copy with rep movs seems to copy 16 bytes at a time, since speeds for 4, 86 1.1 mrg 5, 6 or 7 limb operations are all the same. The 0.75 cycles/limb would be 3 87 1.1 mrg cycles per 16 byte block. 88 1.1 mrg 89 1.1 mrg 90 1.1 mrg 91 1.1 mrg 92 1.1 mrg CODING 93 1.1 mrg 94 1.1 mrg Instructions in general code have been shown grouped if they can execute 95 1.1 mrg together, which means up to three instructions with no successive 96 1.1 mrg dependencies, and with only the first being a multiple micro-op. 97 1.1 mrg 98 1.1 mrg P6 has out-of-order execution, so the groupings are really only showing 99 1.1 mrg dependent paths where some shuffling might allow some latencies to be 100 1.1 mrg hidden. 101 1.1 mrg 102 1.1 mrg 103 1.1 mrg 104 1.1 mrg 105 1.1 mrg REFERENCES 106 1.1 mrg 107 1.1 mrg "Intel Architecture Optimization Reference Manual", 1999, revision 001 dated 108 1.1 mrg 02/99, order number 245127 (order number 730795-001 is in the document too). 109 1.1 mrg Available on-line: 110 1.1 mrg 111 1.1 mrg http://download.intel.com/design/PentiumII/manuals/245127.htm 112 1.1 mrg 113 1.1 mrg "Intel Architecture Optimization Manual", 1997, order number 242816. This 114 1.1 mrg is an older document mostly about P5 and not as good as the above. 115 1.1 mrg Available on-line: 116 1.1 mrg 117 1.1 mrg http://download.intel.com/design/PentiumII/manuals/242816.htm 118 1.1 mrg 119 1.1 mrg 120 1.1 mrg 121 1.1 mrg ---------------- 122 1.1 mrg Local variables: 123 1.1 mrg mode: text 124 1.1 mrg fill-column: 76 125 1.1 mrg End: 126
Indexes created Mon Aug 17 00:26:26 UTC 2026