1 1.26.2.2 tls # $NetBSD: Makefile.inc,v 1.26.2.2 2014/08/20 00:02:14 tls Exp $ 2 1.26.2.2 tls 3 1.26.2.2 tls COMPILER_RT_SRCDIR= ${NETBSDSRCDIR}/sys/external/bsd/compiler_rt/dist 4 1.26.2.2 tls 5 1.26.2.2 tls .if ${LIBC_MACHINE_ARCH} == "powerpc" 6 1.26.2.2 tls COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 7 1.26.2.2 tls COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 8 1.26.2.2 tls .else 9 1.26.2.2 tls COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_CPU} 10 1.26.2.2 tls COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_ARCH} 11 1.26.2.2 tls .endif 12 1.26.2.2 tls 13 1.26.2.2 tls .PATH: ${COMPILER_RT_CPU_DIR} 14 1.26.2.2 tls .PATH: ${COMPILER_RT_ARCH_DIR} 15 1.26.2.2 tls .PATH: ${COMPILER_RT_SRCDIR}/lib/builtins 16 1.26.2.2 tls .PATH: ${COMPILER_RT_SRCDIR}/lib/profile 17 1.26.2.2 tls 18 1.26.2.2 tls # Complex support needs parts of libm 19 1.26.2.2 tls #GENERIC_SRCS+= 20 1.26.2.2 tls # mulxc3.c \ 21 1.26.2.2 tls # mulsc3.c \ 22 1.26.2.2 tls # divxc3.c \ 23 1.26.2.2 tls # divdc3.c \ 24 1.26.2.2 tls # divsc3.c 25 1.26.2.2 tls 26 1.26.2.2 tls # Implemented on top of our atomic interface. 27 1.26.2.2 tls #GENERIC_SRCS+= atomic.c 28 1.26.2.2 tls 29 1.26.2.2 tls .if ${HAVE_LIBGCC_EH} == "no" 30 1.26.2.2 tls GENERIC_SRCS+= \ 31 1.26.2.2 tls gcc_personality_v0.c 32 1.26.2.2 tls .endif 33 1.26.2.2 tls 34 1.26.2.2 tls .if 0 35 1.26.2.2 tls # Conflicts with soft-float 36 1.26.2.2 tls GENERIC_SRCS+= \ 37 1.26.2.2 tls comparedf2.c \ 38 1.26.2.2 tls comparesf2.c \ 39 1.26.2.2 tls adddf3.c \ 40 1.26.2.2 tls addsf3.c \ 41 1.26.2.2 tls addtf3.c \ 42 1.26.2.2 tls divdf3.c \ 43 1.26.2.2 tls divsf3.c \ 44 1.26.2.2 tls divtf3.c \ 45 1.26.2.2 tls extendsfdf2.c \ 46 1.26.2.2 tls extendsftf2.c \ 47 1.26.2.2 tls extenddftf2.c \ 48 1.26.2.2 tls fixdfsi.c \ 49 1.26.2.2 tls fixdfti.c \ 50 1.26.2.2 tls fixsfsi.c \ 51 1.26.2.2 tls fixsfti.c \ 52 1.26.2.2 tls floatsidf.c \ 53 1.26.2.2 tls floatsisf.c \ 54 1.26.2.2 tls floatunsidf.c \ 55 1.26.2.2 tls floatunsisf.c \ 56 1.26.2.2 tls muldf3.c \ 57 1.26.2.2 tls mulsf3.c \ 58 1.26.2.2 tls multf3.c \ 59 1.26.2.2 tls subdf3.c \ 60 1.26.2.2 tls subsf3.c \ 61 1.26.2.2 tls subtf3.c \ 62 1.26.2.2 tls truncdfsf2.c \ 63 1.26.2.2 tls trunctfdf2.c \ 64 1.26.2.2 tls trunctfsf2.c 65 1.26.2.2 tls .endif 66 1.26.2.2 tls 67 1.26.2.2 tls GENERIC_SRCS+= \ 68 1.26.2.2 tls absvsi2.c \ 69 1.26.2.2 tls absvti2.c \ 70 1.26.2.2 tls addvsi3.c \ 71 1.26.2.2 tls addvti3.c \ 72 1.26.2.2 tls ashlti3.c \ 73 1.26.2.2 tls ashrti3.c \ 74 1.26.2.2 tls clzti2.c \ 75 1.26.2.2 tls cmpti2.c \ 76 1.26.2.2 tls ctzti2.c \ 77 1.26.2.2 tls divti3.c \ 78 1.26.2.2 tls ffsti2.c \ 79 1.26.2.2 tls fixsfdi.c \ 80 1.26.2.2 tls fixdfdi.c \ 81 1.26.2.2 tls fixunsdfdi.c \ 82 1.26.2.2 tls fixunsdfsi.c \ 83 1.26.2.2 tls fixunssfdi.c \ 84 1.26.2.2 tls fixunssfsi.c \ 85 1.26.2.2 tls fixunsxfdi.c \ 86 1.26.2.2 tls fixunsxfsi.c \ 87 1.26.2.2 tls fixxfdi.c \ 88 1.26.2.2 tls floatdidf.c \ 89 1.26.2.2 tls floatdisf.c \ 90 1.26.2.2 tls floatdixf.c \ 91 1.26.2.2 tls floatundidf.c \ 92 1.26.2.2 tls floatundisf.c \ 93 1.26.2.2 tls floatundixf.c \ 94 1.26.2.2 tls int_util.c \ 95 1.26.2.2 tls lshrti3.c \ 96 1.26.2.2 tls modti3.c \ 97 1.26.2.2 tls muldc3.c \ 98 1.26.2.2 tls mulosi4.c \ 99 1.26.2.2 tls muloti4.c \ 100 1.26.2.2 tls multi3.c \ 101 1.26.2.2 tls mulvsi3.c \ 102 1.26.2.2 tls mulvti3.c \ 103 1.26.2.2 tls negdf2.c \ 104 1.26.2.2 tls negsf2.c \ 105 1.26.2.2 tls negti2.c \ 106 1.26.2.2 tls negvsi2.c \ 107 1.26.2.2 tls negvti2.c \ 108 1.26.2.2 tls paritysi2.c \ 109 1.26.2.2 tls parityti2.c \ 110 1.26.2.2 tls popcountsi2.c \ 111 1.26.2.2 tls popcountti2.c \ 112 1.26.2.2 tls powidf2.c \ 113 1.26.2.2 tls powisf2.c \ 114 1.26.2.2 tls powitf2.c \ 115 1.26.2.2 tls powixf2.c \ 116 1.26.2.2 tls subvsi3.c \ 117 1.26.2.2 tls subvti3.c \ 118 1.26.2.2 tls ucmpti2.c \ 119 1.26.2.2 tls udivmodti4.c \ 120 1.26.2.2 tls udivti3.c \ 121 1.26.2.2 tls umodti3.c 122 1.26.2.2 tls 123 1.26.2.2 tls .if ${MACHINE_ARCH} != "aarch64" 124 1.26.2.2 tls GENERIC_SRCS+= \ 125 1.26.2.2 tls fixunsdfti.c \ 126 1.26.2.2 tls fixunssfti.c \ 127 1.26.2.2 tls fixunsxfti.c \ 128 1.26.2.2 tls fixxfti.c \ 129 1.26.2.2 tls floattidf.c \ 130 1.26.2.2 tls floattisf.c \ 131 1.26.2.2 tls floattixf.c \ 132 1.26.2.2 tls floatuntidf.c \ 133 1.26.2.2 tls floatuntisf.c \ 134 1.26.2.2 tls floatuntixf.c 135 1.26.2.2 tls .endif 136 1.26.2.2 tls 137 1.26.2.2 tls # These have h/w instructions which are always used. 138 1.26.2.2 tls .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc" \ 139 1.26.2.2 tls && ${LIBC_MACHINE_CPU} != "aarch64" && ${LIBC_MACHINE_ARCH} != "vax" 140 1.26.2.2 tls GENERIC_SRCS+= \ 141 1.26.2.2 tls clzsi2.c \ 142 1.26.2.2 tls ctzsi2.c \ 143 1.26.2.2 tls divmodsi4.c \ 144 1.26.2.2 tls divsi3.c \ 145 1.26.2.2 tls modsi3.c \ 146 1.26.2.2 tls udivmodsi4.c \ 147 1.26.2.2 tls umodsi3.c 148 1.26.2.2 tls 149 1.26.2.2 tls . if ${LIBC_MACHINE_CPU} != "sh3" 150 1.26.2.2 tls # On sh3 __udivsi3 is gcc "millicode" with special calling convention 151 1.26.2.2 tls # (less registers clobbered than usual). Each DSO that needs it gets 152 1.26.2.2 tls # its own hidden copy from libgcc.a. 153 1.26.2.2 tls GENERIC_SRCS+= \ 154 1.26.2.2 tls udivsi3.c 155 1.26.2.2 tls . endif 156 1.26.2.2 tls .endif 157 1.26.2.2 tls 158 1.26.2.2 tls 159 1.26.2.2 tls GENERIC_SRCS+= \ 160 1.26.2.2 tls absvdi2.c \ 161 1.26.2.2 tls addvdi3.c \ 162 1.26.2.2 tls mulodi4.c \ 163 1.26.2.2 tls mulvdi3.c \ 164 1.26.2.2 tls negvdi2.c \ 165 1.26.2.2 tls paritydi2.c \ 166 1.26.2.2 tls popcountdi2.c \ 167 1.26.2.2 tls subvdi3.c 168 1.26.2.2 tls 169 1.26.2.2 tls # These have h/w instructions which are always used. 170 1.26.2.2 tls .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc64" \ 171 1.26.2.2 tls && ${LIBC_MACHINE_ARCH} != "aarch64" 172 1.26.2.2 tls GENERIC_SRCS+= \ 173 1.26.2.2 tls clzdi2.c \ 174 1.26.2.2 tls ctzdi2.c \ 175 1.26.2.2 tls ffsdi2.c 176 1.26.2.2 tls .endif 177 1.26.2.2 tls 178 1.26.2.2 tls # Don't need these on 64-bit machines. 179 1.26.2.2 tls .if empty(LIBC_MACHINE_ARCH:M*64*) && ${LIBC_MACHINE_ARCH} != "alpha" 180 1.26.2.2 tls GENERIC_SRCS+= \ 181 1.26.2.2 tls cmpdi2.c \ 182 1.26.2.2 tls ashldi3.c \ 183 1.26.2.2 tls ashrdi3.c \ 184 1.26.2.2 tls divdi3.c \ 185 1.26.2.2 tls divmoddi4.c \ 186 1.26.2.2 tls lshrdi3.c \ 187 1.26.2.2 tls moddi3.c \ 188 1.26.2.2 tls muldi3.c \ 189 1.26.2.2 tls negdi2.c \ 190 1.26.2.2 tls ucmpdi2.c \ 191 1.26.2.2 tls udivdi3.c \ 192 1.26.2.2 tls udivmoddi4.c \ 193 1.26.2.2 tls umoddi3.c 194 1.26.2.2 tls .endif 195 1.26.2.2 tls 196 1.26.2.2 tls GENERIC_SRCS+= \ 197 1.26.2.2 tls GCDAProfiling.c \ 198 1.26.2.2 tls InstrProfiling.c \ 199 1.26.2.2 tls InstrProfilingBuffer.c \ 200 1.26.2.2 tls InstrProfilingFile.c \ 201 1.26.2.2 tls InstrProfilingPlatformOther.c 202 1.26.2.2 tls 203 1.26.2.2 tls .if ${LIBC_MACHINE_ARCH} == "powerpc" 204 1.26.2.2 tls GENERIC_SRCS+= \ 205 1.26.2.2 tls fixtfdi.c \ 206 1.26.2.2 tls fixunstfdi.c \ 207 1.26.2.2 tls floatditf.c \ 208 1.26.2.2 tls floatunditf.c \ 209 1.26.2.2 tls gcc_qadd.c \ 210 1.26.2.2 tls gcc_qdiv.c \ 211 1.26.2.2 tls gcc_qmul.c \ 212 1.26.2.2 tls gcc_qsub.c 213 1.26.2.2 tls .endif 214 1.26.2.2 tls 215 1.26.2.2 tls .if ${LIBC_MACHINE_CPU} == "aarch64" 216 1.26.2.2 tls GENERIC_SRCS+= \ 217 1.26.2.2 tls clear_cache.c 218 1.26.2.2 tls .endif 219 1.26.2.2 tls 220 1.26.2.2 tls .if ${LIBC_MACHINE_CPU} == "arm" 221 1.26.2.2 tls .if !empty(LIBC_MACHINE_ARCH:Mearm*) 222 1.26.2.2 tls GENERIC_SRCS+= \ 223 1.26.2.2 tls aeabi_idivmod.S \ 224 1.26.2.2 tls aeabi_ldivmod.S \ 225 1.26.2.2 tls aeabi_uidivmod.S \ 226 1.26.2.2 tls aeabi_uldivmod.S 227 1.26.2.2 tls .endif 228 1.26.2.2 tls GENERIC_SRCS+= \ 229 1.26.2.2 tls clear_cache.c 230 1.26.2.2 tls # Not yet, overlaps with softfloat 231 1.26.2.2 tls # aeabi_dcmp.S \ 232 1.26.2.2 tls # aeabi_fcmp.S 233 1.26.2.2 tls # Not yet, requires ARMv6 234 1.26.2.2 tls #GENERIC_SRCS+= \ 235 1.26.2.2 tls # bswapdi2.S \ 236 1.26.2.2 tls # bswapsi2.S 237 1.26.2.2 tls .endif 238 1.26.2.2 tls 239 1.26.2.2 tls .for src in ${GENERIC_SRCS} 240 1.26.2.2 tls . if exists(${COMPILER_RT_CPU_DIR}/${src:R}.S) || \ 241 1.26.2.2 tls exists(${COMPILER_RT_ARCH_DIR}/${src:R}.S) 242 1.26.2.2 tls SRCS+= ${src:R}.S 243 1.26.2.2 tls . else 244 1.26.2.2 tls SRCS+= ${src} 245 1.26.2.2 tls . if ${src:E} != "cc" 246 1.26.2.2 tls COPTS.${src}+= -Wno-missing-prototypes \ 247 1.26.2.2 tls -Wno-old-style-definition \ 248 1.26.2.2 tls -Wno-strict-prototypes \ 249 1.26.2.2 tls -Wno-uninitialized \ 250 1.26.2.2 tls -Wno-cast-qual 251 1.26.2.2 tls . endif 252 1.26.2.2 tls . endif 253 1.26.2.2 tls .endfor 254