1 # $NetBSD: Makefile.inc,v 1.35.4.1 2020/04/08 14:07:12 martin Exp $ 2 3 COMPILER_RT_SRCDIR= ${NETBSDSRCDIR}/sys/external/bsd/compiler_rt/dist 4 5 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 6 COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 7 COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 8 .else 9 COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_CPU} 10 COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_ARCH} 11 .endif 12 13 .PATH: ${COMPILER_RT_CPU_DIR} 14 .PATH: ${COMPILER_RT_ARCH_DIR} 15 .PATH: ${COMPILER_RT_SRCDIR}/lib/builtins 16 .PATH: ${COMPILER_RT_SRCDIR}/lib/profile 17 18 # Complex support needs parts of libm 19 #GENERIC_SRCS+= 20 # mulxc3.c \ 21 # mulsc3.c \ 22 # divxc3.c \ 23 # divdc3.c \ 24 # divsc3.c 25 26 # Implemented on top of our atomic interface. 27 #GENERIC_SRCS+= atomic.c 28 29 .if ${HAVE_LIBGCC_EH} == "no" 30 GENERIC_SRCS+= \ 31 gcc_personality_v0.c 32 .endif 33 34 GENERIC_SRCS+= \ 35 absvsi2.c \ 36 absvti2.c \ 37 addvsi3.c \ 38 addvti3.c \ 39 ashlti3.c \ 40 ashrti3.c \ 41 clzti2.c \ 42 cmpti2.c \ 43 ctzti2.c \ 44 divti3.c \ 45 ffsti2.c \ 46 fixsfdi.c \ 47 fixdfdi.c \ 48 fixunsdfdi.c \ 49 fixunsdfsi.c \ 50 fixunssfdi.c \ 51 fixunssfsi.c \ 52 fixunsxfdi.c \ 53 fixunsxfsi.c \ 54 int_util.c \ 55 lshrti3.c \ 56 modti3.c \ 57 muldc3.c \ 58 mulosi4.c \ 59 muloti4.c \ 60 multi3.c \ 61 mulvsi3.c \ 62 mulvti3.c \ 63 negti2.c \ 64 negvsi2.c \ 65 negvti2.c \ 66 paritysi2.c \ 67 parityti2.c \ 68 popcountsi2.c \ 69 popcountti2.c \ 70 subvsi3.c \ 71 subvti3.c \ 72 ucmpti2.c \ 73 udivmodti4.c \ 74 udivti3.c \ 75 umodti3.c 76 77 # only used for machines using IEEE 754 floating point formats 78 .if ${MACHINE_ARCH} != "vax" 79 80 .if 0 81 # Conflicts with soft-float 82 GENERIC_SRCS+= \ 83 comparedf2.c \ 84 comparesf2.c \ 85 adddf3.c \ 86 addsf3.c \ 87 addtf3.c \ 88 divdf3.c \ 89 divsf3.c \ 90 divtf3.c \ 91 extendsfdf2.c \ 92 extendsftf2.c \ 93 extenddftf2.c \ 94 fixdfsi.c \ 95 fixdfti.c \ 96 fixsfsi.c \ 97 fixsfti.c \ 98 floatsidf.c \ 99 floatsisf.c \ 100 floatunsidf.c \ 101 floatunsisf.c \ 102 muldf3.c \ 103 mulsf3.c \ 104 multf3.c \ 105 subdf3.c \ 106 subsf3.c \ 107 subtf3.c \ 108 truncdfsf2.c \ 109 trunctfdf2.c \ 110 trunctfsf2.c 111 .endif 112 113 GENERIC_SRCS+= \ 114 floatdidf.c \ 115 floatdisf.c \ 116 floatdixf.c \ 117 floatundidf.c \ 118 floatundisf.c \ 119 floatundixf.c \ 120 negdf2.c \ 121 negsf2.c \ 122 powidf2.c \ 123 powisf2.c \ 124 powitf2.c \ 125 powixf2.c 126 127 .endif # IEEE 754 only machines 128 129 .if ${MACHINE_ARCH} != "m68k" 130 GENERIC_SRCS+= \ 131 fixxfdi.c 132 .endif 133 134 135 .if ${MACHINE_ARCH} != "aarch64" 136 GENERIC_SRCS+= \ 137 fixunsdfti.c \ 138 fixunssfti.c \ 139 fixunsxfti.c \ 140 fixxfti.c \ 141 floattidf.c \ 142 floattisf.c \ 143 floattixf.c \ 144 floatuntidf.c \ 145 floatuntisf.c \ 146 floatuntixf.c 147 .endif 148 149 # These have h/w instructions which are always used. 150 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "aarch64" \ 151 && ${LIBC_MACHINE_CPU} != "powerpc" && ${LIBC_MACHINE_CPU} != "or1k" 152 GENERIC_SRCS+= \ 153 clzsi2.c 154 .endif 155 156 # These have h/w instructions which are always used. 157 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_ARCH} != "vax" \ 158 && ${LIBC_MACHINE_CPU} != "aarch64" && ${LIBC_MACHINE_CPU} != "powerpc" \ 159 && ${LIBC_MACHINE_CPU} != "or1k" 160 GENERIC_SRCS+= \ 161 ctzsi2.c 162 .endif 163 164 # These have h/w instructions which are always used. 165 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc" \ 166 && ${LIBC_MACHINE_CPU} != "aarch64" && ${LIBC_MACHINE_ARCH} != "vax" 167 GENERIC_SRCS+= \ 168 divmodsi4.c \ 169 divsi3.c \ 170 udivmodsi4.c \ 171 172 . if ${LIBC_MACHINE_ARCH} != "m68000" 173 # Our __{,u}modsi3 codes assume that __udivsi3 returns remainder to 174 # %d1 (volatile register). __udivsi3 in libgcc does not, and therefore 175 # mixing them up results in mess. 176 GENERIC_SRCS+= \ 177 modsi3.c \ 178 umodsi3.c 179 . endif 180 181 . if ${LIBC_MACHINE_CPU} != "sh3" 182 # On sh3 __udivsi3 is gcc "millicode" with special calling convention 183 # (less registers clobbered than usual). Each DSO that needs it gets 184 # its own hidden copy from libgcc.a. 185 GENERIC_SRCS+= \ 186 udivsi3.c 187 . endif 188 .endif 189 190 191 GENERIC_SRCS+= \ 192 absvdi2.c \ 193 addvdi3.c \ 194 mulodi4.c \ 195 mulvdi3.c \ 196 negvdi2.c \ 197 paritydi2.c \ 198 popcountdi2.c \ 199 subvdi3.c 200 201 # These have h/w instructions which are always used. 202 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc64" \ 203 && ${LIBC_MACHINE_ARCH} != "aarch64" && ${LIBC_MACHINE_CPU} != "or1k" 204 GENERIC_SRCS+= \ 205 clzdi2.c \ 206 ctzdi2.c \ 207 ffsdi2.c 208 .endif 209 210 # Don't need these on 64-bit machines. 211 .if empty(LIBC_MACHINE_ARCH:M*64*) && ${LIBC_MACHINE_ARCH} != "alpha" 212 GENERIC_SRCS+= \ 213 cmpdi2.c \ 214 ashldi3.c \ 215 ashrdi3.c \ 216 divdi3.c \ 217 divmoddi4.c \ 218 lshrdi3.c \ 219 moddi3.c \ 220 muldi3.c \ 221 negdi2.c \ 222 ucmpdi2.c \ 223 udivdi3.c \ 224 udivmoddi4.c \ 225 umoddi3.c 226 .endif 227 228 GENERIC_SRCS+= \ 229 GCDAProfiling.c \ 230 InstrProfiling.c \ 231 InstrProfilingBuffer.c \ 232 InstrProfilingFile.c \ 233 InstrProfilingPlatformLinux.c \ 234 InstrProfilingUtil.c \ 235 InstrProfilingValue.c \ 236 InstrProfilingWriter.c 237 238 .if ${MKPROFILE} != "no" 239 POBJS+= InstrProfilingRuntime.po 240 .endif 241 242 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 243 GENERIC_SRCS+= \ 244 fixtfdi.c \ 245 fixunstfdi.c \ 246 floatditf.c \ 247 floatunditf.c \ 248 gcc_qadd.c \ 249 gcc_qdiv.c \ 250 gcc_qmul.c \ 251 gcc_qsub.c 252 .endif 253 254 .if ${LIBC_MACHINE_CPU} == "aarch64" 255 GENERIC_SRCS+= \ 256 clear_cache.c 257 .endif 258 259 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 260 GENERIC_SRCS+= \ 261 clear_cache.c 262 .endif 263 264 .if ${LIBC_MACHINE_ARCH} == "sparc" || ${LIBC_MACHINE_ARCH} == "sparc64" 265 GENERIC_SRCS+= \ 266 clear_cache.c 267 .endif 268 269 .if ${LIBC_MACHINE_CPU} == "arm" 270 .if !empty(LIBC_MACHINE_ARCH:Mearm*) 271 GENERIC_SRCS+= \ 272 aeabi_idivmod.S \ 273 aeabi_ldivmod.S \ 274 aeabi_uidivmod.S \ 275 aeabi_uldivmod.S 276 .endif 277 GENERIC_SRCS+= \ 278 clear_cache.c 279 # Not yet, overlaps with softfloat 280 # aeabi_dcmp.S \ 281 # aeabi_fcmp.S 282 # Not yet, requires ARMv6 283 #GENERIC_SRCS+= \ 284 # bswapdi2.S \ 285 # bswapsi2.S 286 .endif 287 288 .for src in ${GENERIC_SRCS} 289 . if exists(${COMPILER_RT_CPU_DIR}/${src:R}.S) || \ 290 exists(${COMPILER_RT_ARCH_DIR}/${src:R}.S) 291 SRCS+= ${src:R}.S 292 . else 293 SRCS+= ${src} 294 . if ${src:E} != "cc" 295 COPTS.${src}+= -Wno-missing-prototypes \ 296 -Wno-old-style-definition \ 297 -Wno-strict-prototypes \ 298 -Wno-uninitialized \ 299 -Wno-cast-qual 300 . endif 301 . endif 302 .if ${MKSOFTFLOAT:Uno} != "no" 303 COPTS.${src}+= -D__SOFT_FP__ 304 .endif 305 .endfor 306