Makefile.inc revision 1.35.4.2
1 # $NetBSD: Makefile.inc,v 1.35.4.2 2020/04/13 08:03:09 martin Exp $ 2 3 COMPILER_RT_SRCDIR= ${NETBSDSRCDIR}/sys/external/bsd/compiler_rt/dist 4 5 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 6 COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 7 COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/ppc 8 .else 9 COMPILER_RT_CPU_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_CPU} 10 COMPILER_RT_ARCH_DIR= ${COMPILER_RT_SRCDIR}/lib/builtins/${LIBC_MACHINE_ARCH} 11 .endif 12 13 .PATH: ${COMPILER_RT_CPU_DIR} 14 .PATH: ${COMPILER_RT_ARCH_DIR} 15 .PATH: ${COMPILER_RT_SRCDIR}/lib/builtins 16 .PATH: ${COMPILER_RT_SRCDIR}/lib/profile 17 18 # Complex support needs parts of libm 19 #GENERIC_SRCS+= 20 # mulxc3.c \ 21 # mulsc3.c \ 22 # divxc3.c \ 23 # divdc3.c \ 24 # divsc3.c 25 26 # Implemented on top of our atomic interface. 27 #GENERIC_SRCS+= atomic.c 28 29 .if ${HAVE_LIBGCC_EH} == "no" 30 GENERIC_SRCS+= \ 31 gcc_personality_v0.c 32 .endif 33 34 GENERIC_SRCS+= \ 35 absvsi2.c \ 36 absvti2.c \ 37 addvsi3.c \ 38 addvti3.c \ 39 ashlti3.c \ 40 ashrti3.c \ 41 clzti2.c \ 42 cmpti2.c \ 43 ctzti2.c \ 44 divti3.c \ 45 ffsti2.c \ 46 fixsfdi.c \ 47 fixdfdi.c \ 48 fixunsdfdi.c \ 49 fixunsdfsi.c \ 50 fixunssfdi.c \ 51 fixunssfsi.c \ 52 fixunsxfdi.c \ 53 fixunsxfsi.c \ 54 int_util.c \ 55 lshrti3.c \ 56 modti3.c \ 57 muldc3.c \ 58 mulosi4.c \ 59 muloti4.c \ 60 multi3.c \ 61 mulvsi3.c \ 62 mulvti3.c \ 63 negti2.c \ 64 negvsi2.c \ 65 negvti2.c \ 66 paritysi2.c \ 67 parityti2.c \ 68 popcountsi2.c \ 69 popcountti2.c \ 70 subvsi3.c \ 71 subvti3.c \ 72 ucmpti2.c \ 73 udivmodti4.c \ 74 udivti3.c \ 75 umodti3.c 76 77 # only used for machines using IEEE 754 floating point formats 78 .if ${MACHINE_ARCH} != "vax" 79 80 .if 0 81 # Conflicts with soft-float 82 GENERIC_SRCS+= \ 83 comparedf2.c \ 84 comparesf2.c \ 85 adddf3.c \ 86 addsf3.c \ 87 addtf3.c \ 88 divdf3.c \ 89 divsf3.c \ 90 divtf3.c \ 91 extendsfdf2.c \ 92 extendsftf2.c \ 93 extenddftf2.c \ 94 fixdfsi.c \ 95 fixdfti.c \ 96 fixsfsi.c \ 97 fixsfti.c \ 98 floatsidf.c \ 99 floatsisf.c \ 100 floatunsidf.c \ 101 floatunsisf.c \ 102 muldf3.c \ 103 mulsf3.c \ 104 multf3.c \ 105 subdf3.c \ 106 subsf3.c \ 107 subtf3.c \ 108 truncdfsf2.c \ 109 trunctfdf2.c \ 110 trunctfsf2.c 111 .endif 112 113 GENERIC_SRCS+= \ 114 floatdidf.c \ 115 floatdisf.c \ 116 floatdixf.c \ 117 floatundidf.c \ 118 floatundisf.c \ 119 floatundixf.c \ 120 negdf2.c \ 121 negsf2.c \ 122 powidf2.c \ 123 powisf2.c \ 124 powitf2.c \ 125 powixf2.c 126 127 .endif # IEEE 754 only machines 128 129 .if ${MACHINE_ARCH} != "m68k" 130 GENERIC_SRCS+= \ 131 fixxfdi.c 132 .endif 133 134 135 .if ${MACHINE_ARCH} != "aarch64" 136 GENERIC_SRCS+= \ 137 fixunsdfti.c \ 138 fixunssfti.c \ 139 fixunsxfti.c \ 140 fixxfti.c \ 141 floattidf.c \ 142 floattisf.c \ 143 floattixf.c \ 144 floatuntidf.c \ 145 floatuntisf.c \ 146 floatuntixf.c 147 .else 148 GENERIC_SRCS+= \ 149 comparetf2.c 150 .endif 151 152 # These have h/w instructions which are always used. 153 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "aarch64" \ 154 && ${LIBC_MACHINE_CPU} != "powerpc" && ${LIBC_MACHINE_CPU} != "or1k" 155 GENERIC_SRCS+= \ 156 clzsi2.c 157 .endif 158 159 # These have h/w instructions which are always used. 160 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_ARCH} != "vax" \ 161 && ${LIBC_MACHINE_CPU} != "aarch64" && ${LIBC_MACHINE_CPU} != "powerpc" \ 162 && ${LIBC_MACHINE_CPU} != "or1k" 163 GENERIC_SRCS+= \ 164 ctzsi2.c 165 .endif 166 167 # These have h/w instructions which are always used. 168 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc" \ 169 && ${LIBC_MACHINE_CPU} != "aarch64" && ${LIBC_MACHINE_ARCH} != "vax" 170 GENERIC_SRCS+= \ 171 divmodsi4.c \ 172 divsi3.c \ 173 udivmodsi4.c \ 174 175 . if ${LIBC_MACHINE_ARCH} != "m68000" 176 # Our __{,u}modsi3 codes assume that __udivsi3 returns remainder to 177 # %d1 (volatile register). __udivsi3 in libgcc does not, and therefore 178 # mixing them up results in mess. 179 GENERIC_SRCS+= \ 180 modsi3.c \ 181 umodsi3.c 182 . endif 183 184 . if ${LIBC_MACHINE_CPU} != "sh3" 185 # On sh3 __udivsi3 is gcc "millicode" with special calling convention 186 # (less registers clobbered than usual). Each DSO that needs it gets 187 # its own hidden copy from libgcc.a. 188 GENERIC_SRCS+= \ 189 udivsi3.c 190 . endif 191 .endif 192 193 194 GENERIC_SRCS+= \ 195 absvdi2.c \ 196 addvdi3.c \ 197 mulodi4.c \ 198 mulvdi3.c \ 199 negvdi2.c \ 200 paritydi2.c \ 201 popcountdi2.c \ 202 subvdi3.c 203 204 # These have h/w instructions which are always used. 205 .if ${LIBC_MACHINE_ARCH} != "alpha" && ${LIBC_MACHINE_CPU} != "powerpc64" \ 206 && ${LIBC_MACHINE_ARCH} != "aarch64" && ${LIBC_MACHINE_CPU} != "or1k" 207 GENERIC_SRCS+= \ 208 clzdi2.c \ 209 ctzdi2.c \ 210 ffsdi2.c 211 .endif 212 213 # Don't need these on 64-bit machines. 214 .if empty(LIBC_MACHINE_ARCH:M*64*) && ${LIBC_MACHINE_ARCH} != "alpha" 215 GENERIC_SRCS+= \ 216 cmpdi2.c \ 217 ashldi3.c \ 218 ashrdi3.c \ 219 divdi3.c \ 220 divmoddi4.c \ 221 lshrdi3.c \ 222 moddi3.c \ 223 muldi3.c \ 224 negdi2.c \ 225 ucmpdi2.c \ 226 udivdi3.c \ 227 udivmoddi4.c \ 228 umoddi3.c 229 .endif 230 231 GENERIC_SRCS+= \ 232 GCDAProfiling.c \ 233 InstrProfiling.c \ 234 InstrProfilingBuffer.c \ 235 InstrProfilingFile.c \ 236 InstrProfilingPlatformLinux.c \ 237 InstrProfilingUtil.c \ 238 InstrProfilingValue.c \ 239 InstrProfilingWriter.c 240 241 .if ${MKPROFILE} != "no" 242 POBJS+= InstrProfilingRuntime.po 243 .endif 244 245 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 246 GENERIC_SRCS+= \ 247 fixtfdi.c \ 248 fixunstfdi.c \ 249 floatditf.c \ 250 floatunditf.c \ 251 gcc_qadd.c \ 252 gcc_qdiv.c \ 253 gcc_qmul.c \ 254 gcc_qsub.c 255 .endif 256 257 .if ${LIBC_MACHINE_CPU} == "aarch64" 258 GENERIC_SRCS+= \ 259 clear_cache.c 260 .endif 261 262 .if ${LIBC_MACHINE_ARCH} == "powerpc" || ${LIBC_MACHINE_ARCH} == "powerpc64" 263 GENERIC_SRCS+= \ 264 clear_cache.c 265 .endif 266 267 .if ${LIBC_MACHINE_ARCH} == "sparc" || ${LIBC_MACHINE_ARCH} == "sparc64" 268 GENERIC_SRCS+= \ 269 clear_cache.c 270 .endif 271 272 .if ${LIBC_MACHINE_CPU} == "arm" 273 .if !empty(LIBC_MACHINE_ARCH:Mearm*) 274 GENERIC_SRCS+= \ 275 aeabi_idivmod.S \ 276 aeabi_ldivmod.S \ 277 aeabi_uidivmod.S \ 278 aeabi_uldivmod.S 279 .endif 280 GENERIC_SRCS+= \ 281 clear_cache.c 282 # Not yet, overlaps with softfloat 283 # aeabi_dcmp.S \ 284 # aeabi_fcmp.S 285 # Not yet, requires ARMv6 286 #GENERIC_SRCS+= \ 287 # bswapdi2.S \ 288 # bswapsi2.S 289 .endif 290 291 .for src in ${GENERIC_SRCS} 292 . if exists(${COMPILER_RT_CPU_DIR}/${src:R}.S) || \ 293 exists(${COMPILER_RT_ARCH_DIR}/${src:R}.S) 294 SRCS+= ${src:R}.S 295 . else 296 SRCS+= ${src} 297 . if ${src:E} != "cc" 298 COPTS.${src}+= -Wno-missing-prototypes \ 299 -Wno-old-style-definition \ 300 -Wno-strict-prototypes \ 301 -Wno-uninitialized \ 302 -Wno-cast-qual 303 . endif 304 . endif 305 .if ${MKSOFTFLOAT:Uno} != "no" 306 COPTS.${src}+= -D__SOFT_FP__ 307 .endif 308 .endfor 309
Indexes created Thu Nov 06 07:09:58 GMT 2025